pcie-kirin.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * PCIe host controller driver for Kirin Phone SoCs
  4 *
  5 * Copyright (C) 2017 HiSilicon Electronics Co., Ltd.
  6 *		https://www.huawei.com
  7 *
  8 * Author: Xiaowei Song <songxiaowei@huawei.com>
  9 */
 10
 11#include <linux/clk.h>
 12#include <linux/compiler.h>
 13#include <linux/delay.h>
 14#include <linux/err.h>
 15#include <linux/gpio/consumer.h>
 16#include <linux/interrupt.h>
 17#include <linux/mfd/syscon.h>
 18#include <linux/of.h>
 19#include <linux/of_pci.h>
 20#include <linux/phy/phy.h>
 21#include <linux/pci.h>
 22#include <linux/pci_regs.h>
 23#include <linux/platform_device.h>
 24#include <linux/regmap.h>
 25#include <linux/resource.h>
 26#include <linux/types.h>
 27#include "pcie-designware.h"
 28
 29#define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
 30
 31/* PCIe ELBI registers */
 32#define SOC_PCIECTRL_CTRL0_ADDR		0x000
 33#define SOC_PCIECTRL_CTRL1_ADDR		0x004
 34#define PCIE_ELBI_SLV_DBI_ENABLE	(0x1 << 21)
 35
 36/* info located in APB */
 37#define PCIE_APP_LTSSM_ENABLE	0x01c
 38#define PCIE_APB_PHY_STATUS0	0x400
 39#define PCIE_LINKUP_ENABLE	(0x8020)
 40#define PCIE_LTSSM_ENABLE_BIT	(0x1 << 11)
 41
 42/* info located in sysctrl */
 43#define SCTRL_PCIE_CMOS_OFFSET	0x60
 44#define SCTRL_PCIE_CMOS_BIT	0x10
 45#define SCTRL_PCIE_ISO_OFFSET	0x44
 46#define SCTRL_PCIE_ISO_BIT	0x30
 47#define SCTRL_PCIE_HPCLK_OFFSET	0x190
 48#define SCTRL_PCIE_HPCLK_BIT	0x184000
 49#define SCTRL_PCIE_OE_OFFSET	0x14a
 50#define PCIE_DEBOUNCE_PARAM	0xF0F400
 51#define PCIE_OE_BYPASS		(0x3 << 28)
 52
 53/*
 54 * Max number of connected PCI slots at an external PCI bridge
 55 *
 56 * This is used on HiKey 970, which has a PEX 8606 bridge with 4 connected
 57 * lanes (lane 0 upstream, and the other three lanes, one connected to an
 58 * in-board Ethernet adapter and the other two connected to M.2 and mini
 59 * PCI slots.
 60 *
 61 * Each slot has a different clock source and uses a separate PERST# pin.
 62 */
 63#define MAX_PCI_SLOTS		3
 64
 65enum pcie_kirin_phy_type {
 66	PCIE_KIRIN_INTERNAL_PHY,
 67	PCIE_KIRIN_EXTERNAL_PHY
 68};
 69
 70struct kirin_pcie {
 71	enum pcie_kirin_phy_type	type;
 72
 73	struct dw_pcie	*pci;
 74	struct regmap   *apb;
 75	struct phy	*phy;
 76	void		*phy_priv;	/* only for PCIE_KIRIN_INTERNAL_PHY */
 77
 78	/* DWC PERST# */
 79	struct gpio_desc *id_dwc_perst_gpio;
 80
 81	/* Per-slot PERST# */
 82	int		num_slots;
 83	struct gpio_desc *id_reset_gpio[MAX_PCI_SLOTS];
 84	const char	*reset_names[MAX_PCI_SLOTS];
 85
 86	/* Per-slot clkreq */
 87	int		n_gpio_clkreq;
 88	struct gpio_desc *id_clkreq_gpio[MAX_PCI_SLOTS];
 89	const char	*clkreq_names[MAX_PCI_SLOTS];
 90};
 91
 92/*
 93 * Kirin 960 PHY. Can't be split into a PHY driver without changing the
 94 * DT schema.
 95 */
 96
 97#define REF_CLK_FREQ			100000000
 98
 99/* PHY info located in APB */
100#define PCIE_APB_PHY_CTRL0	0x0
101#define PCIE_APB_PHY_CTRL1	0x4
102#define PCIE_APB_PHY_STATUS0   0x400
103#define PIPE_CLK_STABLE		BIT(19)
104#define PHY_REF_PAD_BIT		BIT(8)
105#define PHY_PWR_DOWN_BIT	BIT(22)
106#define PHY_RST_ACK_BIT		BIT(16)
107
108/* peri_crg ctrl */
109#define CRGCTRL_PCIE_ASSERT_OFFSET	0x88
110#define CRGCTRL_PCIE_ASSERT_BIT		0x8c000000
111
112/* Time for delay */
113#define REF_2_PERST_MIN		21000
114#define REF_2_PERST_MAX		25000
115#define PERST_2_ACCESS_MIN	10000
116#define PERST_2_ACCESS_MAX	12000
117#define PIPE_CLK_WAIT_MIN	550
118#define PIPE_CLK_WAIT_MAX	600
119#define TIME_CMOS_MIN		100
120#define TIME_CMOS_MAX		105
121#define TIME_PHY_PD_MIN		10
122#define TIME_PHY_PD_MAX		11
123
124struct hi3660_pcie_phy {
125	struct device	*dev;
126	void __iomem	*base;
127	struct regmap	*crgctrl;
128	struct regmap	*sysctrl;
129	struct clk	*apb_sys_clk;
130	struct clk	*apb_phy_clk;
131	struct clk	*phy_ref_clk;
132	struct clk	*aclk;
133	struct clk	*aux_clk;
134};
135
136/* Registers in PCIePHY */
137static inline void kirin_apb_phy_writel(struct hi3660_pcie_phy *hi3660_pcie_phy,
138					u32 val, u32 reg)
139{
140	writel(val, hi3660_pcie_phy->base + reg);
141}
142
143static inline u32 kirin_apb_phy_readl(struct hi3660_pcie_phy *hi3660_pcie_phy,
144				      u32 reg)
145{
146	return readl(hi3660_pcie_phy->base + reg);
147}
148
149static int hi3660_pcie_phy_get_clk(struct hi3660_pcie_phy *phy)
150{
151	struct device *dev = phy->dev;
152
153	phy->phy_ref_clk = devm_clk_get(dev, "pcie_phy_ref");
154	if (IS_ERR(phy->phy_ref_clk))
155		return PTR_ERR(phy->phy_ref_clk);
156
157	phy->aux_clk = devm_clk_get(dev, "pcie_aux");
158	if (IS_ERR(phy->aux_clk))
159		return PTR_ERR(phy->aux_clk);
160
161	phy->apb_phy_clk = devm_clk_get(dev, "pcie_apb_phy");
162	if (IS_ERR(phy->apb_phy_clk))
163		return PTR_ERR(phy->apb_phy_clk);
164
165	phy->apb_sys_clk = devm_clk_get(dev, "pcie_apb_sys");
166	if (IS_ERR(phy->apb_sys_clk))
167		return PTR_ERR(phy->apb_sys_clk);
168
169	phy->aclk = devm_clk_get(dev, "pcie_aclk");
170	if (IS_ERR(phy->aclk))
171		return PTR_ERR(phy->aclk);
172
173	return 0;
174}
175
176static int hi3660_pcie_phy_get_resource(struct hi3660_pcie_phy *phy)
177{
178	struct device *dev = phy->dev;
179	struct platform_device *pdev;
180
181	/* registers */
182	pdev = container_of(dev, struct platform_device, dev);
183
184	phy->base = devm_platform_ioremap_resource_byname(pdev, "phy");
185	if (IS_ERR(phy->base))
186		return PTR_ERR(phy->base);
187
188	phy->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl");
189	if (IS_ERR(phy->crgctrl))
190		return PTR_ERR(phy->crgctrl);
191
192	phy->sysctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl");
193	if (IS_ERR(phy->sysctrl))
194		return PTR_ERR(phy->sysctrl);
195
196	return 0;
197}
198
199static int hi3660_pcie_phy_start(struct hi3660_pcie_phy *phy)
200{
201	struct device *dev = phy->dev;
202	u32 reg_val;
203
204	reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL1);
205	reg_val &= ~PHY_REF_PAD_BIT;
206	kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL1);
207
208	reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL0);
209	reg_val &= ~PHY_PWR_DOWN_BIT;
210	kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL0);
211	usleep_range(TIME_PHY_PD_MIN, TIME_PHY_PD_MAX);
212
213	reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL1);
214	reg_val &= ~PHY_RST_ACK_BIT;
215	kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL1);
216
217	usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX);
218	reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_STATUS0);
219	if (reg_val & PIPE_CLK_STABLE)
220		return dev_err_probe(dev, -ETIMEDOUT,
221				     "PIPE clk is not stable\n");
222
223	return 0;
224}
225
226static void hi3660_pcie_phy_oe_enable(struct hi3660_pcie_phy *phy)
227{
228	u32 val;
229
230	regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
231	val |= PCIE_DEBOUNCE_PARAM;
232	val &= ~PCIE_OE_BYPASS;
233	regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
234}
235
236static int hi3660_pcie_phy_clk_ctrl(struct hi3660_pcie_phy *phy, bool enable)
237{
238	int ret = 0;
239
240	if (!enable)
241		goto close_clk;
242
243	ret = clk_set_rate(phy->phy_ref_clk, REF_CLK_FREQ);
244	if (ret)
245		return ret;
246
247	ret = clk_prepare_enable(phy->phy_ref_clk);
248	if (ret)
249		return ret;
250
251	ret = clk_prepare_enable(phy->apb_sys_clk);
252	if (ret)
253		goto apb_sys_fail;
254
255	ret = clk_prepare_enable(phy->apb_phy_clk);
256	if (ret)
257		goto apb_phy_fail;
258
259	ret = clk_prepare_enable(phy->aclk);
260	if (ret)
261		goto aclk_fail;
262
263	ret = clk_prepare_enable(phy->aux_clk);
264	if (ret)
265		goto aux_clk_fail;
266
267	return 0;
268
269close_clk:
270	clk_disable_unprepare(phy->aux_clk);
271aux_clk_fail:
272	clk_disable_unprepare(phy->aclk);
273aclk_fail:
274	clk_disable_unprepare(phy->apb_phy_clk);
275apb_phy_fail:
276	clk_disable_unprepare(phy->apb_sys_clk);
277apb_sys_fail:
278	clk_disable_unprepare(phy->phy_ref_clk);
279
280	return ret;
281}
282
283static int hi3660_pcie_phy_power_on(struct kirin_pcie *pcie)
284{
285	struct hi3660_pcie_phy *phy = pcie->phy_priv;
286	int ret;
287
288	/* Power supply for Host */
289	regmap_write(phy->sysctrl,
290		     SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
291	usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX);
292
293	hi3660_pcie_phy_oe_enable(phy);
294
295	ret = hi3660_pcie_phy_clk_ctrl(phy, true);
296	if (ret)
297		return ret;
298
299	/* ISO disable, PCIeCtrl, PHY assert and clk gate clear */
300	regmap_write(phy->sysctrl,
301		     SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
302	regmap_write(phy->crgctrl,
303		     CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT);
304	regmap_write(phy->sysctrl,
305		     SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT);
306
307	ret = hi3660_pcie_phy_start(phy);
308	if (ret)
309		goto disable_clks;
310
311	return 0;
312
313disable_clks:
314	hi3660_pcie_phy_clk_ctrl(phy, false);
315	return ret;
316}
317
318static int hi3660_pcie_phy_init(struct platform_device *pdev,
319				struct kirin_pcie *pcie)
320{
321	struct device *dev = &pdev->dev;
322	struct hi3660_pcie_phy *phy;
323	int ret;
324
325	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
326	if (!phy)
327		return -ENOMEM;
328
329	pcie->phy_priv = phy;
330	phy->dev = dev;
331
332	ret = hi3660_pcie_phy_get_clk(phy);
333	if (ret)
334		return ret;
335
336	return hi3660_pcie_phy_get_resource(phy);
337}
338
339static int hi3660_pcie_phy_power_off(struct kirin_pcie *pcie)
340{
341	struct hi3660_pcie_phy *phy = pcie->phy_priv;
342
343	/* Drop power supply for Host */
344	regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, 0x00);
345
346	hi3660_pcie_phy_clk_ctrl(phy, false);
347
348	return 0;
349}
350
351/*
352 * The non-PHY part starts here
353 */
354
355static const struct regmap_config pcie_kirin_regmap_conf = {
356	.name = "kirin_pcie_apb",
357	.reg_bits = 32,
358	.val_bits = 32,
359	.reg_stride = 4,
360};
361
362static int kirin_pcie_get_gpio_enable(struct kirin_pcie *pcie,
363				      struct platform_device *pdev)
364{
365	struct device *dev = &pdev->dev;
366	int ret, i;
367
368	/* This is an optional property */
369	ret = gpiod_count(dev, "hisilicon,clken");
370	if (ret < 0)
371		return 0;
372
373	if (ret > MAX_PCI_SLOTS)
374		return dev_err_probe(dev, -EINVAL,
375				     "Too many GPIO clock requests!\n");
376
377	pcie->n_gpio_clkreq = ret;
378
379	for (i = 0; i < pcie->n_gpio_clkreq; i++) {
380		pcie->id_clkreq_gpio[i] = devm_gpiod_get_index(dev,
381							"hisilicon,clken", i,
382							GPIOD_OUT_LOW);
383		if (IS_ERR(pcie->id_clkreq_gpio[i]))
384			return dev_err_probe(dev, PTR_ERR(pcie->id_clkreq_gpio[i]),
385					     "unable to get a valid clken gpio\n");
386
387		pcie->clkreq_names[i] = devm_kasprintf(dev, GFP_KERNEL,
388						       "pcie_clkreq_%d", i);
389		if (!pcie->clkreq_names[i])
390			return -ENOMEM;
391
392		gpiod_set_consumer_name(pcie->id_clkreq_gpio[i],
393					pcie->clkreq_names[i]);
394	}
395
396	return 0;
397}
398
399static int kirin_pcie_parse_port(struct kirin_pcie *pcie,
400				 struct platform_device *pdev,
401				 struct device_node *node)
402{
403	struct device *dev = &pdev->dev;
404	int ret, slot, i;
405
406	for_each_available_child_of_node_scoped(node, parent) {
407		for_each_available_child_of_node_scoped(parent, child) {
408			i = pcie->num_slots;
409
410			pcie->id_reset_gpio[i] = devm_fwnode_gpiod_get_index(dev,
411							 of_fwnode_handle(child),
412							 "reset", 0, GPIOD_OUT_LOW,
413							 NULL);
414			if (IS_ERR(pcie->id_reset_gpio[i])) {
415				if (PTR_ERR(pcie->id_reset_gpio[i]) == -ENOENT)
416					continue;
417				return dev_err_probe(dev, PTR_ERR(pcie->id_reset_gpio[i]),
418						     "unable to get a valid reset gpio\n");
419			}
420
421			if (pcie->num_slots + 1 >= MAX_PCI_SLOTS)
422				return dev_err_probe(dev, -EINVAL,
423						     "Too many PCI slots!\n");
424
425			pcie->num_slots++;
426
427			ret = of_pci_get_devfn(child);
428			if (ret < 0)
429				return dev_err_probe(dev, ret,
430						     "failed to parse devfn\n");
431
432			slot = PCI_SLOT(ret);
433
434			pcie->reset_names[i] = devm_kasprintf(dev, GFP_KERNEL,
435							      "pcie_perst_%d",
436							      slot);
437			if (!pcie->reset_names[i])
438				return -ENOMEM;
439
440			gpiod_set_consumer_name(pcie->id_reset_gpio[i],
441						pcie->reset_names[i]);
442		}
443	}
444
445	return 0;
446}
447
448static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
449				    struct platform_device *pdev)
450{
451	struct device *dev = &pdev->dev;
452	struct device_node *node = dev->of_node;
453	void __iomem *apb_base;
454	int ret;
455
456	apb_base = devm_platform_ioremap_resource_byname(pdev, "apb");
457	if (IS_ERR(apb_base))
458		return PTR_ERR(apb_base);
459
460	kirin_pcie->apb = devm_regmap_init_mmio(dev, apb_base,
461						&pcie_kirin_regmap_conf);
462	if (IS_ERR(kirin_pcie->apb))
463		return PTR_ERR(kirin_pcie->apb);
464
465	/* pcie internal PERST# gpio */
466	kirin_pcie->id_dwc_perst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
467	if (IS_ERR(kirin_pcie->id_dwc_perst_gpio))
468		return dev_err_probe(dev, PTR_ERR(kirin_pcie->id_dwc_perst_gpio),
469				     "unable to get a valid gpio pin\n");
470	gpiod_set_consumer_name(kirin_pcie->id_dwc_perst_gpio, "pcie_perst_bridge");
471
472	ret = kirin_pcie_get_gpio_enable(kirin_pcie, pdev);
473	if (ret)
474		return ret;
475
476	/* Parse OF children */
477	for_each_available_child_of_node_scoped(node, child) {
478		ret = kirin_pcie_parse_port(kirin_pcie, pdev, child);
479		if (ret)
480			return ret;
481	}
482
483	return 0;
484}
485
486static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie,
487					   bool on)
488{
489	u32 val;
490
491	regmap_read(kirin_pcie->apb, SOC_PCIECTRL_CTRL0_ADDR, &val);
492	if (on)
493		val = val | PCIE_ELBI_SLV_DBI_ENABLE;
494	else
495		val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
496
497	regmap_write(kirin_pcie->apb, SOC_PCIECTRL_CTRL0_ADDR, val);
498}
499
500static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie,
501					   bool on)
502{
503	u32 val;
504
505	regmap_read(kirin_pcie->apb, SOC_PCIECTRL_CTRL1_ADDR, &val);
506	if (on)
507		val = val | PCIE_ELBI_SLV_DBI_ENABLE;
508	else
509		val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
510
511	regmap_write(kirin_pcie->apb, SOC_PCIECTRL_CTRL1_ADDR, val);
512}
513
514static int kirin_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn,
515				  int where, int size, u32 *val)
516{
517	struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
518
519	if (PCI_SLOT(devfn))
520		return PCIBIOS_DEVICE_NOT_FOUND;
521
522	*val = dw_pcie_read_dbi(pci, where, size);
523	return PCIBIOS_SUCCESSFUL;
524}
525
526static int kirin_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn,
527				  int where, int size, u32 val)
528{
529	struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
530
531	if (PCI_SLOT(devfn))
532		return PCIBIOS_DEVICE_NOT_FOUND;
533
534	dw_pcie_write_dbi(pci, where, size, val);
535	return PCIBIOS_SUCCESSFUL;
536}
537
538static int kirin_pcie_add_bus(struct pci_bus *bus)
539{
540	struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
541	struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
542	int i, ret;
543
544	if (!kirin_pcie->num_slots)
545		return 0;
546
547	/* Send PERST# to each slot */
548	for (i = 0; i < kirin_pcie->num_slots; i++) {
549		ret = gpiod_direction_output_raw(kirin_pcie->id_reset_gpio[i], 1);
550		if (ret) {
551			dev_err(pci->dev, "PERST# %s error: %d\n",
552				kirin_pcie->reset_names[i], ret);
553		}
554	}
555	usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
556
557	return 0;
558}
559
560static struct pci_ops kirin_pci_ops = {
561	.read = kirin_pcie_rd_own_conf,
562	.write = kirin_pcie_wr_own_conf,
563	.add_bus = kirin_pcie_add_bus,
564};
565
566static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
567			       u32 reg, size_t size)
568{
569	struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
570	u32 ret;
571
572	kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
573	dw_pcie_read(base + reg, size, &ret);
574	kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
575
576	return ret;
577}
578
579static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
580				 u32 reg, size_t size, u32 val)
581{
582	struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
583
584	kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
585	dw_pcie_write(base + reg, size, val);
586	kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
587}
588
589static bool kirin_pcie_link_up(struct dw_pcie *pci)
590{
591	struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
592	u32 val;
593
594	regmap_read(kirin_pcie->apb, PCIE_APB_PHY_STATUS0, &val);
595	return (val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE;
596}
597
598static int kirin_pcie_start_link(struct dw_pcie *pci)
599{
600	struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
601
602	/* assert LTSSM enable */
603	regmap_write(kirin_pcie->apb, PCIE_APP_LTSSM_ENABLE,
604		     PCIE_LTSSM_ENABLE_BIT);
605
606	return 0;
607}
608
609static int kirin_pcie_host_init(struct dw_pcie_rp *pp)
610{
611	pp->bridge->ops = &kirin_pci_ops;
612
613	return 0;
614}
615
616static const struct dw_pcie_ops kirin_dw_pcie_ops = {
617	.read_dbi = kirin_pcie_read_dbi,
618	.write_dbi = kirin_pcie_write_dbi,
619	.link_up = kirin_pcie_link_up,
620	.start_link = kirin_pcie_start_link,
621};
622
623static const struct dw_pcie_host_ops kirin_pcie_host_ops = {
624	.init = kirin_pcie_host_init,
625};
626
627static int kirin_pcie_power_off(struct kirin_pcie *kirin_pcie)
628{
629	int i;
630
631	if (kirin_pcie->type == PCIE_KIRIN_INTERNAL_PHY)
632		return hi3660_pcie_phy_power_off(kirin_pcie);
633
634	for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++)
635		gpiod_direction_output_raw(kirin_pcie->id_clkreq_gpio[i], 1);
636
637	phy_power_off(kirin_pcie->phy);
638	phy_exit(kirin_pcie->phy);
639
640	return 0;
641}
642
643static int kirin_pcie_power_on(struct platform_device *pdev,
644			       struct kirin_pcie *kirin_pcie)
645{
646	struct device *dev = &pdev->dev;
647	int ret;
648
649	if (kirin_pcie->type == PCIE_KIRIN_INTERNAL_PHY) {
650		ret = hi3660_pcie_phy_init(pdev, kirin_pcie);
651		if (ret)
652			return ret;
653
654		ret = hi3660_pcie_phy_power_on(kirin_pcie);
655		if (ret)
656			return ret;
657	} else {
658		kirin_pcie->phy = devm_of_phy_get(dev, dev->of_node, NULL);
659		if (IS_ERR(kirin_pcie->phy))
660			return PTR_ERR(kirin_pcie->phy);
661
662		ret = phy_init(kirin_pcie->phy);
663		if (ret)
664			goto err;
665
666		ret = phy_power_on(kirin_pcie->phy);
667		if (ret)
668			goto err;
669	}
670
671	/* perst assert Endpoint */
672	usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
673
674	ret = gpiod_direction_output_raw(kirin_pcie->id_dwc_perst_gpio, 1);
675	if (ret)
676		goto err;
677
678	usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
679
680	return 0;
681err:
682	kirin_pcie_power_off(kirin_pcie);
683
684	return ret;
685}
686
687static void kirin_pcie_remove(struct platform_device *pdev)
688{
689	struct kirin_pcie *kirin_pcie = platform_get_drvdata(pdev);
690
691	dw_pcie_host_deinit(&kirin_pcie->pci->pp);
692
693	kirin_pcie_power_off(kirin_pcie);
694}
695
696struct kirin_pcie_data {
697	enum pcie_kirin_phy_type	phy_type;
698};
699
700static const struct kirin_pcie_data kirin_960_data = {
701	.phy_type = PCIE_KIRIN_INTERNAL_PHY,
702};
703
704static const struct kirin_pcie_data kirin_970_data = {
705	.phy_type = PCIE_KIRIN_EXTERNAL_PHY,
706};
707
708static const struct of_device_id kirin_pcie_match[] = {
709	{ .compatible = "hisilicon,kirin960-pcie", .data = &kirin_960_data },
710	{ .compatible = "hisilicon,kirin970-pcie", .data = &kirin_970_data },
711	{},
712};
713
714static int kirin_pcie_probe(struct platform_device *pdev)
715{
716	struct device *dev = &pdev->dev;
717	const struct kirin_pcie_data *data;
718	struct kirin_pcie *kirin_pcie;
719	struct dw_pcie *pci;
720	int ret;
721
722	data = of_device_get_match_data(dev);
723	if (!data)
724		return dev_err_probe(dev, -EINVAL, "OF data missing\n");
725
726	kirin_pcie = devm_kzalloc(dev, sizeof(struct kirin_pcie), GFP_KERNEL);
727	if (!kirin_pcie)
728		return -ENOMEM;
729
730	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
731	if (!pci)
732		return -ENOMEM;
733
734	pci->dev = dev;
735	pci->ops = &kirin_dw_pcie_ops;
736	pci->pp.ops = &kirin_pcie_host_ops;
737	kirin_pcie->pci = pci;
738	kirin_pcie->type = data->phy_type;
739
740	ret = kirin_pcie_get_resource(kirin_pcie, pdev);
741	if (ret)
742		return ret;
743
744	platform_set_drvdata(pdev, kirin_pcie);
745
746	ret = kirin_pcie_power_on(pdev, kirin_pcie);
747	if (ret)
748		return ret;
749
750	return dw_pcie_host_init(&pci->pp);
751}
752
753static struct platform_driver kirin_pcie_driver = {
754	.probe			= kirin_pcie_probe,
755	.remove			= kirin_pcie_remove,
756	.driver			= {
757		.name			= "kirin-pcie",
758		.of_match_table		= kirin_pcie_match,
759		.suppress_bind_attrs	= true,
760	},
761};
762module_platform_driver(kirin_pcie_driver);
763
764MODULE_DEVICE_TABLE(of, kirin_pcie_match);
765MODULE_DESCRIPTION("PCIe host controller driver for Kirin Phone SoCs");
766MODULE_AUTHOR("Xiaowei Song <songxiaowei@huawei.com>");
767MODULE_LICENSE("GPL v2");