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pcie-designware.c
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linux-6.19.14/drivers/pci/controller/dwc/pcie-designware.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Synopsys DesignWare PCIe host controller driver 4 * 5 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * 8 * Author: Jingoo Han <jg1.han@samsung.com> 9 */ 10 11#include <linux/align.h> 12#include <linux/bitops.h> 13#include <linux/clk.h> 14#include <linux/delay.h> 15#include <linux/dma/edma.h> 16#include <linux/gpio/consumer.h> 17#include <linux/ioport.h> 18#include <linux/of.h> 19#include <linux/of_address.h> 20#include <linux/pcie-dwc.h> 21#include <linux/platform_device.h> 22#include <linux/sizes.h> 23#include <linux/types.h> 24 25#include "../../pci.h" 26#include "pcie-designware.h" 27 28static const char * const dw_pcie_app_clks[DW_PCIE_NUM_APP_CLKS] = { 29 [DW_PCIE_DBI_CLK] = "dbi", 30 [DW_PCIE_MSTR_CLK] = "mstr", 31 [DW_PCIE_SLV_CLK] = "slv", 32}; 33 34static const char * const dw_pcie_core_clks[DW_PCIE_NUM_CORE_CLKS] = { 35 [DW_PCIE_PIPE_CLK] = "pipe", 36 [DW_PCIE_CORE_CLK] = "core", 37 [DW_PCIE_AUX_CLK] = "aux", 38 [DW_PCIE_REF_CLK] = "ref", 39}; 40 41static const char * const dw_pcie_app_rsts[DW_PCIE_NUM_APP_RSTS] = { 42 [DW_PCIE_DBI_RST] = "dbi", 43 [DW_PCIE_MSTR_RST] = "mstr", 44 [DW_PCIE_SLV_RST] = "slv", 45}; 46 47static const char * const dw_pcie_core_rsts[DW_PCIE_NUM_CORE_RSTS] = { 48 [DW_PCIE_NON_STICKY_RST] = "non-sticky", 49 [DW_PCIE_STICKY_RST] = "sticky", 50 [DW_PCIE_CORE_RST] = "core", 51 [DW_PCIE_PIPE_RST] = "pipe", 52 [DW_PCIE_PHY_RST] = "phy", 53 [DW_PCIE_HOT_RST] = "hot", 54 [DW_PCIE_PWR_RST] = "pwr", 55}; 56 57static const struct dwc_pcie_vsec_id dwc_pcie_ptm_vsec_ids[] = { 58 { .vendor_id = PCI_VENDOR_ID_QCOM, /* EP */ 59 .vsec_id = 0x03, .vsec_rev = 0x1 }, 60 { .vendor_id = PCI_VENDOR_ID_QCOM, /* RC */ 61 .vsec_id = 0x04, .vsec_rev = 0x1 }, 62 { } 63}; 64 65static int dw_pcie_get_clocks(struct dw_pcie *pci) 66{ 67 int i, ret; 68 69 for (i = 0; i < DW_PCIE_NUM_APP_CLKS; i++) 70 pci->app_clks[i].id = dw_pcie_app_clks[i]; 71 72 for (i = 0; i < DW_PCIE_NUM_CORE_CLKS; i++) 73 pci->core_clks[i].id = dw_pcie_core_clks[i]; 74 75 ret = devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_APP_CLKS, 76 pci->app_clks); 77 if (ret) 78 return ret; 79 80 return devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_CORE_CLKS, 81 pci->core_clks); 82} 83 84static int dw_pcie_get_resets(struct dw_pcie *pci) 85{ 86 int i, ret; 87 88 for (i = 0; i < DW_PCIE_NUM_APP_RSTS; i++) 89 pci->app_rsts[i].id = dw_pcie_app_rsts[i]; 90 91 for (i = 0; i < DW_PCIE_NUM_CORE_RSTS; i++) 92 pci->core_rsts[i].id = dw_pcie_core_rsts[i]; 93 94 ret = devm_reset_control_bulk_get_optional_shared(pci->dev, 95 DW_PCIE_NUM_APP_RSTS, 96 pci->app_rsts); 97 if (ret) 98 return ret; 99 100 ret = devm_reset_control_bulk_get_optional_exclusive(pci->dev, 101 DW_PCIE_NUM_CORE_RSTS, 102 pci->core_rsts); 103 if (ret) 104 return ret; 105 106 pci->pe_rst = devm_gpiod_get_optional(pci->dev, "reset", GPIOD_OUT_HIGH); 107 if (IS_ERR(pci->pe_rst)) 108 return PTR_ERR(pci->pe_rst); 109 110 return 0; 111} 112 113int dw_pcie_get_resources(struct dw_pcie *pci) 114{ 115 struct platform_device *pdev = to_platform_device(pci->dev); 116 struct device_node *np = dev_of_node(pci->dev); 117 struct resource *res; 118 int ret; 119 120 if (!pci->dbi_base) { 121 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 122 pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res); 123 if (IS_ERR(pci->dbi_base)) 124 return PTR_ERR(pci->dbi_base); 125 pci->dbi_phys_addr = res->start; 126 } 127 128 /* DBI2 is mainly useful for the endpoint controller */ 129 if (!pci->dbi_base2) { 130 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2"); 131 if (res) { 132 pci->dbi_base2 = devm_pci_remap_cfg_resource(pci->dev, res); 133 if (IS_ERR(pci->dbi_base2)) 134 return PTR_ERR(pci->dbi_base2); 135 } else { 136 pci->dbi_base2 = pci->dbi_base + SZ_4K; 137 } 138 } 139 140 /* For non-unrolled iATU/eDMA platforms this range will be ignored */ 141 if (!pci->atu_base) { 142 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); 143 if (res) { 144 pci->atu_size = resource_size(res); 145 pci->atu_base = devm_ioremap_resource(pci->dev, res); 146 if (IS_ERR(pci->atu_base)) 147 return PTR_ERR(pci->atu_base); 148 pci->atu_phys_addr = res->start; 149 } else { 150 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; 151 } 152 } 153 154 /* Set a default value suitable for at most 8 in and 8 out windows */ 155 if (!pci->atu_size) 156 pci->atu_size = SZ_4K; 157 158 /* eDMA region can be mapped to a custom base address */ 159 if (!pci->edma.reg_base) { 160 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); 161 if (res) { 162 pci->edma.reg_base = devm_ioremap_resource(pci->dev, res); 163 if (IS_ERR(pci->edma.reg_base)) 164 return PTR_ERR(pci->edma.reg_base); 165 } else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) { 166 pci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET; 167 } 168 } 169 170 /* ELBI is an optional resource */ 171 if (!pci->elbi_base) { 172 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); 173 if (res) { 174 pci->elbi_base = devm_ioremap_resource(pci->dev, res); 175 if (IS_ERR(pci->elbi_base)) 176 return PTR_ERR(pci->elbi_base); 177 } 178 } 179 180 /* LLDD is supposed to manually switch the clocks and resets state */ 181 if (dw_pcie_cap_is(pci, REQ_RES)) { 182 ret = dw_pcie_get_clocks(pci); 183 if (ret) 184 return ret; 185 186 ret = dw_pcie_get_resets(pci); 187 if (ret) 188 return ret; 189 } 190 191 if (pci->max_link_speed < 1) 192 pci->max_link_speed = of_pci_get_max_link_speed(np); 193 194 of_property_read_u32(np, "num-lanes", &pci->num_lanes); 195 196 if (of_property_read_bool(np, "snps,enable-cdm-check")) 197 dw_pcie_cap_set(pci, CDM_CHECK); 198 199 return 0; 200} 201 202void dw_pcie_version_detect(struct dw_pcie *pci) 203{ 204 u32 ver; 205 206 /* The content of the CSR is zero on DWC PCIe older than v4.70a */ 207 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_NUMBER); 208 if (!ver) 209 return; 210 211 if (pci->version && pci->version != ver) 212 dev_warn(pci->dev, "Versions don't match (%08x != %08x)\n", 213 pci->version, ver); 214 else 215 pci->version = ver; 216 217 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_TYPE); 218 219 if (pci->type && pci->type != ver) 220 dev_warn(pci->dev, "Types don't match (%08x != %08x)\n", 221 pci->type, ver); 222 else 223 pci->type = ver; 224} 225 226u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) 227{ 228 return PCI_FIND_NEXT_CAP(dw_pcie_read_cfg, PCI_CAPABILITY_LIST, cap, 229 NULL, pci); 230} 231EXPORT_SYMBOL_GPL(dw_pcie_find_capability); 232 233u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) 234{ 235 return PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, 0, cap, NULL, pci); 236} 237EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); 238 239void dw_pcie_remove_capability(struct dw_pcie *pci, u8 cap) 240{ 241 u8 cap_pos, pre_pos, next_pos; 242 u16 reg; 243 244 cap_pos = PCI_FIND_NEXT_CAP(dw_pcie_read_cfg, PCI_CAPABILITY_LIST, cap, 245 &pre_pos, pci); 246 if (!cap_pos) 247 return; 248 249 reg = dw_pcie_readw_dbi(pci, cap_pos); 250 next_pos = (reg & 0xff00) >> 8; 251 252 dw_pcie_dbi_ro_wr_en(pci); 253 if (pre_pos == PCI_CAPABILITY_LIST) 254 dw_pcie_writeb_dbi(pci, PCI_CAPABILITY_LIST, next_pos); 255 else 256 dw_pcie_writeb_dbi(pci, pre_pos + 1, next_pos); 257 dw_pcie_dbi_ro_wr_dis(pci); 258} 259EXPORT_SYMBOL_GPL(dw_pcie_remove_capability); 260 261void dw_pcie_remove_ext_capability(struct dw_pcie *pci, u8 cap) 262{ 263 int cap_pos, next_pos, pre_pos; 264 u32 pre_header, header; 265 266 cap_pos = PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, 0, cap, &pre_pos, pci); 267 if (!cap_pos) 268 return; 269 270 header = dw_pcie_readl_dbi(pci, cap_pos); 271 /* 272 * If the first cap at offset PCI_CFG_SPACE_SIZE is removed, 273 * only set it's capid to zero as it cannot be skipped. 274 */ 275 if (cap_pos == PCI_CFG_SPACE_SIZE) { 276 dw_pcie_dbi_ro_wr_en(pci); 277 dw_pcie_writel_dbi(pci, cap_pos, header & 0xffff0000); 278 dw_pcie_dbi_ro_wr_dis(pci); 279 return; 280 } 281 282 pre_header = dw_pcie_readl_dbi(pci, pre_pos); 283 next_pos = PCI_EXT_CAP_NEXT(header); 284 285 dw_pcie_dbi_ro_wr_en(pci); 286 dw_pcie_writel_dbi(pci, pre_pos, 287 (pre_header & 0xfffff) | (next_pos << 20)); 288 dw_pcie_dbi_ro_wr_dis(pci); 289} 290EXPORT_SYMBOL_GPL(dw_pcie_remove_ext_capability); 291 292static u16 __dw_pcie_find_vsec_capability(struct dw_pcie *pci, u16 vendor_id, 293 u16 vsec_id) 294{ 295 u16 vsec = 0; 296 u32 header; 297 298 if (vendor_id != dw_pcie_readw_dbi(pci, PCI_VENDOR_ID)) 299 return 0; 300 301 while ((vsec = PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, vsec, 302 PCI_EXT_CAP_ID_VNDR, NULL, pci))) { 303 header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); 304 if (PCI_VNDR_HEADER_ID(header) == vsec_id) 305 return vsec; 306 } 307 308 return 0; 309} 310 311static u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, 312 const struct dwc_pcie_vsec_id *vsec_ids) 313{ 314 const struct dwc_pcie_vsec_id *vid; 315 u16 vsec; 316 u32 header; 317 318 for (vid = vsec_ids; vid->vendor_id; vid++) { 319 vsec = __dw_pcie_find_vsec_capability(pci, vid->vendor_id, 320 vid->vsec_id); 321 if (vsec) { 322 header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); 323 if (PCI_VNDR_HEADER_REV(header) == vid->vsec_rev) 324 return vsec; 325 } 326 } 327 328 return 0; 329} 330 331u16 dw_pcie_find_rasdes_capability(struct dw_pcie *pci) 332{ 333 return dw_pcie_find_vsec_capability(pci, dwc_pcie_rasdes_vsec_ids); 334} 335EXPORT_SYMBOL_GPL(dw_pcie_find_rasdes_capability); 336 337u16 dw_pcie_find_ptm_capability(struct dw_pcie *pci) 338{ 339 return dw_pcie_find_vsec_capability(pci, dwc_pcie_ptm_vsec_ids); 340} 341EXPORT_SYMBOL_GPL(dw_pcie_find_ptm_capability); 342 343int dw_pcie_read(void __iomem *addr, int size, u32 *val) 344{ 345 if (!IS_ALIGNED((uintptr_t)addr, size)) { 346 *val = 0; 347 return PCIBIOS_BAD_REGISTER_NUMBER; 348 } 349 350 if (size == 4) { 351 *val = readl(addr); 352 } else if (size == 2) { 353 *val = readw(addr); 354 } else if (size == 1) { 355 *val = readb(addr); 356 } else { 357 *val = 0; 358 return PCIBIOS_BAD_REGISTER_NUMBER; 359 } 360 361 return PCIBIOS_SUCCESSFUL; 362} 363EXPORT_SYMBOL_GPL(dw_pcie_read); 364 365int dw_pcie_write(void __iomem *addr, int size, u32 val) 366{ 367 if (!IS_ALIGNED((uintptr_t)addr, size)) 368 return PCIBIOS_BAD_REGISTER_NUMBER; 369 370 if (size == 4) 371 writel(val, addr); 372 else if (size == 2) 373 writew(val, addr); 374 else if (size == 1) 375 writeb(val, addr); 376 else 377 return PCIBIOS_BAD_REGISTER_NUMBER; 378 379 return PCIBIOS_SUCCESSFUL; 380} 381EXPORT_SYMBOL_GPL(dw_pcie_write); 382 383u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size) 384{ 385 int ret; 386 u32 val; 387 388 if (pci->ops && pci->ops->read_dbi) 389 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); 390 391 ret = dw_pcie_read(pci->dbi_base + reg, size, &val); 392 if (ret) 393 dev_err(pci->dev, "Read DBI address failed\n"); 394 395 return val; 396} 397EXPORT_SYMBOL_GPL(dw_pcie_read_dbi); 398 399void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val) 400{ 401 int ret; 402 403 if (pci->ops && pci->ops->write_dbi) { 404 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); 405 return; 406 } 407 408 ret = dw_pcie_write(pci->dbi_base + reg, size, val); 409 if (ret) 410 dev_err(pci->dev, "Write DBI address failed\n"); 411} 412EXPORT_SYMBOL_GPL(dw_pcie_write_dbi); 413 414void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val) 415{ 416 int ret; 417 418 if (pci->ops && pci->ops->write_dbi2) { 419 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); 420 return; 421 } 422 423 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); 424 if (ret) 425 dev_err(pci->dev, "write DBI address failed\n"); 426} 427EXPORT_SYMBOL_GPL(dw_pcie_write_dbi2); 428 429static inline void __iomem *dw_pcie_select_atu(struct dw_pcie *pci, u32 dir, 430 u32 index) 431{ 432 if (dw_pcie_cap_is(pci, IATU_UNROLL)) 433 return pci->atu_base + PCIE_ATU_UNROLL_BASE(dir, index); 434 435 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, dir | index); 436 return pci->atu_base; 437} 438 439static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 dir, u32 index, u32 reg) 440{ 441 void __iomem *base; 442 int ret; 443 u32 val; 444 445 base = dw_pcie_select_atu(pci, dir, index); 446 447 if (pci->ops && pci->ops->read_dbi) 448 return pci->ops->read_dbi(pci, base, reg, 4); 449 450 ret = dw_pcie_read(base + reg, 4, &val); 451 if (ret) 452 dev_err(pci->dev, "Read ATU address failed\n"); 453 454 return val; 455} 456 457static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 dir, u32 index, 458 u32 reg, u32 val) 459{ 460 void __iomem *base; 461 int ret; 462 463 base = dw_pcie_select_atu(pci, dir, index); 464 465 if (pci->ops && pci->ops->write_dbi) { 466 pci->ops->write_dbi(pci, base, reg, 4, val); 467 return; 468 } 469 470 ret = dw_pcie_write(base + reg, 4, val); 471 if (ret) 472 dev_err(pci->dev, "Write ATU address failed\n"); 473} 474 475static inline u32 dw_pcie_readl_atu_ob(struct dw_pcie *pci, u32 index, u32 reg) 476{ 477 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg); 478} 479 480static inline void dw_pcie_writel_atu_ob(struct dw_pcie *pci, u32 index, u32 reg, 481 u32 val) 482{ 483 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg, val); 484} 485 486static inline u32 dw_pcie_enable_ecrc(u32 val) 487{ 488 /* 489 * DesignWare core version 4.90A has a design issue where the 'TD' 490 * bit in the Control register-1 of the ATU outbound region acts 491 * like an override for the ECRC setting, i.e., the presence of TLP 492 * Digest (ECRC) in the outgoing TLPs is solely determined by this 493 * bit. This is contrary to the PCIe spec which says that the 494 * enablement of the ECRC is solely determined by the AER 495 * registers. 496 * 497 * Because of this, even when the ECRC is enabled through AER 498 * registers, the transactions going through ATU won't have TLP 499 * Digest as there is no way the PCI core AER code could program 500 * the TD bit which is specific to the DesignWare core. 501 * 502 * The best way to handle this scenario is to program the TD bit 503 * always. It affects only the traffic from root port to downstream 504 * devices. 505 * 506 * At this point, 507 * When ECRC is enabled in AER registers, everything works normally 508 * When ECRC is NOT enabled in AER registers, then, 509 * on Root Port:- TLP Digest (DWord size) gets appended to each packet 510 * even through it is not required. Since downstream 511 * TLPs are mostly for configuration accesses and BAR 512 * accesses, they are not in critical path and won't 513 * have much negative effect on the performance. 514 * on End Point:- TLP Digest is received for some/all the packets coming 515 * from the root port. TLP Digest is ignored because, 516 * as per the PCIe Spec r5.0 v1.0 section 2.2.3 517 * "TLP Digest Rules", when an endpoint receives TLP 518 * Digest when its ECRC check functionality is disabled 519 * in AER registers, received TLP Digest is just ignored. 520 * Since there is no issue or error reported either side, best way to 521 * handle the scenario is to program TD bit by default. 522 */ 523 524 return val | PCIE_ATU_TD; 525} 526 527int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, 528 const struct dw_pcie_ob_atu_cfg *atu) 529{ 530 u64 parent_bus_addr = atu->parent_bus_addr; 531 u32 retries, val; 532 u64 limit_addr; 533 534 limit_addr = parent_bus_addr + atu->size - 1; 535 536 if ((limit_addr & ~pci->region_limit) != (parent_bus_addr & ~pci->region_limit) || 537 !IS_ALIGNED(parent_bus_addr, pci->region_align) || 538 !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) { 539 return -EINVAL; 540 } 541 542 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE, 543 lower_32_bits(parent_bus_addr)); 544 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE, 545 upper_32_bits(parent_bus_addr)); 546 547 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT, 548 lower_32_bits(limit_addr)); 549 if (dw_pcie_ver_is_ge(pci, 460A)) 550 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT, 551 upper_32_bits(limit_addr)); 552 553 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET, 554 lower_32_bits(atu->pci_addr)); 555 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET, 556 upper_32_bits(atu->pci_addr)); 557 558 val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no); 559 if (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) && 560 dw_pcie_ver_is_ge(pci, 460A)) 561 val |= PCIE_ATU_INCREASE_REGION_SIZE; 562 if (dw_pcie_ver_is(pci, 490A)) 563 val = dw_pcie_enable_ecrc(val); 564 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); 565 566 val = PCIE_ATU_ENABLE | atu->ctrl2; 567 if (atu->type == PCIE_ATU_TYPE_MSG) { 568 /* The data-less messages only for now */ 569 val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code; 570 } 571 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val); 572 573 /* 574 * Make sure ATU enable takes effect before any subsequent config 575 * and I/O accesses. 576 */ 577 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 578 val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2); 579 if (val & PCIE_ATU_ENABLE) 580 return 0; 581 582 mdelay(LINK_WAIT_IATU); 583 } 584 585 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); 586 587 return -ETIMEDOUT; 588} 589 590static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg) 591{ 592 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg); 593} 594 595static inline void dw_pcie_writel_atu_ib(struct dw_pcie *pci, u32 index, u32 reg, 596 u32 val) 597{ 598 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg, val); 599} 600 601int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, 602 u64 parent_bus_addr, u64 pci_addr, u64 size) 603{ 604 u64 limit_addr = pci_addr + size - 1; 605 u32 retries, val; 606 607 if ((limit_addr & ~pci->region_limit) != (pci_addr & ~pci->region_limit) || 608 !IS_ALIGNED(parent_bus_addr, pci->region_align) || 609 !IS_ALIGNED(pci_addr, pci->region_align) || !size) { 610 return -EINVAL; 611 } 612 613 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_BASE, 614 lower_32_bits(pci_addr)); 615 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_BASE, 616 upper_32_bits(pci_addr)); 617 618 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LIMIT, 619 lower_32_bits(limit_addr)); 620 if (dw_pcie_ver_is_ge(pci, 460A)) 621 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_LIMIT, 622 upper_32_bits(limit_addr)); 623 624 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET, 625 lower_32_bits(parent_bus_addr)); 626 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET, 627 upper_32_bits(parent_bus_addr)); 628 629 val = type; 630 if (upper_32_bits(limit_addr) > upper_32_bits(pci_addr) && 631 dw_pcie_ver_is_ge(pci, 460A)) 632 val |= PCIE_ATU_INCREASE_REGION_SIZE; 633 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, val); 634 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); 635 636 /* 637 * Make sure ATU enable takes effect before any subsequent config 638 * and I/O accesses. 639 */ 640 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 641 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2); 642 if (val & PCIE_ATU_ENABLE) 643 return 0; 644 645 mdelay(LINK_WAIT_IATU); 646 } 647 648 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); 649 650 return -ETIMEDOUT; 651} 652 653int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, 654 int type, u64 parent_bus_addr, u8 bar, size_t size) 655{ 656 u32 retries, val; 657 658 if (!IS_ALIGNED(parent_bus_addr, pci->region_align) || 659 !IS_ALIGNED(parent_bus_addr, size)) 660 return -EINVAL; 661 662 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET, 663 lower_32_bits(parent_bus_addr)); 664 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET, 665 upper_32_bits(parent_bus_addr)); 666 667 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, type | 668 PCIE_ATU_FUNC_NUM(func_no)); 669 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2, 670 PCIE_ATU_ENABLE | PCIE_ATU_FUNC_NUM_MATCH_EN | 671 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8)); 672 673 /* 674 * Make sure ATU enable takes effect before any subsequent config 675 * and I/O accesses. 676 */ 677 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 678 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2); 679 if (val & PCIE_ATU_ENABLE) 680 return 0; 681 682 mdelay(LINK_WAIT_IATU); 683 } 684 685 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); 686 687 return -ETIMEDOUT; 688} 689 690void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index) 691{ 692 dw_pcie_writel_atu(pci, dir, index, PCIE_ATU_REGION_CTRL2, 0); 693} 694 695int dw_pcie_wait_for_link(struct dw_pcie *pci) 696{ 697 u32 offset, val; 698 int retries; 699 700 /* Check if the link is up or not */ 701 for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) { 702 if (dw_pcie_link_up(pci)) 703 break; 704 705 msleep(PCIE_LINK_WAIT_SLEEP_MS); 706 } 707 708 if (retries >= PCIE_LINK_WAIT_MAX_RETRIES) { 709 dev_info(pci->dev, "Phy link never came up\n"); 710 return -ETIMEDOUT; 711 } 712 713 /* 714 * As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link 715 * speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms 716 * after Link training completes before sending a Configuration Request. 717 */ 718 if (pci->max_link_speed > 2) 719 msleep(PCIE_RESET_CONFIG_WAIT_MS); 720 721 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 722 val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); 723 724 dev_info(pci->dev, "PCIe Gen.%u x%u link up\n", 725 FIELD_GET(PCI_EXP_LNKSTA_CLS, val), 726 FIELD_GET(PCI_EXP_LNKSTA_NLW, val)); 727 728 return 0; 729} 730EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link); 731 732bool dw_pcie_link_up(struct dw_pcie *pci) 733{ 734 u32 val; 735 736 if (pci->ops && pci->ops->link_up) 737 return pci->ops->link_up(pci); 738 739 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1); 740 return ((val & PCIE_PORT_DEBUG1_LINK_UP) && 741 (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING))); 742} 743EXPORT_SYMBOL_GPL(dw_pcie_link_up); 744 745void dw_pcie_upconfig_setup(struct dw_pcie *pci) 746{ 747 u32 val; 748 749 val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL); 750 val |= PORT_MLTI_UPCFG_SUPPORT; 751 dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val); 752} 753EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup); 754 755static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) 756{ 757 u32 cap, ctrl2, link_speed; 758 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 759 760 cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 761 762 /* 763 * Even if the platform doesn't want to limit the maximum link speed, 764 * just cache the hardware default value so that the vendor drivers can 765 * use it to do any link specific configuration. 766 */ 767 if (pci->max_link_speed < 1) { 768 pci->max_link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); 769 return; 770 } 771 772 ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2); 773 ctrl2 &= ~PCI_EXP_LNKCTL2_TLS; 774 775 switch (pcie_link_speed[pci->max_link_speed]) { 776 case PCIE_SPEED_2_5GT: 777 link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT; 778 break; 779 case PCIE_SPEED_5_0GT: 780 link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT; 781 break; 782 case PCIE_SPEED_8_0GT: 783 link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT; 784 break; 785 case PCIE_SPEED_16_0GT: 786 link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT; 787 break; 788 default: 789 /* Use hardware capability */ 790 link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); 791 ctrl2 &= ~PCI_EXP_LNKCTL2_HASD; 792 break; 793 } 794 795 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed); 796 797 cap &= ~((u32)PCI_EXP_LNKCAP_SLS); 798 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed); 799 800} 801 802int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) 803{ 804 u8 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 805 u32 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); 806 807 return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); 808} 809 810static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) 811{ 812 u32 lnkcap, lwsc, plc; 813 u8 cap; 814 815 if (!num_lanes) 816 return; 817 818 /* Set the number of lanes */ 819 plc = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); 820 plc &= ~PORT_LINK_FAST_LINK_MODE; 821 plc &= ~PORT_LINK_MODE_MASK; 822 823 /* Set link width speed control register */ 824 lwsc = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 825 lwsc &= ~PORT_LOGIC_LINK_WIDTH_MASK; 826 lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES; 827 switch (num_lanes) { 828 case 1: 829 plc |= PORT_LINK_MODE_1_LANES; 830 break; 831 case 2: 832 plc |= PORT_LINK_MODE_2_LANES; 833 break; 834 case 4: 835 plc |= PORT_LINK_MODE_4_LANES; 836 break; 837 case 8: 838 plc |= PORT_LINK_MODE_8_LANES; 839 break; 840 case 16: 841 plc |= PORT_LINK_MODE_16_LANES; 842 break; 843 default: 844 dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes); 845 return; 846 } 847 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc); 848 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc); 849 850 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 851 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); 852 lnkcap &= ~PCI_EXP_LNKCAP_MLW; 853 lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes); 854 dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap); 855} 856 857void dw_pcie_iatu_detect(struct dw_pcie *pci) 858{ 859 int max_region, ob, ib; 860 u32 val, min, dir; 861 u64 max; 862 863 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); 864 if (val == 0xFFFFFFFF) { 865 dw_pcie_cap_set(pci, IATU_UNROLL); 866 867 max_region = min((int)pci->atu_size / 512, 256); 868 } else { 869 pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE; 870 pci->atu_size = PCIE_ATU_VIEWPORT_SIZE; 871 872 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 0xFF); 873 max_region = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) + 1; 874 } 875 876 for (ob = 0; ob < max_region; ob++) { 877 dw_pcie_writel_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET, 0x11110000); 878 val = dw_pcie_readl_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET); 879 if (val != 0x11110000) 880 break; 881 } 882 883 for (ib = 0; ib < max_region; ib++) { 884 dw_pcie_writel_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET, 0x11110000); 885 val = dw_pcie_readl_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET); 886 if (val != 0x11110000) 887 break; 888 } 889 890 if (ob) { 891 dir = PCIE_ATU_REGION_DIR_OB; 892 } else if (ib) { 893 dir = PCIE_ATU_REGION_DIR_IB; 894 } else { 895 dev_err(pci->dev, "No iATU regions found\n"); 896 return; 897 } 898 899 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_LIMIT, 0x0); 900 min = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_LIMIT); 901 902 if (dw_pcie_ver_is_ge(pci, 460A)) { 903 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT, 0xFFFFFFFF); 904 max = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT); 905 } else { 906 max = 0; 907 } 908 909 pci->num_ob_windows = ob; 910 pci->num_ib_windows = ib; 911 pci->region_align = 1 << fls(min); 912 pci->region_limit = (max << 32) | (SZ_4G - 1); 913 914 dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n", 915 dw_pcie_cap_is(pci, IATU_UNROLL) ? "T" : "F", 916 pci->num_ob_windows, pci->num_ib_windows, 917 pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G); 918} 919 920static u32 dw_pcie_readl_dma(struct dw_pcie *pci, u32 reg) 921{ 922 u32 val = 0; 923 int ret; 924 925 if (pci->ops && pci->ops->read_dbi) 926 return pci->ops->read_dbi(pci, pci->edma.reg_base, reg, 4); 927 928 ret = dw_pcie_read(pci->edma.reg_base + reg, 4, &val); 929 if (ret) 930 dev_err(pci->dev, "Read DMA address failed\n"); 931 932 return val; 933} 934 935static int dw_pcie_edma_irq_vector(struct device *dev, unsigned int nr) 936{ 937 struct platform_device *pdev = to_platform_device(dev); 938 char name[6]; 939 int ret; 940 941 if (nr >= EDMA_MAX_WR_CH + EDMA_MAX_RD_CH) 942 return -EINVAL; 943 944 ret = platform_get_irq_byname_optional(pdev, "dma"); 945 if (ret > 0) 946 return ret; 947 948 snprintf(name, sizeof(name), "dma%u", nr); 949 950 return platform_get_irq_byname_optional(pdev, name); 951} 952 953static struct dw_edma_plat_ops dw_pcie_edma_ops = { 954 .irq_vector = dw_pcie_edma_irq_vector, 955}; 956 957static void dw_pcie_edma_init_data(struct dw_pcie *pci) 958{ 959 pci->edma.dev = pci->dev; 960 961 if (!pci->edma.ops) 962 pci->edma.ops = &dw_pcie_edma_ops; 963 964 pci->edma.flags |= DW_EDMA_CHIP_LOCAL; 965} 966 967static int dw_pcie_edma_find_mf(struct dw_pcie *pci) 968{ 969 u32 val; 970 971 /* 972 * Bail out finding the mapping format if it is already set by the glue 973 * driver. Also ensure that the edma.reg_base is pointing to a valid 974 * memory region. 975 */ 976 if (pci->edma.mf != EDMA_MF_EDMA_LEGACY) 977 return pci->edma.reg_base ? 0 : -ENODEV; 978 979 /* 980 * Indirect eDMA CSRs access has been completely removed since v5.40a 981 * thus no space is now reserved for the eDMA channels viewport and 982 * former DMA CTRL register is no longer fixed to FFs. 983 */ 984 if (dw_pcie_ver_is_ge(pci, 540A)) 985 val = 0xFFFFFFFF; 986 else 987 val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); 988 989 if (val == 0xFFFFFFFF && pci->edma.reg_base) { 990 pci->edma.mf = EDMA_MF_EDMA_UNROLL; 991 } else if (val != 0xFFFFFFFF) { 992 pci->edma.mf = EDMA_MF_EDMA_LEGACY; 993 994 pci->edma.reg_base = pci->dbi_base + PCIE_DMA_VIEWPORT_BASE; 995 } else { 996 return -ENODEV; 997 } 998 999 return 0; 1000} 1001 1002static int dw_pcie_edma_find_channels(struct dw_pcie *pci) 1003{ 1004 u32 val; 1005 1006 /* 1007 * Autodetect the read/write channels count only for non-HDMA platforms. 1008 * HDMA platforms with native CSR mapping doesn't support autodetect, 1009 * so the glue drivers should've passed the valid count already. If not, 1010 * the below sanity check will catch it. 1011 */ 1012 if (pci->edma.mf != EDMA_MF_HDMA_NATIVE) { 1013 val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL); 1014 1015 pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val); 1016 pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); 1017 } 1018 1019 /* Sanity check the channels count if the mapping was incorrect */ 1020 if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH || 1021 !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > EDMA_MAX_RD_CH) 1022 return -EINVAL; 1023 1024 return 0; 1025} 1026 1027static int dw_pcie_edma_find_chip(struct dw_pcie *pci) 1028{ 1029 int ret; 1030 1031 dw_pcie_edma_init_data(pci); 1032 1033 ret = dw_pcie_edma_find_mf(pci); 1034 if (ret) 1035 return ret; 1036 1037 return dw_pcie_edma_find_channels(pci); 1038} 1039 1040static int dw_pcie_edma_irq_verify(struct dw_pcie *pci) 1041{ 1042 struct platform_device *pdev = to_platform_device(pci->dev); 1043 u16 ch_cnt = pci->edma.ll_wr_cnt + pci->edma.ll_rd_cnt; 1044 char name[15]; 1045 int ret; 1046 1047 if (pci->edma.nr_irqs > 1) 1048 return pci->edma.nr_irqs != ch_cnt ? -EINVAL : 0; 1049 1050 ret = platform_get_irq_byname_optional(pdev, "dma"); 1051 if (ret > 0) { 1052 pci->edma.nr_irqs = 1; 1053 return 0; 1054 } 1055 1056 for (; pci->edma.nr_irqs < ch_cnt; pci->edma.nr_irqs++) { 1057 snprintf(name, sizeof(name), "dma%d", pci->edma.nr_irqs); 1058 1059 ret = platform_get_irq_byname_optional(pdev, name); 1060 if (ret <= 0) 1061 return -EINVAL; 1062 } 1063 1064 return 0; 1065} 1066 1067static int dw_pcie_edma_ll_alloc(struct dw_pcie *pci) 1068{ 1069 struct dw_edma_region *ll; 1070 dma_addr_t paddr; 1071 int i; 1072 1073 for (i = 0; i < pci->edma.ll_wr_cnt; i++) { 1074 ll = &pci->edma.ll_region_wr[i]; 1075 ll->sz = DMA_LLP_MEM_SIZE; 1076 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz, 1077 &paddr, GFP_KERNEL); 1078 if (!ll->vaddr.mem) 1079 return -ENOMEM; 1080 1081 ll->paddr = paddr; 1082 } 1083 1084 for (i = 0; i < pci->edma.ll_rd_cnt; i++) { 1085 ll = &pci->edma.ll_region_rd[i]; 1086 ll->sz = DMA_LLP_MEM_SIZE; 1087 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz, 1088 &paddr, GFP_KERNEL); 1089 if (!ll->vaddr.mem) 1090 return -ENOMEM; 1091 1092 ll->paddr = paddr; 1093 } 1094 1095 return 0; 1096} 1097 1098int dw_pcie_edma_detect(struct dw_pcie *pci) 1099{ 1100 int ret; 1101 1102 /* Don't fail if no eDMA was found (for the backward compatibility) */ 1103 ret = dw_pcie_edma_find_chip(pci); 1104 if (ret) 1105 return 0; 1106 1107 /* Don't fail on the IRQs verification (for the backward compatibility) */ 1108 ret = dw_pcie_edma_irq_verify(pci); 1109 if (ret) { 1110 dev_err(pci->dev, "Invalid eDMA IRQs found\n"); 1111 return 0; 1112 } 1113 1114 ret = dw_pcie_edma_ll_alloc(pci); 1115 if (ret) { 1116 dev_err(pci->dev, "Couldn't allocate LLP memory\n"); 1117 return ret; 1118 } 1119 1120 /* Don't fail if the DW eDMA driver can't find the device */ 1121 ret = dw_edma_probe(&pci->edma); 1122 if (ret && ret != -ENODEV) { 1123 dev_err(pci->dev, "Couldn't register eDMA device\n"); 1124 return ret; 1125 } 1126 1127 dev_info(pci->dev, "eDMA: unroll %s, %hu wr, %hu rd\n", 1128 pci->edma.mf == EDMA_MF_EDMA_UNROLL ? "T" : "F", 1129 pci->edma.ll_wr_cnt, pci->edma.ll_rd_cnt); 1130 1131 return 0; 1132} 1133 1134void dw_pcie_edma_remove(struct dw_pcie *pci) 1135{ 1136 dw_edma_remove(&pci->edma); 1137} 1138 1139void dw_pcie_hide_unsupported_l1ss(struct dw_pcie *pci) 1140{ 1141 u16 l1ss; 1142 u32 l1ss_cap; 1143 1144 if (pci->l1ss_support) 1145 return; 1146 1147 l1ss = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); 1148 if (!l1ss) 1149 return; 1150 1151 /* 1152 * Unless the driver claims "l1ss_support", don't advertise L1 PM 1153 * Substates because they require CLKREQ# and possibly other 1154 * device-specific configuration. 1155 */ 1156 l1ss_cap = dw_pcie_readl_dbi(pci, l1ss + PCI_L1SS_CAP); 1157 l1ss_cap &= ~(PCI_L1SS_CAP_PCIPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_1 | 1158 PCI_L1SS_CAP_PCIPM_L1_2 | PCI_L1SS_CAP_ASPM_L1_2 | 1159 PCI_L1SS_CAP_L1_PM_SS); 1160 dw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, l1ss_cap); 1161} 1162 1163void dw_pcie_setup(struct dw_pcie *pci) 1164{ 1165 u32 val; 1166 1167 dw_pcie_link_set_max_speed(pci); 1168 1169 /* Configure Gen1 N_FTS */ 1170 if (pci->n_fts[0]) { 1171 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); 1172 val &= ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK); 1173 val |= PORT_AFR_N_FTS(pci->n_fts[0]); 1174 val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]); 1175 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); 1176 } 1177 1178 /* Configure Gen2+ N_FTS */ 1179 if (pci->n_fts[1]) { 1180 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 1181 val &= ~PORT_LOGIC_N_FTS_MASK; 1182 val |= pci->n_fts[1]; 1183 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 1184 } 1185 1186 if (dw_pcie_cap_is(pci, CDM_CHECK)) { 1187 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); 1188 val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | 1189 PCIE_PL_CHK_REG_CHK_REG_START; 1190 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); 1191 } 1192 1193 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); 1194 val &= ~PORT_LINK_FAST_LINK_MODE; 1195 val |= PORT_LINK_DLL_LINK_EN; 1196 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); 1197 1198 dw_pcie_link_set_max_link_width(pci, pci->num_lanes); 1199} 1200 1201resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci, 1202 const char *reg_name, 1203 resource_size_t cpu_phys_addr) 1204{ 1205 struct device *dev = pci->dev; 1206 struct device_node *np = dev->of_node; 1207 int index; 1208 u64 reg_addr, fixup_addr; 1209 u64 (*fixup)(struct dw_pcie *pcie, u64 cpu_addr); 1210 1211 /* Look up reg_name address on parent bus */ 1212 index = of_property_match_string(np, "reg-names", reg_name); 1213 1214 if (index < 0) { 1215 dev_err(dev, "No %s in devicetree \"reg\" property\n", reg_name); 1216 return 0; 1217 } 1218 1219 of_property_read_reg(np, index, ®_addr, NULL); 1220 1221 fixup = pci->ops ? pci->ops->cpu_addr_fixup : NULL; 1222 if (fixup) { 1223 fixup_addr = fixup(pci, cpu_phys_addr); 1224 if (reg_addr == fixup_addr) { 1225 dev_info(dev, "%s reg[%d] %#010llx == %#010llx == fixup(cpu %#010llx); %ps is redundant with this devicetree\n", 1226 reg_name, index, reg_addr, fixup_addr, 1227 (unsigned long long) cpu_phys_addr, fixup); 1228 } else { 1229 dev_warn(dev, "%s reg[%d] %#010llx != %#010llx == fixup(cpu %#010llx); devicetree is broken\n", 1230 reg_name, index, reg_addr, fixup_addr, 1231 (unsigned long long) cpu_phys_addr); 1232 reg_addr = fixup_addr; 1233 } 1234 1235 return cpu_phys_addr - reg_addr; 1236 } 1237 1238 if (pci->use_parent_dt_ranges) { 1239 1240 /* 1241 * This platform once had a fixup, presumably because it 1242 * translates between CPU and PCI controller addresses. 1243 * Log a note if devicetree didn't describe a translation. 1244 */ 1245 if (reg_addr == cpu_phys_addr) 1246 dev_info(dev, "%s reg[%d] %#010llx == cpu %#010llx\n; no fixup was ever needed for this devicetree\n", 1247 reg_name, index, reg_addr, 1248 (unsigned long long) cpu_phys_addr); 1249 } else { 1250 if (reg_addr != cpu_phys_addr) { 1251 dev_warn(dev, "%s reg[%d] %#010llx != cpu %#010llx; no fixup and devicetree \"ranges\" is broken, assuming no translation\n", 1252 reg_name, index, reg_addr, 1253 (unsigned long long) cpu_phys_addr); 1254 return 0; 1255 } 1256 } 1257 1258 return cpu_phys_addr - reg_addr; 1259}
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