pci-meson.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * PCIe host controller driver for Amlogic MESON SoCs
  4 *
  5 * Copyright (c) 2018 Amlogic, inc.
  6 * Author: Yue Wang <yue.wang@amlogic.com>
  7 */
  8
  9#include <linux/clk.h>
 10#include <linux/delay.h>
 11#include <linux/gpio/consumer.h>
 12#include <linux/pci.h>
 13#include <linux/platform_device.h>
 14#include <linux/reset.h>
 15#include <linux/resource.h>
 16#include <linux/types.h>
 17#include <linux/phy/phy.h>
 18#include <linux/mod_devicetable.h>
 19#include <linux/module.h>
 20
 21#include "pcie-designware.h"
 22
 23#define to_meson_pcie(x) dev_get_drvdata((x)->dev)
 24
 25#define PCIE_CAP_MAX_PAYLOAD_SIZE(x)	((x) << 5)
 26#define PCIE_CAP_MAX_READ_REQ_SIZE(x)	((x) << 12)
 27
 28/* PCIe specific config registers */
 29#define PCIE_CFG0			0x0
 30#define APP_LTSSM_ENABLE		BIT(7)
 31
 32#define PCIE_CFG_STATUS12		0x30
 33#define IS_SMLH_LINK_UP(x)		((x) & (1 << 6))
 34#define IS_RDLH_LINK_UP(x)		((x) & (1 << 16))
 35#define IS_LTSSM_UP(x)			((((x) >> 10) & 0x1f) == 0x11)
 36
 37#define PCIE_CFG_STATUS17		0x44
 38#define PM_CURRENT_STATE(x)		(((x) >> 7) & 0x1)
 39
 40#define PORT_CLK_RATE			100000000UL
 41#define MAX_PAYLOAD_SIZE		256
 42#define MAX_READ_REQ_SIZE		256
 43#define PCIE_RESET_DELAY		500
 44#define PCIE_SHARED_RESET		1
 45#define PCIE_NORMAL_RESET		0
 46
 47enum pcie_data_rate {
 48	PCIE_GEN1,
 49	PCIE_GEN2,
 50	PCIE_GEN3,
 51	PCIE_GEN4
 52};
 53
 54struct meson_pcie_clk_res {
 55	struct clk *clk;
 56	struct clk *port_clk;
 57	struct clk *general_clk;
 58};
 59
 60struct meson_pcie_rc_reset {
 61	struct reset_control *port;
 62	struct reset_control *apb;
 63};
 64
 65struct meson_pcie {
 66	struct dw_pcie pci;
 67	void __iomem *cfg_base;
 68	struct meson_pcie_clk_res clk_res;
 69	struct meson_pcie_rc_reset mrst;
 70	struct gpio_desc *reset_gpio;
 71	struct phy *phy;
 72};
 73
 74static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp,
 75						  const char *id,
 76						  u32 reset_type)
 77{
 78	struct device *dev = mp->pci.dev;
 79	struct reset_control *reset;
 80
 81	if (reset_type == PCIE_SHARED_RESET)
 82		reset = devm_reset_control_get_shared(dev, id);
 83	else
 84		reset = devm_reset_control_get(dev, id);
 85
 86	return reset;
 87}
 88
 89static int meson_pcie_get_resets(struct meson_pcie *mp)
 90{
 91	struct meson_pcie_rc_reset *mrst = &mp->mrst;
 92
 93	mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET);
 94	if (IS_ERR(mrst->port))
 95		return PTR_ERR(mrst->port);
 96	reset_control_deassert(mrst->port);
 97
 98	mrst->apb = meson_pcie_get_reset(mp, "apb", PCIE_SHARED_RESET);
 99	if (IS_ERR(mrst->apb))
100		return PTR_ERR(mrst->apb);
101	reset_control_deassert(mrst->apb);
102
103	return 0;
104}
105
106static int meson_pcie_get_mems(struct platform_device *pdev,
107			       struct meson_pcie *mp)
108{
109	struct dw_pcie *pci = &mp->pci;
110	struct resource *res;
111
112	/*
113	 * For the broken DTs that supply 'dbi' as 'elbi', parse the 'elbi'
114	 * region and assign it to both 'pci->elbi_base' and 'pci->dbi_space' so
115	 * that the DWC core can skip parsing both regions.
116	 */
117	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
118	if (res) {
119		pci->elbi_base = devm_pci_remap_cfg_resource(pci->dev, res);
120		if (IS_ERR(pci->elbi_base))
121			return PTR_ERR(pci->elbi_base);
122
123		pci->dbi_base = pci->elbi_base;
124		pci->dbi_phys_addr = res->start;
125	}
126
127	mp->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
128	if (IS_ERR(mp->cfg_base))
129		return PTR_ERR(mp->cfg_base);
130
131	return 0;
132}
133
134static int meson_pcie_power_on(struct meson_pcie *mp)
135{
136	int ret = 0;
137
138	ret = phy_init(mp->phy);
139	if (ret)
140		return ret;
141
142	ret = phy_power_on(mp->phy);
143	if (ret) {
144		phy_exit(mp->phy);
145		return ret;
146	}
147
148	return 0;
149}
150
151static void meson_pcie_power_off(struct meson_pcie *mp)
152{
153	phy_power_off(mp->phy);
154	phy_exit(mp->phy);
155}
156
157static int meson_pcie_reset(struct meson_pcie *mp)
158{
159	struct meson_pcie_rc_reset *mrst = &mp->mrst;
160	int ret = 0;
161
162	ret = phy_reset(mp->phy);
163	if (ret)
164		return ret;
165
166	reset_control_assert(mrst->port);
167	reset_control_assert(mrst->apb);
168	udelay(PCIE_RESET_DELAY);
169	reset_control_deassert(mrst->port);
170	reset_control_deassert(mrst->apb);
171	udelay(PCIE_RESET_DELAY);
172
173	return 0;
174}
175
176static inline void meson_pcie_disable_clock(void *data)
177{
178	struct clk *clk = data;
179
180	clk_disable_unprepare(clk);
181}
182
183static inline struct clk *meson_pcie_probe_clock(struct device *dev,
184						 const char *id, u64 rate)
185{
186	struct clk *clk;
187	int ret;
188
189	clk = devm_clk_get(dev, id);
190	if (IS_ERR(clk))
191		return clk;
192
193	if (rate) {
194		ret = clk_set_rate(clk, rate);
195		if (ret) {
196			dev_err(dev, "set clk rate failed, ret = %d\n", ret);
197			return ERR_PTR(ret);
198		}
199	}
200
201	ret = clk_prepare_enable(clk);
202	if (ret) {
203		dev_err(dev, "couldn't enable clk\n");
204		return ERR_PTR(ret);
205	}
206
207	devm_add_action_or_reset(dev, meson_pcie_disable_clock, clk);
208
209	return clk;
210}
211
212static int meson_pcie_probe_clocks(struct meson_pcie *mp)
213{
214	struct device *dev = mp->pci.dev;
215	struct meson_pcie_clk_res *res = &mp->clk_res;
216
217	res->port_clk = meson_pcie_probe_clock(dev, "port", PORT_CLK_RATE);
218	if (IS_ERR(res->port_clk))
219		return PTR_ERR(res->port_clk);
220
221	res->general_clk = meson_pcie_probe_clock(dev, "general", 0);
222	if (IS_ERR(res->general_clk))
223		return PTR_ERR(res->general_clk);
224
225	res->clk = meson_pcie_probe_clock(dev, "pclk", 0);
226	if (IS_ERR(res->clk))
227		return PTR_ERR(res->clk);
228
229	return 0;
230}
231
232static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg)
233{
234	return readl(mp->cfg_base + reg);
235}
236
237static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg)
238{
239	writel(val, mp->cfg_base + reg);
240}
241
242static void meson_pcie_assert_reset(struct meson_pcie *mp)
243{
244	gpiod_set_value_cansleep(mp->reset_gpio, 1);
245	udelay(500);
246	gpiod_set_value_cansleep(mp->reset_gpio, 0);
247}
248
249static void meson_pcie_ltssm_enable(struct meson_pcie *mp)
250{
251	u32 val;
252
253	val = meson_cfg_readl(mp, PCIE_CFG0);
254	val |= APP_LTSSM_ENABLE;
255	meson_cfg_writel(mp, val, PCIE_CFG0);
256}
257
258static int meson_size_to_payload(struct meson_pcie *mp, int size)
259{
260	struct device *dev = mp->pci.dev;
261
262	/*
263	 * dwc supports 2^(val+7) payload size, which val is 0~5 default to 1.
264	 * So if input size is not 2^order alignment or less than 2^7 or bigger
265	 * than 2^12, just set to default size 2^(1+7).
266	 */
267	if (!is_power_of_2(size) || size < 128 || size > 4096) {
268		dev_warn(dev, "payload size %d, set to default 256\n", size);
269		return 1;
270	}
271
272	return fls(size) - 8;
273}
274
275static void meson_set_max_payload(struct meson_pcie *mp, int size)
276{
277	struct dw_pcie *pci = &mp->pci;
278	u32 val;
279	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
280	int max_payload_size = meson_size_to_payload(mp, size);
281
282	val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
283	val &= ~PCI_EXP_DEVCTL_PAYLOAD;
284	dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
285
286	val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
287	val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
288	dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
289}
290
291static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size)
292{
293	struct dw_pcie *pci = &mp->pci;
294	u32 val;
295	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
296	int max_rd_req_size = meson_size_to_payload(mp, size);
297
298	val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
299	val &= ~PCI_EXP_DEVCTL_READRQ;
300	dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
301
302	val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
303	val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size);
304	dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
305}
306
307static int meson_pcie_start_link(struct dw_pcie *pci)
308{
309	struct meson_pcie *mp = to_meson_pcie(pci);
310
311	meson_pcie_ltssm_enable(mp);
312	meson_pcie_assert_reset(mp);
313
314	return 0;
315}
316
317static int meson_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn,
318				  int where, int size, u32 *val)
319{
320	int ret;
321
322	ret = pci_generic_config_read(bus, devfn, where, size, val);
323	if (ret != PCIBIOS_SUCCESSFUL)
324		return ret;
325
326	/*
327	 * There is a bug in the MESON AXG PCIe controller whereby software
328	 * cannot program the PCI_CLASS_DEVICE register, so we must fabricate
329	 * the return value in the config accessors.
330	 */
331	if ((where & ~3) == PCI_CLASS_REVISION) {
332		if (size <= 2)
333			*val = (*val & ((1 << (size * 8)) - 1)) << (8 * (where & 3));
334		*val &= ~0xffffff00;
335		*val |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
336		if (size <= 2)
337			*val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
338	}
339
340	return PCIBIOS_SUCCESSFUL;
341}
342
343static struct pci_ops meson_pci_ops = {
344	.map_bus = dw_pcie_own_conf_map_bus,
345	.read = meson_pcie_rd_own_conf,
346	.write = pci_generic_config_write,
347};
348
349static bool meson_pcie_link_up(struct dw_pcie *pci)
350{
351	struct meson_pcie *mp = to_meson_pcie(pci);
352	u32 state12;
353
354	state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
355	return IS_SMLH_LINK_UP(state12) && IS_RDLH_LINK_UP(state12);
356}
357
358static int meson_pcie_host_init(struct dw_pcie_rp *pp)
359{
360	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
361	struct meson_pcie *mp = to_meson_pcie(pci);
362
363	pp->bridge->ops = &meson_pci_ops;
364
365	meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
366	meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
367
368	return 0;
369}
370
371static const struct dw_pcie_host_ops meson_pcie_host_ops = {
372	.init = meson_pcie_host_init,
373};
374
375static const struct dw_pcie_ops dw_pcie_ops = {
376	.link_up = meson_pcie_link_up,
377	.start_link = meson_pcie_start_link,
378};
379
380static int meson_pcie_probe(struct platform_device *pdev)
381{
382	struct device *dev = &pdev->dev;
383	struct dw_pcie *pci;
384	struct meson_pcie *mp;
385	int ret;
386
387	mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
388	if (!mp)
389		return -ENOMEM;
390
391	pci = &mp->pci;
392	pci->dev = dev;
393	pci->ops = &dw_pcie_ops;
394	pci->pp.ops = &meson_pcie_host_ops;
395	pci->num_lanes = 1;
396
397	mp->phy = devm_phy_get(dev, "pcie");
398	if (IS_ERR(mp->phy)) {
399		dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy));
400		return PTR_ERR(mp->phy);
401	}
402
403	mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
404	if (IS_ERR(mp->reset_gpio)) {
405		dev_err(dev, "get reset gpio failed\n");
406		return PTR_ERR(mp->reset_gpio);
407	}
408
409	ret = meson_pcie_get_resets(mp);
410	if (ret) {
411		dev_err(dev, "get reset resource failed, %d\n", ret);
412		return ret;
413	}
414
415	ret = meson_pcie_get_mems(pdev, mp);
416	if (ret) {
417		dev_err(dev, "get memory resource failed, %d\n", ret);
418		return ret;
419	}
420
421	ret = meson_pcie_power_on(mp);
422	if (ret) {
423		dev_err(dev, "phy power on failed, %d\n", ret);
424		return ret;
425	}
426
427	ret = meson_pcie_reset(mp);
428	if (ret) {
429		dev_err(dev, "reset failed, %d\n", ret);
430		goto err_phy;
431	}
432
433	ret = meson_pcie_probe_clocks(mp);
434	if (ret) {
435		dev_err(dev, "init clock resources failed, %d\n", ret);
436		goto err_phy;
437	}
438
439	platform_set_drvdata(pdev, mp);
440
441	ret = dw_pcie_host_init(&pci->pp);
442	if (ret < 0) {
443		dev_err(dev, "Add PCIe port failed, %d\n", ret);
444		goto err_phy;
445	}
446
447	return 0;
448
449err_phy:
450	meson_pcie_power_off(mp);
451	return ret;
452}
453
454static const struct of_device_id meson_pcie_of_match[] = {
455	{
456		.compatible = "amlogic,axg-pcie",
457	},
458	{
459		.compatible = "amlogic,g12a-pcie",
460	},
461	{},
462};
463MODULE_DEVICE_TABLE(of, meson_pcie_of_match);
464
465static struct platform_driver meson_pcie_driver = {
466	.probe = meson_pcie_probe,
467	.driver = {
468		.name = "meson-pcie",
469		.of_match_table = meson_pcie_of_match,
470	},
471};
472
473module_platform_driver(meson_pcie_driver);
474
475MODULE_AUTHOR("Yue Wang <yue.wang@amlogic.com>");
476MODULE_DESCRIPTION("Amlogic PCIe Controller driver");
477MODULE_LICENSE("GPL v2");