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pci-keystone.c
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linux-6.19.14/drivers/pci/controller/dwc/pci-keystone.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * PCIe host controller driver for Texas Instruments Keystone SoCs 4 * 5 * Copyright (C) 2013-2014 Texas Instruments., Ltd. 6 * https://www.ti.com 7 * 8 * Author: Murali Karicheri <m-karicheri2@ti.com> 9 * Implementation based on pci-exynos.c and pcie-designware.c 10 */ 11 12#include <linux/clk.h> 13#include <linux/delay.h> 14#include <linux/gpio/consumer.h> 15#include <linux/init.h> 16#include <linux/interrupt.h> 17#include <linux/irqchip/chained_irq.h> 18#include <linux/irqdomain.h> 19#include <linux/mfd/syscon.h> 20#include <linux/module.h> 21#include <linux/msi.h> 22#include <linux/of.h> 23#include <linux/of_irq.h> 24#include <linux/of_pci.h> 25#include <linux/phy/phy.h> 26#include <linux/platform_device.h> 27#include <linux/regmap.h> 28#include <linux/resource.h> 29#include <linux/signal.h> 30 31#include "../../pci.h" 32#include "pcie-designware.h" 33 34#define PCIE_VENDORID_MASK 0xffff 35#define PCIE_DEVICEID_SHIFT 16 36 37/* Application registers */ 38#define PID 0x000 39#define RTL GENMASK(15, 11) 40#define RTL_SHIFT 11 41#define AM6_PCI_PG1_RTL_VER 0x15 42 43#define CMD_STATUS 0x004 44#define LTSSM_EN_VAL BIT(0) 45#define OB_XLAT_EN_VAL BIT(1) 46#define DBI_CS2 BIT(5) 47 48#define CFG_SETUP 0x008 49#define CFG_BUS(x) (((x) & 0xff) << 16) 50#define CFG_DEVICE(x) (((x) & 0x1f) << 8) 51#define CFG_FUNC(x) ((x) & 0x7) 52#define CFG_TYPE1 BIT(24) 53 54#define OB_SIZE 0x030 55#define OB_OFFSET_INDEX(n) (0x200 + (8 * (n))) 56#define OB_OFFSET_HI(n) (0x204 + (8 * (n))) 57#define OB_ENABLEN BIT(0) 58#define OB_WIN_SIZE 8 /* 8MB */ 59 60#define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1))) 61#define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1))) 62#define PCIE_EP_IRQ_SET 0x64 63#define PCIE_EP_IRQ_CLR 0x68 64#define INT_ENABLE BIT(0) 65 66/* IRQ register defines */ 67#define IRQ_EOI 0x050 68 69#define MSI_IRQ 0x054 70#define MSI_IRQ_STATUS(n) (0x104 + ((n) << 4)) 71#define MSI_IRQ_ENABLE_SET(n) (0x108 + ((n) << 4)) 72#define MSI_IRQ_ENABLE_CLR(n) (0x10c + ((n) << 4)) 73#define MSI_IRQ_OFFSET 4 74 75#define IRQ_STATUS(n) (0x184 + ((n) << 4)) 76#define IRQ_ENABLE_SET(n) (0x188 + ((n) << 4)) 77#define INTx_EN BIT(0) 78 79#define ERR_IRQ_STATUS 0x1c4 80#define ERR_IRQ_ENABLE_SET 0x1c8 81#define ERR_AER BIT(5) /* ECRC error */ 82#define AM6_ERR_AER BIT(4) /* AM6 ECRC error */ 83#define ERR_AXI BIT(4) /* AXI tag lookup fatal error */ 84#define ERR_CORR BIT(3) /* Correctable error */ 85#define ERR_NONFATAL BIT(2) /* Non-fatal error */ 86#define ERR_FATAL BIT(1) /* Fatal error */ 87#define ERR_SYS BIT(0) /* System error */ 88#define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ 89 ERR_NONFATAL | ERR_FATAL | ERR_SYS) 90 91/* PCIE controller device IDs */ 92#define PCIE_RC_K2HK 0xb008 93#define PCIE_RC_K2E 0xb009 94#define PCIE_RC_K2L 0xb00a 95#define PCIE_RC_K2G 0xb00b 96 97#define KS_PCIE_DEV_TYPE_MASK (0x3 << 1) 98#define KS_PCIE_DEV_TYPE(mode) ((mode) << 1) 99 100#define EP 0x0 101#define LEG_EP 0x1 102#define RC 0x2 103 104#define KS_PCIE_SYSCLOCKOUTEN BIT(0) 105 106#define AM654_PCIE_DEV_TYPE_MASK 0x3 107#define AM654_WIN_SIZE SZ_64K 108 109#define APP_ADDR_SPACE_0 (16 * SZ_1K) 110 111#define to_keystone_pcie(x) dev_get_drvdata((x)->dev) 112 113#define PCI_DEVICE_ID_TI_AM654X 0xb00c 114 115struct ks_pcie_of_data { 116 enum dw_pcie_device_mode mode; 117 const struct dw_pcie_host_ops *host_ops; 118 const struct dw_pcie_ep_ops *ep_ops; 119 u32 version; 120}; 121 122struct keystone_pcie { 123 struct dw_pcie *pci; 124 /* PCI Device ID */ 125 u32 device_id; 126 int intx_host_irqs[PCI_NUM_INTX]; 127 128 int msi_host_irq; 129 int num_lanes; 130 u32 num_viewport; 131 struct phy **phy; 132 struct device_link **link; 133 struct device_node *msi_intc_np; 134 struct irq_domain *intx_irq_domain; 135 struct device_node *np; 136 137 /* Application register space */ 138 void __iomem *va_app_base; /* DT 1st resource */ 139 struct resource app; 140 bool is_am6; 141}; 142 143static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset) 144{ 145 return readl(ks_pcie->va_app_base + offset); 146} 147 148static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset, 149 u32 val) 150{ 151 writel(val, ks_pcie->va_app_base + offset); 152} 153 154static void ks_pcie_msi_irq_ack(struct irq_data *data) 155{ 156 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 157 struct keystone_pcie *ks_pcie; 158 u32 irq = data->hwirq; 159 struct dw_pcie *pci; 160 u32 reg_offset; 161 u32 bit_pos; 162 163 pci = to_dw_pcie_from_pp(pp); 164 ks_pcie = to_keystone_pcie(pci); 165 166 reg_offset = irq % 8; 167 bit_pos = irq >> 3; 168 169 ks_pcie_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset), 170 BIT(bit_pos)); 171 ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET); 172} 173 174static void ks_pcie_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 175{ 176 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 177 struct keystone_pcie *ks_pcie; 178 struct dw_pcie *pci; 179 u64 msi_target; 180 181 pci = to_dw_pcie_from_pp(pp); 182 ks_pcie = to_keystone_pcie(pci); 183 184 msi_target = ks_pcie->app.start + MSI_IRQ; 185 msg->address_lo = lower_32_bits(msi_target); 186 msg->address_hi = upper_32_bits(msi_target); 187 msg->data = data->hwirq; 188 189 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", 190 (int)data->hwirq, msg->address_hi, msg->address_lo); 191} 192 193static void ks_pcie_msi_mask(struct irq_data *data) 194{ 195 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 196 struct keystone_pcie *ks_pcie; 197 u32 irq = data->hwirq; 198 struct dw_pcie *pci; 199 unsigned long flags; 200 u32 reg_offset; 201 u32 bit_pos; 202 203 raw_spin_lock_irqsave(&pp->lock, flags); 204 205 pci = to_dw_pcie_from_pp(pp); 206 ks_pcie = to_keystone_pcie(pci); 207 208 reg_offset = irq % 8; 209 bit_pos = irq >> 3; 210 211 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), 212 BIT(bit_pos)); 213 214 raw_spin_unlock_irqrestore(&pp->lock, flags); 215} 216 217static void ks_pcie_msi_unmask(struct irq_data *data) 218{ 219 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 220 struct keystone_pcie *ks_pcie; 221 u32 irq = data->hwirq; 222 struct dw_pcie *pci; 223 unsigned long flags; 224 u32 reg_offset; 225 u32 bit_pos; 226 227 raw_spin_lock_irqsave(&pp->lock, flags); 228 229 pci = to_dw_pcie_from_pp(pp); 230 ks_pcie = to_keystone_pcie(pci); 231 232 reg_offset = irq % 8; 233 bit_pos = irq >> 3; 234 235 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), 236 BIT(bit_pos)); 237 238 raw_spin_unlock_irqrestore(&pp->lock, flags); 239} 240 241static struct irq_chip ks_pcie_msi_irq_chip = { 242 .name = "KEYSTONE-PCI-MSI", 243 .irq_ack = ks_pcie_msi_irq_ack, 244 .irq_compose_msi_msg = ks_pcie_compose_msi_msg, 245 .irq_mask = ks_pcie_msi_mask, 246 .irq_unmask = ks_pcie_msi_unmask, 247}; 248 249/** 250 * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers 251 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone 252 * PCIe host controller driver information. 253 * 254 * Since modification of dbi_cs2 involves different clock domain, read the 255 * status back to ensure the transition is complete. 256 */ 257static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) 258{ 259 u32 val; 260 261 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 262 val |= DBI_CS2; 263 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 264 265 do { 266 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 267 } while (!(val & DBI_CS2)); 268} 269 270/** 271 * ks_pcie_clear_dbi_mode() - Disable DBI mode 272 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone 273 * PCIe host controller driver information. 274 * 275 * Since modification of dbi_cs2 involves different clock domain, read the 276 * status back to ensure the transition is complete. 277 */ 278static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) 279{ 280 u32 val; 281 282 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 283 val &= ~DBI_CS2; 284 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 285 286 do { 287 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 288 } while (val & DBI_CS2); 289} 290 291static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp) 292{ 293 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 294 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 295 296 /* Configure and set up BAR0 */ 297 ks_pcie_set_dbi_mode(ks_pcie); 298 299 /* Enable BAR0 */ 300 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1); 301 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); 302 303 ks_pcie_clear_dbi_mode(ks_pcie); 304 305 /* 306 * For BAR0, just setting bus address for inbound writes (MSI) should 307 * be sufficient. Use physical address to avoid any conflicts. 308 */ 309 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); 310 311 pp->msi_irq_chip = &ks_pcie_msi_irq_chip; 312 return dw_pcie_allocate_domains(pp); 313} 314 315static void ks_pcie_handle_intx_irq(struct keystone_pcie *ks_pcie, 316 int offset) 317{ 318 struct dw_pcie *pci = ks_pcie->pci; 319 struct device *dev = pci->dev; 320 u32 pending; 321 322 pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(offset)); 323 324 if (BIT(0) & pending) { 325 dev_dbg(dev, ": irq: irq_offset %d", offset); 326 generic_handle_domain_irq(ks_pcie->intx_irq_domain, offset); 327 } 328 329 /* EOI the INTx interrupt */ 330 ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset); 331} 332 333static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) 334{ 335 ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); 336} 337 338static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) 339{ 340 u32 reg; 341 struct device *dev = ks_pcie->pci->dev; 342 343 reg = ks_pcie_app_readl(ks_pcie, ERR_IRQ_STATUS); 344 if (!reg) 345 return IRQ_NONE; 346 347 if (reg & ERR_SYS) 348 dev_err(dev, "System Error\n"); 349 350 if (reg & ERR_FATAL) 351 dev_err(dev, "Fatal Error\n"); 352 353 if (reg & ERR_NONFATAL) 354 dev_dbg(dev, "Non Fatal Error\n"); 355 356 if (reg & ERR_CORR) 357 dev_dbg(dev, "Correctable Error\n"); 358 359 if (!ks_pcie->is_am6 && (reg & ERR_AXI)) 360 dev_err(dev, "AXI tag lookup fatal Error\n"); 361 362 if (reg & ERR_AER || (ks_pcie->is_am6 && (reg & AM6_ERR_AER))) 363 dev_err(dev, "ECRC Error\n"); 364 365 ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, reg); 366 367 return IRQ_HANDLED; 368} 369 370static void ks_pcie_ack_intx_irq(struct irq_data *d) 371{ 372} 373 374static void ks_pcie_mask_intx_irq(struct irq_data *d) 375{ 376} 377 378static void ks_pcie_unmask_intx_irq(struct irq_data *d) 379{ 380} 381 382static struct irq_chip ks_pcie_intx_irq_chip = { 383 .name = "Keystone-PCI-INTX-IRQ", 384 .irq_ack = ks_pcie_ack_intx_irq, 385 .irq_mask = ks_pcie_mask_intx_irq, 386 .irq_unmask = ks_pcie_unmask_intx_irq, 387}; 388 389static int ks_pcie_init_intx_irq_map(struct irq_domain *d, 390 unsigned int irq, irq_hw_number_t hw_irq) 391{ 392 irq_set_chip_and_handler(irq, &ks_pcie_intx_irq_chip, 393 handle_level_irq); 394 irq_set_chip_data(irq, d->host_data); 395 396 return 0; 397} 398 399static const struct irq_domain_ops ks_pcie_intx_irq_domain_ops = { 400 .map = ks_pcie_init_intx_irq_map, 401 .xlate = irq_domain_xlate_onetwocell, 402}; 403 404static int ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) 405{ 406 u32 val; 407 u32 num_viewport = ks_pcie->num_viewport; 408 struct dw_pcie *pci = ks_pcie->pci; 409 struct dw_pcie_rp *pp = &pci->pp; 410 struct resource_entry *entry; 411 struct resource *mem; 412 u64 start, end; 413 int i; 414 415 entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); 416 if (!entry) 417 return -ENODEV; 418 419 mem = entry->res; 420 start = mem->start; 421 end = mem->end; 422 423 /* Disable BARs for inbound access */ 424 ks_pcie_set_dbi_mode(ks_pcie); 425 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 426 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); 427 ks_pcie_clear_dbi_mode(ks_pcie); 428 429 if (ks_pcie->is_am6) 430 return 0; 431 432 val = ilog2(OB_WIN_SIZE); 433 ks_pcie_app_writel(ks_pcie, OB_SIZE, val); 434 435 /* Using Direct 1:1 mapping of RC <-> PCI memory space */ 436 for (i = 0; i < num_viewport && (start < end); i++) { 437 ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i), 438 lower_32_bits(start) | OB_ENABLEN); 439 ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i), 440 upper_32_bits(start)); 441 start += OB_WIN_SIZE * SZ_1M; 442 } 443 444 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 445 val |= OB_XLAT_EN_VAL; 446 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 447 448 return 0; 449} 450 451static void __iomem *ks_pcie_other_map_bus(struct pci_bus *bus, 452 unsigned int devfn, int where) 453{ 454 struct dw_pcie_rp *pp = bus->sysdata; 455 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 456 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 457 u32 reg; 458 459 /* 460 * Checking whether the link is up here is a last line of defense 461 * against platforms that forward errors on the system bus as 462 * SError upon PCI configuration transactions issued when the link 463 * is down. This check is racy by definition and does not stop 464 * the system from triggering an SError if the link goes down 465 * after this check is performed. 466 */ 467 if (!dw_pcie_link_up(pci)) 468 return NULL; 469 470 reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) | 471 CFG_FUNC(PCI_FUNC(devfn)); 472 if (!pci_is_root_bus(bus->parent)) 473 reg |= CFG_TYPE1; 474 ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg); 475 476 return pp->va_cfg0_base + where; 477} 478 479static struct pci_ops ks_child_pcie_ops = { 480 .map_bus = ks_pcie_other_map_bus, 481 .read = pci_generic_config_read, 482 .write = pci_generic_config_write, 483}; 484 485static struct pci_ops ks_pcie_ops = { 486 .map_bus = dw_pcie_own_conf_map_bus, 487 .read = pci_generic_config_read, 488 .write = pci_generic_config_write, 489}; 490 491/** 492 * ks_pcie_link_up() - Check if link up 493 * @pci: A pointer to the dw_pcie structure which holds the DesignWare PCIe host 494 * controller driver information. 495 */ 496static bool ks_pcie_link_up(struct dw_pcie *pci) 497{ 498 u32 val; 499 500 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0); 501 return (val & PORT_LOGIC_LTSSM_STATE_MASK) == PORT_LOGIC_LTSSM_STATE_L0; 502} 503 504static void ks_pcie_stop_link(struct dw_pcie *pci) 505{ 506 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 507 u32 val; 508 509 /* Disable Link training */ 510 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 511 val &= ~LTSSM_EN_VAL; 512 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 513} 514 515static int ks_pcie_start_link(struct dw_pcie *pci) 516{ 517 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 518 u32 val; 519 520 /* Initiate Link Training */ 521 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 522 ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); 523 524 return 0; 525} 526 527static void ks_pcie_quirk(struct pci_dev *dev) 528{ 529 struct pci_bus *bus = dev->bus; 530 struct keystone_pcie *ks_pcie; 531 struct device *bridge_dev; 532 struct pci_dev *bridge; 533 u32 val; 534 535 static const struct pci_device_id rc_pci_devids[] = { 536 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK), 537 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 538 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E), 539 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 540 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L), 541 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 542 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G), 543 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 544 { 0, }, 545 }; 546 static const struct pci_device_id am6_pci_devids[] = { 547 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654X), 548 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, 549 { 0, }, 550 }; 551 552 if (pci_is_root_bus(bus)) 553 bridge = dev; 554 555 /* look for the host bridge */ 556 while (!pci_is_root_bus(bus)) { 557 bridge = bus->self; 558 bus = bus->parent; 559 } 560 561 if (!bridge) 562 return; 563 564 /* 565 * Keystone PCI controller has a h/w limitation of 566 * 256 bytes maximum read request size. It can't handle 567 * anything higher than this. So force this limit on 568 * all downstream devices. 569 */ 570 if (pci_match_id(rc_pci_devids, bridge)) { 571 if (pcie_get_readrq(dev) > 256) { 572 dev_info(&dev->dev, "limiting MRRS to 256 bytes\n"); 573 pcie_set_readrq(dev, 256); 574 } 575 } 576 577 /* 578 * Memory transactions fail with PCI controller in AM654 PG1.0 579 * when MRRS is set to more than 128 bytes. Force the MRRS to 580 * 128 bytes in all downstream devices. 581 */ 582 if (pci_match_id(am6_pci_devids, bridge)) { 583 bridge_dev = pci_get_host_bridge_device(dev); 584 if (!bridge_dev || !bridge_dev->parent) 585 return; 586 587 ks_pcie = dev_get_drvdata(bridge_dev->parent); 588 if (!ks_pcie) 589 return; 590 591 val = ks_pcie_app_readl(ks_pcie, PID); 592 val &= RTL; 593 val >>= RTL_SHIFT; 594 if (val != AM6_PCI_PG1_RTL_VER) 595 return; 596 597 if (pcie_get_readrq(dev) > 128) { 598 dev_info(&dev->dev, "limiting MRRS to 128 bytes\n"); 599 pcie_set_readrq(dev, 128); 600 } 601 } 602} 603DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); 604 605static void ks_pcie_msi_irq_handler(struct irq_desc *desc) 606{ 607 unsigned int irq = desc->irq_data.hwirq; 608 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); 609 u32 offset = irq - ks_pcie->msi_host_irq; 610 struct dw_pcie *pci = ks_pcie->pci; 611 struct dw_pcie_rp *pp = &pci->pp; 612 struct device *dev = pci->dev; 613 struct irq_chip *chip = irq_desc_get_chip(desc); 614 u32 vector, reg, pos; 615 616 dev_dbg(dev, "%s, irq %d\n", __func__, irq); 617 618 /* 619 * The chained irq handler installation would have replaced normal 620 * interrupt driver handler so we need to take care of mask/unmask and 621 * ack operation. 622 */ 623 chained_irq_enter(chip, desc); 624 625 reg = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset)); 626 /* 627 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit 628 * shows 1, 9, 17, 25 and so forth 629 */ 630 for (pos = 0; pos < 4; pos++) { 631 if (!(reg & BIT(pos))) 632 continue; 633 634 vector = offset + (pos << 3); 635 dev_dbg(dev, "irq: bit %d, vector %d\n", pos, vector); 636 generic_handle_domain_irq(pp->irq_domain, vector); 637 } 638 639 chained_irq_exit(chip, desc); 640} 641 642/** 643 * ks_pcie_intx_irq_handler() - Handle INTX interrupt 644 * @desc: Pointer to irq descriptor 645 * 646 * Traverse through pending INTX interrupts and invoke handler for each. Also 647 * takes care of interrupt controller level mask/ack operation. 648 */ 649static void ks_pcie_intx_irq_handler(struct irq_desc *desc) 650{ 651 unsigned int irq = irq_desc_get_irq(desc); 652 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); 653 struct dw_pcie *pci = ks_pcie->pci; 654 struct device *dev = pci->dev; 655 u32 irq_offset = irq - ks_pcie->intx_host_irqs[0]; 656 struct irq_chip *chip = irq_desc_get_chip(desc); 657 658 dev_dbg(dev, ": Handling INTX irq %d\n", irq); 659 660 /* 661 * The chained irq handler installation would have replaced normal 662 * interrupt driver handler so we need to take care of mask/unmask and 663 * ack operation. 664 */ 665 chained_irq_enter(chip, desc); 666 ks_pcie_handle_intx_irq(ks_pcie, irq_offset); 667 chained_irq_exit(chip, desc); 668} 669 670static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) 671{ 672 struct device *dev = ks_pcie->pci->dev; 673 struct device_node *np = ks_pcie->np; 674 struct device_node *intc_np; 675 struct irq_data *irq_data; 676 int irq_count, irq, ret, i; 677 678 if (!IS_ENABLED(CONFIG_PCI_MSI)) 679 return 0; 680 681 intc_np = of_get_child_by_name(np, "msi-interrupt-controller"); 682 if (!intc_np) { 683 if (ks_pcie->is_am6) 684 return 0; 685 dev_warn(dev, "msi-interrupt-controller node is absent\n"); 686 return -EINVAL; 687 } 688 689 irq_count = of_irq_count(intc_np); 690 if (!irq_count) { 691 dev_err(dev, "No IRQ entries in msi-interrupt-controller\n"); 692 ret = -EINVAL; 693 goto err; 694 } 695 696 for (i = 0; i < irq_count; i++) { 697 irq = irq_of_parse_and_map(intc_np, i); 698 if (!irq) { 699 ret = -EINVAL; 700 goto err; 701 } 702 703 if (!ks_pcie->msi_host_irq) { 704 irq_data = irq_get_irq_data(irq); 705 if (!irq_data) { 706 ret = -EINVAL; 707 goto err; 708 } 709 ks_pcie->msi_host_irq = irq_data->hwirq; 710 } 711 712 irq_set_chained_handler_and_data(irq, ks_pcie_msi_irq_handler, 713 ks_pcie); 714 } 715 716 of_node_put(intc_np); 717 return 0; 718 719err: 720 of_node_put(intc_np); 721 return ret; 722} 723 724static int ks_pcie_config_intx_irq(struct keystone_pcie *ks_pcie) 725{ 726 struct device *dev = ks_pcie->pci->dev; 727 struct irq_domain *intx_irq_domain; 728 struct device_node *np = ks_pcie->np; 729 struct device_node *intc_np; 730 int irq_count, irq, ret = 0, i; 731 732 intc_np = of_get_child_by_name(np, "legacy-interrupt-controller"); 733 if (!intc_np) { 734 /* 735 * Since INTX interrupts are modeled as edge-interrupts in 736 * AM6, keep it disabled for now. 737 */ 738 if (ks_pcie->is_am6) 739 return 0; 740 dev_warn(dev, "legacy-interrupt-controller node is absent\n"); 741 return -EINVAL; 742 } 743 744 irq_count = of_irq_count(intc_np); 745 if (!irq_count) { 746 dev_err(dev, "No IRQ entries in legacy-interrupt-controller\n"); 747 ret = -EINVAL; 748 goto err; 749 } 750 751 for (i = 0; i < irq_count; i++) { 752 irq = irq_of_parse_and_map(intc_np, i); 753 if (!irq) { 754 ret = -EINVAL; 755 goto err; 756 } 757 ks_pcie->intx_host_irqs[i] = irq; 758 759 irq_set_chained_handler_and_data(irq, 760 ks_pcie_intx_irq_handler, 761 ks_pcie); 762 } 763 764 intx_irq_domain = irq_domain_create_linear(of_fwnode_handle(intc_np), PCI_NUM_INTX, 765 &ks_pcie_intx_irq_domain_ops, NULL); 766 if (!intx_irq_domain) { 767 dev_err(dev, "Failed to add irq domain for INTX irqs\n"); 768 ret = -EINVAL; 769 goto err; 770 } 771 ks_pcie->intx_irq_domain = intx_irq_domain; 772 773 for (i = 0; i < PCI_NUM_INTX; i++) 774 ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), INTx_EN); 775 776err: 777 of_node_put(intc_np); 778 return ret; 779} 780 781static int ks_pcie_init_id(struct keystone_pcie *ks_pcie) 782{ 783 int ret; 784 unsigned int id; 785 struct regmap *devctrl_regs; 786 struct dw_pcie *pci = ks_pcie->pci; 787 struct device *dev = pci->dev; 788 struct device_node *np = dev->of_node; 789 struct of_phandle_args args; 790 unsigned int offset = 0; 791 792 devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-id"); 793 if (IS_ERR(devctrl_regs)) 794 return PTR_ERR(devctrl_regs); 795 796 /* Do not error out to maintain old DT compatibility */ 797 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-id", 1, 0, &args); 798 if (!ret) 799 offset = args.args[0]; 800 801 ret = regmap_read(devctrl_regs, offset, &id); 802 if (ret) 803 return ret; 804 805 dw_pcie_dbi_ro_wr_en(pci); 806 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, id & PCIE_VENDORID_MASK); 807 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, id >> PCIE_DEVICEID_SHIFT); 808 dw_pcie_dbi_ro_wr_dis(pci); 809 810 return 0; 811} 812 813static int ks_pcie_host_init(struct dw_pcie_rp *pp) 814{ 815 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 816 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 817 int ret; 818 819 pp->bridge->ops = &ks_pcie_ops; 820 if (!ks_pcie->is_am6) 821 pp->bridge->child_ops = &ks_child_pcie_ops; 822 823 ret = ks_pcie_config_intx_irq(ks_pcie); 824 if (ret) 825 return ret; 826 827 ret = ks_pcie_config_msi_irq(ks_pcie); 828 if (ret) 829 return ret; 830 831 ks_pcie_stop_link(pci); 832 ret = ks_pcie_setup_rc_app_regs(ks_pcie); 833 if (ret) 834 return ret; 835 836 writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), 837 pci->dbi_base + PCI_IO_BASE); 838 839 ret = ks_pcie_init_id(ks_pcie); 840 if (ret < 0) 841 return ret; 842 843 return 0; 844} 845 846static const struct dw_pcie_host_ops ks_pcie_host_ops = { 847 .init = ks_pcie_host_init, 848 .msi_init = ks_pcie_msi_host_init, 849}; 850 851static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = { 852 .init = ks_pcie_host_init, 853}; 854 855static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv) 856{ 857 struct keystone_pcie *ks_pcie = priv; 858 859 return ks_pcie_handle_error_irq(ks_pcie); 860} 861 862static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base, 863 u32 reg, size_t size, u32 val) 864{ 865 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 866 867 ks_pcie_set_dbi_mode(ks_pcie); 868 dw_pcie_write(base + reg, size, val); 869 ks_pcie_clear_dbi_mode(ks_pcie); 870} 871 872static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { 873 .start_link = ks_pcie_start_link, 874 .stop_link = ks_pcie_stop_link, 875 .link_up = ks_pcie_link_up, 876 .write_dbi2 = ks_pcie_am654_write_dbi2, 877}; 878 879static void ks_pcie_am654_ep_init(struct dw_pcie_ep *ep) 880{ 881 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 882 int flags; 883 884 ep->page_size = AM654_WIN_SIZE; 885 flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32; 886 dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1); 887 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags); 888} 889 890static void ks_pcie_am654_raise_intx_irq(struct keystone_pcie *ks_pcie) 891{ 892 struct dw_pcie *pci = ks_pcie->pci; 893 u8 int_pin; 894 895 int_pin = dw_pcie_readb_dbi(pci, PCI_INTERRUPT_PIN); 896 if (int_pin == 0 || int_pin > 4) 897 return; 898 899 ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_SET(int_pin), 900 INT_ENABLE); 901 ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_SET, INT_ENABLE); 902 mdelay(1); 903 ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_CLR, INT_ENABLE); 904 ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_CLR(int_pin), 905 INT_ENABLE); 906} 907 908static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 909 unsigned int type, u16 interrupt_num) 910{ 911 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 912 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 913 914 switch (type) { 915 case PCI_IRQ_INTX: 916 ks_pcie_am654_raise_intx_irq(ks_pcie); 917 break; 918 case PCI_IRQ_MSI: 919 dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 920 break; 921 case PCI_IRQ_MSIX: 922 dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); 923 break; 924 default: 925 dev_err(pci->dev, "UNKNOWN IRQ type\n"); 926 return -EINVAL; 927 } 928 929 return 0; 930} 931 932static const struct pci_epc_features ks_pcie_am654_epc_features = { 933 DWC_EPC_COMMON_FEATURES, 934 .msi_capable = true, 935 .msix_capable = true, 936 .bar[BAR_0] = { .type = BAR_RESERVED, }, 937 .bar[BAR_1] = { .type = BAR_RESERVED, }, 938 .bar[BAR_2] = { .type = BAR_RESIZABLE, }, 939 .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_64K, }, 940 .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256, }, 941 .bar[BAR_5] = { .type = BAR_RESIZABLE, }, 942 .align = SZ_64K, 943}; 944 945static const struct pci_epc_features* 946ks_pcie_am654_get_features(struct dw_pcie_ep *ep) 947{ 948 return &ks_pcie_am654_epc_features; 949} 950 951static const struct dw_pcie_ep_ops ks_pcie_am654_ep_ops = { 952 .init = ks_pcie_am654_ep_init, 953 .raise_irq = ks_pcie_am654_raise_irq, 954 .get_features = &ks_pcie_am654_get_features, 955}; 956 957static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie) 958{ 959 int num_lanes = ks_pcie->num_lanes; 960 961 while (num_lanes--) { 962 phy_power_off(ks_pcie->phy[num_lanes]); 963 phy_exit(ks_pcie->phy[num_lanes]); 964 } 965} 966 967static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) 968{ 969 int i; 970 int ret; 971 int num_lanes = ks_pcie->num_lanes; 972 973 for (i = 0; i < num_lanes; i++) { 974 ret = phy_reset(ks_pcie->phy[i]); 975 if (ret < 0) 976 goto err_phy; 977 978 ret = phy_init(ks_pcie->phy[i]); 979 if (ret < 0) 980 goto err_phy; 981 982 ret = phy_power_on(ks_pcie->phy[i]); 983 if (ret < 0) { 984 phy_exit(ks_pcie->phy[i]); 985 goto err_phy; 986 } 987 } 988 989 return 0; 990 991err_phy: 992 while (--i >= 0) { 993 phy_power_off(ks_pcie->phy[i]); 994 phy_exit(ks_pcie->phy[i]); 995 } 996 997 return ret; 998} 999 1000static int ks_pcie_set_mode(struct device *dev) 1001{ 1002 struct device_node *np = dev->of_node; 1003 struct of_phandle_args args; 1004 unsigned int offset = 0; 1005 struct regmap *syscon; 1006 u32 val; 1007 u32 mask; 1008 int ret = 0; 1009 1010 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); 1011 if (IS_ERR(syscon)) 1012 return 0; 1013 1014 /* Do not error out to maintain old DT compatibility */ 1015 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args); 1016 if (!ret) 1017 offset = args.args[0]; 1018 1019 mask = KS_PCIE_DEV_TYPE_MASK | KS_PCIE_SYSCLOCKOUTEN; 1020 val = KS_PCIE_DEV_TYPE(RC) | KS_PCIE_SYSCLOCKOUTEN; 1021 1022 ret = regmap_update_bits(syscon, offset, mask, val); 1023 if (ret) { 1024 dev_err(dev, "failed to set pcie mode\n"); 1025 return ret; 1026 } 1027 1028 return 0; 1029} 1030 1031static int ks_pcie_am654_set_mode(struct device *dev, 1032 enum dw_pcie_device_mode mode) 1033{ 1034 struct device_node *np = dev->of_node; 1035 struct of_phandle_args args; 1036 unsigned int offset = 0; 1037 struct regmap *syscon; 1038 u32 val; 1039 u32 mask; 1040 int ret = 0; 1041 1042 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); 1043 if (IS_ERR(syscon)) 1044 return 0; 1045 1046 /* Do not error out to maintain old DT compatibility */ 1047 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args); 1048 if (!ret) 1049 offset = args.args[0]; 1050 1051 mask = AM654_PCIE_DEV_TYPE_MASK; 1052 1053 switch (mode) { 1054 case DW_PCIE_RC_TYPE: 1055 val = RC; 1056 break; 1057 case DW_PCIE_EP_TYPE: 1058 val = EP; 1059 break; 1060 default: 1061 dev_err(dev, "INVALID device type %d\n", mode); 1062 return -EINVAL; 1063 } 1064 1065 ret = regmap_update_bits(syscon, offset, mask, val); 1066 if (ret) { 1067 dev_err(dev, "failed to set pcie mode\n"); 1068 return ret; 1069 } 1070 1071 return 0; 1072} 1073 1074static const struct ks_pcie_of_data ks_pcie_rc_of_data = { 1075 .host_ops = &ks_pcie_host_ops, 1076 .mode = DW_PCIE_RC_TYPE, 1077 .version = DW_PCIE_VER_365A, 1078}; 1079 1080static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = { 1081 .host_ops = &ks_pcie_am654_host_ops, 1082 .mode = DW_PCIE_RC_TYPE, 1083 .version = DW_PCIE_VER_490A, 1084}; 1085 1086static const struct ks_pcie_of_data ks_pcie_am654_ep_of_data = { 1087 .ep_ops = &ks_pcie_am654_ep_ops, 1088 .mode = DW_PCIE_EP_TYPE, 1089 .version = DW_PCIE_VER_490A, 1090}; 1091 1092static const struct of_device_id ks_pcie_of_match[] = { 1093 { 1094 .type = "pci", 1095 .data = &ks_pcie_rc_of_data, 1096 .compatible = "ti,keystone-pcie", 1097 }, 1098 { 1099 .data = &ks_pcie_am654_rc_of_data, 1100 .compatible = "ti,am654-pcie-rc", 1101 }, 1102 { 1103 .data = &ks_pcie_am654_ep_of_data, 1104 .compatible = "ti,am654-pcie-ep", 1105 }, 1106 { }, 1107}; 1108MODULE_DEVICE_TABLE(of, ks_pcie_of_match); 1109 1110static int ks_pcie_probe(struct platform_device *pdev) 1111{ 1112 const struct dw_pcie_host_ops *host_ops; 1113 const struct dw_pcie_ep_ops *ep_ops; 1114 struct device *dev = &pdev->dev; 1115 struct device_node *np = dev->of_node; 1116 const struct ks_pcie_of_data *data; 1117 enum dw_pcie_device_mode mode; 1118 struct dw_pcie *pci; 1119 struct keystone_pcie *ks_pcie; 1120 struct device_link **link; 1121 struct gpio_desc *gpiod; 1122 struct resource *res; 1123 void __iomem *base; 1124 u32 num_viewport; 1125 struct phy **phy; 1126 u32 num_lanes; 1127 char name[10]; 1128 u32 version; 1129 int ret; 1130 int irq; 1131 int i; 1132 1133 data = of_device_get_match_data(dev); 1134 if (!data) 1135 return -EINVAL; 1136 1137 version = data->version; 1138 host_ops = data->host_ops; 1139 ep_ops = data->ep_ops; 1140 mode = data->mode; 1141 1142 ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); 1143 if (!ks_pcie) 1144 return -ENOMEM; 1145 1146 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 1147 if (!pci) 1148 return -ENOMEM; 1149 1150 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); 1151 ks_pcie->va_app_base = devm_ioremap_resource(dev, res); 1152 if (IS_ERR(ks_pcie->va_app_base)) 1153 return PTR_ERR(ks_pcie->va_app_base); 1154 1155 ks_pcie->app = *res; 1156 1157 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); 1158 base = devm_pci_remap_cfg_resource(dev, res); 1159 if (IS_ERR(base)) 1160 return PTR_ERR(base); 1161 1162 if (of_device_is_compatible(np, "ti,am654-pcie-rc")) 1163 ks_pcie->is_am6 = true; 1164 1165 pci->dbi_base = base; 1166 pci->dbi_base2 = base; 1167 pci->dev = dev; 1168 pci->ops = &ks_pcie_dw_pcie_ops; 1169 pci->version = version; 1170 1171 irq = platform_get_irq(pdev, 0); 1172 if (irq < 0) 1173 return irq; 1174 1175 ret = devm_request_irq(dev, irq, ks_pcie_err_irq_handler, IRQF_SHARED, 1176 "ks-pcie-error-irq", ks_pcie); 1177 if (ret < 0) { 1178 dev_err(dev, "failed to request error IRQ %d\n", 1179 irq); 1180 return ret; 1181 } 1182 1183 ret = of_property_read_u32(np, "num-lanes", &num_lanes); 1184 if (ret) 1185 num_lanes = 1; 1186 1187 phy = devm_kcalloc(dev, num_lanes, sizeof(*phy), GFP_KERNEL); 1188 if (!phy) 1189 return -ENOMEM; 1190 1191 link = devm_kcalloc(dev, num_lanes, sizeof(*link), GFP_KERNEL); 1192 if (!link) 1193 return -ENOMEM; 1194 1195 for (i = 0; i < num_lanes; i++) { 1196 snprintf(name, sizeof(name), "pcie-phy%d", i); 1197 phy[i] = devm_phy_optional_get(dev, name); 1198 if (IS_ERR(phy[i])) { 1199 ret = PTR_ERR(phy[i]); 1200 goto err_link; 1201 } 1202 1203 if (!phy[i]) 1204 continue; 1205 1206 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); 1207 if (!link[i]) { 1208 ret = -EINVAL; 1209 goto err_link; 1210 } 1211 } 1212 1213 ks_pcie->np = np; 1214 ks_pcie->pci = pci; 1215 ks_pcie->link = link; 1216 ks_pcie->num_lanes = num_lanes; 1217 ks_pcie->phy = phy; 1218 1219 gpiod = devm_gpiod_get_optional(dev, "reset", 1220 GPIOD_OUT_LOW); 1221 if (IS_ERR(gpiod)) { 1222 ret = PTR_ERR(gpiod); 1223 if (ret != -EPROBE_DEFER) 1224 dev_err(dev, "Failed to get reset GPIO\n"); 1225 goto err_link; 1226 } 1227 1228 /* Obtain references to the PHYs */ 1229 for (i = 0; i < num_lanes; i++) 1230 phy_pm_runtime_get_sync(ks_pcie->phy[i]); 1231 1232 ret = ks_pcie_enable_phy(ks_pcie); 1233 1234 /* Release references to the PHYs */ 1235 for (i = 0; i < num_lanes; i++) 1236 phy_pm_runtime_put_sync(ks_pcie->phy[i]); 1237 1238 if (ret) { 1239 dev_err(dev, "failed to enable phy\n"); 1240 goto err_link; 1241 } 1242 1243 platform_set_drvdata(pdev, ks_pcie); 1244 pm_runtime_enable(dev); 1245 ret = pm_runtime_get_sync(dev); 1246 if (ret < 0) { 1247 dev_err(dev, "pm_runtime_get_sync failed\n"); 1248 goto err_get_sync; 1249 } 1250 1251 if (dw_pcie_ver_is_ge(pci, 480A)) 1252 ret = ks_pcie_am654_set_mode(dev, mode); 1253 else 1254 ret = ks_pcie_set_mode(dev); 1255 if (ret < 0) 1256 goto err_get_sync; 1257 1258 switch (mode) { 1259 case DW_PCIE_RC_TYPE: 1260 if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) { 1261 ret = -ENODEV; 1262 goto err_get_sync; 1263 } 1264 1265 ret = of_property_read_u32(np, "num-viewport", &num_viewport); 1266 if (ret < 0) { 1267 dev_err(dev, "unable to read *num-viewport* property\n"); 1268 goto err_get_sync; 1269 } 1270 1271 /* 1272 * "Power Sequencing and Reset Signal Timings" table in 1273 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0 1274 * indicates PERST# should be deasserted after minimum of 100us 1275 * once REFCLK is stable. The REFCLK to the connector in RC 1276 * mode is selected while enabling the PHY. So deassert PERST# 1277 * after 100 us. 1278 */ 1279 if (gpiod) { 1280 usleep_range(100, 200); 1281 gpiod_set_value_cansleep(gpiod, 1); 1282 } 1283 1284 ks_pcie->num_viewport = num_viewport; 1285 pci->pp.ops = host_ops; 1286 ret = dw_pcie_host_init(&pci->pp); 1287 if (ret < 0) 1288 goto err_get_sync; 1289 break; 1290 case DW_PCIE_EP_TYPE: 1291 if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_EP)) { 1292 ret = -ENODEV; 1293 goto err_get_sync; 1294 } 1295 1296 pci->ep.ops = ep_ops; 1297 ret = dw_pcie_ep_init(&pci->ep); 1298 if (ret < 0) 1299 goto err_get_sync; 1300 1301 ret = dw_pcie_ep_init_registers(&pci->ep); 1302 if (ret) { 1303 dev_err(dev, "Failed to initialize DWC endpoint registers\n"); 1304 goto err_ep_init; 1305 } 1306 1307 pci_epc_init_notify(pci->ep.epc); 1308 1309 break; 1310 default: 1311 dev_err(dev, "INVALID device type %d\n", mode); 1312 ret = -EINVAL; 1313 goto err_get_sync; 1314 } 1315 1316 ks_pcie_enable_error_irq(ks_pcie); 1317 1318 return 0; 1319 1320err_ep_init: 1321 dw_pcie_ep_deinit(&pci->ep); 1322err_get_sync: 1323 pm_runtime_put(dev); 1324 pm_runtime_disable(dev); 1325 ks_pcie_disable_phy(ks_pcie); 1326 1327err_link: 1328 while (--i >= 0 && link[i]) 1329 device_link_del(link[i]); 1330 1331 return ret; 1332} 1333 1334static void ks_pcie_remove(struct platform_device *pdev) 1335{ 1336 struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev); 1337 struct device_link **link = ks_pcie->link; 1338 int num_lanes = ks_pcie->num_lanes; 1339 struct device *dev = &pdev->dev; 1340 1341 pm_runtime_put(dev); 1342 pm_runtime_disable(dev); 1343 ks_pcie_disable_phy(ks_pcie); 1344 while (num_lanes--) 1345 device_link_del(link[num_lanes]); 1346} 1347 1348static struct platform_driver ks_pcie_driver = { 1349 .probe = ks_pcie_probe, 1350 .remove = ks_pcie_remove, 1351 .driver = { 1352 .name = "keystone-pcie", 1353 .of_match_table = ks_pcie_of_match, 1354 }, 1355}; 1356 1357#ifdef CONFIG_ARM 1358/* 1359 * When a PCI device does not exist during config cycles, keystone host 1360 * gets a bus error instead of returning 0xffffffff (PCI_ERROR_RESPONSE). 1361 * This handler always returns 0 for this kind of fault. 1362 */ 1363static int ks_pcie_fault(unsigned long addr, unsigned int fsr, 1364 struct pt_regs *regs) 1365{ 1366 unsigned long instr = *(unsigned long *)instruction_pointer(regs); 1367 1368 if ((instr & 0x0e100090) == 0x00100090) { 1369 int reg = (instr >> 12) & 15; 1370 1371 regs->uregs[reg] = -1; 1372 regs->ARM_pc += 4; 1373 } 1374 1375 return 0; 1376} 1377 1378static int __init ks_pcie_init(void) 1379{ 1380 /* 1381 * PCIe access errors that result into OCP errors are caught by ARM as 1382 * "External aborts" 1383 */ 1384 if (of_find_matching_node(NULL, ks_pcie_of_match)) 1385 hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, 1386 "Asynchronous external abort"); 1387 1388 return platform_driver_register(&ks_pcie_driver); 1389} 1390device_initcall(ks_pcie_init); 1391#else 1392builtin_platform_driver(ks_pcie_driver); 1393#endif 1394 1395MODULE_LICENSE("GPL"); 1396MODULE_DESCRIPTION("PCIe controller driver for Texas Instruments Keystone SoCs"); 1397MODULE_AUTHOR("Murali Karicheri <m-karicheri2@ti.com>");
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