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sba_iommu.c
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linux-6.19.14/drivers/parisc/sba_iommu.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3** System Bus Adapter (SBA) I/O MMU manager 4** 5** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org> 6** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com> 7** (c) Copyright 2000-2004 Hewlett-Packard Company 8** 9** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code) 10** 11** 12** 13** This module initializes the IOC (I/O Controller) found on B1000/C3000/ 14** J5000/J7000/N-class/L-class machines and their successors. 15** 16** FIXME: add DMA hint support programming in both sba and lba modules. 17*/ 18 19#include <linux/types.h> 20#include <linux/kernel.h> 21#include <linux/spinlock.h> 22#include <linux/slab.h> 23#include <linux/init.h> 24 25#include <linux/mm.h> 26#include <linux/string.h> 27#include <linux/pci.h> 28#include <linux/dma-map-ops.h> 29#include <linux/scatterlist.h> 30#include <linux/iommu-helper.h> 31/* 32 * The semantics of 64 register access on 32bit systems can't be guaranteed 33 * by the C standard, we hope the _lo_hi() macros defining readq and writeq 34 * here will behave as expected. 35 */ 36#include <linux/io-64-nonatomic-lo-hi.h> 37 38#include <asm/byteorder.h> 39#include <asm/io.h> 40#include <asm/dma.h> /* for DMA_CHUNK_SIZE */ 41 42#include <asm/hardware.h> /* for register_parisc_driver() stuff */ 43 44#include <linux/proc_fs.h> 45#include <linux/seq_file.h> 46#include <linux/module.h> 47 48#include <asm/ropes.h> 49#include <asm/page.h> /* for PAGE0 */ 50#include <asm/pdc.h> /* for PDC_MODEL_* */ 51#include <asm/pdcpat.h> /* for is_pdc_pat() */ 52#include <asm/parisc-device.h> 53 54#include "iommu.h" 55 56#define MODULE_NAME "SBA" 57 58/* 59** The number of debug flags is a clue - this code is fragile. 60** Don't even think about messing with it unless you have 61** plenty of 710's to sacrifice to the computer gods. :^) 62*/ 63#undef DEBUG_SBA_INIT 64#undef DEBUG_SBA_RUN 65#undef DEBUG_SBA_RUN_SG 66#undef DEBUG_SBA_RESOURCE 67#undef ASSERT_PDIR_SANITY 68#undef DEBUG_LARGE_SG_ENTRIES 69#undef DEBUG_DMB_TRAP 70 71#ifdef DEBUG_SBA_INIT 72#define DBG_INIT(x...) printk(x) 73#else 74#define DBG_INIT(x...) 75#endif 76 77#ifdef DEBUG_SBA_RUN 78#define DBG_RUN(x...) printk(x) 79#else 80#define DBG_RUN(x...) 81#endif 82 83#ifdef DEBUG_SBA_RUN_SG 84#define DBG_RUN_SG(x...) printk(x) 85#else 86#define DBG_RUN_SG(x...) 87#endif 88 89 90#ifdef DEBUG_SBA_RESOURCE 91#define DBG_RES(x...) printk(x) 92#else 93#define DBG_RES(x...) 94#endif 95 96#define DEFAULT_DMA_HINT_REG 0 97 98struct sba_device *sba_list; 99EXPORT_SYMBOL_GPL(sba_list); 100 101static unsigned long ioc_needs_fdc = 0; 102 103/* global count of IOMMUs in the system */ 104static unsigned int global_ioc_cnt = 0; 105 106/* PA8700 (Piranha 2.2) bug workaround */ 107static unsigned long piranha_bad_128k = 0; 108 109/* Looks nice and keeps the compiler happy */ 110#define SBA_DEV(d) ((struct sba_device *) (d)) 111 112#ifdef CONFIG_AGP_PARISC 113#define SBA_AGP_SUPPORT 114#endif /*CONFIG_AGP_PARISC*/ 115 116#ifdef SBA_AGP_SUPPORT 117static int sba_reserve_agpgart = 1; 118module_param(sba_reserve_agpgart, int, 0444); 119MODULE_PARM_DESC(sba_reserve_agpgart, "Reserve half of IO pdir as AGPGART"); 120#endif 121 122static struct proc_dir_entry *proc_runway_root __ro_after_init; 123static struct proc_dir_entry *proc_mckinley_root __ro_after_init; 124 125/************************************ 126** SBA register read and write support 127** 128** BE WARNED: register writes are posted. 129** (ie follow writes which must reach HW with a read) 130** 131** Superdome (in particular, REO) allows only 64-bit CSR accesses. 132*/ 133#define READ_REG32(addr) readl(addr) 134#define READ_REG64(addr) readq(addr) 135#define WRITE_REG32(val, addr) writel((val), (addr)) 136#define WRITE_REG64(val, addr) writeq((val), (addr)) 137 138#ifdef CONFIG_64BIT 139#define READ_REG(addr) READ_REG64(addr) 140#define WRITE_REG(value, addr) WRITE_REG64(value, addr) 141#else 142#define READ_REG(addr) READ_REG32(addr) 143#define WRITE_REG(value, addr) WRITE_REG32(value, addr) 144#endif 145 146#ifdef DEBUG_SBA_INIT 147 148/* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */ 149 150/** 151 * sba_dump_ranges - debugging only - print ranges assigned to this IOA 152 * @hpa: base address of the sba 153 * 154 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO 155 * IO Adapter (aka Bus Converter). 156 */ 157static void 158sba_dump_ranges(void __iomem *hpa) 159{ 160 DBG_INIT("SBA at 0x%p\n", hpa); 161 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE)); 162 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK)); 163 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE)); 164 DBG_INIT("\n"); 165 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE)); 166 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK)); 167 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE)); 168} 169 170/** 171 * sba_dump_tlb - debugging only - print IOMMU operating parameters 172 * @hpa: base address of the IOMMU 173 * 174 * Print the size/location of the IO MMU PDIR. 175 */ 176static void sba_dump_tlb(void __iomem *hpa) 177{ 178 DBG_INIT("IO TLB at 0x%p\n", hpa); 179 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE)); 180 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK)); 181 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG)); 182 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE)); 183 DBG_INIT("\n"); 184} 185#else 186#define sba_dump_ranges(x) 187#define sba_dump_tlb(x) 188#endif /* DEBUG_SBA_INIT */ 189 190 191#ifdef ASSERT_PDIR_SANITY 192 193/** 194 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry 195 * @ioc: IO MMU structure which owns the pdir we are interested in. 196 * @msg: text to print ont the output line. 197 * @pide: pdir index. 198 * 199 * Print one entry of the IO MMU PDIR in human readable form. 200 */ 201static void 202sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide) 203{ 204 /* start printing from lowest pde in rval */ 205 __le64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]); 206 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]); 207 uint rcnt; 208 209 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n", 210 msg, 211 rptr, pide & (BITS_PER_LONG - 1), *rptr); 212 213 rcnt = 0; 214 while (rcnt < BITS_PER_LONG) { 215 printk(KERN_DEBUG "%s %2d %p %016Lx\n", 216 (rcnt == (pide & (BITS_PER_LONG - 1))) 217 ? " -->" : " ", 218 rcnt, ptr, *ptr ); 219 rcnt++; 220 ptr++; 221 } 222 printk(KERN_DEBUG "%s", msg); 223} 224 225 226/** 227 * sba_check_pdir - debugging only - consistency checker 228 * @ioc: IO MMU structure which owns the pdir we are interested in. 229 * @msg: text to print ont the output line. 230 * 231 * Verify the resource map and pdir state is consistent 232 */ 233static int 234sba_check_pdir(struct ioc *ioc, char *msg) 235{ 236 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]); 237 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */ 238 u64 *pptr = ioc->pdir_base; /* pdir ptr */ 239 uint pide = 0; 240 241 while (rptr < rptr_end) { 242 u32 rval = *rptr; 243 int rcnt = 32; /* number of bits we might check */ 244 245 while (rcnt) { 246 /* Get last byte and highest bit from that */ 247 u32 pde = ((u32) (((char *)pptr)[7])) << 24; 248 if ((rval ^ pde) & 0x80000000) 249 { 250 /* 251 ** BUMMER! -- res_map != pdir -- 252 ** Dump rval and matching pdir entries 253 */ 254 sba_dump_pdir_entry(ioc, msg, pide); 255 return(1); 256 } 257 rcnt--; 258 rval <<= 1; /* try the next bit */ 259 pptr++; 260 pide++; 261 } 262 rptr++; /* look at next word of res_map */ 263 } 264 /* It'd be nice if we always got here :^) */ 265 return 0; 266} 267 268 269/** 270 * sba_dump_sg - debugging only - print Scatter-Gather list 271 * @ioc: IO MMU structure which owns the pdir we are interested in. 272 * @startsg: head of the SG list 273 * @nents: number of entries in SG list 274 * 275 * print the SG list so we can verify it's correct by hand. 276 */ 277static void 278sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents) 279{ 280 while (nents-- > 0) { 281 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n", 282 nents, 283 (unsigned long) sg_dma_address(startsg), 284 sg_dma_len(startsg), 285 sg_virt(startsg), startsg->length); 286 startsg++; 287 } 288} 289 290#endif /* ASSERT_PDIR_SANITY */ 291 292 293 294 295/************************************************************** 296* 297* I/O Pdir Resource Management 298* 299* Bits set in the resource map are in use. 300* Each bit can represent a number of pages. 301* LSbs represent lower addresses (IOVA's). 302* 303***************************************************************/ 304#define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */ 305 306/* Convert from IOVP to IOVA and vice versa. */ 307 308#ifdef ZX1_SUPPORT 309/* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */ 310#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset)) 311#define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask) 312#else 313/* only support Astro and ancestors. Saves a few cycles in key places */ 314#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset)) 315#define SBA_IOVP(ioc,iova) (iova) 316#endif 317 318#define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT) 319 320#define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n))) 321#define RESMAP_IDX_MASK (sizeof(unsigned long) - 1) 322 323static unsigned long ptr_to_pide(struct ioc *ioc, unsigned long *res_ptr, 324 unsigned int bitshiftcnt) 325{ 326 return (((unsigned long)res_ptr - (unsigned long)ioc->res_map) << 3) 327 + bitshiftcnt; 328} 329 330/** 331 * sba_search_bitmap - find free space in IO PDIR resource bitmap 332 * @ioc: IO MMU structure which owns the pdir we are interested in. 333 * @dev: device to query the bitmap for 334 * @bits_wanted: number of entries we need. 335 * 336 * Find consecutive free bits in resource bitmap. 337 * Each bit represents one entry in the IO Pdir. 338 * Cool perf optimization: search for log2(size) bits at a time. 339 */ 340static unsigned long 341sba_search_bitmap(struct ioc *ioc, struct device *dev, 342 unsigned long bits_wanted) 343{ 344 unsigned long *res_ptr = ioc->res_hint; 345 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]); 346 unsigned long pide = ~0UL, tpide; 347 unsigned long boundary_size; 348 unsigned long shift; 349 int ret; 350 351 boundary_size = dma_get_seg_boundary_nr_pages(dev, IOVP_SHIFT); 352 353#if defined(ZX1_SUPPORT) 354 BUG_ON(ioc->ibase & ~IOVP_MASK); 355 shift = ioc->ibase >> IOVP_SHIFT; 356#else 357 shift = 0; 358#endif 359 360 if (bits_wanted > (BITS_PER_LONG/2)) { 361 /* Search word at a time - no mask needed */ 362 for(; res_ptr < res_end; ++res_ptr) { 363 tpide = ptr_to_pide(ioc, res_ptr, 0); 364 ret = iommu_is_span_boundary(tpide, bits_wanted, 365 shift, 366 boundary_size); 367 if ((*res_ptr == 0) && !ret) { 368 *res_ptr = RESMAP_MASK(bits_wanted); 369 pide = tpide; 370 break; 371 } 372 } 373 /* point to the next word on next pass */ 374 res_ptr++; 375 ioc->res_bitshift = 0; 376 } else { 377 /* 378 ** Search the resource bit map on well-aligned values. 379 ** "o" is the alignment. 380 ** We need the alignment to invalidate I/O TLB using 381 ** SBA HW features in the unmap path. 382 */ 383 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT); 384 uint bitshiftcnt = ALIGN(ioc->res_bitshift, o); 385 unsigned long mask; 386 387 if (bitshiftcnt >= BITS_PER_LONG) { 388 bitshiftcnt = 0; 389 res_ptr++; 390 } 391 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt; 392 393 DBG_RES("%s() o %ld %p", __func__, o, res_ptr); 394 while(res_ptr < res_end) 395 { 396 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr); 397 WARN_ON(mask == 0); 398 tpide = ptr_to_pide(ioc, res_ptr, bitshiftcnt); 399 ret = iommu_is_span_boundary(tpide, bits_wanted, 400 shift, 401 boundary_size); 402 if ((((*res_ptr) & mask) == 0) && !ret) { 403 *res_ptr |= mask; /* mark resources busy! */ 404 pide = tpide; 405 break; 406 } 407 mask >>= o; 408 bitshiftcnt += o; 409 if (mask == 0) { 410 mask = RESMAP_MASK(bits_wanted); 411 bitshiftcnt=0; 412 res_ptr++; 413 } 414 } 415 /* look in the same word on the next pass */ 416 ioc->res_bitshift = bitshiftcnt + bits_wanted; 417 } 418 419 /* wrapped ? */ 420 if (res_end <= res_ptr) { 421 ioc->res_hint = (unsigned long *) ioc->res_map; 422 ioc->res_bitshift = 0; 423 } else { 424 ioc->res_hint = res_ptr; 425 } 426 return (pide); 427} 428 429 430/** 431 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap 432 * @ioc: IO MMU structure which owns the pdir we are interested in. 433 * @dev: device for which pages should be alloced 434 * @size: number of bytes to create a mapping for 435 * 436 * Given a size, find consecutive unmarked and then mark those bits in the 437 * resource bit map. 438 */ 439static int 440sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size) 441{ 442 unsigned int pages_needed = size >> IOVP_SHIFT; 443#ifdef SBA_COLLECT_STATS 444 unsigned long cr_start = mfctl(16); 445#endif 446 unsigned long pide; 447 448 pide = sba_search_bitmap(ioc, dev, pages_needed); 449 if (pide >= (ioc->res_size << 3)) { 450 pide = sba_search_bitmap(ioc, dev, pages_needed); 451 if (pide >= (ioc->res_size << 3)) 452 panic("%s: I/O MMU @ %p is out of mapping resources\n", 453 __FILE__, ioc->ioc_hpa); 454 } 455 456#ifdef ASSERT_PDIR_SANITY 457 /* verify the first enable bit is clear */ 458 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) { 459 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide); 460 } 461#endif 462 463 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n", 464 __func__, size, pages_needed, pide, 465 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map), 466 ioc->res_bitshift ); 467 468#ifdef SBA_COLLECT_STATS 469 { 470 unsigned long cr_end = mfctl(16); 471 unsigned long tmp = cr_end - cr_start; 472 /* check for roll over */ 473 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp); 474 } 475 ioc->avg_search[ioc->avg_idx++] = cr_start; 476 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1; 477 478 ioc->used_pages += pages_needed; 479#endif 480 481 return (pide); 482} 483 484 485/** 486 * sba_free_range - unmark bits in IO PDIR resource bitmap 487 * @ioc: IO MMU structure which owns the pdir we are interested in. 488 * @iova: IO virtual address which was previously allocated. 489 * @size: number of bytes to create a mapping for 490 * 491 * clear bits in the ioc's resource map 492 */ 493static void 494sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size) 495{ 496 unsigned long iovp = SBA_IOVP(ioc, iova); 497 unsigned int pide = PDIR_INDEX(iovp); 498 unsigned int ridx = pide >> 3; /* convert bit to byte address */ 499 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]); 500 501 int bits_not_wanted = size >> IOVP_SHIFT; 502 503 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */ 504 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1)); 505 506 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n", 507 __func__, (uint) iova, size, 508 bits_not_wanted, m, pide, res_ptr, *res_ptr); 509 510#ifdef SBA_COLLECT_STATS 511 ioc->used_pages -= bits_not_wanted; 512#endif 513 514 *res_ptr &= ~m; 515} 516 517 518/************************************************************** 519* 520* "Dynamic DMA Mapping" support (aka "Coherent I/O") 521* 522***************************************************************/ 523 524#ifdef SBA_HINT_SUPPORT 525#define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir) 526#endif 527 528typedef unsigned long space_t; 529#define KERNEL_SPACE 0 530 531/** 532 * sba_io_pdir_entry - fill in one IO PDIR entry 533 * @pdir_ptr: pointer to IO PDIR entry 534 * @sid: process Space ID - currently only support KERNEL_SPACE 535 * @pba: Physical address of buffer to map 536 * @hint: DMA hint set to use for this mapping 537 * 538 * SBA Mapping Routine 539 * 540 * Given a virtual address (vba, arg2) and space id, (sid, arg1) 541 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by 542 * pdir_ptr (arg0). 543 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry 544 * for Astro/Ike looks like: 545 * 546 * 547 * 0 19 51 55 63 548 * +-+---------------------+----------------------------------+----+--------+ 549 * |V| U | PPN[43:12] | U | VI | 550 * +-+---------------------+----------------------------------+----+--------+ 551 * 552 * Pluto is basically identical, supports fewer physical address bits: 553 * 554 * 0 23 51 55 63 555 * +-+------------------------+-------------------------------+----+--------+ 556 * |V| U | PPN[39:12] | U | VI | 557 * +-+------------------------+-------------------------------+----+--------+ 558 * 559 * V == Valid Bit (Most Significant Bit is bit 0) 560 * U == Unused 561 * PPN == Physical Page Number 562 * VI == Virtual Index (aka Coherent Index) 563 * 564 * LPA instruction output is put into PPN field. 565 * LCI (Load Coherence Index) instruction provides the "VI" bits. 566 * 567 * We pre-swap the bytes since PCX-W is Big Endian and the 568 * IOMMU uses little endian for the pdir. 569 */ 570 571static void 572sba_io_pdir_entry(__le64 *pdir_ptr, space_t sid, phys_addr_t pba, 573 unsigned long hint) 574{ 575 register unsigned ci; /* coherent index */ 576 577 asm("lci 0(%1), %0" : "=r" (ci) : "r" (phys_to_virt(pba))); 578 pba &= IOVP_MASK; 579 pba |= (ci >> PAGE_SHIFT) & 0xff; /* move CI (8 bits) into lowest byte */ 580 581 /* set "valid" bit, swap and store into I/O Pdir */ 582 *pdir_ptr = cpu_to_le64((unsigned long)pba | SBA_PDIR_VALID_BIT); 583 584 /* 585 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set 586 * (bit #61, big endian), we have to flush and sync every time 587 * IO-PDIR is changed in Ike/Astro. 588 */ 589 asm_io_fdc(pdir_ptr); 590} 591 592 593/** 594 * sba_mark_invalid - invalidate one or more IO PDIR entries 595 * @ioc: IO MMU structure which owns the pdir we are interested in. 596 * @iova: IO Virtual Address mapped earlier 597 * @byte_cnt: number of bytes this mapping covers. 598 * 599 * Marking the IO PDIR entry(ies) as Invalid and invalidate 600 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register) 601 * is to purge stale entries in the IO TLB when unmapping entries. 602 * 603 * The PCOM register supports purging of multiple pages, with a minium 604 * of 1 page and a maximum of 2GB. Hardware requires the address be 605 * aligned to the size of the range being purged. The size of the range 606 * must be a power of 2. The "Cool perf optimization" in the 607 * allocation routine helps keep that true. 608 */ 609static void 610sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt) 611{ 612 u32 iovp = (u32) SBA_IOVP(ioc,iova); 613 __le64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)]; 614 615#ifdef ASSERT_PDIR_SANITY 616 /* Assert first pdir entry is set. 617 ** 618 ** Even though this is a big-endian machine, the entries 619 ** in the iopdir are little endian. That's why we look at 620 ** the byte at +7 instead of at +0. 621 */ 622 if (0x80 != (((u8 *) pdir_ptr)[7])) { 623 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp)); 624 } 625#endif 626 627 if (byte_cnt > IOVP_SIZE) 628 { 629#if 0 630 unsigned long entries_per_cacheline = ioc_needs_fdc ? 631 L1_CACHE_ALIGN(((unsigned long) pdir_ptr)) 632 - (unsigned long) pdir_ptr; 633 : 262144; 634#endif 635 636 /* set "size" field for PCOM */ 637 iovp |= get_order(byte_cnt) + PAGE_SHIFT; 638 639 do { 640 /* clear I/O Pdir entry "valid" bit first */ 641 ((u8 *) pdir_ptr)[7] = 0; 642 asm_io_fdc(pdir_ptr); 643 if (ioc_needs_fdc) { 644#if 0 645 entries_per_cacheline = L1_CACHE_SHIFT - 3; 646#endif 647 } 648 pdir_ptr++; 649 byte_cnt -= IOVP_SIZE; 650 } while (byte_cnt > IOVP_SIZE); 651 } else 652 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */ 653 654 /* 655 ** clear I/O PDIR entry "valid" bit. 656 ** We have to R/M/W the cacheline regardless how much of the 657 ** pdir entry that we clobber. 658 ** The rest of the entry would be useful for debugging if we 659 ** could dump core on HPMC. 660 */ 661 ((u8 *) pdir_ptr)[7] = 0; 662 asm_io_fdc(pdir_ptr); 663 664 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM); 665} 666 667/** 668 * sba_dma_supported - PCI driver can query DMA support 669 * @dev: instance of PCI owned by the driver that's asking 670 * @mask: number of address bits this PCI device can handle 671 * 672 * See Documentation/core-api/dma-api-howto.rst 673 */ 674static int sba_dma_supported( struct device *dev, u64 mask) 675{ 676 struct ioc *ioc; 677 678 if (dev == NULL) { 679 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n"); 680 BUG(); 681 return(0); 682 } 683 684 ioc = GET_IOC(dev); 685 if (!ioc) 686 return 0; 687 688 /* 689 * check if mask is >= than the current max IO Virt Address 690 * The max IO Virt address will *always* < 30 bits. 691 */ 692 return((int)(mask >= (ioc->ibase - 1 + 693 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) ))); 694} 695 696 697/** 698 * sba_map_single - map one buffer and return IOVA for DMA 699 * @dev: instance of PCI owned by the driver that's asking. 700 * @addr: driver buffer to map. 701 * @size: number of bytes to map in driver buffer. 702 * @direction: R/W or both. 703 * 704 * See Documentation/core-api/dma-api-howto.rst 705 */ 706static dma_addr_t 707sba_map_single(struct device *dev, phys_addr_t addr, size_t size, 708 enum dma_data_direction direction) 709{ 710 struct ioc *ioc; 711 unsigned long flags; 712 dma_addr_t iovp; 713 dma_addr_t offset; 714 __le64 *pdir_start; 715 int pide; 716 717 ioc = GET_IOC(dev); 718 if (!ioc) 719 return DMA_MAPPING_ERROR; 720 721 /* save offset bits */ 722 offset = offset_in_page(addr); 723 724 /* round up to nearest IOVP_SIZE */ 725 size = (size + offset + ~IOVP_MASK) & IOVP_MASK; 726 727 spin_lock_irqsave(&ioc->res_lock, flags); 728#ifdef ASSERT_PDIR_SANITY 729 sba_check_pdir(ioc,"Check before sba_map_single()"); 730#endif 731 732#ifdef SBA_COLLECT_STATS 733 ioc->msingle_calls++; 734 ioc->msingle_pages += size >> IOVP_SHIFT; 735#endif 736 pide = sba_alloc_range(ioc, dev, size); 737 iovp = (dma_addr_t) pide << IOVP_SHIFT; 738 739 DBG_RUN("%s() 0x%pa -> 0x%lx\n", 740 __func__, &addr, (long) iovp | offset); 741 742 pdir_start = &(ioc->pdir_base[pide]); 743 744 while (size > 0) { 745 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, addr, 0); 746 747 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n", 748 pdir_start, 749 (u8) (((u8 *) pdir_start)[7]), 750 (u8) (((u8 *) pdir_start)[6]), 751 (u8) (((u8 *) pdir_start)[5]), 752 (u8) (((u8 *) pdir_start)[4]), 753 (u8) (((u8 *) pdir_start)[3]), 754 (u8) (((u8 *) pdir_start)[2]), 755 (u8) (((u8 *) pdir_start)[1]), 756 (u8) (((u8 *) pdir_start)[0]) 757 ); 758 759 addr += IOVP_SIZE; 760 size -= IOVP_SIZE; 761 pdir_start++; 762 } 763 764 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */ 765 asm_io_sync(); 766 767#ifdef ASSERT_PDIR_SANITY 768 sba_check_pdir(ioc,"Check after sba_map_single()"); 769#endif 770 spin_unlock_irqrestore(&ioc->res_lock, flags); 771 772 /* form complete address */ 773 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG); 774} 775 776 777static dma_addr_t 778sba_map_phys(struct device *dev, phys_addr_t phys, size_t size, 779 enum dma_data_direction direction, unsigned long attrs) 780{ 781 if (unlikely(attrs & DMA_ATTR_MMIO)) 782 return DMA_MAPPING_ERROR; 783 784 return sba_map_single(dev, phys, size, direction); 785} 786 787 788/** 789 * sba_unmap_phys - unmap one IOVA and free resources 790 * @dev: instance of PCI owned by the driver that's asking. 791 * @iova: IOVA of driver buffer previously mapped. 792 * @size: number of bytes mapped in driver buffer. 793 * @direction: R/W or both. 794 * @attrs: attributes 795 * 796 * See Documentation/core-api/dma-api-howto.rst 797 */ 798static void 799sba_unmap_phys(struct device *dev, dma_addr_t iova, size_t size, 800 enum dma_data_direction direction, unsigned long attrs) 801{ 802 struct ioc *ioc; 803#if DELAYED_RESOURCE_CNT > 0 804 struct sba_dma_pair *d; 805#endif 806 unsigned long flags; 807 dma_addr_t offset; 808 809 DBG_RUN("%s() iovp 0x%lx/%x\n", __func__, (long) iova, size); 810 811 ioc = GET_IOC(dev); 812 if (!ioc) { 813 WARN_ON(!ioc); 814 return; 815 } 816 offset = iova & ~IOVP_MASK; 817 iova ^= offset; /* clear offset bits */ 818 size += offset; 819 size = ALIGN(size, IOVP_SIZE); 820 821 spin_lock_irqsave(&ioc->res_lock, flags); 822 823#ifdef SBA_COLLECT_STATS 824 ioc->usingle_calls++; 825 ioc->usingle_pages += size >> IOVP_SHIFT; 826#endif 827 828 sba_mark_invalid(ioc, iova, size); 829 830#if DELAYED_RESOURCE_CNT > 0 831 /* Delaying when we re-use a IO Pdir entry reduces the number 832 * of MMIO reads needed to flush writes to the PCOM register. 833 */ 834 d = &(ioc->saved[ioc->saved_cnt]); 835 d->iova = iova; 836 d->size = size; 837 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) { 838 int cnt = ioc->saved_cnt; 839 while (cnt--) { 840 sba_free_range(ioc, d->iova, d->size); 841 d--; 842 } 843 ioc->saved_cnt = 0; 844 845 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ 846 } 847#else /* DELAYED_RESOURCE_CNT == 0 */ 848 sba_free_range(ioc, iova, size); 849 850 /* If fdc's were issued, force fdc's to be visible now */ 851 asm_io_sync(); 852 853 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ 854#endif /* DELAYED_RESOURCE_CNT == 0 */ 855 856 spin_unlock_irqrestore(&ioc->res_lock, flags); 857 858 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support. 859 ** For Astro based systems this isn't a big deal WRT performance. 860 ** As long as 2.4 kernels copyin/copyout data from/to userspace, 861 ** we don't need the syncdma. The issue here is I/O MMU cachelines 862 ** are *not* coherent in all cases. May be hwrev dependent. 863 ** Need to investigate more. 864 asm volatile("syncdma"); 865 */ 866} 867 868 869/** 870 * sba_alloc - allocate/map shared mem for DMA 871 * @hwdev: instance of PCI owned by the driver that's asking. 872 * @size: number of bytes mapped in driver buffer. 873 * @dma_handle: IOVA of new buffer. 874 * @gfp: allocation flags 875 * @attrs: attributes 876 * 877 * See Documentation/core-api/dma-api-howto.rst 878 */ 879static void *sba_alloc(struct device *hwdev, size_t size, dma_addr_t *dma_handle, 880 gfp_t gfp, unsigned long attrs) 881{ 882 void *ret; 883 884 if (!hwdev) { 885 /* only support PCI */ 886 *dma_handle = 0; 887 return NULL; 888 } 889 890 ret = (void *) __get_free_pages(gfp, get_order(size)); 891 892 if (ret) { 893 memset(ret, 0, size); 894 *dma_handle = sba_map_single(hwdev, virt_to_phys(ret), size, 0); 895 } 896 897 return ret; 898} 899 900 901/** 902 * sba_free - free/unmap shared mem for DMA 903 * @hwdev: instance of PCI owned by the driver that's asking. 904 * @size: number of bytes mapped in driver buffer. 905 * @vaddr: virtual address IOVA of "consistent" buffer. 906 * @dma_handle: IO virtual address of "consistent" buffer. 907 * @attrs: attributes 908 * 909 * See Documentation/core-api/dma-api-howto.rst 910 */ 911static void 912sba_free(struct device *hwdev, size_t size, void *vaddr, 913 dma_addr_t dma_handle, unsigned long attrs) 914{ 915 sba_unmap_phys(hwdev, dma_handle, size, 0, 0); 916 free_pages((unsigned long) vaddr, get_order(size)); 917} 918 919 920/* 921** Since 0 is a valid pdir_base index value, can't use that 922** to determine if a value is valid or not. Use a flag to indicate 923** the SG list entry contains a valid pdir index. 924*/ 925#define PIDE_FLAG 0x80000000UL 926 927#ifdef SBA_COLLECT_STATS 928#define IOMMU_MAP_STATS 929#endif 930#include "iommu-helpers.h" 931 932#ifdef DEBUG_LARGE_SG_ENTRIES 933int dump_run_sg = 0; 934#endif 935 936 937/** 938 * sba_map_sg - map Scatter/Gather list 939 * @dev: instance of PCI owned by the driver that's asking. 940 * @sglist: array of buffer/length pairs 941 * @nents: number of entries in list 942 * @direction: R/W or both. 943 * @attrs: attributes 944 * 945 * See Documentation/core-api/dma-api-howto.rst 946 */ 947static int 948sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents, 949 enum dma_data_direction direction, unsigned long attrs) 950{ 951 struct ioc *ioc; 952 int filled = 0; 953 unsigned long flags; 954 955 DBG_RUN_SG("%s() START %d entries\n", __func__, nents); 956 957 ioc = GET_IOC(dev); 958 if (!ioc) 959 return -EINVAL; 960 961 /* Fast path single entry scatterlists. */ 962 if (nents == 1) { 963 sg_dma_address(sglist) = sba_map_single(dev, sg_phys(sglist), 964 sglist->length, direction); 965 sg_dma_len(sglist) = sglist->length; 966 return 1; 967 } 968 969 spin_lock_irqsave(&ioc->res_lock, flags); 970 971#ifdef ASSERT_PDIR_SANITY 972 if (sba_check_pdir(ioc,"Check before sba_map_sg()")) 973 { 974 sba_dump_sg(ioc, sglist, nents); 975 panic("Check before sba_map_sg()"); 976 } 977#endif 978 979#ifdef SBA_COLLECT_STATS 980 ioc->msg_calls++; 981#endif 982 983 /* 984 ** First coalesce the chunks and allocate I/O pdir space 985 ** 986 ** If this is one DMA stream, we can properly map using the 987 ** correct virtual address associated with each DMA page. 988 ** w/o this association, we wouldn't have coherent DMA! 989 ** Access to the virtual address is what forces a two pass algorithm. 990 */ 991 iommu_coalesce_chunks(ioc, dev, sglist, nents, sba_alloc_range); 992 993 /* 994 ** Program the I/O Pdir 995 ** 996 ** map the virtual addresses to the I/O Pdir 997 ** o dma_address will contain the pdir index 998 ** o dma_len will contain the number of bytes to map 999 ** o address contains the virtual address. 1000 */ 1001 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry); 1002 1003 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */ 1004 asm_io_sync(); 1005 1006#ifdef ASSERT_PDIR_SANITY 1007 if (sba_check_pdir(ioc,"Check after sba_map_sg()")) 1008 { 1009 sba_dump_sg(ioc, sglist, nents); 1010 panic("Check after sba_map_sg()\n"); 1011 } 1012#endif 1013 1014 spin_unlock_irqrestore(&ioc->res_lock, flags); 1015 1016 DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled); 1017 1018 return filled; 1019} 1020 1021 1022/** 1023 * sba_unmap_sg - unmap Scatter/Gather list 1024 * @dev: instance of PCI owned by the driver that's asking. 1025 * @sglist: array of buffer/length pairs 1026 * @nents: number of entries in list 1027 * @direction: R/W or both. 1028 * @attrs: attributes 1029 * 1030 * See Documentation/core-api/dma-api-howto.rst 1031 */ 1032static void 1033sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents, 1034 enum dma_data_direction direction, unsigned long attrs) 1035{ 1036 struct ioc *ioc; 1037#ifdef ASSERT_PDIR_SANITY 1038 unsigned long flags; 1039#endif 1040 1041 DBG_RUN_SG("%s() START %d entries, %p,%x\n", 1042 __func__, nents, sg_virt(sglist), sglist->length); 1043 1044 ioc = GET_IOC(dev); 1045 if (!ioc) { 1046 WARN_ON(!ioc); 1047 return; 1048 } 1049 1050#ifdef SBA_COLLECT_STATS 1051 ioc->usg_calls++; 1052#endif 1053 1054#ifdef ASSERT_PDIR_SANITY 1055 spin_lock_irqsave(&ioc->res_lock, flags); 1056 sba_check_pdir(ioc,"Check before sba_unmap_sg()"); 1057 spin_unlock_irqrestore(&ioc->res_lock, flags); 1058#endif 1059 1060 while (nents && sg_dma_len(sglist)) { 1061 1062 sba_unmap_phys(dev, sg_dma_address(sglist), sg_dma_len(sglist), 1063 direction, 0); 1064#ifdef SBA_COLLECT_STATS 1065 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT; 1066 ioc->usingle_calls--; /* kluge since call is unmap_sg() */ 1067#endif 1068 ++sglist; 1069 nents--; 1070 } 1071 1072 DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents); 1073 1074#ifdef ASSERT_PDIR_SANITY 1075 spin_lock_irqsave(&ioc->res_lock, flags); 1076 sba_check_pdir(ioc,"Check after sba_unmap_sg()"); 1077 spin_unlock_irqrestore(&ioc->res_lock, flags); 1078#endif 1079 1080} 1081 1082static const struct dma_map_ops sba_ops = { 1083 .dma_supported = sba_dma_supported, 1084 .alloc = sba_alloc, 1085 .free = sba_free, 1086 .map_phys = sba_map_phys, 1087 .unmap_phys = sba_unmap_phys, 1088 .map_sg = sba_map_sg, 1089 .unmap_sg = sba_unmap_sg, 1090 .get_sgtable = dma_common_get_sgtable, 1091 .alloc_pages_op = dma_common_alloc_pages, 1092 .free_pages = dma_common_free_pages, 1093}; 1094 1095 1096/************************************************************************** 1097** 1098** SBA PAT PDC support 1099** 1100** o call pdc_pat_cell_module() 1101** o store ranges in PCI "resource" structures 1102** 1103**************************************************************************/ 1104 1105static void 1106sba_get_pat_resources(struct sba_device *sba_dev) 1107{ 1108#if 0 1109/* 1110** TODO/REVISIT/FIXME: support for directed ranges requires calls to 1111** PAT PDC to program the SBA/LBA directed range registers...this 1112** burden may fall on the LBA code since it directly supports the 1113** PCI subsystem. It's not clear yet. - ggg 1114*/ 1115PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp); 1116 FIXME : ??? 1117PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp); 1118 Tells where the dvi bits are located in the address. 1119PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp); 1120 FIXME : ??? 1121#endif 1122} 1123 1124 1125/************************************************************** 1126* 1127* Initialization and claim 1128* 1129***************************************************************/ 1130#define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */ 1131#define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */ 1132static void * 1133sba_alloc_pdir(unsigned int pdir_size) 1134{ 1135 unsigned long pdir_base; 1136 unsigned long pdir_order = get_order(pdir_size); 1137 1138 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order); 1139 if (NULL == (void *) pdir_base) { 1140 panic("%s() could not allocate I/O Page Table\n", 1141 __func__); 1142 } 1143 1144 /* If this is not PA8700 (PCX-W2) 1145 ** OR newer than ver 2.2 1146 ** OR in a system that doesn't need VINDEX bits from SBA, 1147 ** 1148 ** then we aren't exposed to the HW bug. 1149 */ 1150 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13 1151 || (boot_cpu_data.pdc.versions > 0x202) 1152 || (boot_cpu_data.pdc.capabilities & 0x08L) ) 1153 return (void *) pdir_base; 1154 1155 /* 1156 * PA8700 (PCX-W2, aka piranha) silent data corruption fix 1157 * 1158 * An interaction between PA8700 CPU (Ver 2.2 or older) and 1159 * Ike/Astro can cause silent data corruption. This is only 1160 * a problem if the I/O PDIR is located in memory such that 1161 * (little-endian) bits 17 and 18 are on and bit 20 is off. 1162 * 1163 * Since the max IO Pdir size is 2MB, by cleverly allocating the 1164 * right physical address, we can either avoid (IOPDIR <= 1MB) 1165 * or minimize (2MB IO Pdir) the problem if we restrict the 1166 * IO Pdir to a maximum size of 2MB-128K (1902K). 1167 * 1168 * Because we always allocate 2^N sized IO pdirs, either of the 1169 * "bad" regions will be the last 128K if at all. That's easy 1170 * to test for. 1171 * 1172 */ 1173 if (pdir_order <= (19-12)) { 1174 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) { 1175 /* allocate a new one on 512k alignment */ 1176 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12)); 1177 /* release original */ 1178 free_pages(pdir_base, pdir_order); 1179 1180 pdir_base = new_pdir; 1181 1182 /* release excess */ 1183 while (pdir_order < (19-12)) { 1184 new_pdir += pdir_size; 1185 free_pages(new_pdir, pdir_order); 1186 pdir_order +=1; 1187 pdir_size <<=1; 1188 } 1189 } 1190 } else { 1191 /* 1192 ** 1MB or 2MB Pdir 1193 ** Needs to be aligned on an "odd" 1MB boundary. 1194 */ 1195 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */ 1196 1197 /* release original */ 1198 free_pages( pdir_base, pdir_order); 1199 1200 /* release first 1MB */ 1201 free_pages(new_pdir, 20-12); 1202 1203 pdir_base = new_pdir + 1024*1024; 1204 1205 if (pdir_order > (20-12)) { 1206 /* 1207 ** 2MB Pdir. 1208 ** 1209 ** Flag tells init_bitmap() to mark bad 128k as used 1210 ** and to reduce the size by 128k. 1211 */ 1212 piranha_bad_128k = 1; 1213 1214 new_pdir += 3*1024*1024; 1215 /* release last 1MB */ 1216 free_pages(new_pdir, 20-12); 1217 1218 /* release unusable 128KB */ 1219 free_pages(new_pdir - 128*1024 , 17-12); 1220 1221 pdir_size -= 128*1024; 1222 } 1223 } 1224 1225 memset((void *) pdir_base, 0, pdir_size); 1226 return (void *) pdir_base; 1227} 1228 1229struct ibase_data_struct { 1230 struct ioc *ioc; 1231 int ioc_num; 1232}; 1233 1234static int setup_ibase_imask_callback(struct device *dev, void *data) 1235{ 1236 struct parisc_device *lba = to_parisc_device(dev); 1237 struct ibase_data_struct *ibd = data; 1238 int rope_num = (lba->hpa.start >> 13) & 0xf; 1239 if (rope_num >> 3 == ibd->ioc_num) 1240 lba_set_iregs(lba, ibd->ioc->ibase, ibd->ioc->imask); 1241 return 0; 1242} 1243 1244/* setup Mercury or Elroy IBASE/IMASK registers. */ 1245static void 1246setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1247{ 1248 struct ibase_data_struct ibase_data = { 1249 .ioc = ioc, 1250 .ioc_num = ioc_num, 1251 }; 1252 1253 device_for_each_child(&sba->dev, &ibase_data, 1254 setup_ibase_imask_callback); 1255} 1256 1257#ifdef SBA_AGP_SUPPORT 1258static int 1259sba_ioc_find_quicksilver(struct device *dev, void *data) 1260{ 1261 int *agp_found = data; 1262 struct parisc_device *lba = to_parisc_device(dev); 1263 1264 if (IS_QUICKSILVER(lba)) 1265 *agp_found = 1; 1266 return 0; 1267} 1268#endif 1269 1270static void 1271sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1272{ 1273 u32 iova_space_mask; 1274 u32 iova_space_size; 1275 int iov_order, tcnfg; 1276#ifdef SBA_AGP_SUPPORT 1277 int agp_found = 0; 1278#endif 1279 /* 1280 ** Firmware programs the base and size of a "safe IOVA space" 1281 ** (one that doesn't overlap memory or LMMIO space) in the 1282 ** IBASE and IMASK registers. 1283 */ 1284 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE) & ~0x1fffffULL; 1285 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1; 1286 1287 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) { 1288 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n"); 1289 iova_space_size /= 2; 1290 } 1291 1292 /* 1293 ** iov_order is always based on a 1GB IOVA space since we want to 1294 ** turn on the other half for AGP GART. 1295 */ 1296 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT)); 1297 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64); 1298 1299 DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n", 1300 __func__, ioc->ioc_hpa, iova_space_size >> 20, 1301 iov_order + PAGE_SHIFT); 1302 1303 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL, 1304 get_order(ioc->pdir_size)); 1305 if (!ioc->pdir_base) 1306 panic("Couldn't allocate I/O Page Table\n"); 1307 1308 memset(ioc->pdir_base, 0, ioc->pdir_size); 1309 1310 DBG_INIT("%s() pdir %p size %x\n", 1311 __func__, ioc->pdir_base, ioc->pdir_size); 1312 1313#ifdef SBA_HINT_SUPPORT 1314 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT; 1315 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT)); 1316 1317 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n", 1318 ioc->hint_shift_pdir, ioc->hint_mask_pdir); 1319#endif 1320 1321 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base); 1322 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); 1323 1324 /* build IMASK for IOC and Elroy */ 1325 iova_space_mask = 0xffffffff; 1326 iova_space_mask <<= (iov_order + PAGE_SHIFT); 1327 ioc->imask = iova_space_mask; 1328#ifdef ZX1_SUPPORT 1329 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1); 1330#endif 1331 sba_dump_tlb(ioc->ioc_hpa); 1332 1333 setup_ibase_imask(sba, ioc, ioc_num); 1334 1335 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK); 1336 1337#ifdef CONFIG_64BIT 1338 /* 1339 ** Setting the upper bits makes checking for bypass addresses 1340 ** a little faster later on. 1341 */ 1342 ioc->imask |= 0xFFFFFFFF00000000UL; 1343#endif 1344 1345 /* Set I/O PDIR Page size to system page size */ 1346 switch (PAGE_SHIFT) { 1347 case 12: tcnfg = 0; break; /* 4K */ 1348 case 13: tcnfg = 1; break; /* 8K */ 1349 case 14: tcnfg = 2; break; /* 16K */ 1350 case 16: tcnfg = 3; break; /* 64K */ 1351 default: 1352 panic(__FILE__ "Unsupported system page size %d", 1353 1 << PAGE_SHIFT); 1354 break; 1355 } 1356 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG); 1357 1358 /* 1359 ** Program the IOC's ibase and enable IOVA translation 1360 ** Bit zero == enable bit. 1361 */ 1362 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE); 1363 1364 /* 1365 ** Clear I/O TLB of any possible entries. 1366 ** (Yes. This is a bit paranoid...but so what) 1367 */ 1368 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM); 1369 1370#ifdef SBA_AGP_SUPPORT 1371 1372 /* 1373 ** If an AGP device is present, only use half of the IOV space 1374 ** for PCI DMA. Unfortunately we can't know ahead of time 1375 ** whether GART support will actually be used, for now we 1376 ** can just key on any AGP device found in the system. 1377 ** We program the next pdir index after we stop w/ a key for 1378 ** the GART code to handshake on. 1379 */ 1380 device_for_each_child(&sba->dev, &agp_found, sba_ioc_find_quicksilver); 1381 1382 if (agp_found && sba_reserve_agpgart) { 1383 printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n", 1384 __func__, (iova_space_size/2) >> 20); 1385 ioc->pdir_size /= 2; 1386 ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE; 1387 } 1388#endif /*SBA_AGP_SUPPORT*/ 1389} 1390 1391static void 1392sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1393{ 1394 u32 iova_space_size, iova_space_mask; 1395 unsigned int pdir_size, iov_order, tcnfg; 1396 1397 /* 1398 ** Determine IOVA Space size from memory size. 1399 ** 1400 ** Ideally, PCI drivers would register the maximum number 1401 ** of DMA they can have outstanding for each device they 1402 ** own. Next best thing would be to guess how much DMA 1403 ** can be outstanding based on PCI Class/sub-class. Both 1404 ** methods still require some "extra" to support PCI 1405 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD). 1406 ** 1407 ** While we have 32-bits "IOVA" space, top two 2 bits are used 1408 ** for DMA hints - ergo only 30 bits max. 1409 */ 1410 1411 iova_space_size = (u32) (totalram_pages()/global_ioc_cnt); 1412 1413 /* limit IOVA space size to 1MB-1GB */ 1414 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) { 1415 iova_space_size = 1 << (20 - PAGE_SHIFT); 1416 } 1417 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) { 1418 iova_space_size = 1 << (30 - PAGE_SHIFT); 1419 } 1420 1421 /* 1422 ** iova space must be log2() in size. 1423 ** thus, pdir/res_map will also be log2(). 1424 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced) 1425 */ 1426 iov_order = get_order(iova_space_size << PAGE_SHIFT); 1427 1428 /* iova_space_size is now bytes, not pages */ 1429 iova_space_size = 1 << (iov_order + PAGE_SHIFT); 1430 1431 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64); 1432 1433 DBG_INIT("%s() hpa %px mem %ldMB IOV %dMB (%d bits)\n", 1434 __func__, 1435 ioc->ioc_hpa, 1436 (unsigned long) totalram_pages() >> (20 - PAGE_SHIFT), 1437 iova_space_size>>20, 1438 iov_order + PAGE_SHIFT); 1439 1440 ioc->pdir_base = sba_alloc_pdir(pdir_size); 1441 1442 DBG_INIT("%s() pdir %p size %x\n", 1443 __func__, ioc->pdir_base, pdir_size); 1444 1445#ifdef SBA_HINT_SUPPORT 1446 /* FIXME : DMA HINTs not used */ 1447 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT; 1448 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT)); 1449 1450 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n", 1451 ioc->hint_shift_pdir, ioc->hint_mask_pdir); 1452#endif 1453 1454 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); 1455 1456 /* build IMASK for IOC and Elroy */ 1457 iova_space_mask = 0xffffffff; 1458 iova_space_mask <<= (iov_order + PAGE_SHIFT); 1459 1460 /* 1461 ** On C3000 w/512MB mem, HP-UX 10.20 reports: 1462 ** ibase=0, imask=0xFE000000, size=0x2000000. 1463 */ 1464 ioc->ibase = 0; 1465 ioc->imask = iova_space_mask; /* save it */ 1466#ifdef ZX1_SUPPORT 1467 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1); 1468#endif 1469 1470 DBG_INIT("%s() IOV base %#lx mask %#0lx\n", 1471 __func__, ioc->ibase, ioc->imask); 1472 1473 /* 1474 ** FIXME: Hint registers are programmed with default hint 1475 ** values during boot, so hints should be sane even if we 1476 ** can't reprogram them the way drivers want. 1477 */ 1478 1479 setup_ibase_imask(sba, ioc, ioc_num); 1480 1481 /* 1482 ** Program the IOC's ibase and enable IOVA translation 1483 */ 1484 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE); 1485 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK); 1486 1487 /* Set I/O PDIR Page size to system page size */ 1488 switch (PAGE_SHIFT) { 1489 case 12: tcnfg = 0; break; /* 4K */ 1490 case 13: tcnfg = 1; break; /* 8K */ 1491 case 14: tcnfg = 2; break; /* 16K */ 1492 case 16: tcnfg = 3; break; /* 64K */ 1493 default: 1494 panic(__FILE__ "Unsupported system page size %d", 1495 1 << PAGE_SHIFT); 1496 break; 1497 } 1498 /* Set I/O PDIR Page size to PAGE_SIZE (4k/16k/...) */ 1499 WRITE_REG(tcnfg, ioc->ioc_hpa+IOC_TCNFG); 1500 1501 /* 1502 ** Clear I/O TLB of any possible entries. 1503 ** (Yes. This is a bit paranoid...but so what) 1504 */ 1505 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM); 1506 1507 ioc->ibase = 0; /* used by SBA_IOVA and related macros */ 1508 1509 DBG_INIT("%s() DONE\n", __func__); 1510} 1511 1512 1513 1514/************************************************************************** 1515** 1516** SBA initialization code (HW and SW) 1517** 1518** o identify SBA chip itself 1519** o initialize SBA chip modes (HardFail) 1520** o initialize SBA chip modes (HardFail) 1521** o FIXME: initialize DMA hints for reasonable defaults 1522** 1523**************************************************************************/ 1524 1525static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset) 1526{ 1527 return ioremap(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE); 1528} 1529 1530static void sba_hw_init(struct sba_device *sba_dev) 1531{ 1532 int i; 1533 int num_ioc; 1534 u64 ioc_ctl; 1535 1536 if (!is_pdc_pat()) { 1537 /* Shutdown the USB controller on Astro-based workstations. 1538 ** Once we reprogram the IOMMU, the next DMA performed by 1539 ** USB will HPMC the box. USB is only enabled if a 1540 ** keyboard is present and found. 1541 ** 1542 ** With serial console, j6k v5.0 firmware says: 1543 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7 1544 ** 1545 ** FIXME: Using GFX+USB console at power up but direct 1546 ** linux to serial console is still broken. 1547 ** USB could generate DMA so we must reset USB. 1548 ** The proper sequence would be: 1549 ** o block console output 1550 ** o reset USB device 1551 ** o reprogram serial port 1552 ** o unblock console output 1553 */ 1554 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) { 1555 pdc_io_reset_devices(); 1556 } 1557 1558 } 1559 1560 1561#if 0 1562printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa, 1563 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class); 1564 1565 /* 1566 ** Need to deal with DMA from LAN. 1567 ** Maybe use page zero boot device as a handle to talk 1568 ** to PDC about which device to shutdown. 1569 ** 1570 ** Netbooting, j6k v5.0 firmware says: 1571 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002 1572 ** ARGH! invalid class. 1573 */ 1574 if ((PAGE0->mem_boot.cl_class != CL_RANDOM) 1575 && (PAGE0->mem_boot.cl_class != CL_SEQU)) { 1576 pdc_io_reset(); 1577 } 1578#endif 1579 1580 if (!IS_PLUTO(sba_dev->dev)) { 1581 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL); 1582 DBG_INIT("%s() hpa %px ioc_ctl 0x%Lx ->", 1583 __func__, sba_dev->sba_hpa, ioc_ctl); 1584 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE); 1585 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC; 1586 /* j6700 v1.6 firmware sets 0x294f */ 1587 /* A500 firmware sets 0x4d */ 1588 1589 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL); 1590 1591#ifdef DEBUG_SBA_INIT 1592 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL); 1593 DBG_INIT(" 0x%Lx\n", ioc_ctl); 1594#endif 1595 } /* if !PLUTO */ 1596 1597 if (IS_ASTRO(sba_dev->dev)) { 1598 int err; 1599 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET); 1600 num_ioc = 1; 1601 1602 sba_dev->chip_resv.name = "Astro Intr Ack"; 1603 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL; 1604 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ; 1605 err = request_resource(&iomem_resource, &(sba_dev->chip_resv)); 1606 BUG_ON(err < 0); 1607 1608 } else if (IS_PLUTO(sba_dev->dev)) { 1609 int err; 1610 1611 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET); 1612 num_ioc = 1; 1613 1614 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA"; 1615 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL; 1616 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1); 1617 err = request_resource(&iomem_resource, &(sba_dev->chip_resv)); 1618 WARN_ON(err < 0); 1619 1620 sba_dev->iommu_resv.name = "IOVA Space"; 1621 sba_dev->iommu_resv.start = 0x40000000UL; 1622 sba_dev->iommu_resv.end = 0x50000000UL - 1; 1623 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv)); 1624 WARN_ON(err < 0); 1625 } else { 1626 /* IKE, REO */ 1627 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0)); 1628 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1)); 1629 num_ioc = 2; 1630 1631 /* TODO - LOOKUP Ike/Stretch chipset mem map */ 1632 } 1633 /* XXX: What about Reo Grande? */ 1634 1635 sba_dev->num_ioc = num_ioc; 1636 for (i = 0; i < num_ioc; i++) { 1637 void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa; 1638 unsigned int j; 1639 1640 for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) { 1641 1642 /* 1643 * Clear ROPE(N)_CONFIG AO bit. 1644 * Disables "NT Ordering" (~= !"Relaxed Ordering") 1645 * Overrides bit 1 in DMA Hint Sets. 1646 * Improves netperf UDP_STREAM by ~10% for bcm5701. 1647 */ 1648 if (IS_PLUTO(sba_dev->dev)) { 1649 void __iomem *rope_cfg; 1650 unsigned long cfg_val; 1651 1652 rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j; 1653 cfg_val = READ_REG(rope_cfg); 1654 cfg_val &= ~IOC_ROPE_AO; 1655 WRITE_REG(cfg_val, rope_cfg); 1656 } 1657 1658 /* 1659 ** Make sure the box crashes on rope errors. 1660 */ 1661 WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j); 1662 } 1663 1664 /* flush out the last writes */ 1665 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL); 1666 1667 DBG_INIT(" ioc[%d] ROPE_CFG %#lx ROPE_DBG %lx\n", 1668 i, 1669 (unsigned long) READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40), 1670 (unsigned long) READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50) 1671 ); 1672 DBG_INIT(" STATUS_CONTROL %#lx FLUSH_CTRL %#lx\n", 1673 (unsigned long) READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108), 1674 (unsigned long) READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400) 1675 ); 1676 1677 if (IS_PLUTO(sba_dev->dev)) { 1678 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i); 1679 } else { 1680 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i); 1681 } 1682 } 1683} 1684 1685static void 1686sba_common_init(struct sba_device *sba_dev) 1687{ 1688 int i; 1689 1690 /* add this one to the head of the list (order doesn't matter) 1691 ** This will be useful for debugging - especially if we get coredumps 1692 */ 1693 sba_dev->next = sba_list; 1694 sba_list = sba_dev; 1695 1696 for(i=0; i< sba_dev->num_ioc; i++) { 1697 int res_size; 1698#ifdef DEBUG_DMB_TRAP 1699 extern void iterate_pages(unsigned long , unsigned long , 1700 void (*)(pte_t * , unsigned long), 1701 unsigned long ); 1702 void set_data_memory_break(pte_t * , unsigned long); 1703#endif 1704 /* resource map size dictated by pdir_size */ 1705 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */ 1706 1707 /* Second part of PIRANHA BUG */ 1708 if (piranha_bad_128k) { 1709 res_size -= (128*1024)/sizeof(u64); 1710 } 1711 1712 res_size >>= 3; /* convert bit count to byte count */ 1713 DBG_INIT("%s() res_size 0x%x\n", 1714 __func__, res_size); 1715 1716 sba_dev->ioc[i].res_size = res_size; 1717 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size)); 1718 1719#ifdef DEBUG_DMB_TRAP 1720 iterate_pages( sba_dev->ioc[i].res_map, res_size, 1721 set_data_memory_break, 0); 1722#endif 1723 1724 if (NULL == sba_dev->ioc[i].res_map) 1725 { 1726 panic("%s:%s() could not allocate resource map\n", 1727 __FILE__, __func__ ); 1728 } 1729 1730 memset(sba_dev->ioc[i].res_map, 0, res_size); 1731 /* next available IOVP - circular search */ 1732 sba_dev->ioc[i].res_hint = (unsigned long *) 1733 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]); 1734 1735#ifdef ASSERT_PDIR_SANITY 1736 /* Mark first bit busy - ie no IOVA 0 */ 1737 sba_dev->ioc[i].res_map[0] = 0x80; 1738 sba_dev->ioc[i].pdir_base[0] = (__force __le64) 0xeeffc0addbba0080ULL; 1739#endif 1740 1741 /* Third (and last) part of PIRANHA BUG */ 1742 if (piranha_bad_128k) { 1743 /* region from +1408K to +1536 is un-usable. */ 1744 1745 int idx_start = (1408*1024/sizeof(u64)) >> 3; 1746 int idx_end = (1536*1024/sizeof(u64)) >> 3; 1747 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]); 1748 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]); 1749 1750 /* mark that part of the io pdir busy */ 1751 while (p_start < p_end) 1752 *p_start++ = -1; 1753 1754 } 1755 1756#ifdef DEBUG_DMB_TRAP 1757 iterate_pages( sba_dev->ioc[i].res_map, res_size, 1758 set_data_memory_break, 0); 1759 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size, 1760 set_data_memory_break, 0); 1761#endif 1762 1763 DBG_INIT("%s() %d res_map %x %p\n", 1764 __func__, i, res_size, sba_dev->ioc[i].res_map); 1765 } 1766 1767 spin_lock_init(&sba_dev->sba_lock); 1768 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC; 1769 1770#ifdef DEBUG_SBA_INIT 1771 /* 1772 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set 1773 * (bit #61, big endian), we have to flush and sync every time 1774 * IO-PDIR is changed in Ike/Astro. 1775 */ 1776 if (ioc_needs_fdc) { 1777 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n"); 1778 } else { 1779 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n"); 1780 } 1781#endif 1782} 1783 1784#ifdef CONFIG_PROC_FS 1785static int sba_proc_info(struct seq_file *m, void *p) 1786{ 1787 struct sba_device *sba_dev = sba_list; 1788 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */ 1789 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */ 1790#ifdef SBA_COLLECT_STATS 1791 unsigned long avg = 0, min, max; 1792#endif 1793 int i; 1794 1795 seq_printf(m, "%s rev %d.%d\n", 1796 sba_dev->name, 1797 (sba_dev->hw_rev & 0x7) + 1, 1798 (sba_dev->hw_rev & 0x18) >> 3); 1799 seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n", 1800 (int)((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */ 1801 total_pages); 1802 1803 seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n", 1804 ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */ 1805 1806 seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n", 1807 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE), 1808 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK), 1809 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE)); 1810 1811 for (i=0; i<4; i++) 1812 seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n", 1813 i, 1814 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18), 1815 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18), 1816 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18)); 1817 1818#ifdef SBA_COLLECT_STATS 1819 seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n", 1820 total_pages - ioc->used_pages, ioc->used_pages, 1821 (int)(ioc->used_pages * 100 / total_pages)); 1822 1823 min = max = ioc->avg_search[0]; 1824 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) { 1825 avg += ioc->avg_search[i]; 1826 if (ioc->avg_search[i] > max) max = ioc->avg_search[i]; 1827 if (ioc->avg_search[i] < min) min = ioc->avg_search[i]; 1828 } 1829 avg /= SBA_SEARCH_SAMPLE; 1830 seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n", 1831 min, avg, max); 1832 1833 seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n", 1834 ioc->msingle_calls, ioc->msingle_pages, 1835 (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls)); 1836 1837 /* KLUGE - unmap_sg calls unmap_single for each mapped page */ 1838 min = ioc->usingle_calls; 1839 max = ioc->usingle_pages - ioc->usg_pages; 1840 seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n", 1841 min, max, (int)((max * 1000)/min)); 1842 1843 seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n", 1844 ioc->msg_calls, ioc->msg_pages, 1845 (int)((ioc->msg_pages * 1000)/ioc->msg_calls)); 1846 1847 seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n", 1848 ioc->usg_calls, ioc->usg_pages, 1849 (int)((ioc->usg_pages * 1000)/ioc->usg_calls)); 1850#endif 1851 1852 return 0; 1853} 1854 1855static int 1856sba_proc_bitmap_info(struct seq_file *m, void *p) 1857{ 1858 struct sba_device *sba_dev = sba_list; 1859 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */ 1860 1861 seq_hex_dump(m, " ", DUMP_PREFIX_NONE, 32, 4, ioc->res_map, 1862 ioc->res_size, false); 1863 seq_putc(m, '\n'); 1864 1865 return 0; 1866} 1867#endif /* CONFIG_PROC_FS */ 1868 1869static const struct parisc_device_id sba_tbl[] __initconst = { 1870 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb }, 1871 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc }, 1872 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc }, 1873 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc }, 1874 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc }, 1875 { 0, } 1876}; 1877 1878static int sba_driver_callback(struct parisc_device *); 1879 1880static struct parisc_driver sba_driver __refdata = { 1881 .name = MODULE_NAME, 1882 .id_table = sba_tbl, 1883 .probe = sba_driver_callback, 1884}; 1885 1886/* 1887** Determine if sba should claim this chip (return 0) or not (return 1). 1888** If so, initialize the chip and tell other partners in crime they 1889** have work to do. 1890*/ 1891static int __init sba_driver_callback(struct parisc_device *dev) 1892{ 1893 struct sba_device *sba_dev; 1894 u32 func_class; 1895 int i; 1896 char *version; 1897 void __iomem *sba_addr = ioremap(dev->hpa.start, SBA_FUNC_SIZE); 1898 struct proc_dir_entry *root __maybe_unused; 1899 1900 sba_dump_ranges(sba_addr); 1901 1902 /* Read HW Rev First */ 1903 func_class = READ_REG(sba_addr + SBA_FCLASS); 1904 1905 if (IS_ASTRO(dev)) { 1906 unsigned long fclass; 1907 static char astro_rev[]="Astro ?.?"; 1908 1909 /* Astro is broken...Read HW Rev First */ 1910 fclass = READ_REG(sba_addr); 1911 1912 astro_rev[6] = '1' + (char) (fclass & 0x7); 1913 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3); 1914 version = astro_rev; 1915 1916 } else if (IS_IKE(dev)) { 1917 static char ike_rev[] = "Ike rev ?"; 1918 ike_rev[8] = '0' + (char) (func_class & 0xff); 1919 version = ike_rev; 1920 } else if (IS_PLUTO(dev)) { 1921 static char pluto_rev[]="Pluto ?.?"; 1922 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4); 1923 pluto_rev[8] = '0' + (char) (func_class & 0x0f); 1924 version = pluto_rev; 1925 } else { 1926 static char reo_rev[] = "REO rev ?"; 1927 reo_rev[8] = '0' + (char) (func_class & 0xff); 1928 version = reo_rev; 1929 } 1930 1931 if (!global_ioc_cnt) { 1932 global_ioc_cnt = count_parisc_driver(&sba_driver); 1933 1934 /* Astro and Pluto have one IOC per SBA */ 1935 if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev))) 1936 global_ioc_cnt *= 2; 1937 } 1938 1939 printk(KERN_INFO "%s found %s at 0x%llx\n", 1940 MODULE_NAME, version, (unsigned long long)dev->hpa.start); 1941 1942 sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL); 1943 if (!sba_dev) { 1944 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n"); 1945 return -ENOMEM; 1946 } 1947 1948 parisc_set_drvdata(dev, sba_dev); 1949 1950 for(i=0; i<MAX_IOC; i++) 1951 spin_lock_init(&(sba_dev->ioc[i].res_lock)); 1952 1953 sba_dev->dev = dev; 1954 sba_dev->hw_rev = func_class; 1955 sba_dev->name = dev->name; 1956 sba_dev->sba_hpa = sba_addr; 1957 1958 sba_get_pat_resources(sba_dev); 1959 sba_hw_init(sba_dev); 1960 sba_common_init(sba_dev); 1961 1962 hppa_dma_ops = &sba_ops; 1963 1964 switch (dev->id.hversion) { 1965 case PLUTO_MCKINLEY_PORT: 1966 if (!proc_mckinley_root) 1967 proc_mckinley_root = proc_mkdir("bus/mckinley", NULL); 1968 root = proc_mckinley_root; 1969 break; 1970 case ASTRO_RUNWAY_PORT: 1971 case IKE_MERCED_PORT: 1972 default: 1973 if (!proc_runway_root) 1974 proc_runway_root = proc_mkdir("bus/runway", NULL); 1975 root = proc_runway_root; 1976 break; 1977 } 1978 1979 proc_create_single("sba_iommu", 0, root, sba_proc_info); 1980 proc_create_single("sba_iommu-bitmap", 0, root, sba_proc_bitmap_info); 1981 return 0; 1982} 1983 1984/* 1985** One time initialization to let the world know the SBA was found. 1986** This is the only routine which is NOT static. 1987** Must be called exactly once before pci_init(). 1988*/ 1989static int __init sba_init(void) 1990{ 1991 return register_parisc_driver(&sba_driver); 1992} 1993arch_initcall(sba_init); 1994 1995 1996/** 1997 * sba_get_iommu - Assign the iommu pointer for the pci bus controller. 1998 * @pci_hba: The parisc device. 1999 * 2000 * Returns the appropriate IOMMU data for the given parisc PCI controller. 2001 * This is cached and used later for PCI DMA Mapping. 2002 */ 2003void * sba_get_iommu(struct parisc_device *pci_hba) 2004{ 2005 struct parisc_device *sba_dev = parisc_parent(pci_hba); 2006 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev); 2007 char t = sba_dev->id.hw_type; 2008 int iocnum = (pci_hba->hw_path >> 3); /* IOC # */ 2009 2010 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT)); 2011 2012 return &(sba->ioc[iocnum]); 2013} 2014 2015 2016/** 2017 * sba_directed_lmmio - return first directed LMMIO range routed to rope 2018 * @pci_hba: The parisc device. 2019 * @r: resource PCI host controller wants start/end fields assigned. 2020 * 2021 * For the given parisc PCI controller, determine if any direct ranges 2022 * are routed down the corresponding rope. 2023 */ 2024void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r) 2025{ 2026 struct parisc_device *sba_dev = parisc_parent(pci_hba); 2027 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev); 2028 char t = sba_dev->id.hw_type; 2029 int i; 2030 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */ 2031 2032 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT)); 2033 2034 r->start = r->end = 0; 2035 2036 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */ 2037 for (i=0; i<4; i++) { 2038 int base, size; 2039 void __iomem *reg = sba->sba_hpa + i*0x18; 2040 2041 base = READ_REG32(reg + LMMIO_DIRECT0_BASE); 2042 if ((base & 1) == 0) 2043 continue; /* not enabled */ 2044 2045 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE); 2046 2047 if ((size & (ROPES_PER_IOC-1)) != rope) 2048 continue; /* directed down different rope */ 2049 2050 r->start = (base & ~1UL) | PCI_F_EXTEND; 2051 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK); 2052 r->end = r->start + size; 2053 r->flags = IORESOURCE_MEM; 2054 } 2055} 2056 2057 2058/** 2059 * sba_distributed_lmmio - return portion of distributed LMMIO range 2060 * @pci_hba: The parisc device. 2061 * @r: resource PCI host controller wants start/end fields assigned. 2062 * 2063 * For the given parisc PCI controller, return portion of distributed LMMIO 2064 * range. The distributed LMMIO is always present and it's just a question 2065 * of the base address and size of the range. 2066 */ 2067void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r ) 2068{ 2069 struct parisc_device *sba_dev = parisc_parent(pci_hba); 2070 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev); 2071 char t = sba_dev->id.hw_type; 2072 int base, size; 2073 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */ 2074 2075 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT)); 2076 2077 r->start = r->end = 0; 2078 2079 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE); 2080 if ((base & 1) == 0) { 2081 BUG(); /* Gah! Distr Range wasn't enabled! */ 2082 return; 2083 } 2084 2085 r->start = (base & ~1UL) | PCI_F_EXTEND; 2086 2087 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC; 2088 r->start += rope * (size + 1); /* adjust base for this rope */ 2089 r->end = r->start + size; 2090 r->flags = IORESOURCE_MEM; 2091}
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