imx-ocotp.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * i.MX6 OCOTP fusebox driver
  4 *
  5 * Copyright (c) 2015 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
  6 *
  7 * Copyright 2019 NXP
  8 *
  9 * Based on the barebox ocotp driver,
 10 * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>,
 11 *	Orex Computed Radiography
 12 *
 13 * Write support based on the fsl_otp driver,
 14 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc
 15 */
 16
 17#include <linux/clk.h>
 18#include <linux/device.h>
 19#include <linux/io.h>
 20#include <linux/module.h>
 21#include <linux/nvmem-provider.h>
 22#include <linux/of.h>
 23#include <linux/platform_device.h>
 24#include <linux/slab.h>
 25#include <linux/delay.h>
 26#include <linux/if_ether.h>	/* ETH_ALEN */
 27
 28#define IMX_OCOTP_OFFSET_B0W0		0x400 /* Offset from base address of the
 29					       * OTP Bank0 Word0
 30					       */
 31#define IMX_OCOTP_OFFSET_PER_WORD	0x10  /* Offset between the start addr
 32					       * of two consecutive OTP words.
 33					       */
 34
 35#define IMX_OCOTP_ADDR_CTRL		0x0000
 36#define IMX_OCOTP_ADDR_CTRL_SET		0x0004
 37#define IMX_OCOTP_ADDR_CTRL_CLR		0x0008
 38#define IMX_OCOTP_ADDR_TIMING		0x0010
 39#define IMX_OCOTP_ADDR_DATA0		0x0020
 40#define IMX_OCOTP_ADDR_DATA1		0x0030
 41#define IMX_OCOTP_ADDR_DATA2		0x0040
 42#define IMX_OCOTP_ADDR_DATA3		0x0050
 43
 44#define IMX_OCOTP_BM_CTRL_ADDR		0x000000FF
 45#define IMX_OCOTP_BM_CTRL_BUSY		0x00000100
 46#define IMX_OCOTP_BM_CTRL_ERROR		0x00000200
 47#define IMX_OCOTP_BM_CTRL_REL_SHADOWS	0x00000400
 48
 49#define IMX_OCOTP_BM_CTRL_ADDR_8MP		0x000001FF
 50#define IMX_OCOTP_BM_CTRL_BUSY_8MP		0x00000200
 51#define IMX_OCOTP_BM_CTRL_ERROR_8MP		0x00000400
 52#define IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP	0x00000800
 53
 54#define IMX_OCOTP_BM_CTRL_DEFAULT				\
 55	{							\
 56		.bm_addr = IMX_OCOTP_BM_CTRL_ADDR,		\
 57		.bm_busy = IMX_OCOTP_BM_CTRL_BUSY,		\
 58		.bm_error = IMX_OCOTP_BM_CTRL_ERROR,		\
 59		.bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS,\
 60	}
 61
 62#define IMX_OCOTP_BM_CTRL_8MP					\
 63	{							\
 64		.bm_addr = IMX_OCOTP_BM_CTRL_ADDR_8MP,		\
 65		.bm_busy = IMX_OCOTP_BM_CTRL_BUSY_8MP,		\
 66		.bm_error = IMX_OCOTP_BM_CTRL_ERROR_8MP,	\
 67		.bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP,\
 68	}
 69
 70#define TIMING_STROBE_PROG_US		10	/* Min time to blow a fuse */
 71#define TIMING_STROBE_READ_NS		37	/* Min time before read */
 72#define TIMING_RELAX_NS			17
 73#define DEF_FSOURCE			1001	/* > 1000 ns */
 74#define DEF_STROBE_PROG			10000	/* IPG clocks */
 75#define IMX_OCOTP_WR_UNLOCK		0x3E770000
 76#define IMX_OCOTP_READ_LOCKED_VAL	0xBADABADA
 77
 78static DEFINE_MUTEX(ocotp_mutex);
 79
 80struct ocotp_priv {
 81	struct device *dev;
 82	struct clk *clk;
 83	void __iomem *base;
 84	const struct ocotp_params *params;
 85	struct nvmem_config *config;
 86};
 87
 88struct ocotp_ctrl_reg {
 89	u32 bm_addr;
 90	u32 bm_busy;
 91	u32 bm_error;
 92	u32 bm_rel_shadows;
 93};
 94
 95struct ocotp_params {
 96	unsigned int nregs;
 97	unsigned int bank_address_words;
 98	void (*set_timing)(struct ocotp_priv *priv);
 99	struct ocotp_ctrl_reg ctrl;
100};
101
102static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags)
103{
104	int count;
105	u32 c, mask;
106	u32 bm_ctrl_busy, bm_ctrl_error;
107	void __iomem *base = priv->base;
108
109	bm_ctrl_busy = priv->params->ctrl.bm_busy;
110	bm_ctrl_error = priv->params->ctrl.bm_error;
111
112	mask = bm_ctrl_busy | bm_ctrl_error | flags;
113
114	for (count = 10000; count >= 0; count--) {
115		c = readl(base + IMX_OCOTP_ADDR_CTRL);
116		if (!(c & mask))
117			break;
118		cpu_relax();
119	}
120
121	if (count < 0) {
122		/* HW_OCOTP_CTRL[ERROR] will be set under the following
123		 * conditions:
124		 * - A write is performed to a shadow register during a shadow
125		 *   reload (essentially, while HW_OCOTP_CTRL[RELOAD_SHADOWS] is
126		 *   set. In addition, the contents of the shadow register shall
127		 *   not be updated.
128		 * - A write is performed to a shadow register which has been
129		 *   locked.
130		 * - A read is performed to from a shadow register which has
131		 *   been read locked.
132		 * - A program is performed to a fuse word which has been locked
133		 * - A read is performed to from a fuse word which has been read
134		 *   locked.
135		 */
136		if (c & bm_ctrl_error)
137			return -EPERM;
138		return -ETIMEDOUT;
139	}
140
141	return 0;
142}
143
144static void imx_ocotp_clr_err_if_set(struct ocotp_priv *priv)
145{
146	u32 c, bm_ctrl_error;
147	void __iomem *base = priv->base;
148
149	bm_ctrl_error = priv->params->ctrl.bm_error;
150
151	c = readl(base + IMX_OCOTP_ADDR_CTRL);
152	if (!(c & bm_ctrl_error))
153		return;
154
155	writel(bm_ctrl_error, base + IMX_OCOTP_ADDR_CTRL_CLR);
156}
157
158static int imx_ocotp_read(void *context, unsigned int offset,
159			  void *val, size_t bytes)
160{
161	struct ocotp_priv *priv = context;
162	unsigned int count;
163	u8 *buf, *p;
164	int i, ret;
165	u32 index, num_bytes;
166
167	index = offset >> 2;
168	num_bytes = round_up((offset % 4) + bytes, 4);
169	count = num_bytes >> 2;
170
171	if (count > (priv->params->nregs - index))
172		count = priv->params->nregs - index;
173
174	p = kzalloc(num_bytes, GFP_KERNEL);
175	if (!p)
176		return -ENOMEM;
177
178	mutex_lock(&ocotp_mutex);
179
180	buf = p;
181
182	ret = clk_prepare_enable(priv->clk);
183	if (ret < 0) {
184		mutex_unlock(&ocotp_mutex);
185		dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
186		kfree(p);
187		return ret;
188	}
189
190	ret = imx_ocotp_wait_for_busy(priv, 0);
191	if (ret < 0) {
192		dev_err(priv->dev, "timeout during read setup\n");
193		goto read_end;
194	}
195
196	for (i = index; i < (index + count); i++) {
197		*(u32 *)buf = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 +
198			       i * IMX_OCOTP_OFFSET_PER_WORD);
199
200		/* 47.3.1.2
201		 * For "read locked" registers 0xBADABADA will be returned and
202		 * HW_OCOTP_CTRL[ERROR] will be set. It must be cleared by
203		 * software before any new write, read or reload access can be
204		 * issued
205		 */
206		if (*((u32 *)buf) == IMX_OCOTP_READ_LOCKED_VAL)
207			imx_ocotp_clr_err_if_set(priv);
208
209		buf += 4;
210	}
211
212	index = offset % 4;
213	memcpy(val, &p[index], bytes);
214
215read_end:
216	clk_disable_unprepare(priv->clk);
217	mutex_unlock(&ocotp_mutex);
218
219	kfree(p);
220
221	return ret;
222}
223
224static int imx_ocotp_cell_pp(void *context, const char *id, int index,
225			     unsigned int offset, void *data, size_t bytes)
226{
227	u8 *buf = data;
228	int i;
229
230	/* Deal with some post processing of nvmem cell data */
231	if (id && !strcmp(id, "mac-address")) {
232		bytes = min(bytes, ETH_ALEN);
233		for (i = 0; i < bytes / 2; i++)
234			swap(buf[i], buf[bytes - i - 1]);
235	}
236
237	return 0;
238}
239
240static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv)
241{
242	unsigned long clk_rate;
243	unsigned long strobe_read, relax, strobe_prog;
244	u32 timing;
245
246	/* 47.3.1.3.1
247	 * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX]
248	 * fields with timing values to match the current frequency of the
249	 * ipg_clk. OTP writes will work at maximum bus frequencies as long
250	 * as the HW_OCOTP_TIMING parameters are set correctly.
251	 *
252	 * Note: there are minimum timings required to ensure an OTP fuse burns
253	 * correctly that are independent of the ipg_clk. Those values are not
254	 * formally documented anywhere however, working from the minimum
255	 * timings given in u-boot we can say:
256	 *
257	 * - Minimum STROBE_PROG time is 10 microseconds. Intuitively 10
258	 *   microseconds feels about right as representative of a minimum time
259	 *   to physically burn out a fuse.
260	 *
261	 * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before
262	 *   performing another read is 37 nanoseconds
263	 *
264	 * - Minimum RELAX timing is 17 nanoseconds. This final RELAX minimum
265	 *   timing is not entirely clear the documentation says "This
266	 *   count value specifies the time to add to all default timing
267	 *   parameters other than the Tpgm and Trd. It is given in number
268	 *   of ipg_clk periods." where Tpgm and Trd refer to STROBE_PROG
269	 *   and STROBE_READ respectively. What the other timing parameters
270	 *   are though, is not specified. Experience shows a zero RELAX
271	 *   value will mess up a re-load of the shadow registers post OTP
272	 *   burn.
273	 */
274	clk_rate = clk_get_rate(priv->clk);
275
276	relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1;
277	strobe_read = DIV_ROUND_UP(clk_rate * TIMING_STROBE_READ_NS,
278				   1000000000);
279	strobe_read += 2 * (relax + 1) - 1;
280	strobe_prog = DIV_ROUND_CLOSEST(clk_rate * TIMING_STROBE_PROG_US,
281					1000000);
282	strobe_prog += 2 * (relax + 1) - 1;
283
284	timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000;
285	timing |= strobe_prog & 0x00000FFF;
286	timing |= (relax       << 12) & 0x0000F000;
287	timing |= (strobe_read << 16) & 0x003F0000;
288
289	writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
290}
291
292static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv)
293{
294	unsigned long clk_rate;
295	u64 fsource, strobe_prog;
296	u32 timing;
297
298	/* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1
299	 * 6.4.3.3
300	 */
301	clk_rate = clk_get_rate(priv->clk);
302	fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE,
303				   NSEC_PER_SEC) + 1;
304	strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG,
305					    NSEC_PER_SEC) + 1;
306
307	timing = strobe_prog & 0x00000FFF;
308	timing |= (fsource << 12) & 0x000FF000;
309
310	writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
311}
312
313static int imx_ocotp_write(void *context, unsigned int offset, void *val,
314			   size_t bytes)
315{
316	struct ocotp_priv *priv = context;
317	u32 *buf = val;
318	int ret;
319
320	u32 ctrl;
321	u8 waddr;
322	u8 word = 0;
323
324	/* allow only writing one complete OTP word at a time */
325	if ((bytes != priv->config->word_size) ||
326	    (offset % priv->config->word_size))
327		return -EINVAL;
328
329	mutex_lock(&ocotp_mutex);
330
331	ret = clk_prepare_enable(priv->clk);
332	if (ret < 0) {
333		mutex_unlock(&ocotp_mutex);
334		dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
335		return ret;
336	}
337
338	/* Setup the write timing values */
339	priv->params->set_timing(priv);
340
341	/* 47.3.1.3.2
342	 * Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear.
343	 * Overlapped accesses are not supported by the controller. Any pending
344	 * write or reload must be completed before a write access can be
345	 * requested.
346	 */
347	ret = imx_ocotp_wait_for_busy(priv, 0);
348	if (ret < 0) {
349		dev_err(priv->dev, "timeout during timing setup\n");
350		goto write_end;
351	}
352
353	/* 47.3.1.3.3
354	 * Write the requested address to HW_OCOTP_CTRL[ADDR] and program the
355	 * unlock code into HW_OCOTP_CTRL[WR_UNLOCK]. This must be programmed
356	 * for each write access. The lock code is documented in the register
357	 * description. Both the unlock code and address can be written in the
358	 * same operation.
359	 */
360	if (priv->params->bank_address_words != 0) {
361		/*
362		 * In banked/i.MX7 mode the OTP register bank goes into waddr
363		 * see i.MX 7Solo Applications Processor Reference Manual, Rev.
364		 * 0.1 section 6.4.3.1
365		 */
366		offset = offset / priv->config->word_size;
367		waddr = offset / priv->params->bank_address_words;
368		word  = offset & (priv->params->bank_address_words - 1);
369	} else {
370		/*
371		 * Non-banked i.MX6 mode.
372		 * OTP write/read address specifies one of 128 word address
373		 * locations
374		 */
375		waddr = offset / 4;
376	}
377
378	ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL);
379	ctrl &= ~priv->params->ctrl.bm_addr;
380	ctrl |= waddr & priv->params->ctrl.bm_addr;
381	ctrl |= IMX_OCOTP_WR_UNLOCK;
382
383	writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL);
384
385	/* 47.3.1.3.4
386	 * Write the data to the HW_OCOTP_DATA register. This will automatically
387	 * set HW_OCOTP_CTRL[BUSY] and clear HW_OCOTP_CTRL[WR_UNLOCK]. To
388	 * protect programming same OTP bit twice, before program OCOTP will
389	 * automatically read fuse value in OTP and use read value to mask
390	 * program data. The controller will use masked program data to program
391	 * a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit
392	 * fields with 1's will result in that OTP bit being programmed. Bit
393	 * fields with 0's will be ignored. At the same time that the write is
394	 * accepted, the controller makes an internal copy of
395	 * HW_OCOTP_CTRL[ADDR] which cannot be updated until the next write
396	 * sequence is initiated. This copy guarantees that erroneous writes to
397	 * HW_OCOTP_CTRL[ADDR] will not affect an active write operation. It
398	 * should also be noted that during the programming HW_OCOTP_DATA will
399	 * shift right (with zero fill). This shifting is required to program
400	 * the OTP serially. During the write operation, HW_OCOTP_DATA cannot be
401	 * modified.
402	 * Note: on i.MX7 there are four data fields to write for banked write
403	 *       with the fuse blowing operation only taking place after data0
404	 *	 has been written. This is why data0 must always be the last
405	 *	 register written.
406	 */
407	if (priv->params->bank_address_words != 0) {
408		/* Banked/i.MX7 mode */
409		switch (word) {
410		case 0:
411			writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
412			writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
413			writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
414			writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
415			break;
416		case 1:
417			writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1);
418			writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
419			writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
420			writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
421			break;
422		case 2:
423			writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
424			writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2);
425			writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
426			writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
427			break;
428		case 3:
429			writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
430			writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
431			writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3);
432			writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
433			break;
434		}
435	} else {
436		/* Non-banked i.MX6 mode */
437		writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
438	}
439
440	/* 47.4.1.4.5
441	 * Once complete, the controller will clear BUSY. A write request to a
442	 * protected or locked region will result in no OTP access and no
443	 * setting of HW_OCOTP_CTRL[BUSY]. In addition HW_OCOTP_CTRL[ERROR] will
444	 * be set. It must be cleared by software before any new write access
445	 * can be issued.
446	 */
447	ret = imx_ocotp_wait_for_busy(priv, 0);
448	if (ret < 0) {
449		if (ret == -EPERM) {
450			dev_err(priv->dev, "failed write to locked region");
451			imx_ocotp_clr_err_if_set(priv);
452		} else {
453			dev_err(priv->dev, "timeout during data write\n");
454		}
455		goto write_end;
456	}
457
458	/* 47.3.1.4
459	 * Write Postamble: Due to internal electrical characteristics of the
460	 * OTP during writes, all OTP operations following a write must be
461	 * separated by 2 us after the clearing of HW_OCOTP_CTRL_BUSY following
462	 * the write.
463	 */
464	udelay(2);
465
466	/* reload all shadow registers */
467	writel(priv->params->ctrl.bm_rel_shadows,
468	       priv->base + IMX_OCOTP_ADDR_CTRL_SET);
469	ret = imx_ocotp_wait_for_busy(priv,
470				      priv->params->ctrl.bm_rel_shadows);
471	if (ret < 0)
472		dev_err(priv->dev, "timeout during shadow register reload\n");
473
474write_end:
475	clk_disable_unprepare(priv->clk);
476	mutex_unlock(&ocotp_mutex);
477	return ret < 0 ? ret : bytes;
478}
479
480static struct nvmem_config imx_ocotp_nvmem_config = {
481	.name = "imx-ocotp",
482	.read_only = false,
483	.word_size = 4,
484	.stride = 1,
485	.reg_read = imx_ocotp_read,
486	.reg_write = imx_ocotp_write,
487};
488
489static const struct ocotp_params imx6q_params = {
490	.nregs = 128,
491	.bank_address_words = 0,
492	.set_timing = imx_ocotp_set_imx6_timing,
493	.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
494};
495
496static const struct ocotp_params imx6sl_params = {
497	.nregs = 64,
498	.bank_address_words = 0,
499	.set_timing = imx_ocotp_set_imx6_timing,
500	.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
501};
502
503static const struct ocotp_params imx6sll_params = {
504	.nregs = 80,
505	.bank_address_words = 0,
506	.set_timing = imx_ocotp_set_imx6_timing,
507	.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
508};
509
510static const struct ocotp_params imx6sx_params = {
511	.nregs = 128,
512	.bank_address_words = 0,
513	.set_timing = imx_ocotp_set_imx6_timing,
514	.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
515};
516
517static const struct ocotp_params imx6ul_params = {
518	.nregs = 144,
519	.bank_address_words = 0,
520	.set_timing = imx_ocotp_set_imx6_timing,
521	.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
522};
523
524static const struct ocotp_params imx6ull_params = {
525	.nregs = 80,
526	.bank_address_words = 0,
527	.set_timing = imx_ocotp_set_imx6_timing,
528	.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
529};
530
531static const struct ocotp_params imx7d_params = {
532	.nregs = 64,
533	.bank_address_words = 4,
534	.set_timing = imx_ocotp_set_imx7_timing,
535	.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
536};
537
538static const struct ocotp_params imx7ulp_params = {
539	.nregs = 256,
540	.bank_address_words = 0,
541	.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
542};
543
544static const struct ocotp_params imx8mq_params = {
545	.nregs = 256,
546	.bank_address_words = 0,
547	.set_timing = imx_ocotp_set_imx6_timing,
548	.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
549};
550
551static const struct ocotp_params imx8mm_params = {
552	.nregs = 256,
553	.bank_address_words = 0,
554	.set_timing = imx_ocotp_set_imx6_timing,
555	.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
556};
557
558static const struct ocotp_params imx8mn_params = {
559	.nregs = 256,
560	.bank_address_words = 0,
561	.set_timing = imx_ocotp_set_imx6_timing,
562	.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
563};
564
565static const struct ocotp_params imx8mp_params = {
566	.nregs = 384,
567	.bank_address_words = 0,
568	.set_timing = imx_ocotp_set_imx6_timing,
569	.ctrl = IMX_OCOTP_BM_CTRL_8MP,
570};
571
572static const struct of_device_id imx_ocotp_dt_ids[] = {
573	{ .compatible = "fsl,imx6q-ocotp",  .data = &imx6q_params },
574	{ .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params },
575	{ .compatible = "fsl,imx6sx-ocotp", .data = &imx6sx_params },
576	{ .compatible = "fsl,imx6ul-ocotp", .data = &imx6ul_params },
577	{ .compatible = "fsl,imx6ull-ocotp", .data = &imx6ull_params },
578	{ .compatible = "fsl,imx7d-ocotp",  .data = &imx7d_params },
579	{ .compatible = "fsl,imx6sll-ocotp", .data = &imx6sll_params },
580	{ .compatible = "fsl,imx7ulp-ocotp", .data = &imx7ulp_params },
581	{ .compatible = "fsl,imx8mq-ocotp", .data = &imx8mq_params },
582	{ .compatible = "fsl,imx8mm-ocotp", .data = &imx8mm_params },
583	{ .compatible = "fsl,imx8mn-ocotp", .data = &imx8mn_params },
584	{ .compatible = "fsl,imx8mp-ocotp", .data = &imx8mp_params },
585	{ },
586};
587MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);
588
589static void imx_ocotp_fixup_dt_cell_info(struct nvmem_device *nvmem,
590					 struct nvmem_cell_info *cell)
591{
592	cell->raw_len = round_up(cell->bytes, 4);
593	cell->read_post_process = imx_ocotp_cell_pp;
594}
595
596static int imx_ocotp_probe(struct platform_device *pdev)
597{
598	struct device *dev = &pdev->dev;
599	struct ocotp_priv *priv;
600	struct nvmem_device *nvmem;
601
602	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
603	if (!priv)
604		return -ENOMEM;
605
606	priv->dev = dev;
607
608	priv->base = devm_platform_ioremap_resource(pdev, 0);
609	if (IS_ERR(priv->base))
610		return PTR_ERR(priv->base);
611
612	priv->clk = devm_clk_get(dev, NULL);
613	if (IS_ERR(priv->clk))
614		return PTR_ERR(priv->clk);
615
616	priv->params = of_device_get_match_data(&pdev->dev);
617	imx_ocotp_nvmem_config.add_legacy_fixed_of_cells = true;
618	imx_ocotp_nvmem_config.size = 4 * priv->params->nregs;
619	imx_ocotp_nvmem_config.dev = dev;
620	imx_ocotp_nvmem_config.priv = priv;
621	imx_ocotp_nvmem_config.fixup_dt_cell_info = &imx_ocotp_fixup_dt_cell_info;
622
623	priv->config = &imx_ocotp_nvmem_config;
624
625	clk_prepare_enable(priv->clk);
626	imx_ocotp_clr_err_if_set(priv);
627	clk_disable_unprepare(priv->clk);
628
629	nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config);
630
631	return PTR_ERR_OR_ZERO(nvmem);
632}
633
634static struct platform_driver imx_ocotp_driver = {
635	.probe	= imx_ocotp_probe,
636	.driver = {
637		.name	= "imx_ocotp",
638		.of_match_table = imx_ocotp_dt_ids,
639	},
640};
641module_platform_driver(imx_ocotp_driver);
642
643MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
644MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver");
645MODULE_LICENSE("GPL v2");