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ntb_hw_idt.c
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linux-6.19.14/drivers/ntb/hw/idt/ntb_hw_idt.c
1/* 2 * This file is provided under a GPLv2 license. When using or 3 * redistributing this file, you may do so under that license. 4 * 5 * GPL LICENSE SUMMARY 6 * 7 * Copyright (C) 2016-2018 T-Platforms JSC All Rights Reserved. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2, as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General 16 * Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, one can be found http://www.gnu.org/licenses/. 20 * 21 * The full GNU General Public License is included in this distribution in 22 * the file called "COPYING". 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * IDT PCIe-switch NTB Linux driver 37 * 38 * Contact Information: 39 * Serge Semin <fancer.lancer@gmail.com>, <Sergey.Semin@t-platforms.ru> 40 */ 41 42#include <linux/stddef.h> 43#include <linux/types.h> 44#include <linux/kernel.h> 45#include <linux/bitops.h> 46#include <linux/sizes.h> 47#include <linux/module.h> 48#include <linux/moduleparam.h> 49#include <linux/init.h> 50#include <linux/interrupt.h> 51#include <linux/spinlock.h> 52#include <linux/mutex.h> 53#include <linux/pci.h> 54#include <linux/aer.h> 55#include <linux/slab.h> 56#include <linux/list.h> 57#include <linux/debugfs.h> 58#include <linux/hwmon.h> 59#include <linux/hwmon-sysfs.h> 60#include <linux/ntb.h> 61 62#include "ntb_hw_idt.h" 63 64#define NTB_NAME "ntb_hw_idt" 65#define NTB_DESC "IDT PCI-E Non-Transparent Bridge Driver" 66#define NTB_VER "2.0" 67#define NTB_IRQNAME "ntb_irq_idt" 68 69MODULE_DESCRIPTION(NTB_DESC); 70MODULE_VERSION(NTB_VER); 71MODULE_LICENSE("GPL v2"); 72MODULE_AUTHOR("T-platforms"); 73 74/* 75 * NT Endpoint registers table simplifying a loop access to the functionally 76 * related registers 77 */ 78static const struct idt_ntb_regs ntdata_tbl = { 79 { {IDT_NT_BARSETUP0, IDT_NT_BARLIMIT0, 80 IDT_NT_BARLTBASE0, IDT_NT_BARUTBASE0}, 81 {IDT_NT_BARSETUP1, IDT_NT_BARLIMIT1, 82 IDT_NT_BARLTBASE1, IDT_NT_BARUTBASE1}, 83 {IDT_NT_BARSETUP2, IDT_NT_BARLIMIT2, 84 IDT_NT_BARLTBASE2, IDT_NT_BARUTBASE2}, 85 {IDT_NT_BARSETUP3, IDT_NT_BARLIMIT3, 86 IDT_NT_BARLTBASE3, IDT_NT_BARUTBASE3}, 87 {IDT_NT_BARSETUP4, IDT_NT_BARLIMIT4, 88 IDT_NT_BARLTBASE4, IDT_NT_BARUTBASE4}, 89 {IDT_NT_BARSETUP5, IDT_NT_BARLIMIT5, 90 IDT_NT_BARLTBASE5, IDT_NT_BARUTBASE5} }, 91 { {IDT_NT_INMSG0, IDT_NT_OUTMSG0, IDT_NT_INMSGSRC0}, 92 {IDT_NT_INMSG1, IDT_NT_OUTMSG1, IDT_NT_INMSGSRC1}, 93 {IDT_NT_INMSG2, IDT_NT_OUTMSG2, IDT_NT_INMSGSRC2}, 94 {IDT_NT_INMSG3, IDT_NT_OUTMSG3, IDT_NT_INMSGSRC3} } 95}; 96 97/* 98 * NT Endpoint ports data table with the corresponding pcie command, link 99 * status, control and BAR-related registers 100 */ 101static const struct idt_ntb_port portdata_tbl[IDT_MAX_NR_PORTS] = { 102/*0*/ { IDT_SW_NTP0_PCIECMDSTS, IDT_SW_NTP0_PCIELCTLSTS, 103 IDT_SW_NTP0_NTCTL, 104 IDT_SW_SWPORT0CTL, IDT_SW_SWPORT0STS, 105 { {IDT_SW_NTP0_BARSETUP0, IDT_SW_NTP0_BARLIMIT0, 106 IDT_SW_NTP0_BARLTBASE0, IDT_SW_NTP0_BARUTBASE0}, 107 {IDT_SW_NTP0_BARSETUP1, IDT_SW_NTP0_BARLIMIT1, 108 IDT_SW_NTP0_BARLTBASE1, IDT_SW_NTP0_BARUTBASE1}, 109 {IDT_SW_NTP0_BARSETUP2, IDT_SW_NTP0_BARLIMIT2, 110 IDT_SW_NTP0_BARLTBASE2, IDT_SW_NTP0_BARUTBASE2}, 111 {IDT_SW_NTP0_BARSETUP3, IDT_SW_NTP0_BARLIMIT3, 112 IDT_SW_NTP0_BARLTBASE3, IDT_SW_NTP0_BARUTBASE3}, 113 {IDT_SW_NTP0_BARSETUP4, IDT_SW_NTP0_BARLIMIT4, 114 IDT_SW_NTP0_BARLTBASE4, IDT_SW_NTP0_BARUTBASE4}, 115 {IDT_SW_NTP0_BARSETUP5, IDT_SW_NTP0_BARLIMIT5, 116 IDT_SW_NTP0_BARLTBASE5, IDT_SW_NTP0_BARUTBASE5} } }, 117/*1*/ {0}, 118/*2*/ { IDT_SW_NTP2_PCIECMDSTS, IDT_SW_NTP2_PCIELCTLSTS, 119 IDT_SW_NTP2_NTCTL, 120 IDT_SW_SWPORT2CTL, IDT_SW_SWPORT2STS, 121 { {IDT_SW_NTP2_BARSETUP0, IDT_SW_NTP2_BARLIMIT0, 122 IDT_SW_NTP2_BARLTBASE0, IDT_SW_NTP2_BARUTBASE0}, 123 {IDT_SW_NTP2_BARSETUP1, IDT_SW_NTP2_BARLIMIT1, 124 IDT_SW_NTP2_BARLTBASE1, IDT_SW_NTP2_BARUTBASE1}, 125 {IDT_SW_NTP2_BARSETUP2, IDT_SW_NTP2_BARLIMIT2, 126 IDT_SW_NTP2_BARLTBASE2, IDT_SW_NTP2_BARUTBASE2}, 127 {IDT_SW_NTP2_BARSETUP3, IDT_SW_NTP2_BARLIMIT3, 128 IDT_SW_NTP2_BARLTBASE3, IDT_SW_NTP2_BARUTBASE3}, 129 {IDT_SW_NTP2_BARSETUP4, IDT_SW_NTP2_BARLIMIT4, 130 IDT_SW_NTP2_BARLTBASE4, IDT_SW_NTP2_BARUTBASE4}, 131 {IDT_SW_NTP2_BARSETUP5, IDT_SW_NTP2_BARLIMIT5, 132 IDT_SW_NTP2_BARLTBASE5, IDT_SW_NTP2_BARUTBASE5} } }, 133/*3*/ {0}, 134/*4*/ { IDT_SW_NTP4_PCIECMDSTS, IDT_SW_NTP4_PCIELCTLSTS, 135 IDT_SW_NTP4_NTCTL, 136 IDT_SW_SWPORT4CTL, IDT_SW_SWPORT4STS, 137 { {IDT_SW_NTP4_BARSETUP0, IDT_SW_NTP4_BARLIMIT0, 138 IDT_SW_NTP4_BARLTBASE0, IDT_SW_NTP4_BARUTBASE0}, 139 {IDT_SW_NTP4_BARSETUP1, IDT_SW_NTP4_BARLIMIT1, 140 IDT_SW_NTP4_BARLTBASE1, IDT_SW_NTP4_BARUTBASE1}, 141 {IDT_SW_NTP4_BARSETUP2, IDT_SW_NTP4_BARLIMIT2, 142 IDT_SW_NTP4_BARLTBASE2, IDT_SW_NTP4_BARUTBASE2}, 143 {IDT_SW_NTP4_BARSETUP3, IDT_SW_NTP4_BARLIMIT3, 144 IDT_SW_NTP4_BARLTBASE3, IDT_SW_NTP4_BARUTBASE3}, 145 {IDT_SW_NTP4_BARSETUP4, IDT_SW_NTP4_BARLIMIT4, 146 IDT_SW_NTP4_BARLTBASE4, IDT_SW_NTP4_BARUTBASE4}, 147 {IDT_SW_NTP4_BARSETUP5, IDT_SW_NTP4_BARLIMIT5, 148 IDT_SW_NTP4_BARLTBASE5, IDT_SW_NTP4_BARUTBASE5} } }, 149/*5*/ {0}, 150/*6*/ { IDT_SW_NTP6_PCIECMDSTS, IDT_SW_NTP6_PCIELCTLSTS, 151 IDT_SW_NTP6_NTCTL, 152 IDT_SW_SWPORT6CTL, IDT_SW_SWPORT6STS, 153 { {IDT_SW_NTP6_BARSETUP0, IDT_SW_NTP6_BARLIMIT0, 154 IDT_SW_NTP6_BARLTBASE0, IDT_SW_NTP6_BARUTBASE0}, 155 {IDT_SW_NTP6_BARSETUP1, IDT_SW_NTP6_BARLIMIT1, 156 IDT_SW_NTP6_BARLTBASE1, IDT_SW_NTP6_BARUTBASE1}, 157 {IDT_SW_NTP6_BARSETUP2, IDT_SW_NTP6_BARLIMIT2, 158 IDT_SW_NTP6_BARLTBASE2, IDT_SW_NTP6_BARUTBASE2}, 159 {IDT_SW_NTP6_BARSETUP3, IDT_SW_NTP6_BARLIMIT3, 160 IDT_SW_NTP6_BARLTBASE3, IDT_SW_NTP6_BARUTBASE3}, 161 {IDT_SW_NTP6_BARSETUP4, IDT_SW_NTP6_BARLIMIT4, 162 IDT_SW_NTP6_BARLTBASE4, IDT_SW_NTP6_BARUTBASE4}, 163 {IDT_SW_NTP6_BARSETUP5, IDT_SW_NTP6_BARLIMIT5, 164 IDT_SW_NTP6_BARLTBASE5, IDT_SW_NTP6_BARUTBASE5} } }, 165/*7*/ {0}, 166/*8*/ { IDT_SW_NTP8_PCIECMDSTS, IDT_SW_NTP8_PCIELCTLSTS, 167 IDT_SW_NTP8_NTCTL, 168 IDT_SW_SWPORT8CTL, IDT_SW_SWPORT8STS, 169 { {IDT_SW_NTP8_BARSETUP0, IDT_SW_NTP8_BARLIMIT0, 170 IDT_SW_NTP8_BARLTBASE0, IDT_SW_NTP8_BARUTBASE0}, 171 {IDT_SW_NTP8_BARSETUP1, IDT_SW_NTP8_BARLIMIT1, 172 IDT_SW_NTP8_BARLTBASE1, IDT_SW_NTP8_BARUTBASE1}, 173 {IDT_SW_NTP8_BARSETUP2, IDT_SW_NTP8_BARLIMIT2, 174 IDT_SW_NTP8_BARLTBASE2, IDT_SW_NTP8_BARUTBASE2}, 175 {IDT_SW_NTP8_BARSETUP3, IDT_SW_NTP8_BARLIMIT3, 176 IDT_SW_NTP8_BARLTBASE3, IDT_SW_NTP8_BARUTBASE3}, 177 {IDT_SW_NTP8_BARSETUP4, IDT_SW_NTP8_BARLIMIT4, 178 IDT_SW_NTP8_BARLTBASE4, IDT_SW_NTP8_BARUTBASE4}, 179 {IDT_SW_NTP8_BARSETUP5, IDT_SW_NTP8_BARLIMIT5, 180 IDT_SW_NTP8_BARLTBASE5, IDT_SW_NTP8_BARUTBASE5} } }, 181/*9*/ {0}, 182/*10*/ {0}, 183/*11*/ {0}, 184/*12*/ { IDT_SW_NTP12_PCIECMDSTS, IDT_SW_NTP12_PCIELCTLSTS, 185 IDT_SW_NTP12_NTCTL, 186 IDT_SW_SWPORT12CTL, IDT_SW_SWPORT12STS, 187 { {IDT_SW_NTP12_BARSETUP0, IDT_SW_NTP12_BARLIMIT0, 188 IDT_SW_NTP12_BARLTBASE0, IDT_SW_NTP12_BARUTBASE0}, 189 {IDT_SW_NTP12_BARSETUP1, IDT_SW_NTP12_BARLIMIT1, 190 IDT_SW_NTP12_BARLTBASE1, IDT_SW_NTP12_BARUTBASE1}, 191 {IDT_SW_NTP12_BARSETUP2, IDT_SW_NTP12_BARLIMIT2, 192 IDT_SW_NTP12_BARLTBASE2, IDT_SW_NTP12_BARUTBASE2}, 193 {IDT_SW_NTP12_BARSETUP3, IDT_SW_NTP12_BARLIMIT3, 194 IDT_SW_NTP12_BARLTBASE3, IDT_SW_NTP12_BARUTBASE3}, 195 {IDT_SW_NTP12_BARSETUP4, IDT_SW_NTP12_BARLIMIT4, 196 IDT_SW_NTP12_BARLTBASE4, IDT_SW_NTP12_BARUTBASE4}, 197 {IDT_SW_NTP12_BARSETUP5, IDT_SW_NTP12_BARLIMIT5, 198 IDT_SW_NTP12_BARLTBASE5, IDT_SW_NTP12_BARUTBASE5} } }, 199/*13*/ {0}, 200/*14*/ {0}, 201/*15*/ {0}, 202/*16*/ { IDT_SW_NTP16_PCIECMDSTS, IDT_SW_NTP16_PCIELCTLSTS, 203 IDT_SW_NTP16_NTCTL, 204 IDT_SW_SWPORT16CTL, IDT_SW_SWPORT16STS, 205 { {IDT_SW_NTP16_BARSETUP0, IDT_SW_NTP16_BARLIMIT0, 206 IDT_SW_NTP16_BARLTBASE0, IDT_SW_NTP16_BARUTBASE0}, 207 {IDT_SW_NTP16_BARSETUP1, IDT_SW_NTP16_BARLIMIT1, 208 IDT_SW_NTP16_BARLTBASE1, IDT_SW_NTP16_BARUTBASE1}, 209 {IDT_SW_NTP16_BARSETUP2, IDT_SW_NTP16_BARLIMIT2, 210 IDT_SW_NTP16_BARLTBASE2, IDT_SW_NTP16_BARUTBASE2}, 211 {IDT_SW_NTP16_BARSETUP3, IDT_SW_NTP16_BARLIMIT3, 212 IDT_SW_NTP16_BARLTBASE3, IDT_SW_NTP16_BARUTBASE3}, 213 {IDT_SW_NTP16_BARSETUP4, IDT_SW_NTP16_BARLIMIT4, 214 IDT_SW_NTP16_BARLTBASE4, IDT_SW_NTP16_BARUTBASE4}, 215 {IDT_SW_NTP16_BARSETUP5, IDT_SW_NTP16_BARLIMIT5, 216 IDT_SW_NTP16_BARLTBASE5, IDT_SW_NTP16_BARUTBASE5} } }, 217/*17*/ {0}, 218/*18*/ {0}, 219/*19*/ {0}, 220/*20*/ { IDT_SW_NTP20_PCIECMDSTS, IDT_SW_NTP20_PCIELCTLSTS, 221 IDT_SW_NTP20_NTCTL, 222 IDT_SW_SWPORT20CTL, IDT_SW_SWPORT20STS, 223 { {IDT_SW_NTP20_BARSETUP0, IDT_SW_NTP20_BARLIMIT0, 224 IDT_SW_NTP20_BARLTBASE0, IDT_SW_NTP20_BARUTBASE0}, 225 {IDT_SW_NTP20_BARSETUP1, IDT_SW_NTP20_BARLIMIT1, 226 IDT_SW_NTP20_BARLTBASE1, IDT_SW_NTP20_BARUTBASE1}, 227 {IDT_SW_NTP20_BARSETUP2, IDT_SW_NTP20_BARLIMIT2, 228 IDT_SW_NTP20_BARLTBASE2, IDT_SW_NTP20_BARUTBASE2}, 229 {IDT_SW_NTP20_BARSETUP3, IDT_SW_NTP20_BARLIMIT3, 230 IDT_SW_NTP20_BARLTBASE3, IDT_SW_NTP20_BARUTBASE3}, 231 {IDT_SW_NTP20_BARSETUP4, IDT_SW_NTP20_BARLIMIT4, 232 IDT_SW_NTP20_BARLTBASE4, IDT_SW_NTP20_BARUTBASE4}, 233 {IDT_SW_NTP20_BARSETUP5, IDT_SW_NTP20_BARLIMIT5, 234 IDT_SW_NTP20_BARLTBASE5, IDT_SW_NTP20_BARUTBASE5} } }, 235/*21*/ {0}, 236/*22*/ {0}, 237/*23*/ {0} 238}; 239 240/* 241 * IDT PCIe-switch partitions table with the corresponding control, status 242 * and messages control registers 243 */ 244static const struct idt_ntb_part partdata_tbl[IDT_MAX_NR_PARTS] = { 245/*0*/ { IDT_SW_SWPART0CTL, IDT_SW_SWPART0STS, 246 {IDT_SW_SWP0MSGCTL0, IDT_SW_SWP0MSGCTL1, 247 IDT_SW_SWP0MSGCTL2, IDT_SW_SWP0MSGCTL3} }, 248/*1*/ { IDT_SW_SWPART1CTL, IDT_SW_SWPART1STS, 249 {IDT_SW_SWP1MSGCTL0, IDT_SW_SWP1MSGCTL1, 250 IDT_SW_SWP1MSGCTL2, IDT_SW_SWP1MSGCTL3} }, 251/*2*/ { IDT_SW_SWPART2CTL, IDT_SW_SWPART2STS, 252 {IDT_SW_SWP2MSGCTL0, IDT_SW_SWP2MSGCTL1, 253 IDT_SW_SWP2MSGCTL2, IDT_SW_SWP2MSGCTL3} }, 254/*3*/ { IDT_SW_SWPART3CTL, IDT_SW_SWPART3STS, 255 {IDT_SW_SWP3MSGCTL0, IDT_SW_SWP3MSGCTL1, 256 IDT_SW_SWP3MSGCTL2, IDT_SW_SWP3MSGCTL3} }, 257/*4*/ { IDT_SW_SWPART4CTL, IDT_SW_SWPART4STS, 258 {IDT_SW_SWP4MSGCTL0, IDT_SW_SWP4MSGCTL1, 259 IDT_SW_SWP4MSGCTL2, IDT_SW_SWP4MSGCTL3} }, 260/*5*/ { IDT_SW_SWPART5CTL, IDT_SW_SWPART5STS, 261 {IDT_SW_SWP5MSGCTL0, IDT_SW_SWP5MSGCTL1, 262 IDT_SW_SWP5MSGCTL2, IDT_SW_SWP5MSGCTL3} }, 263/*6*/ { IDT_SW_SWPART6CTL, IDT_SW_SWPART6STS, 264 {IDT_SW_SWP6MSGCTL0, IDT_SW_SWP6MSGCTL1, 265 IDT_SW_SWP6MSGCTL2, IDT_SW_SWP6MSGCTL3} }, 266/*7*/ { IDT_SW_SWPART7CTL, IDT_SW_SWPART7STS, 267 {IDT_SW_SWP7MSGCTL0, IDT_SW_SWP7MSGCTL1, 268 IDT_SW_SWP7MSGCTL2, IDT_SW_SWP7MSGCTL3} } 269}; 270 271/* 272 * DebugFS directory to place the driver debug file 273 */ 274static struct dentry *dbgfs_topdir; 275 276/*============================================================================= 277 * 1. IDT PCIe-switch registers IO-functions 278 * 279 * Beside ordinary configuration space registers IDT PCIe-switch expose 280 * global configuration registers, which are used to determine state of other 281 * device ports as well as being notified of some switch-related events. 282 * Additionally all the configuration space registers of all the IDT 283 * PCIe-switch functions are mapped to the Global Address space, so each 284 * function can determine a configuration of any other PCI-function. 285 * Functions declared in this chapter are created to encapsulate access 286 * to configuration and global registers, so the driver code just need to 287 * provide IDT NTB hardware descriptor and a register address. 288 *============================================================================= 289 */ 290 291/* 292 * idt_nt_write() - PCI configuration space registers write method 293 * @ndev: IDT NTB hardware driver descriptor 294 * @reg: Register to write data to 295 * @data: Value to write to the register 296 * 297 * IDT PCIe-switch registers are all Little endian. 298 */ 299static void idt_nt_write(struct idt_ntb_dev *ndev, 300 const unsigned int reg, const u32 data) 301{ 302 /* 303 * It's obvious bug to request a register exceeding the maximum possible 304 * value as well as to have it unaligned. 305 */ 306 if (WARN_ON(reg > IDT_REG_PCI_MAX || !IS_ALIGNED(reg, IDT_REG_ALIGN))) 307 return; 308 309 /* Just write the value to the specified register */ 310 iowrite32(data, ndev->cfgspc + (ptrdiff_t)reg); 311} 312 313/* 314 * idt_nt_read() - PCI configuration space registers read method 315 * @ndev: IDT NTB hardware driver descriptor 316 * @reg: Register to write data to 317 * 318 * IDT PCIe-switch Global configuration registers are all Little endian. 319 * 320 * Return: register value 321 */ 322static u32 idt_nt_read(struct idt_ntb_dev *ndev, const unsigned int reg) 323{ 324 /* 325 * It's obvious bug to request a register exceeding the maximum possible 326 * value as well as to have it unaligned. 327 */ 328 if (WARN_ON(reg > IDT_REG_PCI_MAX || !IS_ALIGNED(reg, IDT_REG_ALIGN))) 329 return ~0; 330 331 /* Just read the value from the specified register */ 332 return ioread32(ndev->cfgspc + (ptrdiff_t)reg); 333} 334 335/* 336 * idt_sw_write() - Global registers write method 337 * @ndev: IDT NTB hardware driver descriptor 338 * @reg: Register to write data to 339 * @data: Value to write to the register 340 * 341 * IDT PCIe-switch Global configuration registers are all Little endian. 342 */ 343static void idt_sw_write(struct idt_ntb_dev *ndev, 344 const unsigned int reg, const u32 data) 345{ 346 unsigned long irqflags; 347 348 /* 349 * It's obvious bug to request a register exceeding the maximum possible 350 * value as well as to have it unaligned. 351 */ 352 if (WARN_ON(reg > IDT_REG_SW_MAX || !IS_ALIGNED(reg, IDT_REG_ALIGN))) 353 return; 354 355 /* Lock GASA registers operations */ 356 spin_lock_irqsave(&ndev->gasa_lock, irqflags); 357 /* Set the global register address */ 358 iowrite32((u32)reg, ndev->cfgspc + (ptrdiff_t)IDT_NT_GASAADDR); 359 /* Put the new value of the register */ 360 iowrite32(data, ndev->cfgspc + (ptrdiff_t)IDT_NT_GASADATA); 361 /* Unlock GASA registers operations */ 362 spin_unlock_irqrestore(&ndev->gasa_lock, irqflags); 363} 364 365/* 366 * idt_sw_read() - Global registers read method 367 * @ndev: IDT NTB hardware driver descriptor 368 * @reg: Register to write data to 369 * 370 * IDT PCIe-switch Global configuration registers are all Little endian. 371 * 372 * Return: register value 373 */ 374static u32 idt_sw_read(struct idt_ntb_dev *ndev, const unsigned int reg) 375{ 376 unsigned long irqflags; 377 u32 data; 378 379 /* 380 * It's obvious bug to request a register exceeding the maximum possible 381 * value as well as to have it unaligned. 382 */ 383 if (WARN_ON(reg > IDT_REG_SW_MAX || !IS_ALIGNED(reg, IDT_REG_ALIGN))) 384 return ~0; 385 386 /* Lock GASA registers operations */ 387 spin_lock_irqsave(&ndev->gasa_lock, irqflags); 388 /* Set the global register address */ 389 iowrite32((u32)reg, ndev->cfgspc + (ptrdiff_t)IDT_NT_GASAADDR); 390 /* Get the data of the register (read ops acts as MMIO barrier) */ 391 data = ioread32(ndev->cfgspc + (ptrdiff_t)IDT_NT_GASADATA); 392 /* Unlock GASA registers operations */ 393 spin_unlock_irqrestore(&ndev->gasa_lock, irqflags); 394 395 return data; 396} 397 398/* 399 * idt_reg_set_bits() - set bits of a passed register 400 * @ndev: IDT NTB hardware driver descriptor 401 * @reg: Register to change bits of 402 * @reg_lock: Register access spin lock 403 * @valid_mask: Mask of valid bits 404 * @set_bits: Bitmask to set 405 * 406 * Helper method to check whether a passed bitfield is valid and set 407 * corresponding bits of a register. 408 * 409 * WARNING! Make sure the passed register isn't accessed over plane 410 * idt_nt_write() method (read method is ok to be used concurrently). 411 * 412 * Return: zero on success, negative error on invalid bitmask. 413 */ 414static inline int idt_reg_set_bits(struct idt_ntb_dev *ndev, unsigned int reg, 415 spinlock_t *reg_lock, 416 u64 valid_mask, u64 set_bits) 417{ 418 unsigned long irqflags; 419 u32 data; 420 421 if (set_bits & ~(u64)valid_mask) 422 return -EINVAL; 423 424 /* Lock access to the register unless the change is written back */ 425 spin_lock_irqsave(reg_lock, irqflags); 426 data = idt_nt_read(ndev, reg) | (u32)set_bits; 427 idt_nt_write(ndev, reg, data); 428 /* Unlock the register */ 429 spin_unlock_irqrestore(reg_lock, irqflags); 430 431 return 0; 432} 433 434/* 435 * idt_reg_clear_bits() - clear bits of a passed register 436 * @ndev: IDT NTB hardware driver descriptor 437 * @reg: Register to change bits of 438 * @reg_lock: Register access spin lock 439 * @set_bits: Bitmask to clear 440 * 441 * Helper method to check whether a passed bitfield is valid and clear 442 * corresponding bits of a register. 443 * 444 * NOTE! Invalid bits are always considered cleared so it's not an error 445 * to clear them over. 446 * 447 * WARNING! Make sure the passed register isn't accessed over plane 448 * idt_nt_write() method (read method is ok to use concurrently). 449 */ 450static inline void idt_reg_clear_bits(struct idt_ntb_dev *ndev, 451 unsigned int reg, spinlock_t *reg_lock, 452 u64 clear_bits) 453{ 454 unsigned long irqflags; 455 u32 data; 456 457 /* Lock access to the register unless the change is written back */ 458 spin_lock_irqsave(reg_lock, irqflags); 459 data = idt_nt_read(ndev, reg) & ~(u32)clear_bits; 460 idt_nt_write(ndev, reg, data); 461 /* Unlock the register */ 462 spin_unlock_irqrestore(reg_lock, irqflags); 463} 464 465/*=========================================================================== 466 * 2. Ports operations 467 * 468 * IDT PCIe-switches can have from 3 up to 8 ports with possible 469 * NT-functions enabled. So all the possible ports need to be scanned looking 470 * for NTB activated. NTB API will have enumerated only the ports with NTB. 471 *=========================================================================== 472 */ 473 474/* 475 * idt_scan_ports() - scan IDT PCIe-switch ports collecting info in the tables 476 * @ndev: Pointer to the PCI device descriptor 477 * 478 * Return: zero on success, otherwise a negative error number. 479 */ 480static int idt_scan_ports(struct idt_ntb_dev *ndev) 481{ 482 unsigned char pidx, port, part; 483 u32 data, portsts, partsts; 484 485 /* Retrieve the local port number */ 486 data = idt_nt_read(ndev, IDT_NT_PCIELCAP); 487 ndev->port = GET_FIELD(PCIELCAP_PORTNUM, data); 488 489 /* Retrieve the local partition number */ 490 portsts = idt_sw_read(ndev, portdata_tbl[ndev->port].sts); 491 ndev->part = GET_FIELD(SWPORTxSTS_SWPART, portsts); 492 493 /* Initialize port/partition -> index tables with invalid values */ 494 memset(ndev->port_idx_map, -EINVAL, sizeof(ndev->port_idx_map)); 495 memset(ndev->part_idx_map, -EINVAL, sizeof(ndev->part_idx_map)); 496 497 /* 498 * Walk over all the possible ports checking whether any of them has 499 * NT-function activated 500 */ 501 ndev->peer_cnt = 0; 502 for (pidx = 0; pidx < ndev->swcfg->port_cnt; pidx++) { 503 port = ndev->swcfg->ports[pidx]; 504 /* Skip local port */ 505 if (port == ndev->port) 506 continue; 507 508 /* Read the port status register to get it partition */ 509 portsts = idt_sw_read(ndev, portdata_tbl[port].sts); 510 part = GET_FIELD(SWPORTxSTS_SWPART, portsts); 511 512 /* Retrieve the partition status */ 513 partsts = idt_sw_read(ndev, partdata_tbl[part].sts); 514 /* Check if partition state is active and port has NTB */ 515 if (IS_FLD_SET(SWPARTxSTS_STATE, partsts, ACT) && 516 (IS_FLD_SET(SWPORTxSTS_MODE, portsts, NT) || 517 IS_FLD_SET(SWPORTxSTS_MODE, portsts, USNT) || 518 IS_FLD_SET(SWPORTxSTS_MODE, portsts, USNTDMA) || 519 IS_FLD_SET(SWPORTxSTS_MODE, portsts, NTDMA))) { 520 /* Save the port and partition numbers */ 521 ndev->peers[ndev->peer_cnt].port = port; 522 ndev->peers[ndev->peer_cnt].part = part; 523 /* Fill in the port/partition -> index tables */ 524 ndev->port_idx_map[port] = ndev->peer_cnt; 525 ndev->part_idx_map[part] = ndev->peer_cnt; 526 ndev->peer_cnt++; 527 } 528 } 529 530 dev_dbg(&ndev->ntb.pdev->dev, "Local port: %hhu, num of peers: %hhu\n", 531 ndev->port, ndev->peer_cnt); 532 533 /* It's useless to have this driver loaded if there is no any peer */ 534 if (ndev->peer_cnt == 0) { 535 dev_warn(&ndev->ntb.pdev->dev, "No active peer found\n"); 536 return -ENODEV; 537 } 538 539 return 0; 540} 541 542/* 543 * idt_ntb_port_number() - get the local port number 544 * @ntb: NTB device context. 545 * 546 * Return: the local port number 547 */ 548static int idt_ntb_port_number(struct ntb_dev *ntb) 549{ 550 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 551 552 return ndev->port; 553} 554 555/* 556 * idt_ntb_peer_port_count() - get the number of peer ports 557 * @ntb: NTB device context. 558 * 559 * Return the count of detected peer NT-functions. 560 * 561 * Return: number of peer ports 562 */ 563static int idt_ntb_peer_port_count(struct ntb_dev *ntb) 564{ 565 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 566 567 return ndev->peer_cnt; 568} 569 570/* 571 * idt_ntb_peer_port_number() - get peer port by given index 572 * @ntb: NTB device context. 573 * @pidx: Peer port index. 574 * 575 * Return: peer port or negative error 576 */ 577static int idt_ntb_peer_port_number(struct ntb_dev *ntb, int pidx) 578{ 579 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 580 581 if (pidx < 0 || ndev->peer_cnt <= pidx) 582 return -EINVAL; 583 584 /* Return the detected NT-function port number */ 585 return ndev->peers[pidx].port; 586} 587 588/* 589 * idt_ntb_peer_port_idx() - get peer port index by given port number 590 * @ntb: NTB device context. 591 * @port: Peer port number. 592 * 593 * Internal port -> index table is pre-initialized with -EINVAL values, 594 * so we just need to return it value 595 * 596 * Return: peer NT-function port index or negative error 597 */ 598static int idt_ntb_peer_port_idx(struct ntb_dev *ntb, int port) 599{ 600 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 601 602 if (port < 0 || IDT_MAX_NR_PORTS <= port) 603 return -EINVAL; 604 605 return ndev->port_idx_map[port]; 606} 607 608/*=========================================================================== 609 * 3. Link status operations 610 * There is no any ready-to-use method to have peer ports notified if NTB 611 * link is set up or got down. Instead global signal can be used instead. 612 * In case if any one of ports changes local NTB link state, it sends 613 * global signal and clears corresponding global state bit. Then all the ports 614 * receive a notification of that, so to make client driver being aware of 615 * possible NTB link change. 616 * Additionally each of active NT-functions is subscribed to PCIe-link 617 * state changes of peer ports. 618 *=========================================================================== 619 */ 620 621static void idt_ntb_local_link_disable(struct idt_ntb_dev *ndev); 622 623/* 624 * idt_init_link() - Initialize NTB link state notification subsystem 625 * @ndev: IDT NTB hardware driver descriptor 626 * 627 * Function performs the basic initialization of some global registers 628 * needed to enable IRQ-based notifications of PCIe Link Up/Down and 629 * Global Signal events. 630 * NOTE Since it's not possible to determine when all the NTB peer drivers are 631 * unloaded as well as have those registers accessed concurrently, we must 632 * preinitialize them with the same value and leave it uncleared on local 633 * driver unload. 634 */ 635static void idt_init_link(struct idt_ntb_dev *ndev) 636{ 637 u32 part_mask, port_mask, se_mask; 638 unsigned char pidx; 639 640 /* Initialize spin locker of Mapping Table access registers */ 641 spin_lock_init(&ndev->mtbl_lock); 642 643 /* Walk over all detected peers collecting port and partition masks */ 644 port_mask = ~BIT(ndev->port); 645 part_mask = ~BIT(ndev->part); 646 for (pidx = 0; pidx < ndev->peer_cnt; pidx++) { 647 port_mask &= ~BIT(ndev->peers[pidx].port); 648 part_mask &= ~BIT(ndev->peers[pidx].part); 649 } 650 651 /* Clean the Link Up/Down and GLobal Signal status registers */ 652 idt_sw_write(ndev, IDT_SW_SELINKUPSTS, (u32)-1); 653 idt_sw_write(ndev, IDT_SW_SELINKDNSTS, (u32)-1); 654 idt_sw_write(ndev, IDT_SW_SEGSIGSTS, (u32)-1); 655 656 /* Unmask NT-activated partitions to receive Global Switch events */ 657 idt_sw_write(ndev, IDT_SW_SEPMSK, part_mask); 658 659 /* Enable PCIe Link Up events of NT-activated ports */ 660 idt_sw_write(ndev, IDT_SW_SELINKUPMSK, port_mask); 661 662 /* Enable PCIe Link Down events of NT-activated ports */ 663 idt_sw_write(ndev, IDT_SW_SELINKDNMSK, port_mask); 664 665 /* Unmask NT-activated partitions to receive Global Signal events */ 666 idt_sw_write(ndev, IDT_SW_SEGSIGMSK, part_mask); 667 668 /* Unmask Link Up/Down and Global Switch Events */ 669 se_mask = ~(IDT_SEMSK_LINKUP | IDT_SEMSK_LINKDN | IDT_SEMSK_GSIGNAL); 670 idt_sw_write(ndev, IDT_SW_SEMSK, se_mask); 671 672 dev_dbg(&ndev->ntb.pdev->dev, "NTB link status events initialized"); 673} 674 675/* 676 * idt_deinit_link() - deinitialize link subsystem 677 * @ndev: IDT NTB hardware driver descriptor 678 * 679 * Just disable the link back. 680 */ 681static void idt_deinit_link(struct idt_ntb_dev *ndev) 682{ 683 /* Disable the link */ 684 idt_ntb_local_link_disable(ndev); 685 686 dev_dbg(&ndev->ntb.pdev->dev, "NTB link status events deinitialized"); 687} 688 689/* 690 * idt_se_isr() - switch events ISR 691 * @ndev: IDT NTB hardware driver descriptor 692 * @ntint_sts: NT-function interrupt status 693 * 694 * This driver doesn't support IDT PCIe-switch dynamic reconfigurations, 695 * Failover capability, etc, so switch events are utilized to notify of 696 * PCIe and NTB link events. 697 * The method is called from PCIe ISR bottom-half routine. 698 */ 699static void idt_se_isr(struct idt_ntb_dev *ndev, u32 ntint_sts) 700{ 701 u32 sests; 702 703 /* Read Switch Events status */ 704 sests = idt_sw_read(ndev, IDT_SW_SESTS); 705 706 /* Clean the Link Up/Down and Global Signal status registers */ 707 idt_sw_write(ndev, IDT_SW_SELINKUPSTS, (u32)-1); 708 idt_sw_write(ndev, IDT_SW_SELINKDNSTS, (u32)-1); 709 idt_sw_write(ndev, IDT_SW_SEGSIGSTS, (u32)-1); 710 711 /* Clean the corresponding interrupt bit */ 712 idt_nt_write(ndev, IDT_NT_NTINTSTS, IDT_NTINTSTS_SEVENT); 713 714 dev_dbg(&ndev->ntb.pdev->dev, "SE IRQ detected %#08x (SESTS %#08x)", 715 ntint_sts, sests); 716 717 /* Notify the client driver of possible link state change */ 718 ntb_link_event(&ndev->ntb); 719} 720 721/* 722 * idt_ntb_local_link_enable() - enable the local NTB link. 723 * @ndev: IDT NTB hardware driver descriptor 724 * 725 * In order to enable the NTB link we need: 726 * - enable Completion TLPs translation 727 * - initialize mapping table to enable the Request ID translation 728 * - notify peers of NTB link state change 729 */ 730static void idt_ntb_local_link_enable(struct idt_ntb_dev *ndev) 731{ 732 u32 reqid, mtbldata = 0; 733 unsigned long irqflags; 734 735 /* Enable the ID protection and Completion TLPs translation */ 736 idt_nt_write(ndev, IDT_NT_NTCTL, IDT_NTCTL_CPEN); 737 738 /* Retrieve the current Requester ID (Bus:Device:Function) */ 739 reqid = idt_nt_read(ndev, IDT_NT_REQIDCAP); 740 741 /* 742 * Set the corresponding NT Mapping table entry of port partition index 743 * with the data to perform the Request ID translation 744 */ 745 mtbldata = SET_FIELD(NTMTBLDATA_REQID, 0, reqid) | 746 SET_FIELD(NTMTBLDATA_PART, 0, ndev->part) | 747 IDT_NTMTBLDATA_VALID; 748 spin_lock_irqsave(&ndev->mtbl_lock, irqflags); 749 idt_nt_write(ndev, IDT_NT_NTMTBLADDR, ndev->part); 750 idt_nt_write(ndev, IDT_NT_NTMTBLDATA, mtbldata); 751 spin_unlock_irqrestore(&ndev->mtbl_lock, irqflags); 752 753 /* Notify the peers by setting and clearing the global signal bit */ 754 idt_nt_write(ndev, IDT_NT_NTGSIGNAL, IDT_NTGSIGNAL_SET); 755 idt_sw_write(ndev, IDT_SW_SEGSIGSTS, (u32)1 << ndev->part); 756} 757 758/* 759 * idt_ntb_local_link_disable() - disable the local NTB link. 760 * @ndev: IDT NTB hardware driver descriptor 761 * 762 * In order to enable the NTB link we need: 763 * - disable Completion TLPs translation 764 * - clear corresponding mapping table entry 765 * - notify peers of NTB link state change 766 */ 767static void idt_ntb_local_link_disable(struct idt_ntb_dev *ndev) 768{ 769 unsigned long irqflags; 770 771 /* Disable Completion TLPs translation */ 772 idt_nt_write(ndev, IDT_NT_NTCTL, 0); 773 774 /* Clear the corresponding NT Mapping table entry */ 775 spin_lock_irqsave(&ndev->mtbl_lock, irqflags); 776 idt_nt_write(ndev, IDT_NT_NTMTBLADDR, ndev->part); 777 idt_nt_write(ndev, IDT_NT_NTMTBLDATA, 0); 778 spin_unlock_irqrestore(&ndev->mtbl_lock, irqflags); 779 780 /* Notify the peers by setting and clearing the global signal bit */ 781 idt_nt_write(ndev, IDT_NT_NTGSIGNAL, IDT_NTGSIGNAL_SET); 782 idt_sw_write(ndev, IDT_SW_SEGSIGSTS, (u32)1 << ndev->part); 783} 784 785/* 786 * idt_ntb_local_link_is_up() - test wethter local NTB link is up 787 * @ndev: IDT NTB hardware driver descriptor 788 * 789 * Local link is up under the following conditions: 790 * - Bus mastering is enabled 791 * - NTCTL has Completion TLPs translation enabled 792 * - Mapping table permits Request TLPs translation 793 * NOTE: We don't need to check PCIe link state since it's obviously 794 * up while we are able to communicate with IDT PCIe-switch 795 * 796 * Return: true if link is up, otherwise false 797 */ 798static bool idt_ntb_local_link_is_up(struct idt_ntb_dev *ndev) 799{ 800 unsigned long irqflags; 801 u32 data; 802 803 /* Read the local Bus Master Enable status */ 804 data = idt_nt_read(ndev, IDT_NT_PCICMDSTS); 805 if (!(data & IDT_PCICMDSTS_BME)) 806 return false; 807 808 /* Read the local Completion TLPs translation enable status */ 809 data = idt_nt_read(ndev, IDT_NT_NTCTL); 810 if (!(data & IDT_NTCTL_CPEN)) 811 return false; 812 813 /* Read Mapping table entry corresponding to the local partition */ 814 spin_lock_irqsave(&ndev->mtbl_lock, irqflags); 815 idt_nt_write(ndev, IDT_NT_NTMTBLADDR, ndev->part); 816 data = idt_nt_read(ndev, IDT_NT_NTMTBLDATA); 817 spin_unlock_irqrestore(&ndev->mtbl_lock, irqflags); 818 819 return !!(data & IDT_NTMTBLDATA_VALID); 820} 821 822/* 823 * idt_ntb_peer_link_is_up() - test whether peer NTB link is up 824 * @ndev: IDT NTB hardware driver descriptor 825 * @pidx: Peer port index 826 * 827 * Peer link is up under the following conditions: 828 * - PCIe link is up 829 * - Bus mastering is enabled 830 * - NTCTL has Completion TLPs translation enabled 831 * - Mapping table permits Request TLPs translation 832 * 833 * Return: true if link is up, otherwise false 834 */ 835static bool idt_ntb_peer_link_is_up(struct idt_ntb_dev *ndev, int pidx) 836{ 837 unsigned long irqflags; 838 unsigned char port; 839 u32 data; 840 841 /* Retrieve the device port number */ 842 port = ndev->peers[pidx].port; 843 844 /* Check whether PCIe link is up */ 845 data = idt_sw_read(ndev, portdata_tbl[port].sts); 846 if (!(data & IDT_SWPORTxSTS_LINKUP)) 847 return false; 848 849 /* Check whether bus mastering is enabled on the peer port */ 850 data = idt_sw_read(ndev, portdata_tbl[port].pcicmdsts); 851 if (!(data & IDT_PCICMDSTS_BME)) 852 return false; 853 854 /* Check if Completion TLPs translation is enabled on the peer port */ 855 data = idt_sw_read(ndev, portdata_tbl[port].ntctl); 856 if (!(data & IDT_NTCTL_CPEN)) 857 return false; 858 859 /* Read Mapping table entry corresponding to the peer partition */ 860 spin_lock_irqsave(&ndev->mtbl_lock, irqflags); 861 idt_nt_write(ndev, IDT_NT_NTMTBLADDR, ndev->peers[pidx].part); 862 data = idt_nt_read(ndev, IDT_NT_NTMTBLDATA); 863 spin_unlock_irqrestore(&ndev->mtbl_lock, irqflags); 864 865 return !!(data & IDT_NTMTBLDATA_VALID); 866} 867 868/* 869 * idt_ntb_link_is_up() - get the current ntb link state (NTB API callback) 870 * @ntb: NTB device context. 871 * @speed: OUT - The link speed expressed as PCIe generation number. 872 * @width: OUT - The link width expressed as the number of PCIe lanes. 873 * 874 * Get the bitfield of NTB link states for all peer ports 875 * 876 * Return: bitfield of indexed ports link state: bit is set/cleared if the 877 * link is up/down respectively. 878 */ 879static u64 idt_ntb_link_is_up(struct ntb_dev *ntb, 880 enum ntb_speed *speed, enum ntb_width *width) 881{ 882 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 883 unsigned char pidx; 884 u64 status; 885 u32 data; 886 887 /* Retrieve the local link speed and width */ 888 if (speed != NULL || width != NULL) { 889 data = idt_nt_read(ndev, IDT_NT_PCIELCTLSTS); 890 if (speed != NULL) 891 *speed = GET_FIELD(PCIELCTLSTS_CLS, data); 892 if (width != NULL) 893 *width = GET_FIELD(PCIELCTLSTS_NLW, data); 894 } 895 896 /* If local NTB link isn't up then all the links are considered down */ 897 if (!idt_ntb_local_link_is_up(ndev)) 898 return 0; 899 900 /* Collect all the peer ports link states into the bitfield */ 901 status = 0; 902 for (pidx = 0; pidx < ndev->peer_cnt; pidx++) { 903 if (idt_ntb_peer_link_is_up(ndev, pidx)) 904 status |= ((u64)1 << pidx); 905 } 906 907 return status; 908} 909 910/* 911 * idt_ntb_link_enable() - enable local port ntb link (NTB API callback) 912 * @ntb: NTB device context. 913 * @max_speed: The maximum link speed expressed as PCIe generation number. 914 * @max_width: The maximum link width expressed as the number of PCIe lanes. 915 * 916 * Enable just local NTB link. PCIe link parameters are ignored. 917 * 918 * Return: always zero. 919 */ 920static int idt_ntb_link_enable(struct ntb_dev *ntb, enum ntb_speed speed, 921 enum ntb_width width) 922{ 923 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 924 925 /* Just enable the local NTB link */ 926 idt_ntb_local_link_enable(ndev); 927 928 dev_dbg(&ndev->ntb.pdev->dev, "Local NTB link enabled"); 929 930 return 0; 931} 932 933/* 934 * idt_ntb_link_disable() - disable local port ntb link (NTB API callback) 935 * @ntb: NTB device context. 936 * 937 * Disable just local NTB link. 938 * 939 * Return: always zero. 940 */ 941static int idt_ntb_link_disable(struct ntb_dev *ntb) 942{ 943 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 944 945 /* Just disable the local NTB link */ 946 idt_ntb_local_link_disable(ndev); 947 948 dev_dbg(&ndev->ntb.pdev->dev, "Local NTB link disabled"); 949 950 return 0; 951} 952 953/*============================================================================= 954 * 4. Memory Window operations 955 * 956 * IDT PCIe-switches have two types of memory windows: MWs with direct 957 * address translation and MWs with LUT based translation. The first type of 958 * MWs is simple map of corresponding BAR address space to a memory space 959 * of specified target port. So it implemets just ont-to-one mapping. Lookup 960 * table in its turn can map one BAR address space to up to 24 different 961 * memory spaces of different ports. 962 * NT-functions BARs can be turned on to implement either direct or lookup 963 * table based address translations, so: 964 * BAR0 - NT configuration registers space/direct address translation 965 * BAR1 - direct address translation/upper address of BAR0x64 966 * BAR2 - direct address translation/Lookup table with either 12 or 24 entries 967 * BAR3 - direct address translation/upper address of BAR2x64 968 * BAR4 - direct address translation/Lookup table with either 12 or 24 entries 969 * BAR5 - direct address translation/upper address of BAR4x64 970 * Additionally BAR2 and BAR4 can't have 24-entries LUT enabled at the same 971 * time. Since the BARs setup can be rather complicated this driver implements 972 * a scanning algorithm to have all the possible memory windows configuration 973 * covered. 974 * 975 * NOTE 1 BAR setup must be done before Linux kernel enumerated NT-function 976 * of any port, so this driver would have memory windows configurations fixed. 977 * In this way all initializations must be performed either by platform BIOS 978 * or using EEPROM connected to IDT PCIe-switch master SMBus. 979 * 980 * NOTE 2 This driver expects BAR0 mapping NT-function configuration space. 981 * Easy calculation can give us an upper boundary of 29 possible memory windows 982 * per each NT-function if all the BARs are of 32bit type. 983 *============================================================================= 984 */ 985 986/* 987 * idt_get_mw_count() - get memory window count 988 * @mw_type: Memory window type 989 * 990 * Return: number of memory windows with respect to the BAR type 991 */ 992static inline unsigned char idt_get_mw_count(enum idt_mw_type mw_type) 993{ 994 switch (mw_type) { 995 case IDT_MW_DIR: 996 return 1; 997 case IDT_MW_LUT12: 998 return 12; 999 case IDT_MW_LUT24: 1000 return 24; 1001 default: 1002 break; 1003 } 1004 1005 return 0; 1006} 1007 1008/* 1009 * idt_get_mw_name() - get memory window name 1010 * @mw_type: Memory window type 1011 * 1012 * Return: pointer to a string with name 1013 */ 1014static inline char *idt_get_mw_name(enum idt_mw_type mw_type) 1015{ 1016 switch (mw_type) { 1017 case IDT_MW_DIR: 1018 return "DIR "; 1019 case IDT_MW_LUT12: 1020 return "LUT12"; 1021 case IDT_MW_LUT24: 1022 return "LUT24"; 1023 default: 1024 break; 1025 } 1026 1027 return "unknown"; 1028} 1029 1030/* 1031 * idt_scan_mws() - scan memory windows of the port 1032 * @ndev: IDT NTB hardware driver descriptor 1033 * @port: Port to get number of memory windows for 1034 * @mw_cnt: Out - number of memory windows 1035 * 1036 * It walks over BAR setup registers of the specified port and determines 1037 * the memory windows parameters if any activated. 1038 * 1039 * Return: array of memory windows 1040 */ 1041static struct idt_mw_cfg *idt_scan_mws(struct idt_ntb_dev *ndev, int port, 1042 unsigned char *mw_cnt) 1043{ 1044 struct idt_mw_cfg *mws; 1045 const struct idt_ntb_bar *bars; 1046 enum idt_mw_type mw_type; 1047 unsigned char widx, bidx, en_cnt; 1048 bool bar_64bit = false; 1049 int aprt_size; 1050 u32 data; 1051 1052 mws = devm_kcalloc(&ndev->ntb.pdev->dev, IDT_MAX_NR_MWS, 1053 sizeof(*mws), GFP_KERNEL); 1054 if (!mws) 1055 return ERR_PTR(-ENOMEM); 1056 1057 /* Retrieve the array of the BARs registers */ 1058 bars = portdata_tbl[port].bars; 1059 1060 /* Scan all the BARs belonging to the port */ 1061 *mw_cnt = 0; 1062 for (bidx = 0; bidx < IDT_BAR_CNT; bidx += 1 + bar_64bit) { 1063 /* Read BARSETUP register value */ 1064 data = idt_sw_read(ndev, bars[bidx].setup); 1065 1066 /* Skip disabled BARs */ 1067 if (!(data & IDT_BARSETUP_EN)) { 1068 bar_64bit = false; 1069 continue; 1070 } 1071 1072 /* Skip next BARSETUP if current one has 64bit addressing */ 1073 bar_64bit = IS_FLD_SET(BARSETUP_TYPE, data, 64); 1074 1075 /* Skip configuration space mapping BARs */ 1076 if (data & IDT_BARSETUP_MODE_CFG) 1077 continue; 1078 1079 /* Retrieve MW type/entries count and aperture size */ 1080 mw_type = GET_FIELD(BARSETUP_ATRAN, data); 1081 en_cnt = idt_get_mw_count(mw_type); 1082 aprt_size = (u64)1 << GET_FIELD(BARSETUP_SIZE, data); 1083 1084 /* Save configurations of all available memory windows */ 1085 for (widx = 0; widx < en_cnt; widx++, (*mw_cnt)++) { 1086 /* 1087 * IDT can expose a limited number of MWs, so it's bug 1088 * to have more than the driver expects 1089 */ 1090 if (*mw_cnt >= IDT_MAX_NR_MWS) 1091 return ERR_PTR(-EINVAL); 1092 1093 /* Save basic MW info */ 1094 mws[*mw_cnt].type = mw_type; 1095 mws[*mw_cnt].bar = bidx; 1096 mws[*mw_cnt].idx = widx; 1097 /* It's always DWORD aligned */ 1098 mws[*mw_cnt].addr_align = IDT_TRANS_ALIGN; 1099 /* DIR and LUT approachs differently configure MWs */ 1100 if (mw_type == IDT_MW_DIR) 1101 mws[*mw_cnt].size_max = aprt_size; 1102 else if (mw_type == IDT_MW_LUT12) 1103 mws[*mw_cnt].size_max = aprt_size / 16; 1104 else 1105 mws[*mw_cnt].size_max = aprt_size / 32; 1106 mws[*mw_cnt].size_align = (mw_type == IDT_MW_DIR) ? 1107 IDT_DIR_SIZE_ALIGN : mws[*mw_cnt].size_max; 1108 } 1109 } 1110 1111 return mws; 1112} 1113 1114/* 1115 * idt_init_mws() - initialize memory windows subsystem 1116 * @ndev: IDT NTB hardware driver descriptor 1117 * 1118 * Scan BAR setup registers of local and peer ports to determine the 1119 * outbound and inbound memory windows parameters 1120 * 1121 * Return: zero on success, otherwise a negative error number 1122 */ 1123static int idt_init_mws(struct idt_ntb_dev *ndev) 1124{ 1125 struct idt_ntb_peer *peer; 1126 unsigned char pidx; 1127 1128 /* Scan memory windows of the local port */ 1129 ndev->mws = idt_scan_mws(ndev, ndev->port, &ndev->mw_cnt); 1130 if (IS_ERR(ndev->mws)) { 1131 dev_err(&ndev->ntb.pdev->dev, 1132 "Failed to scan mws of local port %hhu", ndev->port); 1133 return PTR_ERR(ndev->mws); 1134 } 1135 1136 /* Scan memory windows of the peer ports */ 1137 for (pidx = 0; pidx < ndev->peer_cnt; pidx++) { 1138 peer = &ndev->peers[pidx]; 1139 peer->mws = idt_scan_mws(ndev, peer->port, &peer->mw_cnt); 1140 if (IS_ERR(peer->mws)) { 1141 dev_err(&ndev->ntb.pdev->dev, 1142 "Failed to scan mws of port %hhu", peer->port); 1143 return PTR_ERR(peer->mws); 1144 } 1145 } 1146 1147 /* Initialize spin locker of the LUT registers */ 1148 spin_lock_init(&ndev->lut_lock); 1149 1150 dev_dbg(&ndev->ntb.pdev->dev, "Outbound and inbound MWs initialized"); 1151 1152 return 0; 1153} 1154 1155/* 1156 * idt_ntb_mw_count() - number of inbound memory windows (NTB API callback) 1157 * @ntb: NTB device context. 1158 * @pidx: Port index of peer device. 1159 * 1160 * The value is returned for the specified peer, so generally speaking it can 1161 * be different for different port depending on the IDT PCIe-switch 1162 * initialization. 1163 * 1164 * Return: the number of memory windows. 1165 */ 1166static int idt_ntb_mw_count(struct ntb_dev *ntb, int pidx) 1167{ 1168 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 1169 1170 if (pidx < 0 || ndev->peer_cnt <= pidx) 1171 return -EINVAL; 1172 1173 return ndev->peers[pidx].mw_cnt; 1174} 1175 1176/* 1177 * idt_ntb_mw_get_align() - inbound memory window parameters (NTB API callback) 1178 * @ntb: NTB device context. 1179 * @pidx: Port index of peer device. 1180 * @widx: Memory window index. 1181 * @addr_align: OUT - the base alignment for translating the memory window 1182 * @size_align: OUT - the size alignment for translating the memory window 1183 * @size_max: OUT - the maximum size of the memory window 1184 * 1185 * The peer memory window parameters have already been determined, so just 1186 * return the corresponding values, which mustn't change within session. 1187 * 1188 * Return: Zero on success, otherwise a negative error number. 1189 */ 1190static int idt_ntb_mw_get_align(struct ntb_dev *ntb, int pidx, int widx, 1191 resource_size_t *addr_align, 1192 resource_size_t *size_align, 1193 resource_size_t *size_max) 1194{ 1195 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 1196 struct idt_ntb_peer *peer; 1197 1198 if (pidx < 0 || ndev->peer_cnt <= pidx) 1199 return -EINVAL; 1200 1201 peer = &ndev->peers[pidx]; 1202 1203 if (widx < 0 || peer->mw_cnt <= widx) 1204 return -EINVAL; 1205 1206 if (addr_align != NULL) 1207 *addr_align = peer->mws[widx].addr_align; 1208 1209 if (size_align != NULL) 1210 *size_align = peer->mws[widx].size_align; 1211 1212 if (size_max != NULL) 1213 *size_max = peer->mws[widx].size_max; 1214 1215 return 0; 1216} 1217 1218/* 1219 * idt_ntb_peer_mw_count() - number of outbound memory windows 1220 * (NTB API callback) 1221 * @ntb: NTB device context. 1222 * 1223 * Outbound memory windows parameters have been determined based on the 1224 * BAR setup registers value, which are mostly constants within one session. 1225 * 1226 * Return: the number of memory windows. 1227 */ 1228static int idt_ntb_peer_mw_count(struct ntb_dev *ntb) 1229{ 1230 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 1231 1232 return ndev->mw_cnt; 1233} 1234 1235/* 1236 * idt_ntb_peer_mw_get_addr() - get map address of an outbound memory window 1237 * (NTB API callback) 1238 * @ntb: NTB device context. 1239 * @widx: Memory window index (within ntb_peer_mw_count() return value). 1240 * @base: OUT - the base address of mapping region. 1241 * @size: OUT - the size of mapping region. 1242 * 1243 * Return just parameters of BAR resources mapping. Size reflects just the size 1244 * of the resource 1245 * 1246 * Return: Zero on success, otherwise a negative error number. 1247 */ 1248static int idt_ntb_peer_mw_get_addr(struct ntb_dev *ntb, int widx, 1249 phys_addr_t *base, resource_size_t *size) 1250{ 1251 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 1252 1253 if (widx < 0 || ndev->mw_cnt <= widx) 1254 return -EINVAL; 1255 1256 /* Mapping address is just properly shifted BAR resource start */ 1257 if (base != NULL) 1258 *base = pci_resource_start(ntb->pdev, ndev->mws[widx].bar) + 1259 ndev->mws[widx].idx * ndev->mws[widx].size_max; 1260 1261 /* Mapping size has already been calculated at MWs scanning */ 1262 if (size != NULL) 1263 *size = ndev->mws[widx].size_max; 1264 1265 return 0; 1266} 1267 1268/* 1269 * idt_ntb_peer_mw_set_trans() - set a translation address of a memory window 1270 * (NTB API callback) 1271 * @ntb: NTB device context. 1272 * @pidx: Port index of peer device the translation address received from. 1273 * @widx: Memory window index. 1274 * @addr: The dma address of the shared memory to access. 1275 * @size: The size of the shared memory to access. 1276 * 1277 * The Direct address translation and LUT base translation is initialized a 1278 * bit differenet. Although the parameters restriction are now determined by 1279 * the same code. 1280 * 1281 * Return: Zero on success, otherwise an error number. 1282 */ 1283static int idt_ntb_peer_mw_set_trans(struct ntb_dev *ntb, int pidx, int widx, 1284 u64 addr, resource_size_t size) 1285{ 1286 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 1287 struct idt_mw_cfg *mw_cfg; 1288 u32 data = 0, lutoff = 0; 1289 1290 if (pidx < 0 || ndev->peer_cnt <= pidx) 1291 return -EINVAL; 1292 1293 if (widx < 0 || ndev->mw_cnt <= widx) 1294 return -EINVAL; 1295 1296 /* 1297 * Retrieve the memory window config to make sure the passed arguments 1298 * fit it restrictions 1299 */ 1300 mw_cfg = &ndev->mws[widx]; 1301 if (!IS_ALIGNED(addr, mw_cfg->addr_align)) 1302 return -EINVAL; 1303 if (!IS_ALIGNED(size, mw_cfg->size_align) || size > mw_cfg->size_max) 1304 return -EINVAL; 1305 1306 /* DIR and LUT based translations are initialized differently */ 1307 if (mw_cfg->type == IDT_MW_DIR) { 1308 const struct idt_ntb_bar *bar = &ntdata_tbl.bars[mw_cfg->bar]; 1309 u64 limit; 1310 /* Set destination partition of translation */ 1311 data = idt_nt_read(ndev, bar->setup); 1312 data = SET_FIELD(BARSETUP_TPART, data, ndev->peers[pidx].part); 1313 idt_nt_write(ndev, bar->setup, data); 1314 /* Set translation base address */ 1315 idt_nt_write(ndev, bar->ltbase, (u32)addr); 1316 idt_nt_write(ndev, bar->utbase, (u32)(addr >> 32)); 1317 /* Set the custom BAR aperture limit */ 1318 limit = pci_bus_address(ntb->pdev, mw_cfg->bar) + size; 1319 idt_nt_write(ndev, bar->limit, (u32)limit); 1320 if (IS_FLD_SET(BARSETUP_TYPE, data, 64)) 1321 idt_nt_write(ndev, (bar + 1)->limit, (limit >> 32)); 1322 } else { 1323 unsigned long irqflags; 1324 /* Initialize corresponding LUT entry */ 1325 lutoff = SET_FIELD(LUTOFFSET_INDEX, 0, mw_cfg->idx) | 1326 SET_FIELD(LUTOFFSET_BAR, 0, mw_cfg->bar); 1327 data = SET_FIELD(LUTUDATA_PART, 0, ndev->peers[pidx].part) | 1328 IDT_LUTUDATA_VALID; 1329 spin_lock_irqsave(&ndev->lut_lock, irqflags); 1330 idt_nt_write(ndev, IDT_NT_LUTOFFSET, lutoff); 1331 idt_nt_write(ndev, IDT_NT_LUTLDATA, (u32)addr); 1332 idt_nt_write(ndev, IDT_NT_LUTMDATA, (u32)(addr >> 32)); 1333 idt_nt_write(ndev, IDT_NT_LUTUDATA, data); 1334 spin_unlock_irqrestore(&ndev->lut_lock, irqflags); 1335 /* Limit address isn't specified since size is fixed for LUT */ 1336 } 1337 1338 return 0; 1339} 1340 1341/* 1342 * idt_ntb_peer_mw_clear_trans() - clear the outbound MW translation address 1343 * (NTB API callback) 1344 * @ntb: NTB device context. 1345 * @pidx: Port index of peer device. 1346 * @widx: Memory window index. 1347 * 1348 * It effectively disables the translation over the specified outbound MW. 1349 * 1350 * Return: Zero on success, otherwise an error number. 1351 */ 1352static int idt_ntb_peer_mw_clear_trans(struct ntb_dev *ntb, int pidx, 1353 int widx) 1354{ 1355 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 1356 struct idt_mw_cfg *mw_cfg; 1357 1358 if (pidx < 0 || ndev->peer_cnt <= pidx) 1359 return -EINVAL; 1360 1361 if (widx < 0 || ndev->mw_cnt <= widx) 1362 return -EINVAL; 1363 1364 mw_cfg = &ndev->mws[widx]; 1365 1366 /* DIR and LUT based translations are initialized differently */ 1367 if (mw_cfg->type == IDT_MW_DIR) { 1368 const struct idt_ntb_bar *bar = &ntdata_tbl.bars[mw_cfg->bar]; 1369 u32 data; 1370 /* Read BARSETUP to check BAR type */ 1371 data = idt_nt_read(ndev, bar->setup); 1372 /* Disable translation by specifying zero BAR limit */ 1373 idt_nt_write(ndev, bar->limit, 0); 1374 if (IS_FLD_SET(BARSETUP_TYPE, data, 64)) 1375 idt_nt_write(ndev, (bar + 1)->limit, 0); 1376 } else { 1377 unsigned long irqflags; 1378 u32 lutoff; 1379 /* Clear the corresponding LUT entry up */ 1380 lutoff = SET_FIELD(LUTOFFSET_INDEX, 0, mw_cfg->idx) | 1381 SET_FIELD(LUTOFFSET_BAR, 0, mw_cfg->bar); 1382 spin_lock_irqsave(&ndev->lut_lock, irqflags); 1383 idt_nt_write(ndev, IDT_NT_LUTOFFSET, lutoff); 1384 idt_nt_write(ndev, IDT_NT_LUTLDATA, 0); 1385 idt_nt_write(ndev, IDT_NT_LUTMDATA, 0); 1386 idt_nt_write(ndev, IDT_NT_LUTUDATA, 0); 1387 spin_unlock_irqrestore(&ndev->lut_lock, irqflags); 1388 } 1389 1390 return 0; 1391} 1392 1393/*============================================================================= 1394 * 5. Doorbell operations 1395 * 1396 * Doorbell functionality of IDT PCIe-switches is pretty unusual. First of 1397 * all there is global doorbell register which state can be changed by any 1398 * NT-function of the IDT device in accordance with global permissions. These 1399 * permissions configs are not supported by NTB API, so it must be done by 1400 * either BIOS or EEPROM settings. In the same way the state of the global 1401 * doorbell is reflected to the NT-functions local inbound doorbell registers. 1402 * It can lead to situations when client driver sets some peer doorbell bits 1403 * and get them bounced back to local inbound doorbell if permissions are 1404 * granted. 1405 * Secondly there is just one IRQ vector for Doorbell, Message, Temperature 1406 * and Switch events, so if client driver left any of Doorbell bits set and 1407 * some other event occurred, the driver will be notified of Doorbell event 1408 * again. 1409 *============================================================================= 1410 */ 1411 1412/* 1413 * idt_db_isr() - doorbell event ISR 1414 * @ndev: IDT NTB hardware driver descriptor 1415 * @ntint_sts: NT-function interrupt status 1416 * 1417 * Doorbell event happans when DBELL bit of NTINTSTS switches from 0 to 1. 1418 * It happens only when unmasked doorbell bits are set to ones on completely 1419 * zeroed doorbell register. 1420 * The method is called from PCIe ISR bottom-half routine. 1421 */ 1422static void idt_db_isr(struct idt_ntb_dev *ndev, u32 ntint_sts) 1423{ 1424 /* 1425 * Doorbell IRQ status will be cleaned only when client 1426 * driver unsets all the doorbell bits. 1427 */ 1428 dev_dbg(&ndev->ntb.pdev->dev, "DB IRQ detected %#08x", ntint_sts); 1429 1430 /* Notify the client driver of possible doorbell state change */ 1431 ntb_db_event(&ndev->ntb, 0); 1432} 1433 1434/* 1435 * idt_ntb_db_valid_mask() - get a mask of doorbell bits supported by the ntb 1436 * (NTB API callback) 1437 * @ntb: NTB device context. 1438 * 1439 * IDT PCIe-switches expose just one Doorbell register of DWORD size. 1440 * 1441 * Return: A mask of doorbell bits supported by the ntb. 1442 */ 1443static u64 idt_ntb_db_valid_mask(struct ntb_dev *ntb) 1444{ 1445 return IDT_DBELL_MASK; 1446} 1447 1448/* 1449 * idt_ntb_db_read() - read the local doorbell register (NTB API callback) 1450 * @ntb: NTB device context. 1451 * 1452 * There is just on inbound doorbell register of each NT-function, so 1453 * this method return it value. 1454 * 1455 * Return: The bits currently set in the local doorbell register. 1456 */ 1457static u64 idt_ntb_db_read(struct ntb_dev *ntb) 1458{ 1459 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 1460 1461 return idt_nt_read(ndev, IDT_NT_INDBELLSTS); 1462} 1463 1464/* 1465 * idt_ntb_db_clear() - clear bits in the local doorbell register 1466 * (NTB API callback) 1467 * @ntb: NTB device context. 1468 * @db_bits: Doorbell bits to clear. 1469 * 1470 * Clear bits of inbound doorbell register by writing ones to it. 1471 * 1472 * NOTE! Invalid bits are always considered cleared so it's not an error 1473 * to clear them over. 1474 * 1475 * Return: always zero as success. 1476 */ 1477static int idt_ntb_db_clear(struct ntb_dev *ntb, u64 db_bits) 1478{ 1479 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 1480 1481 idt_nt_write(ndev, IDT_NT_INDBELLSTS, (u32)db_bits); 1482 1483 return 0; 1484} 1485 1486/* 1487 * idt_ntb_db_read_mask() - read the local doorbell mask (NTB API callback) 1488 * @ntb: NTB device context. 1489 * 1490 * Each inbound doorbell bit can be masked from generating IRQ by setting 1491 * the corresponding bit in inbound doorbell mask. So this method returns 1492 * the value of the register. 1493 * 1494 * Return: The bits currently set in the local doorbell mask register. 1495 */ 1496static u64 idt_ntb_db_read_mask(struct ntb_dev *ntb) 1497{ 1498 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 1499 1500 return idt_nt_read(ndev, IDT_NT_INDBELLMSK); 1501} 1502 1503/* 1504 * idt_ntb_db_set_mask() - set bits in the local doorbell mask 1505 * (NTB API callback) 1506 * @ntb: NTB device context. 1507 * @db_bits: Doorbell mask bits to set. 1508 * 1509 * The inbound doorbell register mask value must be read, then OR'ed with 1510 * passed field and only then set back. 1511 * 1512 * Return: zero on success, negative error if invalid argument passed. 1513 */ 1514static int idt_ntb_db_set_mask(struct ntb_dev *ntb, u64 db_bits) 1515{ 1516 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 1517 1518 return idt_reg_set_bits(ndev, IDT_NT_INDBELLMSK, &ndev->db_mask_lock, 1519 IDT_DBELL_MASK, db_bits); 1520} 1521 1522/* 1523 * idt_ntb_db_clear_mask() - clear bits in the local doorbell mask 1524 * (NTB API callback) 1525 * @ntb: NTB device context. 1526 * @db_bits: Doorbell bits to clear. 1527 * 1528 * The method just clears the set bits up in accordance with the passed 1529 * bitfield. IDT PCIe-switch shall generate an interrupt if there hasn't 1530 * been any unmasked bit set before current unmasking. Otherwise IRQ won't 1531 * be generated since there is only one IRQ vector for all doorbells. 1532 * 1533 * Return: always zero as success 1534 */ 1535static int idt_ntb_db_clear_mask(struct ntb_dev *ntb, u64 db_bits) 1536{ 1537 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 1538 1539 idt_reg_clear_bits(ndev, IDT_NT_INDBELLMSK, &ndev->db_mask_lock, 1540 db_bits); 1541 1542 return 0; 1543} 1544 1545/* 1546 * idt_ntb_peer_db_set() - set bits in the peer doorbell register 1547 * (NTB API callback) 1548 * @ntb: NTB device context. 1549 * @db_bits: Doorbell bits to set. 1550 * 1551 * IDT PCIe-switches exposes local outbound doorbell register to change peer 1552 * inbound doorbell register state. 1553 * 1554 * Return: zero on success, negative error if invalid argument passed. 1555 */ 1556static int idt_ntb_peer_db_set(struct ntb_dev *ntb, u64 db_bits) 1557{ 1558 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 1559 1560 if (db_bits & ~(u64)IDT_DBELL_MASK) 1561 return -EINVAL; 1562 1563 idt_nt_write(ndev, IDT_NT_OUTDBELLSET, (u32)db_bits); 1564 return 0; 1565} 1566 1567/*============================================================================= 1568 * 6. Messaging operations 1569 * 1570 * Each NT-function of IDT PCIe-switch has four inbound and four outbound 1571 * message registers. Each outbound message register can be connected to one or 1572 * even more than one peer inbound message registers by setting global 1573 * configurations. Since NTB API permits one-on-one message registers mapping 1574 * only, the driver acts in according with that restriction. 1575 *============================================================================= 1576 */ 1577 1578/* 1579 * idt_init_msg() - initialize messaging interface 1580 * @ndev: IDT NTB hardware driver descriptor 1581 * 1582 * Just initialize the message registers routing tables locker. 1583 */ 1584static void idt_init_msg(struct idt_ntb_dev *ndev) 1585{ 1586 unsigned char midx; 1587 1588 /* Init the messages routing table lockers */ 1589 for (midx = 0; midx < IDT_MSG_CNT; midx++) 1590 spin_lock_init(&ndev->msg_locks[midx]); 1591 1592 dev_dbg(&ndev->ntb.pdev->dev, "NTB Messaging initialized"); 1593} 1594 1595/* 1596 * idt_msg_isr() - message event ISR 1597 * @ndev: IDT NTB hardware driver descriptor 1598 * @ntint_sts: NT-function interrupt status 1599 * 1600 * Message event happens when MSG bit of NTINTSTS switches from 0 to 1. 1601 * It happens only when unmasked message status bits are set to ones on 1602 * completely zeroed message status register. 1603 * The method is called from PCIe ISR bottom-half routine. 1604 */ 1605static void idt_msg_isr(struct idt_ntb_dev *ndev, u32 ntint_sts) 1606{ 1607 /* 1608 * Message IRQ status will be cleaned only when client 1609 * driver unsets all the message status bits. 1610 */ 1611 dev_dbg(&ndev->ntb.pdev->dev, "Message IRQ detected %#08x", ntint_sts); 1612 1613 /* Notify the client driver of possible message status change */ 1614 ntb_msg_event(&ndev->ntb); 1615} 1616 1617/* 1618 * idt_ntb_msg_count() - get the number of message registers (NTB API callback) 1619 * @ntb: NTB device context. 1620 * 1621 * IDT PCIe-switches support four message registers. 1622 * 1623 * Return: the number of message registers. 1624 */ 1625static int idt_ntb_msg_count(struct ntb_dev *ntb) 1626{ 1627 return IDT_MSG_CNT; 1628} 1629 1630/* 1631 * idt_ntb_msg_inbits() - get a bitfield of inbound message registers status 1632 * (NTB API callback) 1633 * @ntb: NTB device context. 1634 * 1635 * NT message status register is shared between inbound and outbound message 1636 * registers status 1637 * 1638 * Return: bitfield of inbound message registers. 1639 */ 1640static u64 idt_ntb_msg_inbits(struct ntb_dev *ntb) 1641{ 1642 return (u64)IDT_INMSG_MASK; 1643} 1644 1645/* 1646 * idt_ntb_msg_outbits() - get a bitfield of outbound message registers status 1647 * (NTB API callback) 1648 * @ntb: NTB device context. 1649 * 1650 * NT message status register is shared between inbound and outbound message 1651 * registers status 1652 * 1653 * Return: bitfield of outbound message registers. 1654 */ 1655static u64 idt_ntb_msg_outbits(struct ntb_dev *ntb) 1656{ 1657 return (u64)IDT_OUTMSG_MASK; 1658} 1659 1660/* 1661 * idt_ntb_msg_read_sts() - read the message registers status (NTB API callback) 1662 * @ntb: NTB device context. 1663 * 1664 * IDT PCIe-switches expose message status registers to notify drivers of 1665 * incoming data and failures in case if peer message register isn't freed. 1666 * 1667 * Return: status bits of message registers 1668 */ 1669static u64 idt_ntb_msg_read_sts(struct ntb_dev *ntb) 1670{ 1671 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 1672 1673 return idt_nt_read(ndev, IDT_NT_MSGSTS); 1674} 1675 1676/* 1677 * idt_ntb_msg_clear_sts() - clear status bits of message registers 1678 * (NTB API callback) 1679 * @ntb: NTB device context. 1680 * @sts_bits: Status bits to clear. 1681 * 1682 * Clear bits in the status register by writing ones. 1683 * 1684 * NOTE! Invalid bits are always considered cleared so it's not an error 1685 * to clear them over. 1686 * 1687 * Return: always zero as success. 1688 */ 1689static int idt_ntb_msg_clear_sts(struct ntb_dev *ntb, u64 sts_bits) 1690{ 1691 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 1692 1693 idt_nt_write(ndev, IDT_NT_MSGSTS, sts_bits); 1694 1695 return 0; 1696} 1697 1698/* 1699 * idt_ntb_msg_set_mask() - set mask of message register status bits 1700 * (NTB API callback) 1701 * @ntb: NTB device context. 1702 * @mask_bits: Mask bits. 1703 * 1704 * Mask the message status bits from raising an IRQ. 1705 * 1706 * Return: zero on success, negative error if invalid argument passed. 1707 */ 1708static int idt_ntb_msg_set_mask(struct ntb_dev *ntb, u64 mask_bits) 1709{ 1710 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 1711 1712 return idt_reg_set_bits(ndev, IDT_NT_MSGSTSMSK, &ndev->msg_mask_lock, 1713 IDT_MSG_MASK, mask_bits); 1714} 1715 1716/* 1717 * idt_ntb_msg_clear_mask() - clear message registers mask 1718 * (NTB API callback) 1719 * @ntb: NTB device context. 1720 * @mask_bits: Mask bits. 1721 * 1722 * Clear mask of message status bits IRQs. 1723 * 1724 * Return: always zero as success. 1725 */ 1726static int idt_ntb_msg_clear_mask(struct ntb_dev *ntb, u64 mask_bits) 1727{ 1728 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 1729 1730 idt_reg_clear_bits(ndev, IDT_NT_MSGSTSMSK, &ndev->msg_mask_lock, 1731 mask_bits); 1732 1733 return 0; 1734} 1735 1736/* 1737 * idt_ntb_msg_read() - read message register with specified index 1738 * (NTB API callback) 1739 * @ntb: NTB device context. 1740 * @pidx: OUT - Port index of peer device a message retrieved from 1741 * @midx: Message register index 1742 * 1743 * Read data from the specified message register and source register. 1744 * 1745 * Return: inbound message register value. 1746 */ 1747static u32 idt_ntb_msg_read(struct ntb_dev *ntb, int *pidx, int midx) 1748{ 1749 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 1750 1751 if (midx < 0 || IDT_MSG_CNT <= midx) 1752 return ~(u32)0; 1753 1754 /* Retrieve source port index of the message */ 1755 if (pidx != NULL) { 1756 u32 srcpart; 1757 1758 srcpart = idt_nt_read(ndev, ntdata_tbl.msgs[midx].src); 1759 *pidx = ndev->part_idx_map[srcpart]; 1760 1761 /* Sanity check partition index (for initial case) */ 1762 if (*pidx == -EINVAL) 1763 *pidx = 0; 1764 } 1765 1766 /* Retrieve data of the corresponding message register */ 1767 return idt_nt_read(ndev, ntdata_tbl.msgs[midx].in); 1768} 1769 1770/* 1771 * idt_ntb_peer_msg_write() - write data to the specified message register 1772 * (NTB API callback) 1773 * @ntb: NTB device context. 1774 * @pidx: Port index of peer device a message being sent to 1775 * @midx: Message register index 1776 * @msg: Data to send 1777 * 1778 * Just try to send data to a peer. Message status register should be 1779 * checked by client driver. 1780 * 1781 * Return: zero on success, negative error if invalid argument passed. 1782 */ 1783static int idt_ntb_peer_msg_write(struct ntb_dev *ntb, int pidx, int midx, 1784 u32 msg) 1785{ 1786 struct idt_ntb_dev *ndev = to_ndev_ntb(ntb); 1787 unsigned long irqflags; 1788 u32 swpmsgctl = 0; 1789 1790 if (midx < 0 || IDT_MSG_CNT <= midx) 1791 return -EINVAL; 1792 1793 if (pidx < 0 || ndev->peer_cnt <= pidx) 1794 return -EINVAL; 1795 1796 /* Collect the routing information */ 1797 swpmsgctl = SET_FIELD(SWPxMSGCTL_REG, 0, midx) | 1798 SET_FIELD(SWPxMSGCTL_PART, 0, ndev->peers[pidx].part); 1799 1800 /* Lock the messages routing table of the specified register */ 1801 spin_lock_irqsave(&ndev->msg_locks[midx], irqflags); 1802 /* Set the route and send the data */ 1803 idt_sw_write(ndev, partdata_tbl[ndev->part].msgctl[midx], swpmsgctl); 1804 idt_nt_write(ndev, ntdata_tbl.msgs[midx].out, msg); 1805 /* Unlock the messages routing table */ 1806 spin_unlock_irqrestore(&ndev->msg_locks[midx], irqflags); 1807 1808 /* Client driver shall check the status register */ 1809 return 0; 1810} 1811 1812/*============================================================================= 1813 * 7. Temperature sensor operations 1814 * 1815 * IDT PCIe-switch has an embedded temperature sensor, which can be used to 1816 * check current chip core temperature. Since a workload environment can be 1817 * different on different platforms, an offset and ADC/filter settings can be 1818 * specified. Although the offset configuration is only exposed to the sysfs 1819 * hwmon interface at the moment. The rest of the settings can be adjusted 1820 * for instance by the BIOS/EEPROM firmware. 1821 *============================================================================= 1822 */ 1823 1824/* 1825 * idt_get_deg() - convert millidegree Celsius value to just degree 1826 * @mdegC: IN - millidegree Celsius value 1827 * 1828 * Return: Degree corresponding to the passed millidegree value 1829 */ 1830static inline s8 idt_get_deg(long mdegC) 1831{ 1832 return mdegC / 1000; 1833} 1834 1835/* 1836 * idt_get_frac() - retrieve 0/0.5 fraction of the millidegree Celsius value 1837 * @mdegC: IN - millidegree Celsius value 1838 * 1839 * Return: 0/0.5 degree fraction of the passed millidegree value 1840 */ 1841static inline u8 idt_get_deg_frac(long mdegC) 1842{ 1843 return (mdegC % 1000) >= 500 ? 5 : 0; 1844} 1845 1846/* 1847 * idt_get_temp_fmt() - convert millidegree Celsius value to 0:7:1 format 1848 * @mdegC: IN - millidegree Celsius value 1849 * 1850 * Return: 0:7:1 format acceptable by the IDT temperature sensor 1851 */ 1852static inline u8 idt_temp_get_fmt(long mdegC) 1853{ 1854 return (idt_get_deg(mdegC) << 1) | (idt_get_deg_frac(mdegC) ? 1 : 0); 1855} 1856 1857/* 1858 * idt_get_temp_sval() - convert temp sample to signed millidegree Celsius 1859 * @data: IN - shifted to LSB 8-bits temperature sample 1860 * 1861 * Return: signed millidegree Celsius 1862 */ 1863static inline long idt_get_temp_sval(u32 data) 1864{ 1865 return ((s8)data / 2) * 1000 + (data & 0x1 ? 500 : 0); 1866} 1867 1868/* 1869 * idt_get_temp_sval() - convert temp sample to unsigned millidegree Celsius 1870 * @data: IN - shifted to LSB 8-bits temperature sample 1871 * 1872 * Return: unsigned millidegree Celsius 1873 */ 1874static inline long idt_get_temp_uval(u32 data) 1875{ 1876 return (data / 2) * 1000 + (data & 0x1 ? 500 : 0); 1877} 1878 1879/* 1880 * idt_read_temp() - read temperature from chip sensor 1881 * @ntb: NTB device context. 1882 * @type: IN - type of the temperature value to read 1883 * @val: OUT - integer value of temperature in millidegree Celsius 1884 */ 1885static void idt_read_temp(struct idt_ntb_dev *ndev, 1886 const enum idt_temp_val type, long *val) 1887{ 1888 u32 data; 1889 1890 /* Alter the temperature field in accordance with the passed type */ 1891 switch (type) { 1892 case IDT_TEMP_CUR: 1893 data = GET_FIELD(TMPSTS_TEMP, 1894 idt_sw_read(ndev, IDT_SW_TMPSTS)); 1895 break; 1896 case IDT_TEMP_LOW: 1897 data = GET_FIELD(TMPSTS_LTEMP, 1898 idt_sw_read(ndev, IDT_SW_TMPSTS)); 1899 break; 1900 case IDT_TEMP_HIGH: 1901 data = GET_FIELD(TMPSTS_HTEMP, 1902 idt_sw_read(ndev, IDT_SW_TMPSTS)); 1903 break; 1904 case IDT_TEMP_OFFSET: 1905 /* This is the only field with signed 0:7:1 format */ 1906 data = GET_FIELD(TMPADJ_OFFSET, 1907 idt_sw_read(ndev, IDT_SW_TMPADJ)); 1908 *val = idt_get_temp_sval(data); 1909 return; 1910 default: 1911 data = GET_FIELD(TMPSTS_TEMP, 1912 idt_sw_read(ndev, IDT_SW_TMPSTS)); 1913 break; 1914 } 1915 1916 /* The rest of the fields accept unsigned 0:7:1 format */ 1917 *val = idt_get_temp_uval(data); 1918} 1919 1920/* 1921 * idt_write_temp() - write temperature to the chip sensor register 1922 * @ntb: NTB device context. 1923 * @type: IN - type of the temperature value to change 1924 * @val: IN - integer value of temperature in millidegree Celsius 1925 */ 1926static void idt_write_temp(struct idt_ntb_dev *ndev, 1927 const enum idt_temp_val type, const long val) 1928{ 1929 unsigned int reg; 1930 u32 data; 1931 u8 fmt; 1932 1933 /* Retrieve the properly formatted temperature value */ 1934 fmt = idt_temp_get_fmt(val); 1935 1936 mutex_lock(&ndev->hwmon_mtx); 1937 switch (type) { 1938 case IDT_TEMP_LOW: 1939 reg = IDT_SW_TMPALARM; 1940 data = SET_FIELD(TMPALARM_LTEMP, idt_sw_read(ndev, reg), fmt) & 1941 ~IDT_TMPALARM_IRQ_MASK; 1942 break; 1943 case IDT_TEMP_HIGH: 1944 reg = IDT_SW_TMPALARM; 1945 data = SET_FIELD(TMPALARM_HTEMP, idt_sw_read(ndev, reg), fmt) & 1946 ~IDT_TMPALARM_IRQ_MASK; 1947 break; 1948 case IDT_TEMP_OFFSET: 1949 reg = IDT_SW_TMPADJ; 1950 data = SET_FIELD(TMPADJ_OFFSET, idt_sw_read(ndev, reg), fmt); 1951 break; 1952 default: 1953 goto inval_spin_unlock; 1954 } 1955 1956 idt_sw_write(ndev, reg, data); 1957 1958inval_spin_unlock: 1959 mutex_unlock(&ndev->hwmon_mtx); 1960} 1961 1962/* 1963 * idt_sysfs_show_temp() - printout corresponding temperature value 1964 * @dev: Pointer to the NTB device structure 1965 * @da: Sensor device attribute structure 1966 * @buf: Buffer to print temperature out 1967 * 1968 * Return: Number of written symbols or negative error 1969 */ 1970static ssize_t idt_sysfs_show_temp(struct device *dev, 1971 struct device_attribute *da, char *buf) 1972{ 1973 struct sensor_device_attribute *attr = to_sensor_dev_attr(da); 1974 struct idt_ntb_dev *ndev = dev_get_drvdata(dev); 1975 enum idt_temp_val type = attr->index; 1976 long mdeg; 1977 1978 idt_read_temp(ndev, type, &mdeg); 1979 return sprintf(buf, "%ld\n", mdeg); 1980} 1981 1982/* 1983 * idt_sysfs_set_temp() - set corresponding temperature value 1984 * @dev: Pointer to the NTB device structure 1985 * @da: Sensor device attribute structure 1986 * @buf: Buffer to print temperature out 1987 * @count: Size of the passed buffer 1988 * 1989 * Return: Number of written symbols or negative error 1990 */ 1991static ssize_t idt_sysfs_set_temp(struct device *dev, 1992 struct device_attribute *da, const char *buf, 1993 size_t count) 1994{ 1995 struct sensor_device_attribute *attr = to_sensor_dev_attr(da); 1996 struct idt_ntb_dev *ndev = dev_get_drvdata(dev); 1997 enum idt_temp_val type = attr->index; 1998 long mdeg; 1999 int ret; 2000 2001 ret = kstrtol(buf, 10, &mdeg); 2002 if (ret) 2003 return ret; 2004 2005 /* Clamp the passed value in accordance with the type */ 2006 if (type == IDT_TEMP_OFFSET) 2007 mdeg = clamp_val(mdeg, IDT_TEMP_MIN_OFFSET, 2008 IDT_TEMP_MAX_OFFSET); 2009 else 2010 mdeg = clamp_val(mdeg, IDT_TEMP_MIN_MDEG, IDT_TEMP_MAX_MDEG); 2011 2012 idt_write_temp(ndev, type, mdeg); 2013 2014 return count; 2015} 2016 2017/* 2018 * idt_sysfs_reset_hist() - reset temperature history 2019 * @dev: Pointer to the NTB device structure 2020 * @da: Sensor device attribute structure 2021 * @buf: Buffer to print temperature out 2022 * @count: Size of the passed buffer 2023 * 2024 * Return: Number of written symbols or negative error 2025 */ 2026static ssize_t idt_sysfs_reset_hist(struct device *dev, 2027 struct device_attribute *da, 2028 const char *buf, size_t count) 2029{ 2030 struct idt_ntb_dev *ndev = dev_get_drvdata(dev); 2031 2032 /* Just set the maximal value to the lowest temperature field and 2033 * minimal value to the highest temperature field 2034 */ 2035 idt_write_temp(ndev, IDT_TEMP_LOW, IDT_TEMP_MAX_MDEG); 2036 idt_write_temp(ndev, IDT_TEMP_HIGH, IDT_TEMP_MIN_MDEG); 2037 2038 return count; 2039} 2040 2041/* 2042 * Hwmon IDT sysfs attributes 2043 */ 2044static SENSOR_DEVICE_ATTR(temp1_input, 0444, idt_sysfs_show_temp, NULL, 2045 IDT_TEMP_CUR); 2046static SENSOR_DEVICE_ATTR(temp1_lowest, 0444, idt_sysfs_show_temp, NULL, 2047 IDT_TEMP_LOW); 2048static SENSOR_DEVICE_ATTR(temp1_highest, 0444, idt_sysfs_show_temp, NULL, 2049 IDT_TEMP_HIGH); 2050static SENSOR_DEVICE_ATTR(temp1_offset, 0644, idt_sysfs_show_temp, 2051 idt_sysfs_set_temp, IDT_TEMP_OFFSET); 2052static DEVICE_ATTR(temp1_reset_history, 0200, NULL, idt_sysfs_reset_hist); 2053 2054/* 2055 * Hwmon IDT sysfs attributes group 2056 */ 2057static struct attribute *idt_temp_attrs[] = { 2058 &sensor_dev_attr_temp1_input.dev_attr.attr, 2059 &sensor_dev_attr_temp1_lowest.dev_attr.attr, 2060 &sensor_dev_attr_temp1_highest.dev_attr.attr, 2061 &sensor_dev_attr_temp1_offset.dev_attr.attr, 2062 &dev_attr_temp1_reset_history.attr, 2063 NULL 2064}; 2065ATTRIBUTE_GROUPS(idt_temp); 2066 2067/* 2068 * idt_init_temp() - initialize temperature sensor interface 2069 * @ndev: IDT NTB hardware driver descriptor 2070 * 2071 * Simple sensor initializarion method is responsible for device switching 2072 * on and resource management based hwmon interface registration. Note, that 2073 * since the device is shared we won't disable it on remove, but leave it 2074 * working until the system is powered off. 2075 */ 2076static void idt_init_temp(struct idt_ntb_dev *ndev) 2077{ 2078 struct device *hwmon; 2079 2080 /* Enable sensor if it hasn't been already */ 2081 idt_sw_write(ndev, IDT_SW_TMPCTL, 0x0); 2082 2083 /* Initialize hwmon interface fields */ 2084 mutex_init(&ndev->hwmon_mtx); 2085 2086 hwmon = devm_hwmon_device_register_with_groups(&ndev->ntb.pdev->dev, 2087 ndev->swcfg->name, ndev, idt_temp_groups); 2088 if (IS_ERR(hwmon)) { 2089 dev_err(&ndev->ntb.pdev->dev, "Couldn't create hwmon device"); 2090 return; 2091 } 2092 2093 dev_dbg(&ndev->ntb.pdev->dev, "Temperature HWmon interface registered"); 2094} 2095 2096/*============================================================================= 2097 * 8. ISRs related operations 2098 * 2099 * IDT PCIe-switch has strangely developed IRQ system. There is just one 2100 * interrupt vector for doorbell and message registers. So the hardware driver 2101 * can't determine actual source of IRQ if, for example, message event happened 2102 * while any of unmasked doorbell is still set. The similar situation may be if 2103 * switch or temperature sensor events pop up. The difference is that SEVENT 2104 * and TMPSENSOR bits of NT interrupt status register can be cleaned by 2105 * IRQ handler so a next interrupt request won't have false handling of 2106 * corresponding events. 2107 * The hardware driver has only bottom-half handler of the IRQ, since if any 2108 * of events happened the device won't raise it again before the last one is 2109 * handled by clearing of corresponding NTINTSTS bit. 2110 *============================================================================= 2111 */ 2112 2113static irqreturn_t idt_thread_isr(int irq, void *devid); 2114 2115/* 2116 * idt_init_isr() - initialize PCIe interrupt handler 2117 * @ndev: IDT NTB hardware driver descriptor 2118 * 2119 * Return: zero on success, otherwise a negative error number. 2120 */ 2121static int idt_init_isr(struct idt_ntb_dev *ndev) 2122{ 2123 struct pci_dev *pdev = ndev->ntb.pdev; 2124 u32 ntint_mask; 2125 int ret; 2126 2127 /* Allocate just one interrupt vector for the ISR */ 2128 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_INTX); 2129 if (ret != 1) { 2130 dev_err(&pdev->dev, "Failed to allocate IRQ vector"); 2131 return ret; 2132 } 2133 2134 /* Retrieve the IRQ vector */ 2135 ret = pci_irq_vector(pdev, 0); 2136 if (ret < 0) { 2137 dev_err(&pdev->dev, "Failed to get IRQ vector"); 2138 goto err_free_vectors; 2139 } 2140 2141 /* Set the IRQ handler */ 2142 ret = devm_request_threaded_irq(&pdev->dev, ret, NULL, idt_thread_isr, 2143 IRQF_ONESHOT, NTB_IRQNAME, ndev); 2144 if (ret != 0) { 2145 dev_err(&pdev->dev, "Failed to set MSI IRQ handler, %d", ret); 2146 goto err_free_vectors; 2147 } 2148 2149 /* Unmask Message/Doorbell/SE interrupts */ 2150 ntint_mask = idt_nt_read(ndev, IDT_NT_NTINTMSK) & ~IDT_NTINTMSK_ALL; 2151 idt_nt_write(ndev, IDT_NT_NTINTMSK, ntint_mask); 2152 2153 /* From now on the interrupts are enabled */ 2154 dev_dbg(&pdev->dev, "NTB interrupts initialized"); 2155 2156 return 0; 2157 2158err_free_vectors: 2159 pci_free_irq_vectors(pdev); 2160 2161 return ret; 2162} 2163 2164/* 2165 * idt_deinit_ist() - deinitialize PCIe interrupt handler 2166 * @ndev: IDT NTB hardware driver descriptor 2167 * 2168 * Disable corresponding interrupts and free allocated IRQ vectors. 2169 */ 2170static void idt_deinit_isr(struct idt_ntb_dev *ndev) 2171{ 2172 struct pci_dev *pdev = ndev->ntb.pdev; 2173 u32 ntint_mask; 2174 2175 /* Mask interrupts back */ 2176 ntint_mask = idt_nt_read(ndev, IDT_NT_NTINTMSK) | IDT_NTINTMSK_ALL; 2177 idt_nt_write(ndev, IDT_NT_NTINTMSK, ntint_mask); 2178 2179 /* Manually free IRQ otherwise PCI free irq vectors will fail */ 2180 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 0), ndev); 2181 2182 /* Free allocated IRQ vectors */ 2183 pci_free_irq_vectors(pdev); 2184 2185 dev_dbg(&pdev->dev, "NTB interrupts deinitialized"); 2186} 2187 2188/* 2189 * idt_thread_isr() - NT function interrupts handler 2190 * @irq: IRQ number 2191 * @devid: Custom buffer 2192 * 2193 * It reads current NT interrupts state register and handles all the event 2194 * it declares. 2195 * The method is bottom-half routine of actual default PCIe IRQ handler. 2196 */ 2197static irqreturn_t idt_thread_isr(int irq, void *devid) 2198{ 2199 struct idt_ntb_dev *ndev = devid; 2200 bool handled = false; 2201 u32 ntint_sts; 2202 2203 /* Read the NT interrupts status register */ 2204 ntint_sts = idt_nt_read(ndev, IDT_NT_NTINTSTS); 2205 2206 /* Handle messaging interrupts */ 2207 if (ntint_sts & IDT_NTINTSTS_MSG) { 2208 idt_msg_isr(ndev, ntint_sts); 2209 handled = true; 2210 } 2211 2212 /* Handle doorbell interrupts */ 2213 if (ntint_sts & IDT_NTINTSTS_DBELL) { 2214 idt_db_isr(ndev, ntint_sts); 2215 handled = true; 2216 } 2217 2218 /* Handle switch event interrupts */ 2219 if (ntint_sts & IDT_NTINTSTS_SEVENT) { 2220 idt_se_isr(ndev, ntint_sts); 2221 handled = true; 2222 } 2223 2224 dev_dbg(&ndev->ntb.pdev->dev, "IDT IRQs 0x%08x handled", ntint_sts); 2225 2226 return handled ? IRQ_HANDLED : IRQ_NONE; 2227} 2228 2229/*=========================================================================== 2230 * 9. NTB hardware driver initialization 2231 *=========================================================================== 2232 */ 2233 2234/* 2235 * NTB API operations 2236 */ 2237static const struct ntb_dev_ops idt_ntb_ops = { 2238 .port_number = idt_ntb_port_number, 2239 .peer_port_count = idt_ntb_peer_port_count, 2240 .peer_port_number = idt_ntb_peer_port_number, 2241 .peer_port_idx = idt_ntb_peer_port_idx, 2242 .link_is_up = idt_ntb_link_is_up, 2243 .link_enable = idt_ntb_link_enable, 2244 .link_disable = idt_ntb_link_disable, 2245 .mw_count = idt_ntb_mw_count, 2246 .mw_get_align = idt_ntb_mw_get_align, 2247 .peer_mw_count = idt_ntb_peer_mw_count, 2248 .peer_mw_get_addr = idt_ntb_peer_mw_get_addr, 2249 .peer_mw_set_trans = idt_ntb_peer_mw_set_trans, 2250 .peer_mw_clear_trans = idt_ntb_peer_mw_clear_trans, 2251 .db_valid_mask = idt_ntb_db_valid_mask, 2252 .db_read = idt_ntb_db_read, 2253 .db_clear = idt_ntb_db_clear, 2254 .db_read_mask = idt_ntb_db_read_mask, 2255 .db_set_mask = idt_ntb_db_set_mask, 2256 .db_clear_mask = idt_ntb_db_clear_mask, 2257 .peer_db_set = idt_ntb_peer_db_set, 2258 .msg_count = idt_ntb_msg_count, 2259 .msg_inbits = idt_ntb_msg_inbits, 2260 .msg_outbits = idt_ntb_msg_outbits, 2261 .msg_read_sts = idt_ntb_msg_read_sts, 2262 .msg_clear_sts = idt_ntb_msg_clear_sts, 2263 .msg_set_mask = idt_ntb_msg_set_mask, 2264 .msg_clear_mask = idt_ntb_msg_clear_mask, 2265 .msg_read = idt_ntb_msg_read, 2266 .peer_msg_write = idt_ntb_peer_msg_write 2267}; 2268 2269/* 2270 * idt_register_device() - register IDT NTB device 2271 * @ndev: IDT NTB hardware driver descriptor 2272 * 2273 * Return: zero on success, otherwise a negative error number. 2274 */ 2275static int idt_register_device(struct idt_ntb_dev *ndev) 2276{ 2277 int ret; 2278 2279 /* Initialize the rest of NTB device structure and register it */ 2280 ndev->ntb.ops = &idt_ntb_ops; 2281 ndev->ntb.topo = NTB_TOPO_SWITCH; 2282 2283 ret = ntb_register_device(&ndev->ntb); 2284 if (ret != 0) { 2285 dev_err(&ndev->ntb.pdev->dev, "Failed to register NTB device"); 2286 return ret; 2287 } 2288 2289 dev_dbg(&ndev->ntb.pdev->dev, "NTB device successfully registered"); 2290 2291 return 0; 2292} 2293 2294/* 2295 * idt_unregister_device() - unregister IDT NTB device 2296 * @ndev: IDT NTB hardware driver descriptor 2297 */ 2298static void idt_unregister_device(struct idt_ntb_dev *ndev) 2299{ 2300 /* Just unregister the NTB device */ 2301 ntb_unregister_device(&ndev->ntb); 2302 2303 dev_dbg(&ndev->ntb.pdev->dev, "NTB device unregistered"); 2304} 2305 2306/*============================================================================= 2307 * 10. DebugFS node initialization 2308 *============================================================================= 2309 */ 2310 2311static ssize_t idt_dbgfs_info_read(struct file *filp, char __user *ubuf, 2312 size_t count, loff_t *offp); 2313 2314/* 2315 * Driver DebugFS info file operations 2316 */ 2317static const struct file_operations idt_dbgfs_info_ops = { 2318 .owner = THIS_MODULE, 2319 .open = simple_open, 2320 .read = idt_dbgfs_info_read 2321}; 2322 2323/* 2324 * idt_dbgfs_info_read() - DebugFS read info node callback 2325 * @file: File node descriptor. 2326 * @ubuf: User-space buffer to put data to 2327 * @count: Size of the buffer 2328 * @offp: Offset within the buffer 2329 */ 2330static ssize_t idt_dbgfs_info_read(struct file *filp, char __user *ubuf, 2331 size_t count, loff_t *offp) 2332{ 2333 struct idt_ntb_dev *ndev = filp->private_data; 2334 unsigned char idx, pidx, cnt; 2335 unsigned long irqflags, mdeg; 2336 ssize_t ret = 0, off = 0; 2337 enum ntb_speed speed; 2338 enum ntb_width width; 2339 char *strbuf; 2340 size_t size; 2341 u32 data; 2342 2343 /* Lets limit the buffer size the way the Intel/AMD drivers do */ 2344 size = min_t(size_t, count, 0x1000U); 2345 2346 /* Allocate the memory for the buffer */ 2347 strbuf = kmalloc(size, GFP_KERNEL); 2348 if (strbuf == NULL) 2349 return -ENOMEM; 2350 2351 /* Put the data into the string buffer */ 2352 off += scnprintf(strbuf + off, size - off, 2353 "\n\t\tIDT NTB device Information:\n\n"); 2354 2355 /* General local device configurations */ 2356 off += scnprintf(strbuf + off, size - off, 2357 "Local Port %hhu, Partition %hhu\n", ndev->port, ndev->part); 2358 2359 /* Peer ports information */ 2360 off += scnprintf(strbuf + off, size - off, "Peers:\n"); 2361 for (idx = 0; idx < ndev->peer_cnt; idx++) { 2362 off += scnprintf(strbuf + off, size - off, 2363 "\t%hhu. Port %hhu, Partition %hhu\n", 2364 idx, ndev->peers[idx].port, ndev->peers[idx].part); 2365 } 2366 2367 /* Links status */ 2368 data = idt_ntb_link_is_up(&ndev->ntb, &speed, &width); 2369 off += scnprintf(strbuf + off, size - off, 2370 "NTB link status\t- 0x%08x, ", data); 2371 off += scnprintf(strbuf + off, size - off, "PCIe Gen %d x%d lanes\n", 2372 speed, width); 2373 2374 /* Mapping table entries */ 2375 off += scnprintf(strbuf + off, size - off, "NTB Mapping Table:\n"); 2376 for (idx = 0; idx < IDT_MTBL_ENTRY_CNT; idx++) { 2377 spin_lock_irqsave(&ndev->mtbl_lock, irqflags); 2378 idt_nt_write(ndev, IDT_NT_NTMTBLADDR, idx); 2379 data = idt_nt_read(ndev, IDT_NT_NTMTBLDATA); 2380 spin_unlock_irqrestore(&ndev->mtbl_lock, irqflags); 2381 2382 /* Print valid entries only */ 2383 if (data & IDT_NTMTBLDATA_VALID) { 2384 off += scnprintf(strbuf + off, size - off, 2385 "\t%hhu. Partition %d, Requester ID 0x%04x\n", 2386 idx, GET_FIELD(NTMTBLDATA_PART, data), 2387 GET_FIELD(NTMTBLDATA_REQID, data)); 2388 } 2389 } 2390 off += scnprintf(strbuf + off, size - off, "\n"); 2391 2392 /* Outbound memory windows information */ 2393 off += scnprintf(strbuf + off, size - off, 2394 "Outbound Memory Windows:\n"); 2395 for (idx = 0; idx < ndev->mw_cnt; idx += cnt) { 2396 data = ndev->mws[idx].type; 2397 cnt = idt_get_mw_count(data); 2398 2399 /* Print Memory Window information */ 2400 if (data == IDT_MW_DIR) 2401 off += scnprintf(strbuf + off, size - off, 2402 "\t%hhu.\t", idx); 2403 else 2404 off += scnprintf(strbuf + off, size - off, 2405 "\t%hhu-%d.\t", idx, idx + cnt - 1); 2406 2407 off += scnprintf(strbuf + off, size - off, "%s BAR%hhu, ", 2408 idt_get_mw_name(data), ndev->mws[idx].bar); 2409 2410 off += scnprintf(strbuf + off, size - off, 2411 "Address align 0x%08llx, ", ndev->mws[idx].addr_align); 2412 2413 off += scnprintf(strbuf + off, size - off, 2414 "Size align 0x%08llx, Size max %llu\n", 2415 ndev->mws[idx].size_align, ndev->mws[idx].size_max); 2416 } 2417 2418 /* Inbound memory windows information */ 2419 for (pidx = 0; pidx < ndev->peer_cnt; pidx++) { 2420 off += scnprintf(strbuf + off, size - off, 2421 "Inbound Memory Windows for peer %hhu (Port %hhu):\n", 2422 pidx, ndev->peers[pidx].port); 2423 2424 /* Print Memory Windows information */ 2425 for (idx = 0; idx < ndev->peers[pidx].mw_cnt; idx += cnt) { 2426 data = ndev->peers[pidx].mws[idx].type; 2427 cnt = idt_get_mw_count(data); 2428 2429 if (data == IDT_MW_DIR) 2430 off += scnprintf(strbuf + off, size - off, 2431 "\t%hhu.\t", idx); 2432 else 2433 off += scnprintf(strbuf + off, size - off, 2434 "\t%hhu-%d.\t", idx, idx + cnt - 1); 2435 2436 off += scnprintf(strbuf + off, size - off, 2437 "%s BAR%hhu, ", idt_get_mw_name(data), 2438 ndev->peers[pidx].mws[idx].bar); 2439 2440 off += scnprintf(strbuf + off, size - off, 2441 "Address align 0x%08llx, ", 2442 ndev->peers[pidx].mws[idx].addr_align); 2443 2444 off += scnprintf(strbuf + off, size - off, 2445 "Size align 0x%08llx, Size max %llu\n", 2446 ndev->peers[pidx].mws[idx].size_align, 2447 ndev->peers[pidx].mws[idx].size_max); 2448 } 2449 } 2450 off += scnprintf(strbuf + off, size - off, "\n"); 2451 2452 /* Doorbell information */ 2453 data = idt_sw_read(ndev, IDT_SW_GDBELLSTS); 2454 off += scnprintf(strbuf + off, size - off, 2455 "Global Doorbell state\t- 0x%08x\n", data); 2456 data = idt_ntb_db_read(&ndev->ntb); 2457 off += scnprintf(strbuf + off, size - off, 2458 "Local Doorbell state\t- 0x%08x\n", data); 2459 data = idt_nt_read(ndev, IDT_NT_INDBELLMSK); 2460 off += scnprintf(strbuf + off, size - off, 2461 "Local Doorbell mask\t- 0x%08x\n", data); 2462 off += scnprintf(strbuf + off, size - off, "\n"); 2463 2464 /* Messaging information */ 2465 off += scnprintf(strbuf + off, size - off, 2466 "Message event valid\t- 0x%08x\n", IDT_MSG_MASK); 2467 data = idt_ntb_msg_read_sts(&ndev->ntb); 2468 off += scnprintf(strbuf + off, size - off, 2469 "Message event status\t- 0x%08x\n", data); 2470 data = idt_nt_read(ndev, IDT_NT_MSGSTSMSK); 2471 off += scnprintf(strbuf + off, size - off, 2472 "Message event mask\t- 0x%08x\n", data); 2473 off += scnprintf(strbuf + off, size - off, 2474 "Message data:\n"); 2475 for (idx = 0; idx < IDT_MSG_CNT; idx++) { 2476 int src; 2477 data = idt_ntb_msg_read(&ndev->ntb, &src, idx); 2478 off += scnprintf(strbuf + off, size - off, 2479 "\t%hhu. 0x%08x from peer %d (Port %hhu)\n", 2480 idx, data, src, ndev->peers[src].port); 2481 } 2482 off += scnprintf(strbuf + off, size - off, "\n"); 2483 2484 /* Current temperature */ 2485 idt_read_temp(ndev, IDT_TEMP_CUR, &mdeg); 2486 off += scnprintf(strbuf + off, size - off, 2487 "Switch temperature\t\t- %hhd.%hhuC\n", 2488 idt_get_deg(mdeg), idt_get_deg_frac(mdeg)); 2489 2490 /* Copy the buffer to the User Space */ 2491 ret = simple_read_from_buffer(ubuf, count, offp, strbuf, off); 2492 kfree(strbuf); 2493 2494 return ret; 2495} 2496 2497/* 2498 * idt_init_dbgfs() - initialize DebugFS node 2499 * @ndev: IDT NTB hardware driver descriptor 2500 * 2501 * Return: zero on success, otherwise a negative error number. 2502 */ 2503static int idt_init_dbgfs(struct idt_ntb_dev *ndev) 2504{ 2505 char devname[64]; 2506 2507 /* If the top directory is not created then do nothing */ 2508 if (IS_ERR_OR_NULL(dbgfs_topdir)) { 2509 dev_info(&ndev->ntb.pdev->dev, "Top DebugFS directory absent"); 2510 return PTR_ERR_OR_ZERO(dbgfs_topdir); 2511 } 2512 2513 /* Create the info file node */ 2514 snprintf(devname, 64, "info:%s", pci_name(ndev->ntb.pdev)); 2515 ndev->dbgfs_info = debugfs_create_file(devname, 0400, dbgfs_topdir, 2516 ndev, &idt_dbgfs_info_ops); 2517 if (IS_ERR(ndev->dbgfs_info)) { 2518 dev_dbg(&ndev->ntb.pdev->dev, "Failed to create DebugFS node"); 2519 return PTR_ERR(ndev->dbgfs_info); 2520 } 2521 2522 dev_dbg(&ndev->ntb.pdev->dev, "NTB device DebugFS node created"); 2523 2524 return 0; 2525} 2526 2527/* 2528 * idt_deinit_dbgfs() - deinitialize DebugFS node 2529 * @ndev: IDT NTB hardware driver descriptor 2530 * 2531 * Just discard the info node from DebugFS 2532 */ 2533static void idt_deinit_dbgfs(struct idt_ntb_dev *ndev) 2534{ 2535 debugfs_remove(ndev->dbgfs_info); 2536 2537 dev_dbg(&ndev->ntb.pdev->dev, "NTB device DebugFS node discarded"); 2538} 2539 2540/*============================================================================= 2541 * 11. Basic PCIe device initialization 2542 *============================================================================= 2543 */ 2544 2545/* 2546 * idt_check_setup() - Check whether the IDT PCIe-switch is properly 2547 * pre-initialized 2548 * @pdev: Pointer to the PCI device descriptor 2549 * 2550 * Return: zero on success, otherwise a negative error number. 2551 */ 2552static int idt_check_setup(struct pci_dev *pdev) 2553{ 2554 u32 data; 2555 int ret; 2556 2557 /* Read the BARSETUP0 */ 2558 ret = pci_read_config_dword(pdev, IDT_NT_BARSETUP0, &data); 2559 if (ret != 0) { 2560 dev_err(&pdev->dev, 2561 "Failed to read BARSETUP0 config register"); 2562 return ret; 2563 } 2564 2565 /* Check whether the BAR0 register is enabled to be of config space */ 2566 if (!(data & IDT_BARSETUP_EN) || !(data & IDT_BARSETUP_MODE_CFG)) { 2567 dev_err(&pdev->dev, "BAR0 doesn't map config space"); 2568 return -EINVAL; 2569 } 2570 2571 /* Configuration space BAR0 must have certain size */ 2572 if ((data & IDT_BARSETUP_SIZE_MASK) != IDT_BARSETUP_SIZE_CFG) { 2573 dev_err(&pdev->dev, "Invalid size of config space"); 2574 return -EINVAL; 2575 } 2576 2577 dev_dbg(&pdev->dev, "NTB device pre-initialized correctly"); 2578 2579 return 0; 2580} 2581 2582/* 2583 * Create the IDT PCIe-switch driver descriptor 2584 * @pdev: Pointer to the PCI device descriptor 2585 * @id: IDT PCIe-device configuration 2586 * 2587 * It just allocates a memory for IDT PCIe-switch device structure and 2588 * initializes some commonly used fields. 2589 * 2590 * No need of release method, since managed device resource is used for 2591 * memory allocation. 2592 * 2593 * Return: pointer to the descriptor, otherwise a negative error number. 2594 */ 2595static struct idt_ntb_dev *idt_create_dev(struct pci_dev *pdev, 2596 const struct pci_device_id *id) 2597{ 2598 struct idt_ntb_dev *ndev; 2599 2600 /* Allocate memory for the IDT PCIe-device descriptor */ 2601 ndev = devm_kzalloc(&pdev->dev, sizeof(*ndev), GFP_KERNEL); 2602 if (!ndev) { 2603 dev_err(&pdev->dev, "Memory allocation failed for descriptor"); 2604 return ERR_PTR(-ENOMEM); 2605 } 2606 2607 /* Save the IDT PCIe-switch ports configuration */ 2608 ndev->swcfg = (struct idt_89hpes_cfg *)id->driver_data; 2609 /* Save the PCI-device pointer inside the NTB device structure */ 2610 ndev->ntb.pdev = pdev; 2611 2612 /* Initialize spin locker of Doorbell, Message and GASA registers */ 2613 spin_lock_init(&ndev->db_mask_lock); 2614 spin_lock_init(&ndev->msg_mask_lock); 2615 spin_lock_init(&ndev->gasa_lock); 2616 2617 dev_info(&pdev->dev, "IDT %s discovered", ndev->swcfg->name); 2618 2619 dev_dbg(&pdev->dev, "NTB device descriptor created"); 2620 2621 return ndev; 2622} 2623 2624/* 2625 * idt_init_pci() - initialize the basic PCI-related subsystem 2626 * @ndev: Pointer to the IDT PCIe-switch driver descriptor 2627 * 2628 * Managed device resources will be freed automatically in case of failure or 2629 * driver detachment. 2630 * 2631 * Return: zero on success, otherwise negative error number. 2632 */ 2633static int idt_init_pci(struct idt_ntb_dev *ndev) 2634{ 2635 struct pci_dev *pdev = ndev->ntb.pdev; 2636 int ret; 2637 2638 /* Initialize the bit mask of PCI/NTB DMA */ 2639 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2640 if (ret != 0) { 2641 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2642 if (ret != 0) { 2643 dev_err(&pdev->dev, "Failed to set DMA bit mask\n"); 2644 return ret; 2645 } 2646 dev_warn(&pdev->dev, "Cannot set DMA highmem bit mask\n"); 2647 } 2648 2649 /* 2650 * The PCI core enables device error reporting. It's not critical to 2651 * have AER disabled in the kernel. 2652 * 2653 * Cleanup nonfatal error status before getting to init. 2654 */ 2655 pci_aer_clear_nonfatal_status(pdev); 2656 2657 /* First enable the PCI device */ 2658 ret = pcim_enable_device(pdev); 2659 if (ret != 0) { 2660 dev_err(&pdev->dev, "Failed to enable PCIe device\n"); 2661 return ret; 2662 } 2663 2664 /* 2665 * Enable the bus mastering, which effectively enables MSI IRQs and 2666 * Request TLPs translation 2667 */ 2668 pci_set_master(pdev); 2669 2670 /* Request all BARs resources */ 2671 ret = pcim_request_all_regions(pdev, NTB_NAME); 2672 if (ret != 0) { 2673 dev_err(&pdev->dev, "Failed to request resources\n"); 2674 goto err_clear_master; 2675 } 2676 2677 /* ioremap BAR0 - PCI configuration space */ 2678 ndev->cfgspc = pcim_iomap(pdev, 0, 0); 2679 if (!ndev->cfgspc) { 2680 dev_err(&pdev->dev, "Failed to ioremap BAR 0\n"); 2681 ret = -ENOMEM; 2682 goto err_clear_master; 2683 } 2684 2685 /* Put the IDT driver data pointer to the PCI-device private pointer */ 2686 pci_set_drvdata(pdev, ndev); 2687 2688 dev_dbg(&pdev->dev, "NT-function PCIe interface initialized"); 2689 2690 return 0; 2691 2692err_clear_master: 2693 pci_clear_master(pdev); 2694 2695 return ret; 2696} 2697 2698/* 2699 * idt_deinit_pci() - deinitialize the basic PCI-related subsystem 2700 * @ndev: Pointer to the IDT PCIe-switch driver descriptor 2701 * 2702 * Managed resources will be freed on the driver detachment 2703 */ 2704static void idt_deinit_pci(struct idt_ntb_dev *ndev) 2705{ 2706 struct pci_dev *pdev = ndev->ntb.pdev; 2707 2708 /* Clean up the PCI-device private data pointer */ 2709 pci_set_drvdata(pdev, NULL); 2710 2711 /* Clear the bus master disabling the Request TLPs translation */ 2712 pci_clear_master(pdev); 2713 2714 dev_dbg(&pdev->dev, "NT-function PCIe interface cleared"); 2715} 2716 2717/*=========================================================================== 2718 * 12. PCI bus callback functions 2719 *=========================================================================== 2720 */ 2721 2722/* 2723 * idt_pci_probe() - PCI device probe callback 2724 * @pdev: Pointer to PCI device structure 2725 * @id: PCIe device custom descriptor 2726 * 2727 * Return: zero on success, otherwise negative error number 2728 */ 2729static int idt_pci_probe(struct pci_dev *pdev, 2730 const struct pci_device_id *id) 2731{ 2732 struct idt_ntb_dev *ndev; 2733 int ret; 2734 2735 /* Check whether IDT PCIe-switch is properly pre-initialized */ 2736 ret = idt_check_setup(pdev); 2737 if (ret != 0) 2738 return ret; 2739 2740 /* Allocate the memory for IDT NTB device data */ 2741 ndev = idt_create_dev(pdev, id); 2742 if (IS_ERR(ndev)) 2743 return PTR_ERR(ndev); 2744 2745 /* Initialize the basic PCI subsystem of the device */ 2746 ret = idt_init_pci(ndev); 2747 if (ret != 0) 2748 return ret; 2749 2750 /* Scan ports of the IDT PCIe-switch */ 2751 (void)idt_scan_ports(ndev); 2752 2753 /* Initialize NTB link events subsystem */ 2754 idt_init_link(ndev); 2755 2756 /* Initialize MWs subsystem */ 2757 ret = idt_init_mws(ndev); 2758 if (ret != 0) 2759 goto err_deinit_link; 2760 2761 /* Initialize Messaging subsystem */ 2762 idt_init_msg(ndev); 2763 2764 /* Initialize hwmon interface */ 2765 idt_init_temp(ndev); 2766 2767 /* Initialize IDT interrupts handler */ 2768 ret = idt_init_isr(ndev); 2769 if (ret != 0) 2770 goto err_deinit_link; 2771 2772 /* Register IDT NTB devices on the NTB bus */ 2773 ret = idt_register_device(ndev); 2774 if (ret != 0) 2775 goto err_deinit_isr; 2776 2777 /* Initialize DebugFS info node */ 2778 (void)idt_init_dbgfs(ndev); 2779 2780 /* IDT PCIe-switch NTB driver is finally initialized */ 2781 dev_info(&pdev->dev, "IDT NTB device is ready"); 2782 2783 /* May the force be with us... */ 2784 return 0; 2785 2786err_deinit_isr: 2787 idt_deinit_isr(ndev); 2788err_deinit_link: 2789 idt_deinit_link(ndev); 2790 idt_deinit_pci(ndev); 2791 2792 return ret; 2793} 2794 2795/* 2796 * idt_pci_probe() - PCI device remove callback 2797 * @pdev: Pointer to PCI device structure 2798 */ 2799static void idt_pci_remove(struct pci_dev *pdev) 2800{ 2801 struct idt_ntb_dev *ndev = pci_get_drvdata(pdev); 2802 2803 /* Deinit the DebugFS node */ 2804 idt_deinit_dbgfs(ndev); 2805 2806 /* Unregister NTB device */ 2807 idt_unregister_device(ndev); 2808 2809 /* Stop the interrupts handling */ 2810 idt_deinit_isr(ndev); 2811 2812 /* Deinitialize link event subsystem */ 2813 idt_deinit_link(ndev); 2814 2815 /* Deinit basic PCI subsystem */ 2816 idt_deinit_pci(ndev); 2817 2818 /* IDT PCIe-switch NTB driver is finally initialized */ 2819 dev_info(&pdev->dev, "IDT NTB device is removed"); 2820 2821 /* Sayonara... */ 2822} 2823 2824/* 2825 * IDT PCIe-switch models ports configuration structures 2826 */ 2827static const struct idt_89hpes_cfg idt_89hpes24nt6ag2_config = { 2828 .name = "89HPES24NT6AG2", 2829 .port_cnt = 6, .ports = {0, 2, 4, 6, 8, 12} 2830}; 2831static const struct idt_89hpes_cfg idt_89hpes32nt8ag2_config = { 2832 .name = "89HPES32NT8AG2", 2833 .port_cnt = 8, .ports = {0, 2, 4, 6, 8, 12, 16, 20} 2834}; 2835static const struct idt_89hpes_cfg idt_89hpes32nt8bg2_config = { 2836 .name = "89HPES32NT8BG2", 2837 .port_cnt = 8, .ports = {0, 2, 4, 6, 8, 12, 16, 20} 2838}; 2839static const struct idt_89hpes_cfg idt_89hpes12nt12g2_config = { 2840 .name = "89HPES12NT12G2", 2841 .port_cnt = 3, .ports = {0, 8, 16} 2842}; 2843static const struct idt_89hpes_cfg idt_89hpes16nt16g2_config = { 2844 .name = "89HPES16NT16G2", 2845 .port_cnt = 4, .ports = {0, 8, 12, 16} 2846}; 2847static const struct idt_89hpes_cfg idt_89hpes24nt24g2_config = { 2848 .name = "89HPES24NT24G2", 2849 .port_cnt = 8, .ports = {0, 2, 4, 6, 8, 12, 16, 20} 2850}; 2851static const struct idt_89hpes_cfg idt_89hpes32nt24ag2_config = { 2852 .name = "89HPES32NT24AG2", 2853 .port_cnt = 8, .ports = {0, 2, 4, 6, 8, 12, 16, 20} 2854}; 2855static const struct idt_89hpes_cfg idt_89hpes32nt24bg2_config = { 2856 .name = "89HPES32NT24BG2", 2857 .port_cnt = 8, .ports = {0, 2, 4, 6, 8, 12, 16, 20} 2858}; 2859 2860/* 2861 * PCI-ids table of the supported IDT PCIe-switch devices 2862 */ 2863static const struct pci_device_id idt_pci_tbl[] = { 2864 {IDT_PCI_DEVICE_IDS(89HPES24NT6AG2, idt_89hpes24nt6ag2_config)}, 2865 {IDT_PCI_DEVICE_IDS(89HPES32NT8AG2, idt_89hpes32nt8ag2_config)}, 2866 {IDT_PCI_DEVICE_IDS(89HPES32NT8BG2, idt_89hpes32nt8bg2_config)}, 2867 {IDT_PCI_DEVICE_IDS(89HPES12NT12G2, idt_89hpes12nt12g2_config)}, 2868 {IDT_PCI_DEVICE_IDS(89HPES16NT16G2, idt_89hpes16nt16g2_config)}, 2869 {IDT_PCI_DEVICE_IDS(89HPES24NT24G2, idt_89hpes24nt24g2_config)}, 2870 {IDT_PCI_DEVICE_IDS(89HPES32NT24AG2, idt_89hpes32nt24ag2_config)}, 2871 {IDT_PCI_DEVICE_IDS(89HPES32NT24BG2, idt_89hpes32nt24bg2_config)}, 2872 {0} 2873}; 2874MODULE_DEVICE_TABLE(pci, idt_pci_tbl); 2875 2876/* 2877 * IDT PCIe-switch NT-function device driver structure definition 2878 */ 2879static struct pci_driver idt_pci_driver = { 2880 .name = KBUILD_MODNAME, 2881 .probe = idt_pci_probe, 2882 .remove = idt_pci_remove, 2883 .id_table = idt_pci_tbl, 2884}; 2885 2886static int __init idt_pci_driver_init(void) 2887{ 2888 int ret; 2889 pr_info("%s %s\n", NTB_DESC, NTB_VER); 2890 2891 /* Create the top DebugFS directory if the FS is initialized */ 2892 if (debugfs_initialized()) 2893 dbgfs_topdir = debugfs_create_dir(KBUILD_MODNAME, NULL); 2894 2895 /* Register the NTB hardware driver to handle the PCI device */ 2896 ret = pci_register_driver(&idt_pci_driver); 2897 if (ret) 2898 debugfs_remove_recursive(dbgfs_topdir); 2899 2900 return ret; 2901} 2902module_init(idt_pci_driver_init); 2903 2904static void __exit idt_pci_driver_exit(void) 2905{ 2906 /* Unregister the NTB hardware driver */ 2907 pci_unregister_driver(&idt_pci_driver); 2908 2909 /* Discard the top DebugFS directory */ 2910 debugfs_remove_recursive(dbgfs_topdir); 2911} 2912module_exit(idt_pci_driver_exit); 2913
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