txrx.h

  1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
  2/* Copyright(c) 2020  Realtek Corporation
  3 */
  4
  5#ifndef __RTW89_TXRX_H__
  6#define __RTW89_TXRX_H__
  7
  8#include "debug.h"
  9
 10#define DATA_RATE_MODE_CTRL_MASK	GENMASK(8, 7)
 11#define DATA_RATE_MODE_CTRL_MASK_V1	GENMASK(10, 8)
 12#define DATA_RATE_NOT_HT_IDX_MASK	GENMASK(3, 0)
 13#define DATA_RATE_MODE_NON_HT		0x0
 14#define DATA_RATE_HT_IDX_MASK		GENMASK(4, 0)
 15#define DATA_RATE_HT_IDX_MASK_V1	GENMASK(4, 0)
 16#define DATA_RATE_MODE_HT		0x1
 17#define DATA_RATE_HT_NSS_MASK		GENMASK(4, 3)
 18#define DATA_RATE_VHT_HE_NSS_MASK	GENMASK(6, 4)
 19#define DATA_RATE_VHT_HE_IDX_MASK	GENMASK(3, 0)
 20#define DATA_RATE_NSS_MASK_V1		GENMASK(7, 5)
 21#define DATA_RATE_MCS_MASK_V1		GENMASK(4, 0)
 22#define DATA_RATE_MODE_VHT		0x2
 23#define DATA_RATE_MODE_HE		0x3
 24#define DATA_RATE_MODE_EHT		0x4
 25
 26static inline u8 rtw89_get_data_rate_mode(struct rtw89_dev *rtwdev, u16 hw_rate)
 27{
 28	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
 29		return u16_get_bits(hw_rate, DATA_RATE_MODE_CTRL_MASK_V1);
 30
 31	return u16_get_bits(hw_rate, DATA_RATE_MODE_CTRL_MASK);
 32}
 33
 34static inline u8 rtw89_get_data_not_ht_idx(struct rtw89_dev *rtwdev, u16 hw_rate)
 35{
 36	return u16_get_bits(hw_rate, DATA_RATE_NOT_HT_IDX_MASK);
 37}
 38
 39static inline u8 rtw89_get_data_ht_mcs(struct rtw89_dev *rtwdev, u16 hw_rate)
 40{
 41	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
 42		return u16_get_bits(hw_rate, DATA_RATE_HT_IDX_MASK_V1);
 43
 44	return u16_get_bits(hw_rate, DATA_RATE_HT_IDX_MASK);
 45}
 46
 47static inline u8 rtw89_get_data_mcs(struct rtw89_dev *rtwdev, u16 hw_rate)
 48{
 49	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
 50		return u16_get_bits(hw_rate, DATA_RATE_MCS_MASK_V1);
 51
 52	return u16_get_bits(hw_rate, DATA_RATE_VHT_HE_IDX_MASK);
 53}
 54
 55static inline u8 rtw89_get_data_ht_nss(struct rtw89_dev *rtwdev, u16 hw_rate)
 56{
 57	return u16_get_bits(hw_rate, DATA_RATE_HT_NSS_MASK);
 58}
 59
 60static inline u8 rtw89_get_data_nss(struct rtw89_dev *rtwdev, u16 hw_rate)
 61{
 62	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
 63		return u16_get_bits(hw_rate, DATA_RATE_NSS_MASK_V1);
 64
 65	return u16_get_bits(hw_rate, DATA_RATE_VHT_HE_NSS_MASK);
 66}
 67
 68/* TX WD BODY DWORD 0 */
 69#define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24)
 70#define RTW89_TXWD_BODY0_WP_OFFSET_V1 GENMASK(28, 24)
 71#define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
 72#define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
 73#define RTW89_TXWD_BODY0_FW_DL BIT(20)
 74#define RTW89_TXWD_BODY0_CHANNEL_DMA GENMASK(19, 16)
 75#define RTW89_TXWD_BODY0_HDR_LLC_LEN GENMASK(15, 11)
 76#define RTW89_TXWD_BODY0_STF_MODE BIT(10)
 77#define RTW89_TXWD_BODY0_WD_PAGE BIT(7)
 78#define RTW89_TXWD_BODY0_HW_AMSDU BIT(5)
 79#define RTW89_TXWD_BODY0_HW_SSN_SEL GENMASK(3, 2)
 80#define RTW89_TXWD_BODY0_HW_SSN_MODE GENMASK(1, 0)
 81
 82/* TX WD BODY DWORD 1 */
 83#define RTW89_TXWD_BODY1_ADDR_INFO_NUM GENMASK(31, 26)
 84#define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16)
 85#define RTW89_TXWD_BODY1_SEC_KEYID GENMASK(5, 4)
 86#define RTW89_TXWD_BODY1_SEC_TYPE GENMASK(3, 0)
 87
 88/* TX WD BODY DWORD 2 */
 89#define RTW89_TXWD_BODY2_MACID GENMASK(30, 24)
 90#define RTW89_TXWD_BODY2_TID_INDICATE BIT(23)
 91#define RTW89_TXWD_BODY2_QSEL GENMASK(22, 17)
 92#define RTW89_TXWD_BODY2_TXPKT_SIZE GENMASK(13, 0)
 93
 94/* TX WD BODY DWORD 3 */
 95#define RTW89_TXWD_BODY3_BK BIT(13)
 96#define RTW89_TXWD_BODY3_AGG_EN BIT(12)
 97#define RTW89_TXWD_BODY3_SW_SEQ GENMASK(11, 0)
 98
 99/* TX WD BODY DWORD 4 */
100#define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24)
101#define RTW89_TXWD_BODY4_SEC_IV_L0 GENMASK(23, 16)
102
103/* TX WD BODY DWORD 5 */
104#define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24)
105#define RTW89_TXWD_BODY5_SEC_IV_H4 GENMASK(23, 16)
106#define RTW89_TXWD_BODY5_SEC_IV_H3 GENMASK(15, 8)
107#define RTW89_TXWD_BODY5_SEC_IV_H2 GENMASK(7, 0)
108
109/* TX WD BODY DWORD 6 (V1) */
110
111/* TX WD BODY DWORD 7 (V1) */
112#define RTW89_TXWD_BODY7_USE_RATE_V1 BIT(31)
113#define RTW89_TXWD_BODY7_DATA_BW GENMASK(29, 28)
114#define RTW89_TXWD_BODY7_GI_LTF GENMASK(27, 25)
115#define RTW89_TXWD_BODY7_DATA_RATE GENMASK(24, 16)
116
117/* TX WD INFO DWORD 0 */
118#define RTW89_TXWD_INFO0_USE_RATE BIT(30)
119#define RTW89_TXWD_INFO0_DATA_BW GENMASK(29, 28)
120#define RTW89_TXWD_INFO0_GI_LTF GENMASK(27, 25)
121#define RTW89_TXWD_INFO0_DATA_RATE GENMASK(24, 16)
122#define RTW89_TXWD_INFO0_DATA_ER BIT(15)
123#define RTW89_TXWD_INFO0_DATA_STBC BIT(12)
124#define RTW89_TXWD_INFO0_DATA_LDPC BIT(11)
125#define RTW89_TXWD_INFO0_DISDATAFB BIT(10)
126#define RTW89_TXWD_INFO0_DATA_BW_ER BIT(8)
127#define RTW89_TXWD_INFO0_MULTIPORT_ID GENMASK(6, 4)
128
129/* TX WD INFO DWORD 1 */
130#define RTW89_TXWD_INFO1_DATA_TXCNT_LMT_SEL BIT(31)
131#define RTW89_TXWD_INFO1_DATA_TXCNT_LMT GENMASK(30, 25)
132#define RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(24, 16)
133#define RTW89_TXWD_INFO1_A_CTRL_BSR BIT(14)
134#define RTW89_TXWD_INFO1_MAX_AGGNUM GENMASK(7, 0)
135
136/* TX WD INFO DWORD 2 */
137#define RTW89_TXWD_INFO2_AMPDU_DENSITY GENMASK(20, 18)
138#define RTW89_TXWD_INFO2_SEC_TYPE GENMASK(12, 9)
139#define RTW89_TXWD_INFO2_SEC_HW_ENC BIT(8)
140#define RTW89_TXWD_INFO2_FORCE_KEY_EN BIT(8)
141#define RTW89_TXWD_INFO2_SEC_CAM_IDX GENMASK(7, 0)
142
143/* TX WD INFO DWORD 3 */
144#define RTW89_TXWD_INFO3_SPE_RPT BIT(10)
145
146/* TX WD INFO DWORD 4 */
147#define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31)
148#define RTW89_TXWD_INFO4_RTS_EN BIT(27)
149#define RTW89_TXWD_INFO4_SW_DEFINE GENMASK(3, 0)
150
151/* TX WD INFO DWORD 5 */
152
153/* TX WD BODY DWORD 0 */
154#define BE_TXD_BODY0_EN_HWSEQ_MODE GENMASK(1, 0)
155#define BE_TXD_BODY0_HW_SSN_SEL GENMASK(4, 2)
156#define BE_TXD_BODY0_HWAMSDU BIT(5)
157#define BE_TXD_BODY0_HW_SEC_IV BIT(6)
158#define BE_TXD_BODY0_WD_PAGE BIT(7)
159#define BE_TXD_BODY0_CHK_EN BIT(8)
160#define BE_TXD_BODY0_WP_INT BIT(9)
161#define BE_TXD_BODY0_STF_MODE BIT(10)
162#define BE_TXD_BODY0_HDR_LLC_LEN GENMASK(15, 11)
163#define BE_TXD_BODY0_CH_DMA GENMASK(19, 16)
164#define BE_TXD_BODY0_SMH_EN BIT(20)
165#define BE_TXD_BODY0_PKT_OFFSET BIT(21)
166#define BE_TXD_BODY0_WDINFO_EN BIT(22)
167#define BE_TXD_BODY0_MOREDATA BIT(23)
168#define BE_TXD_BODY0_WP_OFFSET_V1 GENMASK(27, 24)
169#define BE_TXD_BODY0_AZ_FTM_SEC_V1 BIT(28)
170#define BE_TXD_BODY0_WD_SOURCE GENMASK(30, 29)
171#define BE_TXD_BODY0_HCI_SEQNUM_MODE BIT(31)
172
173/* TX WD BODY DWORD 1 */
174#define BE_TXD_BODY1_DMA_TXAGG_NUM GENMASK(6, 0)
175#define BE_TXD_BODY1_REUSE_NUM GENMASK(11, 7)
176#define BE_TXD_BODY1_SEC_TYPE GENMASK(15, 12)
177#define BE_TXD_BODY1_SEC_KEYID GENMASK(17, 16)
178#define BE_TXD_BODY1_SW_SEC_IV BIT(18)
179#define BE_TXD_BODY1_REUSE_SIZE GENMASK(23, 20)
180#define BE_TXD_BODY1_REUSE_START_OFFSET GENMASK(25, 24)
181#define BE_TXD_BODY1_ADDR_INFO_NUM GENMASK(31, 26)
182
183/* TX WD BODY DWORD 2 */
184#define BE_TXD_BODY2_TXPKTSIZE GENMASK(13, 0)
185#define BE_TXD_BODY2_AGG_EN BIT(14)
186#define BE_TXD_BODY2_BK BIT(15)
187#define BE_TXD_BODY2_MACID_EXTEND BIT(16)
188#define BE_TXD_BODY2_QSEL GENMASK(22, 17)
189#define BE_TXD_BODY2_TID_IND BIT(23)
190#define BE_TXD_BODY2_MACID GENMASK(31, 24)
191
192/* TX WD BODY DWORD 3 */
193#define BE_TXD_BODY3_WIFI_SEQ GENMASK(11, 0)
194#define BE_TXD_BODY3_MLO_FLAG BIT(12)
195#define BE_TXD_BODY3_IS_MLD_SW_EN BIT(13)
196#define BE_TXD_BODY3_TRY_RATE BIT(14)
197#define BE_TXD_BODY3_RELINK_FLAG_V1 BIT(15)
198#define BE_TXD_BODY3_BAND0_SU_TC_V1 GENMASK(21, 16)
199#define BE_TXD_BODY3_TOTAL_TC GENMASK(27, 22)
200#define BE_TXD_BODY3_RU_RTY BIT(28)
201#define BE_TXD_BODY3_MU_PRI_RTY BIT(29)
202#define BE_TXD_BODY3_MU_2ND_RTY BIT(30)
203#define BE_TXD_BODY3_BAND1_SU_RTY_V1 BIT(31)
204
205/* TX WD BODY DWORD 4 */
206#define BE_TXD_BODY4_TXDESC_CHECKSUM GENMASK(15, 0)
207#define BE_TXD_BODY4_SEC_IV_L0 GENMASK(23, 16)
208#define BE_TXD_BODY4_SEC_IV_L1 GENMASK(31, 24)
209
210/* TX WD BODY DWORD 5 */
211#define BE_TXD_BODY5_SEC_IV_H2 GENMASK(7, 0)
212#define BE_TXD_BODY5_SEC_IV_H3 GENMASK(15, 8)
213#define BE_TXD_BODY5_SEC_IV_H4 GENMASK(23, 16)
214#define BE_TXD_BODY5_SEC_IV_H5 GENMASK(31, 24)
215
216/* TX WD BODY DWORD 6 */
217#define BE_TXD_BODY6_MU_TC GENMASK(4, 0)
218#define BE_TXD_BODY6_RU_TC GENMASK(9, 5)
219#define BE_TXD_BODY6_PS160 BIT(10)
220#define BE_TXD_BODY6_BMC BIT(11)
221#define BE_TXD_BODY6_NO_ACK BIT(12)
222#define BE_TXD_BODY6_UPD_WLAN_HDR BIT(13)
223#define BE_TXD_BODY6_A4_HDR BIT(14)
224#define BE_TXD_BODY6_EOSP_BIT BIT(15)
225#define BE_TXD_BODY6_S_IDX GENMASK(23, 16)
226#define BE_TXD_BODY6_RU_POS GENMASK(31, 24)
227
228/* TX WD BODY DWORD 7 */
229#define BE_TXD_BODY7_RTS_TC GENMASK(5, 0)
230#define BE_TXD_BODY7_MSDU_NUM GENMASK(9, 6)
231#define BE_TXD_BODY7_DATA_ER BIT(10)
232#define BE_TXD_BODY7_DATA_BW_ER BIT(11)
233#define BE_TXD_BODY7_DATA_DCM BIT(12)
234#define BE_TXD_BODY7_GI_LTF GENMASK(15, 13)
235#define BE_TXD_BODY7_DATARATE GENMASK(27, 16)
236#define BE_TXD_BODY7_DATA_BW GENMASK(30, 28)
237#define BE_TXD_BODY7_USERATE_SEL BIT(31)
238
239/* TX WD INFO DWORD 0 */
240#define BE_TXD_INFO0_MBSSID GENMASK(3, 0)
241#define BE_TXD_INFO0_MULTIPORT_ID GENMASK(6, 4)
242#define BE_TXD_INFO0_DISRTSFB BIT(9)
243#define BE_TXD_INFO0_DISDATAFB BIT(10)
244#define BE_TXD_INFO0_DATA_LDPC BIT(11)
245#define BE_TXD_INFO0_DATA_STBC BIT(12)
246#define BE_TXD_INFO0_DATA_TXCNT_LMT GENMASK(21, 16)
247#define BE_TXD_INFO0_DATA_TXCNT_LMT_SEL BIT(22)
248#define BE_TXD_INFO0_RESP_PHYSTS_CSI_EN_V1 BIT(23)
249#define BE_TXD_INFO0_RLS_TO_CPUIO BIT(30)
250#define BE_TXD_INFO0_ACK_CH_INFO BIT(31)
251
252/* TX WD INFO DWORD 1 */
253#define BE_TXD_INFO1_MAX_AGG_NUM GENMASK(7, 0)
254#define BE_TXD_INFO1_BCN_SRCH_SEQ GENMASK(9, 8)
255#define BE_TXD_INFO1_NAVUSEHDR BIT(10)
256#define BE_TXD_INFO1_A_CTRL_BQR BIT(12)
257#define BE_TXD_INFO1_A_CTRL_BSR BIT(14)
258#define BE_TXD_INFO1_A_CTRL_CAS BIT(15)
259#define BE_TXD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(27, 16)
260#define BE_TXD_INFO1_SW_DEFINE GENMASK(31, 28)
261
262/* TX WD INFO DWORD 2 */
263#define BE_TXD_INFO2_SEC_CAM_IDX GENMASK(7, 0)
264#define BE_TXD_INFO2_FORCE_KEY_EN BIT(8)
265#define BE_TXD_INFO2_LIFETIME_SEL GENMASK(15, 13)
266#define BE_TXD_INFO2_FORCE_TXOP BIT(17)
267#define BE_TXD_INFO2_AMPDU_DENSITY GENMASK(20, 18)
268#define BE_TXD_INFO2_LSIG_TXOP_EN BIT(21)
269#define BE_TXD_INFO2_OBW_CTS2SELF_DUP_TYPE GENMASK(29, 26)
270#define BE_TXD_INFO2_SPE_RPT_V1 BIT(30)
271#define BE_TXD_INFO2_SIFS_TX_V1 BIT(31)
272
273/* TX WD INFO DWORD 3 */
274#define BE_TXD_INFO3_SPE_PKT GENMASK(3, 0)
275#define BE_TXD_INFO3_SPE_PKT_TYPE GENMASK(7, 4)
276#define BE_TXD_INFO3_CQI_SND BIT(8)
277#define BE_TXD_INFO3_RTT_EN BIT(9)
278#define BE_TXD_INFO3_HT_DATA_SND_V1 BIT(10)
279#define BE_TXD_INFO3_BT_NULL BIT(11)
280#define BE_TXD_INFO3_TRI_FRAME BIT(12)
281#define BE_TXD_INFO3_NULL_0 BIT(13)
282#define BE_TXD_INFO3_NULL_1 BIT(14)
283#define BE_TXD_INFO3_RAW BIT(15)
284#define BE_TXD_INFO3_GROUP_BIT_IE_OFFSET GENMASK(23, 16)
285#define BE_TXD_INFO3_SIGNALING_TA_PKT_EN BIT(25)
286#define BE_TXD_INFO3_BCNPKT_TSF_CTRL BIT(26)
287#define BE_TXD_INFO3_SIGNALING_TA_PKT_SC GENMASK(30, 27)
288#define BE_TXD_INFO3_FORCE_BSS_CLR BIT(31)
289
290/* TX WD INFO DWORD 4 */
291#define BE_TXD_INFO4_PUNCTURE_PATTERN GENMASK(15, 0)
292#define BE_TXD_INFO4_PUNC_MODE GENMASK(17, 16)
293#define BE_TXD_INFO4_SW_TX_OK_0 BIT(18)
294#define BE_TXD_INFO4_SW_TX_OK_1 BIT(19)
295#define BE_TXD_INFO4_SW_TX_PWR_DBM GENMASK(26, 23)
296#define BE_TXD_INFO4_RTS_EN BIT(27)
297#define BE_TXD_INFO4_CTS2SELF BIT(28)
298#define BE_TXD_INFO4_CCA_RTS GENMASK(30, 29)
299#define BE_TXD_INFO4_HW_RTS_EN BIT(31)
300
301/* TX WD INFO DWORD 5 */
302#define BE_TXD_INFO5_SR_RATE_V1 GENMASK(4, 0)
303#define BE_TXD_INFO5_SR_EN_V1 BIT(5)
304#define BE_TXD_INFO5_NDPA_DURATION GENMASK(31, 16)
305
306/* TX WD INFO DWORD 6 */
307#define BE_TXD_INFO6_UL_APEP_LEN GENMASK(11, 0)
308#define BE_TXD_INFO6_UL_GI_LTF GENMASK(14, 12)
309#define BE_TXD_INFO6_UL_DOPPLER BIT(15)
310#define BE_TXD_INFO6_UL_STBC BIT(16)
311#define BE_TXD_INFO6_UL_LENGTH_REF GENMASK(21, 18)
312#define BE_TXD_INFO6_UL_RF_GAIN_IDX GENMASK(31, 22)
313
314/* TX WD INFO DWORD 7 */
315#define BE_TXD_INFO7_UL_FIXED_GAIN_EN BIT(0)
316#define BE_TXD_INFO7_UL_PRI_EXP_RSSI_DBM GENMASK(7, 1)
317#define BE_TXD_INFO7_ELNA_IDX BIT(8)
318#define BE_TXD_INFO7_UL_APEP_UNIT GENMASK(10, 9)
319#define BE_TXD_INFO7_UL_TRI_PAD GENMASK(13, 11)
320#define BE_TXD_INFO7_UL_T_PE GENMASK(15, 14)
321#define BE_TXD_INFO7_UL_EHT_USR_PRES BIT(16)
322#define BE_TXD_INFO7_UL_HELTF_SYMBOL_NUM GENMASK(19, 17)
323#define BE_TXD_INFO7_ULBW GENMASK(21, 20)
324#define BE_TXD_INFO7_ULBW_EXT GENMASK(23, 22)
325#define BE_TXD_INFO7_USE_WD_UL GENMASK(25, 24)
326#define BE_TXD_INFO7_EXTEND_MODE_SEL GENMASK(31, 28)
327
328/* RX WD dword0 */
329#define AX_RXD_RPKT_LEN_MASK GENMASK(13, 0)
330#define AX_RXD_SHIFT_MASK GENMASK(15, 14)
331#define AX_RXD_WL_HD_IV_LEN_MASK GENMASK(21, 16)
332#define AX_RXD_BB_SEL BIT(22)
333#define AX_RXD_MAC_INFO_VLD BIT(23)
334#define AX_RXD_RPKT_TYPE_MASK GENMASK(27, 24)
335#define AX_RXD_DRV_INFO_SIZE_MASK GENMASK(30, 28)
336#define AX_RXD_LONG_RXD BIT(31)
337
338/* RX WD dword1 */
339#define AX_RXD_PPDU_TYPE_MASK GENMASK(3, 0)
340#define AX_RXD_PPDU_CNT_MASK GENMASK(6, 4)
341#define AX_RXD_SR_EN BIT(7)
342#define AX_RXD_USER_ID_MASK GENMASK(15, 8)
343#define AX_RXD_USER_ID_v1_MASK GENMASK(13, 8)
344#define AX_RXD_RX_DATARATE_MASK GENMASK(24, 16)
345#define AX_RXD_RX_GI_LTF_MASK GENMASK(27, 25)
346#define AX_RXD_NON_SRG_PPDU BIT(28)
347#define AX_RXD_INTER_PPDU BIT(29)
348#define AX_RXD_NON_SRG_PPDU_v1 BIT(14)
349#define AX_RXD_INTER_PPDU_v1 BIT(15)
350#define AX_RXD_BW_MASK GENMASK(31, 30)
351#define AX_RXD_BW_v1_MASK GENMASK(31, 29)
352
353/* RX WD dword2 */
354#define AX_RXD_FREERUN_CNT_MASK GENMASK(31, 0)
355
356/* RX WD dword3 */
357#define AX_RXD_A1_MATCH BIT(0)
358#define AX_RXD_SW_DEC BIT(1)
359#define AX_RXD_HW_DEC BIT(2)
360#define AX_RXD_AMPDU BIT(3)
361#define AX_RXD_AMPDU_END_PKT BIT(4)
362#define AX_RXD_AMSDU BIT(5)
363#define AX_RXD_AMSDU_CUT BIT(6)
364#define AX_RXD_LAST_MSDU BIT(7)
365#define AX_RXD_BYPASS BIT(8)
366#define AX_RXD_CRC32_ERR BIT(9)
367#define AX_RXD_ICV_ERR BIT(10)
368#define AX_RXD_MAGIC_WAKE BIT(11)
369#define AX_RXD_UNICAST_WAKE BIT(12)
370#define AX_RXD_PATTERN_WAKE BIT(13)
371#define AX_RXD_GET_CH_INFO_MASK GENMASK(15, 14)
372#define AX_RXD_PATTERN_IDX_MASK GENMASK(20, 16)
373#define AX_RXD_TARGET_IDC_MASK GENMASK(23, 21)
374#define AX_RXD_CHKSUM_OFFLOAD_EN BIT(24)
375#define AX_RXD_WITH_LLC BIT(25)
376#define AX_RXD_RX_STATISTICS BIT(26)
377
378/* RX WD dword4 */
379#define AX_RXD_TYPE_MASK GENMASK(1, 0)
380#define AX_RXD_MC BIT(2)
381#define AX_RXD_BC BIT(3)
382#define AX_RXD_MD BIT(4)
383#define AX_RXD_MF BIT(5)
384#define AX_RXD_PWR BIT(6)
385#define AX_RXD_QOS BIT(7)
386#define AX_RXD_TID_MASK GENMASK(11, 8)
387#define AX_RXD_EOSP BIT(12)
388#define AX_RXD_HTC BIT(13)
389#define AX_RXD_QNULL BIT(14)
390#define AX_RXD_SEQ_MASK GENMASK(27, 16)
391#define AX_RXD_FRAG_MASK GENMASK(31, 28)
392
393/* RX WD dword5 */
394#define AX_RXD_SEC_CAM_IDX_MASK GENMASK(7, 0)
395#define AX_RXD_ADDR_CAM_MASK GENMASK(15, 8)
396#define AX_RXD_MAC_ID_MASK GENMASK(23, 16)
397#define AX_RXD_RX_PL_ID_MASK GENMASK(27, 24)
398#define AX_RXD_ADDR_CAM_VLD BIT(28)
399#define AX_RXD_ADDR_FWD_EN BIT(29)
400#define AX_RXD_RX_PL_MATCH BIT(30)
401
402/* RX WD dword6 */
403#define AX_RXD_MAC_ADDR_MASK GENMASK(31, 0)
404
405/* RX WD dword7 */
406#define AX_RXD_MAC_ADDR_H_MASK GENMASK(15, 0)
407#define AX_RXD_SMART_ANT BIT(16)
408#define AX_RXD_SEC_TYPE_MASK GENMASK(20, 17)
409#define AX_RXD_HDR_CNV BIT(21)
410#define AX_RXD_HDR_OFFSET_MASK GENMASK(26, 22)
411#define AX_RXD_BIP_KEYID BIT(27)
412#define AX_RXD_BIP_ENC BIT(28)
413
414struct rtw89_rxinfo_user {
415	__le32 w0;
416};
417
418#define RTW89_RXINFO_USER_MAC_ID_VALID BIT(0)
419#define RTW89_RXINFO_USER_DATA BIT(1)
420#define RTW89_RXINFO_USER_CTRL BIT(2)
421#define RTW89_RXINFO_USER_MGMT BIT(3)
422#define RTW89_RXINFO_USER_BCN BIT(4)
423#define RTW89_RXINFO_USER_MACID GENMASK(15, 8)
424#define RTW89_RXINFO_USER_MACID_V1 GENMASK(31, 20)
425
426struct rtw89_rxinfo {
427	__le32 w0;
428	__le32 w1;
429	struct rtw89_rxinfo_user user[];
430} __packed;
431
432#define RTW89_RXINFO_W0_USR_NUM GENMASK(3, 0)
433#define RTW89_RXINFO_W0_USR_NUM_V1 GENMASK(4, 0)
434#define RTW89_RXINFO_W0_FW_DEFINE GENMASK(15, 8)
435#define RTW89_RXINFO_W0_PLCP_LEN_V1 GENMASK(23, 16)
436#define RTW89_RXINFO_W0_LSIG_LEN GENMASK(27, 16)
437#define RTW89_RXINFO_W0_INVALID_V1 BIT(27)
438#define RTW89_RXINFO_W0_IS_TO_SELF BIT(28)
439#define RTW89_RXINFO_W0_RX_CNT_VLD BIT(29)
440#define RTW89_RXINFO_W0_LONG_RXD GENMASK(31, 30)
441#define RTW89_RXINFO_W1_SERVICE GENMASK(15, 0)
442#define RTW89_RXINFO_W1_PLCP_LEN GENMASK(23, 16)
443
444struct rtw89_phy_sts_hdr {
445	__le32 w0;
446	__le32 w1;
447} __packed;
448
449#define RTW89_PHY_STS_HDR_W0_IE_MAP GENMASK(4, 0)
450#define RTW89_PHY_STS_HDR_W0_HDR_2_EN BIT(5)
451#define RTW89_PHY_STS_HDR_W0_VALID BIT(7)
452#define RTW89_PHY_STS_HDR_W0_LEN GENMASK(15, 8)
453#define RTW89_PHY_STS_HDR_W0_RSSI_AVG GENMASK(31, 24)
454#define RTW89_PHY_STS_HDR_W1_RSSI_A GENMASK(7, 0)
455#define RTW89_PHY_STS_HDR_W1_RSSI_B GENMASK(15, 8)
456#define RTW89_PHY_STS_HDR_W1_RSSI_C GENMASK(23, 16)
457#define RTW89_PHY_STS_HDR_W1_RSSI_D GENMASK(31, 24)
458
459struct rtw89_phy_sts_hdr_v2 {
460	__le32 w0;
461	__le32 w1;
462} __packed;
463
464#define RTW89_PHY_STS_HDR_V2_W0_PATH_EN GENMASK(20, 16)
465
466struct rtw89_phy_sts_iehdr {
467	__le32 w0;
468};
469
470#define RTW89_PHY_STS_IEHDR_TYPE GENMASK(4, 0)
471#define RTW89_PHY_STS_IEHDR_LEN GENMASK(11, 5)
472
473/* BE RXD dword0 */
474#define BE_RXD_RPKT_LEN_MASK GENMASK(13, 0)
475#define BE_RXD_SHIFT_MASK GENMASK(15, 14)
476#define BE_RXD_DRV_INFO_SZ_MASK GENMASK(19, 18)
477#define BE_RXD_HDR_CNV_SZ_MASK GENMASK(21, 20)
478#define BE_RXD_PHY_RPT_SZ_MASK GENMASK(23, 22)
479#define BE_RXD_RPKT_TYPE_MASK GENMASK(29, 24)
480#define BE_RXD_BB_SEL BIT(30)
481#define BE_RXD_LONG_RXD BIT(31)
482
483/* BE RXD dword1 */
484#define BE_RXD_PKT_ID_MASK GENMASK(11, 0)
485#define BE_RXD_FWD_TARGET_MASK GENMASK(23, 16)
486#define BE_RXD_BCN_FW_INFO_MASK GENMASK(25, 24)
487#define BE_RXD_FW_RLS BIT(26)
488
489/* BE RXD dword2 */
490#define BE_RXD_MAC_ID_MASK GENMASK(7, 0)
491#define BE_RXD_TYPE_MASK GENMASK(11, 10)
492#define BE_RXD_LAST_MSDU BIT(12)
493#define BE_RXD_AMSDU_CUT BIT(13)
494#define BE_RXD_ADDR_CAM_VLD BIT(14)
495#define BE_RXD_REORDER BIT(15)
496#define BE_RXD_SEQ_MASK GENMASK(27, 16)
497#define BE_RXD_TID_MASK GENMASK(31, 28)
498
499/* BE RXD dword3 */
500#define BE_RXD_SEC_TYPE_MASK GENMASK(3, 0)
501#define BE_RXD_BIP_KEYID BIT(4)
502#define BE_RXD_BIP_ENC BIT(5)
503#define BE_RXD_CRC32_ERR BIT(6)
504#define BE_RXD_ICV_ERR BIT(7)
505#define BE_RXD_HW_DEC BIT(8)
506#define BE_RXD_SW_DEC BIT(9)
507#define BE_RXD_A1_MATCH BIT(10)
508#define BE_RXD_AMPDU BIT(11)
509#define BE_RXD_AMPDU_EOF BIT(12)
510#define BE_RXD_AMSDU BIT(13)
511#define BE_RXD_MC BIT(14)
512#define BE_RXD_BC BIT(15)
513#define BE_RXD_MD BIT(16)
514#define BE_RXD_MF BIT(17)
515#define BE_RXD_PWR BIT(18)
516#define BE_RXD_QOS BIT(19)
517#define BE_RXD_EOSP BIT(20)
518#define BE_RXD_HTC BIT(21)
519#define BE_RXD_QNULL BIT(22)
520#define BE_RXD_A4_FRAME BIT(23)
521#define BE_RXD_FRAG_MASK GENMASK(27, 24)
522#define BE_RXD_GET_CH_INFO_V1_MASK GENMASK(31, 30)
523
524/* BE RXD dword4 */
525#define BE_RXD_PPDU_TYPE_MASK GENMASK(7, 0)
526#define BE_RXD_PPDU_CNT_MASK GENMASK(10, 8)
527#define BE_RXD_BW_MASK GENMASK(14, 12)
528#define BE_RXD_RX_GI_LTF_MASK GENMASK(18, 16)
529#define BE_RXD_RX_REORDER_FIELD_EN BIT(19)
530#define BE_RXD_RX_DATARATE_MASK GENMASK(31, 20)
531
532/* BE RXD dword5 */
533#define BE_RXD_FREERUN_CNT_MASK GENMASK(31, 0)
534
535/* BE RXD dword6 */
536#define BE_RXD_ADDR_CAM_MASK GENMASK(7, 0)
537#define BE_RXD_SR_EN BIT(13)
538#define BE_RXD_NON_SRG_PPDU BIT(14)
539#define BE_RXD_INTER_PPDU BIT(15)
540#define BE_RXD_USER_ID_MASK GENMASK(21, 16)
541#define BE_RXD_RX_STATISTICS BIT(22)
542#define BE_RXD_SMART_ANT BIT(23)
543#define BE_RXD_SEC_CAM_IDX_MASK GENMASK(31, 24)
544
545/* BE RXD dword7 */
546#define BE_RXD_PATTERN_IDX_MASK GENMASK(4, 0)
547#define BE_RXD_MAGIC_WAKE BIT(5)
548#define BE_RXD_UNICAST_WAKE BIT(6)
549#define BE_RXD_PATTERN_WAKE BIT(7)
550#define BE_RXD_RX_PL_MATCH BIT(8)
551#define BE_RXD_RX_PL_ID_MASK GENMASK(15, 12)
552#define BE_RXD_HDR_CNV BIT(16)
553#define BE_RXD_NAT25_HIT BIT(17)
554#define BE_RXD_IS_DA BIT(18)
555#define BE_RXD_CHKSUM_OFFLOAD_EN BIT(19)
556#define BE_RXD_RXSC_ENTRY_MASK GENMASK(22, 20)
557#define BE_RXD_RXSC_HIT BIT(23)
558#define BE_RXD_WITH_LLC BIT(24)
559#define BE_RXD_RX_AGG_FIELD_EN BIT(25)
560
561/* BE RXD dword8 */
562#define BE_RXD_MAC_ADDR_MASK GENMASK(31, 0)
563
564/* BE RXD dword9 */
565#define BE_RXD_MAC_ADDR_H_MASK GENMASK(15, 0)
566#define BE_RXD_HDR_OFFSET_MASK GENMASK(20, 16)
567#define BE_RXD_WL_HD_IV_LEN_MASK GENMASK(26, 21)
568
569/* BE RXD - PHY RPT dword0 */
570#define BE_RXD_PHY_RSSI GENMASK(11, 0)
571
572struct rtw89_phy_sts_ie00 {
573	__le32 w0;
574	__le32 w1;
575	__le32 w2;
576	__le32 w3;
577} __packed;
578
579#define RTW89_PHY_STS_IE00_W0_RPL GENMASK(15, 7)
580#define RTW89_PHY_STS_IE00_W3_RX_PATH_EN GENMASK(31, 28)
581
582struct rtw89_phy_sts_ie00_v2 {
583	__le32 w0;
584	__le32 w1;
585	__le32 w2;
586	__le32 w3;
587	__le32 w4;
588	__le32 w5;
589	__le32 w6;
590	__le32 w7;
591} __packed;
592
593#define RTW89_PHY_STS_IE00_V2_W4_RPL_TD_A GENMASK(8, 0)
594#define RTW89_PHY_STS_IE00_V2_W4_RPL_TD_B GENMASK(17, 9)
595#define RTW89_PHY_STS_IE00_V2_W4_RPL_TD_C GENMASK(26, 18)
596#define RTW89_PHY_STS_IE00_V2_W5_RPL_TD_D GENMASK(8, 0)
597
598struct rtw89_phy_sts_ie01 {
599	__le32 w0;
600	__le32 w1;
601	__le32 w2;
602	__le32 w3;
603	__le32 w4;
604	__le32 w5;
605} __packed;
606
607#define RTW89_PHY_STS_IE01_W0_CH_IDX GENMASK(23, 16)
608#define RTW89_PHY_STS_IE01_W0_RSSI_AVG_FD GENMASK(15, 8)
609#define RTW89_PHY_STS_IE01_W0_RX_PATH_EN GENMASK(31, 28)
610#define RTW89_PHY_STS_IE01_W1_FD_CFO GENMASK(19, 8)
611#define RTW89_PHY_STS_IE01_W1_PREMB_CFO GENMASK(31, 20)
612#define RTW89_PHY_STS_IE01_W2_AVG_SNR GENMASK(5, 0)
613#define RTW89_PHY_STS_IE01_W2_EVM_MAX GENMASK(15, 8)
614#define RTW89_PHY_STS_IE01_W2_EVM_MIN GENMASK(23, 16)
615#define RTW89_PHY_STS_IE01_W2_LDPC BIT(28)
616#define RTW89_PHY_STS_IE01_W2_STBC BIT(30)
617
618struct rtw89_phy_sts_ie01_v2 {
619	__le32 w0;
620	__le32 w1;
621	__le32 w2;
622	__le32 w3;
623	__le32 w4;
624	__le32 w5;
625	__le32 w6;
626	__le32 w7;
627	__le32 w8;
628	__le32 w9;
629} __packed;
630
631#define RTW89_PHY_STS_IE01_V2_W5_BW_IDX GENMASK(31, 29)
632#define RTW89_PHY_STS_IE01_V2_W8_RPL_FD_A GENMASK(11, 4)
633#define RTW89_PHY_STS_IE01_V2_W8_RPL_FD_B GENMASK(23, 16)
634#define RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C GENMASK(11, 4)
635#define RTW89_PHY_STS_IE01_V2_W9_RPL_FD_D GENMASK(23, 16)
636
637enum rtw89_tx_channel {
638	RTW89_TXCH_ACH0	= 0,
639	RTW89_TXCH_ACH1	= 1,
640	RTW89_TXCH_ACH2	= 2,
641	RTW89_TXCH_ACH3	= 3,
642	RTW89_TXCH_ACH4	= 4,
643	RTW89_TXCH_ACH5	= 5,
644	RTW89_TXCH_ACH6	= 6,
645	RTW89_TXCH_ACH7	= 7,
646	RTW89_TXCH_CH8	= 8,  /* MGMT Band 0 */
647	RTW89_TXCH_CH9	= 9,  /* HI Band 0 */
648	RTW89_TXCH_CH10	= 10, /* MGMT Band 1 */
649	RTW89_TXCH_CH11	= 11, /* HI Band 1 */
650	RTW89_TXCH_CH12	= 12, /* FW CMD */
651
652	/* keep last */
653	RTW89_TXCH_NUM,
654	RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1
655};
656
657enum rtw89_rx_channel {
658	RTW89_RXCH_RXQ	= 0,
659	RTW89_RXCH_RPQ	= 1,
660
661	/* keep last */
662	RTW89_RXCH_NUM,
663	RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1
664};
665
666enum rtw89_tx_qsel {
667	RTW89_TX_QSEL_BE_0		= 0x00,
668	RTW89_TX_QSEL_BK_0		= 0x01,
669	RTW89_TX_QSEL_VI_0		= 0x02,
670	RTW89_TX_QSEL_VO_0		= 0x03,
671	RTW89_TX_QSEL_BE_1		= 0x04,
672	RTW89_TX_QSEL_BK_1		= 0x05,
673	RTW89_TX_QSEL_VI_1		= 0x06,
674	RTW89_TX_QSEL_VO_1		= 0x07,
675	RTW89_TX_QSEL_BE_2		= 0x08,
676	RTW89_TX_QSEL_BK_2		= 0x09,
677	RTW89_TX_QSEL_VI_2		= 0x0a,
678	RTW89_TX_QSEL_VO_2		= 0x0b,
679	RTW89_TX_QSEL_BE_3		= 0x0c,
680	RTW89_TX_QSEL_BK_3		= 0x0d,
681	RTW89_TX_QSEL_VI_3		= 0x0e,
682	RTW89_TX_QSEL_VO_3		= 0x0f,
683	RTW89_TX_QSEL_B0_BCN		= 0x10,
684	RTW89_TX_QSEL_B0_HI		= 0x11,
685	RTW89_TX_QSEL_B0_MGMT		= 0x12,
686	RTW89_TX_QSEL_B0_NOPS		= 0x13,
687	RTW89_TX_QSEL_B0_MGMT_FAST	= 0x14,
688	/* reserved */
689	/* reserved */
690	/* reserved */
691	RTW89_TX_QSEL_B1_BCN		= 0x18,
692	RTW89_TX_QSEL_B1_HI		= 0x19,
693	RTW89_TX_QSEL_B1_MGMT		= 0x1a,
694	RTW89_TX_QSEL_B1_NOPS		= 0x1b,
695	RTW89_TX_QSEL_B1_MGMT_FAST	= 0x1c,
696	/* reserved */
697	/* reserved */
698	/* reserved */
699};
700
701static inline u8 rtw89_core_get_qsel(struct rtw89_dev *rtwdev, u8 tid)
702{
703	switch (tid) {
704	default:
705		rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid);
706		fallthrough;
707	case 0:
708	case 3:
709		return RTW89_TX_QSEL_BE_0;
710	case 1:
711	case 2:
712		return RTW89_TX_QSEL_BK_0;
713	case 4:
714	case 5:
715		return RTW89_TX_QSEL_VI_0;
716	case 6:
717	case 7:
718		return RTW89_TX_QSEL_VO_0;
719	}
720}
721
722static inline u8
723rtw89_core_get_qsel_mgmt(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req)
724{
725	struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
726	struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
727
728	if (desc_info->hiq) {
729		if (rtwvif_link->mac_idx == RTW89_MAC_1)
730			return RTW89_TX_QSEL_B1_HI;
731		else
732			return RTW89_TX_QSEL_B0_HI;
733	}
734
735	if (rtwvif_link->mac_idx == RTW89_MAC_1)
736		return RTW89_TX_QSEL_B1_MGMT;
737	else
738		return RTW89_TX_QSEL_B0_MGMT;
739}
740
741static inline u8 rtw89_core_get_tid_indicate(struct rtw89_dev *rtwdev, u8 tid)
742{
743	switch (tid) {
744	case 3:
745	case 2:
746	case 5:
747	case 7:
748		return 1;
749	default:
750		rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid);
751		fallthrough;
752	case 0:
753	case 1:
754	case 4:
755	case 6:
756		return 0;
757	}
758}
759
760#endif