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rtw8852b_common.c
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linux-6.19.14/drivers/net/wireless/realtek/rtw89/rtw8852b_common.c
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* Copyright(c) 2024 Realtek Corporation 3 */ 4 5#include "coex.h" 6#include "debug.h" 7#include "mac.h" 8#include "phy.h" 9#include "reg.h" 10#include "rtw8852b_common.h" 11#include "sar.h" 12#include "util.h" 13 14static const struct rtw89_reg3_def rtw8852bx_pmac_ht20_mcs7_tbl[] = { 15 {0x4580, 0x0000ffff, 0x0}, 16 {0x4580, 0xffff0000, 0x0}, 17 {0x4584, 0x0000ffff, 0x0}, 18 {0x4584, 0xffff0000, 0x0}, 19 {0x4580, 0x0000ffff, 0x1}, 20 {0x4578, 0x00ffffff, 0x2018b}, 21 {0x4570, 0x03ffffff, 0x7}, 22 {0x4574, 0x03ffffff, 0x32407}, 23 {0x45b8, 0x00000010, 0x0}, 24 {0x45b8, 0x00000100, 0x0}, 25 {0x45b8, 0x00000080, 0x0}, 26 {0x45b8, 0x00000008, 0x0}, 27 {0x45a0, 0x0000ff00, 0x0}, 28 {0x45a0, 0xff000000, 0x1}, 29 {0x45a4, 0x0000ff00, 0x2}, 30 {0x45a4, 0xff000000, 0x3}, 31 {0x45b8, 0x00000020, 0x0}, 32 {0x4568, 0xe0000000, 0x0}, 33 {0x45b8, 0x00000002, 0x1}, 34 {0x456c, 0xe0000000, 0x0}, 35 {0x45b4, 0x00006000, 0x0}, 36 {0x45b4, 0x00001800, 0x1}, 37 {0x45b8, 0x00000040, 0x0}, 38 {0x45b8, 0x00000004, 0x0}, 39 {0x45b8, 0x00000200, 0x0}, 40 {0x4598, 0xf8000000, 0x0}, 41 {0x45b8, 0x00100000, 0x0}, 42 {0x45a8, 0x00000fc0, 0x0}, 43 {0x45b8, 0x00200000, 0x0}, 44 {0x45b0, 0x00000038, 0x0}, 45 {0x45b0, 0x000001c0, 0x0}, 46 {0x45a0, 0x000000ff, 0x0}, 47 {0x45b8, 0x00400000, 0x0}, 48 {0x4590, 0x000007ff, 0x0}, 49 {0x45b0, 0x00000e00, 0x0}, 50 {0x45ac, 0x0000001f, 0x0}, 51 {0x45b8, 0x00800000, 0x0}, 52 {0x45a8, 0x0003f000, 0x0}, 53 {0x45b8, 0x01000000, 0x0}, 54 {0x45b0, 0x00007000, 0x0}, 55 {0x45b0, 0x00038000, 0x0}, 56 {0x45a0, 0x00ff0000, 0x0}, 57 {0x45b8, 0x02000000, 0x0}, 58 {0x4590, 0x003ff800, 0x0}, 59 {0x45b0, 0x001c0000, 0x0}, 60 {0x45ac, 0x000003e0, 0x0}, 61 {0x45b8, 0x04000000, 0x0}, 62 {0x45a8, 0x00fc0000, 0x0}, 63 {0x45b8, 0x08000000, 0x0}, 64 {0x45b0, 0x00e00000, 0x0}, 65 {0x45b0, 0x07000000, 0x0}, 66 {0x45a4, 0x000000ff, 0x0}, 67 {0x45b8, 0x10000000, 0x0}, 68 {0x4594, 0x000007ff, 0x0}, 69 {0x45b0, 0x38000000, 0x0}, 70 {0x45ac, 0x00007c00, 0x0}, 71 {0x45b8, 0x20000000, 0x0}, 72 {0x45a8, 0x3f000000, 0x0}, 73 {0x45b8, 0x40000000, 0x0}, 74 {0x45b4, 0x00000007, 0x0}, 75 {0x45b4, 0x00000038, 0x0}, 76 {0x45a4, 0x00ff0000, 0x0}, 77 {0x45b8, 0x80000000, 0x0}, 78 {0x4594, 0x003ff800, 0x0}, 79 {0x45b4, 0x000001c0, 0x0}, 80 {0x4598, 0xf8000000, 0x0}, 81 {0x45b8, 0x00100000, 0x0}, 82 {0x45a8, 0x00000fc0, 0x7}, 83 {0x45b8, 0x00200000, 0x0}, 84 {0x45b0, 0x00000038, 0x0}, 85 {0x45b0, 0x000001c0, 0x0}, 86 {0x45a0, 0x000000ff, 0x0}, 87 {0x45b4, 0x06000000, 0x0}, 88 {0x45b0, 0x00000007, 0x0}, 89 {0x45b8, 0x00080000, 0x0}, 90 {0x45a8, 0x0000003f, 0x0}, 91 {0x457c, 0xffe00000, 0x1}, 92 {0x4530, 0xffffffff, 0x0}, 93 {0x4588, 0x00003fff, 0x0}, 94 {0x4598, 0x000001ff, 0x0}, 95 {0x4534, 0xffffffff, 0x0}, 96 {0x4538, 0xffffffff, 0x0}, 97 {0x453c, 0xffffffff, 0x0}, 98 {0x4588, 0x0fffc000, 0x0}, 99 {0x4598, 0x0003fe00, 0x0}, 100 {0x4540, 0xffffffff, 0x0}, 101 {0x4544, 0xffffffff, 0x0}, 102 {0x4548, 0xffffffff, 0x0}, 103 {0x458c, 0x00003fff, 0x0}, 104 {0x4598, 0x07fc0000, 0x0}, 105 {0x454c, 0xffffffff, 0x0}, 106 {0x4550, 0xffffffff, 0x0}, 107 {0x4554, 0xffffffff, 0x0}, 108 {0x458c, 0x0fffc000, 0x0}, 109 {0x459c, 0x000001ff, 0x0}, 110 {0x4558, 0xffffffff, 0x0}, 111 {0x455c, 0xffffffff, 0x0}, 112 {0x4530, 0xffffffff, 0x4e790001}, 113 {0x4588, 0x00003fff, 0x0}, 114 {0x4598, 0x000001ff, 0x1}, 115 {0x4534, 0xffffffff, 0x0}, 116 {0x4538, 0xffffffff, 0x4b}, 117 {0x45ac, 0x38000000, 0x7}, 118 {0x4588, 0xf0000000, 0x0}, 119 {0x459c, 0x7e000000, 0x0}, 120 {0x45b8, 0x00040000, 0x0}, 121 {0x45b8, 0x00020000, 0x0}, 122 {0x4590, 0xffc00000, 0x0}, 123 {0x45b8, 0x00004000, 0x0}, 124 {0x4578, 0xff000000, 0x0}, 125 {0x45b8, 0x00000400, 0x0}, 126 {0x45b8, 0x00000800, 0x0}, 127 {0x45b8, 0x00001000, 0x0}, 128 {0x45b8, 0x00002000, 0x0}, 129 {0x45b4, 0x00018000, 0x0}, 130 {0x45ac, 0x07800000, 0x0}, 131 {0x45b4, 0x00000600, 0x2}, 132 {0x459c, 0x0001fe00, 0x80}, 133 {0x45ac, 0x00078000, 0x3}, 134 {0x459c, 0x01fe0000, 0x1}, 135}; 136 137static const struct rtw89_reg3_def rtw8852bx_btc_preagc_en_defs[] = { 138 {0x46D0, GENMASK(1, 0), 0x3}, 139 {0x4790, GENMASK(1, 0), 0x3}, 140 {0x4AD4, GENMASK(31, 0), 0xf}, 141 {0x4AE0, GENMASK(31, 0), 0xf}, 142 {0x4688, GENMASK(31, 24), 0x80}, 143 {0x476C, GENMASK(31, 24), 0x80}, 144 {0x4694, GENMASK(7, 0), 0x80}, 145 {0x4694, GENMASK(15, 8), 0x80}, 146 {0x4778, GENMASK(7, 0), 0x80}, 147 {0x4778, GENMASK(15, 8), 0x80}, 148 {0x4AE4, GENMASK(23, 0), 0x780D1E}, 149 {0x4AEC, GENMASK(23, 0), 0x780D1E}, 150 {0x469C, GENMASK(31, 26), 0x34}, 151 {0x49F0, GENMASK(31, 26), 0x34}, 152}; 153 154static DECLARE_PHY_REG3_TBL(rtw8852bx_btc_preagc_en_defs); 155 156static const struct rtw89_reg3_def rtw8852bx_btc_preagc_dis_defs[] = { 157 {0x46D0, GENMASK(1, 0), 0x0}, 158 {0x4790, GENMASK(1, 0), 0x0}, 159 {0x4AD4, GENMASK(31, 0), 0x60}, 160 {0x4AE0, GENMASK(31, 0), 0x60}, 161 {0x4688, GENMASK(31, 24), 0x1a}, 162 {0x476C, GENMASK(31, 24), 0x1a}, 163 {0x4694, GENMASK(7, 0), 0x2a}, 164 {0x4694, GENMASK(15, 8), 0x2a}, 165 {0x4778, GENMASK(7, 0), 0x2a}, 166 {0x4778, GENMASK(15, 8), 0x2a}, 167 {0x4AE4, GENMASK(23, 0), 0x79E99E}, 168 {0x4AEC, GENMASK(23, 0), 0x79E99E}, 169 {0x469C, GENMASK(31, 26), 0x26}, 170 {0x49F0, GENMASK(31, 26), 0x26}, 171}; 172 173static DECLARE_PHY_REG3_TBL(rtw8852bx_btc_preagc_dis_defs); 174 175static void rtw8852bx_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 176 struct rtw8852bx_efuse *map) 177{ 178 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 179 struct rtw8852bx_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 180 u8 i, j; 181 182 tssi->thermal[RF_PATH_A] = map->path_a_therm; 183 tssi->thermal[RF_PATH_B] = map->path_b_therm; 184 185 for (i = 0; i < RF_PATH_NUM_8852BX; i++) { 186 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 187 sizeof(ofst[i]->cck_tssi)); 188 189 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 190 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 191 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 192 i, j, tssi->tssi_cck[i][j]); 193 194 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 195 sizeof(ofst[i]->bw40_tssi)); 196 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 197 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 198 199 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 200 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 201 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 202 i, j, tssi->tssi_mcs[i][j]); 203 } 204} 205 206static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low) 207{ 208 if (high) 209 *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3); 210 if (low) 211 *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3); 212 213 return data != 0xff; 214} 215 216static void rtw8852bx_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev, 217 struct rtw8852bx_efuse *map) 218{ 219 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 220 bool valid = false; 221 222 valid |= _decode_efuse_gain(map->rx_gain_2g_cck, 223 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK], 224 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]); 225 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm, 226 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM], 227 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]); 228 valid |= _decode_efuse_gain(map->rx_gain_5g_low, 229 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW], 230 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]); 231 valid |= _decode_efuse_gain(map->rx_gain_5g_mid, 232 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID], 233 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]); 234 valid |= _decode_efuse_gain(map->rx_gain_5g_high, 235 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH], 236 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]); 237 238 gain->offset_valid = valid; 239} 240 241static int __rtw8852bx_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map, 242 enum rtw89_efuse_block block) 243{ 244 struct rtw89_efuse *efuse = &rtwdev->efuse; 245 struct rtw8852bx_efuse *map; 246 247 map = (struct rtw8852bx_efuse *)log_map; 248 249 efuse->country_code[0] = map->country_code[0]; 250 efuse->country_code[1] = map->country_code[1]; 251 rtw8852bx_efuse_parsing_tssi(rtwdev, map); 252 rtw8852bx_efuse_parsing_gain_offset(rtwdev, map); 253 254 switch (rtwdev->hci.type) { 255 case RTW89_HCI_TYPE_PCIE: 256 ether_addr_copy(efuse->addr, map->e.mac_addr); 257 break; 258 case RTW89_HCI_TYPE_USB: 259 ether_addr_copy(efuse->addr, map->u.mac_addr); 260 break; 261 default: 262 return -EOPNOTSUPP; 263 } 264 265 efuse->rfe_type = map->rfe_type; 266 efuse->xtal_cap = map->xtal_k; 267 268 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 269 270 return 0; 271} 272 273static void rtw8852bx_phycap_parsing_power_cal(struct rtw89_dev *rtwdev, u8 *phycap_map) 274{ 275#define PWR_K_CHK_OFFSET 0x5E9 276#define PWR_K_CHK_VALUE 0xAA 277 u32 offset = PWR_K_CHK_OFFSET - rtwdev->chip->phycap_addr; 278 279 if (phycap_map[offset] == PWR_K_CHK_VALUE) 280 rtwdev->efuse.power_k_valid = true; 281} 282 283static void rtw8852bx_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 284{ 285 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 286 static const u32 tssi_trim_addr[RF_PATH_NUM_8852BX] = {0x5D6, 0x5AB}; 287 u32 addr = rtwdev->chip->phycap_addr; 288 bool pg = false; 289 u32 ofst; 290 u8 i, j; 291 292 for (i = 0; i < RF_PATH_NUM_8852BX; i++) { 293 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 294 /* addrs are in decreasing order */ 295 ofst = tssi_trim_addr[i] - addr - j; 296 tssi->tssi_trim[i][j] = phycap_map[ofst]; 297 298 if (phycap_map[ofst] != 0xff) 299 pg = true; 300 } 301 } 302 303 if (!pg) { 304 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 305 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 306 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 307 } 308 309 for (i = 0; i < RF_PATH_NUM_8852BX; i++) 310 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 311 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 312 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 313 i, j, tssi->tssi_trim[i][j], 314 tssi_trim_addr[i] - j); 315} 316 317static void rtw8852bx_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 318 u8 *phycap_map) 319{ 320 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 321 static const u32 thm_trim_addr[RF_PATH_NUM_8852BX] = {0x5DF, 0x5DC}; 322 u32 addr = rtwdev->chip->phycap_addr; 323 u8 i; 324 325 for (i = 0; i < RF_PATH_NUM_8852BX; i++) { 326 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 327 328 rtw89_debug(rtwdev, RTW89_DBG_RFK, 329 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 330 i, info->thermal_trim[i]); 331 332 if (info->thermal_trim[i] != 0xff) 333 info->pg_thermal_trim = true; 334 } 335} 336 337static void rtw8852bx_thermal_trim(struct rtw89_dev *rtwdev) 338{ 339#define __thm_setting(raw) \ 340({ \ 341 u8 __v = (raw); \ 342 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 343}) 344 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 345 u8 i, val; 346 347 if (!info->pg_thermal_trim) { 348 rtw89_debug(rtwdev, RTW89_DBG_RFK, 349 "[THERMAL][TRIM] no PG, do nothing\n"); 350 351 return; 352 } 353 354 for (i = 0; i < RF_PATH_NUM_8852BX; i++) { 355 val = __thm_setting(info->thermal_trim[i]); 356 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 357 358 rtw89_debug(rtwdev, RTW89_DBG_RFK, 359 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 360 i, val); 361 } 362#undef __thm_setting 363} 364 365static void rtw8852bx_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 366 u8 *phycap_map) 367{ 368 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 369 static const u32 pabias_trim_addr[RF_PATH_NUM_8852BX] = {0x5DE, 0x5DB}; 370 u32 addr = rtwdev->chip->phycap_addr; 371 u8 i; 372 373 for (i = 0; i < RF_PATH_NUM_8852BX; i++) { 374 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 375 376 rtw89_debug(rtwdev, RTW89_DBG_RFK, 377 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 378 i, info->pa_bias_trim[i]); 379 380 if (info->pa_bias_trim[i] != 0xff) 381 info->pg_pa_bias_trim = true; 382 } 383} 384 385static void rtw8852bx_pa_bias_trim(struct rtw89_dev *rtwdev) 386{ 387 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 388 u8 pabias_2g, pabias_5g; 389 u8 i; 390 391 if (!info->pg_pa_bias_trim) { 392 rtw89_debug(rtwdev, RTW89_DBG_RFK, 393 "[PA_BIAS][TRIM] no PG, do nothing\n"); 394 395 return; 396 } 397 398 for (i = 0; i < RF_PATH_NUM_8852BX; i++) { 399 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 400 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 401 402 rtw89_debug(rtwdev, RTW89_DBG_RFK, 403 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 404 i, pabias_2g, pabias_5g); 405 406 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 407 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 408 } 409} 410 411static void rtw8852bx_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map) 412{ 413 static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = { 414 {0x5BB, 0x5BA, 0, 0x5B9, 0x5B8}, 415 {0x590, 0x58F, 0, 0x58E, 0x58D}, 416 }; 417 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 418 u32 phycap_addr = rtwdev->chip->phycap_addr; 419 bool valid = false; 420 int path, i; 421 u8 data; 422 423 for (path = 0; path < 2; path++) 424 for (i = 0; i < RTW89_SUBBAND_2GHZ_5GHZ_NR; i++) { 425 if (comp_addrs[path][i] == 0) 426 continue; 427 428 data = phycap_map[comp_addrs[path][i] - phycap_addr]; 429 valid |= _decode_efuse_gain(data, NULL, 430 &gain->comp[path][i]); 431 } 432 433 gain->comp_valid = valid; 434} 435 436static int __rtw8852bx_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 437{ 438 rtw8852bx_phycap_parsing_power_cal(rtwdev, phycap_map); 439 rtw8852bx_phycap_parsing_tssi(rtwdev, phycap_map); 440 rtw8852bx_phycap_parsing_thermal_trim(rtwdev, phycap_map); 441 rtw8852bx_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 442 rtw8852bx_phycap_parsing_gain_comp(rtwdev, phycap_map); 443 444 return 0; 445} 446 447static void __rtw8852bx_power_trim(struct rtw89_dev *rtwdev) 448{ 449 rtw8852bx_thermal_trim(rtwdev); 450 rtw8852bx_pa_bias_trim(rtwdev); 451} 452 453static void __rtw8852bx_set_channel_mac(struct rtw89_dev *rtwdev, 454 const struct rtw89_chan *chan, 455 u8 mac_idx) 456{ 457 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); 458 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 459 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); 460 u8 txsc20 = 0, txsc40 = 0; 461 462 switch (chan->band_width) { 463 case RTW89_CHANNEL_WIDTH_80: 464 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40); 465 fallthrough; 466 case RTW89_CHANNEL_WIDTH_40: 467 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20); 468 break; 469 default: 470 break; 471 } 472 473 switch (chan->band_width) { 474 case RTW89_CHANNEL_WIDTH_80: 475 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); 476 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); 477 break; 478 case RTW89_CHANNEL_WIDTH_40: 479 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); 480 rtw89_write32(rtwdev, sub_carr, txsc20); 481 break; 482 case RTW89_CHANNEL_WIDTH_20: 483 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); 484 rtw89_write32(rtwdev, sub_carr, 0); 485 break; 486 default: 487 break; 488 } 489 490 if (chan->channel > 14) { 491 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE); 492 rtw89_write8_set(rtwdev, chk_rate, 493 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 494 } else { 495 rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE); 496 rtw89_write8_clr(rtwdev, chk_rate, 497 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 498 } 499} 500 501static const u32 rtw8852bx_sco_barker_threshold[14] = { 502 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, 503 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 504}; 505 506static const u32 rtw8852bx_sco_cck_threshold[14] = { 507 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, 508 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed 509}; 510 511static void rtw8852bx_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch) 512{ 513 u8 ch_element = primary_ch - 1; 514 515 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, 516 rtw8852bx_sco_barker_threshold[ch_element]); 517 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, 518 rtw8852bx_sco_cck_threshold[ch_element]); 519} 520 521static u8 rtw8852bx_sco_mapping(u8 central_ch) 522{ 523 if (central_ch == 1) 524 return 109; 525 else if (central_ch >= 2 && central_ch <= 6) 526 return 108; 527 else if (central_ch >= 7 && central_ch <= 10) 528 return 107; 529 else if (central_ch >= 11 && central_ch <= 14) 530 return 106; 531 else if (central_ch == 36 || central_ch == 38) 532 return 51; 533 else if (central_ch >= 40 && central_ch <= 58) 534 return 50; 535 else if (central_ch >= 60 && central_ch <= 64) 536 return 49; 537 else if (central_ch == 100 || central_ch == 102) 538 return 48; 539 else if (central_ch >= 104 && central_ch <= 126) 540 return 47; 541 else if (central_ch >= 128 && central_ch <= 151) 542 return 46; 543 else if (central_ch >= 153 && central_ch <= 177) 544 return 45; 545 else 546 return 0; 547} 548 549struct rtw8852bx_bb_gain { 550 u32 gain_g[BB_PATH_NUM_8852BX]; 551 u32 gain_a[BB_PATH_NUM_8852BX]; 552 u32 gain_mask; 553}; 554 555static const struct rtw8852bx_bb_gain bb_gain_lna[LNA_GAIN_NUM] = { 556 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 557 .gain_mask = 0x00ff0000 }, 558 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 559 .gain_mask = 0xff000000 }, 560 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 561 .gain_mask = 0x000000ff }, 562 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 563 .gain_mask = 0x0000ff00 }, 564 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 565 .gain_mask = 0x00ff0000 }, 566 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 567 .gain_mask = 0xff000000 }, 568 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 569 .gain_mask = 0x000000ff }, 570}; 571 572static const struct rtw8852bx_bb_gain bb_gain_tia[TIA_GAIN_NUM] = { 573 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 574 .gain_mask = 0x00ff0000 }, 575 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 576 .gain_mask = 0xff000000 }, 577}; 578 579static void rtw8852bx_set_gain_error(struct rtw89_dev *rtwdev, 580 enum rtw89_subband subband, 581 enum rtw89_rf_path path) 582{ 583 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 584 u8 gain_band = rtw89_subband_to_bb_gain_band(subband); 585 s32 val; 586 u32 reg; 587 u32 mask; 588 int i; 589 590 for (i = 0; i < LNA_GAIN_NUM; i++) { 591 if (subband == RTW89_CH_2G) 592 reg = bb_gain_lna[i].gain_g[path]; 593 else 594 reg = bb_gain_lna[i].gain_a[path]; 595 596 mask = bb_gain_lna[i].gain_mask; 597 val = gain->lna_gain[gain_band][path][i]; 598 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 599 } 600 601 for (i = 0; i < TIA_GAIN_NUM; i++) { 602 if (subband == RTW89_CH_2G) 603 reg = bb_gain_tia[i].gain_g[path]; 604 else 605 reg = bb_gain_tia[i].gain_a[path]; 606 607 mask = bb_gain_tia[i].gain_mask; 608 val = gain->tia_gain[gain_band][path][i]; 609 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 610 } 611} 612 613static void rtw8852bt_ext_loss_avg_update(struct rtw89_dev *rtwdev, 614 s8 ext_loss_a, s8 ext_loss_b) 615{ 616 s8 ext_loss_avg; 617 u64 linear; 618 u8 pwrofst; 619 620 if (ext_loss_a == ext_loss_b) { 621 ext_loss_avg = ext_loss_a; 622 } else { 623 linear = rtw89_db_to_linear(abs(ext_loss_a - ext_loss_b)) + 1; 624 linear /= 2; 625 ext_loss_avg = rtw89_linear_to_db(linear); 626 ext_loss_avg += min(ext_loss_a, ext_loss_b); 627 } 628 629 pwrofst = max(DIV_ROUND_CLOSEST(ext_loss_avg, 4) + 16, EDCCA_PWROFST_DEFAULT); 630 631 rtw89_phy_write32_mask(rtwdev, R_PWOFST, B_PWOFST, pwrofst); 632} 633 634static void rtw8852bx_set_gain_offset(struct rtw89_dev *rtwdev, 635 enum rtw89_subband subband, 636 enum rtw89_phy_idx phy_idx) 637{ 638 static const u32 gain_err_addr[2] = {R_P0_AGC_RSVD, R_P1_AGC_RSVD}; 639 static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA1_LNA6_OP1DB_V1, 640 R_PATH1_G_TIA1_LNA6_OP1DB_V1}; 641 struct rtw89_hal *hal = &rtwdev->hal; 642 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain; 643 enum rtw89_gain_offset gain_ofdm_band; 644 s8 ext_loss_a = 0, ext_loss_b = 0; 645 s32 offset_a, offset_b; 646 s32 offset_ofdm, offset_cck; 647 s32 tmp; 648 u8 path; 649 650 if (!efuse_gain->comp_valid) 651 goto next; 652 653 for (path = RF_PATH_A; path < BB_PATH_NUM_8852BX; path++) { 654 tmp = efuse_gain->comp[path][subband]; 655 tmp = clamp_t(s32, tmp << 2, S8_MIN, S8_MAX); 656 rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp); 657 } 658 659next: 660 if (!efuse_gain->offset_valid) 661 goto ext_loss; 662 663 gain_ofdm_band = rtw89_subband_to_gain_offset_band_of_ofdm(subband); 664 665 offset_a = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band]; 666 offset_b = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band]; 667 668 tmp = -((offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2)); 669 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 670 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp); 671 672 tmp = -((offset_b << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2)); 673 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 674 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_B], B_PATH0_R_G_OFST_MASK, tmp); 675 676 if (hal->antenna_rx == RF_B) { 677 offset_ofdm = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band]; 678 offset_cck = -efuse_gain->offset[RF_PATH_B][0]; 679 } else { 680 offset_ofdm = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band]; 681 offset_cck = -efuse_gain->offset[RF_PATH_A][0]; 682 } 683 684 tmp = (offset_ofdm << 4) + efuse_gain->offset_base[RTW89_PHY_0]; 685 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 686 rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx); 687 688 tmp = (offset_ofdm << 4) + efuse_gain->rssi_base[RTW89_PHY_0]; 689 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 690 rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx); 691 692 if (subband == RTW89_CH_2G) { 693 tmp = (offset_cck << 3) + (efuse_gain->offset_base[RTW89_PHY_0] >> 1); 694 tmp = clamp_t(s32, tmp, S8_MIN >> 1, S8_MAX >> 1); 695 rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST, 696 B_RX_RPL_OFST_CCK_MASK, tmp); 697 } 698 699 ext_loss_a = (offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2); 700 ext_loss_b = (offset_b << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2); 701 702ext_loss: 703 if (rtwdev->chip->chip_id == RTL8852BT) 704 rtw8852bt_ext_loss_avg_update(rtwdev, ext_loss_a, ext_loss_b); 705} 706 707static 708void rtw8852bx_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband) 709{ 710 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 711 u8 band = rtw89_subband_to_bb_gain_band(subband); 712 u32 val; 713 714 val = u32_encode_bits((gain->rpl_ofst_20[band][RF_PATH_A] + 715 gain->rpl_ofst_20[band][RF_PATH_B]) >> 1, B_P0_RPL1_20_MASK) | 716 u32_encode_bits((gain->rpl_ofst_40[band][RF_PATH_A][0] + 717 gain->rpl_ofst_40[band][RF_PATH_B][0]) >> 1, B_P0_RPL1_40_MASK) | 718 u32_encode_bits((gain->rpl_ofst_40[band][RF_PATH_A][1] + 719 gain->rpl_ofst_40[band][RF_PATH_B][1]) >> 1, B_P0_RPL1_41_MASK); 720 val >>= B_P0_RPL1_SHIFT; 721 rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val); 722 rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val); 723 724 val = u32_encode_bits((gain->rpl_ofst_40[band][RF_PATH_A][2] + 725 gain->rpl_ofst_40[band][RF_PATH_B][2]) >> 1, B_P0_RTL2_42_MASK) | 726 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][0] + 727 gain->rpl_ofst_80[band][RF_PATH_B][0]) >> 1, B_P0_RTL2_80_MASK) | 728 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][1] + 729 gain->rpl_ofst_80[band][RF_PATH_B][1]) >> 1, B_P0_RTL2_81_MASK) | 730 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][10] + 731 gain->rpl_ofst_80[band][RF_PATH_B][10]) >> 1, B_P0_RTL2_8A_MASK); 732 rtw89_phy_write32(rtwdev, R_P0_RPL2, val); 733 rtw89_phy_write32(rtwdev, R_P1_RPL2, val); 734 735 val = u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][2] + 736 gain->rpl_ofst_80[band][RF_PATH_B][2]) >> 1, B_P0_RTL3_82_MASK) | 737 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][3] + 738 gain->rpl_ofst_80[band][RF_PATH_B][3]) >> 1, B_P0_RTL3_83_MASK) | 739 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][4] + 740 gain->rpl_ofst_80[band][RF_PATH_B][4]) >> 1, B_P0_RTL3_84_MASK) | 741 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][9] + 742 gain->rpl_ofst_80[band][RF_PATH_B][9]) >> 1, B_P0_RTL3_89_MASK); 743 rtw89_phy_write32(rtwdev, R_P0_RPL3, val); 744 rtw89_phy_write32(rtwdev, R_P1_RPL3, val); 745} 746 747static void rtw8852bx_ctrl_ch(struct rtw89_dev *rtwdev, 748 const struct rtw89_chan *chan, 749 enum rtw89_phy_idx phy_idx) 750{ 751 u8 central_ch = chan->channel; 752 u8 subband = chan->subband_type; 753 u8 sco_comp; 754 bool is_2g = central_ch <= 14; 755 756 /* Path A */ 757 if (is_2g) 758 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 759 B_PATH0_BAND_SEL_MSK_V1, 1, phy_idx); 760 else 761 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 762 B_PATH0_BAND_SEL_MSK_V1, 0, phy_idx); 763 764 /* Path B */ 765 if (is_2g) 766 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 767 B_PATH1_BAND_SEL_MSK_V1, 1, phy_idx); 768 else 769 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 770 B_PATH1_BAND_SEL_MSK_V1, 0, phy_idx); 771 772 /* SCO compensate FC setting */ 773 sco_comp = rtw8852bx_sco_mapping(central_ch); 774 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx); 775 776 if (chan->band_type == RTW89_BAND_6G) 777 return; 778 779 /* CCK parameters */ 780 if (central_ch == 14) { 781 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff); 782 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de); 783 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad); 784 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e); 785 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92); 786 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); 787 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); 788 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a); 789 } else { 790 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff); 791 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354); 792 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); 793 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053); 794 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a); 795 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92); 796 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc); 797 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5); 798 } 799 800 rtw8852bx_set_gain_error(rtwdev, subband, RF_PATH_A); 801 rtw8852bx_set_gain_error(rtwdev, subband, RF_PATH_B); 802 rtw8852bx_set_gain_offset(rtwdev, subband, phy_idx); 803 rtw8852bx_set_rxsc_rpl_comp(rtwdev, subband); 804} 805 806static void rtw8852b_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 807{ 808 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC}; 809 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4}; 810 811 switch (bw) { 812 case RTW89_CHANNEL_WIDTH_5: 813 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 814 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 815 break; 816 case RTW89_CHANNEL_WIDTH_10: 817 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 818 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 819 break; 820 case RTW89_CHANNEL_WIDTH_20: 821 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 822 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 823 break; 824 case RTW89_CHANNEL_WIDTH_40: 825 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 826 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 827 break; 828 case RTW89_CHANNEL_WIDTH_80: 829 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 830 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 831 break; 832 default: 833 rtw89_warn(rtwdev, "Fail to set ADC\n"); 834 } 835} 836 837static 838void rtw8852bt_adc_cfg(struct rtw89_dev *rtwdev, u8 bw, u8 path) 839{ 840 static const u32 rck_reset_count[2] = {0xC0E8, 0xC1E8}; 841 static const u32 adc_op5_bw_sel[2] = {0xC0D8, 0xC1D8}; 842 static const u32 adc_sample_td[2] = {0xC0D4, 0xC1D4}; 843 static const u32 adc_rst_cycle[2] = {0xC0EC, 0xC1EC}; 844 static const u32 decim_filter[2] = {0xC0EC, 0xC1EC}; 845 static const u32 rck_offset[2] = {0xC0C4, 0xC1C4}; 846 static const u32 rx_adc_clk[2] = {0x12A0, 0x32A0}; 847 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4}; 848 static const u32 idac2_1[2] = {0xC0D4, 0xC1D4}; 849 static const u32 idac2[2] = {0xC0D4, 0xC1D4}; 850 static const u32 upd_clk_adc = {0x704}; 851 852 if (rtwdev->chip->chip_id != RTL8852BT) 853 return; 854 855 rtw89_phy_write32_mask(rtwdev, idac2[path], B_P0_CFCH_CTL, 0x8); 856 rtw89_phy_write32_mask(rtwdev, rck_reset_count[path], B_ADCMOD_LP, 0x9); 857 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], B_WDADC_SEL, 0x2); 858 rtw89_phy_write32_mask(rtwdev, rx_adc_clk[path], B_P0_RXCK_ADJ, 0x49); 859 rtw89_phy_write32_mask(rtwdev, decim_filter[path], B_DCIM_FR, 0x0); 860 861 switch (bw) { 862 case RTW89_CHANNEL_WIDTH_5: 863 case RTW89_CHANNEL_WIDTH_10: 864 case RTW89_CHANNEL_WIDTH_20: 865 case RTW89_CHANNEL_WIDTH_40: 866 rtw89_phy_write32_mask(rtwdev, idac2_1[path], B_P0_CFCH_EN, 0x2); 867 rtw89_phy_write32_mask(rtwdev, adc_sample_td[path], B_P0_CFCH_BW0, 0x3); 868 rtw89_phy_write32_mask(rtwdev, adc_op5_bw_sel[path], B_P0_CFCH_BW1, 0xf); 869 rtw89_phy_write32_mask(rtwdev, rck_offset[path], B_DRCK_MUL, 0x0); 870 /* Tx TSSI ADC update */ 871 rtw89_phy_write32_mask(rtwdev, upd_clk_adc, B_RSTB_ASYNC_BW80, 0); 872 873 if (rtwdev->efuse.rfe_type >= 51) 874 rtw89_phy_write32_mask(rtwdev, adc_rst_cycle[path], B_DCIM_RC, 0x2); 875 else 876 rtw89_phy_write32_mask(rtwdev, adc_rst_cycle[path], B_DCIM_RC, 0x3); 877 break; 878 case RTW89_CHANNEL_WIDTH_80: 879 rtw89_phy_write32_mask(rtwdev, idac2_1[path], B_P0_CFCH_EN, 0x2); 880 rtw89_phy_write32_mask(rtwdev, adc_sample_td[path], B_P0_CFCH_BW0, 0x2); 881 rtw89_phy_write32_mask(rtwdev, adc_op5_bw_sel[path], B_P0_CFCH_BW1, 0x8); 882 rtw89_phy_write32_mask(rtwdev, rck_offset[path], B_DRCK_MUL, 0x0); 883 rtw89_phy_write32_mask(rtwdev, adc_rst_cycle[path], B_DCIM_RC, 0x3); 884 /* Tx TSSI ADC update */ 885 rtw89_phy_write32_mask(rtwdev, upd_clk_adc, B_RSTB_ASYNC_BW80, 1); 886 break; 887 case RTW89_CHANNEL_WIDTH_160: 888 rtw89_phy_write32_mask(rtwdev, idac2_1[path], B_P0_CFCH_EN, 0x0); 889 rtw89_phy_write32_mask(rtwdev, adc_sample_td[path], B_P0_CFCH_BW0, 0x2); 890 rtw89_phy_write32_mask(rtwdev, adc_op5_bw_sel[path], B_P0_CFCH_BW1, 0x4); 891 rtw89_phy_write32_mask(rtwdev, rck_offset[path], B_DRCK_MUL, 0x6); 892 rtw89_phy_write32_mask(rtwdev, adc_rst_cycle[path], B_DCIM_RC, 0x3); 893 /* Tx TSSI ADC update */ 894 rtw89_phy_write32_mask(rtwdev, upd_clk_adc, B_RSTB_ASYNC_BW80, 2); 895 break; 896 default: 897 rtw89_warn(rtwdev, "Fail to set ADC\n"); 898 break; 899 } 900} 901 902static void rtw8852bx_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 903 enum rtw89_phy_idx phy_idx) 904{ 905 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 906 u32 rx_path_0; 907 908 rx_path_0 = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, phy_idx); 909 910 switch (bw) { 911 case RTW89_CHANNEL_WIDTH_5: 912 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); 913 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx); 914 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); 915 916 /*Set RF mode at 3 */ 917 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 918 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 919 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 920 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 921 if (chip_id == RTL8852BT) { 922 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 923 B_PATH0_BAND_NRBW_EN_V1, 0x0, phy_idx); 924 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 925 B_PATH1_BAND_NRBW_EN_V1, 0x0, phy_idx); 926 } 927 break; 928 case RTW89_CHANNEL_WIDTH_10: 929 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); 930 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx); 931 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); 932 933 /*Set RF mode at 3 */ 934 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 935 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 936 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 937 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 938 if (chip_id == RTL8852BT) { 939 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 940 B_PATH0_BAND_NRBW_EN_V1, 0x0, phy_idx); 941 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 942 B_PATH1_BAND_NRBW_EN_V1, 0x0, phy_idx); 943 } 944 break; 945 case RTW89_CHANNEL_WIDTH_20: 946 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); 947 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); 948 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); 949 950 /*Set RF mode at 3 */ 951 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 952 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 953 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 954 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 955 if (chip_id == RTL8852BT) { 956 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 957 B_PATH0_BAND_NRBW_EN_V1, 0x1, phy_idx); 958 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 959 B_PATH1_BAND_NRBW_EN_V1, 0x1, phy_idx); 960 } 961 break; 962 case RTW89_CHANNEL_WIDTH_40: 963 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx); 964 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); 965 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 966 pri_ch, phy_idx); 967 968 /*Set RF mode at 3 */ 969 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 970 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 971 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 972 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 973 /*CCK primary channel */ 974 if (pri_ch == RTW89_SC_20_UPPER) 975 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); 976 else 977 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); 978 979 break; 980 case RTW89_CHANNEL_WIDTH_80: 981 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx); 982 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); 983 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 984 pri_ch, phy_idx); 985 986 /*Set RF mode at 3 */ 987 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 988 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 989 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 990 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 991 break; 992 default: 993 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 994 pri_ch); 995 } 996 997 if (chip_id == RTL8852B) { 998 rtw8852b_bw_setting(rtwdev, bw, RF_PATH_A); 999 rtw8852b_bw_setting(rtwdev, bw, RF_PATH_B); 1000 } else if (chip_id == RTL8852BT) { 1001 rtw8852bt_adc_cfg(rtwdev, bw, RF_PATH_A); 1002 rtw8852bt_adc_cfg(rtwdev, bw, RF_PATH_B); 1003 } 1004 1005 if (rx_path_0 == 0x1) 1006 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 1007 B_P1_RFMODE_ORI_RX_ALL, 0x111, phy_idx); 1008 else if (rx_path_0 == 0x2) 1009 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 1010 B_P0_RFMODE_ORI_RX_ALL, 0x111, phy_idx); 1011} 1012 1013static void rtw8852bx_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en) 1014{ 1015 if (cck_en) { 1016 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1); 1017 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); 1018 } else { 1019 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0); 1020 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); 1021 } 1022} 1023 1024static void rtw8852bx_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 1025 enum rtw89_phy_idx phy_idx) 1026{ 1027 u8 pri_ch = chan->pri_ch_idx; 1028 bool mask_5m_low; 1029 bool mask_5m_en; 1030 1031 switch (chan->band_width) { 1032 case RTW89_CHANNEL_WIDTH_40: 1033 /* Prich=1: Mask 5M High, Prich=2: Mask 5M Low */ 1034 mask_5m_en = true; 1035 mask_5m_low = pri_ch == RTW89_SC_20_LOWER; 1036 break; 1037 case RTW89_CHANNEL_WIDTH_80: 1038 /* Prich=3: Mask 5M High, Prich=4: Mask 5M Low, Else: Disable */ 1039 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST || 1040 pri_ch == RTW89_SC_20_LOWEST; 1041 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST; 1042 break; 1043 default: 1044 mask_5m_en = false; 1045 break; 1046 } 1047 1048 if (!mask_5m_en) { 1049 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0); 1050 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x0); 1051 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1, 1052 B_ASSIGN_SBD_OPT_EN_V1, 0x0, phy_idx); 1053 return; 1054 } 1055 1056 if (mask_5m_low) { 1057 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x4); 1058 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1); 1059 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0); 1060 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1); 1061 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, 0x4); 1062 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x1); 1063 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, 0x0); 1064 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, 0x1); 1065 } else { 1066 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x4); 1067 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1); 1068 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1); 1069 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0); 1070 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, 0x4); 1071 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x1); 1072 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, 0x1); 1073 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, 0x0); 1074 } 1075 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1, 1076 B_ASSIGN_SBD_OPT_EN_V1, 0x1, phy_idx); 1077} 1078 1079static void __rtw8852bx_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1080{ 1081 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1082 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1083 fsleep(1); 1084 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); 1085 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx); 1086 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1087 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1088 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); 1089} 1090 1091static void rtw8852bx_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1092 enum rtw89_phy_idx phy_idx) 1093{ 1094 u32 addr; 1095 1096 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1097 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1098 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1099} 1100 1101static void __rtw8852bx_bb_sethw(struct rtw89_dev *rtwdev) 1102{ 1103 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 1104 1105 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); 1106 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP); 1107 1108 rtw8852bx_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1109 1110 /* read these registers after loading BB parameters */ 1111 gain->offset_base[RTW89_PHY_0] = 1112 rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK); 1113 gain->rssi_base[RTW89_PHY_0] = 1114 rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK); 1115} 1116 1117static void rtw8852bx_bb_set_pop(struct rtw89_dev *rtwdev) 1118{ 1119 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) 1120 rtw89_phy_write32_clr(rtwdev, R_PKT_CTRL, B_PKT_POP_EN); 1121} 1122 1123static u32 rtw8852bt_spur_freq(struct rtw89_dev *rtwdev, 1124 const struct rtw89_chan *chan) 1125{ 1126 u8 center_chan = chan->channel; 1127 1128 switch (chan->band_type) { 1129 case RTW89_BAND_5G: 1130 if (center_chan == 151 || center_chan == 153 || 1131 center_chan == 155 || center_chan == 163) 1132 return 5760; 1133 break; 1134 default: 1135 break; 1136 } 1137 1138 return 0; 1139} 1140 1141#define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */ 1142#define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */ 1143#define MAX_TONE_NUM 2048 1144 1145static void rtw8852bt_set_csi_tone_idx(struct rtw89_dev *rtwdev, 1146 const struct rtw89_chan *chan, 1147 enum rtw89_phy_idx phy_idx) 1148{ 1149 s32 freq_diff, csi_idx, csi_tone_idx; 1150 u32 spur_freq; 1151 1152 spur_freq = rtw8852bt_spur_freq(rtwdev, chan); 1153 if (spur_freq == 0) { 1154 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN, 1155 0, phy_idx); 1156 return; 1157 } 1158 1159 freq_diff = (spur_freq - chan->freq) * 1000000; 1160 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125); 1161 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx); 1162 1163 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_V1, B_SEG0CSI_IDX, 1164 csi_tone_idx, phy_idx); 1165 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN, 1, phy_idx); 1166} 1167 1168static 1169void __rtw8852bx_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 1170 enum rtw89_phy_idx phy_idx) 1171{ 1172 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1173 bool cck_en = chan->channel <= 14; 1174 u8 pri_ch_idx = chan->pri_ch_idx; 1175 u8 band = chan->band_type, chan_idx; 1176 1177 if (cck_en) 1178 rtw8852bx_ctrl_sco_cck(rtwdev, chan->primary_channel); 1179 1180 rtw8852bx_ctrl_ch(rtwdev, chan, phy_idx); 1181 rtw8852bx_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1182 rtw8852bx_ctrl_cck_en(rtwdev, cck_en); 1183 if (chip_id == RTL8852BT) 1184 rtw8852bt_set_csi_tone_idx(rtwdev, chan, phy_idx); 1185 if (chip_id == RTL8852B && chan->band_type == RTW89_BAND_5G) { 1186 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 1187 B_PATH0_BT_SHARE_V1, 0x0); 1188 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 1189 B_PATH0_BTG_PATH_V1, 0x0); 1190 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 1191 B_PATH1_BT_SHARE_V1, 0x0); 1192 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 1193 B_PATH1_BTG_PATH_V1, 0x0); 1194 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0); 1195 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0); 1196 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, 1197 B_BT_DYN_DC_EST_EN_MSK, 0x0); 1198 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0); 1199 } 1200 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band); 1201 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx); 1202 rtw8852bx_5m_mask(rtwdev, chan, phy_idx); 1203 rtw8852bx_bb_set_pop(rtwdev); 1204 __rtw8852bx_bb_reset_all(rtwdev, phy_idx); 1205} 1206 1207static u32 rtw8852bx_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1208 enum rtw89_phy_idx phy_idx, 1209 s16 ref, u16 pwr_ofst_decrease) 1210{ 1211 const u16 tssi_16dbm_cw = 0x12c; 1212 const u8 base_cw_0db = 0x27; 1213 s16 pwr_s10_3; 1214 s16 rf_pwr_cw; 1215 u16 bb_pwr_cw; 1216 u32 pwr_cw; 1217 u32 tssi_ofst_cw; 1218 1219 pwr_s10_3 = (ref << 1) + (s16)(base_cw_0db << 3) - pwr_ofst_decrease; 1220 bb_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(2, 0)); 1221 rf_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(8, 3)); 1222 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1223 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1224 1225 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)) - 1226 pwr_ofst_decrease; 1227 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1228 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1229 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1230 1231 return u32_encode_bits(tssi_ofst_cw, B_DPD_TSSI_CW) | 1232 u32_encode_bits(pwr_cw, B_DPD_PWR_CW) | 1233 u32_encode_bits(ref, B_DPD_REF); 1234} 1235 1236/* @pwr_ofst (unit: 1/8 dBm): power of path A minus power of path B */ 1237static void rtw8852bx_set_txpwr_ref(struct rtw89_dev *rtwdev, 1238 enum rtw89_phy_idx phy_idx, s16 pwr_ofst) 1239{ 1240 static const u32 addr[RF_PATH_NUM_8852BX] = {0x5800, 0x7800}; 1241 const u32 mask = B_DPD_TSSI_CW | B_DPD_PWR_CW | B_DPD_REF; 1242 u16 ofst_dec[RF_PATH_NUM_8852BX]; 1243 const u8 ofst_ofdm = 0x4; 1244 const u8 ofst_cck = 0x8; 1245 const s16 ref_ofdm = 0; 1246 const s16 ref_cck = 0; 1247 u32 val; 1248 u8 i; 1249 1250 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1251 1252 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1253 B_AX_PWR_REF, 0x0); 1254 1255 ofst_dec[RF_PATH_A] = pwr_ofst > 0 ? 0 : abs(pwr_ofst); 1256 ofst_dec[RF_PATH_B] = pwr_ofst > 0 ? pwr_ofst : 0; 1257 1258 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1259 for (i = 0; i < RF_PATH_NUM_8852BX; i++) { 1260 val = rtw8852bx_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm, ofst_dec[i]); 1261 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, phy_idx); 1262 } 1263 1264 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1265 for (i = 0; i < RF_PATH_NUM_8852BX; i++) { 1266 val = rtw8852bx_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck, ofst_dec[i]); 1267 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, phy_idx); 1268 } 1269} 1270 1271static void rtw8852bx_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev, 1272 const struct rtw89_chan *chan, 1273 u8 tx_shape_idx, 1274 enum rtw89_phy_idx phy_idx) 1275{ 1276#define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2)) 1277#define __DFIR_CFG_MASK 0xffffffff 1278#define __DFIR_CFG_NR 8 1279#define __DECL_DFIR_PARAM(_name, _val...) \ 1280 static const u32 param_ ## _name[] = {_val}; \ 1281 static_assert(ARRAY_SIZE(param_ ## _name) == __DFIR_CFG_NR) 1282 1283 __DECL_DFIR_PARAM(flat, 1284 0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053, 1285 0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5); 1286 __DECL_DFIR_PARAM(sharp, 1287 0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090, 1288 0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5); 1289 __DECL_DFIR_PARAM(sharp_14, 1290 0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E, 1291 0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A); 1292 u8 ch = chan->channel; 1293 const u32 *param; 1294 u32 addr; 1295 int i; 1296 1297 if (ch > 14) { 1298 rtw89_warn(rtwdev, 1299 "set tx shape dfir by unknown ch: %d on 2G\n", ch); 1300 return; 1301 } 1302 1303 if (ch == 14) 1304 param = param_sharp_14; 1305 else 1306 param = tx_shape_idx == 0 ? param_flat : param_sharp; 1307 1308 for (i = 0; i < __DFIR_CFG_NR; i++) { 1309 addr = __DFIR_CFG_ADDR(i); 1310 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1311 "set tx shape dfir: 0x%x: 0x%x\n", addr, param[i]); 1312 rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i], 1313 phy_idx); 1314 } 1315 1316#undef __DECL_DFIR_PARAM 1317#undef __DFIR_CFG_NR 1318#undef __DFIR_CFG_MASK 1319#undef __DECL_CFG_ADDR 1320} 1321 1322static void rtw8852bx_set_tx_shape(struct rtw89_dev *rtwdev, 1323 const struct rtw89_chan *chan, 1324 enum rtw89_phy_idx phy_idx) 1325{ 1326 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 1327 u8 band = chan->band_type; 1328 u8 regd = rtw89_regd_get(rtwdev, band); 1329 u8 tx_shape_cck = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_CCK][regd]; 1330 u8 tx_shape_ofdm = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_OFDM][regd]; 1331 1332 if (band == RTW89_BAND_2G) 1333 rtw8852bx_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx); 1334 1335 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG, 1336 tx_shape_ofdm); 1337} 1338 1339static s16 rtw8852bx_get_txpwr_sar_diff(struct rtw89_dev *rtwdev, 1340 const struct rtw89_chan *chan) 1341{ 1342 struct rtw89_sar_parm sar_parm = { 1343 .center_freq = chan->freq, 1344 .force_path = true, 1345 }; 1346 s16 sar_bb_a, sar_bb_b; 1347 s8 sar_mac; 1348 1349 sar_parm.path = RF_PATH_A; 1350 sar_mac = rtw89_query_sar(rtwdev, &sar_parm); 1351 sar_bb_a = rtw89_phy_txpwr_mac_to_bb(rtwdev, sar_mac); 1352 1353 sar_parm.path = RF_PATH_B; 1354 sar_mac = rtw89_query_sar(rtwdev, &sar_parm); 1355 sar_bb_b = rtw89_phy_txpwr_mac_to_bb(rtwdev, sar_mac); 1356 1357 return sar_bb_a - sar_bb_b; 1358} 1359 1360static void rtw8852bx_set_txpwr_diff(struct rtw89_dev *rtwdev, 1361 const struct rtw89_chan *chan, 1362 enum rtw89_phy_idx phy_idx) 1363{ 1364 s16 pwr_ofst; 1365 1366 pwr_ofst = rtw89_phy_ant_gain_pwr_offset(rtwdev, chan); 1367 pwr_ofst += rtw8852bx_get_txpwr_sar_diff(rtwdev, chan); 1368 rtw8852bx_set_txpwr_ref(rtwdev, phy_idx, pwr_ofst); 1369} 1370 1371static void __rtw8852bx_set_txpwr(struct rtw89_dev *rtwdev, 1372 const struct rtw89_chan *chan, 1373 enum rtw89_phy_idx phy_idx) 1374{ 1375 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 1376 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 1377 rtw8852bx_set_tx_shape(rtwdev, chan, phy_idx); 1378 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 1379 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 1380 rtw8852bx_set_txpwr_diff(rtwdev, chan, phy_idx); 1381} 1382 1383static void __rtw8852bx_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 1384 enum rtw89_phy_idx phy_idx) 1385{ 1386 rtw8852bx_set_txpwr_ref(rtwdev, phy_idx, 0); 1387} 1388 1389static 1390void __rtw8852bx_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1391 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1392{ 1393 u32 reg; 1394 1395 if (pw_ofst < -16 || pw_ofst > 15) { 1396 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst); 1397 return; 1398 } 1399 1400 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx); 1401 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); 1402 1403 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); 1404 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst); 1405 1406 pw_ofst = max_t(s8, pw_ofst - 3, -16); 1407 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); 1408 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst); 1409} 1410 1411static int 1412__rtw8852bx_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1413{ 1414 int ret; 1415 1416 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 1417 if (ret) 1418 return ret; 1419 1420 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000); 1421 if (ret) 1422 return ret; 1423 1424 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 1425 if (ret) 1426 return ret; 1427 1428 rtw8852bx_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ? 1429 RTW89_MAC_1 : RTW89_MAC_0); 1430 1431 return 0; 1432} 1433 1434static 1435void __rtw8852bx_bb_set_plcp_tx(struct rtw89_dev *rtwdev) 1436{ 1437 const struct rtw89_reg3_def *def = rtw8852bx_pmac_ht20_mcs7_tbl; 1438 u8 i; 1439 1440 for (i = 0; i < ARRAY_SIZE(rtw8852bx_pmac_ht20_mcs7_tbl); i++, def++) 1441 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 1442} 1443 1444static void rtw8852bx_stop_pmac_tx(struct rtw89_dev *rtwdev, 1445 struct rtw8852bx_bb_pmac_info *tx_info, 1446 enum rtw89_phy_idx idx) 1447{ 1448 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx"); 1449 if (tx_info->mode == CONT_TX) 1450 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, idx); 1451 else if (tx_info->mode == PKTS_TX) 1452 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, idx); 1453} 1454 1455static void rtw8852bx_start_pmac_tx(struct rtw89_dev *rtwdev, 1456 struct rtw8852bx_bb_pmac_info *tx_info, 1457 enum rtw89_phy_idx idx) 1458{ 1459 enum rtw8852bx_pmac_mode mode = tx_info->mode; 1460 u32 pkt_cnt = tx_info->tx_cnt; 1461 u16 period = tx_info->period; 1462 1463 if (mode == CONT_TX && !tx_info->is_cck) { 1464 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, idx); 1465 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start"); 1466 } else if (mode == PKTS_TX) { 1467 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, idx); 1468 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, 1469 B_PMAC_TX_PRD_MSK, period, idx); 1470 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK, 1471 pkt_cnt, idx); 1472 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start"); 1473 } 1474 1475 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx); 1476 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx); 1477} 1478 1479static 1480void rtw8852bx_bb_set_pmac_tx(struct rtw89_dev *rtwdev, 1481 struct rtw8852bx_bb_pmac_info *tx_info, 1482 enum rtw89_phy_idx idx, const struct rtw89_chan *chan) 1483{ 1484 if (!tx_info->en_pmac_tx) { 1485 rtw8852bx_stop_pmac_tx(rtwdev, tx_info, idx); 1486 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx); 1487 if (chan->band_type == RTW89_BAND_2G) 1488 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS); 1489 return; 1490 } 1491 1492 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable"); 1493 1494 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx); 1495 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx); 1496 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, idx); 1497 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx); 1498 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx); 1499 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); 1500 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx); 1501 1502 rtw8852bx_start_pmac_tx(rtwdev, tx_info, idx); 1503} 1504 1505static 1506void __rtw8852bx_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, 1507 u16 tx_cnt, u16 period, u16 tx_time, 1508 enum rtw89_phy_idx idx, const struct rtw89_chan *chan) 1509{ 1510 struct rtw8852bx_bb_pmac_info tx_info = {0}; 1511 1512 tx_info.en_pmac_tx = enable; 1513 tx_info.is_cck = 0; 1514 tx_info.mode = PKTS_TX; 1515 tx_info.tx_cnt = tx_cnt; 1516 tx_info.period = period; 1517 tx_info.tx_time = tx_time; 1518 1519 rtw8852bx_bb_set_pmac_tx(rtwdev, &tx_info, idx, chan); 1520} 1521 1522static 1523void __rtw8852bx_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, 1524 enum rtw89_phy_idx idx) 1525{ 1526 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm); 1527 1528 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); 1529 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx); 1530} 1531 1532static 1533void __rtw8852bx_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) 1534{ 1535 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0); 1536 1537 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path); 1538 1539 if (tx_path == RF_PATH_A) { 1540 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1); 1541 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0); 1542 } else if (tx_path == RF_PATH_B) { 1543 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2); 1544 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0); 1545 } else if (tx_path == RF_PATH_AB) { 1546 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 3); 1547 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4); 1548 } else { 1549 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path"); 1550 } 1551} 1552 1553static 1554void __rtw8852bx_bb_tx_mode_switch(struct rtw89_dev *rtwdev, 1555 enum rtw89_phy_idx idx, u8 mode) 1556{ 1557 if (mode != 0) 1558 return; 1559 1560 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch"); 1561 1562 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx); 1563 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx); 1564 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx); 1565 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx); 1566 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx); 1567 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx); 1568 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx); 1569} 1570 1571static 1572void __rtw8852bx_bb_backup_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, 1573 struct rtw8852bx_bb_tssi_bak *bak) 1574{ 1575 s32 tmp; 1576 1577 bak->tx_path = rtw89_phy_read32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, idx); 1578 bak->rx_path = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, idx); 1579 bak->p0_rfmode = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, idx); 1580 bak->p0_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, idx); 1581 bak->p1_rfmode = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, idx); 1582 bak->p1_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, idx); 1583 tmp = rtw89_phy_read32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, idx); 1584 bak->tx_pwr = sign_extend32(tmp, 8); 1585} 1586 1587static 1588void __rtw8852bx_bb_restore_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, 1589 const struct rtw8852bx_bb_tssi_bak *bak) 1590{ 1591 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, bak->tx_path, idx); 1592 if (bak->tx_path == RF_AB) 1593 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0x4); 1594 else 1595 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0x0); 1596 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, bak->rx_path, idx); 1597 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); 1598 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, bak->p0_rfmode, idx); 1599 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, bak->p0_rfmode_ftm, idx); 1600 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, bak->p1_rfmode, idx); 1601 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, bak->p1_rfmode_ftm, idx); 1602 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, bak->tx_pwr, idx); 1603} 1604 1605static void __rtw8852bx_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 1606 enum rtw89_phy_idx phy_idx) 1607{ 1608 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8852bx_btc_preagc_en_defs_tbl : 1609 &rtw8852bx_btc_preagc_dis_defs_tbl); 1610} 1611 1612static void __rtw8852bx_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 1613 enum rtw89_phy_idx phy_idx) 1614{ 1615 if (en) { 1616 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 1617 B_PATH0_BT_SHARE_V1, 0x1); 1618 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 1619 B_PATH0_BTG_PATH_V1, 0x0); 1620 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 1621 B_PATH1_G_LNA6_OP1DB_V1, 0x20); 1622 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 1623 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30); 1624 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 1625 B_PATH1_BT_SHARE_V1, 0x1); 1626 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 1627 B_PATH1_BTG_PATH_V1, 0x1); 1628 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 1629 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1); 1630 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x2); 1631 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, 1632 B_BT_DYN_DC_EST_EN_MSK, 0x1); 1633 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1); 1634 } else { 1635 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 1636 B_PATH0_BT_SHARE_V1, 0x0); 1637 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 1638 B_PATH0_BTG_PATH_V1, 0x0); 1639 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 1640 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 1641 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 1642 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 1643 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 1644 B_PATH1_BT_SHARE_V1, 0x0); 1645 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 1646 B_PATH1_BTG_PATH_V1, 0x0); 1647 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc); 1648 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0); 1649 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0); 1650 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, 1651 B_BT_DYN_DC_EST_EN_MSK, 0x1); 1652 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0); 1653 } 1654} 1655 1656static 1657void __rtw8852bx_bb_ctrl_rx_path(struct rtw89_dev *rtwdev, 1658 enum rtw89_rf_path_bit rx_path, 1659 const struct rtw89_chan *chan) 1660{ 1661 u32 rst_mask0; 1662 u32 rst_mask1; 1663 1664 if (rx_path == RF_A) { 1665 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1); 1666 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1); 1667 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1); 1668 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 1669 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 1670 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4); 1671 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 1672 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 1673 } else if (rx_path == RF_B) { 1674 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 2); 1675 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 2); 1676 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 2); 1677 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 1678 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 1679 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4); 1680 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 1681 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 1682 } else if (rx_path == RF_AB) { 1683 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 3); 1684 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 3); 1685 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 3); 1686 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); 1687 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); 1688 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4); 1689 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); 1690 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); 1691 } 1692 1693 rtw8852bx_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0); 1694 1695 if (chan->band_type == RTW89_BAND_2G && 1696 (rx_path == RF_B || rx_path == RF_AB)) 1697 rtw8852bx_ctrl_btg_bt_rx(rtwdev, true, RTW89_PHY_0); 1698 else 1699 rtw8852bx_ctrl_btg_bt_rx(rtwdev, false, RTW89_PHY_0); 1700 1701 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 1702 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 1703 if (rx_path == RF_A) { 1704 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 1705 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 1706 } else { 1707 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 1708 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 1709 } 1710} 1711 1712static void rtw8852bx_bb_ctrl_rf_mode_rx_path(struct rtw89_dev *rtwdev, 1713 enum rtw89_rf_path_bit rx_path) 1714{ 1715 if (rx_path == RF_A) { 1716 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, 1717 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1233312); 1718 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX, 1719 B_P0_RFMODE_FTM_RX, 0x333); 1720 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, 1721 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1111111); 1722 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX, 1723 B_P1_RFMODE_FTM_RX, 0x111); 1724 } else if (rx_path == RF_B) { 1725 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, 1726 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1111111); 1727 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX, 1728 B_P0_RFMODE_FTM_RX, 0x111); 1729 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, 1730 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1233312); 1731 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX, 1732 B_P1_RFMODE_FTM_RX, 0x333); 1733 } else if (rx_path == RF_AB) { 1734 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, 1735 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1233312); 1736 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX, 1737 B_P0_RFMODE_FTM_RX, 0x333); 1738 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, 1739 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1233312); 1740 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX, 1741 B_P1_RFMODE_FTM_RX, 0x333); 1742 } 1743} 1744 1745static void __rtw8852bx_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) 1746{ 1747 struct rtw89_hal *hal = &rtwdev->hal; 1748 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 1749 enum rtw89_rf_path_bit rx_path = hal->antenna_rx ? hal->antenna_rx : RF_AB; 1750 u8 rx_nss = rtwdev->hal.rx_nss; 1751 1752 if (rx_path != RF_AB) 1753 rx_nss = 1; 1754 1755 rtw8852bx_bb_ctrl_rx_path(rtwdev, rx_path, chan); 1756 rtw8852bx_bb_ctrl_rf_mode_rx_path(rtwdev, rx_path); 1757 1758 if (rx_nss == 1) { 1759 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 1760 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 1761 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 1762 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 1763 } else { 1764 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); 1765 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); 1766 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); 1767 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); 1768 } 1769 1770 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); 1771} 1772 1773static u8 __rtw8852bx_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 1774{ 1775 if (rtwdev->is_tssi_mode[rf_path]) { 1776 u32 addr = 0x1c10 + (rf_path << 13); 1777 1778 return rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000); 1779 } 1780 1781 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1782 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 1783 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1784 1785 fsleep(200); 1786 1787 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 1788} 1789 1790static 1791void rtw8852bx_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 1792{ 1793 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000); 1794 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group); 1795 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val); 1796 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); 1797} 1798 1799static void __rtw8852bx_btc_init_cfg(struct rtw89_dev *rtwdev) 1800{ 1801 struct rtw89_btc *btc = &rtwdev->btc; 1802 const struct rtw89_chip_info *chip = rtwdev->chip; 1803 const struct rtw89_mac_ax_coex coex_params = { 1804 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 1805 .direction = RTW89_MAC_AX_COEX_INNER, 1806 }; 1807 1808 /* PTA init */ 1809 rtw89_mac_coex_init(rtwdev, &coex_params); 1810 1811 /* set WL Tx response = Hi-Pri */ 1812 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 1813 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 1814 1815 /* set rf gnt debug off */ 1816 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0); 1817 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0); 1818 1819 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 1820 if (btc->ant_type == BTC_ANT_SHARED) { 1821 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 1822 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 1823 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 1824 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 1825 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x55f); 1826 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 1827 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 1828 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 1829 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 1830 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x5ff); 1831 } 1832 1833 if (rtwdev->chip->chip_id == RTL8852BT) { 1834 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_RX_GROUP, 0x5df); 1835 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_RX_GROUP, 0x5df); 1836 } 1837 1838 /* set PTA break table */ 1839 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); 1840 1841 /* enable BT counter 0xda40[16,2] = 2b'11 */ 1842 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); 1843 btc->cx.wl.status.map.init_ok = true; 1844} 1845 1846static 1847void __rtw8852bx_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 1848{ 1849 u32 bitmap; 1850 u32 reg; 1851 1852 switch (map) { 1853 case BTC_PRI_MASK_TX_RESP: 1854 reg = R_BTC_BT_COEX_MSK_TABLE; 1855 bitmap = B_BTC_PRI_MASK_TX_RESP_V1; 1856 break; 1857 case BTC_PRI_MASK_BEACON: 1858 reg = R_AX_WL_PRI_MSK; 1859 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; 1860 break; 1861 case BTC_PRI_MASK_RX_CCK: 1862 reg = R_BTC_BT_COEX_MSK_TABLE; 1863 bitmap = B_BTC_PRI_MASK_RXCCK_V1; 1864 break; 1865 default: 1866 return; 1867 } 1868 1869 if (state) 1870 rtw89_write32_set(rtwdev, reg, bitmap); 1871 else 1872 rtw89_write32_clr(rtwdev, reg, bitmap); 1873} 1874 1875static 1876s8 __rtw8852bx_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 1877{ 1878 /* +6 for compensate offset */ 1879 return clamp_t(s8, val + 6, -100, 0) + 100; 1880} 1881 1882static 1883void __rtw8852bx_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 1884{ 1885 /* Feature move to firmware */ 1886} 1887 1888static void __rtw8852bx_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 1889{ 1890 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 1891 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 1892 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x31); 1893 1894 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 1895 if (state) 1896 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x179); 1897 else 1898 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x20); 1899 1900 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 1901} 1902 1903static void rtw8852bx_btc_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 1904{ 1905 switch (level) { 1906 case 0: /* default */ 1907 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 1908 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 1909 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 1910 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 1911 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 1912 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 1913 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 1914 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 1915 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 1916 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 1917 break; 1918 case 1: /* Fix LNA2=5 */ 1919 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 1920 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 1921 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 1922 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 1923 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 1924 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 1925 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 1926 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 1927 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 1928 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 1929 break; 1930 } 1931} 1932 1933static void __rtw8852bx_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 1934{ 1935 struct rtw89_btc *btc = &rtwdev->btc; 1936 1937 switch (level) { 1938 case 0: /* original */ 1939 default: 1940 rtw8852bx_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 1941 btc->dm.wl_lna2 = 0; 1942 break; 1943 case 1: /* for FDD free-run */ 1944 rtw8852bx_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0); 1945 btc->dm.wl_lna2 = 0; 1946 break; 1947 case 2: /* for BTG Co-Rx*/ 1948 rtw8852bx_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 1949 btc->dm.wl_lna2 = 1; 1950 break; 1951 } 1952 1953 rtw8852bx_btc_set_wl_lna2(rtwdev, btc->dm.wl_lna2); 1954} 1955 1956static void rtw8852bx_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 1957 struct rtw89_rx_phy_ppdu *phy_ppdu, 1958 struct ieee80211_rx_status *status) 1959{ 1960 u16 chan = phy_ppdu->chan_idx; 1961 enum nl80211_band band; 1962 u8 ch; 1963 1964 if (chan == 0) 1965 return; 1966 1967 rtw89_decode_chan_idx(rtwdev, chan, &ch, &band); 1968 status->freq = ieee80211_channel_to_frequency(ch, band); 1969 status->band = band; 1970} 1971 1972static void __rtw8852bx_query_ppdu(struct rtw89_dev *rtwdev, 1973 struct rtw89_rx_phy_ppdu *phy_ppdu, 1974 struct ieee80211_rx_status *status) 1975{ 1976 u8 path; 1977 u8 *rx_power = phy_ppdu->rssi; 1978 1979 if (!status->signal) 1980 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], 1981 rx_power[RF_PATH_B])); 1982 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 1983 status->chains |= BIT(path); 1984 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 1985 } 1986 if (phy_ppdu->valid) 1987 rtw8852bx_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 1988} 1989 1990static void __rtw8852bx_convert_rpl_to_rssi(struct rtw89_dev *rtwdev, 1991 struct rtw89_rx_phy_ppdu *phy_ppdu) 1992{ 1993 u8 delta = phy_ppdu->rpl_avg - phy_ppdu->rssi_avg; 1994 u8 *rssi = phy_ppdu->rssi; 1995 u8 i; 1996 1997 for (i = 0; i < RF_PATH_NUM_8852BX; i++) 1998 rssi[i] += delta; 1999 2000 phy_ppdu->rssi_avg = phy_ppdu->rpl_avg; 2001} 2002 2003static int __rtw8852bx_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 2004{ 2005 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2006 u32 val32; 2007 int ret; 2008 2009 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 2010 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2011 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x1); 2012 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2013 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2014 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2015 2016 if (chip_id == RTL8852BT) { 2017 val32 = rtw89_read32(rtwdev, R_AX_AFE_OFF_CTRL1); 2018 val32 = u32_replace_bits(val32, 0x1, B_AX_S0_LDO_VSEL_F_MASK); 2019 val32 = u32_replace_bits(val32, 0x1, B_AX_S1_LDO_VSEL_F_MASK); 2020 rtw89_write32(rtwdev, R_AX_AFE_OFF_CTRL1, val32); 2021 } 2022 2023 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7, 2024 FULL_BIT_MASK); 2025 if (ret) 2026 return ret; 2027 2028 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7, 2029 FULL_BIT_MASK); 2030 if (ret) 2031 return ret; 2032 2033 rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE); 2034 2035 return 0; 2036} 2037 2038static int __rtw8852bx_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 2039{ 2040 u8 wl_rfc_s0; 2041 u8 wl_rfc_s1; 2042 int ret; 2043 2044 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2045 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 2046 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2047 2048 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0); 2049 if (ret) 2050 return ret; 2051 wl_rfc_s0 &= ~XTAL_SI_RF00S_EN; 2052 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0, 2053 FULL_BIT_MASK); 2054 if (ret) 2055 return ret; 2056 2057 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1); 2058 if (ret) 2059 return ret; 2060 wl_rfc_s1 &= ~XTAL_SI_RF10S_EN; 2061 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1, 2062 FULL_BIT_MASK); 2063 return ret; 2064} 2065 2066const struct rtw8852bx_info rtw8852bx_info = { 2067 .mac_enable_bb_rf = __rtw8852bx_mac_enable_bb_rf, 2068 .mac_disable_bb_rf = __rtw8852bx_mac_disable_bb_rf, 2069 .bb_sethw = __rtw8852bx_bb_sethw, 2070 .bb_reset_all = __rtw8852bx_bb_reset_all, 2071 .bb_cfg_txrx_path = __rtw8852bx_bb_cfg_txrx_path, 2072 .bb_cfg_tx_path = __rtw8852bx_bb_cfg_tx_path, 2073 .bb_ctrl_rx_path = __rtw8852bx_bb_ctrl_rx_path, 2074 .bb_set_plcp_tx = __rtw8852bx_bb_set_plcp_tx, 2075 .bb_set_power = __rtw8852bx_bb_set_power, 2076 .bb_set_pmac_pkt_tx = __rtw8852bx_bb_set_pmac_pkt_tx, 2077 .bb_backup_tssi = __rtw8852bx_bb_backup_tssi, 2078 .bb_restore_tssi = __rtw8852bx_bb_restore_tssi, 2079 .bb_tx_mode_switch = __rtw8852bx_bb_tx_mode_switch, 2080 .set_channel_mac = __rtw8852bx_set_channel_mac, 2081 .set_channel_bb = __rtw8852bx_set_channel_bb, 2082 .ctrl_nbtg_bt_tx = __rtw8852bx_ctrl_nbtg_bt_tx, 2083 .ctrl_btg_bt_rx = __rtw8852bx_ctrl_btg_bt_rx, 2084 .query_ppdu = __rtw8852bx_query_ppdu, 2085 .convert_rpl_to_rssi = __rtw8852bx_convert_rpl_to_rssi, 2086 .read_efuse = __rtw8852bx_read_efuse, 2087 .read_phycap = __rtw8852bx_read_phycap, 2088 .power_trim = __rtw8852bx_power_trim, 2089 .set_txpwr = __rtw8852bx_set_txpwr, 2090 .set_txpwr_ctrl = __rtw8852bx_set_txpwr_ctrl, 2091 .init_txpwr_unit = __rtw8852bx_init_txpwr_unit, 2092 .set_txpwr_ul_tb_offset = __rtw8852bx_set_txpwr_ul_tb_offset, 2093 .get_thermal = __rtw8852bx_get_thermal, 2094 .adc_cfg = rtw8852bt_adc_cfg, 2095 .btc_init_cfg = __rtw8852bx_btc_init_cfg, 2096 .btc_set_wl_pri = __rtw8852bx_btc_set_wl_pri, 2097 .btc_get_bt_rssi = __rtw8852bx_btc_get_bt_rssi, 2098 .btc_update_bt_cnt = __rtw8852bx_btc_update_bt_cnt, 2099 .btc_wl_s1_standby = __rtw8852bx_btc_wl_s1_standby, 2100 .btc_set_wl_rx_gain = __rtw8852bx_btc_set_wl_rx_gain, 2101}; 2102EXPORT_SYMBOL(rtw8852bx_info); 2103 2104MODULE_AUTHOR("Realtek Corporation"); 2105MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852B common routines"); 2106MODULE_LICENSE("Dual BSD/GPL");
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