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rtw8852a.c
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linux-6.19.14/drivers/net/wireless/realtek/rtw89/rtw8852a.c
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5#include "coex.h" 6#include "fw.h" 7#include "mac.h" 8#include "phy.h" 9#include "reg.h" 10#include "rtw8852a.h" 11#include "rtw8852a_rfk.h" 12#include "rtw8852a_table.h" 13#include "txrx.h" 14 15#define RTW8852A_FW_FORMAT_MAX 0 16#define RTW8852A_FW_BASENAME "rtw89/rtw8852a_fw" 17#define RTW8852A_MODULE_FIRMWARE \ 18 RTW8852A_FW_BASENAME ".bin" 19 20static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = { 21 {128, 1896, grp_0}, /* ACH 0 */ 22 {128, 1896, grp_0}, /* ACH 1 */ 23 {128, 1896, grp_0}, /* ACH 2 */ 24 {128, 1896, grp_0}, /* ACH 3 */ 25 {128, 1896, grp_1}, /* ACH 4 */ 26 {128, 1896, grp_1}, /* ACH 5 */ 27 {128, 1896, grp_1}, /* ACH 6 */ 28 {128, 1896, grp_1}, /* ACH 7 */ 29 {32, 1896, grp_0}, /* B0MGQ */ 30 {128, 1896, grp_0}, /* B0HIQ */ 31 {32, 1896, grp_1}, /* B1MGQ */ 32 {128, 1896, grp_1}, /* B1HIQ */ 33 {40, 0, 0} /* FWCMDQ */ 34}; 35 36static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = { 37 1896, /* Group 0 */ 38 1896, /* Group 1 */ 39 3792, /* Public Max */ 40 0 /* WP threshold */ 41}; 42 43static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = { 44 [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie, 45 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 46 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 47 RTW89_HCIFC_POH}, 48 [RTW89_QTA_INVALID] = {NULL}, 49}; 50 51static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_usb[] = { 52 {22, 402, grp_0}, /* ACH 0 */ 53 {0, 0, grp_0}, /* ACH 1 */ 54 {22, 402, grp_0}, /* ACH 2 */ 55 {0, 0, grp_0}, /* ACH 3 */ 56 {22, 402, grp_0}, /* ACH 4 */ 57 {0, 0, grp_0}, /* ACH 5 */ 58 {22, 402, grp_0}, /* ACH 6 */ 59 {0, 0, grp_0}, /* ACH 7 */ 60 {22, 402, grp_0}, /* B0MGQ */ 61 {0, 0, grp_0}, /* B0HIQ */ 62 {22, 402, grp_0}, /* B1MGQ */ 63 {0, 0, grp_0}, /* B1HIQ */ 64 {0, 0, 0} /* FWCMDQ */ 65}; 66 67static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_usb = { 68 512, /* Group 0 */ 69 0, /* Group 1 */ 70 512, /* Public Max */ 71 104 /* WP threshold */ 72}; 73 74static const struct rtw89_hfc_prec_cfg rtw8852a_hfc_preccfg_usb = { 75 11, /* CH 0-11 pre-cost */ 76 32, /* H2C pre-cost */ 77 76, /* WP CH 0-7 pre-cost */ 78 25, /* WP CH 8-11 pre-cost */ 79 1, /* CH 0-11 full condition */ 80 1, /* H2C full condition */ 81 1, /* WP CH 0-7 full condition */ 82 1, /* WP CH 8-11 full condition */ 83}; 84 85static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_usb[] = { 86 [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_usb, &rtw8852a_hfc_pubcfg_usb, 87 &rtw8852a_hfc_preccfg_usb, RTW89_HCIFC_STF}, 88 [RTW89_QTA_DLFW] = {NULL, NULL, 89 &rtw8852a_hfc_preccfg_usb, RTW89_HCIFC_STF}, 90 [RTW89_QTA_INVALID] = {NULL}, 91}; 92 93static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = { 94 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0, 95 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0, 96 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4, 97 &rtw89_mac_size.ple_qt5}, 98 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size0, 99 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0, 100 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4, 101 &rtw89_mac_size.ple_qt_52a_wow}, 102 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4, 103 &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4, 104 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 105 &rtw89_mac_size.ple_qt13}, 106 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 107 NULL}, 108}; 109 110static const struct rtw89_dle_mem rtw8852a_dle_mem_usb[] = { 111 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size1, 112 &rtw89_mac_size.ple_size1, &rtw89_mac_size.wde_qt1, 113 &rtw89_mac_size.wde_qt1, &rtw89_mac_size.ple_qt25, 114 &rtw89_mac_size.ple_qt26}, 115 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4, 116 &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4, 117 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 118 &rtw89_mac_size.ple_qt13}, 119 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 120 NULL}, 121}; 122 123static const struct rtw89_reg2_def rtw8852a_pmac_ht20_mcs7_tbl[] = { 124 {0x44AC, 0x00000000}, 125 {0x44B0, 0x00000000}, 126 {0x44B4, 0x00000000}, 127 {0x44B8, 0x00000000}, 128 {0x44BC, 0x00000000}, 129 {0x44C0, 0x00000000}, 130 {0x44C4, 0x00000000}, 131 {0x44C8, 0x00000000}, 132 {0x44CC, 0x00000000}, 133 {0x44D0, 0x00000000}, 134 {0x44D4, 0x00000000}, 135 {0x44D8, 0x00000000}, 136 {0x44DC, 0x00000000}, 137 {0x44E0, 0x00000000}, 138 {0x44E4, 0x00000000}, 139 {0x44E8, 0x00000000}, 140 {0x44EC, 0x00000000}, 141 {0x44F0, 0x00000000}, 142 {0x44F4, 0x00000000}, 143 {0x44F8, 0x00000000}, 144 {0x44FC, 0x00000000}, 145 {0x4500, 0x00000000}, 146 {0x4504, 0x00000000}, 147 {0x4508, 0x00000000}, 148 {0x450C, 0x00000000}, 149 {0x4510, 0x00000000}, 150 {0x4514, 0x00000000}, 151 {0x4518, 0x00000000}, 152 {0x451C, 0x00000000}, 153 {0x4520, 0x00000000}, 154 {0x4524, 0x00000000}, 155 {0x4528, 0x00000000}, 156 {0x452C, 0x00000000}, 157 {0x4530, 0x4E1F3E81}, 158 {0x4534, 0x00000000}, 159 {0x4538, 0x0000005A}, 160 {0x453C, 0x00000000}, 161 {0x4540, 0x00000000}, 162 {0x4544, 0x00000000}, 163 {0x4548, 0x00000000}, 164 {0x454C, 0x00000000}, 165 {0x4550, 0x00000000}, 166 {0x4554, 0x00000000}, 167 {0x4558, 0x00000000}, 168 {0x455C, 0x00000000}, 169 {0x4560, 0x4060001A}, 170 {0x4564, 0x40000000}, 171 {0x4568, 0x00000000}, 172 {0x456C, 0x00000000}, 173 {0x4570, 0x04000007}, 174 {0x4574, 0x0000DC87}, 175 {0x4578, 0x00000BAB}, 176 {0x457C, 0x03E00000}, 177 {0x4580, 0x00000048}, 178 {0x4584, 0x00000000}, 179 {0x4588, 0x000003E8}, 180 {0x458C, 0x30000000}, 181 {0x4590, 0x00000000}, 182 {0x4594, 0x10000000}, 183 {0x4598, 0x00000001}, 184 {0x459C, 0x00030000}, 185 {0x45A0, 0x01000000}, 186 {0x45A4, 0x03000200}, 187 {0x45A8, 0xC00001C0}, 188 {0x45AC, 0x78018000}, 189 {0x45B0, 0x80000000}, 190 {0x45B4, 0x01C80600}, 191 {0x45B8, 0x00000002}, 192 {0x4594, 0x10000000} 193}; 194 195static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = { 196 {0x4624, GENMASK(20, 14), 0x40}, 197 {0x46f8, GENMASK(20, 14), 0x40}, 198 {0x4674, GENMASK(20, 19), 0x2}, 199 {0x4748, GENMASK(20, 19), 0x2}, 200 {0x4650, GENMASK(14, 10), 0x18}, 201 {0x4724, GENMASK(14, 10), 0x18}, 202 {0x4688, GENMASK(1, 0), 0x3}, 203 {0x475c, GENMASK(1, 0), 0x3}, 204}; 205 206static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs); 207 208static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = { 209 {0x4624, GENMASK(20, 14), 0x1a}, 210 {0x46f8, GENMASK(20, 14), 0x1a}, 211 {0x4674, GENMASK(20, 19), 0x1}, 212 {0x4748, GENMASK(20, 19), 0x1}, 213 {0x4650, GENMASK(14, 10), 0x12}, 214 {0x4724, GENMASK(14, 10), 0x12}, 215 {0x4688, GENMASK(1, 0), 0x0}, 216 {0x475c, GENMASK(1, 0), 0x0}, 217}; 218 219static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs); 220 221static const struct rtw89_pwr_cfg rtw8852a_pwron[] = { 222 {0x00C6, 223 PWR_CV_MSK_B, 224 PWR_INTF_MSK_PCIE, 225 PWR_BASE_MAC, 226 PWR_CMD_WRITE, BIT(6), BIT(6)}, 227 {0x1086, 228 PWR_CV_MSK_ALL, 229 PWR_INTF_MSK_SDIO, 230 PWR_BASE_MAC, 231 PWR_CMD_WRITE, BIT(0), 0}, 232 {0x1086, 233 PWR_CV_MSK_ALL, 234 PWR_INTF_MSK_SDIO, 235 PWR_BASE_MAC, 236 PWR_CMD_POLL, BIT(1), BIT(1)}, 237 {0x0005, 238 PWR_CV_MSK_ALL, 239 PWR_INTF_MSK_ALL, 240 PWR_BASE_MAC, 241 PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, 242 {0x0005, 243 PWR_CV_MSK_ALL, 244 PWR_INTF_MSK_ALL, 245 PWR_BASE_MAC, 246 PWR_CMD_WRITE, BIT(7), 0}, 247 {0x0005, 248 PWR_CV_MSK_ALL, 249 PWR_INTF_MSK_ALL, 250 PWR_BASE_MAC, 251 PWR_CMD_WRITE, BIT(2), 0}, 252 {0x0006, 253 PWR_CV_MSK_ALL, 254 PWR_INTF_MSK_ALL, 255 PWR_BASE_MAC, 256 PWR_CMD_POLL, BIT(1), BIT(1)}, 257 {0x0006, 258 PWR_CV_MSK_ALL, 259 PWR_INTF_MSK_ALL, 260 PWR_BASE_MAC, 261 PWR_CMD_WRITE, BIT(0), BIT(0)}, 262 {0x0005, 263 PWR_CV_MSK_ALL, 264 PWR_INTF_MSK_ALL, 265 PWR_BASE_MAC, 266 PWR_CMD_WRITE, BIT(0), BIT(0)}, 267 {0x0005, 268 PWR_CV_MSK_ALL, 269 PWR_INTF_MSK_ALL, 270 PWR_BASE_MAC, 271 PWR_CMD_POLL, BIT(0), 0}, 272 {0x106D, 273 PWR_CV_MSK_B | PWR_CV_MSK_C, 274 PWR_INTF_MSK_USB, 275 PWR_BASE_MAC, 276 PWR_CMD_WRITE, BIT(6), 0}, 277 {0x0088, 278 PWR_CV_MSK_ALL, 279 PWR_INTF_MSK_ALL, 280 PWR_BASE_MAC, 281 PWR_CMD_WRITE, BIT(0), BIT(0)}, 282 {0x0088, 283 PWR_CV_MSK_ALL, 284 PWR_INTF_MSK_ALL, 285 PWR_BASE_MAC, 286 PWR_CMD_WRITE, BIT(0), 0}, 287 {0x0088, 288 PWR_CV_MSK_ALL, 289 PWR_INTF_MSK_ALL, 290 PWR_BASE_MAC, 291 PWR_CMD_WRITE, BIT(0), BIT(0)}, 292 {0x0088, 293 PWR_CV_MSK_ALL, 294 PWR_INTF_MSK_ALL, 295 PWR_BASE_MAC, 296 PWR_CMD_WRITE, BIT(0), 0}, 297 {0x0088, 298 PWR_CV_MSK_ALL, 299 PWR_INTF_MSK_ALL, 300 PWR_BASE_MAC, 301 PWR_CMD_WRITE, BIT(0), BIT(0)}, 302 {0x0083, 303 PWR_CV_MSK_ALL, 304 PWR_INTF_MSK_ALL, 305 PWR_BASE_MAC, 306 PWR_CMD_WRITE, BIT(6), 0}, 307 {0x0080, 308 PWR_CV_MSK_ALL, 309 PWR_INTF_MSK_ALL, 310 PWR_BASE_MAC, 311 PWR_CMD_WRITE, BIT(5), BIT(5)}, 312 {0x0024, 313 PWR_CV_MSK_ALL, 314 PWR_INTF_MSK_ALL, 315 PWR_BASE_MAC, 316 PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0}, 317 {0x02A0, 318 PWR_CV_MSK_ALL, 319 PWR_INTF_MSK_ALL, 320 PWR_BASE_MAC, 321 PWR_CMD_WRITE, BIT(1), BIT(1)}, 322 {0x02A2, 323 PWR_CV_MSK_ALL, 324 PWR_INTF_MSK_ALL, 325 PWR_BASE_MAC, 326 PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0}, 327 {0x0071, 328 PWR_CV_MSK_ALL, 329 PWR_INTF_MSK_PCIE, 330 PWR_BASE_MAC, 331 PWR_CMD_WRITE, BIT(4), 0}, 332 {0x0010, 333 PWR_CV_MSK_A, 334 PWR_INTF_MSK_PCIE, 335 PWR_BASE_MAC, 336 PWR_CMD_WRITE, BIT(2), BIT(2)}, 337 {0x02A0, 338 PWR_CV_MSK_A, 339 PWR_INTF_MSK_ALL, 340 PWR_BASE_MAC, 341 PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 342 {0xFFFF, 343 PWR_CV_MSK_ALL, 344 PWR_INTF_MSK_ALL, 345 0, 346 PWR_CMD_END, 0, 0}, 347}; 348 349static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = { 350 {0x02F0, 351 PWR_CV_MSK_ALL, 352 PWR_INTF_MSK_ALL, 353 PWR_BASE_MAC, 354 PWR_CMD_WRITE, 0xFF, 0}, 355 {0x02F1, 356 PWR_CV_MSK_ALL, 357 PWR_INTF_MSK_ALL, 358 PWR_BASE_MAC, 359 PWR_CMD_WRITE, 0xFF, 0}, 360 {0x0006, 361 PWR_CV_MSK_ALL, 362 PWR_INTF_MSK_ALL, 363 PWR_BASE_MAC, 364 PWR_CMD_WRITE, BIT(0), BIT(0)}, 365 {0x0002, 366 PWR_CV_MSK_ALL, 367 PWR_INTF_MSK_ALL, 368 PWR_BASE_MAC, 369 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 370 {0x0082, 371 PWR_CV_MSK_ALL, 372 PWR_INTF_MSK_ALL, 373 PWR_BASE_MAC, 374 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 375 {0x106D, 376 PWR_CV_MSK_B | PWR_CV_MSK_C, 377 PWR_INTF_MSK_USB, 378 PWR_BASE_MAC, 379 PWR_CMD_WRITE, BIT(6), BIT(6)}, 380 {0x0005, 381 PWR_CV_MSK_ALL, 382 PWR_INTF_MSK_ALL, 383 PWR_BASE_MAC, 384 PWR_CMD_WRITE, BIT(1), BIT(1)}, 385 {0x0005, 386 PWR_CV_MSK_ALL, 387 PWR_INTF_MSK_ALL, 388 PWR_BASE_MAC, 389 PWR_CMD_POLL, BIT(1), 0}, 390 {0x0091, 391 PWR_CV_MSK_ALL, 392 PWR_INTF_MSK_PCIE, 393 PWR_BASE_MAC, 394 PWR_CMD_WRITE, BIT(0), 0}, 395 {0x0092, 396 PWR_CV_MSK_ALL, 397 PWR_INTF_MSK_PCIE, 398 PWR_BASE_MAC, 399 PWR_CMD_WRITE, BIT(4), BIT(4)}, 400 {0x0005, 401 PWR_CV_MSK_ALL, 402 PWR_INTF_MSK_PCIE, 403 PWR_BASE_MAC, 404 PWR_CMD_WRITE, BIT(2), BIT(2)}, 405 {0x0007, 406 PWR_CV_MSK_ALL, 407 PWR_INTF_MSK_USB, 408 PWR_BASE_MAC, 409 PWR_CMD_WRITE, BIT(4), 0}, 410 {0x0007, 411 PWR_CV_MSK_ALL, 412 PWR_INTF_MSK_SDIO, 413 PWR_BASE_MAC, 414 PWR_CMD_WRITE, BIT(6) | BIT(4), 0}, 415 {0x0005, 416 PWR_CV_MSK_ALL, 417 PWR_INTF_MSK_SDIO, 418 PWR_BASE_MAC, 419 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 420 {0x0005, 421 PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F | 422 PWR_CV_MSK_G, 423 PWR_INTF_MSK_USB, 424 PWR_BASE_MAC, 425 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 426 {0x1086, 427 PWR_CV_MSK_ALL, 428 PWR_INTF_MSK_SDIO, 429 PWR_BASE_MAC, 430 PWR_CMD_WRITE, BIT(0), BIT(0)}, 431 {0x1086, 432 PWR_CV_MSK_ALL, 433 PWR_INTF_MSK_SDIO, 434 PWR_BASE_MAC, 435 PWR_CMD_POLL, BIT(1), 0}, 436 {0xFFFF, 437 PWR_CV_MSK_ALL, 438 PWR_INTF_MSK_ALL, 439 0, 440 PWR_CMD_END, 0, 0}, 441}; 442 443static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = { 444 rtw8852a_pwron, NULL 445}; 446 447static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = { 448 rtw8852a_pwroff, NULL 449}; 450 451static const u32 rtw8852a_h2c_regs[RTW89_H2CREG_MAX] = { 452 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2, 453 R_AX_H2CREG_DATA3 454}; 455 456static const u32 rtw8852a_c2h_regs[RTW89_C2HREG_MAX] = { 457 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2, 458 R_AX_C2HREG_DATA3 459}; 460 461static const u32 rtw8852a_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = { 462 R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3, 463}; 464 465static const struct rtw89_page_regs rtw8852a_page_regs = { 466 .hci_fc_ctrl = R_AX_HCI_FC_CTRL, 467 .ch_page_ctrl = R_AX_CH_PAGE_CTRL, 468 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL, 469 .ach_page_info = R_AX_ACH0_PAGE_INFO, 470 .pub_page_info3 = R_AX_PUB_PAGE_INFO3, 471 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1, 472 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2, 473 .pub_page_info1 = R_AX_PUB_PAGE_INFO1, 474 .pub_page_info2 = R_AX_PUB_PAGE_INFO2, 475 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1, 476 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2, 477 .wp_page_info1 = R_AX_WP_PAGE_INFO1, 478}; 479 480static const struct rtw89_reg_def rtw8852a_dcfo_comp = { 481 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK 482}; 483 484static const struct rtw89_reg_def rtw8852a_nhm_th[RTW89_NHM_TH_NUM] = { 485 {R_NHM_CFG, B_NHM_TH0_MSK}, 486 {R_NHM_TH1, B_NHM_TH1_MSK}, 487 {R_NHM_TH1, B_NHM_TH2_MSK}, 488 {R_NHM_TH1, B_NHM_TH3_MSK}, 489 {R_NHM_TH1, B_NHM_TH4_MSK}, 490 {R_NHM_TH5, B_NHM_TH5_MSK}, 491 {R_NHM_TH5, B_NHM_TH6_MSK}, 492 {R_NHM_TH5, B_NHM_TH7_MSK}, 493 {R_NHM_TH5, B_NHM_TH8_MSK}, 494 {R_NHM_TH9, B_NHM_TH9_MSK}, 495 {R_NHM_TH9, B_NHM_TH10_MSK}, 496}; 497 498static const struct rtw89_reg_def rtw8852a_nhm_rpt[RTW89_NHM_RPT_NUM] = { 499 {R_NHM_CNT0, B_NHM_CNT0_MSK}, 500 {R_NHM_CNT0, B_NHM_CNT1_MSK}, 501 {R_NHM_CNT2, B_NHM_CNT2_MSK}, 502 {R_NHM_CNT2, B_NHM_CNT3_MSK}, 503 {R_NHM_CNT4, B_NHM_CNT4_MSK}, 504 {R_NHM_CNT4, B_NHM_CNT5_MSK}, 505 {R_NHM_CNT6, B_NHM_CNT6_MSK}, 506 {R_NHM_CNT6, B_NHM_CNT7_MSK}, 507 {R_NHM_CNT8, B_NHM_CNT8_MSK}, 508 {R_NHM_CNT8, B_NHM_CNT9_MSK}, 509 {R_NHM_CNT10, B_NHM_CNT10_MSK}, 510 {R_NHM_CNT10, B_NHM_CNT11_MSK}, 511}; 512 513static const struct rtw89_imr_info rtw8852a_imr_info = { 514 .wdrls_imr_set = B_AX_WDRLS_IMR_SET, 515 .wsec_imr_reg = R_AX_SEC_DEBUG, 516 .wsec_imr_set = B_AX_IMR_ERROR, 517 .mpdu_tx_imr_set = 0, 518 .mpdu_rx_imr_set = 0, 519 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 520 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR, 521 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR, 522 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET, 523 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1, 524 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR, 525 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET, 526 .wde_imr_clr = B_AX_WDE_IMR_CLR, 527 .wde_imr_set = B_AX_WDE_IMR_SET, 528 .ple_imr_clr = B_AX_PLE_IMR_CLR, 529 .ple_imr_set = B_AX_PLE_IMR_SET, 530 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR, 531 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET, 532 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR, 533 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET, 534 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR, 535 .other_disp_imr_set = 0, 536 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR, 537 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR, 538 .bbrpt_err_imr_set = 0, 539 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR, 540 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR, 541 .ptcl_imr_set = B_AX_PTCL_IMR_SET, 542 .cdma_imr_0_reg = R_AX_DLE_CTRL, 543 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR, 544 .cdma_imr_0_set = B_AX_DLE_IMR_SET, 545 .cdma_imr_1_reg = 0, 546 .cdma_imr_1_clr = 0, 547 .cdma_imr_1_set = 0, 548 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR, 549 .phy_intf_imr_clr = 0, 550 .phy_intf_imr_set = 0, 551 .rmac_imr_reg = R_AX_RMAC_ERR_ISR, 552 .rmac_imr_clr = B_AX_RMAC_IMR_CLR, 553 .rmac_imr_set = B_AX_RMAC_IMR_SET, 554 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR, 555 .tmac_imr_clr = B_AX_TMAC_IMR_CLR, 556 .tmac_imr_set = B_AX_TMAC_IMR_SET, 557}; 558 559static const struct rtw89_xtal_info rtw8852a_xtal_info = { 560 .xcap_reg = R_AX_XTAL_ON_CTRL0, 561 .sc_xo_mask = B_AX_XTAL_SC_XO_MASK, 562 .sc_xi_mask = B_AX_XTAL_SC_XI_MASK, 563}; 564 565static const struct rtw89_rrsr_cfgs rtw8852a_rrsr_cfgs = { 566 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 567 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2}, 568}; 569 570static const struct rtw89_rfkill_regs rtw8852a_rfkill_regs = { 571 .pinmux = {R_AX_GPIO8_15_FUNC_SEL, 572 B_AX_PINMUX_GPIO9_FUNC_SEL_MASK, 573 0xf}, 574 .mode = {R_AX_GPIO_EXT_CTRL + 2, 575 (B_AX_GPIO_MOD_9 | B_AX_GPIO_IO_SEL_9) >> 16, 576 0x0}, 577}; 578 579static const struct rtw89_dig_regs rtw8852a_dig_regs = { 580 .seg0_pd_reg = R_SEG0R_PD, 581 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 582 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, 583 .bmode_pd_reg = R_BMODE_PDTH_EN_V1, 584 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, 585 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, 586 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, 587 .p0_lna_init = {R_PATH0_LNA_INIT, B_PATH0_LNA_INIT_IDX_MSK}, 588 .p1_lna_init = {R_PATH1_LNA_INIT, B_PATH1_LNA_INIT_IDX_MSK}, 589 .p0_tia_init = {R_PATH0_TIA_INIT, B_PATH0_TIA_INIT_IDX_MSK}, 590 .p1_tia_init = {R_PATH1_TIA_INIT, B_PATH1_TIA_INIT_IDX_MSK}, 591 .p0_rxb_init = {R_PATH0_RXB_INIT, B_PATH0_RXB_INIT_IDX_MSK}, 592 .p1_rxb_init = {R_PATH1_RXB_INIT, B_PATH1_RXB_INIT_IDX_MSK}, 593 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC, 594 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 595 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC, 596 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 597 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC, 598 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 599 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC, 600 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 601}; 602 603static const struct rtw89_edcca_regs rtw8852a_edcca_regs = { 604 .edcca_level = R_SEG0R_EDCCA_LVL, 605 .edcca_mask = B_EDCCA_LVL_MSK0, 606 .edcca_p_mask = B_EDCCA_LVL_MSK1, 607 .ppdu_level = R_SEG0R_EDCCA_LVL, 608 .ppdu_mask = B_EDCCA_LVL_MSK3, 609 .p = {{ 610 .rpt_a = R_EDCCA_RPT_A, 611 .rpt_b = R_EDCCA_RPT_B, 612 .rpt_sel = R_EDCCA_RPT_SEL, 613 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK, 614 }, { 615 .rpt_a = R_EDCCA_RPT_P1_A, 616 .rpt_b = R_EDCCA_RPT_P1_B, 617 .rpt_sel = R_EDCCA_RPT_SEL, 618 .rpt_sel_mask = B_EDCCA_RPT_SEL_P1_MSK, 619 }}, 620 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST, 621 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M, 622}; 623 624static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 625 struct rtw8852a_efuse *map) 626{ 627 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 628 struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 629 u8 i, j; 630 631 tssi->thermal[RF_PATH_A] = map->path_a_therm; 632 tssi->thermal[RF_PATH_B] = map->path_b_therm; 633 634 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 635 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 636 sizeof(ofst[i]->cck_tssi)); 637 638 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 639 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 640 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 641 i, j, tssi->tssi_cck[i][j]); 642 643 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 644 sizeof(ofst[i]->bw40_tssi)); 645 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 646 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 647 648 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 649 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 650 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 651 i, j, tssi->tssi_mcs[i][j]); 652 } 653} 654 655static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map, 656 enum rtw89_efuse_block block) 657{ 658 struct rtw89_efuse *efuse = &rtwdev->efuse; 659 struct rtw8852a_efuse *map; 660 661 map = (struct rtw8852a_efuse *)log_map; 662 663 efuse->country_code[0] = map->country_code[0]; 664 efuse->country_code[1] = map->country_code[1]; 665 rtw8852a_efuse_parsing_tssi(rtwdev, map); 666 667 switch (rtwdev->hci.type) { 668 case RTW89_HCI_TYPE_PCIE: 669 ether_addr_copy(efuse->addr, map->e.mac_addr); 670 break; 671 case RTW89_HCI_TYPE_USB: 672 ether_addr_copy(efuse->addr, map->u.mac_addr); 673 break; 674 default: 675 return -ENOTSUPP; 676 } 677 678 efuse->rfe_type = map->rfe_type; 679 efuse->xtal_cap = map->xtal_k; 680 681 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 682 683 return 0; 684} 685 686static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 687{ 688 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 689 static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB}; 690 u32 addr = rtwdev->chip->phycap_addr; 691 bool pg = false; 692 u32 ofst; 693 u8 i, j; 694 695 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 696 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 697 /* addrs are in decreasing order */ 698 ofst = tssi_trim_addr[i] - addr - j; 699 tssi->tssi_trim[i][j] = phycap_map[ofst]; 700 701 if (phycap_map[ofst] != 0xff) 702 pg = true; 703 } 704 } 705 706 if (!pg) { 707 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 708 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 709 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 710 } 711 712 for (i = 0; i < RF_PATH_NUM_8852A; i++) 713 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 714 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 715 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 716 i, j, tssi->tssi_trim[i][j], 717 tssi_trim_addr[i] - j); 718} 719 720static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 721 u8 *phycap_map) 722{ 723 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 724 static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC}; 725 u32 addr = rtwdev->chip->phycap_addr; 726 u8 i; 727 728 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 729 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 730 731 rtw89_debug(rtwdev, RTW89_DBG_RFK, 732 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 733 i, info->thermal_trim[i]); 734 735 if (info->thermal_trim[i] != 0xff) 736 info->pg_thermal_trim = true; 737 } 738} 739 740static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev) 741{ 742#define __thm_setting(raw) \ 743({ \ 744 u8 __v = (raw); \ 745 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 746}) 747 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 748 u8 i, val; 749 750 if (!info->pg_thermal_trim) { 751 rtw89_debug(rtwdev, RTW89_DBG_RFK, 752 "[THERMAL][TRIM] no PG, do nothing\n"); 753 754 return; 755 } 756 757 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 758 val = __thm_setting(info->thermal_trim[i]); 759 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 760 761 rtw89_debug(rtwdev, RTW89_DBG_RFK, 762 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 763 i, val); 764 } 765#undef __thm_setting 766} 767 768static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 769 u8 *phycap_map) 770{ 771 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 772 static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB}; 773 u32 addr = rtwdev->chip->phycap_addr; 774 u8 i; 775 776 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 777 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 778 779 rtw89_debug(rtwdev, RTW89_DBG_RFK, 780 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 781 i, info->pa_bias_trim[i]); 782 783 if (info->pa_bias_trim[i] != 0xff) 784 info->pg_pa_bias_trim = true; 785 } 786} 787 788static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev) 789{ 790 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 791 u8 pabias_2g, pabias_5g; 792 u8 i; 793 794 if (!info->pg_pa_bias_trim) { 795 rtw89_debug(rtwdev, RTW89_DBG_RFK, 796 "[PA_BIAS][TRIM] no PG, do nothing\n"); 797 798 return; 799 } 800 801 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 802 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 803 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 804 805 rtw89_debug(rtwdev, RTW89_DBG_RFK, 806 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 807 i, pabias_2g, pabias_5g); 808 809 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 810 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 811 } 812} 813 814static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 815{ 816 rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map); 817 rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map); 818 rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 819 820 return 0; 821} 822 823static void rtw8852a_power_trim(struct rtw89_dev *rtwdev) 824{ 825 rtw8852a_thermal_trim(rtwdev); 826 rtw8852a_pa_bias_trim(rtwdev); 827} 828 829static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev, 830 const struct rtw89_chan *chan, 831 u8 mac_idx) 832{ 833 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); 834 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 835 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); 836 u8 txsc20 = 0, txsc40 = 0; 837 838 switch (chan->band_width) { 839 case RTW89_CHANNEL_WIDTH_80: 840 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, 841 RTW89_CHANNEL_WIDTH_40); 842 fallthrough; 843 case RTW89_CHANNEL_WIDTH_40: 844 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, 845 RTW89_CHANNEL_WIDTH_20); 846 break; 847 default: 848 break; 849 } 850 851 switch (chan->band_width) { 852 case RTW89_CHANNEL_WIDTH_80: 853 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); 854 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); 855 break; 856 case RTW89_CHANNEL_WIDTH_40: 857 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); 858 rtw89_write32(rtwdev, sub_carr, txsc20); 859 break; 860 case RTW89_CHANNEL_WIDTH_20: 861 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); 862 rtw89_write32(rtwdev, sub_carr, 0); 863 break; 864 default: 865 break; 866 } 867 868 if (chan->channel > 14) 869 rtw89_write8_set(rtwdev, chk_rate, 870 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 871 else 872 rtw89_write8_clr(rtwdev, chk_rate, 873 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 874} 875 876static const u32 rtw8852a_sco_barker_threshold[14] = { 877 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, 878 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 879}; 880 881static const u32 rtw8852a_sco_cck_threshold[14] = { 882 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, 883 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed 884}; 885 886static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 887 u8 primary_ch, enum rtw89_bandwidth bw) 888{ 889 u8 ch_element; 890 891 if (bw == RTW89_CHANNEL_WIDTH_20) { 892 ch_element = central_ch - 1; 893 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 894 if (primary_ch == 1) 895 ch_element = central_ch - 1 + 2; 896 else 897 ch_element = central_ch - 1 - 2; 898 } else { 899 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 900 return -EINVAL; 901 } 902 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, 903 rtw8852a_sco_barker_threshold[ch_element]); 904 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, 905 rtw8852a_sco_cck_threshold[ch_element]); 906 907 return 0; 908} 909 910static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch, 911 u8 path) 912{ 913 u32 val; 914 915 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 916 if (val == INV_RF_DATA) { 917 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 918 return; 919 } 920 val &= ~0x303ff; 921 val |= central_ch; 922 if (central_ch > 14) 923 val |= (BIT(16) | BIT(8)); 924 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 925} 926 927static u8 rtw8852a_sco_mapping(u8 central_ch) 928{ 929 if (central_ch == 1) 930 return 109; 931 else if (central_ch >= 2 && central_ch <= 6) 932 return 108; 933 else if (central_ch >= 7 && central_ch <= 10) 934 return 107; 935 else if (central_ch >= 11 && central_ch <= 14) 936 return 106; 937 else if (central_ch == 36 || central_ch == 38) 938 return 51; 939 else if (central_ch >= 40 && central_ch <= 58) 940 return 50; 941 else if (central_ch >= 60 && central_ch <= 64) 942 return 49; 943 else if (central_ch == 100 || central_ch == 102) 944 return 48; 945 else if (central_ch >= 104 && central_ch <= 126) 946 return 47; 947 else if (central_ch >= 128 && central_ch <= 151) 948 return 46; 949 else if (central_ch >= 153 && central_ch <= 177) 950 return 45; 951 else 952 return 0; 953} 954 955static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch, 956 enum rtw89_phy_idx phy_idx) 957{ 958 u8 sco_comp; 959 bool is_2g = central_ch <= 14; 960 961 if (phy_idx == RTW89_PHY_0) { 962 /* Path A */ 963 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A); 964 if (is_2g) 965 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 966 B_PATH0_TIA_ERR_G1_SEL, 1, 967 phy_idx); 968 else 969 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 970 B_PATH0_TIA_ERR_G1_SEL, 0, 971 phy_idx); 972 973 /* Path B */ 974 if (!rtwdev->dbcc_en) { 975 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 976 if (is_2g) 977 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 978 B_P1_MODE_SEL, 979 1, phy_idx); 980 else 981 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 982 B_P1_MODE_SEL, 983 0, phy_idx); 984 } else { 985 if (is_2g) 986 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, 987 B_2P4G_BAND_SEL); 988 else 989 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, 990 B_2P4G_BAND_SEL); 991 } 992 /* SCO compensate FC setting */ 993 sco_comp = rtw8852a_sco_mapping(central_ch); 994 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 995 sco_comp, phy_idx); 996 } else { 997 /* Path B */ 998 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 999 if (is_2g) 1000 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 1001 B_P1_MODE_SEL, 1002 1, phy_idx); 1003 else 1004 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 1005 B_P1_MODE_SEL, 1006 0, phy_idx); 1007 /* SCO compensate FC setting */ 1008 sco_comp = rtw8852a_sco_mapping(central_ch); 1009 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 1010 sco_comp, phy_idx); 1011 } 1012 1013 /* Band edge */ 1014 if (is_2g) 1015 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1, 1016 phy_idx); 1017 else 1018 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0, 1019 phy_idx); 1020 1021 /* CCK parameters */ 1022 if (central_ch == 14) { 1023 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 1024 0x3b13ff); 1025 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 1026 0x1c42de); 1027 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 1028 0xfdb0ad); 1029 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 1030 0xf60f6e); 1031 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 1032 0xfd8f92); 1033 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); 1034 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); 1035 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 1036 0xfff00a); 1037 } else { 1038 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 1039 0x3d23ff); 1040 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 1041 0x29b354); 1042 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); 1043 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 1044 0xfdb053); 1045 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 1046 0xf86f9a); 1047 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 1048 0xfaef92); 1049 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 1050 0xfe5fcc); 1051 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 1052 0xffdff5); 1053 } 1054} 1055 1056static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 1057{ 1058 u32 val = 0; 1059 u32 adc_sel[2] = {0x12d0, 0x32d0}; 1060 u32 wbadc_sel[2] = {0x12ec, 0x32ec}; 1061 1062 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 1063 if (val == INV_RF_DATA) { 1064 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 1065 return; 1066 } 1067 val &= ~(BIT(11) | BIT(10)); 1068 switch (bw) { 1069 case RTW89_CHANNEL_WIDTH_5: 1070 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 1071 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 1072 val |= (BIT(11) | BIT(10)); 1073 break; 1074 case RTW89_CHANNEL_WIDTH_10: 1075 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 1076 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 1077 val |= (BIT(11) | BIT(10)); 1078 break; 1079 case RTW89_CHANNEL_WIDTH_20: 1080 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1081 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1082 val |= (BIT(11) | BIT(10)); 1083 break; 1084 case RTW89_CHANNEL_WIDTH_40: 1085 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1086 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1087 val |= BIT(11); 1088 break; 1089 case RTW89_CHANNEL_WIDTH_80: 1090 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1091 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1092 val |= BIT(10); 1093 break; 1094 default: 1095 rtw89_warn(rtwdev, "Fail to set ADC\n"); 1096 } 1097 1098 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 1099} 1100 1101static void 1102rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 1103 enum rtw89_phy_idx phy_idx) 1104{ 1105 /* Switch bandwidth */ 1106 switch (bw) { 1107 case RTW89_CHANNEL_WIDTH_5: 1108 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1109 phy_idx); 1110 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1, 1111 phy_idx); 1112 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1113 0x0, phy_idx); 1114 break; 1115 case RTW89_CHANNEL_WIDTH_10: 1116 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1117 phy_idx); 1118 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2, 1119 phy_idx); 1120 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1121 0x0, phy_idx); 1122 break; 1123 case RTW89_CHANNEL_WIDTH_20: 1124 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1125 phy_idx); 1126 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1127 phy_idx); 1128 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1129 0x0, phy_idx); 1130 break; 1131 case RTW89_CHANNEL_WIDTH_40: 1132 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 1133 phy_idx); 1134 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1135 phy_idx); 1136 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1137 pri_ch, 1138 phy_idx); 1139 if (pri_ch == RTW89_SC_20_UPPER) 1140 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); 1141 else 1142 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); 1143 break; 1144 case RTW89_CHANNEL_WIDTH_80: 1145 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 1146 phy_idx); 1147 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1148 phy_idx); 1149 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1150 pri_ch, 1151 phy_idx); 1152 break; 1153 default: 1154 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1155 pri_ch); 1156 } 1157 1158 if (phy_idx == RTW89_PHY_0) { 1159 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A); 1160 if (!rtwdev->dbcc_en) 1161 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 1162 } else { 1163 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 1164 } 1165} 1166 1167static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch) 1168{ 1169 if (central_ch == 153) { 1170 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1171 0x210); 1172 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1173 0x210); 1174 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x7c0); 1175 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1176 B_P0_NBIIDX_NOTCH_EN, 0x1); 1177 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1178 B_P1_NBIIDX_NOTCH_EN, 0x1); 1179 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1180 0x1); 1181 } else if (central_ch == 151) { 1182 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1183 0x210); 1184 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1185 0x210); 1186 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x40); 1187 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1188 B_P0_NBIIDX_NOTCH_EN, 0x1); 1189 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1190 B_P1_NBIIDX_NOTCH_EN, 0x1); 1191 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1192 0x1); 1193 } else if (central_ch == 155) { 1194 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1195 0x2d0); 1196 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1197 0x2d0); 1198 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x740); 1199 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1200 B_P0_NBIIDX_NOTCH_EN, 0x1); 1201 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1202 B_P1_NBIIDX_NOTCH_EN, 0x1); 1203 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1204 0x1); 1205 } else { 1206 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1207 B_P0_NBIIDX_NOTCH_EN, 0x0); 1208 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1209 B_P1_NBIIDX_NOTCH_EN, 0x0); 1210 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1211 0x0); 1212 } 1213} 1214 1215static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev, 1216 enum rtw89_phy_idx phy_idx) 1217{ 1218 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1219 phy_idx); 1220 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1221 phy_idx); 1222 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1223 phy_idx); 1224} 1225 1226static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev, 1227 enum rtw89_phy_idx phy_idx, bool en) 1228{ 1229 if (en) 1230 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1231 1, 1232 phy_idx); 1233 else 1234 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1235 0, 1236 phy_idx); 1237} 1238 1239static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev, 1240 enum rtw89_phy_idx phy_idx) 1241{ 1242 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1243 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1244 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1245 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1246 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1247 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1248 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1249 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1250 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1251} 1252 1253static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1254 enum rtw89_phy_idx phy_idx) 1255{ 1256 u32 addr; 1257 1258 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1259 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1260 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1261} 1262 1263static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev) 1264{ 1265 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); 1266 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP); 1267 1268 if (rtwdev->hal.cv <= CHIP_CCV) { 1269 rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG); 1270 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000); 1271 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x43F); 1272 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF); 1273 rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST); 1274 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1275 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1276 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, B_STS_PARSING_TIME); 1277 } 1278 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f); 1279 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c); 1280 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); 1281 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1); 1282 rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK); 1283 rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK); 1284 1285 rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1286} 1287 1288static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev, 1289 enum rtw89_phy_idx phy_idx) 1290{ 1291 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1292 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1293 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1294 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1295 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1296 udelay(1); 1297} 1298 1299static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev, 1300 const struct rtw89_chan *chan, 1301 enum rtw89_phy_idx phy_idx) 1302{ 1303 bool cck_en = chan->channel <= 14; 1304 u8 pri_ch_idx = chan->pri_ch_idx; 1305 1306 if (cck_en) 1307 rtw8852a_ctrl_sco_cck(rtwdev, chan->channel, 1308 chan->primary_channel, 1309 chan->band_width); 1310 1311 rtw8852a_ctrl_ch(rtwdev, chan->channel, phy_idx); 1312 rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1313 if (cck_en) { 1314 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); 1315 } else { 1316 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); 1317 rtw8852a_bbrst_for_rfk(rtwdev, phy_idx); 1318 } 1319 rtw8852a_spur_elimination(rtwdev, chan->channel); 1320 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, 1321 chan->primary_channel); 1322 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1323} 1324 1325static void rtw8852a_set_channel(struct rtw89_dev *rtwdev, 1326 const struct rtw89_chan *chan, 1327 enum rtw89_mac_idx mac_idx, 1328 enum rtw89_phy_idx phy_idx) 1329{ 1330 rtw8852a_set_channel_mac(rtwdev, chan, mac_idx); 1331 rtw8852a_set_channel_bb(rtwdev, chan, phy_idx); 1332} 1333 1334static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en) 1335{ 1336 if (en) 1337 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1338 else 1339 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1340} 1341 1342static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 1343 enum rtw89_rf_path path) 1344{ 1345 static const u32 tssi_trk[2] = {0x5818, 0x7818}; 1346 static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc}; 1347 1348 if (en) { 1349 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0); 1350 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0); 1351 } else { 1352 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1); 1353 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1); 1354 } 1355} 1356 1357static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, 1358 u8 phy_idx) 1359{ 1360 if (!rtwdev->dbcc_en) { 1361 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1362 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1363 } else { 1364 if (phy_idx == RTW89_PHY_0) 1365 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1366 else 1367 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1368 } 1369} 1370 1371static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en) 1372{ 1373 if (en) 1374 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1375 0x0); 1376 else 1377 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1378 0xf); 1379} 1380 1381static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1382 struct rtw89_channel_help_params *p, 1383 const struct rtw89_chan *chan, 1384 enum rtw89_mac_idx mac_idx, 1385 enum rtw89_phy_idx phy_idx) 1386{ 1387 if (enter) { 1388 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en, 1389 RTW89_SCH_TX_SEL_ALL); 1390 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false); 1391 rtw8852a_dfs_en(rtwdev, false); 1392 rtw8852a_tssi_cont_en_phyidx(rtwdev, false, phy_idx); 1393 rtw8852a_adc_en(rtwdev, false); 1394 fsleep(40); 1395 rtw8852a_bb_reset_en(rtwdev, phy_idx, false); 1396 } else { 1397 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true); 1398 rtw8852a_adc_en(rtwdev, true); 1399 rtw8852a_dfs_en(rtwdev, true); 1400 rtw8852a_tssi_cont_en_phyidx(rtwdev, true, phy_idx); 1401 rtw8852a_bb_reset_en(rtwdev, phy_idx, true); 1402 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en); 1403 } 1404} 1405 1406static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev) 1407{ 1408 struct rtw89_efuse *efuse = &rtwdev->efuse; 1409 1410 switch (efuse->rfe_type) { 1411 case 11: 1412 case 12: 1413 case 17: 1414 case 18: 1415 case 51: 1416 case 53: 1417 rtwdev->fem.epa_2g = true; 1418 rtwdev->fem.elna_2g = true; 1419 fallthrough; 1420 case 9: 1421 case 10: 1422 case 15: 1423 case 16: 1424 rtwdev->fem.epa_5g = true; 1425 rtwdev->fem.elna_5g = true; 1426 break; 1427 default: 1428 break; 1429 } 1430} 1431 1432static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev) 1433{ 1434 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1435 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1436 1437 rtw8852a_rck(rtwdev); 1438 rtw8852a_dack(rtwdev, RTW89_CHANCTX_0); 1439 rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true, RTW89_CHANCTX_0); 1440} 1441 1442static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev, 1443 struct rtw89_vif_link *rtwvif_link) 1444{ 1445 enum rtw89_chanctx_idx chanctx_idx = rtwvif_link->chanctx_idx; 1446 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx; 1447 1448 rtw89_btc_ntfy_conn_rfk(rtwdev, true); 1449 1450 rtw8852a_rx_dck(rtwdev, phy_idx, true, chanctx_idx); 1451 rtw8852a_iqk(rtwdev, phy_idx, chanctx_idx); 1452 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30); 1453 rtw8852a_tssi(rtwdev, phy_idx, chanctx_idx); 1454 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30); 1455 rtw8852a_dpk(rtwdev, phy_idx, chanctx_idx); 1456 1457 rtw89_btc_ntfy_conn_rfk(rtwdev, false); 1458} 1459 1460static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev, 1461 enum rtw89_phy_idx phy_idx, 1462 const struct rtw89_chan *chan) 1463{ 1464 rtw8852a_tssi_scan(rtwdev, phy_idx, chan); 1465} 1466 1467static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, 1468 struct rtw89_vif_link *rtwvif_link, 1469 bool start) 1470{ 1471 rtw8852a_wifi_scan_notify(rtwdev, start, rtwvif_link->phy_idx); 1472} 1473 1474static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev) 1475{ 1476 rtw8852a_dpk_track(rtwdev); 1477 rtw8852a_tssi_track(rtwdev); 1478} 1479 1480static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1481 enum rtw89_phy_idx phy_idx, s16 ref) 1482{ 1483 s8 ofst_int = 0; 1484 u8 base_cw_0db = 0x27; 1485 u16 tssi_16dbm_cw = 0x12c; 1486 s16 pwr_s10_3 = 0; 1487 s16 rf_pwr_cw = 0; 1488 u16 bb_pwr_cw = 0; 1489 u32 pwr_cw = 0; 1490 u32 tssi_ofst_cw = 0; 1491 1492 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1493 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1494 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1495 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1496 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1497 1498 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1499 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1500 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1501 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1502 1503 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1504} 1505 1506static 1507void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1508 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1509{ 1510 s8 val_1t = 0; 1511 s8 val_2t = 0; 1512 u32 reg; 1513 1514 if (pw_ofst < -16 || pw_ofst > 15) { 1515 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n", 1516 pw_ofst); 1517 return; 1518 } 1519 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx); 1520 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); 1521 val_1t = pw_ofst; 1522 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); 1523 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t); 1524 val_2t = max(val_1t - 3, -16); 1525 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); 1526 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t); 1527 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n", 1528 val_1t, val_2t); 1529} 1530 1531static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev, 1532 enum rtw89_phy_idx phy_idx) 1533{ 1534 static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800}; 1535 const u32 mask = 0x7FFFFFF; 1536 const u8 ofst_ofdm = 0x4; 1537 const u8 ofst_cck = 0x8; 1538 s16 ref_ofdm = 0; 1539 s16 ref_cck = 0; 1540 u32 val; 1541 u8 i; 1542 1543 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1544 1545 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1546 GENMASK(27, 10), 0x0); 1547 1548 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1549 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1550 1551 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1552 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1553 phy_idx); 1554 1555 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1556 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1557 1558 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1559 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1560 phy_idx); 1561} 1562 1563static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev, 1564 const struct rtw89_chan *chan, 1565 enum rtw89_phy_idx phy_idx) 1566{ 1567 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 1568 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 1569 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 1570 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 1571} 1572 1573static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 1574 enum rtw89_phy_idx phy_idx) 1575{ 1576 rtw8852a_set_txpwr_ref(rtwdev, phy_idx); 1577} 1578 1579static int 1580rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1581{ 1582 int ret; 1583 1584 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 1585 if (ret) 1586 return ret; 1587 1588 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004); 1589 if (ret) 1590 return ret; 1591 1592 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 1593 if (ret) 1594 return ret; 1595 1596 return 0; 1597} 1598 1599void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev) 1600{ 1601 u8 i = 0; 1602 u32 addr, val; 1603 1604 for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) { 1605 addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr; 1606 val = rtw8852a_pmac_ht20_mcs7_tbl[i].data; 1607 rtw89_phy_write32(rtwdev, addr, val); 1608 } 1609} 1610 1611static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev, 1612 struct rtw8852a_bb_pmac_info *tx_info, 1613 enum rtw89_phy_idx idx) 1614{ 1615 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx"); 1616 if (tx_info->mode == CONT_TX) 1617 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, 1618 idx); 1619 else if (tx_info->mode == PKTS_TX) 1620 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, 1621 idx); 1622} 1623 1624static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev, 1625 struct rtw8852a_bb_pmac_info *tx_info, 1626 enum rtw89_phy_idx idx) 1627{ 1628 enum rtw8852a_pmac_mode mode = tx_info->mode; 1629 u32 pkt_cnt = tx_info->tx_cnt; 1630 u16 period = tx_info->period; 1631 1632 if (mode == CONT_TX && !tx_info->is_cck) { 1633 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, 1634 idx); 1635 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start"); 1636 } else if (mode == PKTS_TX) { 1637 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, 1638 idx); 1639 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, 1640 B_PMAC_TX_PRD_MSK, period, idx); 1641 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK, 1642 pkt_cnt, idx); 1643 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start"); 1644 } 1645 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx); 1646 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx); 1647} 1648 1649void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev, 1650 struct rtw8852a_bb_pmac_info *tx_info, 1651 enum rtw89_phy_idx idx, const struct rtw89_chan *chan) 1652{ 1653 if (!tx_info->en_pmac_tx) { 1654 rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx); 1655 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx); 1656 if (chan->band_type == RTW89_BAND_2G) 1657 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS); 1658 return; 1659 } 1660 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable"); 1661 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx); 1662 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx); 1663 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, 1664 idx); 1665 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx); 1666 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx); 1667 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); 1668 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx); 1669 rtw8852a_start_pmac_tx(rtwdev, tx_info, idx); 1670} 1671 1672void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, 1673 u16 tx_cnt, u16 period, u16 tx_time, 1674 enum rtw89_phy_idx idx, const struct rtw89_chan *chan) 1675{ 1676 struct rtw8852a_bb_pmac_info tx_info = {0}; 1677 1678 tx_info.en_pmac_tx = enable; 1679 tx_info.is_cck = 0; 1680 tx_info.mode = PKTS_TX; 1681 tx_info.tx_cnt = tx_cnt; 1682 tx_info.period = period; 1683 tx_info.tx_time = tx_time; 1684 rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx, chan); 1685} 1686 1687void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, 1688 enum rtw89_phy_idx idx) 1689{ 1690 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm); 1691 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); 1692 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx); 1693} 1694 1695void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) 1696{ 1697 u32 rst_mask0 = 0; 1698 u32 rst_mask1 = 0; 1699 1700 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0); 1701 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1); 1702 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path); 1703 if (!rtwdev->dbcc_en) { 1704 if (tx_path == RF_PATH_A) { 1705 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1706 B_TXPATH_SEL_MSK, 1); 1707 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1708 B_TXNSS_MAP_MSK, 0); 1709 } else if (tx_path == RF_PATH_B) { 1710 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1711 B_TXPATH_SEL_MSK, 2); 1712 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1713 B_TXNSS_MAP_MSK, 0); 1714 } else if (tx_path == RF_PATH_AB) { 1715 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1716 B_TXPATH_SEL_MSK, 3); 1717 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1718 B_TXNSS_MAP_MSK, 4); 1719 } else { 1720 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path"); 1721 } 1722 } else { 1723 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1724 1); 1725 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2, 1726 RTW89_PHY_1); 1727 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 1728 0); 1729 rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4, 1730 RTW89_PHY_1); 1731 } 1732 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 1733 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 1734 if (tx_path == RF_PATH_A) { 1735 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 1736 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 1737 } else { 1738 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 1739 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 1740 } 1741} 1742 1743void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev, 1744 enum rtw89_phy_idx idx, u8 mode) 1745{ 1746 if (mode != 0) 1747 return; 1748 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch"); 1749 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx); 1750 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx); 1751 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx); 1752 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx); 1753 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx); 1754 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx); 1755 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx); 1756} 1757 1758static void rtw8852a_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 1759 enum rtw89_phy_idx phy_idx) 1760{ 1761 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8852a_btc_preagc_en_defs_tbl : 1762 &rtw8852a_btc_preagc_dis_defs_tbl); 1763} 1764 1765static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 1766{ 1767 if (rtwdev->is_tssi_mode[rf_path]) { 1768 u32 addr = 0x1c10 + (rf_path << 13); 1769 1770 return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000); 1771 } 1772 1773 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1774 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 1775 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1776 1777 fsleep(200); 1778 1779 return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 1780} 1781 1782static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev) 1783{ 1784 const struct rtw89_btc_ver *ver = rtwdev->btc.ver; 1785 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; 1786 1787 if (ver->fcxinit == 7) { 1788 md->md_v7.rfe_type = rtwdev->efuse.rfe_type; 1789 md->md_v7.kt_ver = rtwdev->hal.cv; 1790 md->md_v7.bt_solo = 0; 1791 md->md_v7.switch_type = BTC_SWITCH_INTERNAL; 1792 1793 if (md->md_v7.rfe_type > 0) 1794 md->md_v7.ant.num = (md->md_v7.rfe_type % 2 ? 2 : 3); 1795 else 1796 md->md_v7.ant.num = 2; 1797 1798 md->md_v7.ant.diversity = 0; 1799 md->md_v7.ant.isolation = 10; 1800 1801 if (md->md_v7.ant.num == 3) { 1802 md->md_v7.ant.type = BTC_ANT_DEDICATED; 1803 md->md_v7.bt_pos = BTC_BT_ALONE; 1804 } else { 1805 md->md_v7.ant.type = BTC_ANT_SHARED; 1806 md->md_v7.bt_pos = BTC_BT_BTG; 1807 } 1808 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos; 1809 rtwdev->btc.ant_type = md->md_v7.ant.type; 1810 } else { 1811 md->md.rfe_type = rtwdev->efuse.rfe_type; 1812 md->md.cv = rtwdev->hal.cv; 1813 md->md.bt_solo = 0; 1814 md->md.switch_type = BTC_SWITCH_INTERNAL; 1815 1816 if (md->md.rfe_type > 0) 1817 md->md.ant.num = (md->md.rfe_type % 2 ? 2 : 3); 1818 else 1819 md->md.ant.num = 2; 1820 1821 md->md.ant.diversity = 0; 1822 md->md.ant.isolation = 10; 1823 1824 if (md->md.ant.num == 3) { 1825 md->md.ant.type = BTC_ANT_DEDICATED; 1826 md->md.bt_pos = BTC_BT_ALONE; 1827 } else { 1828 md->md.ant.type = BTC_ANT_SHARED; 1829 md->md.bt_pos = BTC_BT_BTG; 1830 } 1831 rtwdev->btc.btg_pos = md->md.ant.btg_pos; 1832 rtwdev->btc.ant_type = md->md.ant.type; 1833 } 1834} 1835 1836static 1837void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 1838{ 1839 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000); 1840 rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group); 1841 rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val); 1842 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0); 1843} 1844 1845static void rtw8852a_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 1846 enum rtw89_phy_idx phy_idx) 1847{ 1848 if (en) { 1849 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1); 1850 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3); 1851 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 1852 } else { 1853 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0); 1854 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0); 1855 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 1856 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 1857 } 1858} 1859 1860static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev) 1861{ 1862 struct rtw89_btc *btc = &rtwdev->btc; 1863 const struct rtw89_chip_info *chip = rtwdev->chip; 1864 const struct rtw89_mac_ax_coex coex_params = { 1865 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 1866 .direction = RTW89_MAC_AX_COEX_INNER, 1867 }; 1868 1869 /* PTA init */ 1870 rtw89_mac_coex_init(rtwdev, &coex_params); 1871 1872 /* set WL Tx response = Hi-Pri */ 1873 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 1874 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 1875 1876 /* set rf gnt debug off */ 1877 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0); 1878 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0); 1879 1880 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 1881 if (btc->ant_type == BTC_ANT_SHARED) { 1882 rtw8852a_set_trx_mask(rtwdev, 1883 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 1884 rtw8852a_set_trx_mask(rtwdev, 1885 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 1886 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 1887 rtw8852a_set_trx_mask(rtwdev, 1888 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 1889 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 1890 rtw8852a_set_trx_mask(rtwdev, 1891 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 1892 rtw8852a_set_trx_mask(rtwdev, 1893 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 1894 } 1895 1896 /* set PTA break table */ 1897 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); 1898 1899 /* enable BT counter 0xda40[16,2] = 2b'11 */ 1900 rtw89_write32_set(rtwdev, 1901 R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); 1902 btc->cx.wl.status.map.init_ok = true; 1903} 1904 1905static 1906void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 1907{ 1908 u32 bitmap = 0; 1909 u32 reg = 0; 1910 1911 switch (map) { 1912 case BTC_PRI_MASK_TX_RESP: 1913 reg = R_BTC_BT_COEX_MSK_TABLE; 1914 bitmap = B_BTC_PRI_MASK_TX_RESP_V1; 1915 break; 1916 case BTC_PRI_MASK_BEACON: 1917 reg = R_AX_WL_PRI_MSK; 1918 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; 1919 break; 1920 default: 1921 return; 1922 } 1923 1924 if (state) 1925 rtw89_write32_set(rtwdev, reg, bitmap); 1926 else 1927 rtw89_write32_clr(rtwdev, reg, bitmap); 1928} 1929 1930static inline u32 __btc_ctrl_val_all_time(u32 ctrl) 1931{ 1932 return FIELD_GET(GENMASK(15, 0), ctrl); 1933} 1934 1935static inline u32 __btc_ctrl_rst_all_time(u32 cur) 1936{ 1937 return cur & ~B_AX_FORCE_PWR_BY_RATE_EN; 1938} 1939 1940static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val) 1941{ 1942 u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1943 u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1944 1945 return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN; 1946} 1947 1948static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl) 1949{ 1950 return FIELD_GET(GENMASK(31, 16), ctrl); 1951} 1952 1953static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur) 1954{ 1955 return cur & ~B_AX_TXAGC_BT_EN; 1956} 1957 1958static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val) 1959{ 1960 u32 ov = cur & ~B_AX_TXAGC_BT_MASK; 1961 u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val); 1962 1963 return ov | iv | B_AX_TXAGC_BT_EN; 1964} 1965 1966static void 1967rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 1968{ 1969 const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL; 1970 const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL; 1971 1972#define __do_clr(_chk) ((_chk) == GENMASK(15, 0)) 1973#define __handle(_case) \ 1974 do { \ 1975 const u32 _reg = __btc_cr_ ## _case; \ 1976 u32 _val = __btc_ctrl_val_ ## _case(txpwr_val); \ 1977 u32 _cur, _wrt; \ 1978 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1979 "btc ctrl %s: 0x%x\n", #_case, _val); \ 1980 if (rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur))\ 1981 break; \ 1982 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1983 "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur); \ 1984 _wrt = __do_clr(_val) ? \ 1985 __btc_ctrl_rst_ ## _case(_cur) : \ 1986 __btc_ctrl_gen_ ## _case(_cur, _val); \ 1987 rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\ 1988 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1989 "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt); \ 1990 } while (0) 1991 1992 __handle(all_time); 1993 __handle(gnt_bt); 1994 1995#undef __handle 1996#undef __do_clr 1997} 1998 1999static 2000s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 2001{ 2002 /* +6 for compensate offset */ 2003 return clamp_t(s8, val + 6, -100, 0) + 100; 2004} 2005 2006static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = { 2007 {255, 0, 0, 7}, /* 0 -> original */ 2008 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 2009 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2010 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2011 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2012 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2013 {6, 1, 0, 7}, 2014 {13, 1, 0, 7}, 2015 {13, 1, 0, 7} 2016}; 2017 2018static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = { 2019 {255, 0, 0, 7}, /* 0 -> original */ 2020 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 2021 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2022 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2023 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2024 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2025 {255, 1, 0, 7}, 2026 {255, 1, 0, 7}, 2027 {255, 1, 0, 7} 2028}; 2029 2030static const 2031u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 2032static const 2033u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 2034 2035static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = { 2036 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 2037 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), 2038 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), 2039 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 2040 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 2041 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), 2042 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), 2043 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 2044 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), 2045 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), 2046 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 2047 RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178), 2048}; 2049 2050static 2051void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 2052{ 2053 struct rtw89_btc *btc = &rtwdev->btc; 2054 const struct rtw89_btc_ver *ver = btc->ver; 2055 struct rtw89_btc_cx *cx = &btc->cx; 2056 u32 val; 2057 2058 if (ver->fcxbtcrpt != 1) 2059 return; 2060 2061 val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH); 2062 cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val); 2063 cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val); 2064 2065 val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW); 2066 cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val); 2067 cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val); 2068 2069 /* clock-gate off before reset counter*/ 2070 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 2071 rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 2072 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 2073 rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 2074} 2075 2076static 2077void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 2078{ 2079 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 2080 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2081 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1); 2082 2083 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 2084 if (state) 2085 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2086 RFREG_MASK, 0xa2d7c); 2087 else 2088 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2089 RFREG_MASK, 0xa2020); 2090 2091 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2092} 2093 2094static void rtw8852a_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 2095{ 2096 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB 2097 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB 2098 * To improve BT ACI in co-rx 2099 */ 2100 2101 switch (level) { 2102 case 0: /* default */ 2103 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2104 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2105 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2106 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2107 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2108 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2109 break; 2110 case 1: /* Fix LNA2=5 */ 2111 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2112 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2113 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2114 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2115 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2116 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2117 break; 2118 } 2119} 2120 2121static void rtw8852a_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2122{ 2123 struct rtw89_btc *btc = &rtwdev->btc; 2124 2125 switch (level) { 2126 case 0: /* original */ 2127 default: 2128 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2129 btc->dm.wl_lna2 = 0; 2130 break; 2131 case 1: /* for FDD free-run */ 2132 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0); 2133 btc->dm.wl_lna2 = 0; 2134 break; 2135 case 2: /* for BTG Co-Rx*/ 2136 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2137 btc->dm.wl_lna2 = 1; 2138 break; 2139 } 2140 2141 rtw8852a_set_wl_lna2(rtwdev, btc->dm.wl_lna2); 2142} 2143 2144static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2145 struct rtw89_rx_phy_ppdu *phy_ppdu, 2146 struct ieee80211_rx_status *status) 2147{ 2148 u16 chan = phy_ppdu->chan_idx; 2149 u8 band; 2150 2151 if (chan == 0) 2152 return; 2153 2154 band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 2155 status->freq = ieee80211_channel_to_frequency(chan, band); 2156 status->band = band; 2157} 2158 2159static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev, 2160 struct rtw89_rx_phy_ppdu *phy_ppdu, 2161 struct ieee80211_rx_status *status) 2162{ 2163 u8 path; 2164 u8 *rx_power = phy_ppdu->rssi; 2165 u8 raw; 2166 2167 if (!status->signal) { 2168 if (phy_ppdu->to_self) 2169 raw = ewma_rssi_read(&rtwdev->phystat.bcn_rssi); 2170 else 2171 raw = max(rx_power[RF_PATH_A], rx_power[RF_PATH_B]); 2172 2173 status->signal = RTW89_RSSI_RAW_TO_DBM(raw); 2174 } 2175 2176 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2177 status->chains |= BIT(path); 2178 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2179 } 2180 if (phy_ppdu->valid) 2181 rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2182} 2183 2184#ifdef CONFIG_PM 2185static const struct wiphy_wowlan_support rtw_wowlan_stub_8852a = { 2186 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 2187 .n_patterns = RTW89_MAX_PATTERN_NUM, 2188 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 2189 .pattern_min_len = 1, 2190}; 2191#endif 2192 2193static const struct rtw89_chip_ops rtw8852a_chip_ops = { 2194 .enable_bb_rf = rtw89_mac_enable_bb_rf, 2195 .disable_bb_rf = rtw89_mac_disable_bb_rf, 2196 .bb_preinit = NULL, 2197 .bb_postinit = NULL, 2198 .bb_reset = rtw8852a_bb_reset, 2199 .bb_sethw = rtw8852a_bb_sethw, 2200 .read_rf = rtw89_phy_read_rf, 2201 .write_rf = rtw89_phy_write_rf, 2202 .set_channel = rtw8852a_set_channel, 2203 .set_channel_help = rtw8852a_set_channel_help, 2204 .read_efuse = rtw8852a_read_efuse, 2205 .read_phycap = rtw8852a_read_phycap, 2206 .fem_setup = rtw8852a_fem_setup, 2207 .rfe_gpio = NULL, 2208 .rfk_hw_init = NULL, 2209 .rfk_init = rtw8852a_rfk_init, 2210 .rfk_init_late = NULL, 2211 .rfk_channel = rtw8852a_rfk_channel, 2212 .rfk_band_changed = rtw8852a_rfk_band_changed, 2213 .rfk_scan = rtw8852a_rfk_scan, 2214 .rfk_track = rtw8852a_rfk_track, 2215 .power_trim = rtw8852a_power_trim, 2216 .set_txpwr = rtw8852a_set_txpwr, 2217 .set_txpwr_ctrl = rtw8852a_set_txpwr_ctrl, 2218 .init_txpwr_unit = rtw8852a_init_txpwr_unit, 2219 .get_thermal = rtw8852a_get_thermal, 2220 .chan_to_rf18_val = NULL, 2221 .ctrl_btg_bt_rx = rtw8852a_ctrl_btg_bt_rx, 2222 .query_ppdu = rtw8852a_query_ppdu, 2223 .convert_rpl_to_rssi = NULL, 2224 .phy_rpt_to_rssi = NULL, 2225 .ctrl_nbtg_bt_tx = rtw8852a_ctrl_nbtg_bt_tx, 2226 .cfg_txrx_path = NULL, 2227 .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset, 2228 .digital_pwr_comp = NULL, 2229 .pwr_on_func = NULL, 2230 .pwr_off_func = NULL, 2231 .query_rxdesc = rtw89_core_query_rxdesc, 2232 .fill_txdesc = rtw89_core_fill_txdesc, 2233 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 2234 .get_ch_dma = {rtw89_core_get_ch_dma, 2235 rtw89_core_get_ch_dma_v2, 2236 NULL,}, 2237 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 2238 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 2239 .stop_sch_tx = rtw89_mac_stop_sch_tx, 2240 .resume_sch_tx = rtw89_mac_resume_sch_tx, 2241 .h2c_dctl_sec_cam = NULL, 2242 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl, 2243 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl, 2244 .h2c_ampdu_cmac_tbl = NULL, 2245 .h2c_txtime_cmac_tbl = rtw89_fw_h2c_txtime_cmac_tbl, 2246 .h2c_punctured_cmac_tbl = NULL, 2247 .h2c_default_dmac_tbl = NULL, 2248 .h2c_update_beacon = rtw89_fw_h2c_update_beacon, 2249 .h2c_ba_cam = rtw89_fw_h2c_ba_cam, 2250 2251 .btc_set_rfe = rtw8852a_btc_set_rfe, 2252 .btc_init_cfg = rtw8852a_btc_init_cfg, 2253 .btc_set_wl_pri = rtw8852a_btc_set_wl_pri, 2254 .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl, 2255 .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi, 2256 .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt, 2257 .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby, 2258 .btc_set_wl_rx_gain = rtw8852a_btc_set_wl_rx_gain, 2259 .btc_set_policy = rtw89_btc_set_policy, 2260}; 2261 2262const struct rtw89_chip_info rtw8852a_chip_info = { 2263 .chip_id = RTL8852A, 2264 .chip_gen = RTW89_CHIP_AX, 2265 .ops = &rtw8852a_chip_ops, 2266 .mac_def = &rtw89_mac_gen_ax, 2267 .phy_def = &rtw89_phy_gen_ax, 2268 .fw_basename = RTW8852A_FW_BASENAME, 2269 .fw_format_max = RTW8852A_FW_FORMAT_MAX, 2270 .try_ce_fw = false, 2271 .bbmcu_nr = 0, 2272 .needed_fw_elms = 0, 2273 .fw_blacklist = NULL, 2274 .fifo_size = 458752, 2275 .small_fifo_size = false, 2276 .dle_scc_rsvd_size = 0, 2277 .max_amsdu_limit = 3500, 2278 .dis_2g_40m_ul_ofdma = true, 2279 .rsvd_ple_ofst = 0x6f800, 2280 .hfc_param_ini = {rtw8852a_hfc_param_ini_pcie, 2281 rtw8852a_hfc_param_ini_usb, 2282 NULL}, 2283 .dle_mem = {rtw8852a_dle_mem_pcie, 2284 rtw8852a_dle_mem_usb, 2285 rtw8852a_dle_mem_usb, 2286 NULL}, 2287 .wde_qempty_acq_grpnum = 16, 2288 .wde_qempty_mgq_grpsel = 16, 2289 .rf_base_addr = {0xc000, 0xd000}, 2290 .thermal_th = {0x32, 0x35}, 2291 .pwr_on_seq = pwr_on_seq_8852a, 2292 .pwr_off_seq = pwr_off_seq_8852a, 2293 .bb_table = &rtw89_8852a_phy_bb_table, 2294 .bb_gain_table = NULL, 2295 .rf_table = {&rtw89_8852a_phy_radioa_table, 2296 &rtw89_8852a_phy_radiob_table,}, 2297 .nctl_table = &rtw89_8852a_phy_nctl_table, 2298 .nctl_post_table = NULL, 2299 .dflt_parms = &rtw89_8852a_dflt_parms, 2300 .rfe_parms_conf = NULL, 2301 .txpwr_factor_bb = 3, 2302 .txpwr_factor_rf = 2, 2303 .txpwr_factor_mac = 1, 2304 .dig_table = &rtw89_8852a_phy_dig_table, 2305 .dig_regs = &rtw8852a_dig_regs, 2306 .tssi_dbw_table = NULL, 2307 .support_macid_num = RTW89_MAX_MAC_ID_NUM, 2308 .support_link_num = 0, 2309 .support_chanctx_num = 1, 2310 .support_rnr = false, 2311 .support_bands = BIT(NL80211_BAND_2GHZ) | 2312 BIT(NL80211_BAND_5GHZ), 2313 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) | 2314 BIT(NL80211_CHAN_WIDTH_40) | 2315 BIT(NL80211_CHAN_WIDTH_80), 2316 .support_unii4 = false, 2317 .support_ant_gain = false, 2318 .support_tas = false, 2319 .support_sar_by_ant = false, 2320 .support_noise = true, 2321 .ul_tb_waveform_ctrl = false, 2322 .ul_tb_pwr_diff = false, 2323 .rx_freq_frome_ie = true, 2324 .hw_sec_hdr = false, 2325 .hw_mgmt_tx_encrypt = false, 2326 .hw_tkip_crypto = false, 2327 .hw_mlo_bmc_crypto = false, 2328 .rf_path_num = 2, 2329 .tx_nss = 2, 2330 .rx_nss = 2, 2331 .acam_num = 128, 2332 .bcam_num = 10, 2333 .scam_num = 128, 2334 .bacam_num = 2, 2335 .bacam_dynamic_num = 4, 2336 .bacam_ver = RTW89_BACAM_V0, 2337 .addrcam_ver = 0, 2338 .ppdu_max_usr = 4, 2339 .sec_ctrl_efuse_size = 4, 2340 .physical_efuse_size = 1216, 2341 .logical_efuse_size = 1536, 2342 .limit_efuse_size = 1152, 2343 .dav_phy_efuse_size = 0, 2344 .dav_log_efuse_size = 0, 2345 .efuse_blocks = NULL, 2346 .phycap_addr = 0x580, 2347 .phycap_size = 128, 2348 .para_ver = 0x0, 2349 .wlcx_desired = 0x06000000, 2350 .scbd = 0x1, 2351 .mailbox = 0x1, 2352 2353 .afh_guard_ch = 6, 2354 .wl_rssi_thres = rtw89_btc_8852a_wl_rssi_thres, 2355 .bt_rssi_thres = rtw89_btc_8852a_bt_rssi_thres, 2356 .rssi_tol = 2, 2357 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852a_mon_reg), 2358 .mon_reg = rtw89_btc_8852a_mon_reg, 2359 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_ul), 2360 .rf_para_ulink = rtw89_btc_8852a_rf_ul, 2361 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_dl), 2362 .rf_para_dlink = rtw89_btc_8852a_rf_dl, 2363 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2364 BIT(RTW89_PS_MODE_CLK_GATED) | 2365 BIT(RTW89_PS_MODE_PWR_GATED), 2366 .low_power_hci_modes = 0, 2367 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD, 2368 .hci_func_en_addr = R_AX_HCI_FUNC_EN, 2369 .h2c_desc_size = sizeof(struct rtw89_txwd_body), 2370 .txwd_body_size = sizeof(struct rtw89_txwd_body), 2371 .txwd_info_size = sizeof(struct rtw89_txwd_info), 2372 .h2c_ctrl_reg = R_AX_H2CREG_CTRL, 2373 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 2374 .h2c_regs = rtw8852a_h2c_regs, 2375 .c2h_ctrl_reg = R_AX_C2HREG_CTRL, 2376 .c2h_regs = rtw8852a_c2h_regs, 2377 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 2378 .page_regs = &rtw8852a_page_regs, 2379 .wow_reason_reg = rtw8852a_wow_wakeup_regs, 2380 .cfo_src_fd = false, 2381 .cfo_hw_comp = false, 2382 .dcfo_comp = &rtw8852a_dcfo_comp, 2383 .dcfo_comp_sft = 10, 2384 .nhm_report = &rtw8852a_nhm_rpt, 2385 .nhm_th = &rtw8852a_nhm_th, 2386 .imr_info = &rtw8852a_imr_info, 2387 .imr_dmac_table = NULL, 2388 .imr_cmac_table = NULL, 2389 .rrsr_cfgs = &rtw8852a_rrsr_cfgs, 2390 .bss_clr_vld = {R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0}, 2391 .bss_clr_map_reg = R_BSS_CLR_MAP, 2392 .rfkill_init = &rtw8852a_rfkill_regs, 2393 .rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9}, 2394 .dma_ch_mask = 0, 2395 .edcca_regs = &rtw8852a_edcca_regs, 2396#ifdef CONFIG_PM 2397 .wowlan_stub = &rtw_wowlan_stub_8852a, 2398#endif 2399 .xtal_info = &rtw8852a_xtal_info, 2400}; 2401EXPORT_SYMBOL(rtw8852a_chip_info); 2402 2403MODULE_FIRMWARE(RTW8852A_MODULE_FIRMWARE); 2404MODULE_AUTHOR("Realtek Corporation"); 2405MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852A driver"); 2406MODULE_LICENSE("Dual BSD/GPL");
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