FILE
rtw8851b.c
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linux-6.19.14/drivers/net/wireless/realtek/rtw89/rtw8851b.c
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* Copyright(c) 2022-2023 Realtek Corporation 3 */ 4 5#include "coex.h" 6#include "efuse.h" 7#include "fw.h" 8#include "mac.h" 9#include "phy.h" 10#include "reg.h" 11#include "rtw8851b.h" 12#include "rtw8851b_rfk.h" 13#include "rtw8851b_rfk_table.h" 14#include "rtw8851b_table.h" 15#include "txrx.h" 16#include "util.h" 17 18#define RTW8851B_FW_FORMAT_MAX 0 19#define RTW8851B_FW_BASENAME "rtw89/rtw8851b_fw" 20#define RTW8851B_MODULE_FIRMWARE \ 21 RTW8851B_FW_BASENAME ".bin" 22 23static const struct rtw89_hfc_ch_cfg rtw8851b_hfc_chcfg_pcie[] = { 24 {5, 343, grp_0}, /* ACH 0 */ 25 {5, 343, grp_0}, /* ACH 1 */ 26 {5, 343, grp_0}, /* ACH 2 */ 27 {5, 343, grp_0}, /* ACH 3 */ 28 {0, 0, grp_0}, /* ACH 4 */ 29 {0, 0, grp_0}, /* ACH 5 */ 30 {0, 0, grp_0}, /* ACH 6 */ 31 {0, 0, grp_0}, /* ACH 7 */ 32 {4, 344, grp_0}, /* B0MGQ */ 33 {4, 344, grp_0}, /* B0HIQ */ 34 {0, 0, grp_0}, /* B1MGQ */ 35 {0, 0, grp_0}, /* B1HIQ */ 36 {40, 0, 0} /* FWCMDQ */ 37}; 38 39static const struct rtw89_hfc_pub_cfg rtw8851b_hfc_pubcfg_pcie = { 40 448, /* Group 0 */ 41 0, /* Group 1 */ 42 448, /* Public Max */ 43 0 /* WP threshold */ 44}; 45 46static const struct rtw89_hfc_param_ini rtw8851b_hfc_param_ini_pcie[] = { 47 [RTW89_QTA_SCC] = {rtw8851b_hfc_chcfg_pcie, &rtw8851b_hfc_pubcfg_pcie, 48 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 49 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 50 RTW89_HCIFC_POH}, 51 [RTW89_QTA_INVALID] = {NULL}, 52}; 53 54static const struct rtw89_hfc_ch_cfg rtw8851b_hfc_chcfg_usb[] = { 55 {18, 152, grp_0}, /* ACH 0 */ 56 {18, 152, grp_0}, /* ACH 1 */ 57 {18, 152, grp_0}, /* ACH 2 */ 58 {18, 152, grp_0}, /* ACH 3 */ 59 {0, 0, grp_0}, /* ACH 4 */ 60 {0, 0, grp_0}, /* ACH 5 */ 61 {0, 0, grp_0}, /* ACH 6 */ 62 {0, 0, grp_0}, /* ACH 7 */ 63 {18, 152, grp_0}, /* B0MGQ */ 64 {18, 152, grp_0}, /* B0HIQ */ 65 {0, 0, grp_0}, /* B1MGQ */ 66 {0, 0, grp_0}, /* B1HIQ */ 67 {0, 0, 0} /* FWCMDQ */ 68}; 69 70static const struct rtw89_hfc_pub_cfg rtw8851b_hfc_pubcfg_usb = { 71 152, /* Group 0 */ 72 0, /* Group 1 */ 73 152, /* Public Max */ 74 0 /* WP threshold */ 75}; 76 77static const struct rtw89_hfc_prec_cfg rtw8851b_hfc_preccfg_usb = { 78 9, /* CH 0-11 pre-cost */ 79 32, /* H2C pre-cost */ 80 64, /* WP CH 0-7 pre-cost */ 81 24, /* WP CH 8-11 pre-cost */ 82 1, /* CH 0-11 full condition */ 83 1, /* H2C full condition */ 84 1, /* WP CH 0-7 full condition */ 85 1, /* WP CH 8-11 full condition */ 86}; 87 88static const struct rtw89_hfc_param_ini rtw8851b_hfc_param_ini_usb[] = { 89 [RTW89_QTA_SCC] = {rtw8851b_hfc_chcfg_usb, &rtw8851b_hfc_pubcfg_usb, 90 &rtw8851b_hfc_preccfg_usb, RTW89_HCIFC_STF}, 91 [RTW89_QTA_DLFW] = {NULL, NULL, 92 &rtw8851b_hfc_preccfg_usb, RTW89_HCIFC_STF}, 93 [RTW89_QTA_INVALID] = {NULL}, 94}; 95 96static const struct rtw89_dle_mem rtw8851b_dle_mem_pcie[] = { 97 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size6, 98 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6, 99 &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18, 100 &rtw89_mac_size.ple_qt58}, 101 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size6, 102 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6, 103 &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18, 104 &rtw89_mac_size.ple_qt_51b_wow}, 105 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9, 106 &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4, 107 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 108 &rtw89_mac_size.ple_qt13}, 109 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 110 NULL}, 111}; 112 113static const struct rtw89_dle_mem rtw8851b_dle_mem_usb2[] = { 114 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size25, 115 &rtw89_mac_size.ple_size32, &rtw89_mac_size.wde_qt25, 116 &rtw89_mac_size.wde_qt25, &rtw89_mac_size.ple_qt72, 117 &rtw89_mac_size.ple_qt73}, 118 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9, 119 &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4, 120 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 121 &rtw89_mac_size.ple_qt13}, 122 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 123 NULL}, 124}; 125 126static const struct rtw89_dle_mem rtw8851b_dle_mem_usb3[] = { 127 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size25, 128 &rtw89_mac_size.ple_size33, &rtw89_mac_size.wde_qt25, 129 &rtw89_mac_size.wde_qt25, &rtw89_mac_size.ple_qt74, 130 &rtw89_mac_size.ple_qt75}, 131 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9, 132 &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4, 133 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 134 &rtw89_mac_size.ple_qt13}, 135 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 136 NULL}, 137}; 138 139static const struct rtw89_reg3_def rtw8851b_btc_preagc_en_defs[] = { 140 {0x46D0, GENMASK(1, 0), 0x3}, 141 {0x4AD4, GENMASK(31, 0), 0xf}, 142 {0x4688, GENMASK(23, 16), 0x80}, 143 {0x4688, GENMASK(31, 24), 0x80}, 144 {0x4694, GENMASK(7, 0), 0x80}, 145 {0x4694, GENMASK(15, 8), 0x80}, 146 {0x4AE4, GENMASK(11, 6), 0x34}, 147 {0x4AE4, GENMASK(17, 12), 0x0}, 148 {0x469C, GENMASK(31, 26), 0x34}, 149}; 150 151static DECLARE_PHY_REG3_TBL(rtw8851b_btc_preagc_en_defs); 152 153static const struct rtw89_reg3_def rtw8851b_btc_preagc_dis_defs[] = { 154 {0x46D0, GENMASK(1, 0), 0x0}, 155 {0x4AD4, GENMASK(31, 0), 0x60}, 156 {0x4688, GENMASK(23, 16), 0x10}, 157 {0x4690, GENMASK(31, 24), 0x2a}, 158 {0x4694, GENMASK(15, 8), 0x2a}, 159 {0x4AE4, GENMASK(11, 6), 0x26}, 160 {0x4AE4, GENMASK(17, 12), 0x1e}, 161 {0x469C, GENMASK(31, 26), 0x26}, 162}; 163 164static DECLARE_PHY_REG3_TBL(rtw8851b_btc_preagc_dis_defs); 165 166static const u32 rtw8851b_h2c_regs[RTW89_H2CREG_MAX] = { 167 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2, 168 R_AX_H2CREG_DATA3 169}; 170 171static const u32 rtw8851b_c2h_regs[RTW89_C2HREG_MAX] = { 172 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2, 173 R_AX_C2HREG_DATA3 174}; 175 176static const u32 rtw8851b_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = { 177 R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3, 178}; 179 180static const struct rtw89_page_regs rtw8851b_page_regs = { 181 .hci_fc_ctrl = R_AX_HCI_FC_CTRL, 182 .ch_page_ctrl = R_AX_CH_PAGE_CTRL, 183 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL, 184 .ach_page_info = R_AX_ACH0_PAGE_INFO, 185 .pub_page_info3 = R_AX_PUB_PAGE_INFO3, 186 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1, 187 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2, 188 .pub_page_info1 = R_AX_PUB_PAGE_INFO1, 189 .pub_page_info2 = R_AX_PUB_PAGE_INFO2, 190 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1, 191 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2, 192 .wp_page_info1 = R_AX_WP_PAGE_INFO1, 193}; 194 195static const struct rtw89_reg_def rtw8851b_dcfo_comp = { 196 R_DCFO_COMP_S0_V2, B_DCFO_COMP_S0_MSK_V2 197}; 198 199static const struct rtw89_imr_info rtw8851b_imr_info = { 200 .wdrls_imr_set = B_AX_WDRLS_IMR_SET, 201 .wsec_imr_reg = R_AX_SEC_DEBUG, 202 .wsec_imr_set = B_AX_IMR_ERROR, 203 .mpdu_tx_imr_set = 0, 204 .mpdu_rx_imr_set = 0, 205 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 206 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR, 207 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR, 208 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET, 209 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1, 210 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR, 211 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET, 212 .wde_imr_clr = B_AX_WDE_IMR_CLR, 213 .wde_imr_set = B_AX_WDE_IMR_SET, 214 .ple_imr_clr = B_AX_PLE_IMR_CLR, 215 .ple_imr_set = B_AX_PLE_IMR_SET, 216 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR, 217 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET, 218 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR, 219 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET, 220 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR, 221 .other_disp_imr_set = 0, 222 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR, 223 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR, 224 .bbrpt_err_imr_set = 0, 225 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR, 226 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL, 227 .ptcl_imr_set = B_AX_PTCL_IMR_SET, 228 .cdma_imr_0_reg = R_AX_DLE_CTRL, 229 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR, 230 .cdma_imr_0_set = B_AX_DLE_IMR_SET, 231 .cdma_imr_1_reg = 0, 232 .cdma_imr_1_clr = 0, 233 .cdma_imr_1_set = 0, 234 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR, 235 .phy_intf_imr_clr = 0, 236 .phy_intf_imr_set = 0, 237 .rmac_imr_reg = R_AX_RMAC_ERR_ISR, 238 .rmac_imr_clr = B_AX_RMAC_IMR_CLR, 239 .rmac_imr_set = B_AX_RMAC_IMR_SET, 240 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR, 241 .tmac_imr_clr = B_AX_TMAC_IMR_CLR, 242 .tmac_imr_set = B_AX_TMAC_IMR_SET, 243}; 244 245static const struct rtw89_xtal_info rtw8851b_xtal_info = { 246 .xcap_reg = R_AX_XTAL_ON_CTRL3, 247 .sc_xo_mask = B_AX_XTAL_SC_XO_A_BLOCK_MASK, 248 .sc_xi_mask = B_AX_XTAL_SC_XI_A_BLOCK_MASK, 249}; 250 251static const struct rtw89_rrsr_cfgs rtw8851b_rrsr_cfgs = { 252 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 253 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2}, 254}; 255 256static const struct rtw89_rfkill_regs rtw8851b_rfkill_regs = { 257 .pinmux = {R_AX_GPIO8_15_FUNC_SEL, 258 B_AX_PINMUX_GPIO9_FUNC_SEL_MASK, 259 0xf}, 260 .mode = {R_AX_GPIO_EXT_CTRL + 2, 261 (B_AX_GPIO_MOD_9 | B_AX_GPIO_IO_SEL_9) >> 16, 262 0x0}, 263}; 264 265static const struct rtw89_dig_regs rtw8851b_dig_regs = { 266 .seg0_pd_reg = R_SEG0R_PD_V1, 267 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 268 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1, 269 .bmode_pd_reg = R_BMODE_PDTH_EN_V1, 270 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, 271 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, 272 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, 273 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, 274 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, 275 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, 276 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1}, 277 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1}, 278 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1}, 279 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2, 280 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 281 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2, 282 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 283 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2, 284 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 285 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2, 286 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 287}; 288 289static const struct rtw89_edcca_regs rtw8851b_edcca_regs = { 290 .edcca_level = R_SEG0R_EDCCA_LVL_V1, 291 .edcca_mask = B_EDCCA_LVL_MSK0, 292 .edcca_p_mask = B_EDCCA_LVL_MSK1, 293 .ppdu_level = R_SEG0R_EDCCA_LVL_V1, 294 .ppdu_mask = B_EDCCA_LVL_MSK3, 295 .p = {{ 296 .rpt_a = R_EDCCA_RPT_A, 297 .rpt_b = R_EDCCA_RPT_B, 298 .rpt_sel = R_EDCCA_RPT_SEL, 299 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK, 300 }, { 301 .rpt_a = R_EDCCA_RPT_P1_A, 302 .rpt_b = R_EDCCA_RPT_P1_B, 303 .rpt_sel = R_EDCCA_RPT_SEL, 304 .rpt_sel_mask = B_EDCCA_RPT_SEL_P1_MSK, 305 }}, 306 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST, 307 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M, 308}; 309 310static const struct rtw89_btc_rf_trx_para rtw89_btc_8851b_rf_ul[] = { 311 {255, 0, 0, 7}, /* 0 -> original */ 312 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 313 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 314 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 315 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 316 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 317 {6, 1, 0, 7}, 318 {13, 1, 0, 7}, 319 {13, 1, 0, 7} 320}; 321 322static const struct rtw89_btc_rf_trx_para rtw89_btc_8851b_rf_dl[] = { 323 {255, 0, 0, 7}, /* 0 -> original */ 324 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 325 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 326 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 327 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 328 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 329 {255, 1, 0, 7}, 330 {255, 1, 0, 7}, 331 {255, 1, 0, 7} 332}; 333 334static const struct rtw89_btc_fbtc_mreg rtw89_btc_8851b_mon_reg[] = { 335 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 336 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), 337 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), 338 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 339 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 340 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), 341 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), 342 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 343 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), 344 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), 345 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200), 346 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220), 347 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 348 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4738), 349 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4688), 350 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4694), 351}; 352 353static const u8 rtw89_btc_8851b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40}; 354static const u8 rtw89_btc_8851b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20}; 355 356static int rtw8851b_pwr_on_func(struct rtw89_dev *rtwdev) 357{ 358 u32 val32; 359 u8 val8; 360 int ret; 361 362 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN | 363 B_AX_AFSM_PCIE_SUS_EN); 364 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC); 365 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC); 366 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN); 367 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 368 369 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR, 370 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 371 if (ret) 372 return ret; 373 374 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 375 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 376 377 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC), 378 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 379 if (ret) 380 return ret; 381 382 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 383 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 384 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 385 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 386 387 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 388 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) 389 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1); 390 391 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI, 392 XTAL_SI_OFF_WEI); 393 if (ret) 394 return ret; 395 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI, 396 XTAL_SI_OFF_EI); 397 if (ret) 398 return ret; 399 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF); 400 if (ret) 401 return ret; 402 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI, 403 XTAL_SI_PON_WEI); 404 if (ret) 405 return ret; 406 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI, 407 XTAL_SI_PON_EI); 408 if (ret) 409 return ret; 410 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC); 411 if (ret) 412 return ret; 413 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS); 414 if (ret) 415 return ret; 416 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS); 417 if (ret) 418 return ret; 419 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP); 420 if (ret) 421 return ret; 422 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_DRV, 0, XTAL_SI_DRV_LATCH); 423 if (ret) 424 return ret; 425 426 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 427 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE); 428 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15); 429 430 fsleep(1000); 431 432 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14); 433 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 434 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) 435 rtw89_write32_set(rtwdev, R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN, 436 B_AX_GPIO10_PULL_LOW_EN | B_AX_GPIO16_PULL_LOW_EN_V1); 437 438 if (rtwdev->hal.cv == CHIP_CAV) { 439 ret = rtw89_read_efuse_ver(rtwdev, &val8); 440 if (!ret) 441 rtwdev->hal.cv = val8; 442 } 443 444 rtw89_write32_clr(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG, 445 B_AX_XTAL_SI_ADDR_NOT_CHK); 446 if (rtwdev->hal.cv != CHIP_CAV) { 447 rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY); 448 rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY); 449 } 450 451 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 452 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN | 453 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN | 454 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN | 455 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN | 456 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN | 457 B_AX_DMACREG_GCKEN); 458 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN, 459 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 460 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | 461 B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN | 462 B_AX_RMAC_EN); 463 464 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK, 465 PINMUX_EESK_FUNC_SEL_BT_LOG); 466 467 return 0; 468} 469 470static void rtw8851b_patch_swr_pfm2pwm(struct rtw89_dev *rtwdev) 471{ 472 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_PWMM_DSWR); 473 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_ASWRM); 474 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_DSWRM); 475 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_ASWRM); 476} 477 478static int rtw8851b_pwr_off_func(struct rtw89_dev *rtwdev) 479{ 480 u32 val32; 481 int ret; 482 483 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF, 484 XTAL_SI_RFC2RF); 485 if (ret) 486 return ret; 487 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI); 488 if (ret) 489 return ret; 490 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI); 491 if (ret) 492 return ret; 493 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00); 494 if (ret) 495 return ret; 496 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC, 497 XTAL_SI_SRAM2RFC); 498 if (ret) 499 return ret; 500 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI); 501 if (ret) 502 return ret; 503 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI); 504 if (ret) 505 return ret; 506 507 rtw89_write32_set(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG, 508 B_AX_XTAL_SI_ADDR_NOT_CHK); 509 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 510 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 511 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB); 512 513 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC); 514 515 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC), 516 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 517 if (ret) 518 return ret; 519 520 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) 521 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION); 522 else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) 523 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_EDSWR); 524 525 if (rtwdev->hal.cv == CHIP_CAV) { 526 rtw8851b_patch_swr_pfm2pwm(rtwdev); 527 } else { 528 rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY); 529 rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY); 530 } 531 532 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 533 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 534 } else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) { 535 val32 = rtw89_read32(rtwdev, R_AX_SYS_PW_CTRL); 536 val32 &= ~B_AX_AFSM_PCIE_SUS_EN; 537 val32 |= B_AX_AFSM_WLSUS_EN; 538 rtw89_write32(rtwdev, R_AX_SYS_PW_CTRL, val32); 539 } 540 541 return 0; 542} 543 544static void rtw8851b_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 545 struct rtw8851b_efuse *map) 546{ 547 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 548 struct rtw8851b_tssi_offset *ofst[] = {&map->path_a_tssi}; 549 u8 i, j; 550 551 tssi->thermal[RF_PATH_A] = map->path_a_therm; 552 553 for (i = 0; i < RF_PATH_NUM_8851B; i++) { 554 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 555 sizeof(ofst[i]->cck_tssi)); 556 557 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 558 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 559 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 560 i, j, tssi->tssi_cck[i][j]); 561 562 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 563 sizeof(ofst[i]->bw40_tssi)); 564 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 565 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 566 567 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 568 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 569 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 570 i, j, tssi->tssi_mcs[i][j]); 571 } 572} 573 574static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low) 575{ 576 if (high) 577 *high = sign_extend32(u8_get_bits(data, GENMASK(7, 4)), 3); 578 if (low) 579 *low = sign_extend32(u8_get_bits(data, GENMASK(3, 0)), 3); 580 581 return data != 0xff; 582} 583 584static void rtw8851b_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev, 585 struct rtw8851b_efuse *map) 586{ 587 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 588 bool valid = false; 589 590 valid |= _decode_efuse_gain(map->rx_gain_2g_cck, 591 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK], 592 NULL); 593 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm, 594 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM], 595 NULL); 596 valid |= _decode_efuse_gain(map->rx_gain_5g_low, 597 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW], 598 NULL); 599 valid |= _decode_efuse_gain(map->rx_gain_5g_mid, 600 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID], 601 NULL); 602 valid |= _decode_efuse_gain(map->rx_gain_5g_high, 603 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH], 604 NULL); 605 606 gain->offset_valid = valid; 607} 608 609static int rtw8851b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map, 610 enum rtw89_efuse_block block) 611{ 612 struct rtw89_efuse *efuse = &rtwdev->efuse; 613 struct rtw8851b_efuse *map; 614 615 map = (struct rtw8851b_efuse *)log_map; 616 617 efuse->country_code[0] = map->country_code[0]; 618 efuse->country_code[1] = map->country_code[1]; 619 rtw8851b_efuse_parsing_tssi(rtwdev, map); 620 rtw8851b_efuse_parsing_gain_offset(rtwdev, map); 621 622 switch (rtwdev->hci.type) { 623 case RTW89_HCI_TYPE_PCIE: 624 ether_addr_copy(efuse->addr, map->e.mac_addr); 625 break; 626 case RTW89_HCI_TYPE_USB: 627 ether_addr_copy(efuse->addr, map->u.mac_addr); 628 break; 629 default: 630 return -EOPNOTSUPP; 631 } 632 633 efuse->rfe_type = map->rfe_type; 634 efuse->xtal_cap = map->xtal_k; 635 636 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 637 638 return 0; 639} 640 641static void rtw8851b_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 642{ 643 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 644 static const u32 tssi_trim_addr[RF_PATH_NUM_8851B] = {0x5D6}; 645 u32 addr = rtwdev->chip->phycap_addr; 646 bool pg = false; 647 u32 ofst; 648 u8 i, j; 649 650 for (i = 0; i < RF_PATH_NUM_8851B; i++) { 651 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 652 /* addrs are in decreasing order */ 653 ofst = tssi_trim_addr[i] - addr - j; 654 tssi->tssi_trim[i][j] = phycap_map[ofst]; 655 656 if (phycap_map[ofst] != 0xff) 657 pg = true; 658 } 659 } 660 661 if (!pg) { 662 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 663 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 664 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 665 } 666 667 for (i = 0; i < RF_PATH_NUM_8851B; i++) 668 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 669 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 670 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 671 i, j, tssi->tssi_trim[i][j], 672 tssi_trim_addr[i] - j); 673} 674 675static void rtw8851b_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 676 u8 *phycap_map) 677{ 678 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 679 static const u32 thm_trim_addr[RF_PATH_NUM_8851B] = {0x5DF}; 680 u32 addr = rtwdev->chip->phycap_addr; 681 u8 i; 682 683 for (i = 0; i < RF_PATH_NUM_8851B; i++) { 684 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 685 686 rtw89_debug(rtwdev, RTW89_DBG_RFK, 687 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 688 i, info->thermal_trim[i]); 689 690 if (info->thermal_trim[i] != 0xff) 691 info->pg_thermal_trim = true; 692 } 693} 694 695static void rtw8851b_thermal_trim(struct rtw89_dev *rtwdev) 696{ 697#define __thm_setting(raw) \ 698({ \ 699 u8 __v = (raw); \ 700 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 701}) 702 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 703 u8 i, val; 704 705 if (!info->pg_thermal_trim) { 706 rtw89_debug(rtwdev, RTW89_DBG_RFK, 707 "[THERMAL][TRIM] no PG, do nothing\n"); 708 709 return; 710 } 711 712 for (i = 0; i < RF_PATH_NUM_8851B; i++) { 713 val = __thm_setting(info->thermal_trim[i]); 714 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 715 716 rtw89_debug(rtwdev, RTW89_DBG_RFK, 717 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 718 i, val); 719 } 720#undef __thm_setting 721} 722 723static void rtw8851b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 724 u8 *phycap_map) 725{ 726 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 727 static const u32 pabias_trim_addr[] = {0x5DE}; 728 u32 addr = rtwdev->chip->phycap_addr; 729 u8 i; 730 731 for (i = 0; i < RF_PATH_NUM_8851B; i++) { 732 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 733 734 rtw89_debug(rtwdev, RTW89_DBG_RFK, 735 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 736 i, info->pa_bias_trim[i]); 737 738 if (info->pa_bias_trim[i] != 0xff) 739 info->pg_pa_bias_trim = true; 740 } 741} 742 743static void rtw8851b_pa_bias_trim(struct rtw89_dev *rtwdev) 744{ 745 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 746 u8 pabias_2g, pabias_5g; 747 u8 i; 748 749 if (!info->pg_pa_bias_trim) { 750 rtw89_debug(rtwdev, RTW89_DBG_RFK, 751 "[PA_BIAS][TRIM] no PG, do nothing\n"); 752 753 return; 754 } 755 756 for (i = 0; i < RF_PATH_NUM_8851B; i++) { 757 pabias_2g = u8_get_bits(info->pa_bias_trim[i], GENMASK(3, 0)); 758 pabias_5g = u8_get_bits(info->pa_bias_trim[i], GENMASK(7, 4)); 759 760 rtw89_debug(rtwdev, RTW89_DBG_RFK, 761 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 762 i, pabias_2g, pabias_5g); 763 764 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 765 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 766 } 767} 768 769static void rtw8851b_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map) 770{ 771 static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = { 772 {0x5BB, 0x5BA, 0, 0x5B9, 0x5B8}, 773 }; 774 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 775 u32 phycap_addr = rtwdev->chip->phycap_addr; 776 bool valid = false; 777 int path, i; 778 u8 data; 779 780 for (path = 0; path < BB_PATH_NUM_8851B; path++) 781 for (i = 0; i < RTW89_SUBBAND_2GHZ_5GHZ_NR; i++) { 782 if (comp_addrs[path][i] == 0) 783 continue; 784 785 data = phycap_map[comp_addrs[path][i] - phycap_addr]; 786 valid |= _decode_efuse_gain(data, NULL, 787 &gain->comp[path][i]); 788 } 789 790 gain->comp_valid = valid; 791} 792 793static void rtw8851b_phycap_parsing_adc_td(struct rtw89_dev *rtwdev, u8 *phycap_map) 794{ 795 u32 phycap_addr = rtwdev->chip->phycap_addr; 796 struct rtw89_efuse *efuse = &rtwdev->efuse; 797 const u32 addr_adc_td = 0x5AF; 798 799 efuse->adc_td = phycap_map[addr_adc_td - phycap_addr] & GENMASK(4, 0); 800} 801 802static int rtw8851b_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 803{ 804 rtw8851b_phycap_parsing_tssi(rtwdev, phycap_map); 805 rtw8851b_phycap_parsing_thermal_trim(rtwdev, phycap_map); 806 rtw8851b_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 807 rtw8851b_phycap_parsing_gain_comp(rtwdev, phycap_map); 808 rtw8851b_phycap_parsing_adc_td(rtwdev, phycap_map); 809 810 return 0; 811} 812 813static void rtw8851b_set_bb_gpio(struct rtw89_dev *rtwdev, u8 gpio_idx, bool inv, 814 u8 src_sel) 815{ 816 u32 addr, mask; 817 818 if (gpio_idx >= 32) 819 return; 820 821 /* 2 continual 32-bit registers for 32 GPIOs, and each GPIO occupies 2 bits */ 822 addr = R_RFE_SEL0_A2 + (gpio_idx / 16) * sizeof(u32); 823 mask = B_RFE_SEL0_MASK << (gpio_idx % 16) * 2; 824 825 rtw89_phy_write32_mask(rtwdev, addr, mask, RF_PATH_A); 826 rtw89_phy_write32_mask(rtwdev, R_RFE_INV0, BIT(gpio_idx), inv); 827 828 /* 4 continual 32-bit registers for 32 GPIOs, and each GPIO occupies 4 bits */ 829 addr = R_RFE_SEL0_BASE + (gpio_idx / 8) * sizeof(u32); 830 mask = B_RFE_SEL0_SRC_MASK << (gpio_idx % 8) * 4; 831 832 rtw89_phy_write32_mask(rtwdev, addr, mask, src_sel); 833} 834 835static void rtw8851b_set_mac_gpio(struct rtw89_dev *rtwdev, u8 func) 836{ 837 static const struct rtw89_reg3_def func16 = { 838 R_AX_GPIO16_23_FUNC_SEL, B_AX_PINMUX_GPIO16_FUNC_SEL_MASK, BIT(3) 839 }; 840 static const struct rtw89_reg3_def func17 = { 841 R_AX_GPIO16_23_FUNC_SEL, B_AX_PINMUX_GPIO17_FUNC_SEL_MASK, BIT(7) >> 4, 842 }; 843 const struct rtw89_reg3_def *def; 844 845 switch (func) { 846 case 16: 847 def = &func16; 848 break; 849 case 17: 850 def = &func17; 851 break; 852 default: 853 rtw89_warn(rtwdev, "undefined gpio func %d\n", func); 854 return; 855 } 856 857 rtw89_write8_mask(rtwdev, def->addr, def->mask, def->data); 858} 859 860static void rtw8851b_rfe_gpio(struct rtw89_dev *rtwdev) 861{ 862 u8 rfe_type = rtwdev->efuse.rfe_type; 863 864 if (rfe_type > 50) 865 return; 866 867 if (rfe_type % 3 == 2) { 868 rtw8851b_set_bb_gpio(rtwdev, 16, true, RFE_SEL0_SRC_ANTSEL_0); 869 rtw8851b_set_bb_gpio(rtwdev, 17, false, RFE_SEL0_SRC_ANTSEL_0); 870 871 rtw8851b_set_mac_gpio(rtwdev, 16); 872 rtw8851b_set_mac_gpio(rtwdev, 17); 873 } 874} 875 876static void rtw8851b_power_trim(struct rtw89_dev *rtwdev) 877{ 878 rtw8851b_thermal_trim(rtwdev); 879 rtw8851b_pa_bias_trim(rtwdev); 880} 881 882static void rtw8851b_set_channel_mac(struct rtw89_dev *rtwdev, 883 const struct rtw89_chan *chan, 884 u8 mac_idx) 885{ 886 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 887 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); 888 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); 889 u8 txsc20 = 0, txsc40 = 0; 890 891 switch (chan->band_width) { 892 case RTW89_CHANNEL_WIDTH_80: 893 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40); 894 fallthrough; 895 case RTW89_CHANNEL_WIDTH_40: 896 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20); 897 break; 898 default: 899 break; 900 } 901 902 switch (chan->band_width) { 903 case RTW89_CHANNEL_WIDTH_80: 904 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); 905 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); 906 break; 907 case RTW89_CHANNEL_WIDTH_40: 908 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); 909 rtw89_write32(rtwdev, sub_carr, txsc20); 910 break; 911 case RTW89_CHANNEL_WIDTH_20: 912 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); 913 rtw89_write32(rtwdev, sub_carr, 0); 914 break; 915 default: 916 break; 917 } 918 919 if (chan->channel > 14) { 920 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE); 921 rtw89_write8_set(rtwdev, chk_rate, 922 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 923 } else { 924 rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE); 925 rtw89_write8_clr(rtwdev, chk_rate, 926 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 927 } 928} 929 930static const u32 rtw8851b_sco_barker_threshold[14] = { 931 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, 932 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 933}; 934 935static const u32 rtw8851b_sco_cck_threshold[14] = { 936 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, 937 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed 938}; 939 940static void rtw8851b_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch) 941{ 942 u8 ch_element = primary_ch - 1; 943 944 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, 945 rtw8851b_sco_barker_threshold[ch_element]); 946 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, 947 rtw8851b_sco_cck_threshold[ch_element]); 948} 949 950static u8 rtw8851b_sco_mapping(u8 central_ch) 951{ 952 if (central_ch == 1) 953 return 109; 954 else if (central_ch >= 2 && central_ch <= 6) 955 return 108; 956 else if (central_ch >= 7 && central_ch <= 10) 957 return 107; 958 else if (central_ch >= 11 && central_ch <= 14) 959 return 106; 960 else if (central_ch == 36 || central_ch == 38) 961 return 51; 962 else if (central_ch >= 40 && central_ch <= 58) 963 return 50; 964 else if (central_ch >= 60 && central_ch <= 64) 965 return 49; 966 else if (central_ch == 100 || central_ch == 102) 967 return 48; 968 else if (central_ch >= 104 && central_ch <= 126) 969 return 47; 970 else if (central_ch >= 128 && central_ch <= 151) 971 return 46; 972 else if (central_ch >= 153 && central_ch <= 177) 973 return 45; 974 else 975 return 0; 976} 977 978struct rtw8851b_bb_gain { 979 u32 gain_g[BB_PATH_NUM_8851B]; 980 u32 gain_a[BB_PATH_NUM_8851B]; 981 u32 gain_mask; 982}; 983 984static const struct rtw8851b_bb_gain bb_gain_lna[LNA_GAIN_NUM] = { 985 { .gain_g = {0x4678}, .gain_a = {0x45DC}, 986 .gain_mask = 0x00ff0000 }, 987 { .gain_g = {0x4678}, .gain_a = {0x45DC}, 988 .gain_mask = 0xff000000 }, 989 { .gain_g = {0x467C}, .gain_a = {0x4660}, 990 .gain_mask = 0x000000ff }, 991 { .gain_g = {0x467C}, .gain_a = {0x4660}, 992 .gain_mask = 0x0000ff00 }, 993 { .gain_g = {0x467C}, .gain_a = {0x4660}, 994 .gain_mask = 0x00ff0000 }, 995 { .gain_g = {0x467C}, .gain_a = {0x4660}, 996 .gain_mask = 0xff000000 }, 997 { .gain_g = {0x4680}, .gain_a = {0x4664}, 998 .gain_mask = 0x000000ff }, 999}; 1000 1001static const struct rtw8851b_bb_gain bb_gain_tia[TIA_GAIN_NUM] = { 1002 { .gain_g = {0x4680}, .gain_a = {0x4664}, 1003 .gain_mask = 0x00ff0000 }, 1004 { .gain_g = {0x4680}, .gain_a = {0x4664}, 1005 .gain_mask = 0xff000000 }, 1006}; 1007 1008static void rtw8851b_set_gain_error(struct rtw89_dev *rtwdev, 1009 enum rtw89_subband subband, 1010 enum rtw89_rf_path path) 1011{ 1012 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1013 u8 gain_band = rtw89_subband_to_bb_gain_band(subband); 1014 s32 val; 1015 u32 reg; 1016 u32 mask; 1017 int i; 1018 1019 for (i = 0; i < LNA_GAIN_NUM; i++) { 1020 if (subband == RTW89_CH_2G) 1021 reg = bb_gain_lna[i].gain_g[path]; 1022 else 1023 reg = bb_gain_lna[i].gain_a[path]; 1024 1025 mask = bb_gain_lna[i].gain_mask; 1026 val = gain->lna_gain[gain_band][path][i]; 1027 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 1028 } 1029 1030 for (i = 0; i < TIA_GAIN_NUM; i++) { 1031 if (subband == RTW89_CH_2G) 1032 reg = bb_gain_tia[i].gain_g[path]; 1033 else 1034 reg = bb_gain_tia[i].gain_a[path]; 1035 1036 mask = bb_gain_tia[i].gain_mask; 1037 val = gain->tia_gain[gain_band][path][i]; 1038 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 1039 } 1040} 1041 1042static void rtw8851b_set_gain_offset(struct rtw89_dev *rtwdev, 1043 enum rtw89_subband subband, 1044 enum rtw89_phy_idx phy_idx) 1045{ 1046 static const u32 rssi_ofst_addr[] = {R_PATH0_G_TIA1_LNA6_OP1DB_V1}; 1047 static const u32 gain_err_addr[] = {R_P0_AGC_RSVD}; 1048 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain; 1049 enum rtw89_gain_offset gain_ofdm_band; 1050 s32 offset_ofdm, offset_cck; 1051 s32 offset_a; 1052 s32 tmp; 1053 u8 path; 1054 1055 if (!efuse_gain->comp_valid) 1056 goto next; 1057 1058 for (path = RF_PATH_A; path < BB_PATH_NUM_8851B; path++) { 1059 tmp = efuse_gain->comp[path][subband]; 1060 tmp = clamp_t(s32, tmp << 2, S8_MIN, S8_MAX); 1061 rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp); 1062 } 1063 1064next: 1065 if (!efuse_gain->offset_valid) 1066 return; 1067 1068 gain_ofdm_band = rtw89_subband_to_gain_offset_band_of_ofdm(subband); 1069 1070 offset_a = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band]; 1071 1072 tmp = -((offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2)); 1073 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 1074 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp); 1075 1076 offset_ofdm = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band]; 1077 offset_cck = -efuse_gain->offset[RF_PATH_A][0]; 1078 1079 tmp = (offset_ofdm << 4) + efuse_gain->offset_base[RTW89_PHY_0]; 1080 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 1081 rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx); 1082 1083 tmp = (offset_ofdm << 4) + efuse_gain->rssi_base[RTW89_PHY_0]; 1084 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 1085 rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx); 1086 1087 if (subband == RTW89_CH_2G) { 1088 tmp = (offset_cck << 3) + (efuse_gain->offset_base[RTW89_PHY_0] >> 1); 1089 tmp = clamp_t(s32, tmp, S8_MIN >> 1, S8_MAX >> 1); 1090 rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST, 1091 B_RX_RPL_OFST_CCK_MASK, tmp); 1092 } 1093} 1094 1095static 1096void rtw8851b_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband) 1097{ 1098 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1099 u8 band = rtw89_subband_to_bb_gain_band(subband); 1100 u32 val; 1101 1102 val = u32_encode_bits(gain->rpl_ofst_20[band][RF_PATH_A], B_P0_RPL1_20_MASK) | 1103 u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][0], B_P0_RPL1_40_MASK) | 1104 u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][1], B_P0_RPL1_41_MASK); 1105 val >>= B_P0_RPL1_SHIFT; 1106 rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val); 1107 rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val); 1108 1109 val = u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][2], B_P0_RTL2_42_MASK) | 1110 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][0], B_P0_RTL2_80_MASK) | 1111 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][1], B_P0_RTL2_81_MASK) | 1112 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][10], B_P0_RTL2_8A_MASK); 1113 rtw89_phy_write32(rtwdev, R_P0_RPL2, val); 1114 rtw89_phy_write32(rtwdev, R_P1_RPL2, val); 1115 1116 val = u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][2], B_P0_RTL3_82_MASK) | 1117 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][3], B_P0_RTL3_83_MASK) | 1118 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][4], B_P0_RTL3_84_MASK) | 1119 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][9], B_P0_RTL3_89_MASK); 1120 rtw89_phy_write32(rtwdev, R_P0_RPL3, val); 1121 rtw89_phy_write32(rtwdev, R_P1_RPL3, val); 1122} 1123 1124static void rtw8851b_ctrl_ch(struct rtw89_dev *rtwdev, 1125 const struct rtw89_chan *chan, 1126 enum rtw89_phy_idx phy_idx) 1127{ 1128 u8 subband = chan->subband_type; 1129 u8 central_ch = chan->channel; 1130 bool is_2g = central_ch <= 14; 1131 u8 sco_comp; 1132 1133 if (is_2g) 1134 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 1135 B_PATH0_BAND_SEL_MSK_V1, 1, phy_idx); 1136 else 1137 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 1138 B_PATH0_BAND_SEL_MSK_V1, 0, phy_idx); 1139 /* SCO compensate FC setting */ 1140 sco_comp = rtw8851b_sco_mapping(central_ch); 1141 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx); 1142 1143 if (chan->band_type == RTW89_BAND_6G) 1144 return; 1145 1146 /* CCK parameters */ 1147 if (central_ch == 14) { 1148 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff); 1149 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de); 1150 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad); 1151 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e); 1152 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92); 1153 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); 1154 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); 1155 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a); 1156 } else { 1157 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff); 1158 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354); 1159 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); 1160 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053); 1161 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a); 1162 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92); 1163 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc); 1164 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5); 1165 } 1166 1167 rtw8851b_set_gain_error(rtwdev, subband, RF_PATH_A); 1168 rtw8851b_set_gain_offset(rtwdev, subband, phy_idx); 1169 rtw8851b_set_rxsc_rpl_comp(rtwdev, subband); 1170} 1171 1172static void rtw8851b_bw_setting(struct rtw89_dev *rtwdev, u8 bw) 1173{ 1174 struct rtw89_efuse *efuse = &rtwdev->efuse; 1175 u8 adc_bw_sel; 1176 1177 switch (efuse->adc_td) { 1178 default: 1179 case 0x19: 1180 adc_bw_sel = 0x4; 1181 break; 1182 case 0x11: 1183 adc_bw_sel = 0x5; 1184 break; 1185 case 0x9: 1186 adc_bw_sel = 0x3; 1187 break; 1188 } 1189 1190 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_BW1, adc_bw_sel); 1191 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_MUL, 0xf); 1192 rtw89_phy_write32_mask(rtwdev, R_ADCMOD, B_ADCMOD_LP, 0xa); 1193 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_RC, 0x3); 1194 1195 switch (bw) { 1196 case RTW89_CHANNEL_WIDTH_5: 1197 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_CTL, 0x8); 1198 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_EN, 0x2); 1199 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_BW0, 0x2); 1200 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1); 1201 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x0); 1202 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x1); 1203 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ADJ, 0x92); 1204 break; 1205 case RTW89_CHANNEL_WIDTH_10: 1206 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_CTL, 0x8); 1207 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_EN, 0x2); 1208 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_BW0, 0x2); 1209 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1); 1210 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x1); 1211 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0); 1212 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ADJ, 0x92); 1213 break; 1214 case RTW89_CHANNEL_WIDTH_20: 1215 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_CTL, 0x8); 1216 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_EN, 0x2); 1217 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_BW0, 0x2); 1218 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2); 1219 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2); 1220 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0); 1221 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ADJ, 0x92); 1222 break; 1223 case RTW89_CHANNEL_WIDTH_40: 1224 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_CTL, 0x8); 1225 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_EN, 0x2); 1226 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_BW0, 0x2); 1227 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2); 1228 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2); 1229 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0); 1230 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ADJ, 0x92); 1231 break; 1232 case RTW89_CHANNEL_WIDTH_80: 1233 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_CTL, 0x8); 1234 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_EN, 0x2); 1235 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_BW0, 0x2); 1236 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x0); 1237 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2); 1238 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0); 1239 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ADJ, 0x92); 1240 break; 1241 default: 1242 rtw89_warn(rtwdev, "Fail to set ADC\n"); 1243 } 1244} 1245 1246static void rtw8851b_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 1247 enum rtw89_phy_idx phy_idx) 1248{ 1249 switch (bw) { 1250 case RTW89_CHANNEL_WIDTH_5: 1251 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); 1252 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx); 1253 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); 1254 break; 1255 case RTW89_CHANNEL_WIDTH_10: 1256 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); 1257 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx); 1258 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); 1259 break; 1260 case RTW89_CHANNEL_WIDTH_20: 1261 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); 1262 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); 1263 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); 1264 break; 1265 case RTW89_CHANNEL_WIDTH_40: 1266 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx); 1267 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); 1268 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 1269 pri_ch, phy_idx); 1270 /* CCK primary channel */ 1271 if (pri_ch == RTW89_SC_20_UPPER) 1272 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); 1273 else 1274 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); 1275 1276 break; 1277 case RTW89_CHANNEL_WIDTH_80: 1278 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx); 1279 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); 1280 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 1281 pri_ch, phy_idx); 1282 break; 1283 default: 1284 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1285 pri_ch); 1286 } 1287 1288 rtw8851b_bw_setting(rtwdev, bw); 1289} 1290 1291static void rtw8851b_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en) 1292{ 1293 if (cck_en) { 1294 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); 1295 rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF, 1296 B_PD_ARBITER_OFF, 0); 1297 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1); 1298 } else { 1299 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); 1300 rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF, 1301 B_PD_ARBITER_OFF, 1); 1302 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0); 1303 } 1304} 1305 1306static u32 rtw8851b_spur_freq(struct rtw89_dev *rtwdev, 1307 const struct rtw89_chan *chan) 1308{ 1309 u8 center_chan = chan->channel; 1310 1311 switch (chan->band_type) { 1312 case RTW89_BAND_5G: 1313 if (center_chan == 151 || center_chan == 153 || 1314 center_chan == 155 || center_chan == 163) 1315 return 5760; 1316 else if (center_chan == 54 || center_chan == 58) 1317 return 5280; 1318 break; 1319 default: 1320 break; 1321 } 1322 1323 return 0; 1324} 1325 1326#define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */ 1327#define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */ 1328#define MAX_TONE_NUM 2048 1329 1330static void rtw8851b_set_csi_tone_idx(struct rtw89_dev *rtwdev, 1331 const struct rtw89_chan *chan, 1332 enum rtw89_phy_idx phy_idx) 1333{ 1334 u32 spur_freq; 1335 s32 freq_diff, csi_idx, csi_tone_idx; 1336 1337 spur_freq = rtw8851b_spur_freq(rtwdev, chan); 1338 if (spur_freq == 0) { 1339 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN, 1340 0, phy_idx); 1341 return; 1342 } 1343 1344 freq_diff = (spur_freq - chan->freq) * 1000000; 1345 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125); 1346 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx); 1347 1348 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_V1, B_SEG0CSI_IDX, 1349 csi_tone_idx, phy_idx); 1350 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN, 1, phy_idx); 1351} 1352 1353static const struct rtw89_nbi_reg_def rtw8851b_nbi_reg_def = { 1354 .notch1_idx = {0x46E4, 0xFF}, 1355 .notch1_frac_idx = {0x46E4, 0xC00}, 1356 .notch1_en = {0x46E4, 0x1000}, 1357 .notch2_idx = {0x47A4, 0xFF}, 1358 .notch2_frac_idx = {0x47A4, 0xC00}, 1359 .notch2_en = {0x47A4, 0x1000}, 1360}; 1361 1362static void rtw8851b_set_nbi_tone_idx(struct rtw89_dev *rtwdev, 1363 const struct rtw89_chan *chan) 1364{ 1365 const struct rtw89_nbi_reg_def *nbi = &rtw8851b_nbi_reg_def; 1366 s32 nbi_frac_idx, nbi_frac_tone_idx; 1367 s32 nbi_idx, nbi_tone_idx; 1368 bool notch2_chk = false; 1369 u32 spur_freq, fc; 1370 s32 freq_diff; 1371 1372 spur_freq = rtw8851b_spur_freq(rtwdev, chan); 1373 if (spur_freq == 0) { 1374 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, 1375 nbi->notch1_en.mask, 0); 1376 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, 1377 nbi->notch2_en.mask, 0); 1378 return; 1379 } 1380 1381 fc = chan->freq; 1382 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) { 1383 fc = (spur_freq > fc) ? fc + 40 : fc - 40; 1384 if ((fc > spur_freq && 1385 chan->channel < chan->primary_channel) || 1386 (fc < spur_freq && 1387 chan->channel > chan->primary_channel)) 1388 notch2_chk = true; 1389 } 1390 1391 freq_diff = (spur_freq - fc) * 1000000; 1392 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5, 1393 &nbi_frac_idx); 1394 1395 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) { 1396 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx); 1397 } else { 1398 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ? 1399 128 : 256; 1400 1401 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx); 1402 } 1403 nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx, 1404 CARRIER_SPACING_78_125); 1405 1406 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) { 1407 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr, 1408 nbi->notch2_idx.mask, nbi_tone_idx); 1409 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr, 1410 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx); 1411 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, 1412 nbi->notch2_en.mask, 0); 1413 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, 1414 nbi->notch2_en.mask, 1); 1415 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, 1416 nbi->notch1_en.mask, 0); 1417 } else { 1418 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr, 1419 nbi->notch1_idx.mask, nbi_tone_idx); 1420 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr, 1421 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx); 1422 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, 1423 nbi->notch1_en.mask, 0); 1424 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, 1425 nbi->notch1_en.mask, 1); 1426 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, 1427 nbi->notch2_en.mask, 0); 1428 } 1429} 1430 1431static void rtw8851b_set_cfr(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan) 1432{ 1433 if (chan->band_type == RTW89_BAND_2G && 1434 chan->band_width == RTW89_CHANNEL_WIDTH_20 && 1435 (chan->channel == 1 || chan->channel == 13)) { 1436 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR, 1437 B_PATH0_TX_CFR_LGC0, 0xf8); 1438 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR, 1439 B_PATH0_TX_CFR_LGC1, 0x120); 1440 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING, 1441 B_PATH0_TX_POLAR_CLIPPING_LGC0, 0x0); 1442 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING, 1443 B_PATH0_TX_POLAR_CLIPPING_LGC1, 0x3); 1444 } else { 1445 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR, 1446 B_PATH0_TX_CFR_LGC0, 0x120); 1447 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR, 1448 B_PATH0_TX_CFR_LGC1, 0x3ff); 1449 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING, 1450 B_PATH0_TX_POLAR_CLIPPING_LGC0, 0x3); 1451 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING, 1452 B_PATH0_TX_POLAR_CLIPPING_LGC1, 0x7); 1453 } 1454} 1455 1456static void rtw8851b_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 1457 enum rtw89_phy_idx phy_idx) 1458{ 1459 u8 pri_ch = chan->pri_ch_idx; 1460 bool mask_5m_low; 1461 bool mask_5m_en; 1462 1463 switch (chan->band_width) { 1464 case RTW89_CHANNEL_WIDTH_40: 1465 /* Prich=1: Mask 5M High, Prich=2: Mask 5M Low */ 1466 mask_5m_en = true; 1467 mask_5m_low = pri_ch == RTW89_SC_20_LOWER; 1468 break; 1469 case RTW89_CHANNEL_WIDTH_80: 1470 /* Prich=3: Mask 5M High, Prich=4: Mask 5M Low, Else: Disable */ 1471 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST || 1472 pri_ch == RTW89_SC_20_LOWEST; 1473 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST; 1474 break; 1475 default: 1476 mask_5m_en = false; 1477 break; 1478 } 1479 1480 if (!mask_5m_en) { 1481 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0); 1482 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1, 1483 B_ASSIGN_SBD_OPT_EN_V1, 0x0, phy_idx); 1484 return; 1485 } 1486 1487 if (mask_5m_low) { 1488 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5); 1489 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1); 1490 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0); 1491 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1); 1492 } else { 1493 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5); 1494 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1); 1495 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1); 1496 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0); 1497 } 1498 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1, 1499 B_ASSIGN_SBD_OPT_EN_V1, 0x1, phy_idx); 1500} 1501 1502static void rtw8851b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1503{ 1504 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1505 fsleep(1); 1506 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); 1507 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx); 1508 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1509 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); 1510} 1511 1512static void rtw8851b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band, 1513 enum rtw89_phy_idx phy_idx, bool en) 1514{ 1515 if (en) { 1516 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1517 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1518 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); 1519 if (band == RTW89_BAND_2G) 1520 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0); 1521 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); 1522 } else { 1523 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1); 1524 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); 1525 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1526 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1527 fsleep(1); 1528 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx); 1529 } 1530} 1531 1532static void rtw8851b_bb_reset(struct rtw89_dev *rtwdev, 1533 enum rtw89_phy_idx phy_idx) 1534{ 1535 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 1536 B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x1); 1537 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1538 rtw8851b_bb_reset_all(rtwdev, phy_idx); 1539 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 1540 B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x3); 1541 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1542} 1543 1544static 1545void rtw8851b_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1546 u8 tx_path_en, u8 trsw_tx, 1547 u8 trsw_rx, u8 trsw_a, u8 trsw_b) 1548{ 1549 u32 mask_ofst = 16; 1550 u32 val; 1551 1552 if (path != RF_PATH_A) 1553 return; 1554 1555 mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2; 1556 val = u32_encode_bits(trsw_a, B_P0_TRSW_A) | 1557 u32_encode_bits(trsw_b, B_P0_TRSW_B); 1558 1559 rtw89_phy_write32_mask(rtwdev, R_P0_TRSW, 1560 (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val); 1561} 1562 1563static void rtw8851b_bb_gpio_init(struct rtw89_dev *rtwdev) 1564{ 1565 rtw89_phy_write32_set(rtwdev, R_P0_TRSW, B_P0_TRSW_A); 1566 rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_X); 1567 rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_SO_A2); 1568 rtw89_phy_write32(rtwdev, R_RFE_SEL0_BASE, 0x77777777); 1569 rtw89_phy_write32(rtwdev, R_RFE_SEL32_BASE, 0x77777777); 1570 1571 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff); 1572 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0); 1573 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0); 1574 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0); 1575 1576 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1); 1577 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0); 1578 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0); 1579 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0); 1580 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1); 1581 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0); 1582 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0); 1583 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0); 1584} 1585 1586static void rtw8851b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1587 enum rtw89_phy_idx phy_idx) 1588{ 1589 u32 addr; 1590 1591 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1592 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1593 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1594} 1595 1596static void rtw8851b_bb_sethw(struct rtw89_dev *rtwdev) 1597{ 1598 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 1599 1600 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); 1601 1602 rtw8851b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1603 rtw8851b_bb_gpio_init(rtwdev); 1604 1605 rtw89_write32_clr(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_VALUE); 1606 rtw89_write32_set(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_EN); 1607 1608 /* read these registers after loading BB parameters */ 1609 gain->offset_base[RTW89_PHY_0] = 1610 rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK); 1611 gain->rssi_base[RTW89_PHY_0] = 1612 rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK); 1613} 1614 1615static void rtw8851b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 1616 enum rtw89_phy_idx phy_idx) 1617{ 1618 u8 band = chan->band_type, chan_idx; 1619 bool cck_en = chan->channel <= 14; 1620 u8 pri_ch_idx = chan->pri_ch_idx; 1621 1622 if (cck_en) 1623 rtw8851b_ctrl_sco_cck(rtwdev, chan->primary_channel); 1624 1625 rtw8851b_ctrl_ch(rtwdev, chan, phy_idx); 1626 rtw8851b_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1627 rtw8851b_ctrl_cck_en(rtwdev, cck_en); 1628 rtw8851b_set_nbi_tone_idx(rtwdev, chan); 1629 rtw8851b_set_csi_tone_idx(rtwdev, chan, phy_idx); 1630 1631 if (chan->band_type == RTW89_BAND_5G) { 1632 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 1633 B_PATH0_BT_SHARE_V1, 0x0); 1634 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 1635 B_PATH0_BTG_PATH_V1, 0x0); 1636 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0); 1637 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0); 1638 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, 1639 B_BT_DYN_DC_EST_EN_MSK, 0x0); 1640 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0); 1641 } 1642 1643 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band); 1644 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx); 1645 rtw8851b_5m_mask(rtwdev, chan, phy_idx); 1646 rtw8851b_set_cfr(rtwdev, chan); 1647 rtw8851b_bb_reset_all(rtwdev, phy_idx); 1648} 1649 1650static void rtw8851b_set_channel(struct rtw89_dev *rtwdev, 1651 const struct rtw89_chan *chan, 1652 enum rtw89_mac_idx mac_idx, 1653 enum rtw89_phy_idx phy_idx) 1654{ 1655 rtw8851b_set_channel_mac(rtwdev, chan, mac_idx); 1656 rtw8851b_set_channel_bb(rtwdev, chan, phy_idx); 1657 rtw8851b_set_channel_rf(rtwdev, chan, phy_idx); 1658} 1659 1660static void rtw8851b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 1661 enum rtw89_rf_path path) 1662{ 1663 if (en) { 1664 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x0); 1665 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x0); 1666 } else { 1667 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x1); 1668 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x1); 1669 } 1670} 1671 1672static void rtw8851b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, 1673 u8 phy_idx) 1674{ 1675 rtw8851b_tssi_cont_en(rtwdev, en, RF_PATH_A); 1676} 1677 1678static void rtw8851b_adc_en(struct rtw89_dev *rtwdev, bool en) 1679{ 1680 if (en) 1681 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0); 1682 else 1683 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf); 1684} 1685 1686static void rtw8851b_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1687 struct rtw89_channel_help_params *p, 1688 const struct rtw89_chan *chan, 1689 enum rtw89_mac_idx mac_idx, 1690 enum rtw89_phy_idx phy_idx) 1691{ 1692 if (enter) { 1693 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL); 1694 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 1695 rtw8851b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0); 1696 rtw8851b_adc_en(rtwdev, false); 1697 fsleep(40); 1698 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false); 1699 } else { 1700 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 1701 rtw8851b_adc_en(rtwdev, true); 1702 rtw8851b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0); 1703 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true); 1704 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en); 1705 } 1706} 1707 1708static void rtw8851b_rfk_init(struct rtw89_dev *rtwdev) 1709{ 1710 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1711 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1712 rtw8851b_lck_init(rtwdev); 1713 1714 rtw8851b_dpk_init(rtwdev); 1715 rtw8851b_aack(rtwdev); 1716 rtw8851b_rck(rtwdev); 1717 rtw8851b_dack(rtwdev); 1718 rtw8851b_rx_dck(rtwdev, RTW89_PHY_0, RTW89_CHANCTX_0); 1719} 1720 1721static void rtw8851b_rfk_channel(struct rtw89_dev *rtwdev, 1722 struct rtw89_vif_link *rtwvif_link) 1723{ 1724 enum rtw89_chanctx_idx chanctx_idx = rtwvif_link->chanctx_idx; 1725 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx; 1726 1727 rtw89_btc_ntfy_conn_rfk(rtwdev, true); 1728 1729 rtw8851b_rx_dck(rtwdev, phy_idx, chanctx_idx); 1730 rtw8851b_iqk(rtwdev, phy_idx, chanctx_idx); 1731 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30); 1732 rtw8851b_tssi(rtwdev, phy_idx, true, chanctx_idx); 1733 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30); 1734 rtw8851b_dpk(rtwdev, phy_idx, chanctx_idx); 1735 1736 rtw89_btc_ntfy_conn_rfk(rtwdev, false); 1737} 1738 1739static void rtw8851b_rfk_band_changed(struct rtw89_dev *rtwdev, 1740 enum rtw89_phy_idx phy_idx, 1741 const struct rtw89_chan *chan) 1742{ 1743 rtw8851b_tssi_scan(rtwdev, phy_idx, chan); 1744} 1745 1746static void rtw8851b_rfk_scan(struct rtw89_dev *rtwdev, 1747 struct rtw89_vif_link *rtwvif_link, 1748 bool start) 1749{ 1750 rtw8851b_wifi_scan_notify(rtwdev, start, rtwvif_link->phy_idx, 1751 rtwvif_link->chanctx_idx); 1752} 1753 1754static void rtw8851b_rfk_track(struct rtw89_dev *rtwdev) 1755{ 1756 rtw8851b_dpk_track(rtwdev); 1757 rtw8851b_lck_track(rtwdev); 1758} 1759 1760static u32 rtw8851b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1761 enum rtw89_phy_idx phy_idx, s16 ref) 1762{ 1763 const u16 tssi_16dbm_cw = 0x12c; 1764 const u8 base_cw_0db = 0x27; 1765 const s8 ofst_int = 0; 1766 s16 pwr_s10_3; 1767 s16 rf_pwr_cw; 1768 u16 bb_pwr_cw; 1769 u32 pwr_cw; 1770 u32 tssi_ofst_cw; 1771 1772 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1773 bb_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(2, 0)); 1774 rf_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(8, 3)); 1775 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1776 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1777 1778 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1779 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1780 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1781 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1782 1783 return u32_encode_bits(tssi_ofst_cw, B_DPD_TSSI_CW) | 1784 u32_encode_bits(pwr_cw, B_DPD_PWR_CW) | 1785 u32_encode_bits(ref, B_DPD_REF); 1786} 1787 1788static void rtw8851b_set_txpwr_ref(struct rtw89_dev *rtwdev, 1789 enum rtw89_phy_idx phy_idx) 1790{ 1791 static const u32 addr[RF_PATH_NUM_8851B] = {0x5800}; 1792 const u32 mask = B_DPD_TSSI_CW | B_DPD_PWR_CW | B_DPD_REF; 1793 const u8 ofst_ofdm = 0x4; 1794 const u8 ofst_cck = 0x8; 1795 const s16 ref_ofdm = 0; 1796 const s16 ref_cck = 0; 1797 u32 val; 1798 u8 i; 1799 1800 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1801 1802 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1803 B_AX_PWR_REF, 0x0); 1804 1805 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1806 val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1807 1808 for (i = 0; i < RF_PATH_NUM_8851B; i++) 1809 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1810 phy_idx); 1811 1812 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1813 val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1814 1815 for (i = 0; i < RF_PATH_NUM_8851B; i++) 1816 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1817 phy_idx); 1818} 1819 1820static void rtw8851b_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev, 1821 const struct rtw89_chan *chan, 1822 u8 tx_shape_idx, 1823 enum rtw89_phy_idx phy_idx) 1824{ 1825#define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2)) 1826#define __DFIR_CFG_MASK 0xffffffff 1827#define __DFIR_CFG_NR 8 1828#define __DECL_DFIR_PARAM(_name, _val...) \ 1829 static const u32 param_ ## _name[] = {_val}; \ 1830 static_assert(ARRAY_SIZE(param_ ## _name) == __DFIR_CFG_NR) 1831 1832 __DECL_DFIR_PARAM(flat, 1833 0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053, 1834 0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5); 1835 __DECL_DFIR_PARAM(sharp, 1836 0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090, 1837 0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5); 1838 __DECL_DFIR_PARAM(sharp_14, 1839 0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E, 1840 0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A); 1841 u8 ch = chan->channel; 1842 const u32 *param; 1843 u32 addr; 1844 int i; 1845 1846 if (ch > 14) { 1847 rtw89_warn(rtwdev, 1848 "set tx shape dfir by unknown ch: %d on 2G\n", ch); 1849 return; 1850 } 1851 1852 if (ch == 14) 1853 param = param_sharp_14; 1854 else 1855 param = tx_shape_idx == 0 ? param_flat : param_sharp; 1856 1857 for (i = 0; i < __DFIR_CFG_NR; i++) { 1858 addr = __DFIR_CFG_ADDR(i); 1859 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1860 "set tx shape dfir: 0x%x: 0x%x\n", addr, param[i]); 1861 rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i], 1862 phy_idx); 1863 } 1864 1865#undef __DECL_DFIR_PARAM 1866#undef __DFIR_CFG_NR 1867#undef __DFIR_CFG_MASK 1868#undef __DECL_CFG_ADDR 1869} 1870 1871static void rtw8851b_set_tx_shape(struct rtw89_dev *rtwdev, 1872 const struct rtw89_chan *chan, 1873 enum rtw89_phy_idx phy_idx) 1874{ 1875 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 1876 u8 band = chan->band_type; 1877 u8 regd = rtw89_regd_get(rtwdev, band); 1878 u8 tx_shape_cck = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_CCK][regd]; 1879 u8 tx_shape_ofdm = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_OFDM][regd]; 1880 1881 if (band == RTW89_BAND_2G) 1882 rtw8851b_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx); 1883 1884 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG, 1885 tx_shape_ofdm); 1886} 1887 1888static void rtw8851b_set_txpwr(struct rtw89_dev *rtwdev, 1889 const struct rtw89_chan *chan, 1890 enum rtw89_phy_idx phy_idx) 1891{ 1892 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 1893 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 1894 rtw8851b_set_tx_shape(rtwdev, chan, phy_idx); 1895 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 1896 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 1897} 1898 1899static void rtw8851b_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 1900 enum rtw89_phy_idx phy_idx) 1901{ 1902 rtw8851b_set_txpwr_ref(rtwdev, phy_idx); 1903} 1904 1905static 1906void rtw8851b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1907 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1908{ 1909 u32 reg; 1910 1911 if (pw_ofst < -16 || pw_ofst > 15) { 1912 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst); 1913 return; 1914 } 1915 1916 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx); 1917 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); 1918 1919 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); 1920 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst); 1921 1922 pw_ofst = max_t(s8, pw_ofst - 3, -16); 1923 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); 1924 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst); 1925} 1926 1927static int 1928rtw8851b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1929{ 1930 int ret; 1931 1932 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 1933 if (ret) 1934 return ret; 1935 1936 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000); 1937 if (ret) 1938 return ret; 1939 1940 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 1941 if (ret) 1942 return ret; 1943 1944 rtw8851b_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ? 1945 RTW89_MAC_1 : RTW89_MAC_0); 1946 1947 return 0; 1948} 1949 1950static void rtw8851b_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 1951 enum rtw89_phy_idx phy_idx) 1952{ 1953 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 1954 1955 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8851b_btc_preagc_en_defs_tbl : 1956 &rtw8851b_btc_preagc_dis_defs_tbl); 1957 1958 if (!en) { 1959 if (chan->band_type == RTW89_BAND_2G) { 1960 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 1961 B_PATH0_G_LNA6_OP1DB_V1, 0x20); 1962 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 1963 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x30); 1964 } else { 1965 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 1966 B_PATH0_G_LNA6_OP1DB_V1, 0x1a); 1967 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 1968 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a); 1969 } 1970 } 1971} 1972 1973static void rtw8851b_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 1974 enum rtw89_phy_idx phy_idx) 1975{ 1976 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 1977 1978 if (en) { 1979 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 1980 B_PATH0_BT_SHARE_V1, 0x1); 1981 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 1982 B_PATH0_BTG_PATH_V1, 0x1); 1983 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 1984 B_PATH0_G_LNA6_OP1DB_V1, 0x20); 1985 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 1986 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x30); 1987 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 1988 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1); 1989 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x1); 1990 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, 1991 B_BT_DYN_DC_EST_EN_MSK, 0x1); 1992 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1); 1993 } else { 1994 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 1995 B_PATH0_BT_SHARE_V1, 0x0); 1996 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 1997 B_PATH0_BTG_PATH_V1, 0x0); 1998 if (chan->band_type == RTW89_BAND_2G) { 1999 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2000 B_PATH0_G_LNA6_OP1DB_V1, 0x80); 2001 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2002 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80); 2003 } else { 2004 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2005 B_PATH0_G_LNA6_OP1DB_V1, 0x1a); 2006 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2007 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2008 } 2009 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc); 2010 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0); 2011 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0); 2012 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, 2013 B_BT_DYN_DC_EST_EN_MSK, 0x1); 2014 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0); 2015 } 2016} 2017 2018static void rtw8851b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev, 2019 enum rtw89_rf_path_bit rx_path) 2020{ 2021 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 2022 u32 rst_mask0; 2023 2024 if (rx_path == RF_A) { 2025 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1); 2026 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1); 2027 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1); 2028 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 2029 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 2030 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4); 2031 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2032 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2033 } 2034 2035 rtw8851b_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0); 2036 2037 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 2038 if (rx_path == RF_A) { 2039 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 2040 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 2041 } 2042} 2043 2044static void rtw8851b_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) 2045{ 2046 rtw8851b_bb_ctrl_rx_path(rtwdev, RF_A); 2047 2048 if (rtwdev->hal.rx_nss == 1) { 2049 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 2050 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 2051 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2052 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2053 } 2054 2055 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); 2056} 2057 2058static u8 rtw8851b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 2059{ 2060 if (rtwdev->is_tssi_mode[rf_path]) { 2061 u32 addr = R_TSSI_THER + (rf_path << 13); 2062 2063 return rtw89_phy_read32_mask(rtwdev, addr, B_TSSI_THER); 2064 } 2065 2066 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2067 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 2068 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2069 2070 fsleep(200); 2071 2072 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 2073} 2074 2075static void rtw8851b_btc_set_rfe(struct rtw89_dev *rtwdev) 2076{ 2077 const struct rtw89_btc_ver *ver = rtwdev->btc.ver; 2078 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; 2079 2080 if (ver->fcxinit == 7) { 2081 md->md_v7.rfe_type = rtwdev->efuse.rfe_type; 2082 md->md_v7.kt_ver = rtwdev->hal.cv; 2083 md->md_v7.bt_solo = 0; 2084 md->md_v7.switch_type = BTC_SWITCH_INTERNAL; 2085 md->md_v7.ant.isolation = 10; 2086 md->md_v7.kt_ver_adie = rtwdev->hal.acv; 2087 2088 if (md->md_v7.rfe_type == 0) 2089 return; 2090 2091 /* rfe_type 3*n+1: 1-Ant(shared), 2092 * 3*n+2: 2-Ant+Div(non-shared), 2093 * 3*n+3: 2-Ant+no-Div(non-shared) 2094 */ 2095 md->md_v7.ant.num = (md->md_v7.rfe_type % 3 == 1) ? 1 : 2; 2096 /* WL-1ss at S0, btg at s0 (On 1 WL RF) */ 2097 md->md_v7.ant.single_pos = RF_PATH_A; 2098 md->md_v7.ant.btg_pos = RF_PATH_A; 2099 md->md_v7.ant.stream_cnt = 1; 2100 2101 if (md->md_v7.ant.num == 1) { 2102 md->md_v7.ant.type = BTC_ANT_SHARED; 2103 md->md_v7.bt_pos = BTC_BT_BTG; 2104 md->md_v7.wa_type = 1; 2105 md->md_v7.ant.diversity = 0; 2106 } else { /* ant.num == 2 */ 2107 md->md_v7.ant.type = BTC_ANT_DEDICATED; 2108 md->md_v7.bt_pos = BTC_BT_ALONE; 2109 md->md_v7.switch_type = BTC_SWITCH_EXTERNAL; 2110 md->md_v7.wa_type = 0; 2111 if (md->md_v7.rfe_type % 3 == 2) 2112 md->md_v7.ant.diversity = 1; 2113 } 2114 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos; 2115 rtwdev->btc.ant_type = md->md_v7.ant.type; 2116 } else { 2117 md->md.rfe_type = rtwdev->efuse.rfe_type; 2118 md->md.cv = rtwdev->hal.cv; 2119 md->md.bt_solo = 0; 2120 md->md.switch_type = BTC_SWITCH_INTERNAL; 2121 md->md.ant.isolation = 10; 2122 md->md.kt_ver_adie = rtwdev->hal.acv; 2123 2124 if (md->md.rfe_type == 0) 2125 return; 2126 2127 /* rfe_type 3*n+1: 1-Ant(shared), 2128 * 3*n+2: 2-Ant+Div(non-shared), 2129 * 3*n+3: 2-Ant+no-Div(non-shared) 2130 */ 2131 md->md.ant.num = (md->md.rfe_type % 3 == 1) ? 1 : 2; 2132 /* WL-1ss at S0, btg at s0 (On 1 WL RF) */ 2133 md->md.ant.single_pos = RF_PATH_A; 2134 md->md.ant.btg_pos = RF_PATH_A; 2135 md->md.ant.stream_cnt = 1; 2136 2137 if (md->md.ant.num == 1) { 2138 md->md.ant.type = BTC_ANT_SHARED; 2139 md->md.bt_pos = BTC_BT_BTG; 2140 md->md.wa_type = 1; 2141 md->md.ant.diversity = 0; 2142 } else { /* ant.num == 2 */ 2143 md->md.ant.type = BTC_ANT_DEDICATED; 2144 md->md.bt_pos = BTC_BT_ALONE; 2145 md->md.switch_type = BTC_SWITCH_EXTERNAL; 2146 md->md.wa_type = 0; 2147 if (md->md.rfe_type % 3 == 2) 2148 md->md.ant.diversity = 1; 2149 } 2150 rtwdev->btc.btg_pos = md->md.ant.btg_pos; 2151 rtwdev->btc.ant_type = md->md.ant.type; 2152 } 2153} 2154 2155static 2156void rtw8851b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 2157{ 2158 if (group > BTC_BT_SS_GROUP) 2159 group--; /* Tx-group=1, Rx-group=2 */ 2160 2161 if (rtwdev->btc.ant_type == BTC_ANT_SHARED) /* 1-Ant */ 2162 group += 3; 2163 2164 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group); 2165 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val); 2166} 2167 2168static void rtw8851b_btc_init_cfg(struct rtw89_dev *rtwdev) 2169{ 2170 static const struct rtw89_mac_ax_coex coex_params = { 2171 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 2172 .direction = RTW89_MAC_AX_COEX_INNER, 2173 }; 2174 const struct rtw89_chip_info *chip = rtwdev->chip; 2175 struct rtw89_btc *btc = &rtwdev->btc; 2176 union rtw89_btc_module_info *md = &btc->mdinfo; 2177 const struct rtw89_btc_ver *ver = btc->ver; 2178 u8 path, path_min, path_max, str_cnt, ant_sing_pos; 2179 2180 /* PTA init */ 2181 rtw89_mac_coex_init(rtwdev, &coex_params); 2182 2183 /* set WL Tx response = Hi-Pri */ 2184 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 2185 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 2186 2187 if (ver->fcxinit == 7) { 2188 str_cnt = md->md_v7.ant.stream_cnt; 2189 ant_sing_pos = md->md_v7.ant.single_pos; 2190 } else { 2191 str_cnt = md->md.ant.stream_cnt; 2192 ant_sing_pos = md->md.ant.single_pos; 2193 } 2194 2195 /* for 1-Ant && 1-ss case: only 1-path */ 2196 if (str_cnt == 1) { 2197 path_min = ant_sing_pos; 2198 path_max = path_min; 2199 } else { 2200 path_min = RF_PATH_A; 2201 path_max = RF_PATH_B; 2202 } 2203 2204 for (path = path_min; path <= path_max; path++) { 2205 /* set rf gnt-debug off */ 2206 rtw89_write_rf(rtwdev, path, RR_WLSEL, RFREG_MASK, 0x0); 2207 2208 /* set DEBUG_LUT_RFMODE_MASK = 1 to start trx-mask-setup */ 2209 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, BIT(17)); 2210 2211 /* if GNT_WL=0 && BT=SS_group --> WL Tx/Rx = THRU */ 2212 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_SS_GROUP, 0x5ff); 2213 2214 /* if GNT_WL=0 && BT=Rx_group --> WL-Rx = THRU + WL-Tx = MASK */ 2215 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_RX_GROUP, 0x5df); 2216 2217 /* if GNT_WL = 0 && BT = Tx_group --> 2218 * Shared-Ant && BTG-path:WL mask(0x55f), others:WL THRU(0x5ff) 2219 */ 2220 if (btc->ant_type == BTC_ANT_SHARED && btc->btg_pos == path) 2221 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x55f); 2222 else 2223 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x5ff); 2224 2225 /* set DEBUG_LUT_RFMODE_MASK = 0 to stop trx-mask-setup */ 2226 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0); 2227 } 2228 2229 /* set PTA break table */ 2230 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); 2231 2232 /* enable BT counter 0xda40[16,2] = 2b'11 */ 2233 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); 2234 2235 btc->cx.wl.status.map.init_ok = true; 2236} 2237 2238static 2239void rtw8851b_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 2240{ 2241 u32 bitmap; 2242 u32 reg; 2243 2244 switch (map) { 2245 case BTC_PRI_MASK_TX_RESP: 2246 reg = R_BTC_BT_COEX_MSK_TABLE; 2247 bitmap = B_BTC_PRI_MASK_TX_RESP_V1; 2248 break; 2249 case BTC_PRI_MASK_BEACON: 2250 reg = R_AX_WL_PRI_MSK; 2251 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; 2252 break; 2253 case BTC_PRI_MASK_RX_CCK: 2254 reg = R_BTC_BT_COEX_MSK_TABLE; 2255 bitmap = B_BTC_PRI_MASK_RXCCK_V1; 2256 break; 2257 default: 2258 return; 2259 } 2260 2261 if (state) 2262 rtw89_write32_set(rtwdev, reg, bitmap); 2263 else 2264 rtw89_write32_clr(rtwdev, reg, bitmap); 2265} 2266 2267union rtw8851b_btc_wl_txpwr_ctrl { 2268 u32 txpwr_val; 2269 struct { 2270 union { 2271 u16 ctrl_all_time; 2272 struct { 2273 s16 data:9; 2274 u16 rsvd:6; 2275 u16 flag:1; 2276 } all_time; 2277 }; 2278 union { 2279 u16 ctrl_gnt_bt; 2280 struct { 2281 s16 data:9; 2282 u16 rsvd:7; 2283 } gnt_bt; 2284 }; 2285 }; 2286} __packed; 2287 2288static void 2289rtw8851b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 2290{ 2291 union rtw8851b_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val }; 2292 s32 val; 2293 2294#define __write_ctrl(_reg, _msk, _val, _en, _cond) \ 2295do { \ 2296 u32 _wrt = FIELD_PREP(_msk, _val); \ 2297 BUILD_BUG_ON(!!(_msk & _en)); \ 2298 if (_cond) \ 2299 _wrt |= _en; \ 2300 else \ 2301 _wrt &= ~_en; \ 2302 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \ 2303 _msk | _en, _wrt); \ 2304} while (0) 2305 2306 switch (arg.ctrl_all_time) { 2307 case 0xffff: 2308 val = 0; 2309 break; 2310 default: 2311 val = arg.all_time.data; 2312 break; 2313 } 2314 2315 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, 2316 val, B_AX_FORCE_PWR_BY_RATE_EN, 2317 arg.ctrl_all_time != 0xffff); 2318 2319 switch (arg.ctrl_gnt_bt) { 2320 case 0xffff: 2321 val = 0; 2322 break; 2323 default: 2324 val = arg.gnt_bt.data; 2325 break; 2326 } 2327 2328 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val, 2329 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff); 2330 2331#undef __write_ctrl 2332} 2333 2334static 2335s8 rtw8851b_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 2336{ 2337 val = clamp_t(s8, val, -100, 0) + 100; 2338 val = min(val + 6, 100); /* compensate offset */ 2339 2340 return val; 2341} 2342 2343static 2344void rtw8851b_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 2345{ 2346 /* Feature move to firmware */ 2347} 2348 2349static void rtw8851b_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 2350{ 2351 struct rtw89_btc *btc = &rtwdev->btc; 2352 2353 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWE, RFREG_MASK, 0x80000); 2354 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWA, RFREG_MASK, 0x1); 2355 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD1, RFREG_MASK, 0x110); 2356 2357 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 2358 if (state) 2359 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD0, RFREG_MASK, 0x179c); 2360 else 2361 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD0, RFREG_MASK, 0x208); 2362 2363 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWE, RFREG_MASK, 0x0); 2364} 2365 2366#define LNA2_51B_MA 0x700 2367 2368static const struct rtw89_reg2_def btc_8851b_rf_0[] = {{0x2, 0x0}}; 2369static const struct rtw89_reg2_def btc_8851b_rf_1[] = {{0x2, 0x1}}; 2370 2371static void rtw8851b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2372{ 2373 /* To improve BT ACI in co-rx 2374 * level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB 2375 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB 2376 */ 2377 struct rtw89_btc *btc = &rtwdev->btc; 2378 const struct rtw89_reg2_def *rf; 2379 u32 n, i, val; 2380 2381 switch (level) { 2382 case 0: /* original */ 2383 default: 2384 btc->dm.wl_lna2 = 0; 2385 break; 2386 case 1: /* for FDD free-run */ 2387 btc->dm.wl_lna2 = 0; 2388 break; 2389 case 2: /* for BTG Co-Rx*/ 2390 btc->dm.wl_lna2 = 1; 2391 break; 2392 } 2393 2394 if (btc->dm.wl_lna2 == 0) { 2395 rf = btc_8851b_rf_0; 2396 n = ARRAY_SIZE(btc_8851b_rf_0); 2397 } else { 2398 rf = btc_8851b_rf_1; 2399 n = ARRAY_SIZE(btc_8851b_rf_1); 2400 } 2401 2402 for (i = 0; i < n; i++, rf++) { 2403 val = rf->data; 2404 /* bit[10] = 1 if non-shared-ant for 8851b */ 2405 if (btc->ant_type == BTC_ANT_DEDICATED) 2406 val |= 0x4; 2407 2408 rtw89_write_rf(rtwdev, btc->btg_pos, rf->addr, LNA2_51B_MA, val); 2409 } 2410} 2411 2412static void rtw8851b_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2413 struct rtw89_rx_phy_ppdu *phy_ppdu, 2414 struct ieee80211_rx_status *status) 2415{ 2416 u16 chan = phy_ppdu->chan_idx; 2417 enum nl80211_band band; 2418 u8 ch; 2419 2420 if (chan == 0) 2421 return; 2422 2423 rtw89_decode_chan_idx(rtwdev, chan, &ch, &band); 2424 status->freq = ieee80211_channel_to_frequency(ch, band); 2425 status->band = band; 2426} 2427 2428static void rtw8851b_query_ppdu(struct rtw89_dev *rtwdev, 2429 struct rtw89_rx_phy_ppdu *phy_ppdu, 2430 struct ieee80211_rx_status *status) 2431{ 2432 u8 path; 2433 u8 *rx_power = phy_ppdu->rssi; 2434 2435 if (!status->signal) 2436 status->signal = RTW89_RSSI_RAW_TO_DBM(rx_power[RF_PATH_A]); 2437 2438 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2439 status->chains |= BIT(path); 2440 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2441 } 2442 if (phy_ppdu->valid) 2443 rtw8851b_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2444} 2445 2446static int rtw8851b_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 2447{ 2448 int ret; 2449 2450 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 2451 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2452 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2453 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2454 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2455 2456 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7, 2457 FULL_BIT_MASK); 2458 if (ret) 2459 return ret; 2460 2461 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7, 2462 FULL_BIT_MASK); 2463 if (ret) 2464 return ret; 2465 2466 rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE); 2467 2468 return 0; 2469} 2470 2471static int rtw8851b_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 2472{ 2473 u8 wl_rfc_s0; 2474 u8 wl_rfc_s1; 2475 int ret; 2476 2477 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2478 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 2479 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2480 2481 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0); 2482 if (ret) 2483 return ret; 2484 wl_rfc_s0 &= ~XTAL_SI_RF00S_EN; 2485 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0, 2486 FULL_BIT_MASK); 2487 if (ret) 2488 return ret; 2489 2490 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1); 2491 if (ret) 2492 return ret; 2493 wl_rfc_s1 &= ~XTAL_SI_RF10S_EN; 2494 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1, 2495 FULL_BIT_MASK); 2496 return ret; 2497} 2498 2499static const struct rtw89_chip_ops rtw8851b_chip_ops = { 2500 .enable_bb_rf = rtw8851b_mac_enable_bb_rf, 2501 .disable_bb_rf = rtw8851b_mac_disable_bb_rf, 2502 .bb_preinit = NULL, 2503 .bb_postinit = NULL, 2504 .bb_reset = rtw8851b_bb_reset, 2505 .bb_sethw = rtw8851b_bb_sethw, 2506 .read_rf = rtw89_phy_read_rf_v1, 2507 .write_rf = rtw89_phy_write_rf_v1, 2508 .set_channel = rtw8851b_set_channel, 2509 .set_channel_help = rtw8851b_set_channel_help, 2510 .read_efuse = rtw8851b_read_efuse, 2511 .read_phycap = rtw8851b_read_phycap, 2512 .fem_setup = NULL, 2513 .rfe_gpio = rtw8851b_rfe_gpio, 2514 .rfk_hw_init = NULL, 2515 .rfk_init = rtw8851b_rfk_init, 2516 .rfk_init_late = NULL, 2517 .rfk_channel = rtw8851b_rfk_channel, 2518 .rfk_band_changed = rtw8851b_rfk_band_changed, 2519 .rfk_scan = rtw8851b_rfk_scan, 2520 .rfk_track = rtw8851b_rfk_track, 2521 .power_trim = rtw8851b_power_trim, 2522 .set_txpwr = rtw8851b_set_txpwr, 2523 .set_txpwr_ctrl = rtw8851b_set_txpwr_ctrl, 2524 .init_txpwr_unit = rtw8851b_init_txpwr_unit, 2525 .get_thermal = rtw8851b_get_thermal, 2526 .chan_to_rf18_val = NULL, 2527 .ctrl_btg_bt_rx = rtw8851b_ctrl_btg_bt_rx, 2528 .query_ppdu = rtw8851b_query_ppdu, 2529 .convert_rpl_to_rssi = NULL, 2530 .phy_rpt_to_rssi = NULL, 2531 .ctrl_nbtg_bt_tx = rtw8851b_ctrl_nbtg_bt_tx, 2532 .cfg_txrx_path = rtw8851b_bb_cfg_txrx_path, 2533 .set_txpwr_ul_tb_offset = rtw8851b_set_txpwr_ul_tb_offset, 2534 .digital_pwr_comp = NULL, 2535 .pwr_on_func = rtw8851b_pwr_on_func, 2536 .pwr_off_func = rtw8851b_pwr_off_func, 2537 .query_rxdesc = rtw89_core_query_rxdesc, 2538 .fill_txdesc = rtw89_core_fill_txdesc, 2539 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 2540 .get_ch_dma = {rtw89_core_get_ch_dma, 2541 rtw89_core_get_ch_dma, 2542 NULL,}, 2543 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 2544 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 2545 .stop_sch_tx = rtw89_mac_stop_sch_tx, 2546 .resume_sch_tx = rtw89_mac_resume_sch_tx, 2547 .h2c_dctl_sec_cam = NULL, 2548 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl, 2549 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl, 2550 .h2c_ampdu_cmac_tbl = NULL, 2551 .h2c_txtime_cmac_tbl = rtw89_fw_h2c_txtime_cmac_tbl, 2552 .h2c_punctured_cmac_tbl = NULL, 2553 .h2c_default_dmac_tbl = NULL, 2554 .h2c_update_beacon = rtw89_fw_h2c_update_beacon, 2555 .h2c_ba_cam = rtw89_fw_h2c_ba_cam, 2556 2557 .btc_set_rfe = rtw8851b_btc_set_rfe, 2558 .btc_init_cfg = rtw8851b_btc_init_cfg, 2559 .btc_set_wl_pri = rtw8851b_btc_set_wl_pri, 2560 .btc_set_wl_txpwr_ctrl = rtw8851b_btc_set_wl_txpwr_ctrl, 2561 .btc_get_bt_rssi = rtw8851b_btc_get_bt_rssi, 2562 .btc_update_bt_cnt = rtw8851b_btc_update_bt_cnt, 2563 .btc_wl_s1_standby = rtw8851b_btc_wl_s1_standby, 2564 .btc_set_wl_rx_gain = rtw8851b_btc_set_wl_rx_gain, 2565 .btc_set_policy = rtw89_btc_set_policy_v1, 2566}; 2567 2568#ifdef CONFIG_PM 2569static const struct wiphy_wowlan_support rtw_wowlan_stub_8851b = { 2570 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 2571 .n_patterns = RTW89_MAX_PATTERN_NUM, 2572 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 2573 .pattern_min_len = 1, 2574}; 2575#endif 2576 2577const struct rtw89_chip_info rtw8851b_chip_info = { 2578 .chip_id = RTL8851B, 2579 .chip_gen = RTW89_CHIP_AX, 2580 .ops = &rtw8851b_chip_ops, 2581 .mac_def = &rtw89_mac_gen_ax, 2582 .phy_def = &rtw89_phy_gen_ax, 2583 .fw_basename = RTW8851B_FW_BASENAME, 2584 .fw_format_max = RTW8851B_FW_FORMAT_MAX, 2585 .try_ce_fw = true, 2586 .bbmcu_nr = 0, 2587 .needed_fw_elms = 0, 2588 .fw_blacklist = NULL, 2589 .fifo_size = 196608, 2590 .small_fifo_size = true, 2591 .dle_scc_rsvd_size = 98304, 2592 .max_amsdu_limit = 3500, 2593 .dis_2g_40m_ul_ofdma = true, 2594 .rsvd_ple_ofst = 0x2f800, 2595 .hfc_param_ini = {rtw8851b_hfc_param_ini_pcie, 2596 rtw8851b_hfc_param_ini_usb, 2597 NULL}, 2598 .dle_mem = {rtw8851b_dle_mem_pcie, 2599 rtw8851b_dle_mem_usb2, 2600 rtw8851b_dle_mem_usb3, 2601 NULL}, 2602 .wde_qempty_acq_grpnum = 4, 2603 .wde_qempty_mgq_grpsel = 4, 2604 .rf_base_addr = {0xe000}, 2605 .thermal_th = {0x32, 0x35}, 2606 .pwr_on_seq = NULL, 2607 .pwr_off_seq = NULL, 2608 .bb_table = &rtw89_8851b_phy_bb_table, 2609 .bb_gain_table = &rtw89_8851b_phy_bb_gain_table, 2610 .rf_table = {&rtw89_8851b_phy_radioa_table,}, 2611 .nctl_table = &rtw89_8851b_phy_nctl_table, 2612 .nctl_post_table = &rtw8851b_nctl_post_defs_tbl, 2613 .dflt_parms = &rtw89_8851b_dflt_parms, 2614 .rfe_parms_conf = rtw89_8851b_rfe_parms_conf, 2615 .txpwr_factor_bb = 3, 2616 .txpwr_factor_rf = 2, 2617 .txpwr_factor_mac = 1, 2618 .dig_table = NULL, 2619 .dig_regs = &rtw8851b_dig_regs, 2620 .tssi_dbw_table = NULL, 2621 .support_macid_num = RTW89_MAX_MAC_ID_NUM, 2622 .support_link_num = 0, 2623 .support_chanctx_num = 0, 2624 .support_rnr = false, 2625 .support_bands = BIT(NL80211_BAND_2GHZ) | 2626 BIT(NL80211_BAND_5GHZ), 2627 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) | 2628 BIT(NL80211_CHAN_WIDTH_40) | 2629 BIT(NL80211_CHAN_WIDTH_80), 2630 .support_unii4 = true, 2631 .support_ant_gain = false, 2632 .support_tas = false, 2633 .support_sar_by_ant = false, 2634 .support_noise = false, 2635 .ul_tb_waveform_ctrl = true, 2636 .ul_tb_pwr_diff = false, 2637 .rx_freq_frome_ie = true, 2638 .hw_sec_hdr = false, 2639 .hw_mgmt_tx_encrypt = false, 2640 .hw_tkip_crypto = false, 2641 .hw_mlo_bmc_crypto = false, 2642 .rf_path_num = 1, 2643 .tx_nss = 1, 2644 .rx_nss = 1, 2645 .acam_num = 32, 2646 .bcam_num = 20, 2647 .scam_num = 128, 2648 .bacam_num = 2, 2649 .bacam_dynamic_num = 4, 2650 .bacam_ver = RTW89_BACAM_V0, 2651 .addrcam_ver = 0, 2652 .ppdu_max_usr = 4, 2653 .sec_ctrl_efuse_size = 4, 2654 .physical_efuse_size = 1216, 2655 .logical_efuse_size = 2048, 2656 .limit_efuse_size = 1280, 2657 .dav_phy_efuse_size = 0, 2658 .dav_log_efuse_size = 0, 2659 .efuse_blocks = NULL, 2660 .phycap_addr = 0x580, 2661 .phycap_size = 128, 2662 .para_ver = 0, 2663 .wlcx_desired = 0x06000000, 2664 .scbd = 0x1, 2665 .mailbox = 0x1, 2666 2667 .afh_guard_ch = 6, 2668 .wl_rssi_thres = rtw89_btc_8851b_wl_rssi_thres, 2669 .bt_rssi_thres = rtw89_btc_8851b_bt_rssi_thres, 2670 .rssi_tol = 2, 2671 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8851b_mon_reg), 2672 .mon_reg = rtw89_btc_8851b_mon_reg, 2673 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8851b_rf_ul), 2674 .rf_para_ulink = rtw89_btc_8851b_rf_ul, 2675 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8851b_rf_dl), 2676 .rf_para_dlink = rtw89_btc_8851b_rf_dl, 2677 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2678 BIT(RTW89_PS_MODE_CLK_GATED), 2679 .low_power_hci_modes = 0, 2680 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD, 2681 .hci_func_en_addr = R_AX_HCI_FUNC_EN, 2682 .h2c_desc_size = sizeof(struct rtw89_txwd_body), 2683 .txwd_body_size = sizeof(struct rtw89_txwd_body), 2684 .txwd_info_size = sizeof(struct rtw89_txwd_info), 2685 .h2c_ctrl_reg = R_AX_H2CREG_CTRL, 2686 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 2687 .h2c_regs = rtw8851b_h2c_regs, 2688 .c2h_ctrl_reg = R_AX_C2HREG_CTRL, 2689 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 2690 .c2h_regs = rtw8851b_c2h_regs, 2691 .page_regs = &rtw8851b_page_regs, 2692 .wow_reason_reg = rtw8851b_wow_wakeup_regs, 2693 .cfo_src_fd = true, 2694 .cfo_hw_comp = true, 2695 .dcfo_comp = &rtw8851b_dcfo_comp, 2696 .dcfo_comp_sft = 12, 2697 .nhm_report = NULL, 2698 .nhm_th = NULL, 2699 .imr_info = &rtw8851b_imr_info, 2700 .imr_dmac_table = NULL, 2701 .imr_cmac_table = NULL, 2702 .rrsr_cfgs = &rtw8851b_rrsr_cfgs, 2703 .bss_clr_vld = {R_BSS_CLR_MAP_V1, B_BSS_CLR_MAP_VLD0}, 2704 .bss_clr_map_reg = R_BSS_CLR_MAP_V1, 2705 .rfkill_init = &rtw8851b_rfkill_regs, 2706 .rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9}, 2707 .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) | 2708 BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) | 2709 BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI), 2710 .edcca_regs = &rtw8851b_edcca_regs, 2711#ifdef CONFIG_PM 2712 .wowlan_stub = &rtw_wowlan_stub_8851b, 2713#endif 2714 .xtal_info = &rtw8851b_xtal_info, 2715}; 2716EXPORT_SYMBOL(rtw8851b_chip_info); 2717 2718MODULE_FIRMWARE(RTW8851B_MODULE_FIRMWARE); 2719MODULE_AUTHOR("Realtek Corporation"); 2720MODULE_DESCRIPTION("Realtek 802.11ax wireless 8851B driver"); 2721MODULE_LICENSE("Dual BSD/GPL");
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