reg.h

   1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2/* Copyright(c) 2019-2020  Realtek Corporation
   3 */
   4
   5#ifndef __RTW89_REG_H__
   6#define __RTW89_REG_H__
   7
   8#define R_AX_SYS_WL_EFUSE_CTRL 0x000A
   9#define B_AX_AUTOLOAD_SUS BIT(5)
  10
  11#define R_AX_SYS_ISO_CTRL 0x0000
  12#define B_AX_PWC_EV2EF_MASK GENMASK(15, 14)
  13#define B_AX_PWC_EV2EF_B15 BIT(15)
  14#define B_AX_PWC_EV2EF_B14 BIT(14)
  15#define B_AX_ISO_EB2CORE BIT(8)
  16
  17#define R_AX_SYS_FUNC_EN 0x0002
  18#define B_AX_FEN_BB_GLB_RSTN BIT(1)
  19#define B_AX_FEN_BBRSTB BIT(0)
  20
  21#define R_AX_SYS_PW_CTRL 0x0004
  22#define B_AX_SOP_ASWRM BIT(31)
  23#define B_AX_SOP_PWMM_DSWR BIT(29)
  24#define B_AX_SOP_EDSWR BIT(28)
  25#define B_AX_XTAL_OFF_A_DIE BIT(22)
  26#define B_AX_DIS_WLBT_PDNSUSEN_SOPC BIT(18)
  27#define B_AX_RDY_SYSPWR BIT(17)
  28#define B_AX_EN_WLON BIT(16)
  29#define B_AX_APDM_HPDN BIT(15)
  30#define B_AX_PSUS_OFF_CAPC_EN BIT(14)
  31#define B_AX_AFSM_PCIE_SUS_EN BIT(12)
  32#define B_AX_AFSM_WLSUS_EN BIT(11)
  33#define B_AX_APFM_SWLPS BIT(10)
  34#define B_AX_APFM_OFFMAC BIT(9)
  35#define B_AX_APFN_ONMAC BIT(8)
  36
  37#define R_AX_SYS_CLK_CTRL 0x0008
  38#define B_AX_CPU_CLK_EN BIT(14)
  39
  40#define R_AX_SYS_SWR_CTRL1 0x0010
  41#define B_AX_SYM_CTRL_SPS_PWMFREQ BIT(10)
  42
  43#define R_AX_SYS_ADIE_PAD_PWR_CTRL 0x0018
  44#define B_AX_SYM_PADPDN_WL_PTA_1P3 BIT(6)
  45#define B_AX_SYM_PADPDN_WL_RFC_1P3 BIT(5)
  46
  47#define R_AX_RSV_CTRL 0x001C
  48#define B_AX_R_DIS_PRST BIT(6)
  49#define B_AX_WLOCK_1C_BIT6 BIT(5)
  50
  51#define R_AX_AFE_LDO_CTRL 0x0020
  52#define B_AX_AON_OFF_PC_EN BIT(23)
  53
  54#define R_AX_EFUSE_CTRL_1 0x0038
  55#define B_AX_EF_PGPD_MASK GENMASK(30, 28)
  56#define B_AX_EF_RDT BIT(27)
  57#define B_AX_EF_VDDQST_MASK GENMASK(26, 24)
  58#define B_AX_EF_PGTS_MASK GENMASK(23, 20)
  59#define B_AX_EF_PD_DIS BIT(11)
  60#define B_AX_EF_POR BIT(10)
  61#define B_AX_EF_CELL_SEL_MASK GENMASK(9, 8)
  62
  63#define R_AX_EFUSE_CTRL 0x0030
  64#define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30)
  65#define B_AX_EF_RDY BIT(29)
  66#define B_AX_EF_COMP_RESULT BIT(28)
  67#define B_AX_EF_ADDR_MASK GENMASK(26, 16)
  68#define B_AX_EF_DATA_MASK GENMASK(15, 0)
  69
  70#define R_AX_EFUSE_CTRL_1_V1 0x0038
  71#define B_AX_EF_ENT BIT(31)
  72#define B_AX_EF_BURST BIT(19)
  73#define B_AX_EF_TEST_SEL_MASK GENMASK(18, 16)
  74#define B_AX_EF_TROW_EN BIT(15)
  75#define B_AX_EF_ERR_FLAG BIT(14)
  76#define B_AX_EF_DSB_EN BIT(11)
  77#define B_AX_PCIE_CALIB_EN_V1 BIT(12)
  78#define B_AX_WDT_WAKE_PCIE_EN BIT(10)
  79#define B_AX_WDT_WAKE_USB_EN BIT(9)
  80
  81#define R_AX_GPIO_MUXCFG 0x0040
  82#define B_AX_BOOT_MODE BIT(19)
  83#define B_AX_WL_EECS_EXT_32K_SEL BIT(18)
  84#define B_AX_WL_SEC_BONDING_OPT_STS BIT(17)
  85#define B_AX_SECSIC_SEL BIT(16)
  86#define B_AX_ENHTP BIT(14)
  87#define B_AX_BT_AOD_GPIO3 BIT(13)
  88#define B_AX_ENSIC BIT(12)
  89#define B_AX_SIC_SWRST BIT(11)
  90#define B_AX_PO_WIFI_PTA_PINS BIT(10)
  91#define B_AX_PO_BT_PTA_PINS BIT(9)
  92#define B_AX_ENUARTTX BIT(8)
  93#define B_AX_BTMODE_MASK GENMASK(7, 6)
  94#define MAC_AX_BT_MODE_0_3 0
  95#define MAC_AX_BT_MODE_2 2
  96#define MAC_AX_RTK_MODE 0
  97#define MAC_AX_CSR_MODE 1
  98#define B_AX_ENBT BIT(5)
  99#define B_AX_EROM_EN BIT(4)
 100#define B_AX_ENUARTRX BIT(2)
 101#define B_AX_GPIOSEL_MASK GENMASK(1, 0)
 102
 103#define R_AX_DBG_CTRL 0x0058
 104#define B_AX_DBG_SEL1_4BIT GENMASK(31, 30)
 105#define B_AX_DBG_SEL1_16BIT BIT(27)
 106#define B_AX_DBG_SEL1 GENMASK(23, 16)
 107#define B_AX_DBG_SEL0_4BIT GENMASK(15, 14)
 108#define B_AX_DBG_SEL0_16BIT BIT(11)
 109#define B_AX_DBG_SEL0 GENMASK(7, 0)
 110
 111#define R_AX_GPIO_EXT_CTRL 0x0060
 112#define B_AX_GPIO_MOD_15_TO_8_MASK GENMASK(31, 24)
 113#define B_AX_GPIO_MOD_9 BIT(25)
 114#define B_AX_GPIO_IO_SEL_15_TO_8_MASK GENMASK(23, 16)
 115#define B_AX_GPIO_IO_SEL_9 BIT(17)
 116#define B_AX_GPIO_OUT_15_TO_8_MASK GENMASK(15, 8)
 117#define B_AX_GPIO_IN_15_TO_8_MASK GENMASK(7, 0)
 118#define B_AX_GPIO_IN_9 BIT(1)
 119
 120#define R_AX_SYS_SDIO_CTRL 0x0070
 121#define B_AX_PCIE_DIS_L2_CTRL_LDO_HCI BIT(15)
 122#define B_AX_PCIE_DIS_WLSUS_AFT_PDN BIT(14)
 123#define B_AX_PCIE_FORCE_PWR_NGAT BIT(13)
 124#define B_AX_PCIE_CALIB_EN_V1 BIT(12)
 125#define B_AX_PCIE_AUXCLK_GATE BIT(11)
 126#define B_AX_LTE_MUX_CTRL_PATH BIT(26)
 127
 128#define R_AX_HCI_OPT_CTRL 0x0074
 129#define BIT_WAKE_CTRL_V1 BIT(23)
 130#define BIT_WAKE_CTRL BIT(5)
 131
 132#define R_AX_HCI_BG_CTRL 0x0078
 133#define B_AX_IBX_EN_VALUE BIT(15)
 134#define B_AX_IB_EN_VALUE BIT(14)
 135#define B_AX_FORCED_IB_EN BIT(4)
 136#define B_AX_EN_REGBG BIT(3)
 137#define B_AX_R_AX_BG_LPF BIT(2)
 138#define B_AX_R_AX_BG GENMASK(1, 0)
 139
 140#define R_AX_HCI_LDO_CTRL 0x007A
 141#define B_AX_R_AX_VADJ_MASK GENMASK(3, 0)
 142
 143#define R_AX_PLATFORM_ENABLE 0x0088
 144#define B_AX_AXIDMA_EN BIT(3)
 145#define B_AX_APB_WRAP_EN BIT(2)
 146#define B_AX_WCPU_EN BIT(1)
 147#define B_AX_PLATFORM_EN BIT(0)
 148
 149#define R_AX_WLLPS_CTRL 0x0090
 150#define B_AX_LPSOP_ASWRM BIT(17)
 151#define B_AX_LPSOP_DSWRM BIT(9)
 152#define B_AX_DIS_WLBT_LPSEN_LOPC BIT(1)
 153#define SW_LPS_OPTION 0x0001A0B2
 154
 155#define R_AX_SCOREBOARD  0x00AC
 156#define B_AX_TOGGLE BIT(31)
 157#define B_MAC_AX_SB_FW_MASK GENMASK(30, 24)
 158#define B_MAC_AX_SB_DRV_MASK GENMASK(23, 0)
 159#define B_MAC_AX_BTGS1_NOTIFY BIT(0)
 160#define MAC_AX_NOTIFY_TP_MAJOR 0x81
 161#define MAC_AX_NOTIFY_PWR_MAJOR 0x80
 162
 163#define R_AX_DBG_PORT_SEL 0x00C0
 164#define B_AX_DEBUG_ST_MASK GENMASK(31, 0)
 165
 166#define R_AX_PMC_DBG_CTRL2 0x00CC
 167#define B_AX_SYSON_DIS_PMCR_AX_WRMSK BIT(2)
 168
 169#define R_AX_PCIE_MIO_INTF 0x00E4
 170#define B_AX_PCIE_MIO_ADDR_PAGE_V1_MASK GENMASK(20, 16)
 171#define B_AX_PCIE_MIO_BYIOREG BIT(13)
 172#define B_AX_PCIE_MIO_RE BIT(12)
 173#define B_AX_PCIE_MIO_WE_MASK GENMASK(11, 8)
 174#define MIO_WRITE_BYTE_ALL 0xF
 175#define B_AX_PCIE_MIO_ADDR_MASK GENMASK(7, 0)
 176#define MIO_ADDR_PAGE_MASK GENMASK(12, 8)
 177
 178#define R_AX_PCIE_MIO_INTD 0x00E8
 179#define B_AX_PCIE_MIO_DATA_MASK GENMASK(31, 0)
 180
 181#define R_AX_SYS_CFG1 0x00F0
 182#define B_AX_CHIP_VER_MASK GENMASK(15, 12)
 183
 184#define R_AX_SYS_STATUS1 0x00F4
 185#define B_AX_SEL_0XC0_MASK GENMASK(17, 16)
 186#define B_AX_AUTO_WLPON BIT(10)
 187#define B_AX_PAD_HCI_SEL_V2_MASK GENMASK(5, 3)
 188#define MAC_AX_HCI_SEL_SDIO_UART 0
 189#define MAC_AX_HCI_SEL_MULTI_USB 1
 190#define MAC_AX_HCI_SEL_PCIE_UART 2
 191#define MAC_AX_HCI_SEL_PCIE_USB 3
 192#define MAC_AX_HCI_SEL_MULTI_SDIO 4
 193
 194#define R_AX_HALT_H2C_CTRL 0x0160
 195#define R_AX_HALT_H2C 0x0168
 196#define B_AX_HALT_H2C_TRIGGER BIT(0)
 197#define R_AX_HALT_C2H_CTRL 0x0164
 198#define R_AX_HALT_C2H 0x016C
 199
 200#define R_AX_WCPU_FW_CTRL 0x01E0
 201#define B_AX_IDMEM_SHARE_MODE_RECORD_MASK GENMASK(27, 24)
 202#define B_AX_IDMEM_SHARE_MODE_RECORD_VALID BIT(23)
 203#define B_AX_WCPU_FWDL_STS_MASK GENMASK(7, 5)
 204#define B_AX_FWDL_PATH_RDY BIT(2)
 205#define B_AX_H2C_PATH_RDY BIT(1)
 206#define B_AX_WCPU_FWDL_EN BIT(0)
 207
 208#define R_AX_RPWM 0x01E4
 209#define R_AX_PCIE_HRPWM 0x10C0
 210#define PS_RPWM_TOGGLE BIT(15)
 211#define PS_RPWM_ACK BIT(14)
 212#define PS_RPWM_SEQ_NUM GENMASK(13, 12)
 213#define PS_RPWM_NOTIFY_WAKE BIT(8)
 214#define PS_RPWM_STATE 0x7
 215#define RPWM_SEQ_NUM_MAX 3
 216#define PS_CPWM_SEQ_NUM GENMASK(13, 12)
 217#define PS_CPWM_RSP_SEQ_NUM GENMASK(9, 8)
 218#define PS_CPWM_STATE GENMASK(2, 0)
 219#define CPWM_SEQ_NUM_MAX 3
 220
 221#define R_AX_BOOT_REASON 0x01E6
 222#define B_AX_BOOT_REASON_MASK GENMASK(2, 0)
 223
 224#define R_AX_LDM 0x01E8
 225#define B_AX_EN_32K BIT(31)
 226
 227#define R_AX_UDM0 0x01F0
 228#define R_AX_UDM1 0x01F4
 229#define B_AX_UDM1_MASK GENMASK(31, 16)
 230#define B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK GENMASK(15, 12)
 231#define B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK GENMASK(11, 8)
 232#define B_AX_UDM1_WCPU_C2H_ENQ_CNT_MASK GENMASK(7, 4)
 233#define B_AX_UDM1_WCPU_H2C_DEQ_CNT_MASK GENMASK(3, 0)
 234#define R_AX_UDM2 0x01F8
 235#define R_AX_UDM3 0x01FC
 236
 237#define R_AX_SPS_DIG_ON_CTRL0 0x0200
 238#define B_AX_VREFPFM_L_MASK GENMASK(25, 22)
 239#define B_AX_REG_ZCDC_H_MASK GENMASK(18, 17)
 240#define B_AX_OCP_L1_MASK GENMASK(15, 13)
 241#define B_AX_VOL_L1_MASK GENMASK(3, 0)
 242
 243#define R_AX_SPSLDO_ON_CTRL1 0x0204
 244#define B_AX_FPWMDELAY BIT(3)
 245
 246#define R_AX_LDO_AON_CTRL0 0x0218
 247#define B_AX_PD_REGU_L BIT(16)
 248
 249#define R_AX_SPSANA_ON_CTRL1 0x0224
 250
 251#define R_AX_SPS_ANA_ON_CTRL2 0x0228
 252#define RTL8852B_RFE_05_SPS_ANA 0x4A82
 253
 254#define R_AX_WLAN_XTAL_SI_CTRL 0x0270
 255#define B_AX_WL_XTAL_SI_CMD_POLL BIT(31)
 256#define B_AX_BT_XTAL_SI_ERR_FLAG BIT(30)
 257#define B_AX_WL_XTAL_GNT BIT(29)
 258#define B_AX_BT_XTAL_GNT BIT(28)
 259#define B_AX_WL_XTAL_SI_MODE_MASK GENMASK(25, 24)
 260#define XTAL_SI_NORMAL_WRITE 0x00
 261#define XTAL_SI_NORMAL_READ 0x01
 262#define B_AX_WL_XTAL_SI_BITMASK_MASK GENMASK(23, 16)
 263#define B_AX_WL_XTAL_SI_DATA_MASK GENMASK(15, 8)
 264#define B_AX_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0)
 265
 266#define R_AX_WLAN_XTAL_SI_CONFIG 0x0274
 267#define B_AX_XTAL_SI_ADDR_NOT_CHK BIT(0)
 268
 269#define R_AX_XTAL_ON_CTRL0 0x0280
 270#define B_AX_XTAL_SC_LPS BIT(31)
 271#define B_AX_XTAL_SC_XO_MASK GENMASK(23, 17)
 272#define B_AX_XTAL_SC_XI_MASK GENMASK(16, 10)
 273#define B_AX_XTAL_SC_MASK GENMASK(6, 0)
 274
 275#define R_AX_XTAL_ON_CTRL3 0x028C
 276#define B_AX_XTAL_SC_INIT_A_BLOCK_MASK GENMASK(30, 24)
 277#define B_AX_XTAL_SC_LPS_A_BLOCK_MASK GENMASK(22, 16)
 278#define B_AX_XTAL_SC_XO_A_BLOCK_MASK GENMASK(14, 8)
 279#define B_AX_XTAL_SC_XI_A_BLOCK_MASK GENMASK(6, 0)
 280
 281#define R_AX_GPIO0_7_FUNC_SEL 0x02D0
 282
 283#define R_AX_GPIO8_15_FUNC_SEL 0x02D4
 284#define B_AX_PINMUX_GPIO9_FUNC_SEL_MASK GENMASK(7, 4)
 285
 286#define R_AX_EECS_EESK_FUNC_SEL 0x02D8
 287#define B_AX_PINMUX_EESK_FUNC_SEL_MASK GENMASK(7, 4)
 288
 289#define R_AX_GPIO16_23_FUNC_SEL 0x02D8
 290#define B_AX_PINMUX_GPIO17_FUNC_SEL_MASK GENMASK(7, 4)
 291#define B_AX_PINMUX_GPIO16_FUNC_SEL_MASK GENMASK(3, 0)
 292
 293#define R_AX_LED1_FUNC_SEL 0x02DC
 294#define B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK GENMASK(27, 24)
 295#define PINMUX_EESK_FUNC_SEL_BT_LOG 0x1
 296
 297#define R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN 0x02E4
 298#define B_AX_LED1_PULL_LOW_EN BIT(18)
 299#define B_AX_EESK_PULL_LOW_EN BIT(17)
 300#define B_AX_EECS_PULL_LOW_EN BIT(16)
 301
 302#define R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN 0x02E4
 303#define B_AX_GPIO16_PULL_LOW_EN_V1 BIT(19)
 304#define B_AX_GPIO10_PULL_LOW_EN BIT(10)
 305
 306#define R_AX_WLRF_CTRL 0x02F0
 307#define B_AX_AFC_AFEDIG BIT(17)
 308#define B_AX_WLRF1_CTRL_7 BIT(15)
 309#define B_AX_WLRF1_CTRL_1 BIT(9)
 310#define B_AX_WLRF_CTRL_7 BIT(7)
 311#define B_AX_WLRF_CTRL_1 BIT(1)
 312
 313#define R_AX_IC_PWR_STATE 0x03F0
 314#define B_AX_WHOLE_SYS_PWR_STE_MASK GENMASK(25, 16)
 315#define B_AX_WLMAC_PWR_STE_MASK GENMASK(9, 8)
 316#define B_AX_UART_HCISYS_PWR_STE_MASK GENMASK(7, 6)
 317#define B_AX_SDIO_HCISYS_PWR_STE_MASK GENMASK(5, 4)
 318#define B_AX_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2)
 319#define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)
 320
 321#define R_AX_SPS_DIG_OFF_CTRL0 0x0400
 322#define B_AX_C3_L1_MASK GENMASK(5, 4)
 323#define B_AX_C1_L1_MASK GENMASK(1, 0)
 324
 325#define R_AX_AFE_OFF_CTRL1 0x0444
 326#define B_AX_S1_LDO_VSEL_F_MASK GENMASK(25, 24)
 327#define B_AX_S1_LDO2PWRCUT_F BIT(23)
 328#define B_AX_S0_LDO_VSEL_F_MASK GENMASK(22, 21)
 329
 330#define R_AX_DBG_WOW 0x0504
 331#define B_AX_DBG_WOW_CPU_IO_RX_EN BIT(8)
 332
 333#define R_AX_SEC_CTRL 0x0C00
 334#define B_AX_SEC_IDMEM_SIZE_CONFIG_MASK GENMASK(17, 16)
 335
 336#define R_AX_FILTER_MODEL_ADDR 0x0C04
 337
 338#define R_AX_HAXI_INIT_CFG1 0x1000
 339#define B_AX_WD_ITVL_IDLE_V1_MASK GENMASK(31, 28)
 340#define B_AX_WD_ITVL_ACT_V1_MASK GENMASK(27, 24)
 341#define B_AX_DMA_MODE_MASK GENMASK(19, 18)
 342#define DMA_MOD_PCIE_1B 0x0
 343#define DMA_MOD_PCIE_4B 0x1
 344#define DMA_MOD_USB 0x2
 345#define DMA_MOD_SDIO 0x3
 346#define B_AX_STOP_AXI_MST BIT(17)
 347#define B_AX_HAXI_RST_KEEP_REG BIT(16)
 348#define B_AX_RXHCI_EN_V1 BIT(15)
 349#define B_AX_RXBD_MODE_V1 BIT(14)
 350#define B_AX_HAXI_MAX_RXDMA_MASK GENMASK(9, 8)
 351#define B_AX_TXHCI_EN_V1 BIT(7)
 352#define B_AX_FLUSH_AXI_MST BIT(4)
 353#define B_AX_RST_BDRAM BIT(3)
 354#define B_AX_HAXI_MAX_TXDMA_MASK GENMASK(1, 0)
 355
 356#define R_AX_HAXI_DMA_STOP1 0x1010
 357#define B_AX_STOP_WPDMA BIT(19)
 358#define B_AX_STOP_CH12 BIT(18)
 359#define B_AX_STOP_CH9 BIT(17)
 360#define B_AX_STOP_CH8 BIT(16)
 361#define B_AX_STOP_ACH7 BIT(15)
 362#define B_AX_STOP_ACH6 BIT(14)
 363#define B_AX_STOP_ACH5 BIT(13)
 364#define B_AX_STOP_ACH4 BIT(12)
 365#define B_AX_STOP_ACH3 BIT(11)
 366#define B_AX_STOP_ACH2 BIT(10)
 367#define B_AX_STOP_ACH1 BIT(9)
 368#define B_AX_STOP_ACH0 BIT(8)
 369
 370#define R_AX_HAXI_DMA_BUSY1 0x101C
 371#define B_AX_HAXIIO_BUSY BIT(20)
 372#define B_AX_WPDMA_BUSY BIT(19)
 373#define B_AX_CH12_BUSY BIT(18)
 374#define B_AX_CH9_BUSY BIT(17)
 375#define B_AX_CH8_BUSY BIT(16)
 376#define B_AX_ACH7_BUSY BIT(15)
 377#define B_AX_ACH6_BUSY BIT(14)
 378#define B_AX_ACH5_BUSY BIT(13)
 379#define B_AX_ACH4_BUSY BIT(12)
 380#define B_AX_ACH3_BUSY BIT(11)
 381#define B_AX_ACH2_BUSY BIT(10)
 382#define B_AX_ACH1_BUSY BIT(9)
 383#define B_AX_ACH0_BUSY BIT(8)
 384
 385#define R_AX_USB_ENDPOINT_0 0x1060
 386#define B_AX_EP_IDX GENMASK(3, 0)
 387#define R_AX_USB_ENDPOINT_2 0x1068
 388#define NUMP 0x1
 389#define R_AX_USB_HOST_REQUEST_2 0x1078
 390#define B_AX_R_USBIO_MODE BIT(4)
 391#define R_AX_USB3_MAC_NPI_CONFIG_INTF_0 0x1114
 392#define B_AX_SSPHY_LFPS_FILTER BIT(31)
 393#define R_AX_USB_WLAN0_1 0x1174
 394#define B_AX_USBRX_RST BIT(9)
 395#define B_AX_USBTX_RST BIT(8)
 396
 397#define R_AX_PCIE_DBG_CTRL 0x11C0
 398#define B_AX_DBG_DUMMY_MASK GENMASK(23, 16)
 399#define B_AX_PCIE_DBG_SEL_MASK GENMASK(15, 13)
 400#define B_AX_MRD_TIMEOUT_EN BIT(10)
 401#define B_AX_ASFF_FULL_NO_STK BIT(1)
 402#define B_AX_EN_STUCK_DBG BIT(0)
 403
 404#define R_AX_HAXI_DMA_STOP2 0x11C0
 405#define B_AX_STOP_CH11 BIT(1)
 406#define B_AX_STOP_CH10 BIT(0)
 407
 408#define R_AX_HAXI_DMA_BUSY2 0x11C8
 409#define B_AX_CH11_BUSY BIT(1)
 410#define B_AX_CH10_BUSY BIT(0)
 411
 412#define R_AX_HAXI_DMA_BUSY3 0x1208
 413#define B_AX_RPQ_BUSY BIT(1)
 414#define B_AX_RXQ_BUSY BIT(0)
 415
 416#define R_AX_LTR_DEC_CTRL 0x1600
 417#define B_AX_LTR_IDX_DRV_VLD BIT(16)
 418#define B_AX_LTR_CURR_IDX_DRV_MASK GENMASK(15, 14)
 419#define B_AX_LTR_IDX_FW_VLD BIT(13)
 420#define B_AX_LTR_CURR_IDX_FW_MASK GENMASK(12, 11)
 421#define B_AX_LTR_IDX_HW_VLD BIT(10)
 422#define B_AX_LTR_CURR_IDX_HW_MASK GENMASK(9, 8)
 423#define B_AX_LTR_REQ_DRV BIT(7)
 424#define B_AX_LTR_IDX_DRV_MASK GENMASK(6, 5)
 425#define PCIE_LTR_IDX_IDLE 3
 426#define B_AX_LTR_DRV_DEC_EN BIT(4)
 427#define B_AX_LTR_FW_DEC_EN BIT(3)
 428#define B_AX_LTR_HW_DEC_EN BIT(2)
 429#define B_AX_LTR_SPACE_IDX_V1_MASK GENMASK(1, 0)
 430#define LTR_EN_BITS (B_AX_LTR_HW_DEC_EN | B_AX_LTR_FW_DEC_EN | B_AX_LTR_DRV_DEC_EN)
 431
 432#define R_AX_LTR_LATENCY_IDX0 0x1604
 433#define R_AX_LTR_LATENCY_IDX1 0x1608
 434#define R_AX_LTR_LATENCY_IDX2 0x160C
 435#define R_AX_LTR_LATENCY_IDX3 0x1610
 436
 437#define R_AX_HCI_FC_CTRL_V1 0x1700
 438#define R_AX_CH_PAGE_CTRL_V1 0x1704
 439
 440#define R_AX_ACH0_PAGE_CTRL_V1 0x1710
 441#define R_AX_ACH1_PAGE_CTRL_V1 0x1714
 442#define R_AX_ACH2_PAGE_CTRL_V1 0x1718
 443#define R_AX_ACH3_PAGE_CTRL_V1 0x171C
 444#define R_AX_ACH4_PAGE_CTRL_V1 0x1720
 445#define R_AX_ACH5_PAGE_CTRL_V1 0x1724
 446#define R_AX_ACH6_PAGE_CTRL_V1 0x1728
 447#define R_AX_ACH7_PAGE_CTRL_V1 0x172C
 448#define R_AX_CH8_PAGE_CTRL_V1 0x1730
 449#define R_AX_CH9_PAGE_CTRL_V1 0x1734
 450#define R_AX_CH10_PAGE_CTRL_V1 0x1738
 451#define R_AX_CH11_PAGE_CTRL_V1 0x173C
 452
 453#define R_AX_ACH0_PAGE_INFO_V1 0x1750
 454#define R_AX_ACH1_PAGE_INFO_V1 0x1754
 455#define R_AX_ACH2_PAGE_INFO_V1 0x1758
 456#define R_AX_ACH3_PAGE_INFO_V1 0x175C
 457#define R_AX_ACH4_PAGE_INFO_V1 0x1760
 458#define R_AX_ACH5_PAGE_INFO_V1 0x1764
 459#define R_AX_ACH6_PAGE_INFO_V1 0x1768
 460#define R_AX_ACH7_PAGE_INFO_V1 0x176C
 461#define R_AX_CH8_PAGE_INFO_V1 0x1770
 462#define R_AX_CH9_PAGE_INFO_V1 0x1774
 463#define R_AX_CH10_PAGE_INFO_V1 0x1778
 464#define R_AX_CH11_PAGE_INFO_V1 0x177C
 465#define R_AX_CH12_PAGE_INFO_V1 0x1780
 466
 467#define R_AX_PUB_PAGE_INFO3_V1 0x178C
 468#define R_AX_PUB_PAGE_CTRL1_V1 0x1790
 469#define R_AX_PUB_PAGE_CTRL2_V1 0x1794
 470#define R_AX_PUB_PAGE_INFO1_V1 0x1798
 471#define R_AX_PUB_PAGE_INFO2_V1 0x179C
 472#define R_AX_WP_PAGE_CTRL1_V1 0x17A0
 473#define R_AX_WP_PAGE_CTRL2_V1 0x17A4
 474#define R_AX_WP_PAGE_INFO1_V1 0x17A8
 475
 476#define R_AX_USB_ENDPOINT_0_V1 0x5060
 477#define B_AX_EP_IDX_V1 GENMASK(3, 0)
 478#define R_AX_USB_ENDPOINT_2_V1 0x5068
 479#define R_AX_USB_HOST_REQUEST_2_V1 0x5078
 480#define B_AX_R_USBIO_MODE_V1 BIT(4)
 481#define R_AX_USB3_MAC_NPI_CONFIG_INTF_0_V1 0x5114
 482#define B_AX_SSPHY_LFPS_FILTER_V1 BIT(31)
 483#define R_AX_USB_WLAN0_1_V1 0x5174
 484#define B_AX_USBRX_RST_V1 BIT(9)
 485#define B_AX_USBTX_RST_V1 BIT(8)
 486
 487#define R_AX_H2CREG_DATA0_V1 0x7140
 488#define R_AX_H2CREG_DATA1_V1 0x7144
 489#define R_AX_H2CREG_DATA2_V1 0x7148
 490#define R_AX_H2CREG_DATA3_V1 0x714C
 491#define R_AX_C2HREG_DATA0_V1 0x7150
 492#define R_AX_C2HREG_DATA1_V1 0x7154
 493#define R_AX_C2HREG_DATA2_V1 0x7158
 494#define R_AX_C2HREG_DATA3_V1 0x715C
 495#define R_AX_H2CREG_CTRL_V1 0x7160
 496#define R_AX_C2HREG_CTRL_V1 0x7164
 497
 498#define R_AX_HCI_FUNC_EN_V1 0x7880
 499
 500#define R_AX_PHYREG_SET 0x8040
 501#define PHYREG_SET_ALL_CYCLE 0x8
 502#define PHYREG_SET_XYN_CYCLE 0xE
 503
 504#define R_AX_HD0IMR 0x8110
 505#define B_AX_WDT_PTFM_INT_EN BIT(5)
 506#define B_AX_CPWM_INT_EN BIT(2)
 507#define B_AX_GT3_INT_EN BIT(1)
 508#define B_AX_C2H_INT_EN BIT(0)
 509#define R_AX_HD0ISR 0x8114
 510#define B_AX_C2H_INT BIT(0)
 511
 512#define R_AX_H2CREG_DATA0 0x8140
 513#define R_AX_H2CREG_DATA1 0x8144
 514#define R_AX_H2CREG_DATA2 0x8148
 515#define R_AX_H2CREG_DATA3 0x814C
 516#define R_AX_C2HREG_DATA0 0x8150
 517#define R_AX_C2HREG_DATA1 0x8154
 518#define R_AX_C2HREG_DATA2 0x8158
 519#define R_AX_C2HREG_DATA3 0x815C
 520#define R_AX_H2CREG_CTRL 0x8160
 521#define B_AX_H2CREG_TRIGGER BIT(0)
 522#define R_AX_C2HREG_CTRL 0x8164
 523#define B_AX_C2HREG_TRIGGER BIT(0)
 524#define R_AX_CPWM 0x8170
 525
 526#define R_AX_HCI_FUNC_EN 0x8380
 527#define B_AX_HCI_RXDMA_EN BIT(1)
 528#define B_AX_HCI_TXDMA_EN BIT(0)
 529
 530#define R_AX_BOOT_DBG 0x83F0
 531
 532#define R_AX_DMAC_FUNC_EN 0x8400
 533#define B_AX_DMAC_CRPRT BIT(31)
 534#define B_AX_MAC_FUNC_EN BIT(30)
 535#define B_AX_DMAC_FUNC_EN BIT(29)
 536#define B_AX_MPDU_PROC_EN BIT(28)
 537#define B_AX_WD_RLS_EN BIT(27)
 538#define B_AX_DLE_WDE_EN BIT(26)
 539#define B_AX_TXPKT_CTRL_EN BIT(25)
 540#define B_AX_STA_SCH_EN BIT(24)
 541#define B_AX_DLE_PLE_EN BIT(23)
 542#define B_AX_PKT_BUF_EN BIT(22)
 543#define B_AX_DMAC_TBL_EN BIT(21)
 544#define B_AX_PKT_IN_EN BIT(20)
 545#define B_AX_DLE_CPUIO_EN BIT(19)
 546#define B_AX_DISPATCHER_EN BIT(18)
 547#define B_AX_BBRPT_EN BIT(17)
 548#define B_AX_MAC_SEC_EN BIT(16)
 549#define B_AX_DMACREG_GCKEN BIT(15)
 550#define B_AX_MAC_UN_EN BIT(15)
 551#define B_AX_H_AXIDMA_EN BIT(14)
 552
 553#define R_AX_DMAC_CLK_EN 0x8404
 554#define B_AX_WD_RLS_CLK_EN BIT(27)
 555#define B_AX_DLE_WDE_CLK_EN BIT(26)
 556#define B_AX_TXPKT_CTRL_CLK_EN BIT(25)
 557#define B_AX_STA_SCH_CLK_EN BIT(24)
 558#define B_AX_DLE_PLE_CLK_EN BIT(23)
 559#define B_AX_PKT_IN_CLK_EN BIT(20)
 560#define B_AX_DLE_CPUIO_CLK_EN BIT(19)
 561#define B_AX_DISPATCHER_CLK_EN BIT(18)
 562#define B_AX_BBRPT_CLK_EN BIT(17)
 563#define B_AX_MAC_SEC_CLK_EN BIT(16)
 564#define B_AX_AXIDMA_CLK_EN BIT(9)
 565
 566#define PCI_LTR_IDLE_TIMER_1US 0
 567#define PCI_LTR_IDLE_TIMER_10US 1
 568#define PCI_LTR_IDLE_TIMER_100US 2
 569#define PCI_LTR_IDLE_TIMER_200US 3
 570#define PCI_LTR_IDLE_TIMER_400US 4
 571#define PCI_LTR_IDLE_TIMER_800US 5
 572#define PCI_LTR_IDLE_TIMER_1_6MS 6
 573#define PCI_LTR_IDLE_TIMER_3_2MS 7
 574#define PCI_LTR_IDLE_TIMER_R_ERR 0xFD
 575#define PCI_LTR_IDLE_TIMER_DEF 0xFE
 576#define PCI_LTR_IDLE_TIMER_IGNORE 0xFF
 577
 578#define PCI_LTR_SPC_10US 0
 579#define PCI_LTR_SPC_100US 1
 580#define PCI_LTR_SPC_500US 2
 581#define PCI_LTR_SPC_1MS 3
 582#define PCI_LTR_SPC_R_ERR 0xFD
 583#define PCI_LTR_SPC_DEF 0xFE
 584#define PCI_LTR_SPC_IGNORE 0xFF
 585
 586#define R_AX_LTR_CTRL_0 0x8410
 587#define B_AX_LTR_SPACE_IDX_MASK GENMASK(13, 12)
 588#define B_AX_LTR_IDLE_TIMER_IDX_MASK GENMASK(10, 8)
 589#define B_AX_LTR_WD_NOEMP_CHK BIT(6)
 590#define B_AX_APP_LTR_ACT BIT(5)
 591#define B_AX_APP_LTR_IDLE BIT(4)
 592#define B_AX_LTR_EN BIT(1)
 593#define B_AX_LTR_WD_NOEMP_CHK_V1 BIT(1)
 594#define B_AX_LTR_HW_EN BIT(0)
 595
 596#define R_AX_LTR_CTRL_1 0x8414
 597#define B_AX_LTR_RX1_TH_MASK GENMASK(27, 16)
 598#define B_AX_LTR_RX0_TH_MASK GENMASK(11, 0)
 599
 600#define R_AX_LTR_IDLE_LATENCY 0x8418
 601
 602#define R_AX_LTR_ACTIVE_LATENCY 0x841C
 603
 604#define R_AX_SER_DBG_INFO 0x8424
 605#define B_AX_L0_TO_L1_EVENT_MASK GENMASK(31, 28)
 606
 607#define R_AX_DLE_EMPTY0 0x8430
 608#define B_AX_PLE_EMPTY_QTA_DMAC_CPUIO BIT(26)
 609#define B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX BIT(25)
 610#define B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU BIT(24)
 611#define B_AX_PLE_EMPTY_QTA_DMAC_H2C BIT(23)
 612#define B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL BIT(22)
 613#define B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL BIT(21)
 614#define B_AX_WDE_EMPTY_QTA_DMAC_CPUIO BIT(20)
 615#define B_AX_WDE_EMPTY_QTA_DMAC_PKTIN BIT(19)
 616#define B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU BIT(18)
 617#define B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU BIT(17)
 618#define B_AX_WDE_EMPTY_QTA_DMAC_HIF BIT(16)
 619#define B_AX_WDE_EMPTY_QUE_DMAC_PKTIN BIT(10)
 620#define B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX BIT(9)
 621#define B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX BIT(8)
 622#define B_AX_WDE_EMPTY_QUE_OTHERS BIT(7)
 623#define B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 BIT(4)
 624#define B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 BIT(3)
 625#define B_AX_WDE_EMPTY_QUE_CMAC1_MBH BIT(2)
 626#define B_AX_WDE_EMPTY_QUE_CMAC0_MBH BIT(1)
 627#define B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC BIT(0)
 628
 629#define R_AX_DLE_EMPTY1 0x8434
 630#define B_AX_PLE_EMPTY_QTA_DMAC_WDRLS BIT(20)
 631#define B_AX_PLE_EMPTY_QTA_CMAC1_DMA_BBRPT BIT(19)
 632#define B_AX_PLE_EMPTY_QTA_CMAC1_DMA_RX BIT(18)
 633#define B_AX_PLE_EMPTY_QTA_CMAC0_DMA_RX BIT(17)
 634#define B_AX_PLE_EMPTY_QTA_DMAC_C2H BIT(16)
 635#define B_AX_PLE_EMPTY_QUE_DMAC_PLRLS BIT(5)
 636#define B_AX_PLE_EMPTY_QUE_DMAC_CPUIO BIT(4)
 637#define B_AX_PLE_EMPTY_QUE_DMAC_SEC_RX BIT(3)
 638#define B_AX_PLE_EMPTY_QUE_DMAC_MPDU_RX BIT(2)
 639#define B_AX_PLE_EMPTY_QUE_DMAC_HDP BIT(1)
 640#define B_AX_WDE_EMPTY_QUE_DMAC_WDRLS BIT(0)
 641
 642#define R_AX_DMAC_ERR_IMR 0x8520
 643#define B_AX_DLE_CPUIO_ERR_INT_EN BIT(10)
 644#define B_AX_APB_BRIDGE_ERR_INT_EN BIT(9)
 645#define B_AX_DISPATCH_ERR_INT_EN BIT(8)
 646#define B_AX_PKTIN_ERR_INT_EN BIT(7)
 647#define B_AX_PLE_DLE_ERR_INT_EN BIT(6)
 648#define B_AX_TXPKTCTRL_ERR_INT_EN BIT(5)
 649#define B_AX_WDE_DLE_ERR_INT_EN BIT(4)
 650#define B_AX_STA_SCHEDULER_ERR_INT_EN BIT(3)
 651#define B_AX_MPDU_ERR_INT_EN BIT(2)
 652#define B_AX_WSEC_ERR_INT_EN BIT(1)
 653#define B_AX_WDRLS_ERR_INT_EN BIT(0)
 654#define DMAC_ERR_IMR_EN GENMASK(31, 0)
 655#define DMAC_ERR_IMR_DIS 0
 656
 657#define R_AX_DMAC_ERR_ISR 0x8524
 658#define B_AX_HAXIDMA_ERR_FLAG BIT(14)
 659#define B_AX_PAXIDMA_ERR_FLAG BIT(13)
 660#define B_AX_HCI_BUF_ERR_FLAG BIT(12)
 661#define B_AX_BBRPT_ERR_FLAG BIT(11)
 662#define B_AX_DLE_CPUIO_ERR_FLAG BIT(10)
 663#define B_AX_APB_BRIDGE_ERR_FLAG BIT(9)
 664#define B_AX_DISPATCH_ERR_FLAG BIT(8)
 665#define B_AX_PKTIN_ERR_FLAG BIT(7)
 666#define B_AX_PLE_DLE_ERR_FLAG BIT(6)
 667#define B_AX_TXPKTCTRL_ERR_FLAG BIT(5)
 668#define B_AX_WDE_DLE_ERR_FLAG BIT(4)
 669#define B_AX_STA_SCHEDULER_ERR_FLAG BIT(3)
 670#define B_AX_MPDU_ERR_FLAG BIT(2)
 671#define B_AX_WSEC_ERR_FLAG BIT(1)
 672#define B_AX_WDRLS_ERR_FLAG BIT(0)
 673
 674#define R_AX_DISPATCHER_GLOBAL_SETTING_0 0x8800
 675#define B_AX_PL_PAGE_128B_SEL BIT(9)
 676#define B_AX_WD_PAGE_64B_SEL BIT(8)
 677#define R_AX_OTHER_DISPATCHER_ERR_ISR 0x8804
 678#define R_AX_HOST_DISPATCHER_ERR_ISR 0x8808
 679#define R_AX_CPU_DISPATCHER_ERR_ISR 0x880C
 680#define R_AX_TX_ADDRESS_INFO_MODE_SETTING 0x8810
 681#define B_AX_HOST_ADDR_INFO_8B_SEL BIT(0)
 682
 683#define R_AX_HOST_DISPATCHER_ERR_IMR 0x8850
 684#define B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN BIT(31)
 685#define B_AX_HDT_RX_WRITE_OVERFLOW_INT_EN BIT(30)
 686#define B_AX_HDT_CHKSUM_FSM_ERR_INT_EN BIT(29)
 687#define B_AX_HDT_SHIFT_DMA_CFG_ERR_INT_EN BIT(28)
 688#define B_AX_HDT_DMA_PROCESS_ERR_INT_EN BIT(27)
 689#define B_AX_HDT_TOTAL_LEN_ERR_INT_EN BIT(26)
 690#define B_AX_HDT_SHIFT_EN_ERR_INT_EN BIT(25)
 691#define B_AX_HDT_RXAGG_CFG_ERR_INT_EN BIT(24)
 692#define B_AX_HDT_OUTPUT_ERR_INT_EN BIT(21)
 693#define B_AX_HDT_RES_ERR_INT_EN BIT(20)
 694#define B_AX_HDT_BURST_NUM_ERR_INT_EN BIT(19)
 695#define B_AX_HDT_NULLPKT_ERR_INT_EN BIT(18)
 696#define B_AX_HDT_FLOW_CTRL_ERR_INT_EN BIT(17)
 697#define B_AX_HDT_PLD_CMD_UNDERFLOW_INT_EN BIT(16)
 698#define B_AX_HDT_PLD_CMD_OVERLOW_INT_EN BIT(15)
 699#define B_AX_HDT_TX_WRITE_UNDERFLOW_INT_EN BIT(14)
 700#define B_AX_HDT_TX_WRITE_OVERFLOW_INT_EN BIT(13)
 701#define B_AX_HDT_TCP_CHK_ERR_INT_EN BIT(12)
 702#define B_AX_HDT_TXPKTSIZE_ERR_INT_EN BIT(11)
 703#define B_AX_HDT_PRE_COST_ERR_INT_EN BIT(10)
 704#define B_AX_HDT_WD_CHK_ERR_INT_EN BIT(9)
 705#define B_AX_HDT_CHANNEL_DMA_ERR_INT_EN BIT(8)
 706#define B_AX_HDT_OFFSET_UNMATCH_INT_EN BIT(7)
 707#define B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN BIT(6)
 708#define B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN BIT(5)
 709#define B_AX_HDT_PERMU_UNDERFLOW_INT_EN BIT(4)
 710#define B_AX_HDT_PERMU_OVERFLOW_INT_EN BIT(3)
 711#define B_AX_HDT_PKT_FAIL_DBG_INT_EN BIT(2)
 712#define B_AX_HDT_CHANNEL_ID_ERR_INT_EN BIT(1)
 713#define B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN BIT(0)
 714#define B_AX_HOST_DISP_IMR_CLR (B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN | \
 715				B_AX_HDT_CHANNEL_ID_ERR_INT_EN | \
 716				B_AX_HDT_PKT_FAIL_DBG_INT_EN | \
 717				B_AX_HDT_PERMU_OVERFLOW_INT_EN | \
 718				B_AX_HDT_PERMU_UNDERFLOW_INT_EN | \
 719				B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN | \
 720				B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN | \
 721				B_AX_HDT_OFFSET_UNMATCH_INT_EN | \
 722				B_AX_HDT_CHANNEL_DMA_ERR_INT_EN | \
 723				B_AX_HDT_WD_CHK_ERR_INT_EN | \
 724				B_AX_HDT_PRE_COST_ERR_INT_EN | \
 725				B_AX_HDT_TXPKTSIZE_ERR_INT_EN | \
 726				B_AX_HDT_TCP_CHK_ERR_INT_EN | \
 727				B_AX_HDT_TX_WRITE_OVERFLOW_INT_EN | \
 728				B_AX_HDT_TX_WRITE_UNDERFLOW_INT_EN | \
 729				B_AX_HDT_PLD_CMD_OVERLOW_INT_EN | \
 730				B_AX_HDT_PLD_CMD_UNDERFLOW_INT_EN | \
 731				B_AX_HDT_FLOW_CTRL_ERR_INT_EN | \
 732				B_AX_HDT_NULLPKT_ERR_INT_EN | \
 733				B_AX_HDT_BURST_NUM_ERR_INT_EN | \
 734				B_AX_HDT_RXAGG_CFG_ERR_INT_EN | \
 735				B_AX_HDT_SHIFT_EN_ERR_INT_EN | \
 736				B_AX_HDT_TOTAL_LEN_ERR_INT_EN | \
 737				B_AX_HDT_DMA_PROCESS_ERR_INT_EN | \
 738				B_AX_HDT_SHIFT_DMA_CFG_ERR_INT_EN | \
 739				B_AX_HDT_CHKSUM_FSM_ERR_INT_EN | \
 740				B_AX_HDT_RX_WRITE_OVERFLOW_INT_EN | \
 741				B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN)
 742#define B_AX_HOST_DISP_IMR_SET (B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN | \
 743				B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN | \
 744				B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN | \
 745				B_AX_HDT_CHANNEL_DMA_ERR_INT_EN | \
 746				B_AX_HDT_TOTAL_LEN_ERR_INT_EN | \
 747				B_AX_HDT_DMA_PROCESS_ERR_INT_EN)
 748#define B_AX_HOST_DISP_IMR_SET_V01 (B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN | \
 749				    B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN | \
 750				    B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN | \
 751				    B_AX_HDT_CHANNEL_DMA_ERR_INT_EN | \
 752				    B_AX_HDT_TOTAL_LEN_ERR_INT_EN | \
 753				    B_AX_HDT_DMA_PROCESS_ERR_INT_EN | \
 754				    B_AX_HDT_RX_WRITE_OVERFLOW_INT_EN | \
 755				    B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN)
 756
 757#define B_AX_HR_WRFF_UNDERFLOW_ERR_INT_EN BIT(31)
 758#define B_AX_HR_WRFF_OVERFLOW_ERR_INT_EN BIT(30)
 759#define B_AX_HR_CHKSUM_FSM_ERR_INT_EN BIT(29)
 760#define B_AX_HR_SHIFT_DMA_CFG_ERR_INT_EN BIT(28)
 761#define B_AX_HR_DMA_PROCESS_ERR_INT_EN BIT(27)
 762#define B_AX_HR_TOTAL_LEN_UNDER_ERR_INT_EN BIT(26)
 763#define B_AX_HR_SHIFT_EN_ERR_INT_EN BIT(25)
 764#define B_AX_HR_AGG_CFG_ERR_INT_EN BIT(24)
 765#define B_AX_HR_DMA_RD_CNT_DEQ_ERR_INT_EN BIT(23)
 766#define B_AX_HR_PLD_LEN_ZERO_ERR_INT_EN BIT(22)
 767#define B_AX_HT_ILL_CH_ERR_INT_EN BIT(20)
 768#define B_AX_HT_ADDR_INFO_LEN_ERR_INT_EN BIT(18)
 769#define B_AX_HT_WD_LEN_OVER_ERR_INT_EN BIT(17)
 770#define B_AX_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN BIT(16)
 771#define B_AX_HT_PLD_CMD_OVERFLOW_ERR_INT_EN BIT(15)
 772#define B_AX_HT_WRFF_UNDERFLOW_ERR_INT_EN BIT(14)
 773#define B_AX_HT_WRFF_OVERFLOW_ERR_INT_EN BIT(13)
 774#define B_AX_HT_CHKSUM_FSM_ERR_INT_EN BIT(12)
 775#define B_AX_HT_TXPKTSIZE_ERR_INT_EN BIT(11)
 776#define B_AX_HT_PRE_SUB_ERR_INT_EN BIT(10)
 777#define B_AX_HT_WD_CHKSUM_ERR_INT_EN BIT(9)
 778#define B_AX_HT_CHANNEL_DMA_ERR_INT_EN BIT(8)
 779#define B_AX_HT_OFFSET_UNMATCH_ERR_INT_EN BIT(7)
 780#define B_AX_HT_PAYLOAD_UNDER_ERR_INT_EN BIT(6)
 781#define B_AX_HT_PAYLOAD_OVER_ERR_INT_EN BIT(5)
 782#define B_AX_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4)
 783#define B_AX_HT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3)
 784#define B_AX_HT_PKT_FAIL_ERR_INT_EN BIT(2)
 785#define B_AX_HT_CH_ID_ERR_INT_EN BIT(1)
 786#define B_AX_HT_EP_CH_DIFF_ERR_INT_EN BIT(0)
 787#define B_AX_HOST_DISP_IMR_CLR_V1 (B_AX_HT_EP_CH_DIFF_ERR_INT_EN | \
 788				   B_AX_HT_CH_ID_ERR_INT_EN | \
 789				   B_AX_HT_PKT_FAIL_ERR_INT_EN | \
 790				   B_AX_HT_PERMU_FF_OVERFLOW_ERR_INT_EN | \
 791				   B_AX_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \
 792				   B_AX_HT_PAYLOAD_OVER_ERR_INT_EN | \
 793				   B_AX_HT_PAYLOAD_UNDER_ERR_INT_EN | \
 794				   B_AX_HT_OFFSET_UNMATCH_ERR_INT_EN | \
 795				   B_AX_HT_CHANNEL_DMA_ERR_INT_EN | \
 796				   B_AX_HT_WD_CHKSUM_ERR_INT_EN | \
 797				   B_AX_HT_PRE_SUB_ERR_INT_EN | \
 798				   B_AX_HT_TXPKTSIZE_ERR_INT_EN | \
 799				   B_AX_HT_CHKSUM_FSM_ERR_INT_EN | \
 800				   B_AX_HT_WRFF_OVERFLOW_ERR_INT_EN | \
 801				   B_AX_HT_WRFF_UNDERFLOW_ERR_INT_EN | \
 802				   B_AX_HT_PLD_CMD_OVERFLOW_ERR_INT_EN | \
 803				   B_AX_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \
 804				   B_AX_HT_WD_LEN_OVER_ERR_INT_EN | \
 805				   B_AX_HT_ADDR_INFO_LEN_ERR_INT_EN | \
 806				   B_AX_HT_ILL_CH_ERR_INT_EN | \
 807				   B_AX_HR_PLD_LEN_ZERO_ERR_INT_EN | \
 808				   B_AX_HR_DMA_RD_CNT_DEQ_ERR_INT_EN | \
 809				   B_AX_HR_AGG_CFG_ERR_INT_EN | \
 810				   B_AX_HR_SHIFT_EN_ERR_INT_EN | \
 811				   B_AX_HR_TOTAL_LEN_UNDER_ERR_INT_EN | \
 812				   B_AX_HR_DMA_PROCESS_ERR_INT_EN | \
 813				   B_AX_HR_SHIFT_DMA_CFG_ERR_INT_EN | \
 814				   B_AX_HR_CHKSUM_FSM_ERR_INT_EN | \
 815				   B_AX_HR_WRFF_OVERFLOW_ERR_INT_EN | \
 816				   B_AX_HR_WRFF_UNDERFLOW_ERR_INT_EN)
 817#define B_AX_HOST_DISP_IMR_SET_V1 (B_AX_HT_PAYLOAD_OVER_ERR_INT_EN | \
 818				   B_AX_HT_PAYLOAD_UNDER_ERR_INT_EN | \
 819				   B_AX_HT_ILL_CH_ERR_INT_EN | \
 820				   B_AX_HR_TOTAL_LEN_UNDER_ERR_INT_EN | \
 821				   B_AX_HR_DMA_PROCESS_ERR_INT_EN)
 822
 823#define R_AX_CPU_DISPATCHER_ERR_IMR 0x8854
 824#define B_AX_CPU_RX_WRITE_UNDERFLOW_INT_EN BIT(31)
 825#define B_AX_CPU_RX_WRITE_OVERFLOW_INT_EN BIT(30)
 826#define B_AX_CPU_CHKSUM_FSM_ERR_INT_EN BIT(29)
 827#define B_AX_CPU_SHIFT_DMA_CFG_ERR_INT_EN BIT(28)
 828#define B_AX_CPU_DMA_PROCESS_ERR_INT_EN BIT(27)
 829#define B_AX_CPU_TOTAL_LEN_ERR_INT_EN BIT(26)
 830#define B_AX_CPU_SHIFT_EN_ERR_INT_EN BIT(25)
 831#define B_AX_CPU_RXAGG_CFG_ERR_INT_EN BIT(24)
 832#define B_AX_CPU_OUTPUT_ERR_INT_EN BIT(20)
 833#define B_AX_CPU_RESP_ERR_INT_EN BIT(19)
 834#define B_AX_CPU_BURST_NUM_ERR_INT_EN BIT(18)
 835#define B_AX_CPU_NULLPKT_ERR_INT_EN BIT(17)
 836#define B_AX_CPU_FLOW_CTRL_ERR_INT_EN BIT(16)
 837#define B_AX_CPU_F2P_SEQ_ERR_INT_EN BIT(15)
 838#define B_AX_CPU_F2P_QSEL_ERR_INT_EN BIT(14)
 839#define B_AX_CPU_PLD_CMD_UNDERFLOW_INT_EN BIT(13)
 840#define B_AX_CPU_PLD_CMD_OVERLOW_INT_EN BIT(12)
 841#define B_AX_CPU_PRE_COST_ERR_INT_EN BIT(11)
 842#define B_AX_CPU_WD_CHK_ERR_INT_EN BIT(10)
 843#define B_AX_CPU_CHANNEL_DMA_ERR_INT_EN BIT(9)
 844#define B_AX_CPU_OFFSET_UNMATCH_INT_EN BIT(8)
 845#define B_AX_CPU_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7)
 846#define B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN BIT(6)
 847#define B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN BIT(5)
 848#define B_AX_CPU_PERMU_UNDERFLOW_INT_EN BIT(4)
 849#define B_AX_CPU_PERMU_OVERFLOW_INT_EN BIT(3)
 850#define B_AX_CPU_CHANNEL_ID_ERR_INT_EN BIT(2)
 851#define B_AX_CPU_PKT_FAIL_DBG_INT_EN BIT(1)
 852#define B_AX_CPU_CHANNEL_DIFF_ERR_INT_EN BIT(0)
 853#define B_AX_CPU_DISP_IMR_CLR (B_AX_CPU_CHANNEL_DIFF_ERR_INT_EN | \
 854			       B_AX_CPU_PKT_FAIL_DBG_INT_EN | \
 855			       B_AX_CPU_CHANNEL_ID_ERR_INT_EN | \
 856			       B_AX_CPU_PERMU_OVERFLOW_INT_EN | \
 857			       B_AX_CPU_PERMU_UNDERFLOW_INT_EN | \
 858			       B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN | \
 859			       B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN | \
 860			       B_AX_CPU_PAYLOAD_CHKSUM_ERR_INT_EN | \
 861			       B_AX_CPU_OFFSET_UNMATCH_INT_EN | \
 862			       B_AX_CPU_CHANNEL_DMA_ERR_INT_EN | \
 863			       B_AX_CPU_WD_CHK_ERR_INT_EN | \
 864			       B_AX_CPU_PRE_COST_ERR_INT_EN | \
 865			       B_AX_CPU_PLD_CMD_OVERLOW_INT_EN | \
 866			       B_AX_CPU_PLD_CMD_UNDERFLOW_INT_EN | \
 867			       B_AX_CPU_F2P_QSEL_ERR_INT_EN | \
 868			       B_AX_CPU_F2P_SEQ_ERR_INT_EN | \
 869			       B_AX_CPU_FLOW_CTRL_ERR_INT_EN | \
 870			       B_AX_CPU_NULLPKT_ERR_INT_EN | \
 871			       B_AX_CPU_BURST_NUM_ERR_INT_EN | \
 872			       B_AX_CPU_RXAGG_CFG_ERR_INT_EN | \
 873			       B_AX_CPU_SHIFT_EN_ERR_INT_EN | \
 874			       B_AX_CPU_TOTAL_LEN_ERR_INT_EN | \
 875			       B_AX_CPU_DMA_PROCESS_ERR_INT_EN | \
 876			       B_AX_CPU_SHIFT_DMA_CFG_ERR_INT_EN | \
 877			       B_AX_CPU_CHKSUM_FSM_ERR_INT_EN | \
 878			       B_AX_CPU_RX_WRITE_OVERFLOW_INT_EN | \
 879			       B_AX_CPU_RX_WRITE_UNDERFLOW_INT_EN)
 880#define B_AX_CPU_DISP_IMR_SET (B_AX_CPU_PKT_FAIL_DBG_INT_EN | \
 881			       B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN | \
 882			       B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN | \
 883			       B_AX_CPU_TOTAL_LEN_ERR_INT_EN)
 884
 885#define B_AX_CR_PLD_LEN_ERR_INT_EN BIT(30)
 886#define B_AX_CR_WRFF_UNDERFLOW_ERR_INT_EN BIT(29)
 887#define B_AX_CR_WRFF_OVERFLOW_ERR_INT_EN BIT(28)
 888#define B_AX_CR_SHIFT_DMA_CFG_ERR_INT_EN BIT(27)
 889#define B_AX_CR_DMA_PROCESS_ERR_INT_EN BIT(26)
 890#define B_AX_CR_TOTAL_LEN_UNDER_ERR_INT_EN BIT(25)
 891#define B_AX_CR_SHIFT_EN_ERR_INT_EN BIT(24)
 892#define B_AX_REUSE_FIFO_B_UNDER_ERR_INT_EN BIT(22)
 893#define B_AX_REUSE_FIFO_B_OVER_ERR_INT_EN BIT(21)
 894#define B_AX_REUSE_FIFO_A_UNDER_ERR_INT_EN BIT(20)
 895#define B_AX_REUSE_FIFO_A_OVER_ERR_INT_EN BIT(19)
 896#define B_AX_CT_ADDR_INFO_LEN_MISS_ERR_INT_EN BIT(17)
 897#define B_AX_CT_WD_LEN_OVER_ERR_INT_EN BIT(16)
 898#define B_AX_CT_F2P_SEQ_ERR_INT_EN BIT(15)
 899#define B_AX_CT_F2P_QSEL_ERR_INT_EN BIT(14)
 900#define B_AX_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN BIT(13)
 901#define B_AX_CT_PLD_CMD_OVERFLOW_ERR_INT_EN BIT(12)
 902#define B_AX_CT_PRE_SUB_ERR_INT_EN BIT(11)
 903#define B_AX_CT_WD_CHKSUM_ERR_INT_EN BIT(10)
 904#define B_AX_CT_CHANNEL_DMA_ERR_INT_EN BIT(9)
 905#define B_AX_CT_OFFSET_UNMATCH_ERR_INT_EN BIT(8)
 906#define B_AX_CT_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7)
 907#define B_AX_CT_PAYLOAD_UNDER_ERR_INT_EN BIT(6)
 908#define B_AX_CT_PAYLOAD_OVER_ERR_INT_EN BIT(5)
 909#define B_AX_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4)
 910#define B_AX_CT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3)
 911#define B_AX_CT_CH_ID_ERR_INT_EN BIT(2)
 912#define B_AX_CT_EP_CH_DIFF_ERR_INT_EN BIT(0)
 913#define B_AX_CPU_DISP_IMR_CLR_V1 (B_AX_CT_EP_CH_DIFF_ERR_INT_EN | \
 914				  B_AX_CT_CH_ID_ERR_INT_EN | \
 915				  B_AX_CT_PERMU_FF_OVERFLOW_ERR_INT_EN | \
 916				  B_AX_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \
 917				  B_AX_CT_PAYLOAD_OVER_ERR_INT_EN | \
 918				  B_AX_CT_PAYLOAD_UNDER_ERR_INT_EN | \
 919				  B_AX_CT_PAYLOAD_CHKSUM_ERR_INT_EN | \
 920				  B_AX_CT_OFFSET_UNMATCH_ERR_INT_EN | \
 921				  B_AX_CT_CHANNEL_DMA_ERR_INT_EN | \
 922				  B_AX_CT_WD_CHKSUM_ERR_INT_EN | \
 923				  B_AX_CT_PRE_SUB_ERR_INT_EN | \
 924				  B_AX_CT_PLD_CMD_OVERFLOW_ERR_INT_EN | \
 925				  B_AX_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \
 926				  B_AX_CT_F2P_QSEL_ERR_INT_EN | \
 927				  B_AX_CT_F2P_SEQ_ERR_INT_EN | \
 928				  B_AX_CT_WD_LEN_OVER_ERR_INT_EN | \
 929				  B_AX_CT_ADDR_INFO_LEN_MISS_ERR_INT_EN | \
 930				  B_AX_REUSE_FIFO_A_OVER_ERR_INT_EN | \
 931				  B_AX_REUSE_FIFO_A_UNDER_ERR_INT_EN | \
 932				  B_AX_REUSE_FIFO_B_OVER_ERR_INT_EN | \
 933				  B_AX_REUSE_FIFO_B_UNDER_ERR_INT_EN | \
 934				  B_AX_CR_SHIFT_EN_ERR_INT_EN | \
 935				  B_AX_CR_TOTAL_LEN_UNDER_ERR_INT_EN | \
 936				  B_AX_CR_DMA_PROCESS_ERR_INT_EN | \
 937				  B_AX_CR_SHIFT_DMA_CFG_ERR_INT_EN | \
 938				  B_AX_CR_WRFF_OVERFLOW_ERR_INT_EN | \
 939				  B_AX_CR_WRFF_UNDERFLOW_ERR_INT_EN | \
 940				  B_AX_CR_PLD_LEN_ERR_INT_EN)
 941#define B_AX_CPU_DISP_IMR_SET_V1 (B_AX_CT_PAYLOAD_OVER_ERR_INT_EN | \
 942				  B_AX_CT_PAYLOAD_UNDER_ERR_INT_EN | \
 943				  B_AX_CR_TOTAL_LEN_UNDER_ERR_INT_EN | \
 944				  B_AX_CR_DMA_PROCESS_ERR_INT_EN | \
 945				  B_AX_CR_WRFF_OVERFLOW_ERR_INT_EN | \
 946				  B_AX_CR_WRFF_UNDERFLOW_ERR_INT_EN)
 947
 948#define R_AX_OTHER_DISPATCHER_ERR_IMR 0x8858
 949#define B_AX_OTHER_STF_WROQT_UNDERFLOW_INT_EN BIT(29)
 950#define B_AX_OTHER_STF_WROQT_OVERFLOW_INT_EN BIT(28)
 951#define B_AX_OTHER_STF_WRFF_UNDERFLOW_INT_EN BIT(27)
 952#define B_AX_OTHER_STF_WRFF_OVERFLOW_INT_EN BIT(26)
 953#define B_AX_OTHER_STF_CMD_UNDERFLOW_INT_EN BIT(25)
 954#define B_AX_OTHER_STF_CMD_OVERFLOW_INT_EN BIT(24)
 955#define B_AX_HOST_ADDR_INFO_LEN_ZERO_ERR_INT_EN BIT(17)
 956#define B_AX_CPU_ADDR_INFO_LEN_ZERO_ERR_INT_EN BIT(16)
 957#define B_AX_PLE_OUTPUT_ERR_INT_EN BIT(12)
 958#define B_AX_PLE_RESP_ERR_INT_EN BIT(11)
 959#define B_AX_PLE_BURST_NUM_ERR_INT_EN BIT(10)
 960#define B_AX_PLE_NULL_PKT_ERR_INT_EN BIT(9)
 961#define B_AX_PLE_FLOW_CTRL_ERR_INT_EN BIT(8)
 962#define B_AX_WDE_OUTPUT_ERR_INT_EN BIT(4)
 963#define B_AX_WDE_RESP_ERR_INT_EN BIT(3)
 964#define B_AX_WDE_BURST_NUM_ERR_INT_EN BIT(2)
 965#define B_AX_WDE_NULL_PKT_ERR_INT_EN BIT(1)
 966#define B_AX_WDE_FLOW_CTRL_ERR_INT_EN BIT(0)
 967#define B_AX_OTHER_DISP_IMR_CLR (B_AX_OTHER_STF_WROQT_UNDERFLOW_INT_EN | \
 968				 B_AX_OTHER_STF_WROQT_OVERFLOW_INT_EN | \
 969				 B_AX_OTHER_STF_WRFF_UNDERFLOW_INT_EN | \
 970				 B_AX_OTHER_STF_WRFF_OVERFLOW_INT_EN | \
 971				 B_AX_OTHER_STF_CMD_UNDERFLOW_INT_EN | \
 972				 B_AX_OTHER_STF_CMD_OVERFLOW_INT_EN | \
 973				 B_AX_HOST_ADDR_INFO_LEN_ZERO_ERR_INT_EN | \
 974				 B_AX_CPU_ADDR_INFO_LEN_ZERO_ERR_INT_EN | \
 975				 B_AX_PLE_OUTPUT_ERR_INT_EN | \
 976				 B_AX_PLE_RESP_ERR_INT_EN | \
 977				 B_AX_PLE_BURST_NUM_ERR_INT_EN | \
 978				 B_AX_PLE_NULL_PKT_ERR_INT_EN | \
 979				 B_AX_PLE_FLOW_CTRL_ERR_INT_EN | \
 980				 B_AX_WDE_OUTPUT_ERR_INT_EN | \
 981				 B_AX_WDE_RESP_ERR_INT_EN | \
 982				 B_AX_WDE_BURST_NUM_ERR_INT_EN | \
 983				 B_AX_WDE_NULL_PKT_ERR_INT_EN | \
 984				 B_AX_WDE_FLOW_CTRL_ERR_INT_EN)
 985
 986#define B_AX_REUSE_SIZE_ERR_INT_EN BIT(31)
 987#define B_AX_REUSE_EN_ERR_INT_EN BIT(30)
 988#define B_AX_STF_OQT_UNDERFLOW_ERR_INT_EN BIT(29)
 989#define B_AX_STF_OQT_OVERFLOW_ERR_INT_EN BIT(28)
 990#define B_AX_STF_WRFF_UNDERFLOW_ERR_INT_EN BIT(27)
 991#define B_AX_STF_WRFF_OVERFLOW_ERR_INT_EN BIT(26)
 992#define B_AX_STF_CMD_UNDERFLOW_ERR_INT_EN BIT(25)
 993#define B_AX_STF_CMD_OVERFLOW_ERR_INT_EN BIT(24)
 994#define B_AX_REUSE_SIZE_ZERO_ERR_INT_EN BIT(23)
 995#define B_AX_REUSE_PKT_CNT_ERR_INT_EN BIT(22)
 996#define B_AX_CDT_PTR_TIMEOUT_ERR_INT_EN BIT(21)
 997#define B_AX_CDT_HCI_TIMEOUT_ERR_INT_EN BIT(20)
 998#define B_AX_HDT_PTR_TIMEOUT_ERR_INT_EN BIT(19)
 999#define B_AX_HDT_HCI_TIMEOUT_ERR_INT_EN BIT(18)
1000#define B_AX_CDT_ADDR_INFO_LEN_ERR_INT_EN BIT(17)
1001#define B_AX_HDT_ADDR_INFO_LEN_ERR_INT_EN BIT(16)
1002#define B_AX_CDR_DMA_TIMEOUT_ERR_INT_EN BIT(15)
1003#define B_AX_CDR_RX_TIMEOUT_ERR_INT_EN BIT(14)
1004#define B_AX_PLE_RESPOSE_ERR_INT_EN BIT(11)
1005#define B_AX_HDR_DMA_TIMEOUT_ERR_INT_EN BIT(7)
1006#define B_AX_HDR_RX_TIMEOUT_ERR_INT_EN BIT(6)
1007#define B_AX_WDE_RESPONSE_ERR_INT_EN BIT(3)
1008#define B_AX_OTHER_DISP_IMR_CLR_V1 (B_AX_CT_EP_CH_DIFF_ERR_INT_EN | \
1009				    B_AX_WDE_FLOW_CTRL_ERR_INT_EN | \
1010				    B_AX_WDE_NULL_PKT_ERR_INT_EN | \
1011				    B_AX_WDE_BURST_NUM_ERR_INT_EN | \
1012				    B_AX_WDE_RESPONSE_ERR_INT_EN | \
1013				    B_AX_WDE_OUTPUT_ERR_INT_EN | \
1014				    B_AX_HDR_RX_TIMEOUT_ERR_INT_EN | \
1015				    B_AX_HDR_DMA_TIMEOUT_ERR_INT_EN | \
1016				    B_AX_PLE_FLOW_CTRL_ERR_INT_EN | \
1017				    B_AX_PLE_NULL_PKT_ERR_INT_EN | \
1018				    B_AX_PLE_BURST_NUM_ERR_INT_EN | \
1019				    B_AX_PLE_RESPOSE_ERR_INT_EN | \
1020				    B_AX_PLE_OUTPUT_ERR_INT_EN | \
1021				    B_AX_CDR_RX_TIMEOUT_ERR_INT_EN | \
1022				    B_AX_CDR_DMA_TIMEOUT_ERR_INT_EN | \
1023				    B_AX_HDT_ADDR_INFO_LEN_ERR_INT_EN | \
1024				    B_AX_CDT_ADDR_INFO_LEN_ERR_INT_EN | \
1025				    B_AX_HDT_HCI_TIMEOUT_ERR_INT_EN | \
1026				    B_AX_HDT_PTR_TIMEOUT_ERR_INT_EN | \
1027				    B_AX_CDT_HCI_TIMEOUT_ERR_INT_EN | \
1028				    B_AX_CDT_PTR_TIMEOUT_ERR_INT_EN | \
1029				    B_AX_REUSE_PKT_CNT_ERR_INT_EN | \
1030				    B_AX_REUSE_SIZE_ZERO_ERR_INT_EN | \
1031				    B_AX_STF_CMD_OVERFLOW_ERR_INT_EN | \
1032				    B_AX_STF_CMD_UNDERFLOW_ERR_INT_EN | \
1033				    B_AX_STF_WRFF_OVERFLOW_ERR_INT_EN | \
1034				    B_AX_STF_WRFF_UNDERFLOW_ERR_INT_EN | \
1035				    B_AX_STF_OQT_OVERFLOW_ERR_INT_EN | \
1036				    B_AX_STF_OQT_UNDERFLOW_ERR_INT_EN | \
1037				    B_AX_REUSE_EN_ERR_INT_EN | \
1038				    B_AX_REUSE_SIZE_ERR_INT_EN)
1039#define B_AX_OTHER_DISP_IMR_SET_V1 (B_AX_CDR_RX_TIMEOUT_ERR_INT_EN | \
1040				    B_AX_CDR_DMA_TIMEOUT_ERR_INT_EN | \
1041				    B_AX_HDT_HCI_TIMEOUT_ERR_INT_EN | \
1042				    B_AX_HDT_PTR_TIMEOUT_ERR_INT_EN | \
1043				    B_AX_CDT_HCI_TIMEOUT_ERR_INT_EN | \
1044				    B_AX_CDT_PTR_TIMEOUT_ERR_INT_EN | \
1045				    B_AX_STF_OQT_OVERFLOW_ERR_INT_EN | \
1046				    B_AX_STF_OQT_UNDERFLOW_ERR_INT_EN)
1047
1048#define R_AX_DISPATCHER_DBG_PORT 0x8860
1049#define B_AX_DISPATCHER_DBG_SEL_MASK GENMASK(11, 8)
1050#define B_AX_DISPATCHER_INTN_SEL_MASK GENMASK(7, 4)
1051#define B_AX_DISPATCHER_CH_SEL_MASK GENMASK(3, 0)
1052
1053#define R_AX_RXDMA_SETTING 0x8908
1054#define B_AX_BULK_SIZE GENMASK(1, 0)
1055#define USB11_BULKSIZE 0x2
1056#define USB2_BULKSIZE 0x1
1057#define USB3_BULKSIZE 0x0
1058
1059#define R_AX_RX_FUNCTION_STOP 0x8920
1060#define B_AX_HDR_RX_STOP BIT(0)
1061
1062#define R_AX_HCI_FC_CTRL 0x8A00
1063#define B_AX_HCI_FC_CH12_FULL_COND_MASK GENMASK(11, 10)
1064#define B_AX_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8)
1065#define B_AX_HCI_FC_WP_CH07_FULL_COND_MASK GENMASK(7, 6)
1066#define B_AX_HCI_FC_WD_FULL_COND_MASK GENMASK(5, 4)
1067#define B_AX_HCI_FC_CH12_EN BIT(3)
1068#define B_AX_HCI_FC_MODE_MASK GENMASK(2, 1)
1069#define B_AX_HCI_FC_EN BIT(0)
1070
1071#define R_AX_CH_PAGE_CTRL 0x8A04
1072#define B_AX_PREC_PAGE_CH12_MASK GENMASK(24, 16)
1073#define B_AX_PREC_PAGE_CH011_MASK GENMASK(8, 0)
1074
1075#define B_AX_MAX_PG_MASK GENMASK(28, 16)
1076#define B_AX_MIN_PG_MASK GENMASK(12, 0)
1077#define B_AX_GRP BIT(31)
1078#define R_AX_ACH0_PAGE_CTRL 0x8A10
1079#define R_AX_ACH1_PAGE_CTRL 0x8A14
1080#define R_AX_ACH2_PAGE_CTRL 0x8A18
1081#define R_AX_ACH3_PAGE_CTRL 0x8A1C
1082#define R_AX_ACH4_PAGE_CTRL 0x8A20
1083#define R_AX_ACH5_PAGE_CTRL 0x8A24
1084#define R_AX_ACH6_PAGE_CTRL 0x8A28
1085#define R_AX_ACH7_PAGE_CTRL 0x8A2C
1086#define R_AX_CH8_PAGE_CTRL 0x8A30
1087#define R_AX_CH9_PAGE_CTRL 0x8A34
1088#define R_AX_CH10_PAGE_CTRL 0x8A38
1089#define R_AX_CH11_PAGE_CTRL 0x8A3C
1090
1091#define B_AX_AVAL_PG_MASK GENMASK(27, 16)
1092#define B_AX_USE_PG_MASK GENMASK(12, 0)
1093#define R_AX_ACH0_PAGE_INFO 0x8A50
1094#define R_AX_ACH1_PAGE_INFO 0x8A54
1095#define R_AX_ACH2_PAGE_INFO 0x8A58
1096#define R_AX_ACH3_PAGE_INFO 0x8A5C
1097#define R_AX_ACH4_PAGE_INFO 0x8A60
1098#define R_AX_ACH5_PAGE_INFO 0x8A64
1099#define R_AX_ACH6_PAGE_INFO 0x8A68
1100#define R_AX_ACH7_PAGE_INFO 0x8A6C
1101#define R_AX_CH8_PAGE_INFO 0x8A70
1102#define R_AX_CH9_PAGE_INFO 0x8A74
1103#define R_AX_CH10_PAGE_INFO 0x8A78
1104#define R_AX_CH11_PAGE_INFO 0x8A7C
1105#define R_AX_CH12_PAGE_INFO 0x8A80
1106
1107#define R_AX_PUB_PAGE_INFO3 0x8A8C
1108#define B_AX_G1_AVAL_PG_MASK GENMASK(28, 16)
1109#define B_AX_G0_AVAL_PG_MASK GENMASK(12, 0)
1110
1111#define R_AX_PUB_PAGE_CTRL1 0x8A90
1112#define B_AX_PUBPG_G1_MASK GENMASK(28, 16)
1113#define B_AX_PUBPG_G0_MASK GENMASK(12, 0)
1114
1115#define R_AX_PUB_PAGE_CTRL2 0x8A94
1116#define B_AX_PUBPG_ALL_MASK GENMASK(12, 0)
1117
1118#define R_AX_PUB_PAGE_INFO1 0x8A98
1119#define B_AX_G1_USE_PG_MASK GENMASK(28, 16)
1120#define B_AX_G0_USE_PG_MASK GENMASK(12, 0)
1121
1122#define R_AX_PUB_PAGE_INFO2 0x8A9C
1123#define B_AX_PUB_AVAL_PG_MASK GENMASK(12, 0)
1124
1125#define R_AX_WP_PAGE_CTRL1 0x8AA0
1126#define B_AX_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16)
1127#define B_AX_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0)
1128
1129#define R_AX_WP_PAGE_CTRL2 0x8AA4
1130#define B_AX_WP_THRD_MASK GENMASK(12, 0)
1131
1132#define R_AX_WP_PAGE_INFO1 0x8AA8
1133#define B_AX_WP_AVAL_PG_MASK GENMASK(28, 16)
1134
1135#define R_AX_WDE_PKTBUF_CFG 0x8C08
1136#define B_AX_WDE_START_BOUND_MASK GENMASK(13, 8)
1137#define B_AX_WDE_PAGE_SEL_MASK GENMASK(1, 0)
1138#define B_AX_WDE_FREE_PAGE_NUM_MASK GENMASK(28, 16)
1139
1140#define R_AX_WDE_ERRFLAG_MSG 0x8C30
1141#define B_AX_WDE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
1142
1143#define R_AX_WDE_ERR_FLAG_CFG_NUM1 0x8C34
1144#define B_AX_WDE_ERR_FLAG_NUM1_VLD BIT(31)
1145#define B_AX_WDE_ERR_FLAG_NUM1_MSTIDX_MASK GENMASK(27, 24)
1146#define B_AX_WDE_ERR_FLAG_NUM1_ISRIDX_MASK GENMASK(20, 16)
1147#define B_AX_WDE_DATCHN_FRZTMR_MODE BIT(2)
1148#define B_AX_WDE_QUEMGN_FRZTMR_MODE BIT(1)
1149#define B_AX_WDE_BUFMGN_FRZTMR_MODE BIT(0)
1150
1151#define R_AX_WDE_ERR_IMR 0x8C38
1152#define B_AX_WDE_DATCHN_UAPG_ERR_INT_EN BIT(30)
1153#define B_AX_WDE_DATCHN_RRDY_ERR_INT_EN BIT(27)
1154#define B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN BIT(26)
1155#define B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN BIT(25)
1156#define B_AX_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24)
1157#define B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN BIT(19)
1158#define B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN BIT(18)
1159#define B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN BIT(17)
1160#define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16)
1161#define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15)
1162#define B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN BIT(14)
1163#define B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN BIT(13)
1164#define B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN BIT(12)
1165#define B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN BIT(7)
1166#define B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN BIT(6)
1167#define B_AX_WDE_GETNPG_STRPG_ERR_INT_EN BIT(5)
1168#define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(4)
1169#define B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN BIT(3)
1170#define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(2)
1171#define B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN BIT(1)
1172#define B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN BIT(0)
1173#define B_AX_WDE_IMR_CLR (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \
1174			  B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \
1175			  B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
1176			  B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN | \
1177			  B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
1178			  B_AX_WDE_GETNPG_STRPG_ERR_INT_EN | \
1179			  B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN | \
1180			  B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN | \
1181			  B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \
1182			  B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \
1183			  B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \
1184			  B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
1185			  B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
1186			  B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \
1187			  B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \
1188			  B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
1189			  B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \
1190			  B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \
1191			  B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN)
1192#define B_AX_WDE_IMR_CLR_V01 (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \
1193			      B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \
1194			      B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
1195			      B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN | \
1196			      B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
1197			      B_AX_WDE_GETNPG_STRPG_ERR_INT_EN | \
1198			      B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN | \
1199			      B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN | \
1200			      B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \
1201			      B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \
1202			      B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \
1203			      B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
1204			      B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
1205			      B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \
1206			      B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \
1207			      B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
1208			      B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \
1209			      B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \
1210			      B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN | \
1211			      B_AX_WDE_DATCHN_RRDY_ERR_INT_EN | \
1212			      B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN | \
1213			      B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN | \
1214			      B_AX_WDE_DATCHN_UAPG_ERR_INT_EN)
1215#define B_AX_WDE_IMR_SET (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \
1216			  B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \
1217			  B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
1218			  B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN | \
1219			  B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
1220			  B_AX_WDE_GETNPG_STRPG_ERR_INT_EN | \
1221			  B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN | \
1222			  B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN | \
1223			  B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \
1224			  B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \
1225			  B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \
1226			  B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
1227			  B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
1228			  B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \
1229			  B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \
1230			  B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
1231			  B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \
1232			  B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \
1233			  B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN)
1234#define B_AX_WDE_IMR_SET_V01 (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \
1235			      B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \
1236			      B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
1237			      B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN | \
1238			      B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
1239			      B_AX_WDE_GETNPG_STRPG_ERR_INT_EN | \
1240			      B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN | \
1241			      B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN | \
1242			      B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \
1243			      B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \
1244			      B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \
1245			      B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
1246			      B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
1247			      B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \
1248			      B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \
1249			      B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
1250			      B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \
1251			      B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \
1252			      B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN | \
1253			      B_AX_WDE_DATCHN_RRDY_ERR_INT_EN | \
1254			      B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN | \
1255			      B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN)
1256
1257#define B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN BIT(29)
1258#define B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN BIT(28)
1259#define B_AX_WDE_DATCHN_RRDY_ERR_INT_EN BIT(27)
1260#define B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN BIT(26)
1261#define B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN BIT(25)
1262#define B_AX_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24)
1263#define B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN BIT(19)
1264#define B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN BIT(18)
1265#define B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN BIT(17)
1266#define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16)
1267#define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15)
1268#define B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN BIT(14)
1269#define B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9)
1270#define B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN_V1 BIT(8)
1271#define B_AX_WDE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7)
1272#define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 BIT(6)
1273#define B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN_V1 BIT(5)
1274#define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4)
1275#define B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN_V1 BIT(3)
1276#define B_AX_WDE_BUFREQ_SIZELMT_INT_EN BIT(2)
1277#define B_AX_WDE_BUFREQ_SIZE0_INT_EN BIT(1)
1278#define B_AX_WDE_IMR_CLR_V1 (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \
1279			     B_AX_WDE_BUFREQ_SIZE0_INT_EN | \
1280			     B_AX_WDE_BUFREQ_SIZELMT_INT_EN | \
1281			     B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \
1282			     B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \
1283			     B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN_V1 | \
1284			     B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \
1285			     B_AX_WDE_GETNPG_STRPG_ERR_INT_EN_V1 | \
1286			     B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN_V1 | \
1287			     B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \
1288			     B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \
1289			     B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \
1290			     B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \
1291			     B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
1292			     B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
1293			     B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \
1294			     B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \
1295			     B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
1296			     B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \
1297			     B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \
1298			     B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN | \
1299			     B_AX_WDE_DATCHN_RRDY_ERR_INT_EN | \
1300			     B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN | \
1301			     B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN)
1302#define B_AX_WDE_IMR_SET_V1 (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \
1303			     B_AX_WDE_BUFREQ_SIZE0_INT_EN | \
1304			     B_AX_WDE_BUFREQ_SIZELMT_INT_EN | \
1305			     B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \
1306			     B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \
1307			     B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN_V1 | \
1308			     B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \
1309			     B_AX_WDE_GETNPG_STRPG_ERR_INT_EN_V1 | \
1310			     B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN_V1 | \
1311			     B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \
1312			     B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \
1313			     B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \
1314			     B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \
1315			     B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
1316			     B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
1317			     B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \
1318			     B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \
1319			     B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
1320			     B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \
1321			     B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \
1322			     B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN | \
1323			     B_AX_WDE_DATCHN_RRDY_ERR_INT_EN | \
1324			     B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN | \
1325			     B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN)
1326
1327#define R_AX_WDE_ERR_ISR 0x8C3C
1328#define B_AX_WDE_DATCHN_RRDY_ERR BIT(27)
1329#define B_AX_WDE_DATCHN_FRZTO_ERR BIT(26)
1330#define B_AX_WDE_DATCHN_NULLPG_ERR BIT(25)
1331#define B_AX_WDE_DATCHN_ARBT_ERR BIT(24)
1332#define B_AX_WDE_QUEMGN_FRZTO_ERR BIT(19)
1333#define B_AX_WDE_NXTPKTLL_AD_ERR BIT(18)
1334#define B_AX_WDE_PREPKTLLT_AD_ERR BIT(17)
1335#define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR BIT(16)
1336#define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR BIT(15)
1337#define B_AX_WDE_QUE_SRCQUEID_ERR BIT(14)
1338#define B_AX_WDE_QUE_DSTQUEID_ERR BIT(13)
1339#define B_AX_WDE_QUE_CMDTYPE_ERR BIT(12)
1340#define B_AX_WDE_BUFMGN_FRZTO_ERR BIT(7)
1341#define B_AX_WDE_GETNPG_PGOFST_ERR BIT(6)
1342#define B_AX_WDE_GETNPG_STRPG_ERR BIT(5)
1343#define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR BIT(4)
1344#define B_AX_WDE_BUFRTN_SIZE_ERR BIT(3)
1345#define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR BIT(2)
1346#define B_AX_WDE_BUFREQ_UNAVAL_ERR BIT(1)
1347#define B_AX_WDE_BUFREQ_QTAID_ERR BIT(0)
1348
1349#define B_AX_WDE_MAX_SIZE_MASK GENMASK(27, 16)
1350#define B_AX_WDE_MIN_SIZE_MASK GENMASK(11, 0)
1351#define R_AX_WDE_QTA0_CFG 0x8C40
1352#define R_AX_WDE_QTA1_CFG 0x8C44
1353#define R_AX_WDE_QTA2_CFG 0x8C48
1354#define R_AX_WDE_QTA3_CFG 0x8C4C
1355#define R_AX_WDE_QTA4_CFG 0x8C50
1356
1357#define B_AX_DLE_PUB_PGNUM GENMASK(12, 0)
1358#define B_AX_DLE_FREE_HEADPG GENMASK(11, 0)
1359#define B_AX_DLE_FREE_TAILPG GENMASK(27, 16)
1360#define B_AX_DLE_USE_PGNUM GENMASK(27, 16)
1361#define B_AX_DLE_RSV_PGNUM GENMASK(11, 0)
1362#define B_AX_DLE_QEMPTY_GRP GENMASK(31, 0)
1363
1364#define R_AX_WDE_INI_STATUS 0x8D00
1365#define B_AX_WDE_Q_MGN_INI_RDY BIT(1)
1366#define B_AX_WDE_BUF_MGN_INI_RDY BIT(0)
1367#define WDE_MGN_INI_RDY (B_AX_WDE_Q_MGN_INI_RDY | B_AX_WDE_BUF_MGN_INI_RDY)
1368#define R_AX_WDE_DBG_FUN_INTF_CTL 0x8D10
1369#define B_AX_WDE_DFI_ACTIVE BIT(31)
1370#define B_AX_WDE_DFI_TRGSEL_MASK GENMASK(19, 16)
1371#define B_AX_WDE_DFI_ADDR_MASK GENMASK(15, 0)
1372#define R_AX_WDE_DBG_FUN_INTF_DATA 0x8D14
1373#define B_AX_WDE_DFI_DATA_MASK GENMASK(31, 0)
1374
1375#define R_AX_PLE_PKTBUF_CFG 0x9008
1376#define B_AX_PLE_START_BOUND_MASK GENMASK(13, 8)
1377#define B_AX_PLE_PAGE_SEL_MASK GENMASK(1, 0)
1378#define B_AX_PLE_FREE_PAGE_NUM_MASK GENMASK(28, 16)
1379
1380#define R_AX_PLE_DBGERR_LOCKEN 0x9020
1381#define B_AX_PLE_LOCKEN_DLEPIF07 BIT(7)
1382#define B_AX_PLE_LOCKEN_DLEPIF06 BIT(6)
1383#define B_AX_PLE_LOCKEN_DLEPIF05 BIT(5)
1384#define B_AX_PLE_LOCKEN_DLEPIF04 BIT(4)
1385#define B_AX_PLE_LOCKEN_DLEPIF03 BIT(3)
1386#define B_AX_PLE_LOCKEN_DLEPIF02 BIT(2)
1387#define B_AX_PLE_LOCKEN_DLEPIF01 BIT(1)
1388#define B_AX_PLE_LOCKEN_DLEPIF00 BIT(0)
1389
1390#define R_AX_PLE_DBGERR_STS 0x9024
1391#define B_AX_PLE_LOCKON_DLEPIF07 BIT(7)
1392#define B_AX_PLE_LOCKON_DLEPIF06 BIT(6)
1393#define B_AX_PLE_LOCKON_DLEPIF05 BIT(5)
1394#define B_AX_PLE_LOCKON_DLEPIF04 BIT(4)
1395#define B_AX_PLE_LOCKON_DLEPIF03 BIT(3)
1396#define B_AX_PLE_LOCKON_DLEPIF02 BIT(2)
1397#define B_AX_PLE_LOCKON_DLEPIF01 BIT(1)
1398#define B_AX_PLE_LOCKON_DLEPIF00 BIT(0)
1399
1400#define R_AX_PLE_ERR_FLAG_CFG_NUM1 0x9034
1401#define B_AX_PLE_ERR_FLAG_NUM1_VLD BIT(31)
1402#define B_AX_PLE_ERR_FLAG_NUM1_MSTIDX_MASK GENMASK(27, 24)
1403#define B_AX_PLE_ERR_FLAG_NUM1_ISRIDX_MASK GENMASK(20, 16)
1404#define B_AX_PLE_DATCHN_FRZTMR_MODE BIT(2)
1405#define B_AX_PLE_QUEMGN_FRZTMR_MODE BIT(1)
1406#define B_AX_PLE_BUFMGN_FRZTMR_MODE BIT(0)
1407
1408#define R_AX_PLE_ERRFLAG_MSG 0x9030
1409#define B_AX_PLE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
1410#define B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN BIT(29)
1411#define B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN BIT(28)
1412#define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9)
1413#define B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 BIT(8)
1414#define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7)
1415#define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 BIT(6)
1416#define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 BIT(5)
1417#define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4)
1418#define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 BIT(3)
1419#define B_AX_PLE_BUFREQ_SIZELMT_INT_EN BIT(2)
1420#define B_AX_PLE_BUFREQ_SIZE0_INT_EN BIT(1)
1421#define B_AX_PLE_DATCHN_CAMREQ_ERR BIT(29)
1422#define B_AX_PLE_DATCHN_ADRERR_ERR BIT(28)
1423#define B_AX_PLE_BUFMGN_FRZTO_ERR_V1 BIT(9)
1424#define B_AX_PLE_GETNPG_PGOFST_ERR_V1 BIT(8)
1425#define B_AX_PLE_GETNPG_STRPG_ERR_V1 BIT(7)
1426#define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_V1 BIT(6)
1427#define B_AX_PLE_BUFRTN_SIZE_ERR_V1 BIT(5)
1428#define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_V1 BIT(4)
1429#define B_AX_PLE_BUFREQ_UNAVAL_ERR_V1 BIT(3)
1430#define B_AX_PLE_BUFREQ_SIZELMT_ERR BIT(2)
1431#define B_AX_PLE_BUFREQ_SIZE0_ERR BIT(1)
1432
1433#define R_AX_PLE_ERR_IMR 0x9038
1434#define B_AX_PLE_DATCHN_RRDY_ERR_INT_EN BIT(27)
1435#define B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN BIT(26)
1436#define B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN BIT(25)
1437#define B_AX_PLE_DATCHN_ARBT_ERR_INT_EN BIT(24)
1438#define B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN BIT(19)
1439#define B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN BIT(18)
1440#define B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN BIT(17)
1441#define B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16)
1442#define B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15)
1443#define B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN BIT(14)
1444#define B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN BIT(13)
1445#define B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN BIT(12)
1446#define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN BIT(7)
1447#define B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN BIT(6)
1448#define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN BIT(5)
1449#define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(4)
1450#define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN BIT(3)
1451#define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(2)
1452#define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN BIT(1)
1453#define B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN BIT(0)
1454#define B_AX_PLE_IMR_CLR (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \
1455			  B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN | \
1456			  B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
1457			  B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN | \
1458			  B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
1459			  B_AX_PLE_GETNPG_STRPG_ERR_INT_EN | \
1460			  B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN | \
1461			  B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN | \
1462			  B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \
1463			  B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \
1464			  B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \
1465			  B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
1466			  B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
1467			  B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \
1468			  B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \
1469			  B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \
1470			  B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \
1471			  B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \
1472			  B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN)
1473#define B_AX_PLE_IMR_SET (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \
1474			  B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN | \
1475			  B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
1476			  B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN | \
1477			  B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
1478			  B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN | \
1479			  B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN | \
1480			  B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \
1481			  B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \
1482			  B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \
1483			  B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
1484			  B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
1485			  B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \
1486			  B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \
1487			  B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \
1488			  B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \
1489			  B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \
1490			  B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN)
1491
1492#define B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN BIT(29)
1493#define B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN BIT(28)
1494#define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9)
1495#define B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 BIT(8)
1496#define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7)
1497#define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 BIT(6)
1498#define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 BIT(5)
1499#define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4)
1500#define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 BIT(3)
1501#define B_AX_PLE_BUFREQ_SIZELMT_INT_EN BIT(2)
1502#define B_AX_PLE_BUFREQ_SIZE0_INT_EN BIT(1)
1503#define B_AX_PLE_IMR_CLR_V1 (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \
1504			     B_AX_PLE_BUFREQ_SIZE0_INT_EN | \
1505			     B_AX_PLE_BUFREQ_SIZELMT_INT_EN | \
1506			     B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \
1507			     B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \
1508			     B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 | \
1509			     B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \
1510			     B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 | \
1511			     B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 | \
1512			     B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \
1513			     B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \
1514			     B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \
1515			     B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \
1516			     B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
1517			     B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
1518			     B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \
1519			     B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \
1520			     B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \
1521			     B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \
1522			     B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \
1523			     B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN | \
1524			     B_AX_PLE_DATCHN_RRDY_ERR_INT_EN | \
1525			     B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN | \
1526			     B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN)
1527#define B_AX_PLE_IMR_SET_V1 (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \
1528			     B_AX_PLE_BUFREQ_SIZE0_INT_EN | \
1529			     B_AX_PLE_BUFREQ_SIZELMT_INT_EN | \
1530			     B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \
1531			     B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \
1532			     B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 | \
1533			     B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \
1534			     B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 | \
1535			     B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 | \
1536			     B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \
1537			     B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \
1538			     B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \
1539			     B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \
1540			     B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
1541			     B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
1542			     B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \
1543			     B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \
1544			     B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \
1545			     B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \
1546			     B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \
1547			     B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN | \
1548			     B_AX_PLE_DATCHN_RRDY_ERR_INT_EN | \
1549			     B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN | \
1550			     B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN)
1551
1552#define R_AX_PLE_ERR_FLAG_ISR 0x903C
1553#define B_AX_PLE_MAX_SIZE_MASK GENMASK(27, 16)
1554#define B_AX_PLE_MIN_SIZE_MASK GENMASK(11, 0)
1555#define R_AX_PLE_QTA0_CFG 0x9040
1556#define R_AX_PLE_QTA1_CFG 0x9044
1557#define R_AX_PLE_QTA2_CFG 0x9048
1558#define R_AX_PLE_QTA3_CFG 0x904C
1559#define R_AX_PLE_QTA4_CFG 0x9050
1560#define R_AX_PLE_QTA5_CFG 0x9054
1561#define R_AX_PLE_QTA6_CFG 0x9058
1562#define B_AX_PLE_Q6_MAX_SIZE_MASK GENMASK(27, 16)
1563#define B_AX_PLE_Q6_MIN_SIZE_MASK GENMASK(11, 0)
1564#define R_AX_PLE_QTA7_CFG 0x905C
1565#define B_AX_PLE_Q7_MAX_SIZE_MASK GENMASK(27, 16)
1566#define B_AX_PLE_Q7_MIN_SIZE_MASK GENMASK(11, 0)
1567#define R_AX_PLE_QTA8_CFG 0x9060
1568#define R_AX_PLE_QTA9_CFG 0x9064
1569#define R_AX_PLE_QTA10_CFG 0x9068
1570#define R_AX_PLE_QTA11_CFG 0x906C
1571
1572#define R_AX_PLE_INI_STATUS 0x9100
1573#define B_AX_PLE_Q_MGN_INI_RDY BIT(1)
1574#define B_AX_PLE_BUF_MGN_INI_RDY BIT(0)
1575#define PLE_MGN_INI_RDY (B_AX_PLE_Q_MGN_INI_RDY | B_AX_PLE_BUF_MGN_INI_RDY)
1576#define R_AX_PLE_DBG_FUN_INTF_CTL 0x9110
1577#define B_AX_PLE_DFI_ACTIVE BIT(31)
1578#define B_AX_PLE_DFI_TRGSEL_MASK GENMASK(19, 16)
1579#define B_AX_PLE_DFI_ADDR_MASK GENMASK(15, 0)
1580#define R_AX_PLE_DBG_FUN_INTF_DATA 0x9114
1581#define B_AX_PLE_DFI_DATA_MASK GENMASK(31, 0)
1582
1583#define R_AX_WDRLS_CFG 0x9408
1584#define B_AX_RLSRPT_BUFREQ_TO_MASK GENMASK(15, 8)
1585#define B_AX_WDRLS_MODE_MASK GENMASK(1, 0)
1586
1587#define R_AX_RLSRPT0_CFG0 0x9410
1588#define B_AX_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24)
1589#define B_AX_RLSRPT0_PKTTYPE_MASK GENMASK(19, 16)
1590#define B_AX_RLSRPT0_PID_MASK GENMASK(10, 8)
1591#define B_AX_RLSRPT0_QID_MASK GENMASK(5, 0)
1592
1593#define R_AX_RLSRPT0_CFG1 0x9414
1594#define B_AX_RLSRPT0_TO_MASK GENMASK(23, 16)
1595#define B_AX_RLSRPT0_AGGNUM_MASK GENMASK(7, 0)
1596
1597#define R_AX_WDRLS_ERR_IMR 0x9430
1598#define B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN BIT(13)
1599#define B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN BIT(12)
1600#define B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN BIT(9)
1601#define B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN BIT(8)
1602#define B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN BIT(5)
1603#define B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN BIT(4)
1604#define B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN BIT(2)
1605#define B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN BIT(1)
1606#define B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN BIT(0)
1607#define B_AX_WDRLS_IMR_EN_CLR (B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \
1608			       B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \
1609			       B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN | \
1610			       B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN | \
1611			       B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \
1612			       B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \
1613			       B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN | \
1614			       B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \
1615			       B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN)
1616#define B_AX_WDRLS_IMR_SET (B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \
1617			    B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \
1618			    B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN | \
1619			    B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \
1620			    B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \
1621			    B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN | \
1622			    B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \
1623			    B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN)
1624#define B_AX_WDRLS_IMR_SET_V1 (B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \
1625			      B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \
1626			      B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN | \
1627			      B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN | \
1628			      B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \
1629			      B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \
1630			      B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN | \
1631			      B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \
1632			      B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN)
1633
1634#define R_AX_WDRLS_ERR_ISR 0x9434
1635
1636#define R_AX_BBRPT_COM_ERR_IMR 0x9608
1637#define B_AX_BBRPT_COM_HANG_EN BIT(1)
1638#define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN BIT(0)
1639
1640#define R_AX_BBRPT_COM_ERR_IMR_ISR 0x960C
1641#define B_AX_BBRPT_COM_NULL_PLPKTID_ERR BIT(16)
1642#define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN BIT(0)
1643
1644#define R_AX_BBRPT_COM_ERR_ISR 0x960C
1645#define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_V1 BIT(0)
1646
1647#define R_AX_BBRPT_CHINFO_ERR_ISR 0x962C
1648#define B_AX_BBPRT_CHIF_TO_ERR_V1 BIT(7)
1649#define B_AX_BBPRT_CHIF_NULL_ERR_V1 BIT(6)
1650#define B_AX_BBPRT_CHIF_LEFT2_ERR_V1 BIT(5)
1651#define B_AX_BBPRT_CHIF_LEFT1_ERR_V1 BIT(4)
1652#define B_AX_BBPRT_CHIF_HDRL_ERR_V1 BIT(3)
1653#define B_AX_BBPRT_CHIF_BOVF_ERR_V1 BIT(2)
1654#define B_AX_BBPRT_CHIF_OVF_ERR_V1 BIT(1)
1655#define B_AX_BBPRT_CHIF_BB_TO_ERR_V1 BIT(0)
1656
1657#define R_AX_BBRPT_CHINFO_ERR_IMR 0x9628
1658#define B_AX_BBPRT_CHIF_TO_ERR_INT_EN BIT(7)
1659#define B_AX_BBPRT_CHIF_NULL_ERR_INT_EN BIT(6)
1660#define B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN BIT(5)
1661#define B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN BIT(4)
1662#define B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN BIT(3)
1663#define B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN BIT(2)
1664#define B_AX_BBPRT_CHIF_OVF_ERR_INT_EN BIT(1)
1665#define B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN BIT(0)
1666#define R_AX_BBRPT_CHINFO_IMR_SET_V1 (B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN | \
1667				      B_AX_BBPRT_CHIF_OVF_ERR_INT_EN | \
1668				      B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN | \
1669				      B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN | \
1670				      B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN | \
1671				      B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN | \
1672				      B_AX_BBPRT_CHIF_NULL_ERR_INT_EN | \
1673				      B_AX_BBPRT_CHIF_TO_ERR_INT_EN)
1674
1675#define R_AX_BBRPT_CHINFO_ERR_IMR_ISR 0x962C
1676#define B_AX_BBPRT_CHIF_TO_ERR BIT(23)
1677#define B_AX_BBPRT_CHIF_NULL_ERR BIT(22)
1678#define B_AX_BBPRT_CHIF_LEFT2_ERR BIT(21)
1679#define B_AX_BBPRT_CHIF_LEFT1_ERR BIT(20)
1680#define B_AX_BBPRT_CHIF_HDRL_ERR BIT(19)
1681#define B_AX_BBPRT_CHIF_BOVF_ERR BIT(18)
1682#define B_AX_BBPRT_CHIF_OVF_ERR BIT(17)
1683#define B_AX_BBPRT_CHIF_BB_TO_ERR BIT(16)
1684#define B_AX_BBPRT_CHIF_TO_ERR_INT_EN BIT(7)
1685#define B_AX_BBPRT_CHIF_NULL_ERR_INT_EN BIT(6)
1686#define B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN BIT(5)
1687#define B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN BIT(4)
1688#define B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN BIT(3)
1689#define B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN BIT(2)
1690#define B_AX_BBPRT_CHIF_OVF_ERR_INT_EN BIT(1)
1691#define B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN BIT(0)
1692#define B_AX_BBRPT_CHINFO_IMR_CLR (B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN | \
1693				   B_AX_BBPRT_CHIF_OVF_ERR_INT_EN | \
1694				   B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN | \
1695				   B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN | \
1696				   B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN | \
1697				   B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN | \
1698				   B_AX_BBPRT_CHIF_NULL_ERR_INT_EN | \
1699				   B_AX_BBPRT_CHIF_TO_ERR_INT_EN)
1700
1701#define R_AX_BBRPT_DFS_ERR_IMR 0x9638
1702#define B_AX_BBRPT_DFS_TO_ERR_INT_EN BIT(0)
1703
1704#define R_AX_BBRPT_DFS_ERR_IMR_ISR 0x963C
1705#define B_AX_BBRPT_DFS_TO_ERR BIT(16)
1706#define B_AX_BBRPT_DFS_TO_ERR_INT_EN BIT(0)
1707
1708#define R_AX_BBRPT_DFS_ERR_ISR 0x963C
1709#define B_AX_BBRPT_DFS_TO_ERR_V1 BIT(0)
1710
1711#define R_AX_LA_ERRFLAG 0x966C
1712#define B_AX_LA_ISR_DATA_LOSS_ERR BIT(16)
1713#define B_AX_LA_IMR_DATA_LOSS_ERR BIT(0)
1714
1715#define R_AX_WD_BUF_REQ 0x9800
1716#define R_AX_PL_BUF_REQ 0x9820
1717#define B_AX_WD_BUF_REQ_EXEC BIT(31)
1718#define B_AX_WD_BUF_REQ_QUOTA_ID_MASK GENMASK(23, 16)
1719#define B_AX_WD_BUF_REQ_LEN_MASK GENMASK(15, 0)
1720
1721#define R_AX_WD_BUF_STATUS 0x9804
1722#define R_AX_PL_BUF_STATUS 0x9824
1723#define B_AX_WD_BUF_STAT_DONE BIT(31)
1724#define B_AX_WD_BUF_STAT_PKTID_MASK GENMASK(11, 0)
1725#define S_WD_BUF_STAT_PKTID_INVALID GENMASK(11, 0)
1726
1727#define R_AX_WD_CPUQ_OP_0 0x9810
1728#define R_AX_PL_CPUQ_OP_0 0x9830
1729#define B_AX_WD_CPUQ_OP_EXEC BIT(31)
1730#define B_AX_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24)
1731#define B_AX_CPUQ_OP_MACID_MASK GENMASK(23, 16)
1732#define B_AX_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0)
1733
1734#define R_AX_WD_CPUQ_OP_1 0x9814
1735#define R_AX_PL_CPUQ_OP_1 0x9834
1736#define B_AX_CPUQ_OP_SRC_PID_MASK GENMASK(24, 22)
1737#define B_AX_CPUQ_OP_SRC_QID_MASK GENMASK(21, 16)
1738#define B_AX_CPUQ_OP_DST_PID_MASK GENMASK(8, 6)
1739#define B_AX_CPUQ_OP_DST_QID_MASK GENMASK(5, 0)
1740
1741#define R_AX_WD_CPUQ_OP_2 0x9818
1742#define R_AX_PL_CPUQ_OP_2 0x9838
1743#define B_AX_WD_CPUQ_OP_STRT_PKTID_MASK GENMASK(27, 16)
1744#define B_AX_WD_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0)
1745
1746#define R_AX_WD_CPUQ_OP_STATUS 0x981C
1747#define R_AX_PL_CPUQ_OP_STATUS 0x983C
1748#define B_AX_WD_CPUQ_OP_STAT_DONE BIT(31)
1749#define B_AX_WD_CPUQ_OP_PKTID_MASK GENMASK(11, 0)
1750
1751#define R_AX_CPUIO_ERR_IMR 0x9840
1752#define B_AX_PLEQUE_OP_ERR_INT_EN BIT(12)
1753#define B_AX_PLEBUF_OP_ERR_INT_EN BIT(8)
1754#define B_AX_WDEQUE_OP_ERR_INT_EN BIT(4)
1755#define B_AX_WDEBUF_OP_ERR_INT_EN BIT(0)
1756#define B_AX_CPUIO_IMR_CLR (B_AX_WDEBUF_OP_ERR_INT_EN | \
1757			    B_AX_WDEQUE_OP_ERR_INT_EN | \
1758			    B_AX_PLEBUF_OP_ERR_INT_EN | \
1759			    B_AX_PLEQUE_OP_ERR_INT_EN)
1760#define B_AX_CPUIO_IMR_SET (B_AX_WDEBUF_OP_ERR_INT_EN | \
1761			    B_AX_WDEQUE_OP_ERR_INT_EN | \
1762			    B_AX_PLEBUF_OP_ERR_INT_EN | \
1763			    B_AX_PLEQUE_OP_ERR_INT_EN)
1764
1765#define R_AX_CPUIO_ERR_ISR 0x9844
1766
1767#define R_AX_SEC_ERR_IMR_ISR 0x991C
1768
1769#define R_AX_PKTIN_SETTING 0x9A00
1770#define B_AX_WD_ADDR_INFO_LENGTH BIT(1)
1771
1772#define R_AX_PKTIN_ERR_IMR 0x9A20
1773#define B_AX_PKTIN_GETPKTID_ERR_INT_EN BIT(0)
1774
1775#define R_AX_PKTIN_ERR_ISR 0x9A24
1776
1777#define R_AX_MPDU_TX_ERR_ISR 0x9BF0
1778#define R_AX_MPDU_TX_ERR_IMR 0x9BF4
1779#define B_AX_TX_KSRCH_ERR_EN BIT(9)
1780#define B_AX_TX_NW_TYPE_ERR_EN BIT(8)
1781#define B_AX_TX_LLC_PRE_ERR_EN BIT(7)
1782#define B_AX_TX_ETH_TYPE_ERR_EN BIT(6)
1783#define B_AX_TX_HDR3_SIZE_ERR_INT_EN BIT(5)
1784#define B_AX_TX_OFFSET_ERR_INT_EN BIT(4)
1785#define B_AX_TX_MPDU_SIZE_ZERO_INT_EN BIT(3)
1786#define B_AX_TX_NXT_ERRPKTID_INT_EN BIT(2)
1787#define B_AX_TX_GET_ERRPKTID_INT_EN BIT(1)
1788#define B_AX_MPDU_TX_IMR_SET_V1 (B_AX_TX_GET_ERRPKTID_INT_EN | \
1789				 B_AX_TX_NXT_ERRPKTID_INT_EN | \
1790				 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | \
1791				 B_AX_TX_HDR3_SIZE_ERR_INT_EN | \
1792				 B_AX_TX_ETH_TYPE_ERR_EN | \
1793				 B_AX_TX_NW_TYPE_ERR_EN | \
1794				 B_AX_TX_KSRCH_ERR_EN)
1795
1796#define R_AX_MPDU_PROC 0x9C00
1797#define B_AX_A_ICV_ERR BIT(1)
1798#define B_AX_APPEND_FCS BIT(0)
1799
1800#define R_AX_ACTION_FWD0 0x9C04
1801#define TRXCFG_MPDU_PROC_ACT_FRWD 0x02A95A95
1802
1803#define R_AX_ACTION_FWD1 0x9C08
1804
1805#define R_AX_TF_FWD 0x9C14
1806#define TRXCFG_MPDU_PROC_TF_FRWD 0x0000AA55
1807
1808#define R_AX_HW_RPT_FWD 0x9C18
1809#define B_AX_FWD_PPDU_STAT_MASK GENMASK(1, 0)
1810#define RTW89_PRPT_DEST_HOST 1
1811#define RTW89_PRPT_DEST_WLCPU 2
1812
1813#define R_AX_CUT_AMSDU_CTRL 0x9C40
1814#define TRXCFG_MPDU_PROC_CUT_CTRL	0x010E05F0
1815
1816#define R_AX_WOW_CTRL 0x9C50
1817#define B_AX_WOW_WOWEN BIT(1)
1818
1819#define R_AX_MPDU_RX_ERR_ISR 0x9CF0
1820#define R_AX_MPDU_RX_ERR_IMR 0x9CF4
1821#define B_AX_RPT_ERR_INT_EN BIT(3)
1822#define B_AX_MHDRLEN_ERR_INT_EN BIT(1)
1823#define B_AX_GETPKTID_ERR_INT_EN BIT(0)
1824#define B_AX_MPDU_RX_IMR_SET_V1 B_AX_RPT_ERR_INT_EN
1825
1826#define R_AX_SEC_ENG_CTRL 0x9D00
1827#define B_AX_SEC_DBG_PORT_FIELD_MASK GENMASK(19, 16)
1828#define B_AX_TX_PARTIAL_MODE BIT(11)
1829#define B_AX_CLK_EN_CGCMP BIT(10)
1830#define B_AX_CLK_EN_WAPI BIT(9)
1831#define B_AX_CLK_EN_WEP_TKIP BIT(8)
1832#define B_AX_BMC_MGNT_DEC BIT(5)
1833#define B_AX_UC_MGNT_DEC BIT(4)
1834#define B_AX_MC_DEC BIT(3)
1835#define B_AX_BC_DEC BIT(2)
1836#define B_AX_SEC_RX_DEC BIT(1)
1837#define B_AX_SEC_TX_ENC BIT(0)
1838
1839#define R_AX_SEC_MPDU_PROC 0x9D04
1840#define B_AX_APPEND_ICV BIT(1)
1841#define B_AX_APPEND_MIC BIT(0)
1842
1843#define R_AX_SEC_CAM_ACCESS 0x9D10
1844#define R_AX_SEC_CAM_RDATA 0x9D14
1845#define R_AX_SEC_CAM_WDATA 0x9D18
1846
1847#define R_AX_SEC_DEBUG 0x9D1C
1848#define B_AX_IMR_ERROR BIT(3)
1849
1850#define R_AX_SEC_DEBUG1 0x9D1C
1851#define B_AX_TX_TIMEOUT_SEL_MASK GENMASK(31, 30)
1852#define AX_TX_TO_VAL  0x2
1853
1854#define R_AX_SEC_TX_DEBUG 0x9D20
1855#define R_AX_SEC_RX_DEBUG 0x9D24
1856#define R_AX_SEC_TRX_PKT_CNT 0x9D28
1857
1858#define R_AX_SEC_DEBUG2 0x9D28
1859#define B_AX_DBG_READ_SH 2
1860#define B_AX_DBG_READ_MSK 0x3fffffff
1861
1862#define R_AX_SEC_TRX_BLK_CNT 0x9D2C
1863
1864#define R_AX_SEC_ERROR_FLAG_IMR 0x9D2C
1865#define B_AX_RX_HANG_IMR BIT(1)
1866#define B_AX_TX_HANG_IMR BIT(0)
1867
1868#define R_AX_SEC_ERROR_FLAG 0x9D30
1869#define B_AX_RX_HANG_ERROR_V1 BIT(1)
1870#define B_AX_TX_HANG_ERROR_V1 BIT(0)
1871
1872#define R_AX_SS_CTRL 0x9E10
1873#define B_AX_SS_INIT_DONE_1 BIT(31)
1874#define B_AX_SS_WARM_INIT_FLG BIT(29)
1875#define B_AX_SS_NONEMPTY_SS2FINFO_EN BIT(28)
1876#define B_AX_SS_EN BIT(0)
1877
1878#define R_AX_SS2FINFO_PATH 0x9E50
1879#define B_AX_SS_UL_REL BIT(31)
1880#define B_AX_SS_REL_QUEUE_MASK GENMASK(29, 24)
1881#define B_AX_SS_REL_PORT_MASK GENMASK(18, 16)
1882#define B_AX_SS_DEST_QUEUE_MASK GENMASK(13, 8)
1883#define SS2F_PATH_WLCPU 0x0A
1884#define B_AX_SS_DEST_PORT_MASK GENMASK(2, 0)
1885
1886#define R_AX_SS_MACID_PAUSE_0 0x9EB0
1887#define B_AX_SS_MACID31_0_PAUSE_SH 0
1888#define B_AX_SS_MACID31_0_PAUSE_MASK GENMASK(31, 0)
1889
1890#define R_AX_SS_MACID_PAUSE_1 0x9EB4
1891#define B_AX_SS_MACID63_32_PAUSE_SH 0
1892#define B_AX_SS_MACID63_32_PAUSE_MASK GENMASK(31, 0)
1893
1894#define R_AX_SS_MACID_PAUSE_2 0x9EB8
1895#define B_AX_SS_MACID95_64_PAUSE_SH 0
1896#define B_AX_SS_MACID95_64_PAUSE_MASK GENMASK(31, 0)
1897
1898#define R_AX_SS_MACID_PAUSE_3 0x9EBC
1899#define B_AX_SS_MACID127_96_PAUSE_SH 0
1900#define B_AX_SS_MACID127_96_PAUSE_MASK GENMASK(31, 0)
1901
1902#define R_AX_STA_SCHEDULER_ERR_IMR 0x9EF0
1903#define B_AX_PLE_B_PKTID_ERR_INT_EN BIT(2)
1904#define B_AX_RPT_HANG_TIMEOUT_INT_EN BIT(1)
1905#define B_AX_SEARCH_HANG_TIMEOUT_INT_EN BIT(0)
1906#define B_AX_STA_SCHEDULER_IMR_SET (B_AX_SEARCH_HANG_TIMEOUT_INT_EN | \
1907				    B_AX_RPT_HANG_TIMEOUT_INT_EN | \
1908				    B_AX_PLE_B_PKTID_ERR_INT_EN)
1909
1910#define R_AX_STA_SCHEDULER_ERR_ISR 0x9EF4
1911
1912#define R_AX_TXPKTCTL_ERR_IMR_ISR 0x9F1C
1913#define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR BIT(25)
1914#define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR BIT(24)
1915#define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR BIT(19)
1916#define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR BIT(18)
1917#define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR BIT(17)
1918#define B_AX_TXPKTCTL_USRCTL_REINIT_ERR BIT(16)
1919#define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9)
1920#define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN BIT(8)
1921#define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN BIT(3)
1922#define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN BIT(2)
1923#define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN BIT(1)
1924#define B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN BIT(0)
1925#define B_AX_TXPKTCTL_IMR_B0_CLR (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \
1926				  B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN | \
1927				  B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN | \
1928				  B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | \
1929				  B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN | \
1930				  B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN)
1931#define B_AX_TXPKTCTL_IMR_B1_CLR (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \
1932				  B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN | \
1933				  B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN | \
1934				  B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | \
1935				  B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN | \
1936				  B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN)
1937#define B_AX_TXPKTCTL_IMR_B0_SET (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \
1938				  B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN)
1939#define B_AX_TXPKTCTL_IMR_B1_SET (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \
1940				  B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN | \
1941				  B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN | \
1942				  B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN)
1943
1944#define R_AX_TXPKTCTL_ERR_IMR_ISR_B1 0x9F2C
1945#define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9)
1946#define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN BIT(3)
1947#define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN BIT(2)
1948#define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN BIT(1)
1949
1950#define R_AX_DBG_FUN_INTF_CTL 0x9F30
1951#define B_AX_DFI_ACTIVE BIT(31)
1952#define B_AX_DFI_TRGSEL_MASK GENMASK(19, 16)
1953#define B_AX_DFI_ADDR_MASK GENMASK(15, 0)
1954#define R_AX_DBG_FUN_INTF_DATA 0x9F34
1955#define B_AX_DFI_DATA_MASK GENMASK(31, 0)
1956
1957#define R_AX_TXPKTCTL_B0_PRELD_CFG0 0x9F48
1958#define B_AX_B0_PRELD_FEN BIT(31)
1959#define B_AX_B0_PRELD_USEMAXSZ_MASK GENMASK(25, 16)
1960#define PRELD_B0_ENT_NUM 10
1961#define PRELD_AMSDU_SIZE 52
1962#define B_AX_B0_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)
1963#define B_AX_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
1964
1965#define R_AX_TXPKTCTL_B0_PRELD_CFG1 0x9F4C
1966#define B_AX_B0_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)
1967#define PRELD_NEXT_WND 1
1968#define B_AX_B0_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
1969
1970#define R_AX_TXPKTCTL_B0_ERRFLAG_IMR 0x9F78
1971#define B_AX_B0_IMR_ERR_PRELD_ENTNUMCFG BIT(21)
1972#define B_AX_B0_IMR_ERR_PRELD_RLSPKTSZERR BIT(20)
1973#define B_AX_B0_IMR_ERR_MPDUIF_DATAERR BIT(18)
1974#define B_AX_B0_IMR_ERR_MPDUINFO_RECFG BIT(16)
1975#define B_AX_B0_IMR_ERR_CMDPSR_TBLSZ BIT(11)
1976#define B_AX_B0_IMR_ERR_CMDPSR_FRZTO BIT(10)
1977#define B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE BIT(9)
1978#define B_AX_B0_IMR_ERR_CMDPSR_1STCMDERR BIT(8)
1979#define B_AX_B0_IMR_ERR_USRCTL_RLSBMPLEN BIT(3)
1980#define B_AX_B0_IMR_ERR_USRCTL_RDNRLSCMD BIT(2)
1981#define B_AX_B0_IMR_ERR_USRCTL_NOINIT BIT(1)
1982#define B_AX_B0_IMR_ERR_USRCTL_REINIT BIT(0)
1983#define B_AX_TXPKTCTL_IMR_B0_CLR_V1 (B_AX_B0_IMR_ERR_USRCTL_REINIT | \
1984				     B_AX_B0_IMR_ERR_USRCTL_NOINIT | \
1985				     B_AX_B0_IMR_ERR_USRCTL_RDNRLSCMD | \
1986				     B_AX_B0_IMR_ERR_USRCTL_RLSBMPLEN | \
1987				     B_AX_B0_IMR_ERR_CMDPSR_1STCMDERR | \
1988				     B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE | \
1989				     B_AX_B0_IMR_ERR_CMDPSR_FRZTO | \
1990				     B_AX_B0_IMR_ERR_CMDPSR_TBLSZ | \
1991				     B_AX_B0_IMR_ERR_MPDUINFO_RECFG | \
1992				     B_AX_B0_IMR_ERR_MPDUIF_DATAERR | \
1993				     B_AX_B0_IMR_ERR_PRELD_RLSPKTSZERR | \
1994				     B_AX_B0_IMR_ERR_PRELD_ENTNUMCFG)
1995#define B_AX_TXPKTCTL_IMR_B0_SET_V1 (B_AX_B0_IMR_ERR_USRCTL_REINIT | \
1996				     B_AX_B0_IMR_ERR_USRCTL_NOINIT | \
1997				     B_AX_B0_IMR_ERR_CMDPSR_1STCMDERR | \
1998				     B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE | \
1999				     B_AX_B0_IMR_ERR_CMDPSR_TBLSZ | \
2000				     B_AX_B0_IMR_ERR_MPDUINFO_RECFG | \
2001				     B_AX_B0_IMR_ERR_MPDUIF_DATAERR | \
2002				     B_AX_B0_IMR_ERR_PRELD_RLSPKTSZERR | \
2003				     B_AX_B0_IMR_ERR_PRELD_ENTNUMCFG)
2004
2005#define R_AX_TXPKTCTL_B0_ERRFLAG_ISR 0x9F7C
2006#define B_AX_B0_ISR_ERR_PRELD_EVT3 BIT(23)
2007#define B_AX_B0_ISR_ERR_PRELD_EVT2 BIT(22)
2008#define B_AX_B0_ISR_ERR_PRELD_ENTNUMCFG BIT(21)
2009#define B_AX_B0_ISR_ERR_PRELD_RLSPKTSZERR BIT(20)
2010#define B_AX_B0_ISR_ERR_MPDUIF_ERR1 BIT(19)
2011#define B_AX_B0_ISR_ERR_MPDUIF_DATAERR BIT(18)
2012#define B_AX_B0_ISR_ERR_MPDUINFO_ERR1 BIT(17)
2013#define B_AX_B0_ISR_ERR_MPDUINFO_RECFG BIT(16)
2014#define B_AX_B0_ISR_ERR_CMDPSR_TBLSZ BIT(11)
2015#define B_AX_B0_ISR_ERR_CMDPSR_FRZTO BIT(10)
2016#define B_AX_B0_ISR_ERR_CMDPSR_CMDTYPE BIT(9)
2017#define B_AX_B0_ISR_ERR_CMDPSR_1STCMDERR BIT(8)
2018#define B_AX_B0_ISR_ERR_USRCTL_EVT7 BIT(7)
2019#define B_AX_B0_ISR_ERR_USRCTL_EVT6 BIT(6)
2020#define B_AX_B0_ISR_ERR_USRCTL_EVT5 BIT(5)
2021#define B_AX_B0_ISR_ERR_USRCTL_EVT4 BIT(4)
2022#define B_AX_B0_ISR_ERR_USRCTL_RLSBMPLEN BIT(3)
2023#define B_AX_B0_ISR_ERR_USRCTL_RDNRLSCMD BIT(2)
2024#define B_AX_B0_ISR_ERR_USRCTL_NOINIT BIT(1)
2025#define B_AX_B0_ISR_ERR_USRCTL_REINIT BIT(0)
2026
2027#define R_AX_TXPKTCTL_B1_PRELD_CFG0 0x9F88
2028#define B_AX_B1_PRELD_FEN BIT(31)
2029#define B_AX_B1_PRELD_USEMAXSZ_MASK GENMASK(25, 16)
2030#define PRELD_B1_ENT_NUM 4
2031#define B_AX_B1_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)
2032#define B_AX_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
2033
2034#define R_AX_TXPKTCTL_B1_PRELD_CFG1 0x9F8C
2035#define B_AX_B1_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)
2036#define B_AX_B1_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
2037
2038#define R_AX_TXPKTCTL_B1_ERRFLAG_IMR 0x9FB8
2039#define B_AX_B1_IMR_ERR_PRELD_ENTNUMCFG BIT(21)
2040#define B_AX_B1_IMR_ERR_PRELD_RLSPKTSZERR BIT(20)
2041#define B_AX_B1_IMR_ERR_MPDUIF_DATAERR BIT(18)
2042#define B_AX_B1_IMR_ERR_MPDUINFO_RECFG BIT(16)
2043#define B_AX_B1_IMR_ERR_CMDPSR_TBLSZ BIT(11)
2044#define B_AX_B1_IMR_ERR_CMDPSR_FRZTO BIT(10)
2045#define B_AX_B1_IMR_ERR_CMDPSR_CMDTYPE BIT(9)
2046#define B_AX_B1_IMR_ERR_CMDPSR_1STCMDERR BIT(8)
2047#define B_AX_B1_IMR_ERR_USRCTL_RLSBMPLEN BIT(3)
2048#define B_AX_B1_IMR_ERR_USRCTL_RDNRLSCMD BIT(2)
2049#define B_AX_B1_IMR_ERR_USRCTL_NOINIT BIT(1)
2050#define B_AX_B1_IMR_ERR_USRCTL_REINIT BIT(0)
2051#define B_AX_TXPKTCTL_IMR_B1_CLR_V1 (B_AX_B1_IMR_ERR_USRCTL_REINIT | \
2052				     B_AX_B1_IMR_ERR_USRCTL_NOINIT | \
2053				     B_AX_B1_IMR_ERR_USRCTL_RDNRLSCMD | \
2054				     B_AX_B1_IMR_ERR_USRCTL_RLSBMPLEN | \
2055				     B_AX_B1_IMR_ERR_CMDPSR_1STCMDERR | \
2056				     B_AX_B1_IMR_ERR_CMDPSR_CMDTYPE | \
2057				     B_AX_B1_IMR_ERR_CMDPSR_FRZTO | \
2058				     B_AX_B1_IMR_ERR_CMDPSR_TBLSZ | \
2059				     B_AX_B1_IMR_ERR_MPDUINFO_RECFG | \
2060				     B_AX_B1_IMR_ERR_MPDUIF_DATAERR | \
2061				     B_AX_B1_IMR_ERR_PRELD_RLSPKTSZERR | \
2062				     B_AX_B1_IMR_ERR_PRELD_ENTNUMCFG)
2063#define B_AX_TXPKTCTL_IMR_B1_SET_V1 (B_AX_B1_IMR_ERR_USRCTL_REINIT | \
2064				     B_AX_B1_IMR_ERR_USRCTL_NOINIT | \
2065				     B_AX_B1_IMR_ERR_CMDPSR_1STCMDERR | \
2066				     B_AX_B1_IMR_ERR_CMDPSR_CMDTYPE | \
2067				     B_AX_B1_IMR_ERR_CMDPSR_FRZTO | \
2068				     B_AX_B1_IMR_ERR_CMDPSR_TBLSZ | \
2069				     B_AX_B1_IMR_ERR_MPDUINFO_RECFG | \
2070				     B_AX_B1_IMR_ERR_MPDUIF_DATAERR | \
2071				     B_AX_B1_IMR_ERR_PRELD_RLSPKTSZERR | \
2072				     B_AX_B1_IMR_ERR_PRELD_ENTNUMCFG)
2073
2074#define R_AX_TXPKTCTL_B1_ERRFLAG_ISR 0x9FBC
2075#define B_AX_B1_ISR_ERR_PRELD_EVT3 BIT(23)
2076#define B_AX_B1_ISR_ERR_PRELD_EVT2 BIT(22)
2077#define B_AX_B1_ISR_ERR_PRELD_ENTNUMCFG BIT(21)
2078#define B_AX_B1_ISR_ERR_PRELD_RLSPKTSZERR BIT(20)
2079#define B_AX_B1_ISR_ERR_MPDUIF_ERR1 BIT(19)
2080#define B_AX_B1_ISR_ERR_MPDUIF_DATAERR BIT(18)
2081#define B_AX_B1_ISR_ERR_MPDUINFO_ERR1 BIT(17)
2082#define B_AX_B1_ISR_ERR_MPDUINFO_RECFG BIT(16)
2083#define B_AX_B1_ISR_ERR_CMDPSR_TBLSZ BIT(11)
2084#define B_AX_B1_ISR_ERR_CMDPSR_FRZTO BIT(10)
2085#define B_AX_B1_ISR_ERR_CMDPSR_CMDTYPE BIT(9)
2086#define B_AX_B1_ISR_ERR_CMDPSR_1STCMDERR BIT(8)
2087#define B_AX_B1_ISR_ERR_USRCTL_EVT7 BIT(7)
2088#define B_AX_B1_ISR_ERR_USRCTL_EVT6 BIT(6)
2089#define B_AX_B1_ISR_ERR_USRCTL_EVT5 BIT(5)
2090#define B_AX_B1_ISR_ERR_USRCTL_EVT4 BIT(4)
2091#define B_AX_B1_ISR_ERR_USRCTL_RLSBMPLEN BIT(3)
2092#define B_AX_B1_ISR_ERR_USRCTL_RDNRLSCMD BIT(2)
2093#define B_AX_B1_ISR_ERR_USRCTL_NOINIT BIT(1)
2094#define B_AX_B1_ISR_ERR_USRCTL_REINIT BIT(0)
2095
2096#define R_AX_AFE_CTRL1 0x0024
2097
2098#define B_AX_R_SYM_WLCMAC1_P4_PC_EN BIT(4)
2099#define B_AX_R_SYM_WLCMAC1_P3_PC_EN BIT(3)
2100#define B_AX_R_SYM_WLCMAC1_P2_PC_EN BIT(2)
2101#define B_AX_R_SYM_WLCMAC1_P1_PC_EN BIT(1)
2102#define B_AX_R_SYM_WLCMAC1_PC_EN BIT(0)
2103
2104#define R_AX_SYS_ISO_CTRL_EXTEND 0x0080
2105#define B_AX_CMAC1_FEN BIT(30)
2106#define B_AX_R_SYM_FEN_WLBBGLB_1 BIT(17)
2107#define B_AX_R_SYM_FEN_WLBBFUN_1 BIT(16)
2108#define B_AX_R_SYM_ISO_CMAC12PP BIT(5)
2109
2110#define R_AX_CMAC_REG_START 0xC000
2111
2112#define R_AX_CMAC_FUNC_EN 0xC000
2113#define R_AX_CMAC_FUNC_EN_C1 0xE000
2114#define B_AX_CMAC_CRPRT BIT(31)
2115#define B_AX_CMAC_EN BIT(30)
2116#define B_AX_CMAC_TXEN BIT(29)
2117#define B_AX_CMAC_RXEN BIT(28)
2118#define B_AX_FORCE_CMACREG_GCKEN BIT(15)
2119#define B_AX_PHYINTF_EN BIT(5)
2120#define B_AX_CMAC_DMA_EN BIT(4)
2121#define B_AX_PTCLTOP_EN BIT(3)
2122#define B_AX_SCHEDULER_EN BIT(2)
2123#define B_AX_TMAC_EN BIT(1)
2124#define B_AX_RMAC_EN BIT(0)
2125
2126#define R_AX_CK_EN 0xC004
2127#define R_AX_CK_EN_C1 0xE004
2128#define B_AX_CMAC_ALLCKEN GENMASK(31, 0)
2129#define B_AX_CMAC_CKEN BIT(30)
2130#define B_AX_PHYINTF_CKEN BIT(5)
2131#define B_AX_CMAC_DMA_CKEN BIT(4)
2132#define B_AX_PTCLTOP_CKEN BIT(3)
2133#define B_AX_SCHEDULER_CKEN BIT(2)
2134#define B_AX_TMAC_CKEN BIT(1)
2135#define B_AX_RMAC_CKEN BIT(0)
2136
2137#define R_AX_WMAC_RFMOD 0xC010
2138#define R_AX_WMAC_RFMOD_C1 0xE010
2139#define B_AX_WMAC_RFMOD_MASK GENMASK(1, 0)
2140#define AX_WMAC_RFMOD_20M 0
2141#define AX_WMAC_RFMOD_40M 1
2142#define AX_WMAC_RFMOD_80M 2
2143#define AX_WMAC_RFMOD_160M 3
2144
2145#define R_AX_GID_POSITION0 0xC070
2146#define R_AX_GID_POSITION0_C1 0xE070
2147#define R_AX_GID_POSITION1 0xC074
2148#define R_AX_GID_POSITION1_C1 0xE074
2149#define R_AX_GID_POSITION2 0xC078
2150#define R_AX_GID_POSITION2_C1 0xE078
2151#define R_AX_GID_POSITION3 0xC07C
2152#define R_AX_GID_POSITION3_C1 0xE07C
2153#define R_AX_GID_POSITION_EN0 0xC080
2154#define R_AX_GID_POSITION_EN0_C1 0xE080
2155#define R_AX_GID_POSITION_EN1 0xC084
2156#define R_AX_GID_POSITION_EN1_C1 0xE084
2157
2158#define R_AX_TX_SUB_CARRIER_VALUE 0xC088
2159#define R_AX_TX_SUB_CARRIER_VALUE_C1 0xE088
2160#define B_AX_TXSC_80M_MASK GENMASK(11, 8)
2161#define B_AX_TXSC_40M_MASK GENMASK(7, 4)
2162#define B_AX_TXSC_20M_MASK GENMASK(3, 0)
2163
2164#define R_AX_PTCL_RRSR1 0xC090
2165#define R_AX_PTCL_RRSR1_C1 0xE090
2166#define B_AX_RRSR_RATE_EN_MASK GENMASK(11, 8)
2167#define RRSR_OFDM_CCK_EN 3
2168#define B_AX_RSC_MASK GENMASK(7, 6)
2169#define B_AX_RRSR_CCK_MASK GENMASK(3, 0)
2170
2171#define R_AX_CMAC_ERR_IMR 0xC160
2172#define R_AX_CMAC_ERR_IMR_C1 0xE160
2173#define B_AX_WMAC_TX_ERR_IND_EN BIT(7)
2174#define B_AX_WMAC_RX_ERR_IND_EN BIT(6)
2175#define B_AX_TXPWR_CTRL_ERR_IND_EN BIT(5)
2176#define B_AX_PHYINTF_ERR_IND_EN BIT(4)
2177#define B_AX_DMA_TOP_ERR_IND_EN BIT(3)
2178#define B_AX_PTCL_TOP_ERR_IND_EN BIT(1)
2179#define B_AX_SCHEDULE_TOP_ERR_IND_EN BIT(0)
2180#define CMAC0_ERR_IMR_EN GENMASK(31, 0)
2181#define CMAC1_ERR_IMR_EN GENMASK(31, 0)
2182#define CMAC0_ERR_IMR_DIS 0
2183#define CMAC1_ERR_IMR_DIS 0
2184
2185#define R_AX_CMAC_ERR_ISR 0xC164
2186#define R_AX_CMAC_ERR_ISR_C1 0xE164
2187#define B_AX_WMAC_TX_ERR_IND BIT(7)
2188#define B_AX_WMAC_RX_ERR_IND BIT(6)
2189#define B_AX_TXPWR_CTRL_ERR_IND BIT(5)
2190#define B_AX_PHYINTF_ERR_IND BIT(4)
2191#define B_AX_DMA_TOP_ERR_IND BIT(3)
2192#define B_AX_PTCL_TOP_ERR_IND BIT(1)
2193#define B_AX_SCHEDULE_TOP_ERR_IND BIT(0)
2194
2195#define R_AX_PORT0_TSF_SYNC 0xC2A0
2196#define R_AX_PORT0_TSF_SYNC_C1 0xE2A0
2197#define R_AX_PORT1_TSF_SYNC 0xC2A4
2198#define R_AX_PORT1_TSF_SYNC_C1 0xE2A4
2199#define R_AX_PORT2_TSF_SYNC 0xC2A8
2200#define R_AX_PORT2_TSF_SYNC_C1 0xE2A8
2201#define R_AX_PORT3_TSF_SYNC 0xC2AC
2202#define R_AX_PORT3_TSF_SYNC_C1 0xE2AC
2203#define R_AX_PORT4_TSF_SYNC 0xC2B0
2204#define R_AX_PORT4_TSF_SYNC_C1 0xE2B0
2205#define B_AX_SYNC_NOW BIT(30)
2206#define B_AX_SYNC_ONCE BIT(29)
2207#define B_AX_SYNC_AUTO BIT(28)
2208#define B_AX_SYNC_PORT_SRC GENMASK(26, 24)
2209#define B_AX_SYNC_PORT_OFFSET_SIGN BIT(18)
2210#define B_AX_SYNC_PORT_OFFSET_VAL GENMASK(17, 0)
2211
2212#define R_AX_MACID_SLEEP_0 0xC2C0
2213#define R_AX_MACID_SLEEP_0_C1 0xE2C0
2214#define B_AX_MACID31_0_SLEEP_SH 0
2215#define B_AX_MACID31_0_SLEEP_MASK GENMASK(31, 0)
2216
2217#define R_AX_MACID_SLEEP_1 0xC2C4
2218#define R_AX_MACID_SLEEP_1_C1 0xE2C4
2219#define B_AX_MACID63_32_SLEEP_SH 0
2220#define B_AX_MACID63_32_SLEEP_MASK GENMASK(31, 0)
2221
2222#define R_AX_MACID_SLEEP_2 0xC2C8
2223#define R_AX_MACID_SLEEP_2_C1 0xE2C8
2224#define B_AX_MACID95_64_SLEEP_SH 0
2225#define B_AX_MACID95_64_SLEEP_MASK GENMASK(31, 0)
2226
2227#define R_AX_MACID_SLEEP_3 0xC2CC
2228#define R_AX_MACID_SLEEP_3_C1 0xE2CC
2229#define B_AX_MACID127_96_SLEEP_SH 0
2230#define B_AX_MACID127_96_SLEEP_MASK GENMASK(31, 0)
2231
2232#define SCH_PREBKF_24US 0x18
2233#define R_AX_PREBKF_CFG_0 0xC338
2234#define R_AX_PREBKF_CFG_0_C1 0xE338
2235#define B_AX_PREBKF_TIME_MASK GENMASK(4, 0)
2236
2237#define R_AX_PREBKF_CFG_1 0xC33C
2238#define R_AX_PREBKF_CFG_1_C1 0xE33C
2239#define B_AX_SIFS_TIMEOUT_TB_AGGR_MASK GENMASK(30, 24)
2240#define B_AX_SIFS_PREBKF_MASK GENMASK(23, 16)
2241#define B_AX_SIFS_TIMEOUT_T2_MASK GENMASK(14, 8)
2242#define B_AX_SIFS_MACTXEN_T1_MASK GENMASK(6, 0)
2243#define SIFS_MACTXEN_T1 0x47
2244#define SIFS_MACTXEN_T1_V1 0x41
2245
2246#define R_AX_CCA_CFG_0 0xC340
2247#define R_AX_CCA_CFG_0_C1 0xE340
2248#define B_AX_BTCCA_BRK_TXOP_EN BIT(9)
2249#define B_AX_BTCCA_EN BIT(5)
2250#define B_AX_EDCCA_EN BIT(4)
2251#define B_AX_SEC80_EN BIT(3)
2252#define B_AX_SEC40_EN BIT(2)
2253#define B_AX_SEC20_EN BIT(1)
2254#define B_AX_CCA_EN BIT(0)
2255
2256#define R_AX_CTN_TXEN 0xC348
2257#define R_AX_CTN_TXEN_C1 0xE348
2258#define B_AX_CTN_TXEN_TWT_1 BIT(15)
2259#define B_AX_CTN_TXEN_TWT_0 BIT(14)
2260#define B_AX_CTN_TXEN_ULQ BIT(13)
2261#define B_AX_CTN_TXEN_BCNQ BIT(12)
2262#define B_AX_CTN_TXEN_HGQ BIT(11)
2263#define B_AX_CTN_TXEN_CPUMGQ BIT(10)
2264#define B_AX_CTN_TXEN_MGQ1 BIT(9)
2265#define B_AX_CTN_TXEN_MGQ BIT(8)
2266#define B_AX_CTN_TXEN_VO_1 BIT(7)
2267#define B_AX_CTN_TXEN_VI_1 BIT(6)
2268#define B_AX_CTN_TXEN_BK_1 BIT(5)
2269#define B_AX_CTN_TXEN_BE_1 BIT(4)
2270#define B_AX_CTN_TXEN_VO_0 BIT(3)
2271#define B_AX_CTN_TXEN_VI_0 BIT(2)
2272#define B_AX_CTN_TXEN_BK_0 BIT(1)
2273#define B_AX_CTN_TXEN_BE_0 BIT(0)
2274#define B_AX_CTN_TXEN_ALL_MASK GENMASK(15, 0)
2275
2276#define R_AX_MUEDCA_BE_PARAM_0 0xC350
2277#define R_AX_MUEDCA_BE_PARAM_0_C1 0xE350
2278#define B_AX_MUEDCA_BE_PARAM_0_TIMER_MASK GENMASK(31, 16)
2279#define B_AX_MUEDCA_BE_PARAM_0_CW_MASK GENMASK(15, 8)
2280#define B_AX_MUEDCA_BE_PARAM_0_AIFS_MASK GENMASK(7, 0)
2281
2282#define R_AX_MUEDCA_BK_PARAM_0 0xC354
2283#define R_AX_MUEDCA_BK_PARAM_0_C1 0xE354
2284#define R_AX_MUEDCA_VI_PARAM_0 0xC358
2285#define R_AX_MUEDCA_VI_PARAM_0_C1 0xE358
2286#define R_AX_MUEDCA_VO_PARAM_0 0xC35C
2287#define R_AX_MUEDCA_VO_PARAM_0_C1 0xE35C
2288
2289#define R_AX_MUEDCA_EN 0xC370
2290#define R_AX_MUEDCA_EN_C1 0xE370
2291#define B_AX_MUEDCA_WMM_SEL BIT(8)
2292#define B_AX_SET_MUEDCATIMER_TF_0 BIT(4)
2293#define B_AX_MUEDCA_EN_0 BIT(0)
2294
2295#define R_AX_CCA_CONTROL 0xC390
2296#define R_AX_CCA_CONTROL_C1 0xE390
2297#define B_AX_TB_CHK_TX_NAV BIT(31)
2298#define B_AX_TB_CHK_BASIC_NAV BIT(30)
2299#define B_AX_TB_CHK_BTCCA BIT(29)
2300#define B_AX_TB_CHK_EDCCA BIT(28)
2301#define B_AX_TB_CHK_CCA_S80 BIT(27)
2302#define B_AX_TB_CHK_CCA_S40 BIT(26)
2303#define B_AX_TB_CHK_CCA_S20 BIT(25)
2304#define B_AX_TB_CHK_CCA_P20 BIT(24)
2305#define B_AX_SIFS_CHK_BTCCA BIT(21)
2306#define B_AX_SIFS_CHK_EDCCA BIT(20)
2307#define B_AX_SIFS_CHK_CCA_S80 BIT(19)
2308#define B_AX_SIFS_CHK_CCA_S40 BIT(18)
2309#define B_AX_SIFS_CHK_CCA_S20 BIT(17)
2310#define B_AX_SIFS_CHK_CCA_P20 BIT(16)
2311#define B_AX_CTN_CHK_TXNAV BIT(8)
2312#define B_AX_CTN_CHK_INTRA_NAV BIT(7)
2313#define B_AX_CTN_CHK_BASIC_NAV BIT(6)
2314#define B_AX_CTN_CHK_BTCCA BIT(5)
2315#define B_AX_CTN_CHK_EDCCA BIT(4)
2316#define B_AX_CTN_CHK_CCA_S80 BIT(3)
2317#define B_AX_CTN_CHK_CCA_S40 BIT(2)
2318#define B_AX_CTN_CHK_CCA_S20 BIT(1)
2319#define B_AX_CTN_CHK_CCA_P20 BIT(0)
2320
2321#define R_AX_CTN_DRV_TXEN 0xC398
2322#define R_AX_CTN_DRV_TXEN_C1 0xE398
2323#define B_AX_CTN_TXEN_TWT_3 BIT(17)
2324#define B_AX_CTN_TXEN_TWT_2 BIT(16)
2325#define B_AX_CTN_TXEN_ALL_MASK_V1 GENMASK(17, 0)
2326
2327#define R_AX_SCHEDULE_ERR_IMR 0xC3E8
2328#define R_AX_SCHEDULE_ERR_IMR_C1 0xE3E8
2329#define B_AX_SORT_NON_IDLE_ERR_INT_EN BIT(1)
2330
2331#define R_AX_SCHEDULE_ERR_ISR 0xC3EC
2332#define R_AX_SCHEDULE_ERR_ISR_C1 0xE3EC
2333
2334#define R_AX_SCH_DBG_SEL 0xC3F4
2335#define R_AX_SCH_DBG_SEL_C1 0xE3F4
2336#define B_AX_SCH_DBG_EN BIT(16)
2337#define B_AX_SCH_CFG_CMD_SEL GENMASK(15, 8)
2338#define B_AX_SCH_DBG_SEL_MASK GENMASK(7, 0)
2339
2340#define R_AX_SCH_DBG 0xC3F8
2341#define R_AX_SCH_DBG_C1 0xE3F8
2342#define B_AX_SCHEDULER_DBG_MASK GENMASK(31, 0)
2343
2344#define R_AX_SCH_EXT_CTRL 0xC3FC
2345#define R_AX_SCH_EXT_CTRL_C1 0xE3FC
2346#define B_AX_PORT_RST_TSF_ADV BIT(1)
2347
2348#define R_AX_PORT_CFG_P0 0xC400
2349#define R_AX_PORT_CFG_P1 0xC440
2350#define R_AX_PORT_CFG_P2 0xC480
2351#define R_AX_PORT_CFG_P3 0xC4C0
2352#define R_AX_PORT_CFG_P4 0xC500
2353#define B_AX_BRK_SETUP BIT(16)
2354#define B_AX_TBTT_UPD_SHIFT_SEL BIT(15)
2355#define B_AX_BCN_DROP_ALLOW BIT(14)
2356#define B_AX_TBTT_PROHIB_EN BIT(13)
2357#define B_AX_BCNTX_EN BIT(12)
2358#define B_AX_NET_TYPE_MASK GENMASK(11, 10)
2359#define B_AX_BCN_FORCETX_EN BIT(9)
2360#define B_AX_TXBCN_BTCCA_EN BIT(8)
2361#define B_AX_BCNERR_CNT_EN BIT(7)
2362#define B_AX_BCN_AGRES BIT(6)
2363#define B_AX_TSFTR_RST BIT(5)
2364#define B_AX_RX_BSSID_FIT_EN BIT(4)
2365#define B_AX_TSF_UDT_EN BIT(3)
2366#define B_AX_PORT_FUNC_EN BIT(2)
2367#define B_AX_TXBCN_RPT_EN BIT(1)
2368#define B_AX_RXBCN_RPT_EN BIT(0)
2369
2370#define R_AX_TBTT_PROHIB_P0 0xC404
2371#define R_AX_TBTT_PROHIB_P1 0xC444
2372#define R_AX_TBTT_PROHIB_P2 0xC484
2373#define R_AX_TBTT_PROHIB_P3 0xC4C4
2374#define R_AX_TBTT_PROHIB_P4 0xC504
2375#define B_AX_TBTT_HOLD_MASK GENMASK(27, 16)
2376#define B_AX_TBTT_SETUP_MASK GENMASK(7, 0)
2377
2378#define R_AX_BCN_AREA_P0 0xC408
2379#define R_AX_BCN_AREA_P1 0xC448
2380#define R_AX_BCN_AREA_P2 0xC488
2381#define R_AX_BCN_AREA_P3 0xC4C8
2382#define R_AX_BCN_AREA_P4 0xC508
2383#define B_AX_BCN_MSK_AREA_MASK GENMASK(27, 16)
2384#define B_AX_BCN_CTN_AREA_MASK GENMASK(11, 0)
2385
2386#define R_AX_BCNERLYINT_CFG_P0 0xC40C
2387#define R_AX_BCNERLYINT_CFG_P1 0xC44C
2388#define R_AX_BCNERLYINT_CFG_P2 0xC48C
2389#define R_AX_BCNERLYINT_CFG_P3 0xC4CC
2390#define R_AX_BCNERLYINT_CFG_P4 0xC50C
2391#define B_AX_BCNERLY_MASK GENMASK(11, 0)
2392
2393#define R_AX_TBTTERLYINT_CFG_P0 0xC40E
2394#define R_AX_TBTTERLYINT_CFG_P1 0xC44E
2395#define R_AX_TBTTERLYINT_CFG_P2 0xC48E
2396#define R_AX_TBTTERLYINT_CFG_P3 0xC4CE
2397#define R_AX_TBTTERLYINT_CFG_P4 0xC50E
2398#define B_AX_TBTTERLY_MASK GENMASK(11, 0)
2399
2400#define R_AX_TBTT_AGG_P0 0xC412
2401#define R_AX_TBTT_AGG_P1 0xC452
2402#define R_AX_TBTT_AGG_P2 0xC492
2403#define R_AX_TBTT_AGG_P3 0xC4D2
2404#define R_AX_TBTT_AGG_P4 0xC512
2405#define B_AX_TBTT_AGG_NUM_MASK GENMASK(15, 8)
2406
2407#define R_AX_BCN_SPACE_CFG_P0 0xC414
2408#define R_AX_BCN_SPACE_CFG_P1 0xC454
2409#define R_AX_BCN_SPACE_CFG_P2 0xC494
2410#define R_AX_BCN_SPACE_CFG_P3 0xC4D4
2411#define R_AX_BCN_SPACE_CFG_P4 0xC514
2412#define B_AX_SUB_BCN_SPACE_MASK GENMASK(23, 16)
2413#define B_AX_BCN_SPACE_MASK GENMASK(15, 0)
2414
2415#define R_AX_BCN_FORCETX_P0 0xC418
2416#define R_AX_BCN_FORCETX_P1 0xC458
2417#define R_AX_BCN_FORCETX_P2 0xC498
2418#define R_AX_BCN_FORCETX_P3 0xC4D8
2419#define R_AX_BCN_FORCETX_P4 0xC518
2420#define B_AX_FORCE_BCN_CURRCNT_MASK GENMASK(23, 16)
2421#define B_AX_FORCE_BCN_NUM_MASK GENMASK(15, 0)
2422#define B_AX_BCN_MAX_ERR_MASK GENMASK(7, 0)
2423
2424#define R_AX_BCN_ERR_CNT_P0 0xC420
2425#define R_AX_BCN_ERR_CNT_P1 0xC460
2426#define R_AX_BCN_ERR_CNT_P2 0xC4A0
2427#define R_AX_BCN_ERR_CNT_P3 0xC4E0
2428#define R_AX_BCN_ERR_CNT_P4 0xC520
2429#define B_AX_BCN_ERR_CNT_SUM_MASK GENMASK(31, 24)
2430#define B_AX_BCN_ERR_CNT_NAV_MASK GENMASK(23, 16)
2431#define B_AX_BCN_ERR_CNT_EDCCA_MASK GENMASK(15, 0)
2432#define B_AX_BCN_ERR_CNT_CCA_MASK GENMASK(7, 0)
2433
2434#define R_AX_BCN_ERR_FLAG_P0 0xC424
2435#define R_AX_BCN_ERR_FLAG_P1 0xC464
2436#define R_AX_BCN_ERR_FLAG_P2 0xC4A4
2437#define R_AX_BCN_ERR_FLAG_P3 0xC4E4
2438#define R_AX_BCN_ERR_FLAG_P4 0xC524
2439#define B_AX_BCN_ERR_FLAG_OTHERS BIT(6)
2440#define B_AX_BCN_ERR_FLAG_MAC BIT(5)
2441#define B_AX_BCN_ERR_FLAG_TXON BIT(4)
2442#define B_AX_BCN_ERR_FLAG_SRCHEND BIT(3)
2443#define B_AX_BCN_ERR_FLAG_INVALID BIT(2)
2444#define B_AX_BCN_ERR_FLAG_CMP BIT(1)
2445#define B_AX_BCN_ERR_FLAG_LOCK BIT(0)
2446
2447#define R_AX_DTIM_CTRL_P0 0xC426
2448#define R_AX_DTIM_CTRL_P1 0xC466
2449#define R_AX_DTIM_CTRL_P2 0xC4A6
2450#define R_AX_DTIM_CTRL_P3 0xC4E6
2451#define R_AX_DTIM_CTRL_P4 0xC526
2452#define B_AX_DTIM_NUM_MASK GENMASK(15, 8)
2453#define B_AX_DTIM_CURRCNT_MASK GENMASK(7, 0)
2454
2455#define R_AX_TBTT_SHIFT_P0 0xC428
2456#define R_AX_TBTT_SHIFT_P1 0xC468
2457#define R_AX_TBTT_SHIFT_P2 0xC4A8
2458#define R_AX_TBTT_SHIFT_P3 0xC4E8
2459#define R_AX_TBTT_SHIFT_P4 0xC528
2460#define B_AX_TBTT_SHIFT_OFST_MASK GENMASK(11, 0)
2461#define B_AX_TBTT_SHIFT_OFST_SIGN BIT(11)
2462#define B_AX_TBTT_SHIFT_OFST_MAG GENMASK(10, 0)
2463
2464#define R_AX_BCN_CNT_TMR_P0 0xC434
2465#define R_AX_BCN_CNT_TMR_P1 0xC474
2466#define R_AX_BCN_CNT_TMR_P2 0xC4B4
2467#define R_AX_BCN_CNT_TMR_P3 0xC4F4
2468#define R_AX_BCN_CNT_TMR_P4 0xC534
2469#define B_AX_BCN_CNT_TMR_MASK GENMASK(31, 0)
2470
2471#define R_AX_TSFTR_LOW_P0 0xC438
2472#define R_AX_TSFTR_LOW_P1 0xC478
2473#define R_AX_TSFTR_LOW_P2 0xC4B8
2474#define R_AX_TSFTR_LOW_P3 0xC4F8
2475#define R_AX_TSFTR_LOW_P4 0xC538
2476#define B_AX_TSFTR_LOW_MASK GENMASK(31, 0)
2477
2478#define R_AX_TSFTR_HIGH_P0 0xC43C
2479#define R_AX_TSFTR_HIGH_P1 0xC47C
2480#define R_AX_TSFTR_HIGH_P2 0xC4BC
2481#define R_AX_TSFTR_HIGH_P3 0xC4FC
2482#define R_AX_TSFTR_HIGH_P4 0xC53C
2483#define B_AX_TSFTR_HIGH_MASK GENMASK(31, 0)
2484
2485#define R_AX_BCN_DROP_ALL0 0xC560
2486#define R_AX_BCN_DROP_ALL0_C1 0xE560
2487#define B_AX_BCN_DROP_ALL_P4 BIT(4)
2488#define B_AX_BCN_DROP_ALL_P3 BIT(3)
2489#define B_AX_BCN_DROP_ALL_P2 BIT(2)
2490#define B_AX_BCN_DROP_ALL_P1 BIT(1)
2491#define B_AX_BCN_DROP_ALL_P0 BIT(0)
2492
2493#define R_AX_MBSSID_CTRL 0xC568
2494#define R_AX_MBSSID_CTRL_C1 0xE568
2495#define B_AX_P0MB_ALL_MASK GENMASK(23, 1)
2496#define B_AX_P0MB_NUM_MASK GENMASK(19, 16)
2497#define B_AX_P0MB15_EN BIT(15)
2498#define B_AX_P0MB14_EN BIT(14)
2499#define B_AX_P0MB13_EN BIT(13)
2500#define B_AX_P0MB12_EN BIT(12)
2501#define B_AX_P0MB11_EN BIT(11)
2502#define B_AX_P0MB10_EN BIT(10)
2503#define B_AX_P0MB9_EN BIT(9)
2504#define B_AX_P0MB8_EN BIT(8)
2505#define B_AX_P0MB7_EN BIT(7)
2506#define B_AX_P0MB6_EN BIT(6)
2507#define B_AX_P0MB5_EN BIT(5)
2508#define B_AX_P0MB4_EN BIT(4)
2509#define B_AX_P0MB3_EN BIT(3)
2510#define B_AX_P0MB2_EN BIT(2)
2511#define B_AX_P0MB1_EN BIT(1)
2512
2513#define R_AX_P0MB_HGQ_WINDOW_CFG_0 0xC590
2514#define R_AX_P0MB_HGQ_WINDOW_CFG_0_C1 0xE590
2515#define R_AX_PORT_HGQ_WINDOW_CFG 0xC5A0
2516#define R_AX_PORT_HGQ_WINDOW_CFG_C1 0xE5A0
2517
2518#define R_AX_PTCL_COMMON_SETTING_0 0xC600
2519#define R_AX_PTCL_COMMON_SETTING_0_C1 0xE600
2520#define B_AX_PCIE_MODE_MASK GENMASK(15, 14)
2521#define B_AX_CPUMGQ_LIFETIME_EN BIT(8)
2522#define B_AX_MGQ_LIFETIME_EN BIT(7)
2523#define B_AX_LIFETIME_EN BIT(6)
2524#define B_AX_PTCL_TRIGGER_SS_EN_UL BIT(4)
2525#define B_AX_PTCL_TRIGGER_SS_EN_1 BIT(3)
2526#define B_AX_PTCL_TRIGGER_SS_EN_0 BIT(2)
2527#define B_AX_CMAC_TX_MODE_1 BIT(1)
2528#define B_AX_CMAC_TX_MODE_0 BIT(0)
2529
2530#define R_AX_AMPDU_AGG_LIMIT 0xC610
2531#define B_AX_AMPDU_MAX_TIME_MASK GENMASK(31, 24)
2532#define B_AX_RA_TRY_RATE_AGG_LMT_MASK GENMASK(23, 16)
2533#define B_AX_RTS_MAX_AGG_NUM_MASK GENMASK(15, 8)
2534#define B_AX_MAX_AGG_NUM_MASK GENMASK(7, 0)
2535
2536#define R_AX_AGG_LEN_HT_0 0xC614
2537#define R_AX_AGG_LEN_HT_0_C1 0xE614
2538#define B_AX_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16)
2539#define B_AX_RTS_TXTIME_TH_MASK GENMASK(15, 8)
2540#define B_AX_RTS_LEN_TH_MASK GENMASK(7, 0)
2541
2542#define R_AX_AGG_LEN_VHT_0 0xC618
2543#define R_AX_AGG_LEN_VHT_0_C1 0xE618
2544#define B_AX_AMPDU_MAX_LEN_VHT_MASK GENMASK(19, 0)
2545
2546#define S_AX_CTS2S_TH_SEC_256B 1
2547#define R_AX_SIFS_SETTING 0xC624
2548#define R_AX_SIFS_SETTING_C1 0xE624
2549#define B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24)
2550#define B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK GENMASK(23, 18)
2551#define B_AX_HW_CTS2SELF_EN BIT(16)
2552#define B_AX_SPEC_SIFS_OFDM_PTCL_SH 8
2553#define B_AX_SPEC_SIFS_OFDM_PTCL_MASK GENMASK(15, 8)
2554#define B_AX_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0)
2555#define S_AX_CTS2S_TH_1K 4
2556
2557#define R_AX_TXRATE_CHK 0xC628
2558#define R_AX_TXRATE_CHK_C1 0xE628
2559#define B_AX_DEFT_RATE_MASK GENMASK(15, 7)
2560#define B_AX_BAND_MODE BIT(4)
2561#define B_AX_MAX_TXNSS_MASK GENMASK(3, 2)
2562#define B_AX_RTS_LIMIT_IN_OFDM6 BIT(1)
2563#define B_AX_CHECK_CCK_EN BIT(0)
2564
2565#define R_AX_TXCNT 0xC62C
2566#define R_AX_TXCNT_C1 0xE62C
2567#define B_AX_ADD_TXCNT_BY BIT(31)
2568#define B_AX_S_TXCNT_LMT_MASK GENMASK(29, 24)
2569#define B_AX_L_TXCNT_LMT_MASK GENMASK(21, 16)
2570
2571#define R_AX_MBSSID_DROP_0 0xC63C
2572#define R_AX_MBSSID_DROP_0_C1 0xE63C
2573#define B_AX_GI_LTF_FB_SEL BIT(30)
2574#define B_AX_RATE_SEL_MASK GENMASK(29, 24)
2575#define B_AX_PORT_DROP_4_0_MASK GENMASK(20, 16)
2576#define B_AX_MBSSID_DROP_15_0_MASK GENMASK(15, 0)
2577
2578#define R_AX_PTCLRPT_FULL_HDL 0xC660
2579#define R_AX_PTCLRPT_FULL_HDL_C1 0xE660
2580#define B_AX_RPT_LATCH_PHY_TIME_MASK GENMASK(15, 12)
2581#define B_AX_F2PCMD_FWWD_RLS_MODE BIT(9)
2582#define B_AX_F2PCMD_RPT_EN BIT(8)
2583#define B_AX_BCN_RPT_PATH_MASK GENMASK(7, 6)
2584#define B_AX_SPE_RPT_PATH_MASK GENMASK(5, 4)
2585#define FWD_TO_WLCPU 1
2586#define B_AX_TX_RPT_PATH_MASK GENMASK(3, 2)
2587#define B_AX_F2PCMDRPT_FULL_DROP BIT(1)
2588#define B_AX_NON_F2PCMDRPT_FULL_DROP BIT(0)
2589
2590#define R_AX_BT_PLT 0xC67C
2591#define R_AX_BT_PLT_C1 0xE67C
2592#define B_AX_BT_PLT_PKT_CNT_MASK GENMASK(31, 16)
2593#define B_AX_BT_PLT_RST BIT(9)
2594#define B_AX_PLT_EN BIT(8)
2595#define B_AX_RX_PLT_GNT_LTE_RX BIT(7)
2596#define B_AX_RX_PLT_GNT_BT_RX BIT(6)
2597#define B_AX_RX_PLT_GNT_BT_TX BIT(5)
2598#define B_AX_RX_PLT_GNT_WL BIT(4)
2599#define B_AX_TX_PLT_GNT_LTE_RX BIT(3)
2600#define B_AX_TX_PLT_GNT_BT_RX BIT(2)
2601#define B_AX_TX_PLT_GNT_BT_TX BIT(1)
2602#define B_AX_TX_PLT_GNT_WL BIT(0)
2603
2604#define R_AX_PTCL_BSS_COLOR_0 0xC6A0
2605#define R_AX_PTCL_BSS_COLOR_0_C1 0xE6A0
2606#define B_AX_BSS_COLOB_AX_PORT_3_MASK GENMASK(29, 24)
2607#define B_AX_BSS_COLOB_AX_PORT_2_MASK GENMASK(21, 16)
2608#define B_AX_BSS_COLOB_AX_PORT_1_MASK GENMASK(13, 8)
2609#define B_AX_BSS_COLOB_AX_PORT_0_MASK GENMASK(5, 0)
2610
2611#define R_AX_PTCL_BSS_COLOR_1 0xC6A4
2612#define R_AX_PTCL_BSS_COLOR_1_C1 0xE6A4
2613#define B_AX_BSS_COLOB_AX_PORT_4_MASK GENMASK(5, 0)
2614
2615#define R_AX_PTCL_IMR0 0xC6C0
2616#define R_AX_PTCL_IMR0_C1 0xE6C0
2617#define B_AX_F2PCMD_PKTID_ERR_INT_EN BIT(31)
2618#define B_AX_F2PCMD_RD_PKTID_ERR_INT_EN BIT(30)
2619#define B_AX_F2PCMD_ASSIGN_PKTID_ERR_INT_EN BIT(29)
2620#define B_AX_F2PCMD_USER_ALLC_ERR_INT_EN BIT(28)
2621#define B_AX_RX_SPF_U0_PKTID_ERR_INT_EN BIT(27)
2622#define B_AX_TX_SPF_U1_PKTID_ERR_INT_EN BIT(26)
2623#define B_AX_TX_SPF_U2_PKTID_ERR_INT_EN BIT(25)
2624#define B_AX_TX_SPF_U3_PKTID_ERR_INT_EN BIT(24)
2625#define B_AX_TX_RECORD_PKTID_ERR_INT_EN BIT(23)
2626#define B_AX_F2PCMD_EMPTY_ERR_INT_EN BIT(15)
2627#define B_AX_TWTSP_QSEL_ERR_INT_EN BIT(14)
2628#define B_AX_BCNQ_ORDER_ERR_INT_EN BIT(12)
2629#define B_AX_Q_PKTID_ERR_INT_EN BIT(11)
2630#define B_AX_D_PKTID_ERR_INT_EN BIT(10)
2631#define B_AX_TXPRT_FULL_DROP_ERR_INT_EN BIT(9)
2632#define B_AX_F2PCMDRPT_FULL_DROP_ERR_INT_EN BIT(8)
2633#define B_AX_FSM1_TIMEOUT_ERR_INT_EN BIT(1)
2634#define B_AX_FSM_TIMEOUT_ERR_INT_EN BIT(0)
2635#define B_AX_PTCL_IMR_CLR_ALL GENMASK(31, 0)
2636#define B_AX_PTCL_IMR_CLR (B_AX_FSM_TIMEOUT_ERR_INT_EN | \
2637			   B_AX_F2PCMDRPT_FULL_DROP_ERR_INT_EN | \
2638			   B_AX_TXPRT_FULL_DROP_ERR_INT_EN | \
2639			   B_AX_D_PKTID_ERR_INT_EN | \
2640			   B_AX_Q_PKTID_ERR_INT_EN | \
2641			   B_AX_BCNQ_ORDER_ERR_INT_EN | \
2642			   B_AX_TWTSP_QSEL_ERR_INT_EN | \
2643			   B_AX_F2PCMD_EMPTY_ERR_INT_EN | \
2644			   B_AX_TX_RECORD_PKTID_ERR_INT_EN | \
2645			   B_AX_TX_SPF_U3_PKTID_ERR_INT_EN | \
2646			   B_AX_TX_SPF_U2_PKTID_ERR_INT_EN | \
2647			   B_AX_TX_SPF_U1_PKTID_ERR_INT_EN | \
2648			   B_AX_RX_SPF_U0_PKTID_ERR_INT_EN | \
2649			   B_AX_F2PCMD_USER_ALLC_ERR_INT_EN | \
2650			   B_AX_F2PCMD_ASSIGN_PKTID_ERR_INT_EN | \
2651			   B_AX_F2PCMD_RD_PKTID_ERR_INT_EN | \
2652			   B_AX_F2PCMD_PKTID_ERR_INT_EN)
2653#define B_AX_PTCL_IMR_SET (B_AX_FSM_TIMEOUT_ERR_INT_EN | \
2654			   B_AX_TX_RECORD_PKTID_ERR_INT_EN | \
2655			   B_AX_F2PCMD_USER_ALLC_ERR_INT_EN)
2656#define B_AX_PTCL_IMR_CLR_V1 (B_AX_FSM1_TIMEOUT_ERR_INT_EN | \
2657			      B_AX_FSM_TIMEOUT_ERR_INT_EN)
2658#define B_AX_PTCL_IMR_SET_V1 (B_AX_FSM1_TIMEOUT_ERR_INT_EN | \
2659			      B_AX_FSM_TIMEOUT_ERR_INT_EN)
2660
2661#define R_AX_PTCL_ISR0 0xC6C4
2662#define R_AX_PTCL_ISR0_C1 0xE6C4
2663
2664#define S_AX_PTCL_TO_2MS 0x3F
2665#define R_AX_PTCL_FSM_MON 0xC6E8
2666#define R_AX_PTCL_FSM_MON_C1 0xE6E8
2667#define B_AX_PTCL_TX_ARB_TO_MODE BIT(6)
2668#define B_AX_PTCL_TX_ARB_TO_THR_MASK GENMASK(5, 0)
2669
2670#define R_AX_PTCL_TX_CTN_SEL 0xC6EC
2671#define R_AX_PTCL_TX_CTN_SEL_C1 0xE6EC
2672#define B_AX_PTCL_TX_ON_STAT BIT(7)
2673
2674#define R_AX_PTCL_DBG_INFO 0xC6F0
2675#define R_AX_PTCL_DBG_INFO_C1 0xE6F0
2676#define B_AX_PTCL_DBG_INFO_MASK_BY_PORT(port) \
2677({\
2678	typeof(port) _port = (port); \
2679	GENMASK((_port) * 2 + 1, (_port) * 2); \
2680})
2681
2682#define B_AX_PTCL_DBG_INFO_MASK GENMASK(31, 0)
2683#define R_AX_PTCL_DBG 0xC6F4
2684#define R_AX_PTCL_DBG_C1 0xE6F4
2685#define B_AX_PTCL_DBG_EN BIT(8)
2686#define B_AX_PTCL_DBG_SEL_MASK GENMASK(7, 0)
2687#define AX_PTCL_DBG_BCNQ_NUM0 8
2688#define AX_PTCL_DBG_BCNQ_NUM1 9
2689
2690
2691#define R_AX_DLE_CTRL 0xC800
2692#define R_AX_DLE_CTRL_C1 0xE800
2693#define B_AX_NO_RESERVE_PAGE_ERR_IMR BIT(23)
2694#define B_AX_RXDATA_FSM_HANG_ERROR_IMR BIT(15)
2695#define B_AX_RXSTS_FSM_HANG_ERROR_IMR BIT(14)
2696#define B_AX_DLE_IMR_CLR (B_AX_RXSTS_FSM_HANG_ERROR_IMR | \
2697			  B_AX_RXDATA_FSM_HANG_ERROR_IMR | \
2698			  B_AX_NO_RESERVE_PAGE_ERR_IMR)
2699#define B_AX_DLE_IMR_SET (B_AX_RXSTS_FSM_HANG_ERROR_IMR | \
2700			  B_AX_RXDATA_FSM_HANG_ERROR_IMR)
2701
2702#define R_AX_RX_ERR_FLAG 0xC800
2703#define R_AX_RX_ERR_FLAG_C1 0xE800
2704#define B_AX_RX_GET_NO_PAGE_ERR BIT(31)
2705#define B_AX_RX_GET_NULL_PKT_ERR BIT(30)
2706#define B_AX_RX_RU0_FSM_HANG_ERR BIT(29)
2707#define B_AX_RX_RU1_FSM_HANG_ERR BIT(28)
2708#define B_AX_RX_RU2_FSM_HANG_ERR BIT(27)
2709#define B_AX_RX_RU3_FSM_HANG_ERR BIT(26)
2710#define B_AX_RX_RU4_FSM_HANG_ERR BIT(25)
2711#define B_AX_RX_RU5_FSM_HANG_ERR BIT(24)
2712#define B_AX_RX_RU6_FSM_HANG_ERR BIT(23)
2713#define B_AX_RX_RU7_FSM_HANG_ERR BIT(22)
2714#define B_AX_RX_RXSTS_FSM_HANG_ERR BIT(21)
2715#define B_AX_RX_CSI_FSM_HANG_ERR BIT(20)
2716#define B_AX_RX_TXRPT_FSM_HANG_ERR BIT(19)
2717#define B_AX_RX_F2PCMD_FSM_HANG_ERR BIT(18)
2718#define B_AX_RX_RU0_ZERO_LEN_ERR BIT(17)
2719#define B_AX_RX_RU1_ZERO_LEN_ERR BIT(16)
2720#define B_AX_RX_RU2_ZERO_LEN_ERR BIT(15)
2721#define B_AX_RX_RU3_ZERO_LEN_ERR BIT(14)
2722#define B_AX_RX_RU4_ZERO_LEN_ERR BIT(13)
2723#define B_AX_RX_RU5_ZERO_LEN_ERR BIT(12)
2724#define B_AX_RX_RU6_ZERO_LEN_ERR BIT(11)
2725#define B_AX_RX_RU7_ZERO_LEN_ERR BIT(10)
2726#define B_AX_RX_RXSTS_ZERO_LEN_ERR BIT(9)
2727#define B_AX_RX_CSI_ZERO_LEN_ERR BIT(8)
2728#define B_AX_PLE_DATA_OPT_FSM_HANG BIT(7)
2729#define B_AX_PLE_RXDATA_REQ_BUF_FSM_HANG BIT(6)
2730#define B_AX_PLE_TXRPT_REQ_BUF_FSM_HANG BIT(5)
2731#define B_AX_PLE_WD_OPT_FSM_HANG BIT(4)
2732#define B_AX_PLE_ENQ_FSM_HANG BIT(3)
2733#define B_AX_RXDATA_ENQUE_ORDER_ERR BIT(2)
2734#define B_AX_RXSTS_ENQUE_ORDER_ERR BIT(1)
2735#define B_AX_RX_CSI_PKT_NUM_ERR BIT(0)
2736
2737#define R_AX_RXDMA_CTRL_0 0xC804
2738#define R_AX_RXDMA_CTRL_0_C1 0xE804
2739#define B_AX_RXDMA_DBGOUT_EN BIT(31)
2740#define B_AX_RXDMA_DBG_SEL_MASK GENMASK(30, 29)
2741#define B_AX_RXDMA_FIFO_DBG_SEL_MASK GENMASK(28, 25)
2742#define B_AX_RXDMA_DEFAULT_PAGE_MASK GENMASK(22, 21)
2743#define B_AX_RXDMA_BUFF_REQ_PRI_MASK GENMASK(20, 19)
2744#define B_AX_RXDMA_TGT_QUEID_MASK GENMASK(18, 13)
2745#define B_AX_RXDMA_TGT_PRID_MASK GENMASK(12, 10)
2746#define B_AX_RXDMA_DIS_CSI_RELEASE BIT(9)
2747#define B_AX_RXDMA_DIS_RXSTS_WAIT_PTR_CLR BIT(7)
2748#define B_AX_RXDMA_DIS_CSI_WAIT_PTR_CLR BIT(6)
2749#define B_AX_RXSTS_PTR_FULL_MODE BIT(5)
2750#define B_AX_CSI_PTR_FULL_MODE BIT(4)
2751#define B_AX_RU3_PTR_FULL_MODE BIT(3)
2752#define B_AX_RU2_PTR_FULL_MODE BIT(2)
2753#define B_AX_RU1_PTR_FULL_MODE BIT(1)
2754#define B_AX_RU0_PTR_FULL_MODE BIT(0)
2755#define RX_FULL_MODE (B_AX_RU0_PTR_FULL_MODE | B_AX_RU1_PTR_FULL_MODE | \
2756		      B_AX_RU2_PTR_FULL_MODE | B_AX_RU3_PTR_FULL_MODE | \
2757		      B_AX_CSI_PTR_FULL_MODE | B_AX_RXSTS_PTR_FULL_MODE)
2758
2759#define R_AX_RX_CTRL0 0xC808
2760#define R_AX_RX_CTRL0_C1 0xE808
2761#define B_AX_DLE_CLOCK_FORCE_V1 BIT(31)
2762#define B_AX_TXDMA_CLOCK_FORCE_V1 BIT(30)
2763#define B_AX_RXDMA_CLOCK_FORCE_V1 BIT(29)
2764#define B_AX_RXDMA_DEFAULT_PAGE_V1_MASK GENMASK(28, 24)
2765#define B_AX_RXDMA_CSI_TGT_QUEID_MASK GENMASK(23, 18)
2766#define B_AX_RXDMA_CSI_TGT_PRID_MASK GENMASK(17, 15)
2767#define B_AX_RXDMA_DIS_CSI_RELEASE_V1 BIT(14)
2768#define B_AX_CSI_PTR_FULL_MODE_V1 BIT(13)
2769#define B_AX_RXDATA_PTR_FULL_MODE BIT(12)
2770#define B_AX_RXSTS_PTR_FULL_MODE_V1 BIT(11)
2771#define B_AX_TXRPT_FULL_RSV_DEPTH_V1_MASK GENMASK(10, 8)
2772#define B_AX_RXDATA_FULL_RSV_DEPTH_MASK GENMASK(7, 5)
2773#define B_AX_RXSTS_FULL_RSV_DEPTH_V1_MASK GENMASK(4, 2)
2774#define B_AX_ORDER_FIFO_MASK GENMASK(1, 0)
2775
2776#define R_AX_RX_CTRL1 0xC80C
2777#define R_AX_RX_CTRL1_C1 0xE80C
2778#define B_AX_RXDMA_TXRPT_QUEUE_ID_SW_EN BIT(31)
2779#define B_AX_RXDMA_TXRPT_QUEUE_ID_SW_V1_MASK GENMASK(30, 25)
2780#define B_AX_RXDMA_F2PCMD_QUEUE_ID_SW_EN BIT(24)
2781#define B_AX_RXDMA_F2PCMD_QUEUE_ID_SW_V1_MASK GENMASK(23, 18)
2782#define B_AX_RXDMA_TXRPT_QUEUE_ID_TGT_SW_EN BIT(17)
2783#define B_AX_RXDMA_TXRPT_QUEUE_ID_TGT_SW_1_MASK GENMASK(16, 11)
2784#define B_AX_RXDMA_F2PCMD_QUEUE_ID_TGT_SW_EN BIT(10)
2785#define B_AX_RXDMA_F2PCMD_QUEUE_ID_TGT_SW_1_MASK GENMASK(9, 4)
2786#define B_AX_ORDER_FIFO_OUT BIT(3)
2787#define B_AX_ORDER_FIFO_EMPTY BIT(2)
2788#define B_AX_DBG_SEL_MASK GENMASK(1, 0)
2789
2790#define R_AX_RX_CTRL2 0xC810
2791#define R_AX_RX_CTRL2_C1 0xE810
2792#define B_AX_DLE_WDE_STATE_V1_MASK GENMASK(31, 30)
2793#define B_AX_DLE_PLE_STATE_V1_MASK GENMASK(29, 28)
2794#define B_AX_DLE_REQ_BUF_STATE_MASK GENMASK(27, 26)
2795#define B_AX_DLE_ENQ_STATE_V1 BIT(25)
2796#define B_AX_RX_DBG_SEL_MASK GENMASK(24, 19)
2797#define B_AX_MACRX_CS_MASK GENMASK(18, 14)
2798#define B_AX_RXSTS_CS_MASK GENMASK(13, 9)
2799#define B_AX_ERR_INDICATOR BIT(5)
2800#define B_AX_TXRPT_CS_MASK GENMASK(4, 0)
2801
2802#define R_AX_RXDMA_PKT_INFO_0 0xC814
2803#define R_AX_RXDMA_PKT_INFO_1 0xC818
2804#define R_AX_RXDMA_PKT_INFO_2 0xC81C
2805
2806#define R_AX_RX_ERR_FLAG_IMR 0xC804
2807#define R_AX_RX_ERR_FLAG_IMR_C1 0xE804
2808#define B_AX_RX_GET_NULL_PKT_ERR_MSK BIT(30)
2809#define B_AX_RX_RU0_FSM_HANG_MSK_ERR_MSK BIT(29)
2810#define B_AX_RX_RU1_FSM_HANG_MSK_ERR_MSK BIT(28)
2811#define B_AX_RX_RU2_FSM_HANG_MSK_ERR_MSK BIT(27)
2812#define B_AX_RX_RU3_FSM_HANG_MSK_ERR_MSK BIT(26)
2813#define B_AX_RX_RU4_FSM_HANG_MSK_ERR_MSK BIT(25)
2814#define B_AX_RX_RU5_FSM_HANG_MSK_ERR_MSK BIT(24)
2815#define B_AX_RX_RU6_FSM_HANG_MSK_ERR_MSK BIT(23)
2816#define B_AX_RX_RU7_FSM_HANG_MSK_ERR_MSK BIT(22)
2817#define B_AX_RX_RXSTS_FSM_HANG_MSK_ERR_MSK BIT(21)
2818#define B_AX_RX_CSI_FSM_HANG_MSK_ERR_MSK BIT(20)
2819#define B_AX_RX_TXRPT_FSM_HANG_MSK_ERR_MSK BIT(19)
2820#define B_AX_RX_F2PCMD_FSM_HANG_MSK_ERR_MSK BIT(18)
2821#define B_AX_RX_RU0_ZERO_LEN_ERR_MSK BIT(17)
2822#define B_AX_RX_RU1_ZERO_LEN_ERR_MSK BIT(16)
2823#define B_AX_RX_RU2_ZERO_LEN_ERR_MSK BIT(15)
2824#define B_AX_RX_RU3_ZERO_LEN_ERR_MSK BIT(14)
2825#define B_AX_RX_RU4_ZERO_LEN_ERR_MSK BIT(13)
2826#define B_AX_RX_RU5_ZERO_LEN_ERR_MSK BIT(12)
2827#define B_AX_RX_RU6_ZERO_LEN_ERR_MSK BIT(11)
2828#define B_AX_RX_RU7_ZERO_LEN_ERR_MSK BIT(10)
2829#define B_AX_RX_RXSTS_ZERO_LEN_ERR_MSK BIT(9)
2830#define B_AX_RX_CSI_ZERO_LEN_ERR_MSK BIT(8)
2831#define B_AX_PLE_DATA_OPT_FSM_HANG_MSK BIT(7)
2832#define B_AX_PLE_RXDATA_REQ_BUF_FSM_HANG_MSK BIT(6)
2833#define B_AX_PLE_TXRPT_REQ_BUF_FSM_HANG_MSK BIT(5)
2834#define B_AX_PLE_WD_OPT_FSM_HANG_MSK BIT(4)
2835#define B_AX_PLE_ENQ_FSM_HANG_MSK BIT(3)
2836#define B_AX_RXDATA_ENQUE_ORDER_ERR_MSK BIT(2)
2837#define B_AX_RXSTS_ENQUE_ORDER_ERR_MSK BIT(1)
2838#define B_AX_RX_CSI_PKT_NUM_ERR_MSK BIT(0)
2839#define B_AX_RX_ERR_IMR_CLR_V1 (B_AX_RXSTS_ENQUE_ORDER_ERR_MSK | \
2840				B_AX_RXDATA_ENQUE_ORDER_ERR_MSK | \
2841				B_AX_RX_CSI_ZERO_LEN_ERR_MSK | \
2842				B_AX_RX_RXSTS_ZERO_LEN_ERR_MSK | \
2843				B_AX_RX_RU7_ZERO_LEN_ERR_MSK | \
2844				B_AX_RX_RU6_ZERO_LEN_ERR_MSK | \
2845				B_AX_RX_RU5_ZERO_LEN_ERR_MSK | \
2846				B_AX_RX_RU4_ZERO_LEN_ERR_MSK | \
2847				B_AX_RX_RU3_ZERO_LEN_ERR_MSK | \
2848				B_AX_RX_RU2_ZERO_LEN_ERR_MSK | \
2849				B_AX_RX_RU1_ZERO_LEN_ERR_MSK | \
2850				B_AX_RX_RU0_ZERO_LEN_ERR_MSK | \
2851				B_AX_RX_F2PCMD_FSM_HANG_MSK_ERR_MSK | \
2852				B_AX_RX_TXRPT_FSM_HANG_MSK_ERR_MSK | \
2853				B_AX_RX_CSI_FSM_HANG_MSK_ERR_MSK | \
2854				B_AX_RX_RXSTS_FSM_HANG_MSK_ERR_MSK | \
2855				B_AX_RX_RU7_FSM_HANG_MSK_ERR_MSK | \
2856				B_AX_RX_RU6_FSM_HANG_MSK_ERR_MSK | \
2857				B_AX_RX_RU5_FSM_HANG_MSK_ERR_MSK | \
2858				B_AX_RX_RU4_FSM_HANG_MSK_ERR_MSK | \
2859				B_AX_RX_RU3_FSM_HANG_MSK_ERR_MSK | \
2860				B_AX_RX_RU2_FSM_HANG_MSK_ERR_MSK | \
2861				B_AX_RX_RU1_FSM_HANG_MSK_ERR_MSK | \
2862				B_AX_RX_RU0_FSM_HANG_MSK_ERR_MSK | \
2863				B_AX_RX_GET_NULL_PKT_ERR_MSK)
2864#define B_AX_RX_ERR_IMR_SET_V1 (B_AX_RXSTS_ENQUE_ORDER_ERR_MSK | \
2865				B_AX_RXDATA_ENQUE_ORDER_ERR_MSK | \
2866				B_AX_RX_CSI_ZERO_LEN_ERR_MSK | \
2867				B_AX_RX_RXSTS_ZERO_LEN_ERR_MSK | \
2868				B_AX_RX_RU7_ZERO_LEN_ERR_MSK | \
2869				B_AX_RX_RU6_ZERO_LEN_ERR_MSK | \
2870				B_AX_RX_RU5_ZERO_LEN_ERR_MSK | \
2871				B_AX_RX_RU4_ZERO_LEN_ERR_MSK | \
2872				B_AX_RX_RU3_ZERO_LEN_ERR_MSK | \
2873				B_AX_RX_RU2_ZERO_LEN_ERR_MSK | \
2874				B_AX_RX_RU1_ZERO_LEN_ERR_MSK | \
2875				B_AX_RX_RU0_ZERO_LEN_ERR_MSK | \
2876				B_AX_RX_F2PCMD_FSM_HANG_MSK_ERR_MSK | \
2877				B_AX_RX_TXRPT_FSM_HANG_MSK_ERR_MSK | \
2878				B_AX_RX_CSI_FSM_HANG_MSK_ERR_MSK | \
2879				B_AX_RX_RXSTS_FSM_HANG_MSK_ERR_MSK | \
2880				B_AX_RX_RU7_FSM_HANG_MSK_ERR_MSK | \
2881				B_AX_RX_RU6_FSM_HANG_MSK_ERR_MSK | \
2882				B_AX_RX_RU5_FSM_HANG_MSK_ERR_MSK | \
2883				B_AX_RX_RU4_FSM_HANG_MSK_ERR_MSK | \
2884				B_AX_RX_RU3_FSM_HANG_MSK_ERR_MSK | \
2885				B_AX_RX_RU2_FSM_HANG_MSK_ERR_MSK | \
2886				B_AX_RX_RU1_FSM_HANG_MSK_ERR_MSK | \
2887				B_AX_RX_RU0_FSM_HANG_MSK_ERR_MSK | \
2888				B_AX_RX_GET_NULL_PKT_ERR_MSK)
2889
2890#define R_AX_TX_ERR_FLAG_IMR 0xC870
2891#define R_AX_TX_ERR_FLAG_IMR_C1 0xE870
2892#define B_AX_TX_RU0_FSM_HANG_ERR_MSK BIT(31)
2893#define B_AX_TX_RU1_FSM_HANG_ERR_MSK BIT(30)
2894#define B_AX_TX_RU2_FSM_HANG_ERR_MSK BIT(29)
2895#define B_AX_TX_RU3_FSM_HANG_ERR_MSK BIT(28)
2896#define B_AX_TX_RU4_FSM_HANG_ERR_MSK BIT(27)
2897#define B_AX_TX_RU5_FSM_HANG_ERR_MSK BIT(26)
2898#define B_AX_TX_RU6_FSM_HANG_ERR_MSK BIT(25)
2899#define B_AX_TX_RU7_FSM_HANG_ERR_MSK BIT(24)
2900#define B_AX_TX_RU8_FSM_HANG_ERR_MSK BIT(23)
2901#define B_AX_TX_RU9_FSM_HANG_ERR_MSK BIT(22)
2902#define B_AX_TX_RU10_FSM_HANG_ERR_MSK BIT(21)
2903#define B_AX_TX_RU11_FSM_HANG_ERR_MSK BIT(20)
2904#define B_AX_TX_RU12_FSM_HANG_ERR_MSK BIT(19)
2905#define B_AX_TX_RU13_FSM_HANG_ERR_MSK BIT(18)
2906#define B_AX_TX_RU14_FSM_HANG_ERR_MSK BIT(17)
2907#define B_AX_TX_RU15_FSM_HANG_ERR_MSK BIT(16)
2908#define B_AX_TX_CSI_FSM_HANG_ERR_MSK BIT(15)
2909#define B_AX_TX_WD_PLD_ID_FSM_HANG_ERR_MSK BIT(14)
2910#define B_AX_TX_ERR_IMR_CLR_V1 (B_AX_TX_WD_PLD_ID_FSM_HANG_ERR_MSK | \
2911				B_AX_TX_CSI_FSM_HANG_ERR_MSK | \
2912				B_AX_TX_RU7_FSM_HANG_ERR_MSK | \
2913				B_AX_TX_RU6_FSM_HANG_ERR_MSK | \
2914				B_AX_TX_RU5_FSM_HANG_ERR_MSK | \
2915				B_AX_TX_RU4_FSM_HANG_ERR_MSK | \
2916				B_AX_TX_RU3_FSM_HANG_ERR_MSK | \
2917				B_AX_TX_RU2_FSM_HANG_ERR_MSK | \
2918				B_AX_TX_RU1_FSM_HANG_ERR_MSK | \
2919				B_AX_TX_RU0_FSM_HANG_ERR_MSK)
2920#define B_AX_TX_ERR_IMR_SET_V1 (B_AX_TX_WD_PLD_ID_FSM_HANG_ERR_MSK | \
2921				B_AX_TX_CSI_FSM_HANG_ERR_MSK | \
2922				B_AX_TX_RU7_FSM_HANG_ERR_MSK | \
2923				B_AX_TX_RU6_FSM_HANG_ERR_MSK | \
2924				B_AX_TX_RU5_FSM_HANG_ERR_MSK | \
2925				B_AX_TX_RU4_FSM_HANG_ERR_MSK | \
2926				B_AX_TX_RU3_FSM_HANG_ERR_MSK | \
2927				B_AX_TX_RU2_FSM_HANG_ERR_MSK | \
2928				B_AX_TX_RU1_FSM_HANG_ERR_MSK | \
2929				B_AX_TX_RU0_FSM_HANG_ERR_MSK)
2930
2931#define R_AX_TCR0 0xCA00
2932#define R_AX_TCR0_C1 0xEA00
2933#define B_AX_TCR_ZLD_NUM_MASK GENMASK(31, 24)
2934#define B_AX_TCR_UDF_EN BIT(23)
2935#define B_AX_TCR_UDF_THSD_MASK GENMASK(22, 16)
2936#define TCR_UDF_THSD 0x6
2937#define B_AX_TCR_ERRSTEN_MASK GENMASK(15, 10)
2938#define B_AX_TCR_VHTSIGA1_TXPS BIT(9)
2939#define B_AX_TCR_PLCP_ERRHDL_EN BIT(8)
2940#define B_AX_TCR_PADSEL BIT(7)
2941#define B_AX_TCR_MASK_SIGBCRC BIT(6)
2942#define B_AX_TCR_SR_VAL15_ALLOW BIT(5)
2943#define B_AX_TCR_EN_EOF BIT(4)
2944#define B_AX_TCR_EN_SCRAM_INC BIT(3)
2945#define B_AX_TCR_EN_20MST BIT(2)
2946#define B_AX_TCR_CRC BIT(1)
2947#define B_AX_TCR_DISGCLK BIT(0)
2948
2949#define R_AX_TCR1 0xCA04
2950#define R_AX_TCR1_C1 0xEA04
2951#define B_AX_TXDFIFO_THRESHOLD GENMASK(31, 28)
2952#define B_AX_TCR_CCK_LOCK_CLK BIT(27)
2953#define B_AX_TCR_FORCE_READ_TXDFIFO BIT(26)
2954#define B_AX_TCR_USTIME GENMASK(23, 16)
2955#define B_AX_TCR_SMOOTH_VAL BIT(15)
2956#define B_AX_TCR_SMOOTH_CTRL BIT(14)
2957#define B_AX_CS_REQ_VAL BIT(13)
2958#define B_AX_CS_REQ_SEL BIT(12)
2959#define B_AX_TCR_ZLD_USTIME_AFTERPHYTXON GENMASK(11, 8)
2960#define B_AX_TCR_TXTIMEOUT GENMASK(7, 0)
2961
2962#define R_AX_MD_TSFT_STMP_CTL 0xCA08
2963#define R_AX_MD_TSFT_STMP_CTL_C1 0xEA08
2964#define B_AX_TSFT_OFS_MASK GENMASK(31, 16)
2965#define B_AX_STMP_THSD_MASK GENMASK(15, 8)
2966#define B_AX_UPD_HGQMD BIT(1)
2967#define B_AX_UPD_TIMIE BIT(0)
2968
2969#define R_AX_PPWRBIT_SETTING 0xCA0C
2970#define R_AX_PPWRBIT_SETTING_C1 0xEA0C
2971
2972#define R_AX_TXD_FIFO_CTRL 0xCA1C
2973#define R_AX_TXD_FIFO_CTRL_C1 0xEA1C
2974#define B_AX_NON_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(28, 24)
2975#define B_AX_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(20, 16)
2976#define B_AX_TXDFIFO_HIGH_MCS_THRE_MASK GENMASK(15, 12)
2977#define TXDFIFO_HIGH_MCS_THRE 0x7
2978#define B_AX_TXDFIFO_LOW_MCS_THRE_MASK GENMASK(11, 8)
2979#define TXDFIFO_LOW_MCS_THRE  0x7
2980#define B_AX_HIGH_MCS_PHY_RATE_MASK GENMASK(7, 4)
2981#define B_AX_BW_PHY_RATE_MASK GENMASK(1, 0)
2982
2983#define R_AX_MACTX_DBG_SEL_CNT 0xCA20
2984#define R_AX_MACTX_DBG_SEL_CNT_C1 0xEA20
2985#define B_AX_MACTX_MPDU_CNT GENMASK(31, 24)
2986#define B_AX_MACTX_DMA_CNT GENMASK(23, 16)
2987#define B_AX_LENGTH_ERR_FLAG_U3 BIT(11)
2988#define B_AX_LENGTH_ERR_FLAG_U2 BIT(10)
2989#define B_AX_LENGTH_ERR_FLAG_U1 BIT(9)
2990#define B_AX_LENGTH_ERR_FLAG_U0 BIT(8)
2991#define B_AX_DBGSEL_MACTX_MASK GENMASK(5, 0)
2992
2993#define R_AX_WMAC_TX_CTRL_DEBUG 0xCAE4
2994#define R_AX_WMAC_TX_CTRL_DEBUG_C1 0xEAE4
2995#define B_AX_TX_CTRL_DEBUG_SEL_MASK GENMASK(3, 0)
2996
2997#define R_AX_WMAC_TX_INFO0_DEBUG 0xCAE8
2998#define R_AX_WMAC_TX_INFO0_DEBUG_C1 0xEAE8
2999#define B_AX_TX_CTRL_INFO_P0_MASK GENMASK(31, 0)
3000
3001#define R_AX_WMAC_TX_INFO1_DEBUG 0xCAEC
3002#define R_AX_WMAC_TX_INFO1_DEBUG_C1 0xEAEC
3003#define B_AX_TX_CTRL_INFO_P1_MASK GENMASK(31, 0)
3004
3005#define R_AX_RSP_CHK_SIG 0xCC00
3006#define R_AX_RSP_CHK_SIG_C1 0xEC00
3007#define B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN BIT(30)
3008#define B_AX_RSP_TBPPDU_CHK_PWR BIT(29)
3009#define B_AX_RSP_CHK_BASIC_NAV BIT(21)
3010#define B_AX_RSP_CHK_INTRA_NAV BIT(20)
3011#define B_AX_RSP_CHK_TXNAV BIT(19)
3012#define B_AX_TXDATA_END_PS_OPT BIT(18)
3013#define B_AX_CHECK_SOUNDING_SEQ BIT(17)
3014#define B_AX_RXBA_IGNOREA2 BIT(16)
3015#define B_AX_ACKTO_CCK_MASK GENMASK(15, 8)
3016#define B_AX_ACKTO_MASK GENMASK(7, 0)
3017
3018#define R_AX_TRXPTCL_RESP_0 0xCC04
3019#define R_AX_TRXPTCL_RESP_0_C1 0xEC04
3020#define B_AX_WMAC_RESP_STBC_EN BIT(31)
3021#define B_AX_WMAC_RXFTM_TXACK_SC BIT(30)
3022#define B_AX_WMAC_RXFTM_TXACKBWEQ BIT(29)
3023#define B_AX_RSP_CHK_SEC_CCA_80 BIT(28)
3024#define B_AX_RSP_CHK_SEC_CCA_40 BIT(27)
3025#define B_AX_RSP_CHK_SEC_CCA_20 BIT(26)
3026#define B_AX_RSP_CHK_BTCCA BIT(25)
3027#define B_AX_RSP_CHK_EDCCA BIT(24)
3028#define B_AX_RSP_CHK_CCA BIT(23)
3029#define B_AX_WMAC_LDPC_EN BIT(22)
3030#define B_AX_WMAC_SGIEN BIT(21)
3031#define B_AX_WMAC_SPLCPEN BIT(20)
3032#define B_AX_WMAC_BESP_EARLY_TXBA BIT(17)
3033#define B_AX_WMAC_SPEC_SIFS_OFDM_MASK GENMASK(15, 8)
3034#define B_AX_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0)
3035#define WMAC_SPEC_SIFS_OFDM_52A 0x15
3036#define WMAC_SPEC_SIFS_OFDM_52B 0x11
3037#define WMAC_SPEC_SIFS_OFDM_52C 0x11
3038#define WMAC_SPEC_SIFS_CCK	 0xA
3039
3040#define R_AX_TRXPTCL_RRSR_CTL_0 0xCC08
3041#define R_AX_TRXPTCL_RRSR_CTL_0_C1 0xEC08
3042#define B_AX_RESP_TX_MACID_CCA_TH_EN BIT(31)
3043#define B_AX_RESP_TX_PWRMODE_MASK GENMASK(30, 28)
3044#define B_AX_FTM_RRSR_RATE_EN_MASK GENMASK(27, 24)
3045#define B_AX_NESS_MASK GENMASK(23, 22)
3046#define B_AX_WMAC_RESP_DOPPLEB_AX_EN BIT(21)
3047#define B_AX_WMAC_RESP_DCM_EN BIT(20)
3048#define B_AX_WMAC_RRSB_AX_CCK_MASK GENMASK(19, 16)
3049#define B_AX_WMAC_RESP_RATE_EN_MASK GENMASK(15, 12)
3050#define B_AX_WMAC_RESP_RSC_MASK GENMASK(11, 10)
3051#define B_AX_WMAC_RESP_REF_RATE_SEL BIT(9)
3052#define B_AX_WMAC_RESP_REF_RATE_MASK GENMASK(8, 0)
3053
3054#define R_AX_MAC_LOOPBACK 0xCC20
3055#define R_AX_MAC_LOOPBACK_C1 0xEC20
3056#define B_AX_MACLBK_EN BIT(0)
3057
3058#define R_AX_WMAC_NAV_CTL 0xCC80
3059#define R_AX_WMAC_NAV_CTL_C1 0xEC80
3060#define B_AX_WMAC_NAV_UPPER_EN BIT(26)
3061#define B_AX_WMAC_0P125US_TIMER_MASK GENMASK(25, 18)
3062#define B_AX_WMAC_PLCP_UP_NAV_EN BIT(17)
3063#define B_AX_WMAC_TF_UP_NAV_EN BIT(16)
3064#define B_AX_WMAC_NAV_UPPER_MASK GENMASK(15, 8)
3065#define NAV_12MS 0xBC
3066#define NAV_25MS 0xC4
3067#define B_AX_WMAC_RTS_RST_DUR_MASK GENMASK(7, 0)
3068
3069#define R_AX_RXTRIG_TEST_USER_2 0xCCB0
3070#define R_AX_RXTRIG_TEST_USER_2_C1 0xECB0
3071#define B_AX_RXTRIG_MACID_MASK GENMASK(31, 24)
3072#define B_AX_RXTRIG_RU26_DIS BIT(21)
3073#define B_AX_RXTRIG_FCSCHK_EN BIT(20)
3074#define B_AX_RXTRIG_PORT_SEL_MASK GENMASK(19, 17)
3075#define B_AX_RXTRIG_EN BIT(16)
3076#define B_AX_RXTRIG_USERINFO_2_MASK GENMASK(15, 0)
3077
3078#define R_AX_TRXPTCL_ERROR_INDICA_MASK 0xCCBC
3079#define R_AX_TRXPTCL_ERROR_INDICA_MASK_C1 0xECBC
3080#define B_AX_WMAC_MODE BIT(22)
3081#define B_AX_WMAC_TIMETOUT_THR_MASK GENMASK(21, 16)
3082#define B_AX_RMAC_FTM BIT(8)
3083#define B_AX_RMAC_CSI BIT(7)
3084#define B_AX_TMAC_MIMO_CTRL BIT(6)
3085#define B_AX_TMAC_RXTB BIT(5)
3086#define B_AX_TMAC_HWSIGB_GEN BIT(4)
3087#define B_AX_TMAC_TXPLCP BIT(3)
3088#define B_AX_TMAC_RESP BIT(2)
3089#define B_AX_TMAC_TXCTL BIT(1)
3090#define B_AX_TMAC_MACTX BIT(0)
3091#define B_AX_TMAC_IMR_CLR_V1 (B_AX_TMAC_MACTX | \
3092			      B_AX_TMAC_TXCTL | \
3093			      B_AX_TMAC_RESP | \
3094			      B_AX_TMAC_TXPLCP | \
3095			      B_AX_TMAC_HWSIGB_GEN | \
3096			      B_AX_TMAC_RXTB | \
3097			      B_AX_TMAC_MIMO_CTRL | \
3098			      B_AX_RMAC_CSI | \
3099			      B_AX_RMAC_FTM)
3100#define B_AX_TMAC_IMR_SET_V1 (B_AX_TMAC_MACTX | \
3101			      B_AX_TMAC_TXCTL | \
3102			      B_AX_TMAC_RESP | \
3103			      B_AX_TMAC_TXPLCP | \
3104			      B_AX_TMAC_HWSIGB_GEN | \
3105			      B_AX_TMAC_RXTB | \
3106			      B_AX_TMAC_MIMO_CTRL | \
3107			      B_AX_RMAC_FTM)
3108
3109#define R_AX_TRXPTCL_ERROR_INDICA 0xCCC0
3110#define R_AX_TRXPTCL_ERROR_INDICA_C1 0xECC0
3111#define B_AX_FTM_ERROR_FLAG_CLR BIT(8)
3112#define B_AX_CSI_ERROR_FLAG_CLR BIT(7)
3113#define B_AX_MIMOCTRL_ERROR_FLAG_CLR BIT(6)
3114#define B_AX_RXTB_ERROR_FLAG_CLR BIT(5)
3115#define B_AX_HWSIGB_GEN_ERROR_FLAG_CLR BIT(4)
3116#define B_AX_TXPLCP_ERROR_FLAG_CLR BIT(3)
3117#define B_AX_RESP_ERROR_FLAG_CLR BIT(2)
3118#define B_AX_TXCTL_ERROR_FLAG_CLR BIT(1)
3119#define B_AX_MACTX_ERROR_FLAG_CLR BIT(0)
3120
3121#define R_AX_WMAC_TX_TF_INFO_0 0xCCD0
3122#define R_AX_WMAC_TX_TF_INFO_0_C1 0xECD0
3123#define B_AX_WMAC_TX_TF_INFO_SEL_MASK GENMASK(2, 0)
3124
3125#define R_AX_WMAC_TX_TF_INFO_1 0xCCD4
3126#define R_AX_WMAC_TX_TF_INFO_1_C1 0xECD4
3127#define B_AX_WMAC_TX_TF_INFO_P0_MASK GENMASK(31, 0)
3128
3129#define R_AX_WMAC_TX_TF_INFO_2 0xCCD8
3130#define R_AX_WMAC_TX_TF_INFO_2_C1 0xECD8
3131#define B_AX_WMAC_TX_TF_INFO_P1_MASK GENMASK(31, 0)
3132
3133#define R_AX_TMAC_ERR_IMR_ISR 0xCCEC
3134#define R_AX_TMAC_ERR_IMR_ISR_C1 0xECEC
3135#define B_AX_TMAC_TXPLCP_ERR_CLR BIT(19)
3136#define B_AX_TMAC_RESP_ERR_CLR BIT(18)
3137#define B_AX_TMAC_TXCTL_ERR_CLR BIT(17)
3138#define B_AX_TMAC_MACTX_ERR_CLR BIT(16)
3139#define B_AX_TMAC_TXPLCP_ERR BIT(14)
3140#define B_AX_TMAC_RESP_ERR BIT(13)
3141#define B_AX_TMAC_TXCTL_ERR BIT(12)
3142#define B_AX_TMAC_MACTX_ERR BIT(11)
3143#define B_AX_TMAC_TXPLCP_INT_EN BIT(10)
3144#define B_AX_TMAC_RESP_INT_EN BIT(9)
3145#define B_AX_TMAC_TXCTL_INT_EN BIT(8)
3146#define B_AX_TMAC_MACTX_INT_EN BIT(7)
3147#define B_AX_WMAC_INT_MODE BIT(6)
3148#define B_AX_TMAC_TIMETOUT_THR_MASK GENMASK(5, 0)
3149#define B_AX_TMAC_IMR_CLR (B_AX_TMAC_MACTX_INT_EN | \
3150			   B_AX_TMAC_TXCTL_INT_EN | \
3151			   B_AX_TMAC_RESP_INT_EN | \
3152			   B_AX_TMAC_TXPLCP_INT_EN)
3153#define B_AX_TMAC_IMR_SET (B_AX_TMAC_MACTX_INT_EN | \
3154			   B_AX_TMAC_TXCTL_INT_EN | \
3155			   B_AX_TMAC_RESP_INT_EN | \
3156			   B_AX_TMAC_TXPLCP_INT_EN)
3157
3158#define R_AX_DBGSEL_TRXPTCL 0xCCF4
3159#define R_AX_DBGSEL_TRXPTCL_C1 0xECF4
3160#define B_AX_DBGSEL_TRXPTCL_MASK GENMASK(7, 0)
3161
3162#define R_AX_PHYINFO_ERR_IMR_V1 0xCCF8
3163#define R_AX_PHYINFO_ERR_IMR_V1_C1 0xECF8
3164#define B_AX_PHYINTF_TIMEOUT_THR_MSAK_V1 GENMASK(21, 16)
3165#define B_AX_CSI_ON_TIMEOUT_EN BIT(5)
3166#define B_AX_STS_ON_TIMEOUT_EN BIT(4)
3167#define B_AX_DATA_ON_TIMEOUT_EN BIT(3)
3168#define B_AX_OFDM_CCA_TIMEOUT_EN BIT(2)
3169#define B_AX_CCK_CCA_TIMEOUT_EN BIT(1)
3170#define B_AX_PHY_TXON_TIMEOUT_EN BIT(0)
3171#define B_AX_PHYINFO_IMR_CLR_V1 (B_AX_PHY_TXON_TIMEOUT_EN | \
3172				 B_AX_CCK_CCA_TIMEOUT_EN | \
3173				 B_AX_OFDM_CCA_TIMEOUT_EN | \
3174				 B_AX_DATA_ON_TIMEOUT_EN | \
3175				 B_AX_STS_ON_TIMEOUT_EN | \
3176				 B_AX_CSI_ON_TIMEOUT_EN)
3177#define B_AX_PHYINFO_IMR_SET_V1 (B_AX_PHY_TXON_TIMEOUT_EN | \
3178				 B_AX_CCK_CCA_TIMEOUT_EN | \
3179				 B_AX_OFDM_CCA_TIMEOUT_EN | \
3180				 B_AX_DATA_ON_TIMEOUT_EN | \
3181				 B_AX_STS_ON_TIMEOUT_EN | \
3182				 B_AX_CSI_ON_TIMEOUT_EN)
3183
3184#define R_AX_PHYINFO_ERR_IMR 0xCCFC
3185#define R_AX_PHYINFO_ERR_IMR_C1 0xECFC
3186#define B_AX_CSI_ON_TIMEOUT BIT(29)
3187#define B_AX_STS_ON_TIMEOUT BIT(28)
3188#define B_AX_DATA_ON_TIMEOUT BIT(27)
3189#define B_AX_OFDM_CCA_TIMEOUT BIT(26)
3190#define B_AX_CCK_CCA_TIMEOUT BIT(25)
3191#define B_AXC_PHY_TXON_TIMEOUT BIT(24)
3192#define B_AX_CSI_ON_TIMEOUT_INT_EN BIT(21)
3193#define B_AX_STS_ON_TIMEOUT_INT_EN BIT(20)
3194#define B_AX_DATA_ON_TIMEOUT_INT_EN BIT(19)
3195#define B_AX_OFDM_CCA_TIMEOUT_INT_EN BIT(18)
3196#define B_AX_CCK_CCA_TIMEOUT_INT_EN BIT(17)
3197#define B_AX_PHY_TXON_TIMEOUT_INT_EN BIT(16)
3198#define B_AX_PHYINTF_TIMEOUT_THR_MSAK GENMASK(5, 0)
3199#define B_AX_PHYINFO_IMR_EN_ALL (B_AX_PHY_TXON_TIMEOUT_INT_EN | \
3200				 B_AX_CCK_CCA_TIMEOUT_INT_EN | \
3201				 B_AX_OFDM_CCA_TIMEOUT_INT_EN | \
3202				 B_AX_DATA_ON_TIMEOUT_INT_EN | \
3203				 B_AX_STS_ON_TIMEOUT_INT_EN | \
3204				 B_AX_CSI_ON_TIMEOUT_INT_EN | \
3205				 B_AX_PHYINTF_TIMEOUT_THR_MSAK)
3206#define B_AX_PHYINFO_IMR_SET (B_AX_PHY_TXON_TIMEOUT_INT_EN | 0x7)
3207
3208#define R_AX_PHYINFO_ERR_ISR 0xCCFC
3209#define R_AX_PHYINFO_ERR_ISR_C1 0xECFC
3210
3211#define R_AX_BFMER_CTRL_0 0xCD78
3212#define R_AX_BFMER_CTRL_0_C1 0xED78
3213#define B_AX_BFMER_HE_CSI_OFFSET_MASK GENMASK(31, 24)
3214#define B_AX_BFMER_VHT_CSI_OFFSET_MASK GENMASK(23, 16)
3215#define B_AX_BFMER_HT_CSI_OFFSET_MASK GENMASK(15, 8)
3216#define B_AX_BFMER_NDP_BFEN BIT(2)
3217#define B_AX_BFMER_VHT_BFPRT_CHK BIT(0)
3218
3219#define R_AX_BFMEE_RESP_OPTION 0xCD80
3220#define R_AX_BFMEE_RESP_OPTION_C1 0xED80
3221#define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK GENMASK(31, 24)
3222#define B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK GENMASK(23, 20)
3223#define BFRP_RX_STANDBY_TIMER_KEEP 0x0
3224#define BFRP_RX_STANDBY_TIMER_RELEASE 0x1
3225#define B_AX_MU_BFRPTSEG_SEL_MASK GENMASK(18, 17)
3226#define B_AX_BFMEE_NDP_RXSTDBY_SEL BIT(16)
3227#define BFRP_RX_STANDBY_TIMER		0x0
3228#define NDP_RX_STANDBY_TIMER		0xFF
3229#define B_AX_BFMEE_HE_NDPA_EN BIT(2)
3230#define B_AX_BFMEE_VHT_NDPA_EN BIT(1)
3231#define B_AX_BFMEE_HT_NDPA_EN BIT(0)
3232
3233#define R_AX_TRXPTCL_RESP_CSI_CTRL_0 0xCD88
3234#define R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 0xED88
3235#define R_AX_TRXPTCL_RESP_CSI_CTRL_1 0xCD94
3236#define R_AX_TRXPTCL_RESP_CSI_CTRL_1_C1 0xED94
3237#define B_AX_BFMEE_CSISEQ_SEL BIT(29)
3238#define B_AX_BFMEE_BFPARAM_SEL BIT(28)
3239#define B_AX_BFMEE_OFDM_LEN_TH_MASK GENMASK(27, 24)
3240#define B_AX_BFMEE_BF_PORT_SEL BIT(23)
3241#define B_AX_BFMEE_USE_NSTS BIT(22)
3242#define B_AX_BFMEE_CSI_RATE_FB_EN BIT(21)
3243#define B_AX_BFMEE_CSI_GID_SEL BIT(20)
3244#define B_AX_BFMEE_CSI_RSC_MASK GENMASK(19, 18)
3245#define B_AX_BFMEE_CSI_FORCE_RETE_EN BIT(17)
3246#define B_AX_BFMEE_CSI_USE_NDPARATE BIT(16)
3247#define B_AX_BFMEE_CSI_WITHHTC_EN BIT(15)
3248#define B_AX_BFMEE_CSIINFO0_BF_EN BIT(14)
3249#define B_AX_BFMEE_CSIINFO0_STBC_EN BIT(13)
3250#define B_AX_BFMEE_CSIINFO0_LDPC_EN BIT(12)
3251#define B_AX_BFMEE_CSIINFO0_CS_MASK GENMASK(11, 10)
3252#define B_AX_BFMEE_CSIINFO0_CB_MASK GENMASK(9, 8)
3253#define B_AX_BFMEE_CSIINFO0_NG_MASK GENMASK(7, 6)
3254#define B_AX_BFMEE_CSIINFO0_NR_MASK GENMASK(5, 3)
3255#define B_AX_BFMEE_CSIINFO0_NC_MASK GENMASK(2, 0)
3256
3257#define R_AX_TRXPTCL_RESP_CSI_RRSC 0xCD8C
3258#define R_AX_TRXPTCL_RESP_CSI_RRSC_C1 0xED8C
3259#define CSI_RRSC_BMAP 0x29292911
3260
3261#define R_AX_TRXPTCL_RESP_CSI_RATE 0xCD90
3262#define R_AX_TRXPTCL_RESP_CSI_RATE_C1 0xED90
3263#define B_AX_BFMEE_HE_CSI_RATE_MASK GENMASK(22, 16)
3264#define B_AX_BFMEE_VHT_CSI_RATE_MASK GENMASK(14, 8)
3265#define B_AX_BFMEE_HT_CSI_RATE_MASK GENMASK(6, 0)
3266#define CSI_INIT_RATE_HE		0x3
3267#define CSI_INIT_RATE_VHT		0x3
3268#define CSI_INIT_RATE_HT		0x3
3269
3270#define R_AX_RCR 0xCE00
3271#define R_AX_RCR_C1 0xEE00
3272#define B_AX_STOP_RX_IN BIT(11)
3273#define B_AX_DRV_INFO_SIZE_MASK GENMASK(10, 8)
3274#define B_AX_CH_EN_MASK GENMASK(3, 0)
3275
3276#define R_AX_DLK_PROTECT_CTL 0xCE02
3277#define R_AX_DLK_PROTECT_CTL_C1 0xEE02
3278#define B_AX_RX_DLK_CCA_TIME_MASK GENMASK(15, 8)
3279#define B_AX_RX_DLK_DATA_TIME_MASK GENMASK(7, 4)
3280#define B_AX_RX_DLK_RST_EN BIT(1)
3281#define B_AX_RX_DLK_INT_EN BIT(0)
3282
3283#define R_AX_PLCP_HDR_FLTR 0xCE04
3284#define R_AX_PLCP_HDR_FLTR_C1 0xEE04
3285#define B_AX_DIS_CHK_MIN_LEN BIT(8)
3286#define B_AX_HE_SIGB_CRC_CHK BIT(6)
3287#define B_AX_VHT_MU_SIGB_CRC_CHK BIT(5)
3288#define B_AX_VHT_SU_SIGB_CRC_CHK BIT(4)
3289#define B_AX_SIGA_CRC_CHK BIT(3)
3290#define B_AX_LSIG_PARITY_CHK_EN BIT(2)
3291#define B_AX_CCK_SIG_CHK BIT(1)
3292#define B_AX_CCK_CRC_CHK BIT(0)
3293
3294#define R_AX_RX_FLTR_OPT 0xCE20
3295#define R_AX_RX_FLTR_OPT_C1 0xEE20
3296#define B_AX_UID_FILTER_MASK GENMASK(31, 24)
3297#define B_AX_UNSPT_FILTER_SH 22
3298#define B_AX_UNSPT_FILTER_MASK GENMASK(23, 22)
3299#define B_AX_RX_MPDU_MAX_LEN_MASK GENMASK(21, 16)
3300#define B_AX_RX_MPDU_MAX_LEN_SIZE 0x3f
3301#define B_AX_A_FTM_REQ BIT(14)
3302#define B_AX_A_ERR_PKT BIT(13)
3303#define B_AX_A_UNSUP_PKT BIT(12)
3304#define B_AX_A_CRC32_ERR BIT(11)
3305#define B_AX_A_PWR_MGNT BIT(10)
3306#define B_AX_A_BCN_CHK_RULE_MASK GENMASK(9, 8)
3307#define B_AX_A_BCN_CHK_EN BIT(7)
3308#define B_AX_A_MC_LIST_CAM_MATCH BIT(6)
3309#define B_AX_A_BC_CAM_MATCH BIT(5)
3310#define B_AX_A_UC_CAM_MATCH BIT(4)
3311#define B_AX_A_MC BIT(3)
3312#define B_AX_A_BC BIT(2)
3313#define B_AX_A_A1_MATCH BIT(1)
3314#define B_AX_SNIFFER_MODE BIT(0)
3315#define DEFAULT_AX_RX_FLTR (B_AX_A_A1_MATCH | B_AX_A_BC | B_AX_A_MC |	       \
3316			    B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH |	       \
3317			    B_AX_A_PWR_MGNT | B_AX_A_FTM_REQ |		       \
3318			    u32_encode_bits(3, B_AX_UID_FILTER_MASK) |	       \
3319			    B_AX_A_BCN_CHK_EN)
3320#define B_AX_RX_FLTR_CFG_MASK ((u32)~B_AX_RX_MPDU_MAX_LEN_MASK)
3321
3322#define R_AX_CTRL_FLTR 0xCE24
3323#define R_AX_CTRL_FLTR_C1 0xEE24
3324#define R_AX_MGNT_FLTR 0xCE28
3325#define R_AX_MGNT_FLTR_C1 0xEE28
3326#define R_AX_DATA_FLTR 0xCE2C
3327#define R_AX_DATA_FLTR_C1 0xEE2C
3328#define RX_FLTR_FRAME_DROP	0x00000000
3329#define RX_FLTR_FRAME_TO_HOST	0x55555555
3330#define RX_FLTR_FRAME_TO_WLCPU	0xAAAAAAAA
3331
3332#define R_AX_ADDR_CAM_CTRL 0xCE34
3333#define R_AX_ADDR_CAM_CTRL_C1 0xEE34
3334#define B_AX_ADDR_CAM_RANGE_MASK GENMASK(23, 16)
3335#define B_AX_ADDR_CAM_CMPLIMT_MASK GENMASK(15, 12)
3336#define B_AX_ADDR_CAM_CLR BIT(8)
3337#define B_AX_ADDR_CAM_A2_B0_CHK BIT(2)
3338#define B_AX_ADDR_CAM_SRCH_PERPKT BIT(1)
3339#define B_AX_ADDR_CAM_EN BIT(0)
3340
3341#define R_AX_RESPBA_CAM_CTRL 0xCE3C
3342#define R_AX_RESPBA_CAM_CTRL_C1 0xEE3C
3343#define B_AX_SSN_SEL BIT(2)
3344#define B_AX_BACAM_RST_MASK GENMASK(1, 0)
3345#define S_AX_BACAM_RST_ALL 2
3346
3347#define R_AX_PPDU_STAT 0xCE40
3348#define R_AX_PPDU_STAT_C1 0xEE40
3349#define B_AX_PPDU_STAT_RPT_TRIG BIT(8)
3350#define B_AX_PPDU_STAT_RPT_CRC32 BIT(5)
3351#define B_AX_PPDU_STAT_RPT_A1M BIT(4)
3352#define B_AX_APP_PLCP_HDR_RPT BIT(3)
3353#define B_AX_APP_RX_CNT_RPT BIT(2)
3354#define B_AX_APP_MAC_INFO_RPT BIT(1)
3355#define B_AX_PPDU_STAT_RPT_EN BIT(0)
3356
3357#define R_AX_RX_SR_CTRL 0xCE4A
3358#define R_AX_RX_SR_CTRL_C1 0xEE4A
3359#define B_AX_SR_EN BIT(0)
3360
3361#define R_AX_BSSID_SRC_CTRL 0xCE4B
3362#define R_AX_BSSID_SRC_CTRL_C1 0xEE4B
3363#define B_AX_BSSID_MATCH BIT(3)
3364#define B_AX_PARTIAL_AID_MATCH BIT(2)
3365#define B_AX_BSSCOLOR_MATCH BIT(1)
3366#define B_AX_PLCP_SRC_EN BIT(0)
3367
3368#define R_AX_CSIRPT_OPTION 0xCE64
3369#define R_AX_CSIRPT_OPTION_C1 0xEE64
3370#define B_AX_CSIPRT_HESU_AID_EN BIT(25)
3371#define B_AX_CSIPRT_VHTSU_AID_EN BIT(24)
3372
3373#define R_AX_BCN_PSR_RPT_P0 0xCE84
3374#define R_AX_BCN_PSR_RPT_P0_C1 0xEE84
3375#define B_AX_BCAID_P0_MASK GENMASK(10, 0)
3376
3377#define R_AX_RX_STATE_MONITOR 0xCEF0
3378#define R_AX_RX_STATE_MONITOR_C1 0xEEF0
3379#define B_AX_RX_STATE_MONITOR_MASK GENMASK(31, 0)
3380#define B_AX_STATE_CUR_MASK GENMASK(31, 16)
3381#define B_AX_STATE_NXT_MASK GENMASK(13, 8)
3382#define B_AX_STATE_UPD BIT(7)
3383#define B_AX_STATE_SEL_MASK GENMASK(4, 0)
3384
3385#define R_AX_RMAC_ERR_ISR 0xCEF4
3386#define R_AX_RMAC_ERR_ISR_C1 0xEEF4
3387#define B_AX_RXERR_INTPS_EN BIT(31)
3388#define B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN BIT(19)
3389#define B_AX_RMAC_RX_TIMEOUT_INT_EN BIT(18)
3390#define B_AX_RMAC_CSI_TIMEOUT_INT_EN BIT(17)
3391#define B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN BIT(16)
3392#define B_AX_RMAC_CCA_TIMEOUT_INT_EN BIT(15)
3393#define B_AX_RMAC_DMA_TIMEOUT_INT_EN BIT(14)
3394#define B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN BIT(13)
3395#define B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN BIT(12)
3396#define B_AX_RMAC_RX_CSI_TIMEOUT_FLAG BIT(7)
3397#define B_AX_RMAC_RX_TIMEOUT_FLAG BIT(6)
3398#define B_AX_BMAC_CSI_TIMEOUT_FLAG BIT(5)
3399#define B_AX_BMAC_DATA_ON_TIMEOUT_FLAG BIT(4)
3400#define B_AX_BMAC_CCA_TIMEOUT_FLAG BIT(3)
3401#define B_AX_BMAC_DMA_TIMEOUT_FLAG BIT(2)
3402#define B_AX_BMAC_DATA_ON_TO_IDLE_TIMEOUT_FLAG BIT(1)
3403#define B_AX_BMAC_CCA_TO_IDLE_TIMEOUT_FLAG BIT(0)
3404#define B_AX_RMAC_IMR_CLR (B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN | \
3405			   B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN | \
3406			   B_AX_RMAC_DMA_TIMEOUT_INT_EN | \
3407			   B_AX_RMAC_CCA_TIMEOUT_INT_EN | \
3408			   B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN | \
3409			   B_AX_RMAC_CSI_TIMEOUT_INT_EN | \
3410			   B_AX_RMAC_RX_TIMEOUT_INT_EN | \
3411			   B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN)
3412#define B_AX_RMAC_IMR_SET (B_AX_RMAC_DMA_TIMEOUT_INT_EN | \
3413			   B_AX_RMAC_CSI_TIMEOUT_INT_EN | \
3414			   B_AX_RMAC_RX_TIMEOUT_INT_EN | \
3415			   B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN)
3416
3417#define R_AX_RX_ERR_IMR 0xCEF8
3418#define R_AX_RX_ERR_IMR_C1 0xEEF8
3419#define B_AX_RX_ERR_TRIG_ACT_TO_MSK BIT(9)
3420#define B_AX_RX_ERR_STS_ACT_TO_MSK BIT(8)
3421#define B_AX_RX_ERR_CSI_ACT_TO_MSK BIT(7)
3422#define B_AX_RX_ERR_ACT_TO_MSK BIT(6)
3423#define B_AX_CSI_DATAON_ASSERT_TO_MSK BIT(5)
3424#define B_AX_DATAON_ASSERT_TO_MSK BIT(4)
3425#define B_AX_CCA_ASSERT_TO_MSK BIT(3)
3426#define B_AX_RX_ERR_DMA_TO_MSK BIT(2)
3427#define B_AX_RX_ERR_DATA_TO_MSK BIT(1)
3428#define B_AX_RX_ERR_CCA_TO_MSK BIT(0)
3429#define B_AX_RMAC_IMR_CLR_V1 (B_AX_RX_ERR_CCA_TO_MSK | \
3430			      B_AX_RX_ERR_DATA_TO_MSK | \
3431			      B_AX_RX_ERR_DMA_TO_MSK | \
3432			      B_AX_CCA_ASSERT_TO_MSK | \
3433			      B_AX_DATAON_ASSERT_TO_MSK | \
3434			      B_AX_CSI_DATAON_ASSERT_TO_MSK | \
3435			      B_AX_RX_ERR_ACT_TO_MSK | \
3436			      B_AX_RX_ERR_CSI_ACT_TO_MSK | \
3437			      B_AX_RX_ERR_STS_ACT_TO_MSK | \
3438			      B_AX_RX_ERR_TRIG_ACT_TO_MSK)
3439#define B_AX_RMAC_IMR_SET_V1 (B_AX_RX_ERR_CCA_TO_MSK | \
3440			      B_AX_RX_ERR_DATA_TO_MSK | \
3441			      B_AX_RX_ERR_DMA_TO_MSK | \
3442			      B_AX_CCA_ASSERT_TO_MSK | \
3443			      B_AX_DATAON_ASSERT_TO_MSK | \
3444			      B_AX_CSI_DATAON_ASSERT_TO_MSK | \
3445			      B_AX_RX_ERR_ACT_TO_MSK | \
3446			      B_AX_RX_ERR_CSI_ACT_TO_MSK | \
3447			      B_AX_RX_ERR_STS_ACT_TO_MSK | \
3448			      B_AX_RX_ERR_TRIG_ACT_TO_MSK)
3449
3450#define R_AX_RMAC_PLCP_MON 0xCEF8
3451#define R_AX_RMAC_PLCP_MON_C1 0xEEF8
3452#define B_AX_RMAC_PLCP_MON_MASK GENMASK(31, 0)
3453#define B_AX_PCLP_MON_SEL_MASK GENMASK(31, 28)
3454#define B_AX_PCLP_MON_CONT_MASK GENMASK(27, 0)
3455
3456#define R_AX_RX_DEBUG_SELECT 0xCEFC
3457#define R_AX_RX_DEBUG_SELECT_C1 0xEEFC
3458#define B_AX_DEBUG_SEL_MASK GENMASK(7, 0)
3459
3460#define R_AX_PWR_RATE_CTRL 0xD200
3461#define R_AX_PWR_RATE_CTRL_C1 0xF200
3462#define B_AX_PWR_REF GENMASK(27, 10)
3463#define B_AX_FORCE_PWR_BY_RATE_EN BIT(9)
3464#define B_AX_FORCE_PWR_BY_RATE_VALUE_MASK GENMASK(8, 0)
3465
3466#define R_AX_PWR_RATE_OFST_CTRL 0xD204
3467#define R_AX_PWR_COEXT_CTRL 0xD220
3468#define B_AX_TXAGC_BT_EN BIT(1)
3469#define B_AX_TXAGC_BT_MASK GENMASK(11, 3)
3470
3471#define R_AX_PWR_SWING_OTHER_CTRL0 0xD230
3472#define R_AX_PWR_SWING_OTHER_CTRL0_C1 0xF230
3473#define B_AX_CFIR_BY_RATE_OFF_MASK GENMASK(17, 0)
3474
3475#define R_AX_PWR_UL_CTRL0 0xD240
3476#define R_AX_PWR_UL_CTRL2 0xD248
3477#define B_AX_PWR_UL_CFO_MASK GENMASK(2, 0)
3478#define B_AX_PWR_UL_CTRL2_MASK 0x07700007
3479
3480#define R_AX_PWR_NORM_FORCE1 0xD260
3481#define R_AX_PWR_NORM_FORCE1_C1 0xF260
3482#define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_EN BIT(29)
3483#define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_MASK GENMASK(28, 24)
3484#define B_AX_FORCE_HE_ER_SU_EN_EN BIT(23)
3485#define B_AX_FORCE_HE_ER_SU_EN_VALUE BIT(22)
3486#define B_AX_FORCE_MACID_CCA_TH_EN_EN BIT(21)
3487#define B_AX_FORCE_MACID_CCA_TH_EN_VALUE BIT(20)
3488#define B_AX_FORCE_BT_GRANT_EN BIT(19)
3489#define B_AX_FORCE_BT_GRANT_VALUE BIT(18)
3490#define B_AX_FORCE_RX_LTE_EN BIT(17)
3491#define B_AX_FORCE_RX_LTE_VALUE BIT(16)
3492#define B_AX_FORCE_TXBF_EN_EN BIT(15)
3493#define B_AX_FORCE_TXBF_EN_VALUE BIT(14)
3494#define B_AX_FORCE_TXSC_EN BIT(13)
3495#define B_AX_FORCE_TXSC_VALUE_MASK GENMASK(12, 9)
3496#define B_AX_FORCE_NTX_EN BIT(6)
3497#define B_AX_FORCE_NTX_VALUE BIT(5)
3498#define B_AX_FORCE_PWR_MODE_EN BIT(3)
3499#define B_AX_FORCE_PWR_MODE_VALUE_MASK GENMASK(2, 0)
3500
3501#define R_AX_PWR_UL_TB_CTRL 0xD288
3502#define B_AX_PWR_UL_TB_CTRL_EN BIT(31)
3503#define R_AX_PWR_UL_TB_1T 0xD28C
3504#define B_AX_PWR_UL_TB_1T_MASK GENMASK(4, 0)
3505#define B_AX_PWR_UL_TB_1T_V1_MASK GENMASK(7, 0)
3506#define B_AX_PWR_UL_TB_1T_NORM_BW160 GENMASK(31, 24)
3507#define R_AX_PWR_UL_TB_2T 0xD290
3508#define B_AX_PWR_UL_TB_2T_MASK GENMASK(4, 0)
3509#define B_AX_PWR_UL_TB_2T_V1_MASK GENMASK(7, 0)
3510#define B_AX_PWR_UL_TB_2T_NORM_BW160 GENMASK(31, 24)
3511#define R_AX_PWR_BY_RATE_TABLE0 0xD2C0
3512#define R_AX_PWR_BY_RATE_TABLE6 0xD2D8
3513#define R_AX_PWR_BY_RATE_TABLE10 0xD2E8
3514#define R_AX_PWR_BY_RATE R_AX_PWR_BY_RATE_TABLE0
3515#define R_AX_PWR_BY_RATE_1SS_MAX R_AX_PWR_BY_RATE_TABLE6
3516#define R_AX_PWR_BY_RATE_MAX R_AX_PWR_BY_RATE_TABLE10
3517#define R_AX_PWR_LMT_TABLE0 0xD2EC
3518#define R_AX_PWR_LMT_TABLE9 0xD310
3519#define R_AX_PWR_LMT_TABLE19 0xD338
3520#define R_AX_PWR_LMT R_AX_PWR_LMT_TABLE0
3521#define R_AX_PWR_LMT_1SS_MAX R_AX_PWR_LMT_TABLE9
3522#define R_AX_PWR_LMT_MAX R_AX_PWR_LMT_TABLE19
3523#define R_AX_PWR_RU_LMT_TABLE0 0xD33C
3524#define R_AX_PWR_RU_LMT_TABLE5 0xD350
3525#define R_AX_PWR_RU_LMT_TABLE11 0xD368
3526#define R_AX_PWR_RU_LMT R_AX_PWR_RU_LMT_TABLE0
3527#define R_AX_PWR_RU_LMT_1SS_MAX R_AX_PWR_RU_LMT_TABLE5
3528#define R_AX_PWR_RU_LMT_MAX R_AX_PWR_RU_LMT_TABLE11
3529#define R_AX_PWR_MACID_LMT_TABLE0 0xD36C
3530#define R_AX_PWR_MACID_LMT_TABLE127 0xD568
3531
3532#define R_AX_PATH_COM0 0xD800
3533#define AX_PATH_COM0_DFVAL 0x00000000
3534#define AX_PATH_COM0_PATHA 0x08889880
3535#define AX_PATH_COM0_PATHB 0x11111900
3536#define AX_PATH_COM0_PATHAB 0x19999980
3537#define R_AX_PATH_COM1 0xD804
3538#define B_AX_PATH_COM1_NORM_1STS GENMASK(31, 28)
3539#define AX_PATH_COM1_DFVAL 0x00000000
3540#define AX_PATH_COM1_PATHA 0x13111111
3541#define AX_PATH_COM1_PATHB 0x23222222
3542#define AX_PATH_COM1_PATHAB 0x33333333
3543#define R_AX_PATH_COM2 0xD808
3544#define B_AX_PATH_COM2_RESP_1STS_PATH GENMASK(7, 4)
3545#define AX_PATH_COM2_DFVAL 0x00000000
3546#define AX_PATH_COM2_PATHA 0x01209313
3547#define AX_PATH_COM2_PATHB 0x01209323
3548#define AX_PATH_COM2_PATHAB 0x01209333
3549#define R_AX_PATH_COM3 0xD80C
3550#define AX_PATH_COM3_DFVAL 0x49249249
3551#define R_AX_PATH_COM4 0xD810
3552#define AX_PATH_COM4_DFVAL 0x1C9C9C49
3553#define R_AX_PATH_COM5 0xD814
3554#define AX_PATH_COM5_DFVAL 0x39393939
3555#define R_AX_PATH_COM6 0xD818
3556#define AX_PATH_COM6_DFVAL 0x39393939
3557#define R_AX_PATH_COM7 0xD81C
3558#define AX_PATH_COM7_DFVAL 0x39393939
3559#define AX_PATH_COM7_PATHA 0x39393939
3560#define AX_PATH_COM7_PATHB 0x39383939
3561#define AX_PATH_COM7_PATHAB 0x39393939
3562#define R_AX_PATH_COM8 0xD820
3563#define AX_PATH_COM8_DFVAL 0x00000000
3564#define AX_PATH_COM8_PATHA 0x00003939
3565#define AX_PATH_COM8_PATHB 0x00003938
3566#define AX_PATH_COM8_PATHAB 0x00003939
3567#define R_AX_PATH_COM9 0xD824
3568#define AX_PATH_COM9_DFVAL 0x000007C0
3569#define R_AX_PATH_COM10 0xD828
3570#define AX_PATH_COM10_DFVAL 0xE0000000
3571#define R_AX_PATH_COM11 0xD82C
3572#define AX_PATH_COM11_DFVAL 0x00000000
3573#define R_P80_AT_HIGH_FREQ_BB_WRP 0xD848
3574#define B_P80_AT_HIGH_FREQ_BB_WRP BIT(28)
3575#define R_AX_TSSI_CTRL_HEAD 0xD908
3576#define R_AX_BANDEDGE_CFG 0xD94C
3577#define B_AX_BANDEDGE_CFG_IDX_MASK GENMASK(31, 30)
3578#define R_AX_TSSI_CTRL_TAIL 0xD95C
3579
3580#define R_AX_TXPWR_IMR 0xD9E0
3581#define R_AX_TXPWR_IMR_C1 0xF9E0
3582#define R_AX_TXPWR_ISR 0xD9E4
3583#define R_AX_TXPWR_ISR_C1 0xF9E4
3584
3585#define R_AX_BTC_CFG 0xDA00
3586#define B_AX_BTC_EN BIT(31)
3587#define B_AX_EN_EXT_BT_PINMUX BIT(29)
3588#define B_AX_BTC_RST BIT(28)
3589#define B_AX_BTC_DBG_SRC_SEL BIT(27)
3590#define B_AX_BTC_MODE_MASK GENMASK(25, 24)
3591#define B_AX_INV_WL_ACT2 BIT(17)
3592#define B_AX_BTG_LNA1_GAIN_SEL BIT(16)
3593#define B_AX_COEX_DLY_CLK_MASK GENMASK(15, 8)
3594#define B_AX_IGN_GNT_BT2_RX BIT(7)
3595#define B_AX_IGN_GNT_BT2_TX BIT(6)
3596#define B_AX_IGN_GNT_BT2 BIT(5)
3597#define B_AX_BTC_DBG_SEL_MASK GENMASK(4, 3)
3598#define B_AX_DIS_BTC_CLK_G BIT(2)
3599#define B_AX_GNT_WL_RX_CTRL BIT(1)
3600#define B_AX_WL_SRC BIT(0)
3601
3602#define R_AX_RTK_MODE_CFG_V1 0xDA04
3603#define R_AX_RTK_MODE_CFG_V1_C1 0xFA04
3604#define B_AX_BT_BLE_EN_V1 BIT(24)
3605#define B_AX_BT_ULTRA_EN BIT(16)
3606#define B_AX_BT_L_RX_ULTRA_MASK GENMASK(15, 14)
3607#define B_AX_BT_L_TX_ULTRA_MASK GENMASK(13, 12)
3608#define B_AX_BT_H_RX_ULTRA_MASK GENMASK(11, 10)
3609#define B_AX_BT_H_TX_ULTRA_MASK GENMASK(9, 8)
3610#define B_AX_SAMPLE_CLK_MASK GENMASK(7, 0)
3611
3612#define R_AX_WL_PRI_MSK 0xDA10
3613#define B_AX_PTA_WL_PRI_MASK_BCNQ BIT(8)
3614
3615#define R_AX_BT_CNT_CFG 0xDA10
3616#define R_AX_BT_CNT_CFG_C1 0xFA10
3617#define B_AX_BT_CNT_RST_V1 BIT(1)
3618#define B_AX_BT_CNT_EN BIT(0)
3619
3620#define R_BTC_BT_CNT_HIGH 0xDA14
3621#define R_BTC_BT_CNT_LOW 0xDA18
3622
3623#define R_AX_BTC_FUNC_EN 0xDA20
3624#define R_AX_BTC_FUNC_EN_C1 0xFA20
3625#define B_AX_PTA_WL_TX_EN BIT(1)
3626#define B_AX_PTA_EDCCA_EN BIT(0)
3627
3628#define R_BTC_COEX_WL_REQ 0xDA24
3629#define R_BTC_COEX_WL_REQ_BE 0xE324
3630#define B_BTC_TX_NULL_HI BIT(23)
3631#define B_BTC_TX_BCN_HI BIT(22)
3632#define B_BTC_TX_TRI_HI BIT(17)
3633#define B_BTC_RSP_ACK_HI BIT(10)
3634#define B_BTC_PRI_MASK_TX_TIME GENMASK(4, 3)
3635#define B_BTC_PRI_MASK_RX_TIME_V1 GENMASK(2, 1)
3636
3637#define R_BTC_BREAK_TABLE 0xDA2C
3638#define BTC_BREAK_PARAM 0xf0ffffff
3639
3640#define R_BTC_BT_COEX_MSK_TABLE 0xDA30
3641#define B_BTC_PRI_MASK_RXCCK_V1 BIT(28)
3642#define B_BTC_PRI_MASK_TX_RESP_V1 BIT(3)
3643
3644#define R_AX_BT_COEX_CFG_2 0xDA34
3645#define R_AX_BT_COEX_CFG_2_C1 0xFA34
3646#define B_AX_GNT_BT_BYPASS_PRIORITY BIT(12)
3647#define B_AX_GNT_BT_POLARITY BIT(8)
3648#define B_AX_TIMER_MASK GENMASK(7, 0)
3649#define MAC_AX_CSR_RATE 80
3650
3651#define R_AX_CSR_MODE 0xDA40
3652#define R_AX_CSR_MODE_C1 0xFA40
3653#define B_AX_BT_CNT_RST BIT(16)
3654#define B_AX_BT_STAT_DELAY_MASK GENMASK(15, 12)
3655#define MAC_AX_CSR_DELAY 0
3656#define B_AX_BT_TRX_INIT_DETECT_MASK GENMASK(11, 8)
3657#define MAC_AX_CSR_TRX_TO 4
3658#define B_AX_BT_PRI_DETECT_TO_MASK GENMASK(7, 4)
3659#define MAC_AX_CSR_PRI_TO 5
3660#define B_AX_WL_ACT_MSK BIT(3)
3661#define B_AX_STATIS_BT_EN BIT(2)
3662#define B_AX_WL_ACT_MASK_ENABLE BIT(1)
3663#define B_AX_ENHANCED_BT BIT(0)
3664
3665#define R_AX_BT_BREAK_TABLE 0xDA44
3666
3667#define R_AX_BT_STAST_HIGH 0xDA44
3668#define B_AX_STATIS_BT_HI_RX_MASK GENMASK(31, 16)
3669#define B_AX_STATIS_BT_HI_TX_MASK GENMASK(15, 0)
3670#define R_AX_BT_STAST_LOW 0xDA48
3671#define B_AX_STATIS_BT_LO_TX_1_MASK GENMASK(15, 0)
3672#define B_AX_STATIS_BT_LO_RX_1_MASK GENMASK(31, 16)
3673
3674#define R_AX_GNT_SW_CTRL 0xDA48
3675#define R_AX_GNT_SW_CTRL_C1 0xFA48
3676#define B_AX_WL_ACT2_VAL BIT(21)
3677#define B_AX_WL_ACT2_SWCTRL BIT(20)
3678#define B_AX_WL_ACT_VAL BIT(19)
3679#define B_AX_WL_ACT_SWCTRL BIT(18)
3680#define B_AX_GNT_BT_RX_VAL BIT(17)
3681#define B_AX_GNT_BT_RX_SWCTRL BIT(16)
3682#define B_AX_GNT_BT_TX_VAL BIT(15)
3683#define B_AX_GNT_BT_TX_SWCTRL BIT(14)
3684#define B_AX_GNT_WL_RX_VAL BIT(13)
3685#define B_AX_GNT_WL_RX_SWCTRL BIT(12)
3686#define B_AX_GNT_WL_TX_VAL BIT(11)
3687#define B_AX_GNT_WL_TX_SWCTRL BIT(10)
3688#define B_AX_GNT_BT_RFC_S1_VAL BIT(9)
3689#define B_AX_GNT_BT_RFC_S1_SWCTRL BIT(8)
3690#define B_AX_GNT_WL_RFC_S1_VAL BIT(7)
3691#define B_AX_GNT_WL_RFC_S1_SWCTRL BIT(6)
3692#define B_AX_GNT_BT_RFC_S0_VAL BIT(5)
3693#define B_AX_GNT_BT_RFC_S0_SWCTRL BIT(4)
3694#define B_AX_GNT_WL_RFC_S0_VAL BIT(3)
3695#define B_AX_GNT_WL_RFC_S0_SWCTRL BIT(2)
3696#define B_AX_GNT_WL_BB_VAL BIT(1)
3697#define B_AX_GNT_WL_BB_SWCTRL BIT(0)
3698
3699#define R_AX_GNT_VAL 0x0054
3700#define B_AX_GNT_BT_RFC_S1_STA BIT(5)
3701#define B_AX_GNT_WL_RFC_S1_STA BIT(4)
3702#define B_AX_GNT_BT_RFC_S0_STA BIT(3)
3703#define B_AX_GNT_WL_RFC_S0_STA BIT(2)
3704
3705#define R_AX_GNT_VAL_V1 0xDA4C
3706#define B_AX_GNT_BT_RFC_S1 BIT(4)
3707#define B_AX_GNT_BT_RFC_S0 BIT(3)
3708#define B_AX_GNT_WL_RFC_S1 BIT(2)
3709#define B_AX_GNT_WL_RFC_S0 BIT(1)
3710
3711#define R_AX_TDMA_MODE 0xDA4C
3712#define R_AX_TDMA_MODE_C1 0xFA4C
3713#define B_AX_R_BT_CMD_RPT_MASK GENMASK(31, 16)
3714#define B_AX_R_RPT_FROM_BT_MASK GENMASK(15, 8)
3715#define B_AX_BT_HID_ISR_SET_MASK GENMASK(7, 6)
3716#define B_AX_TDMA_BT_START_NOTIFY BIT(5)
3717#define B_AX_ENABLE_TDMA_FW_MODE BIT(4)
3718#define B_AX_ENABLE_PTA_TDMA_MODE BIT(3)
3719#define B_AX_ENABLE_COEXIST_TAB_IN_TDMA BIT(2)
3720#define B_AX_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1)
3721#define B_AX_RTK_BT_ENABLE BIT(0)
3722
3723#define R_AX_BT_COEX_CFG_5 0xDA6C
3724#define R_AX_BT_COEX_CFG_5_C1 0xFA6C
3725#define B_AX_BT_TIME_MASK GENMASK(31, 6)
3726#define B_AX_BT_RPT_SAMPLE_RATE_MASK GENMASK(5, 0)
3727#define MAC_AX_RTK_RATE 5
3728
3729#define R_AX_LTE_CTRL 0xDAF0
3730#define R_AX_LTE_WDATA 0xDAF4
3731#define R_AX_LTE_RDATA 0xDAF8
3732
3733#define R_AX_MACID_ANT_TABLE 0xDC00
3734#define R_AX_MACID_ANT_TABLE_LAST 0xDDFC
3735
3736#define CMAC1_START_ADDR_AX 0xE000
3737#define CMAC1_END_ADDR_AX 0xFFFF
3738#define R_AX_CMAC_REG_END 0xFFFF
3739
3740#define R_AX_LTE_SW_CFG_1 0x0038
3741#define R_AX_LTE_SW_CFG_1_C1 0x2038
3742#define B_AX_GNT_BT_RFC_S1_SW_VAL BIT(31)
3743#define B_AX_GNT_BT_RFC_S1_SW_CTRL BIT(30)
3744#define B_AX_GNT_WL_RFC_S1_SW_VAL BIT(29)
3745#define B_AX_GNT_WL_RFC_S1_SW_CTRL BIT(28)
3746#define B_AX_GNT_BT_BB_S1_SW_VAL BIT(27)
3747#define B_AX_GNT_BT_BB_S1_SW_CTRL BIT(26)
3748#define B_AX_GNT_WL_BB_S1_SW_VAL BIT(25)
3749#define B_AX_GNT_WL_BB_S1_SW_CTRL BIT(24)
3750#define B_AX_BT_SW_CTRL_WL_PRIORITY BIT(19)
3751#define B_AX_WL_SW_CTRL_WL_PRIORITY BIT(18)
3752#define B_AX_LTE_PATTERN_2_EN BIT(17)
3753#define B_AX_LTE_PATTERN_1_EN BIT(16)
3754#define B_AX_GNT_BT_RFC_S0_SW_VAL BIT(15)
3755#define B_AX_GNT_BT_RFC_S0_SW_CTRL BIT(14)
3756#define B_AX_GNT_WL_RFC_S0_SW_VAL BIT(13)
3757#define B_AX_GNT_WL_RFC_S0_SW_CTRL BIT(12)
3758#define B_AX_GNT_BT_BB_S0_SW_VAL BIT(11)
3759#define B_AX_GNT_BT_BB_S0_SW_CTRL BIT(10)
3760#define B_AX_GNT_WL_BB_S0_SW_VAL BIT(9)
3761#define B_AX_GNT_WL_BB_S0_SW_CTRL BIT(8)
3762#define B_AX_LTECOEX_FUN_EN BIT(7)
3763#define B_AX_LTECOEX_3WIRE_CTRL_MUX BIT(6)
3764#define B_AX_LTECOEX_OP_MODE_SEL_MASK GENMASK(5, 4)
3765#define B_AX_LTECOEX_UART_MUX BIT(3)
3766#define B_AX_LTECOEX_UART_MODE_SEL_MASK GENMASK(2, 0)
3767
3768#define R_AX_LTE_SW_CFG_2 0x003C
3769#define R_AX_LTE_SW_CFG_2_C1 0x203C
3770#define B_AX_WL_RX_CTRL BIT(8)
3771#define B_AX_GNT_WL_RX_SW_VAL BIT(7)
3772#define B_AX_GNT_WL_RX_SW_CTRL BIT(6)
3773#define B_AX_GNT_WL_TX_SW_VAL BIT(5)
3774#define B_AX_GNT_WL_TX_SW_CTRL BIT(4)
3775#define B_AX_GNT_BT_RX_SW_VAL BIT(3)
3776#define B_AX_GNT_BT_RX_SW_CTRL BIT(2)
3777#define B_AX_GNT_BT_TX_SW_VAL BIT(1)
3778#define B_AX_GNT_BT_TX_SW_CTRL BIT(0)
3779
3780#define R_BE_SYS_ISO_CTRL 0x0000
3781#define B_BE_PWC_EV2EF_B BIT(15)
3782#define B_BE_PWC_EV2EF_S BIT(14)
3783#define B_BE_PA33V_EN BIT(13)
3784#define B_BE_PA12V_EN BIT(12)
3785#define B_BE_PAOOBS33V_EN BIT(11)
3786#define B_BE_PAOOBS12V_EN BIT(10)
3787#define B_BE_ISO_RFDIO BIT(9)
3788#define B_BE_ISO_EB2CORE BIT(8)
3789#define B_BE_ISO_DIOE BIT(7)
3790#define B_BE_ISO_WLPON2PP BIT(6)
3791#define B_BE_ISO_IP2MAC_WA02PP BIT(5)
3792#define B_BE_ISO_PD2CORE BIT(4)
3793#define B_BE_ISO_PA2PCIE BIT(3)
3794#define B_BE_ISO_PAOOBS2PCIE BIT(1)
3795#define B_BE_ISO_WD2PP BIT(0)
3796
3797#define R_BE_SYS_PW_CTRL 0x0004
3798#define B_BE_SOP_ASWRM BIT(31)
3799#define B_BE_SOP_EASWR BIT(30)
3800#define B_BE_SOP_PWMM_DSWR BIT(29)
3801#define B_BE_SOP_EDSWR BIT(28)
3802#define B_BE_SOP_ACKF BIT(27)
3803#define B_BE_SOP_ERCK BIT(26)
3804#define B_BE_SOP_ANA_CLK_DIVISION_2 BIT(25)
3805#define B_BE_SOP_EXTL BIT(24)
3806#define B_BE_SOP_OFF_CAPC_EN BIT(23)
3807#define B_BE_XTAL_OFF_A_DIE BIT(22)
3808#define B_BE_ROP_SWPR BIT(21)
3809#define B_BE_DIS_HW_LPLDM BIT(20)
3810#define B_BE_DIS_HW_LPURLDO BIT(19)
3811#define B_BE_DIS_WLBT_PDNSUSEN_SOPC BIT(18)
3812#define B_BE_RDY_SYSPWR BIT(17)
3813#define B_BE_EN_WLON BIT(16)
3814#define B_BE_APDM_HPDN BIT(15)
3815#define B_BE_PSUS_OFF_CAPC_EN BIT(14)
3816#define B_BE_AFSM_PCIE_SUS_EN BIT(12)
3817#define B_BE_AFSM_WLSUS_EN BIT(11)
3818#define B_BE_APFM_SWLPS BIT(10)
3819#define B_BE_APFM_OFFMAC BIT(9)
3820#define B_BE_APFN_ONMAC BIT(8)
3821#define B_BE_CHIP_PDN_EN BIT(7)
3822#define B_BE_RDY_MACDIS BIT(6)
3823
3824#define R_BE_SYS_CLK_CTRL 0x0008
3825#define B_BE_CPU_CLK_EN BIT(14)
3826#define B_BE_SYMR_BE_CLK_EN BIT(13)
3827#define B_BE_MAC_CLK_EN BIT(11)
3828#define B_BE_EXT_32K_EN BIT(8)
3829#define B_BE_WL_CLK_TEST BIT(7)
3830#define B_BE_LOADER_CLK_EN BIT(5)
3831#define B_BE_ANA_CLK_DIVISION_2 BIT(1)
3832#define B_BE_CNTD16V_EN BIT(0)
3833
3834#define R_BE_SYS_WL_EFUSE_CTRL 0x000A
3835#define B_BE_OTP_B_PWC_RPT BIT(15)
3836#define B_BE_OTP_S_PWC_RPT BIT(14)
3837#define B_BE_OTP_ISO_RPT BIT(13)
3838#define B_BE_OTP_BURST_RPT BIT(12)
3839#define B_BE_OTP_AUTOLOAD_RPT BIT(11)
3840#define B_BE_AUTOLOAD_DIS_A_DIE BIT(6)
3841#define B_BE_AUTOLOAD_SUS BIT(5)
3842#define B_BE_AUTOLOAD_DIS BIT(4)
3843
3844#define R_BE_SYS_PAGE_CLK_GATED 0x000C
3845#define B_BE_USB_APHY_PC_DLP_OP BIT(27)
3846#define B_BE_PCIE_APHY_PC_DLP_OP BIT(26)
3847#define B_BE_UPHY_POWER_READY_CHK BIT(25)
3848#define B_BE_CPHY_POWER_READY_CHK BIT(24)
3849#define B_BE_PCIE_PRST_DEBUNC_PERIOD_MASK GENMASK(23, 22)
3850#define B_BE_SYM_PRST_DEBUNC_SEL BIT(21)
3851#define B_BE_CPHY_AUXCLK_OP BIT(20)
3852#define B_BE_SOP_OFFUA_PC BIT(19)
3853#define B_BE_SOP_OFFPOOBS_PC BIT(18)
3854#define B_BE_PCIE_LAN1_MASK BIT(17)
3855#define B_BE_PCIE_LAN0_MASK BIT(16)
3856#define B_BE_DIS_CLK_REGF_GATE BIT(15)
3857#define B_BE_DIS_CLK_REGE_GATE BIT(14)
3858#define B_BE_DIS_CLK_REGD_GATE BIT(13)
3859#define B_BE_DIS_CLK_REGC_GATE BIT(12)
3860#define B_BE_DIS_CLK_REGB_GATE BIT(11)
3861#define B_BE_DIS_CLK_REGA_GATE BIT(10)
3862#define B_BE_DIS_CLK_REG9_GATE BIT(9)
3863#define B_BE_DIS_CLK_REG8_GATE BIT(8)
3864#define B_BE_DIS_CLK_REG7_GATE BIT(7)
3865#define B_BE_DIS_CLK_REG6_GATE BIT(6)
3866#define B_BE_DIS_CLK_REG5_GATE BIT(5)
3867#define B_BE_DIS_CLK_REG4_GATE BIT(4)
3868#define B_BE_DIS_CLK_REG3_GATE BIT(3)
3869#define B_BE_DIS_CLK_REG2_GATE BIT(2)
3870#define B_BE_DIS_CLK_REG1_GATE BIT(1)
3871#define B_BE_DIS_CLK_REG0_GATE BIT(0)
3872
3873#define R_BE_ANAPAR_POW_MAC 0x0016
3874#define B_BE_POW_PC_LDO_PORT1 BIT(3)
3875#define B_BE_POW_PC_LDO_PORT0 BIT(2)
3876#define B_BE_POW_PLL_V1 BIT(1)
3877#define B_BE_POW_POWER_CUT_POW_LDO BIT(0)
3878
3879#define R_BE_SYS_ADIE_PAD_PWR_CTRL 0x0018
3880#define B_BE_SYM_PADPDN_WL_RFC1_1P3 BIT(6)
3881#define B_BE_SYM_PADPDN_WL_RFC0_1P3 BIT(5)
3882
3883#define R_BE_RSV_CTRL 0x001C
3884#define B_BE_HR_BE_DBG GENMASK(23, 12)
3885#define B_BE_R_SYM_DIS_PCIE_FLR BIT(9)
3886#define B_BE_R_EN_HRST_PWRON BIT(8)
3887#define B_BE_LOCK_ALL_EN BIT(7)
3888#define B_BE_R_DIS_PRST BIT(6)
3889#define B_BE_WLOCK_1C_BIT6 BIT(5)
3890#define B_BE_WLOCK_40 BIT(4)
3891#define B_BE_WLOCK_08 BIT(3)
3892#define B_BE_WLOCK_04 BIT(2)
3893#define B_BE_WLOCK_00 BIT(1)
3894#define B_BE_WLOCK_ALL BIT(0)
3895
3896#define R_BE_AFE_LDO_CTRL 0x0020
3897#define B_BE_FORCE_MACBBBT_PWR_ON BIT(31)
3898#define B_BE_R_SYM_WLPOFF_P4_PC_EN BIT(28)
3899#define B_BE_R_SYM_WLPOFF_P3_PC_EN BIT(27)
3900#define B_BE_R_SYM_WLPOFF_P2_PC_EN BIT(26)
3901#define B_BE_R_SYM_WLPOFF_P1_PC_EN BIT(25)
3902#define B_BE_R_SYM_WLPOFF_PC_EN BIT(24)
3903#define B_BE_AON_OFF_PC_EN BIT(23)
3904#define B_BE_R_SYM_WLPON_P3_PC_EN BIT(21)
3905#define B_BE_R_SYM_WLPON_P2_PC_EN BIT(20)
3906#define B_BE_R_SYM_WLPON_P1_PC_EN BIT(19)
3907#define B_BE_R_SYM_WLPON_PC_EN BIT(18)
3908#define B_BE_R_SYM_WLBBPON1_P1_PC_EN BIT(15)
3909#define B_BE_R_SYM_WLBBPON1_PC_EN BIT(14)
3910#define B_BE_R_SYM_WLBBPON_P1_PC_EN BIT(13)
3911#define B_BE_R_SYM_WLBBPON_PC_EN BIT(12)
3912#define B_BE_R_SYM_DIS_WPHYBBOFF_PC BIT(10)
3913#define B_BE_R_SYM_WLBBOFF1_P4_PC_EN BIT(9)
3914#define B_BE_R_SYM_WLBBOFF1_P3_PC_EN BIT(8)
3915#define B_BE_R_SYM_WLBBOFF1_P2_PC_EN BIT(7)
3916#define B_BE_R_SYM_WLBBOFF1_P1_PC_EN BIT(6)
3917#define B_BE_R_SYM_WLBBOFF1_PC_EN BIT(5)
3918#define B_BE_R_SYM_WLBBOFF_P4_PC_EN BIT(4)
3919#define B_BE_R_SYM_WLBBOFF_P3_PC_EN BIT(3)
3920#define B_BE_R_SYM_WLBBOFF_P2_PC_EN BIT(2)
3921#define B_BE_R_SYM_WLBBOFF_P1_PC_EN BIT(1)
3922#define B_BE_R_SYM_WLBBOFF_PC_EN BIT(0)
3923
3924#define R_BE_AFE_CTRL1 0x0024
3925#define B_BE_R_SYM_WLCMAC0_P4_PC_EN BIT(28)
3926#define B_BE_R_SYM_WLCMAC0_P3_PC_EN BIT(27)
3927#define B_BE_R_SYM_WLCMAC0_P2_PC_EN BIT(26)
3928#define B_BE_R_SYM_WLCMAC0_P1_PC_EN BIT(25)
3929#define B_BE_R_SYM_WLCMAC0_PC_EN BIT(24)
3930#define B_BE_DATAMEM_PC3_EN BIT(23)
3931#define B_BE_DATAMEM_PC2_EN BIT(22)
3932#define B_BE_DATAMEM_PC1_EN BIT(21)
3933#define B_BE_DATAMEM_PC_EN BIT(20)
3934#define B_BE_DMEM7_PC_EN BIT(19)
3935#define B_BE_DMEM6_PC_EN BIT(18)
3936#define B_BE_DMEM5_PC_EN BIT(17)
3937#define B_BE_DMEM4_PC_EN BIT(16)
3938#define B_BE_DMEM3_PC_EN BIT(15)
3939#define B_BE_DMEM2_PC_EN BIT(14)
3940#define B_BE_DMEM1_PC_EN BIT(13)
3941#define B_BE_IMEM4_PC_EN BIT(12)
3942#define B_BE_IMEM3_PC_EN BIT(11)
3943#define B_BE_IMEM2_PC_EN BIT(10)
3944#define B_BE_IMEM1_PC_EN BIT(9)
3945#define B_BE_IMEM0_PC_EN BIT(8)
3946#define B_BE_R_SYM_WLCMAC1_P4_PC_EN BIT(4)
3947#define B_BE_R_SYM_WLCMAC1_P3_PC_EN BIT(3)
3948#define B_BE_R_SYM_WLCMAC1_P2_PC_EN BIT(2)
3949#define B_BE_R_SYM_WLCMAC1_P1_PC_EN BIT(1)
3950#define B_BE_R_SYM_WLCMAC1_PC_EN BIT(0)
3951#define B_BE_AFE_CTRL1_SET (B_BE_R_SYM_WLCMAC1_PC_EN | \
3952			    B_BE_R_SYM_WLCMAC1_P1_PC_EN | \
3953			    B_BE_R_SYM_WLCMAC1_P2_PC_EN | \
3954			    B_BE_R_SYM_WLCMAC1_P3_PC_EN | \
3955			    B_BE_R_SYM_WLCMAC1_P4_PC_EN)
3956
3957#define R_BE_EFUSE_CTRL 0x0030
3958#define B_BE_EF_MODE_SEL_MASK GENMASK(31, 30)
3959#define B_BE_EF_RDY BIT(29)
3960#define B_BE_EF_COMP_RESULT BIT(28)
3961#define B_BE_EF_ADDR_MASK GENMASK(15, 0)
3962
3963#define R_BE_EFUSE_CTRL_1_V1 0x0034
3964#define B_BE_EF_DATA_MASK GENMASK(31, 0)
3965
3966#define R_BE_GPIO_MUXCFG 0x0040
3967#define B_BE_WCPU_AUTO_EN BIT(26)
3968#define B_BE_WCPU_JTAG_EN BIT(24)
3969#define B_BE_WCPU_DBG_EN BIT(23)
3970#define B_BE_JTAG_CHAIN_EN BIT(20)
3971#define B_BE_BOOT_MODE BIT(19)
3972#define B_BE_WL_EECS_EXT_32K_SEL BIT(18)
3973#define B_BE_WL_SEC_BONDING_OPT_STS BIT(17)
3974#define B_BE_SECSIC_SEL BIT(16)
3975#define B_BE_ENHTP BIT(14)
3976#define B_BE_ENSIC BIT(12)
3977#define B_BE_SIC_SWRST BIT(11)
3978#define B_BE_PINMUX_PTA_EN BIT(10)
3979#define B_BE_WL_BT_PTA_SEC BIT(9)
3980#define B_BE_ENUARTTX BIT(8)
3981#define B_BE_DBG_GNT_BT_S1_POLARITY BIT(4)
3982#define B_BE_ENUARTRX BIT(2)
3983
3984#define R_BE_GPIO_EXT_CTRL 0x0060
3985#define B_BE_GPIO_MOD_15_TO_8_MASK GENMASK(31, 24)
3986#define B_BE_GPIO_MOD_9 BIT(25)
3987#define B_BE_GPIO_IO_SEL_15_TO_8_MASK GENMASK(23, 16)
3988#define B_BE_GPIO_IO_SEL_9 BIT(17)
3989#define B_BE_GPIO_OUT_15_TO_8_MASK GENMASK(15, 8)
3990#define B_BE_GPIO_IN_15_TO_8_MASK GENMASK(7, 0)
3991#define B_BE_GPIO_IN_9 BIT(1)
3992
3993#define R_BE_WL_BT_PWR_CTRL 0x0068
3994#define B_BE_ISO_BD2PP BIT(31)
3995#define B_BE_LDOV12B_EN BIT(30)
3996#define B_BE_CKEN_BT BIT(29)
3997#define B_BE_FEN_BT BIT(28)
3998#define B_BE_BTCPU_BOOTSEL BIT(27)
3999#define B_BE_SPI_SPEEDUP BIT(26)
4000#define B_BE_BT_LDO_MODE BIT(25)
4001#define B_BE_ISO_BTPON2PP BIT(22)
4002#define B_BE_BT_FUNC_EN BIT(18)
4003#define B_BE_BT_HWPDN_SL BIT(17)
4004#define B_BE_BT_DISN_EN BIT(16)
4005#define B_BE_SDM_SRC_SEL BIT(12)
4006#define B_BE_ISO_BA2PP BIT(11)
4007#define B_BE_BT_AFE_LDO_EN BIT(10)
4008#define B_BE_BT_AFE_PLL_EN BIT(9)
4009#define B_BE_WLAN_32K_SEL BIT(6)
4010#define B_BE_WL_DRV_EXIST_IDX BIT(5)
4011#define B_BE_DOP_EHPAD BIT(4)
4012#define B_BE_WL_FUNC_EN BIT(2)
4013#define B_BE_WL_HWPDN_SL BIT(1)
4014#define B_BE_WL_HWPDN_EN BIT(0)
4015
4016#define R_BE_SYS_SDIO_CTRL 0x0070
4017#define B_BE_MCM_FLASH_EN BIT(28)
4018#define B_BE_PCIE_SEC_LOAD BIT(26)
4019#define B_BE_PCIE_SER_RSTB BIT(25)
4020#define B_BE_PCIE_SEC_LOAD_CLR BIT(24)
4021#define B_BE_SDIO_CMD_SW_RST BIT(20)
4022#define B_BE_SDIO_INT_POLARITY BIT(19)
4023#define B_BE_SDIO_OFF_EN BIT(17)
4024#define B_BE_SDIO_ON_EN BIT(16)
4025#define B_BE_PCIE_DIS_L2__CTRL_LDO_HCI BIT(15)
4026#define B_BE_PCIE_DIS_L2_RTK_PERST BIT(14)
4027#define B_BE_PCIE_FORCE_PWR_NGAT BIT(13)
4028#define B_BE_PCIE_FORCE_IBX_EN BIT(12)
4029#define B_BE_PCIE_AUXCLK_GATE BIT(11)
4030#define B_BE_PCIE_WAIT_TIMEOUT_EVENT BIT(10)
4031#define B_BE_PCIE_WAIT_TIME BIT(9)
4032#define B_BE_L1OFF_TO_L0_RESUME_EVT BIT(8)
4033#define B_BE_USBA_FORCE_PWR_NGAT BIT(7)
4034#define B_BE_USBD_FORCE_PWR_NGAT BIT(6)
4035#define B_BE_BT_CTRL_USB_PWR BIT(5)
4036#define B_BE_USB_D_STATE_HOLD BIT(4)
4037#define B_BE_R_BE_FORCE_DP BIT(3)
4038#define B_BE_R_BE_DP_MODE BIT(2)
4039#define B_BE_RES_USB_MASS_STORAGE_DESC BIT(1)
4040#define B_BE_USB_WAIT_TIME BIT(0)
4041
4042#define R_BE_HCI_OPT_CTRL 0x0074
4043#define B_BE_HCI_WLAN_IO_ST BIT(31)
4044#define B_BE_HCI_WLAN_IO_EN BIT(28)
4045#define B_BE_HAXIDMA_IO_ST BIT(27)
4046#define B_BE_HAXIDMA_BACKUP_RESTORE_ST BIT(26)
4047#define B_BE_HAXIDMA_IO_EN BIT(24)
4048#define B_BE_EN_PCIE_WAKE BIT(23)
4049#define B_BE_SDIO_PAD_H3L1 BIT(22)
4050#define B_BE_USBMAC_ANACLK_SW BIT(21)
4051#define B_BE_PCIE_CPHY_CCK_XTAL_SEL BIT(20)
4052#define B_BE_SDIO_DATA_PAD_SMT BIT(19)
4053#define B_BE_SDIO_PAD_E5 BIT(18)
4054#define B_BE_FORCE_PCIE_AUXCLK BIT(17)
4055#define B_BE_HCI_LA_ADDR_MAP BIT(16)
4056#define B_BE_HCI_LA_GLO_RST BIT(15)
4057#define B_BE_USB3_SUS_DIS BIT(14)
4058#define B_BE_NOPWR_CTRL_SEL BIT(13)
4059#define B_BE_USB_HOST_PWR_OFF_EN BIT(12)
4060#define B_BE_SYM_LPS_BLOCK_EN BIT(11)
4061#define B_BE_USB_LPM_ACT_EN BIT(10)
4062#define B_BE_USB_LPM_NY BIT(9)
4063#define B_BE_USB2_SUS_DIS BIT(8)
4064#define B_BE_SDIO_PAD_E_MASK GENMASK(7, 5)
4065#define B_BE_USB_LPPLL_EN BIT(4)
4066#define B_BE_USB1_1_USB2_0_DECISION BIT(3)
4067#define B_BE_ROP_SW15 BIT(2)
4068#define B_BE_PCI_CKRDY_OPT BIT(1)
4069#define B_BE_PCI_VAUX_EN BIT(0)
4070
4071#define R_BE_SYS_ISO_CTRL_EXTEND 0x0080
4072#define B_BE_R_SYM_ISO_DMEM62PP BIT(29)
4073#define B_BE_R_SYM_ISO_DMEM52PP BIT(28)
4074#define B_BE_R_SYM_ISO_DMEM42PP BIT(27)
4075#define B_BE_R_SYM_ISO_DMEM32PP BIT(26)
4076#define B_BE_R_SYM_ISO_DMEM22PP BIT(25)
4077#define B_BE_R_SYM_ISO_DMEM12PP BIT(24)
4078#define B_BE_R_SYM_ISO_IMEM42PP BIT(22)
4079#define B_BE_R_SYM_ISO_IMEM32PP BIT(21)
4080#define B_BE_R_SYM_ISO_IMEM22PP BIT(20)
4081#define B_BE_R_SYM_ISO_IMEM12PP BIT(19)
4082#define B_BE_R_SYM_ISO_IMEM02PP BIT(18)
4083#define B_BE_R_SYM_ISO_AON_OFF2PP BIT(15)
4084#define B_BE_R_SYM_PWC_HCILA BIT(13)
4085#define B_BE_R_SYM_PWC_PD12V BIT(12)
4086#define B_BE_R_SYM_PWC_UD12V BIT(11)
4087#define B_BE_R_SYM_PWC_BTBRG BIT(10)
4088#define B_BE_R_SYM_LDOBTSDIO_EN BIT(9)
4089#define B_BE_R_SYM_LDOSPDIO_EN BIT(8)
4090#define B_BE_R_SYM_ISO_HCILA BIT(4)
4091#define B_BE_R_SYM_ISO_BTBRG2PP BIT(2)
4092#define B_BE_R_SYM_ISO_BTSDIO2PP BIT(1)
4093#define B_BE_R_SYM_ISO_SPDIO2PP BIT(0)
4094
4095#define R_BE_FEN_RST_ENABLE 0x0084
4096#define B_BE_R_SYM_FEN_WLMACOFF BIT(31)
4097#define B_BE_R_SYM_ISO_WA12PP BIT(28)
4098#define B_BE_R_SYM_ISO_CMAC12PP BIT(25)
4099#define B_BE_R_SYM_ISO_CMAC02PP BIT(24)
4100#define B_BE_R_SYM_ISO_ADDA_P32PP BIT(23)
4101#define B_BE_R_SYM_ISO_ADDA_P22PP BIT(22)
4102#define B_BE_R_SYM_ISO_ADDA_P12PP BIT(21)
4103#define B_BE_R_SYM_ISO_ADDA_P02PP BIT(20)
4104#define B_BE_CMAC1_FEN BIT(17)
4105#define B_BE_CMAC0_FEN BIT(16)
4106#define B_BE_SYM_ISO_BBPON12PP BIT(13)
4107#define B_BE_SYM_ISO_BB12PP BIT(12)
4108#define B_BE_BOOT_RDY1 BIT(10)
4109#define B_BE_FEN_BB1_IP_RSTN BIT(9)
4110#define B_BE_FEN_BB1PLAT_RSTB BIT(8)
4111#define B_BE_SYM_ISO_BBPON02PP BIT(5)
4112#define B_BE_SYM_ISO_BB02PP BIT(4)
4113#define B_BE_BOOT_RDY0 BIT(2)
4114#define B_BE_FEN_BB_IP_RSTN BIT(1)
4115#define B_BE_FEN_BBPLAT_RSTB BIT(0)
4116
4117#define R_BE_PLATFORM_ENABLE 0x0088
4118#define B_BE_HOLD_AFTER_RESET BIT(11)
4119#define B_BE_SYM_WLPLT_MEM_MUX_EN BIT(10)
4120#define B_BE_WCPU_WARM_EN BIT(9)
4121#define B_BE_SPIC_EN BIT(8)
4122#define B_BE_UART_EN BIT(7)
4123#define B_BE_IDDMA_EN BIT(6)
4124#define B_BE_IPSEC_EN BIT(5)
4125#define B_BE_HIOE_EN BIT(4)
4126#define B_BE_APB_WRAP_EN BIT(2)
4127#define B_BE_WCPU_EN BIT(1)
4128#define B_BE_PLATFORM_EN BIT(0)
4129
4130#define R_BE_WLLPS_CTRL 0x0090
4131#define B_BE_LPSOP_BBMEMDS BIT(30)
4132#define B_BE_LPSOP_BBOFF BIT(29)
4133#define B_BE_LPSOP_MACOFF BIT(28)
4134#define B_BE_LPSOP_OFF_CAPC_EN BIT(27)
4135#define B_BE_LPSOP_MEM_DS BIT(26)
4136#define B_BE_LPSOP_XTALM_LPS BIT(23)
4137#define B_BE_LPSOP_XTAL BIT(22)
4138#define B_BE_LPSOP_ACLK_DIV_2 BIT(21)
4139#define B_BE_LPSOP_ACLK_SEL BIT(20)
4140#define B_BE_LPSOP_ASWRM BIT(17)
4141#define B_BE_LPSOP_ASWR BIT(16)
4142#define B_BE_LPSOP_DSWR_ADJ_MASK GENMASK(15, 12)
4143#define B_BE_LPSOP_DSWRSD BIT(10)
4144#define B_BE_LPSOP_DSWRM BIT(9)
4145#define B_BE_LPSOP_DSWR BIT(8)
4146#define B_BE_LPSOP_OLD_ADJ_MASK GENMASK(7, 4)
4147#define B_BE_FORCE_LEAVE_LPS BIT(3)
4148#define B_BE_LPSOP_OLDSD BIT(2)
4149#define B_BE_DIS_WLBT_LPSEN_LOPC BIT(1)
4150#define B_BE_WL_LPS_EN BIT(0)
4151
4152#define R_BE_WLRESUME_CTRL 0x0094
4153#define B_BE_LPSROP_DMEM5_RSU_EN BIT(31)
4154#define B_BE_LPSROP_DMEM4_RSU_EN BIT(30)
4155#define B_BE_LPSROP_DMEM3_RSU_EN BIT(29)
4156#define B_BE_LPSROP_DMEM2_RSU_EN BIT(28)
4157#define B_BE_LPSROP_DMEM1_RSU_EN BIT(27)
4158#define B_BE_LPSROP_DMEM0_RSU_EN BIT(26)
4159#define B_BE_LPSROP_IMEM5_RSU_EN BIT(25)
4160#define B_BE_LPSROP_IMEM4_RSU_EN BIT(24)
4161#define B_BE_LPSROP_IMEM3_RSU_EN BIT(23)
4162#define B_BE_LPSROP_IMEM2_RSU_EN BIT(22)
4163#define B_BE_LPSROP_IMEM1_RSU_EN BIT(21)
4164#define B_BE_LPSROP_IMEM0_RSU_EN BIT(20)
4165#define B_BE_LPSROP_BB1_W_BB0 BIT(14)
4166#define B_BE_LPSROP_CMAC1 BIT(13)
4167#define B_BE_LPSROP_CMAC0 BIT(12)
4168#define B_BE_LPSROP_XTALM BIT(11)
4169#define B_BE_LPSROP_PLLM BIT(10)
4170#define B_BE_LPSROP_HIOE BIT(9)
4171#define B_BE_LPSROP_CPU BIT(8)
4172#define B_BE_LPSROP_LOWPWRPLL BIT(7)
4173#define B_BE_LPSROP_DSWRSD_SEL_MASK GENMASK(5, 4)
4174
4175#define R_BE_EFUSE_CTRL_2_V1 0x00A4
4176#define B_BE_EF_ENT BIT(31)
4177#define B_BE_EF_TCOLUMN_EN BIT(29)
4178#define B_BE_BT_OTP_PWC_DIS BIT(28)
4179#define B_BE_EF_RDT BIT(27)
4180#define B_BE_R_SYM_AUTOLOAD_WITH_PMC_SEL BIT(24)
4181#define B_BE_EF_PGTS_MASK GENMASK(23, 20)
4182#define B_BE_EF_BURST BIT(19)
4183#define B_BE_EF_TEST_SEL_MASK GENMASK(18, 16)
4184#define B_BE_EF_TROW_EN BIT(15)
4185#define B_BE_EF_ERR_FLAG BIT(14)
4186#define B_BE_EF_FBURST_DIS BIT(13)
4187#define B_BE_EF_HT_SEL BIT(12)
4188#define B_BE_EF_DSB_EN BIT(11)
4189#define B_BE_EF_DLY_SEL_MASK GENMASK(3, 0)
4190
4191#define R_BE_PMC_DBG_CTRL2 0x00CC
4192#define B_BE_EFUSE_BURN_GNT_MASK GENMASK(31, 24)
4193#define B_BE_DIS_IOWRAP_TIMEOUT BIT(16)
4194#define B_BE_STOP_WL_PMC BIT(9)
4195#define B_BE_STOP_SYM_PMC BIT(8)
4196#define B_BE_SYM_REG_PCIE_WRMSK BIT(7)
4197#define B_BE_BT_ACCESS_WL_PAGE0 BIT(6)
4198#define B_BE_R_BE_RST_WLPMC BIT(5)
4199#define B_BE_R_BE_RST_PD12N BIT(4)
4200#define B_BE_SYSON_DIS_WLR_BE_WRMSK BIT(3)
4201#define B_BE_SYSON_DIS_PMCR_BE_WRMSK BIT(2)
4202#define B_BE_SYSON_R_BE_ARB_MASK GENMASK(1, 0)
4203
4204#define R_BE_MEM_PWR_CTRL 0x00D0
4205#define B_BE_DMEM5_WLMCU_DS BIT(31)
4206#define B_BE_DMEM4_WLMCU_DS BIT(30)
4207#define B_BE_DMEM3_WLMCU_DS BIT(29)
4208#define B_BE_DMEM2_WLMCU_DS BIT(28)
4209#define B_BE_DMEM1_WLMCU_DS BIT(27)
4210#define B_BE_DMEM0_WLMCU_DS BIT(26)
4211#define B_BE_IMEM5_WLMCU_DS BIT(25)
4212#define B_BE_IMEM4_WLMCU_DS BIT(24)
4213#define B_BE_IMEM3_WLMCU_DS BIT(23)
4214#define B_BE_IMEM2_WLMCU_DS BIT(22)
4215#define B_BE_IMEM1_WLMCU_DS BIT(21)
4216#define B_BE_IMEM0_WLMCU_DS BIT(20)
4217#define B_BE_MEM_BBMCU1_DS BIT(19)
4218#define B_BE_MEM_BBMCU0_DS_V1 BIT(17)
4219#define B_BE_MEM_BT_DS BIT(10)
4220#define B_BE_MEM_SDIO_LS BIT(9)
4221#define B_BE_MEM_SDIO_DS BIT(8)
4222#define B_BE_MEM_USB_LS BIT(7)
4223#define B_BE_MEM_USB_DS BIT(6)
4224#define B_BE_MEM_PCI_LS BIT(5)
4225#define B_BE_MEM_PCI_DS BIT(4)
4226#define B_BE_MEM_WLMAC_LS BIT(3)
4227
4228#define R_BE_PCIE_MIO_INTF 0x00E4
4229#define B_BE_AON_MIO_EPHY_1K_SEL_MASK GENMASK(29, 24)
4230#define B_BE_PCIE_MIO_ADDR_PAGE_V1_MASK GENMASK(20, 16)
4231#define B_BE_PCIE_MIO_ASIF BIT(15)
4232#define B_BE_PCIE_MIO_BYIOREG BIT(13)
4233#define B_BE_PCIE_MIO_RE BIT(12)
4234#define B_BE_PCIE_MIO_WE_MASK GENMASK(11, 8)
4235#define B_BE_PCIE_MIO_ADDR_MASK GENMASK(7, 0)
4236
4237#define R_BE_PCIE_MIO_INTD 0x00E8
4238#define B_BE_PCIE_MIO_DATA_MASK GENMASK(31, 0)
4239
4240#define R_BE_HALT_H2C_CTRL 0x0160
4241#define B_BE_HALT_H2C_TRIGGER BIT(0)
4242
4243#define R_BE_HALT_C2H_CTRL 0x0164
4244#define B_BE_HALT_C2H_TRIGGER BIT(0)
4245
4246#define R_BE_HALT_H2C 0x0168
4247#define B_BE_HALT_H2C_MASK GENMASK(31, 0)
4248
4249#define R_BE_HALT_C2H 0x016C
4250#define B_BE_HALT_C2H_ERROR_SENARIO_MASK GENMASK(31, 28)
4251#define B_BE_ERROR_CODE_MASK GENMASK(15, 0)
4252
4253#define R_BE_SYS_CFG5 0x0170
4254#define B_BE_WDT_DATACPU_WAKE_PCIE_EN BIT(12)
4255#define B_BE_WDT_DATACPU_WAKE_USB_EN BIT(11)
4256#define B_BE_WDT_WAKE_PCIE_EN BIT(10)
4257#define B_BE_WDT_WAKE_USB_EN BIT(9)
4258#define B_BE_SYM_DIS_HC_ACCESS_MAC BIT(8)
4259#define B_BE_LPS_STATUS BIT(3)
4260#define B_BE_HCI_TXDMA_BUSY BIT(2)
4261
4262#define R_BE_SECURE_BOOT_MALLOC_INFO 0x0184
4263
4264#define R_BE_FWS1IMR 0x0198
4265#define B_BE_FS_RPWM_INT_EN_V1 BIT(24)
4266#define B_BE_PCIE_HOTRST_EN BIT(22)
4267#define B_BE_PCIE_SER_TIMEOUT_INDIC_EN BIT(21)
4268#define B_BE_PCIE_RXI300_SLVTOUT_INDIC_EN BIT(20)
4269#define B_BE_AON_PCIE_FLR_INT_EN BIT(19)
4270#define B_BE_PCIE_ERR_INDIC_INT_EN BIT(18)
4271#define B_BE_SDIO_ERR_INDIC_INT_EN BIT(17)
4272#define B_BE_USB_ERR_INDIC_INT_EN BIT(16)
4273#define B_BE_FS_GPIO27_INT_EN BIT(11)
4274#define B_BE_FS_GPIO26_INT_EN BIT(10)
4275#define B_BE_FS_GPIO25_INT_EN BIT(9)
4276#define B_BE_FS_GPIO24_INT_EN BIT(8)
4277#define B_BE_FS_GPIO23_INT_EN BIT(7)
4278#define B_BE_FS_GPIO22_INT_EN BIT(6)
4279#define B_BE_FS_GPIO21_INT_EN BIT(5)
4280#define B_BE_FS_GPIO20_INT_EN BIT(4)
4281#define B_BE_FS_GPIO19_INT_EN BIT(3)
4282#define B_BE_FS_GPIO18_INT_EN BIT(2)
4283#define B_BE_FS_GPIO17_INT_EN BIT(1)
4284#define B_BE_FS_GPIO16_INT_EN BIT(0)
4285
4286#define R_BE_HIMR0 0x01A0
4287#define B_BE_WDT_DATACPU_TIMEOUT_INT_EN BIT(25)
4288#define B_BE_HALT_D2H_INT_EN BIT(24)
4289#define B_BE_WDT_TIMEOUT_INT_EN BIT(22)
4290#define B_BE_HALT_C2H_INT_EN BIT(21)
4291#define B_BE_RON_INT_EN BIT(20)
4292#define B_BE_PDNINT_EN BIT(19)
4293#define B_BE_SPSANA_OCP_INT_EN BIT(18)
4294#define B_BE_SPS_OCP_INT_EN BIT(17)
4295#define B_BE_BTON_STS_UPDATE_INT_EN BIT(16)
4296#define B_BE_GPIOF_INT_EN BIT(15)
4297#define B_BE_GPIOE_INT_EN BIT(14)
4298#define B_BE_GPIOD_INT_EN BIT(13)
4299#define B_BE_GPIOC_INT_EN BIT(12)
4300#define B_BE_GPIOB_INT_EN BIT(11)
4301#define B_BE_GPIOA_INT_EN BIT(10)
4302#define B_BE_GPIO9_INT_EN BIT(9)
4303#define B_BE_GPIO8_INT_EN BIT(8)
4304#define B_BE_GPIO7_INT_EN BIT(7)
4305#define B_BE_GPIO6_INT_EN BIT(6)
4306#define B_BE_GPIO5_INT_EN BIT(5)
4307#define B_BE_GPIO4_INT_EN BIT(4)
4308#define B_BE_GPIO3_INT_EN BIT(3)
4309#define B_BE_GPIO2_INT_EN BIT(2)
4310#define B_BE_GPIO1_INT_EN BIT(1)
4311#define B_BE_GPIO0_INT_EN BIT(0)
4312
4313#define R_BE_HISR0 0x01A4
4314#define B_BE_WDT_DATACPU_TIMEOUT_INT BIT(25)
4315#define B_BE_HALT_D2H_INT BIT(24)
4316#define B_BE_WDT_TIMEOUT_INT BIT(22)
4317#define B_BE_HALT_C2H_INT BIT(21)
4318#define B_BE_RON_INT BIT(20)
4319#define B_BE_PDNINT BIT(19)
4320#define B_BE_SPSANA_OCP_INT BIT(18)
4321#define B_BE_SPS_OCP_INT BIT(17)
4322#define B_BE_BTON_STS_UPDATE_INT BIT(16)
4323#define B_BE_GPIOF_INT BIT(15)
4324#define B_BE_GPIOE_INT BIT(14)
4325#define B_BE_GPIOD_INT BIT(13)
4326#define B_BE_GPIOC_INT BIT(12)
4327#define B_BE_GPIOB_INT BIT(11)
4328#define B_BE_GPIOA_INT BIT(10)
4329#define B_BE_GPIO9_INT BIT(9)
4330#define B_BE_GPIO8_INT BIT(8)
4331#define B_BE_GPIO7_INT BIT(7)
4332#define B_BE_GPIO6_INT BIT(6)
4333#define B_BE_GPIO5_INT BIT(5)
4334#define B_BE_GPIO4_INT BIT(4)
4335#define B_BE_GPIO3_INT BIT(3)
4336#define B_BE_GPIO2_INT BIT(2)
4337#define B_BE_GPIO1_INT BIT(1)
4338#define B_BE_GPIO0_INT BIT(0)
4339
4340#define R_BE_WCPU_FW_CTRL 0x01E0
4341#define B_BE_RUN_ENV_MASK GENMASK(31, 30)
4342#define B_BE_WCPU_FWDL_STATUS_MASK GENMASK(29, 26)
4343#define B_BE_WDT_PLT_RST_EN BIT(17)
4344#define B_BE_HOST_EXIST BIT(16)
4345#define B_BE_FW_SEC_AUTH_DONE BIT(14)
4346#define B_BE_FW_CPU_UTIL_STS_EN BIT(13)
4347#define B_BE_BBMCU1_FWDL_EN BIT(12)
4348#define B_BE_BBMCU0_FWDL_EN BIT(11)
4349#define B_BE_DATACPU_FWDL_EN BIT(10)
4350#define B_BE_WLANCPU_FWDL_EN BIT(9)
4351#define B_BE_WCPU_ROM_CUT_GET BIT(8)
4352#define B_BE_WCPU_ROM_CUT_VAL_MASK GENMASK(7, 4)
4353#define B_BE_FW_BOOT_MODE_MASK GENMASK(3, 2)
4354#define B_BE_H2C_PATH_RDY BIT(1)
4355#define B_BE_DLFW_PATH_RDY BIT(0)
4356
4357#define R_BE_BOOT_REASON 0x01E6
4358#define B_BE_BOOT_REASON_MASK GENMASK(2, 0)
4359
4360#define R_BE_LDM 0x01E8
4361#define B_BE_EN_32K BIT(31)
4362#define B_BE_LDM_MASK GENMASK(30, 0)
4363
4364#define R_BE_UDM0 0x01F0
4365#define B_BE_UDM0_SEND2RA_CNT_MASK GENMASK(31, 28)
4366#define B_BE_UDM0_TX_RPT_CNT_MASK GENMASK(27, 24)
4367#define B_BE_UDM0_FS_CODE_MASK GENMASK(23, 8)
4368#define B_BE_NULL_POINTER_INDC BIT(7)
4369#define B_BE_ROM_ASSERT_INDC BIT(6)
4370#define B_BE_RAM_ASSERT_INDC BIT(5)
4371#define B_BE_FW_IMAGE_TYPE BIT(4)
4372#define B_BE_UDM0_TRAP_LOOP_CTRL BIT(2)
4373#define B_BE_UDM0_SEND_HALTC2H_CTRL BIT(1)
4374#define B_BE_UDM0_DBG_MODE_CTRL BIT(0)
4375
4376#define R_BE_UDM1 0x01F4
4377#define B_BE_UDM1_ERROR_ADDR_MASK GENMASK(31, 16)
4378#define B_BE_UDM1_HALMAC_C2H_ENQ_CNT_MASK GENMASK(15, 12)
4379#define B_BE_UDM1_HALMAC_H2C_DEQ_CNT_MASK GENMASK(11, 8)
4380#define B_BE_UDM1_WCPU_C2H_ENQ_CNT_MASK GENMASK(7, 4)
4381#define B_BE_UDM1_WCPU_H2C_DEQ_CNT_MASK GENMASK(3, 0)
4382
4383#define R_BE_UDM2 0x01F8
4384#define B_BE_UDM2_EPC_RA_MASK GENMASK(31, 0)
4385
4386#define R_BE_AFE_ON_CTRL0 0x0240
4387#define B_BE_REG_LPF_R3_3_0_MASK GENMASK(31, 29)
4388#define B_BE_REG_LPF_R2_MASK GENMASK(28, 24)
4389#define B_BE_REG_LPF_C3_MASK GENMASK(23, 21)
4390#define B_BE_REG_LPF_C2_MASK GENMASK(20, 18)
4391#define B_BE_REG_LPF_C1_MASK GENMASK(17, 15)
4392#define B_BE_REG_CP_ICPX2 BIT(14)
4393#define B_BE_REG_CP_ICP_SEL_FAST_MASK GENMASK(13, 10)
4394#define B_BE_REG_CP_ICP_SEL_MASK GENMASK(9, 6)
4395#define B_BE_REG_IB_PI_MASK GENMASK(5, 4)
4396#define B_BE_REG_CK_DEBUG_BT BIT(3)
4397#define B_BE_EN_PC_LDO BIT(2)
4398#define B_BE_LDO_VSEL_MASK GENMASK(1, 0)
4399
4400#define R_BE_AFE_ON_CTRL1 0x0244
4401#define B_BE_REG_CK_MON_SEL_MASK GENMASK(31, 29)
4402#define B_BE_REG_CK_MON_CK960M_EN BIT(28)
4403#define B_BE_REG_XTAL_FREQ_SEL BIT(27)
4404#define B_BE_REG_XTAL_EDGE_SEL BIT(26)
4405#define B_BE_REG_VCO_KVCO BIT(25)
4406#define B_BE_REG_SDM_EDGE_SEL BIT(24)
4407#define B_BE_REG_SDM_CK_SEL BIT(23)
4408#define B_BE_REG_SDM_CK_GATED BIT(22)
4409#define B_BE_REG_PFD_RESET_GATED BIT(21)
4410#define B_BE_REG_LPF_R3_FAST_MASK GENMASK(20, 16)
4411#define B_BE_REG_LPF_R2_FAST_MASK GENMASK(15, 11)
4412#define B_BE_REG_LPF_C3_FAST_MASK GENMASK(10, 8)
4413#define B_BE_REG_LPF_C2_FAST_MASK GENMASK(7, 5)
4414#define B_BE_REG_LPF_C1_FAST_MASK GENMASK(4, 2)
4415#define B_BE_REG_LPF_R3_4_MASK GENMASK(1, 0)
4416
4417#define R_BE_AFE_ON_CTRL3 0x024C
4418#define B_BE_LDO_VSEL_DA_1_MASK GENMASK(31, 30)
4419#define B_BE_LDO_VSEL_DA_0_MASK GENMASK(29, 28)
4420#define B_BE_LDO_VSEL_D2S_1_MASK GENMASK(27, 26)
4421#define B_BE_LDO_VSEL_D2S_0_MASK GENMASK(25, 24)
4422#define B_BE_LDO_VSEL_BUF_MASK GENMASK(23, 22)
4423#define B_BE_REG_R2_L_MASK GENMASK(21, 19)
4424#define B_BE_REG_R1_L_MASK GENMASK(18, 16)
4425#define B_BE_REG_CK_DEBUG_BT_MON BIT(15)
4426#define B_BE_REG_BT_CLK_BUF_POWER BIT(14)
4427#define B_BE_REG_BG_OUT_BTADC_V1 BIT(13)
4428#define B_BE_REG_SEL_V18 BIT(11)
4429#define B_BE_REG_FRAC_EN BIT(10)
4430#define B_BE_REG_CK1920M_EN BIT(9)
4431#define B_BE_REG_CK1280M_EN BIT(8)
4432#define B_BE_REG_12LDO_SEL_MASK GENMASK(7, 6)
4433#define B_BE_REG_09LDO_SEL_MASK GENMASK(5, 4)
4434#define B_BE_REG_VC_TH BIT(3)
4435#define B_BE_REG_VC_TL BIT(2)
4436#define B_BE_REG_CK40M_EN BIT(1)
4437#define B_BE_REG_CK640M_EN BIT(0)
4438
4439#define R_BE_GPIO8_15_FUNC_SEL 0x02D4
4440#define B_BE_PINMUX_GPIO9_FUNC_SEL_MASK GENMASK(7, 4)
4441
4442#define R_BE_WLAN_XTAL_SI_CTRL 0x0270
4443#define B_BE_WL_XTAL_SI_CMD_POLL BIT(31)
4444#define B_BE_WL_XTAL_SI_CHIPID_MASK GENMASK(30, 28)
4445#define B_BE_WL_XTAL_SI_MODE_MASK GENMASK(25, 24)
4446#define B_BE_WL_XTAL_SI_BITMASK_MASK GENMASK(23, 16)
4447#define B_BE_WL_XTAL_SI_DATA_MASK GENMASK(15, 8)
4448#define B_BE_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0)
4449
4450#define R_BE_IC_PWR_STATE 0x03F0
4451#define B_BE_WHOLE_SYS_PWR_STE_MASK GENMASK(25, 16)
4452#define MAC_AX_SYS_ACT 0x220
4453#define B_BE_WLMAC_PWR_STE_MASK GENMASK(9, 8)
4454#define B_BE_UART_HCISYS_PWR_STE_MASK GENMASK(7, 6)
4455#define B_BE_SDIO_HCISYS_PWR_STE_MASK GENMASK(5, 4)
4456#define B_BE_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2)
4457#define B_BE_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)
4458
4459#define R_BE_WLCPU_PORT_PC 0x03FC
4460
4461#define R_BE_DBG_WOW 0x0504
4462
4463#define R_BE_DCPU_PLATFORM_ENABLE 0x0888
4464#define B_BE_DCPU_SYM_DPLT_MEM_MUX_EN BIT(10)
4465#define B_BE_DCPU_WARM_EN BIT(9)
4466#define B_BE_DCPU_UART_EN BIT(7)
4467#define B_BE_DCPU_IDDMA_EN BIT(6)
4468#define B_BE_DCPU_APB_WRAP_EN BIT(2)
4469#define B_BE_DCPU_EN BIT(1)
4470#define B_BE_DCPU_PLATFORM_EN BIT(0)
4471
4472#define R_BE_PL_AXIDMA_IDCT_MSK 0x0910
4473#define B_BE_PL_AXIDMA_RRESP_ERR_MASK BIT(6)
4474#define B_BE_PL_AXIDMA_BRESP_ERR_MASK BIT(5)
4475#define B_BE_PL_AXIDMA_FC_ERR_MASK BIT(4)
4476#define B_BE_PL_AXIDMA_TXBD_LEN0_MASK BIT(3)
4477#define B_BE_PL_AXIDMA_TXBD_4KBOUD_LENERR_MASK BIT(2)
4478#define B_BE_PL_AXIDMA_TXBD_RX_STUCK_MASK BIT(1)
4479#define B_BE_PL_AXIDMA_TXBD_TX_STUCK_MASK BIT(0)
4480#define B_BE_PL_AXIDMA_IDCT_MSK_CLR (B_BE_PL_AXIDMA_TXBD_TX_STUCK_MASK | \
4481				     B_BE_PL_AXIDMA_TXBD_RX_STUCK_MASK | \
4482				     B_BE_PL_AXIDMA_TXBD_LEN0_MASK | \
4483				     B_BE_PL_AXIDMA_FC_ERR_MASK | \
4484				     B_BE_PL_AXIDMA_BRESP_ERR_MASK | \
4485				     B_BE_PL_AXIDMA_RRESP_ERR_MASK)
4486#define B_BE_PL_AXIDMA_IDCT_MSK_SET (B_BE_PL_AXIDMA_TXBD_TX_STUCK_MASK | \
4487				     B_BE_PL_AXIDMA_TXBD_RX_STUCK_MASK | \
4488				     B_BE_PL_AXIDMA_TXBD_LEN0_MASK | \
4489				     B_BE_PL_AXIDMA_FC_ERR_MASK)
4490
4491#define R_BE_PL_AXIDMA_IDCT 0x0914
4492#define B_BE_PL_AXIDMA_RRESP_ERR BIT(6)
4493#define B_BE_PL_AXIDMA_BRESP_ERR BIT(5)
4494#define B_BE_PL_AXIDMA_FC_ERR BIT(4)
4495#define B_BE_PL_AXIDMA_TXBD_LEN0 BIT(3)
4496#define B_BE_PL_AXIDMA_TXBD_4KBOUD_LENERR BIT(2)
4497#define B_BE_PL_AXIDMA_TXBD_RX_STUCK BIT(1)
4498#define B_BE_PL_AXIDMA_TXBD_TX_STUCK BIT(0)
4499
4500#define R_BE_FILTER_MODEL_ADDR 0x0C04
4501
4502#define R_BE_WLAN_WDT 0x3050
4503#define B_BE_WLAN_WDT_TIMEOUT BIT(31)
4504#define B_BE_WLAN_WDT_TIMER_CLEAR BIT(4)
4505#define B_BE_WLAN_WDT_BYPASS BIT(1)
4506#define B_BE_WLAN_WDT_ENABLE BIT(0)
4507
4508#define R_BE_AXIDMA_WDT 0x305C
4509#define B_BE_AXIDMA_WDT_TIMEOUT BIT(31)
4510#define B_BE_AXIDMA_WDT_TIMER_CLEAR BIT(4)
4511#define B_BE_AXIDMA_WDT_BYPASS BIT(1)
4512#define B_BE_AXIDMA_WDT_ENABLE BIT(0)
4513
4514#define R_BE_AON_WDT 0x3068
4515#define B_BE_AON_WDT_TIMEOUT BIT(31)
4516#define B_BE_AON_WDT_TIMER_CLEAR BIT(4)
4517#define B_BE_AON_WDT_BYPASS BIT(1)
4518#define B_BE_AON_WDT_ENABLE BIT(0)
4519
4520#define R_BE_AON_WDT_TMR 0x306C
4521#define R_BE_MDIO_WDT_TMR 0x3090
4522#define R_BE_LA_MODE_WDT_TMR 0x309C
4523#define R_BE_WDT_AR_TMR 0x3144
4524#define R_BE_WDT_AW_TMR 0x3150
4525#define R_BE_WLAN_WDT_TMR 0x3054
4526#define R_BE_WDT_W_TMR 0x315C
4527#define R_BE_AXIDMA_WDT_TMR 0x3060
4528#define R_BE_WDT_B_TMR 0x3164
4529#define R_BE_WDT_R_TMR 0x316C
4530#define R_BE_LOCAL_WDT_TMR 0x3084
4531
4532#define R_BE_LOCAL_WDT 0x3080
4533#define B_BE_LOCAL_WDT_TIMEOUT BIT(31)
4534#define B_BE_LOCAL_WDT_TIMER_CLEAR BIT(4)
4535#define B_BE_LOCAL_WDT_BYPASS BIT(1)
4536#define B_BE_LOCAL_WDT_ENABLE BIT(0)
4537
4538#define R_BE_MDIO_WDT 0x308C
4539#define B_BE_MDIO_WDT_TIMEOUT BIT(31)
4540#define B_BE_MDIO_WDT_TIMER_CLEAR BIT(4)
4541#define B_BE_MDIO_WDT_BYPASS BIT(1)
4542#define B_BE_MDIO_WDT_ENABLE BIT(0)
4543
4544#define R_BE_LA_MODE_WDT 0x3098
4545#define B_BE_LA_MODE_WDT_TIMEOUT BIT(31)
4546#define B_BE_LA_MODE_WDT_TIMER_CLEAR BIT(4)
4547#define B_BE_LA_MODE_WDT_BYPASS BIT(1)
4548#define B_BE_LA_MODE_WDT_ENABLE BIT(0)
4549
4550#define R_BE_WDT_AR 0x3140
4551#define B_BE_WDT_AR_TIMEOUT BIT(31)
4552#define B_BE_WDT_AR_TIMER_CLEAR BIT(4)
4553#define B_BE_WDT_AR_BYPASS BIT(1)
4554#define B_BE_WDT_AR_ENABLE BIT(0)
4555
4556#define R_BE_WDT_AW 0x314C
4557#define B_BE_WDT_AW_TIMEOUT BIT(31)
4558#define B_BE_WDT_AW_TIMER_CLEAR BIT(4)
4559#define B_BE_WDT_AW_BYPASS BIT(1)
4560#define B_BE_WDT_AW_ENABLE BIT(0)
4561
4562#define R_BE_WDT_W 0x3158
4563#define B_BE_WDT_W_TIMEOUT BIT(31)
4564#define B_BE_WDT_W_TIMER_CLEAR BIT(4)
4565#define B_BE_WDT_W_BYPASS BIT(1)
4566#define B_BE_WDT_W_ENABLE BIT(0)
4567
4568#define R_BE_WDT_B 0x3160
4569#define B_BE_WDT_B_TIMEOUT BIT(31)
4570#define B_BE_WDT_B_TIMER_CLEAR BIT(4)
4571#define B_BE_WDT_B_BYPASS BIT(1)
4572#define B_BE_WDT_B_ENABLE BIT(0)
4573
4574#define R_BE_WDT_R 0x3168
4575#define B_BE_WDT_R_TIMEOUT BIT(31)
4576#define B_BE_WDT_R_TIMER_CLEAR BIT(4)
4577#define B_BE_WDT_R_BYPASS BIT(1)
4578#define B_BE_WDT_R_ENABLE BIT(0)
4579
4580#define R_BE_LTR_DECISION_CTRL_V1 0x3610
4581#define B_BE_ENABLE_LTR_CTL_DECISION BIT(31)
4582#define B_BE_LAT_LTR_IDX_DRV_VLD_V1 BIT(24)
4583#define B_BE_LAT_LTR_IDX_DRV_V1_MASK GENMASK(23, 22)
4584#define B_BE_LAT_LTR_IDX_FW_VLD_V1 BIT(21)
4585#define B_BE_LAT_LTR_IDX_FW_V1_MASK GENMASK(20, 19)
4586#define B_BE_LAT_LTR_IDX_HW_VLD_V1 BIT(18)
4587#define B_BE_LAT_LTR_IDX_HW_V1_MASK GENMASK(17, 16)
4588#define B_BE_LTR_IDX_DRV_V1_MASK GENMASK(15, 14)
4589#define B_BE_LTR_REQ_DRV_V1 BIT(13)
4590#define B_BE_LTR_IDX_DISABLE_V1_MASK GENMASK(9, 8)
4591#define B_BE_LTR_EN_PORT_V1_MASK GENMASK(6, 4)
4592#define B_BE_LTR_DRV_DEC_EN_V1 BIT(6)
4593#define B_BE_LTR_FW_DEC_EN_V1 BIT(5)
4594#define B_BE_LTR_HW_DEC_EN_V1 BIT(4)
4595#define B_BE_LTR_SPACE_IDX_MASK GENMASK(1, 0)
4596
4597#define R_BE_LTR_LATENCY_IDX0_V1 0x3614
4598#define R_BE_LTR_LATENCY_IDX1_V1 0x3618
4599#define R_BE_LTR_LATENCY_IDX2_V1 0x361C
4600#define R_BE_LTR_LATENCY_IDX3_V1 0x3620
4601
4602#define R_BE_H2CREG_DATA0 0x7140
4603#define R_BE_H2CREG_DATA1 0x7144
4604#define R_BE_H2CREG_DATA2 0x7148
4605#define R_BE_H2CREG_DATA3 0x714C
4606#define R_BE_C2HREG_DATA0 0x7150
4607#define R_BE_C2HREG_DATA1 0x7154
4608#define R_BE_C2HREG_DATA2 0x7158
4609#define R_BE_C2HREG_DATA3 0x715C
4610#define R_BE_H2CREG_CTRL 0x7160
4611#define B_BE_H2CREG_TRIGGER BIT(0)
4612#define R_BE_C2HREG_CTRL 0x7164
4613#define B_BE_C2HREG_TRIGGER BIT(0)
4614
4615#define R_BE_HCI_FUNC_EN 0x7880
4616#define B_BE_HCI_CR_PROTECT BIT(31)
4617#define B_BE_HCI_TRXBUF_EN BIT(2)
4618#define B_BE_HCI_RXDMA_EN BIT(1)
4619#define B_BE_HCI_TXDMA_EN BIT(0)
4620
4621#define R_BE_BOOT_DBG 0x78F0
4622#define B_BE_BOOT_STATUS_MASK GENMASK(31, 16)
4623#define B_BE_SECUREBOOT_STATUS_MASK GENMASK(15, 0)
4624
4625#define R_BE_DBG_WOW_READY 0x815E
4626#define B_BE_DBG_WOW_READY GENMASK(7, 0)
4627
4628#define R_BE_DMAC_FUNC_EN 0x8400
4629#define B_BE_DMAC_CRPRT BIT(31)
4630#define B_BE_MAC_FUNC_EN BIT(30)
4631#define B_BE_DMAC_FUNC_EN BIT(29)
4632#define B_BE_MPDU_PROC_EN BIT(28)
4633#define B_BE_WD_RLS_EN BIT(27)
4634#define B_BE_DLE_WDE_EN BIT(26)
4635#define B_BE_TXPKT_CTRL_EN BIT(25)
4636#define B_BE_STA_SCH_EN BIT(24)
4637#define B_BE_DLE_PLE_EN BIT(23)
4638#define B_BE_PKT_BUF_EN BIT(22)
4639#define B_BE_DMAC_TBL_EN BIT(21)
4640#define B_BE_PKT_IN_EN BIT(20)
4641#define B_BE_DLE_CPUIO_EN BIT(19)
4642#define B_BE_DISPATCHER_EN BIT(18)
4643#define B_BE_BBRPT_EN BIT(17)
4644#define B_BE_MAC_SEC_EN BIT(16)
4645#define B_BE_DMACREG_GCKEN BIT(15)
4646#define B_BE_H_AXIDMA_EN BIT(14)
4647#define B_BE_DMAC_MLO_EN BIT(11)
4648#define B_BE_PLRLS_EN BIT(10)
4649#define B_BE_P_AXIDMA_EN BIT(9)
4650#define B_BE_DLE_DATACPUIO_EN BIT(8)
4651#define B_BE_LTR_CTL_EN BIT(7)
4652
4653#define R_BE_DMAC_CLK_EN 0x8404
4654#define B_BE_MAC_CKEN BIT(30)
4655#define B_BE_DMAC_CKEN BIT(29)
4656#define B_BE_MPDU_CKEN BIT(28)
4657#define B_BE_WD_RLS_CLK_EN BIT(27)
4658#define B_BE_DLE_WDE_CLK_EN BIT(26)
4659#define B_BE_TXPKT_CTRL_CLK_EN BIT(25)
4660#define B_BE_STA_SCH_CLK_EN BIT(24)
4661#define B_BE_DLE_PLE_CLK_EN BIT(23)
4662#define B_BE_PKTBUF_CKEN BIT(22)
4663#define B_BE_DMAC_TABLE_CLK_EN BIT(21)
4664#define B_BE_PKT_IN_CLK_EN BIT(20)
4665#define B_BE_DLE_CPUIO_CLK_EN BIT(19)
4666#define B_BE_DISPATCHER_CLK_EN BIT(18)
4667#define B_BE_BBRPT_CLK_EN BIT(17)
4668#define B_BE_MAC_SEC_CLK_EN BIT(16)
4669#define B_BE_H_AXIDMA_CKEN BIT(14)
4670#define B_BE_DMAC_MLO_CKEN BIT(11)
4671#define B_BE_PLRLS_CKEN BIT(10)
4672#define B_BE_P_AXIDMA_CKEN BIT(9)
4673#define B_BE_DLE_DATACPUIO_CKEN BIT(8)
4674
4675#define R_BE_LTR_CTRL_0 0x8410
4676#define B_BE_LTR_REQ_FW BIT(18)
4677#define B_BE_LTR_IDX_FW_MASK GENMASK(17, 16)
4678#define B_BE_LTR_IDLE_TIMER_IDX_MASK GENMASK(10, 8)
4679#define B_BE_LTR_WD_NOEMP_CHK BIT(1)
4680#define B_BE_LTR_HW_EN BIT(0)
4681
4682#define R_BE_LTR_CFG_0 0x8414
4683#define B_BE_LTR_IDX_DISABLE_MASK GENMASK(17, 16)
4684#define B_BE_LTR_IDX_IDLE_MASK GENMASK(15, 14)
4685#define B_BE_LTR_IDX_ACTIVE_MASK GENMASK(13, 12)
4686#define B_BE_LTR_IDLE_TIMER_IDX_MASK GENMASK(10, 8)
4687#define B_BE_EN_LTR_CMAC_RX_USE_PG_CHK BIT(3)
4688#define B_BE_EN_LTR_WD_NON_EMPTY_CHK BIT(2)
4689#define B_BE_EN_LTR_HAXIDMA_TX_IDLE_CHK BIT(1)
4690#define B_BE_EN_LTR_HAXIDMA_RX_IDLE_CHK BIT(0)
4691
4692#define R_BE_LTR_CFG_1 0x8418
4693#define B_BE_LTR_CMAC1_RX_USE_PG_TH_MASK GENMASK(27, 16)
4694#define B_BE_LTR_CMAC0_RX_USE_PG_TH_MASK GENMASK(11, 0)
4695
4696#define R_BE_DMAC_TABLE_CTRL 0x8420
4697#define B_BE_HWAMSDU_PADDING_MODE BIT(31)
4698#define B_BE_MACID_MPDU_PROCESSOR_OFFSET_MASK GENMASK(26, 16)
4699#define B_BE_DMAC_ADDR_MODE BIT(12)
4700#define B_BE_DMAC_CTRL_INFO_SER_IO BIT(11)
4701#define B_BE_DMAC_CTRL_INFO_OFFSET_MASK GENMASK(10, 0)
4702
4703#define R_BE_SER_DBG_INFO 0x8424
4704#define B_BE_SER_L0_PROMOTE_L1_EVENT_MASK GENMASK(31, 28)
4705#define B_BE_SER_L1_COUNTER_MASK GENMASK(27, 24)
4706#define B_BE_RMAC_PPDU_HANG_CNT_MASK GENMASK(23, 16)
4707#define B_BE_SER_L0_COUNTER_MASK GENMASK(8, 0)
4708
4709#define R_BE_DMAC_SYS_CR32B 0x842C
4710#define B_BE_DMAC_BB_PHY1_MASK GENMASK(31, 16)
4711#define B_BE_DMAC_BB_PHY0_MASK GENMASK(15, 0)
4712#define B_BE_DMAC_BB_CTRL_39 BIT(31)
4713#define B_BE_DMAC_BB_CTRL_38 BIT(30)
4714#define B_BE_DMAC_BB_CTRL_37 BIT(29)
4715#define B_BE_DMAC_BB_CTRL_36 BIT(28)
4716#define B_BE_DMAC_BB_CTRL_35 BIT(27)
4717#define B_BE_DMAC_BB_CTRL_34 BIT(26)
4718#define B_BE_DMAC_BB_CTRL_33 BIT(25)
4719#define B_BE_DMAC_BB_CTRL_32 BIT(24)
4720#define B_BE_DMAC_BB_CTRL_31 BIT(23)
4721#define B_BE_DMAC_BB_CTRL_30 BIT(22)
4722#define B_BE_DMAC_BB_CTRL_29 BIT(21)
4723#define B_BE_DMAC_BB_CTRL_28 BIT(20)
4724#define B_BE_DMAC_BB_CTRL_27 BIT(19)
4725#define B_BE_DMAC_BB_CTRL_26 BIT(18)
4726#define B_BE_DMAC_BB_CTRL_25 BIT(17)
4727#define B_BE_DMAC_BB_CTRL_24 BIT(16)
4728#define B_BE_DMAC_BB_CTRL_23 BIT(15)
4729#define B_BE_DMAC_BB_CTRL_22 BIT(14)
4730#define B_BE_DMAC_BB_CTRL_21 BIT(13)
4731#define B_BE_DMAC_BB_CTRL_20 BIT(12)
4732#define B_BE_DMAC_BB_CTRL_19 BIT(11)
4733#define B_BE_DMAC_BB_CTRL_18 BIT(10)
4734#define B_BE_DMAC_BB_CTRL_17 BIT(9)
4735#define B_BE_DMAC_BB_CTRL_16 BIT(8)
4736#define B_BE_DMAC_BB_CTRL_15 BIT(7)
4737#define B_BE_DMAC_BB_CTRL_14 BIT(6)
4738#define B_BE_DMAC_BB_CTRL_13 BIT(5)
4739#define B_BE_DMAC_BB_CTRL_12 BIT(4)
4740#define B_BE_DMAC_BB_CTRL_11 BIT(3)
4741#define B_BE_DMAC_BB_CTRL_10 BIT(2)
4742#define B_BE_DMAC_BB_CTRL_9 BIT(1)
4743#define B_BE_DMAC_BB_CTRL_8 BIT(0)
4744
4745#define R_BE_DLE_EMPTY0 0x8430
4746#define B_BE_PLE_EMPTY_QTA_DMAC_H2D BIT(27)
4747#define B_BE_PLE_EMPTY_QTA_DMAC_CPUIO BIT(26)
4748#define B_BE_PLE_EMPTY_QTA_DMAC_MPDU_TX BIT(25)
4749#define B_BE_PLE_EMPTY_QTA_DMAC_WLAN_CPU BIT(24)
4750#define B_BE_PLE_EMPTY_QTA_DMAC_H2C BIT(23)
4751#define B_BE_PLE_EMPTY_QTA_DMAC_B1_TXPL BIT(22)
4752#define B_BE_PLE_EMPTY_QTA_DMAC_B0_TXPL BIT(21)
4753#define B_BE_WDE_EMPTY_QTA_DMAC_CPUIO BIT(20)
4754#define B_BE_WDE_EMPTY_QTA_DMAC_PKTIN BIT(19)
4755#define B_BE_WDE_EMPTY_QTA_DMAC_DATA_CPU BIT(18)
4756#define B_BE_WDE_EMPTY_QTA_DMAC_WLAN_CPU BIT(17)
4757#define B_BE_WDE_EMPTY_QTA_DMAC_HIF BIT(16)
4758#define B_BE_WDE_EMPTY_QUE_CMAC_B1_HIQ BIT(15)
4759#define B_BE_WDE_EMPTY_QUE_CMAC_B1_MBH BIT(14)
4760#define B_BE_WDE_EMPTY_QUE_CMAC_B0_OTHERS BIT(13)
4761#define B_BE_WDE_EMPTY_QUE_DMAC_MLO_ACQ BIT(12)
4762#define B_BE_WDE_EMPTY_QUE_DMAC_MLO_MISC BIT(11)
4763#define B_BE_WDE_EMPTY_QUE_DMAC_PKTIN BIT(10)
4764#define B_BE_PLE_EMPTY_QUE_DMAC_SEC_TX BIT(9)
4765#define B_BE_PLE_EMPTY_QUE_DMAC_MPDU_TX BIT(8)
4766#define B_BE_WDE_EMPTY_QUE_OTHERS BIT(7)
4767#define B_BE_WDE_EMPTY_QUE_CMAC_WMM3 BIT(6)
4768#define B_BE_WDE_EMPTY_QUE_CMAC_WMM2 BIT(5)
4769#define B_BE_WDE_EMPTY_QUE_CMAC0_WMM1 BIT(4)
4770#define B_BE_WDE_EMPTY_QUE_CMAC0_WMM0 BIT(3)
4771#define B_BE_WDE_EMPTY_QUE_CMAC1_MBH BIT(2)
4772#define B_BE_WDE_EMPTY_QUE_CMAC0_MBH BIT(1)
4773#define B_BE_WDE_EMPTY_QUE_CMAC0_ALL_AC BIT(0)
4774
4775#define R_BE_DLE_EMPTY1 0x8434
4776#define B_BE_PLE_EMPTY_QTA_CMAC_DMA_TXRPT BIT(21)
4777#define B_BE_PLE_EMPTY_QTA_DMAC_WDRLS BIT(20)
4778#define B_BE_PLE_EMPTY_QTA_CMAC1_DMA_BBRPT BIT(19)
4779#define B_BE_PLE_EMPTY_QTA_CMAC1_DMA_RX BIT(18)
4780#define B_BE_PLE_EMPTY_QTA_CMAC0_DMA_RX BIT(17)
4781#define B_BE_PLE_EMPTY_QTA_DMAC_C2H BIT(16)
4782#define B_BE_PLE_EMPTY_QUE_DMAC_PLRLS BIT(5)
4783#define B_BE_PLE_EMPTY_QUE_DMAC_CPUIO BIT(4)
4784#define B_BE_PLE_EMPTY_QUE_DMAC_SEC_RX BIT(3)
4785#define B_BE_PLE_EMPTY_QUE_DMAC_MPDU_RX BIT(2)
4786#define B_BE_PLE_EMPTY_QUE_DMAC_HDP BIT(1)
4787#define B_BE_WDE_EMPTY_QUE_DMAC_WDRLS BIT(0)
4788
4789#define R_BE_SER_L1_DBG_CNT_0 0x8440
4790#define B_BE_SER_L1_WDRLS_CNT_MASK GENMASK(31, 24)
4791#define B_BE_SER_L1_SEC_CNT_MASK GENMASK(23, 16)
4792#define B_BE_SER_L1_MPDU_CNT_MASK GENMASK(15, 8)
4793#define B_BE_SER_L1_STA_SCH_CNT_MASK GENMASK(7, 0)
4794
4795#define R_BE_SER_L1_DBG_CNT_1 0x8444
4796#define B_BE_SER_L1_WDE_CNT_MASK GENMASK(31, 24)
4797#define B_BE_SER_L1_TXPKTCTRL_CNT_MASK GENMASK(23, 16)
4798#define B_BE_SER_L1_PLE_CNT_MASK GENMASK(15, 8)
4799#define B_BE_SER_L1_PKTIN_CNT_MASK GENMASK(7, 0)
4800
4801#define R_BE_SER_L1_DBG_CNT_2 0x8448
4802#define B_BE_SER_L1_DISP_CNT_MASK GENMASK(31, 24)
4803#define B_BE_SER_L1_APB_BRIDGE_CNT_MASK GENMASK(23, 16)
4804#define B_BE_SER_L1_DLE_W_CPUIO_CNT_MASK GENMASK(15, 8)
4805#define B_BE_SER_L1_BBRPT_CNT_MASK GENMASK(7, 0)
4806
4807#define R_BE_SER_L1_DBG_CNT_3 0x844C
4808#define B_BE_SER_L1_HCI_BUF_CNT_MASK GENMASK(31, 24)
4809#define B_BE_SER_L1_P_AXIDMA_CNT_MASK GENMASK(23, 16)
4810#define B_BE_SER_L1_H_AXIDMA_CNT_MASK GENMASK(15, 8)
4811#define B_BE_SER_L1_MLO_ERR_CNT_MASK GENMASK(7, 0)
4812
4813#define R_BE_SER_L1_DBG_CNT_4 0x8450
4814#define B_BE_SER_L1_PLDRLS_ERR_CNT_MASK GENMASK(31, 24)
4815#define B_BE_SER_L1_DLE_D_CPUIO_CNT_MASK GENMASK(23, 16)
4816
4817#define R_BE_SER_L1_DBG_CNT_5 0x8454
4818#define B_BE_SER_L1_DBG_0_MASK GENMASK(31, 0)
4819
4820#define R_BE_SER_L1_DBG_CNT_6 0x8458
4821#define B_BE_SER_L1_DBG_1_MASK GENMASK(31, 0)
4822
4823#define R_BE_SER_L1_DBG_CNT_7 0x845C
4824#define B_BE_SER_L1_DBG_2_MASK GENMASK(31, 0)
4825
4826#define R_BE_DMAC_ERR_IMR 0x8520
4827#define B_BE_DMAC_NOTX_ERR_INT_EN BIT(21)
4828#define B_BE_DMAC_NORX_ERR_INT_EN BIT(20)
4829#define B_BE_DLE_DATACPUIO_ERR_INT_EN BIT(19)
4830#define B_BE_PLRSL_ERR_INT_EN BIT(18)
4831#define B_BE_MLO_ERR_INT_EN BIT(17)
4832#define B_BE_DMAC_FW_ERR_INT_EN BIT(16)
4833#define B_BE_H_AXIDMA_ERR_INT_EN BIT(14)
4834#define B_BE_P_AXIDMA_ERR_INT_EN BIT(13)
4835#define B_BE_HCI_BUF_ERR_INT_EN BIT(12)
4836#define B_BE_BBRPT_ERR_INT_EN BIT(11)
4837#define B_BE_DLE_CPUIO_ERR_INT_EN BIT(10)
4838#define B_BE_APB_BRIDGE_ERR_INT_EN BIT(9)
4839#define B_BE_DISPATCH_ERR_INT_EN BIT(8)
4840#define B_BE_PKTIN_ERR_INT_EN BIT(7)
4841#define B_BE_PLE_DLE_ERR_INT_EN BIT(6)
4842#define B_BE_TXPKTCTRL_ERR_INT_EN BIT(5)
4843#define B_BE_WDE_DLE_ERR_INT_EN BIT(4)
4844#define B_BE_STA_SCHEDULER_ERR_INT_EN BIT(3)
4845#define B_BE_MPDU_ERR_INT_EN BIT(2)
4846#define B_BE_WSEC_ERR_INT_EN BIT(1)
4847#define B_BE_WDRLS_ERR_INT_EN BIT(0)
4848
4849#define R_BE_DMAC_ERR_ISR 0x8524
4850#define B_BE_DLE_DATACPUIO_ERR_INT BIT(19)
4851#define B_BE_PLRLS_ERR_INT BIT(18)
4852#define B_BE_MLO_ERR_INT BIT(17)
4853#define B_BE_DMAC_FW_ERR_IDCT BIT(16)
4854#define B_BE_H_AXIDMA_ERR_INT BIT(14)
4855#define B_BE_P_AXIDMA_ERR_INT BIT(13)
4856#define B_BE_HCI_BUF_ERR_FLAG BIT(12)
4857#define B_BE_BBRPT_ERR_FLAG BIT(11)
4858#define B_BE_DLE_CPUIO_ERR_FLAG BIT(10)
4859#define B_BE_APB_BRIDGE_ERR_FLAG BIT(9)
4860#define B_BE_DISPATCH_ERR_FLAG BIT(8)
4861#define B_BE_PKTIN_ERR_FLAG BIT(7)
4862#define B_BE_PLE_DLE_ERR_FLAG BIT(6)
4863#define B_BE_TXPKTCTRL_ERR_FLAG BIT(5)
4864#define B_BE_WDE_DLE_ERR_FLAG BIT(4)
4865#define B_BE_STA_SCHEDULER_ERR_FLAG BIT(3)
4866#define B_BE_MPDU_ERR_FLAG BIT(2)
4867#define B_BE_WSEC_ERR_FLAG BIT(1)
4868#define B_BE_WDRLS_ERR_FLAG BIT(0)
4869
4870#define R_BE_DISP_ERROR_ISR0 0x8804
4871#define B_BE_REUSE_SIZE_ERR BIT(31)
4872#define B_BE_REUSE_EN_ERR BIT(30)
4873#define B_BE_STF_OQT_UNDERFLOW_ERR BIT(29)
4874#define B_BE_STF_OQT_OVERFLOW_ERR BIT(28)
4875#define B_BE_STF_WRFF_UNDERFLOW_ERR BIT(27)
4876#define B_BE_STF_WRFF_OVERFLOW_ERR BIT(26)
4877#define B_BE_STF_CMD_UNDERFLOW_ERR BIT(25)
4878#define B_BE_STF_CMD_OVERFLOW_ERR BIT(24)
4879#define B_BE_REUSE_SIZE_ZERO_ERR BIT(23)
4880#define B_BE_REUSE_PKT_CNT_ERR BIT(22)
4881#define B_BE_CDT_PTR_TIMEOUT_ERR BIT(21)
4882#define B_BE_CDT_HCI_TIMEOUT_ERR BIT(20)
4883#define B_BE_HDT_PTR_TIMEOUT_ERR BIT(19)
4884#define B_BE_HDT_HCI_TIMEOUT_ERR BIT(18)
4885#define B_BE_CDT_ADDR_INFO_LEN_ERR BIT(17)
4886#define B_BE_HDT_ADDR_INFO_LEN_ERR BIT(16)
4887#define B_BE_CDR_DMA_TIMEOUT_ERR BIT(15)
4888#define B_BE_CDR_RX_TIMEOUT_ERR BIT(14)
4889#define B_BE_PLE_OUTPUT_ERR BIT(12)
4890#define B_BE_PLE_RESPOSE_ERR BIT(11)
4891#define B_BE_PLE_BURST_NUM_ERR BIT(10)
4892#define B_BE_PLE_NULL_PKT_ERR BIT(9)
4893#define B_BE_PLE_FLOW_CTRL_ERR BIT(8)
4894#define B_BE_HDR_DMA_TIMEOUT_ERR BIT(7)
4895#define B_BE_HDR_RX_TIMEOUT_ERR BIT(6)
4896#define B_BE_WDE_OUTPUT_ERR BIT(4)
4897#define B_BE_WDE_RESPONSE_ERR BIT(3)
4898#define B_BE_WDE_BURST_NUM_ERR BIT(2)
4899#define B_BE_WDE_NULL_PKT_ERR BIT(1)
4900#define B_BE_WDE_FLOW_CTRL_ERR BIT(0)
4901
4902#define R_BE_DISP_ERROR_ISR1 0x8808
4903#define B_BE_HR_WRFF_UNDERFLOW_ERR BIT(31)
4904#define B_BE_HR_WRFF_OVERFLOW_ERR BIT(30)
4905#define B_BE_HR_CHKSUM_FSM_ERR BIT(29)
4906#define B_BE_HR_SHIFT_DMA_CFG_ERR BIT(28)
4907#define B_BE_HR_DMA_PROCESS_ERR BIT(27)
4908#define B_BE_HR_TOTAL_LEN_UNDER_ERR BIT(26)
4909#define B_BE_HR_SHIFT_EN_ERR BIT(25)
4910#define B_BE_HR_AGG_CFG_ERR BIT(24)
4911#define B_BE_HR_PLD_LEN_ZERO_ERR BIT(22)
4912#define B_BE_HT_ILL_CH_ERR BIT(20)
4913#define B_BE_HT_ADDR_INFO_LEN_ERR BIT(18)
4914#define B_BE_HT_WD_LEN_OVER_ERR BIT(17)
4915#define B_BE_HT_PLD_CMD_UNDERFLOW_ERR BIT(16)
4916#define B_BE_HT_PLD_CMD_OVERFLOW_ERR BIT(15)
4917#define B_BE_HT_WRFF_UNDERFLOW_ERR BIT(14)
4918#define B_BE_HT_WRFF_OVERFLOW_ERR BIT(13)
4919#define B_BE_HT_CHKSUM_FSM_ERR BIT(12)
4920#define B_BE_HT_NON_IDLE_PKT_STR_ERR BIT(11)
4921#define B_BE_HT_PRE_SUB_BE_ERR BIT(10)
4922#define B_BE_HT_WD_CHKSUM_ERR BIT(9)
4923#define B_BE_HT_CHANNEL_DMA_ERR BIT(8)
4924#define B_BE_HT_OFFSET_UNMATCH_ERR BIT(7)
4925#define B_BE_HT_PAYLOAD_UNDER_ERR BIT(6)
4926#define B_BE_HT_PAYLOAD_OVER_ERR BIT(5)
4927#define B_BE_HT_PERMU_FF_UNDERFLOW_ERR BIT(4)
4928#define B_BE_HT_PERMU_FF_OVERFLOW_ERR BIT(3)
4929#define B_BE_HT_PKT_FAIL_ERR BIT(2)
4930#define B_BE_HT_CH_ID_ERR BIT(1)
4931#define B_BE_HT_EP_CH_DIFF_ERR BIT(0)
4932
4933#define R_BE_DISP_ERROR_ISR2 0x880C
4934#define B_BE_CR_PLD_LEN_ERR BIT(30)
4935#define B_BE_CR_WRFF_UNDERFLOW_ERR BIT(29)
4936#define B_BE_CR_WRFF_OVERFLOW_ERR BIT(28)
4937#define B_BE_CR_SHIFT_DMA_CFG_ERR BIT(27)
4938#define B_BE_CR_DMA_PROCESS_ERR BIT(26)
4939#define B_BE_CR_SHIFT_EN_ERR BIT(24)
4940#define B_BE_REUSE_FIFO_B_UNDER_ERR BIT(22)
4941#define B_BE_REUSE_FIFO_B_OVER_ERR BIT(21)
4942#define B_BE_REUSE_FIFO_A_UNDER_ERR BIT(20)
4943#define B_BE_REUSE_FIFO_A_OVER_ERR BIT(19)
4944#define B_BE_CT_ADDR_INFO_LEN_MISS_ERR BIT(17)
4945#define B_BE_CT_WD_LEN_OVER_ERR BIT(16)
4946#define B_BE_CT_F2P_SEQ_ERR BIT(15)
4947#define B_BE_CT_F2P_QSEL_ERR BIT(14)
4948#define B_BE_CT_PLD_CMD_UNDERFLOW_ERR BIT(13)
4949#define B_BE_CT_PLD_CMD_OVERFLOW_ERR BIT(12)
4950#define B_BE_CT_PRE_SUB_ERR BIT(11)
4951#define B_BE_CT_WD_CHKSUM_ERR BIT(10)
4952#define B_BE_CT_CHANNEL_DMA_ERR BIT(9)
4953#define B_BE_CT_OFFSET_UNMATCH_ERR BIT(8)
4954#define B_BE_F2P_TOTAL_NUM_ERR BIT(7)
4955#define B_BE_CT_PAYLOAD_UNDER_ERR BIT(6)
4956#define B_BE_CT_PAYLOAD_OVER_ERR BIT(5)
4957#define B_BE_CT_PERMU_FF_UNDERFLOW_ERR BIT(4)
4958#define B_BE_CT_PERMU_FF_OVERFLOW_ERR BIT(3)
4959#define B_BE_CT_CH_ID_ERR BIT(2)
4960#define B_BE_CT_EP_CH_DIFF_ERR BIT(0)
4961
4962#define R_BE_DISP_OTHER_IMR 0x8870
4963#define B_BE_REUSE_SIZE_ERR_INT_EN BIT(31)
4964#define B_BE_REUSE_EN_ERR_INT_EN BIT(30)
4965#define B_BE_STF_OQT_UNDERFLOW_ERR_INT_EN BIT(29)
4966#define B_BE_STF_OQT_OVERFLOW_ERR_INT_EN BIT(28)
4967#define B_BE_STF_WRFF_UNDERFLOW_ERR_INT_EN BIT(27)
4968#define B_BE_STF_WRFF_OVERFLOW_ERR_INT_EN BIT(26)
4969#define B_BE_STF_CMD_UNDERFLOW_ERR_INT_EN BIT(25)
4970#define B_BE_STF_CMD_OVERFLOW_ERR_INT_EN BIT(24)
4971#define B_BE_REUSE_SIZE_ZERO_ERR_INT_EN BIT(23)
4972#define B_BE_REUSE_PKT_CNT_ERR_INT_EN BIT(22)
4973#define B_BE_CDT_PTR_TIMEOUT_ERR_INT_EN BIT(21)
4974#define B_BE_CDT_HCI_TIMEOUT_ERR_INT_EN BIT(20)
4975#define B_BE_HDT_PTR_TIMEOUT_ERR_INT_EN BIT(19)
4976#define B_BE_HDT_HCI_TIMEOUT_ERR_INT_EN BIT(18)
4977#define B_BE_CDT_ADDR_INFO_LEN_ERR_INT_EN BIT(17)
4978#define B_BE_HDT_ADDR_INFO_LEN_ERR_INT_EN BIT(16)
4979#define B_BE_CDR_DMA_TIMEOUT_ERR_INT_EN BIT(15)
4980#define B_BE_CDR_RX_TIMEOUT_ERR_INT_EN BIT(14)
4981#define B_BE_PLE_OUTPUT_ERR_INT_EN BIT(12)
4982#define B_BE_PLE_RESPOSE_ERR_INT_EN BIT(11)
4983#define B_BE_PLE_BURST_NUM_ERR_INT_EN BIT(10)
4984#define B_BE_PLE_NULL_PKT_ERR_INT_EN BIT(9)
4985#define B_BE_PLE_FLOW_CTRL_ERR_INT_EN BIT(8)
4986#define B_BE_HDR_DMA_TIMEOUT_ERR_INT_EN BIT(7)
4987#define B_BE_HDR_RX_TIMEOUT_ERR_INT_EN BIT(6)
4988#define B_BE_WDE_OUTPUT_ERR_INT_EN BIT(4)
4989#define B_BE_WDE_RESPONSE_ERR_INT_EN BIT(3)
4990#define B_BE_WDE_BURST_NUM_ERR_INT_EN BIT(2)
4991#define B_BE_WDE_NULL_PKT_ERR_INT_EN BIT(1)
4992#define B_BE_WDE_FLOW_CTRL_ERR_INT_EN BIT(0)
4993#define B_BE_DISP_OTHER_IMR_CLR (B_BE_WDE_FLOW_CTRL_ERR_INT_EN | \
4994				 B_BE_WDE_NULL_PKT_ERR_INT_EN | \
4995				 B_BE_WDE_BURST_NUM_ERR_INT_EN | \
4996				 B_BE_WDE_RESPONSE_ERR_INT_EN | \
4997				 B_BE_WDE_OUTPUT_ERR_INT_EN | \
4998				 B_BE_HDR_RX_TIMEOUT_ERR_INT_EN | \
4999				 B_BE_HDR_DMA_TIMEOUT_ERR_INT_EN | \
5000				 B_BE_PLE_FLOW_CTRL_ERR_INT_EN | \
5001				 B_BE_PLE_NULL_PKT_ERR_INT_EN | \
5002				 B_BE_PLE_BURST_NUM_ERR_INT_EN | \
5003				 B_BE_PLE_RESPOSE_ERR_INT_EN | \
5004				 B_BE_PLE_OUTPUT_ERR_INT_EN | \
5005				 B_BE_CDR_RX_TIMEOUT_ERR_INT_EN | \
5006				 B_BE_CDR_DMA_TIMEOUT_ERR_INT_EN | \
5007				 B_BE_HDT_ADDR_INFO_LEN_ERR_INT_EN | \
5008				 B_BE_CDT_ADDR_INFO_LEN_ERR_INT_EN | \
5009				 B_BE_HDT_HCI_TIMEOUT_ERR_INT_EN | \
5010				 B_BE_HDT_PTR_TIMEOUT_ERR_INT_EN | \
5011				 B_BE_CDT_HCI_TIMEOUT_ERR_INT_EN | \
5012				 B_BE_CDT_PTR_TIMEOUT_ERR_INT_EN | \
5013				 B_BE_REUSE_PKT_CNT_ERR_INT_EN | \
5014				 B_BE_REUSE_SIZE_ZERO_ERR_INT_EN | \
5015				 B_BE_STF_CMD_OVERFLOW_ERR_INT_EN | \
5016				 B_BE_STF_CMD_UNDERFLOW_ERR_INT_EN | \
5017				 B_BE_STF_WRFF_OVERFLOW_ERR_INT_EN | \
5018				 B_BE_STF_WRFF_UNDERFLOW_ERR_INT_EN | \
5019				 B_BE_STF_OQT_OVERFLOW_ERR_INT_EN | \
5020				 B_BE_STF_OQT_UNDERFLOW_ERR_INT_EN | \
5021				 B_BE_REUSE_EN_ERR_INT_EN | \
5022				 B_BE_REUSE_SIZE_ERR_INT_EN)
5023#define B_BE_DISP_OTHER_IMR_SET (B_BE_STF_CMD_OVERFLOW_ERR_INT_EN | \
5024				 B_BE_STF_CMD_UNDERFLOW_ERR_INT_EN | \
5025				 B_BE_STF_WRFF_OVERFLOW_ERR_INT_EN | \
5026				 B_BE_STF_WRFF_UNDERFLOW_ERR_INT_EN | \
5027				 B_BE_STF_OQT_OVERFLOW_ERR_INT_EN | \
5028				 B_BE_STF_OQT_UNDERFLOW_ERR_INT_EN)
5029
5030#define R_BE_DISP_HOST_IMR 0x8874
5031#define B_BE_HR_WRFF_UNDERFLOW_ERR_INT_EN BIT(31)
5032#define B_BE_HR_WRFF_OVERFLOW_ERR_INT_EN BIT(30)
5033#define B_BE_HR_CHKSUM_FSM_ERR_INT_EN BIT(29)
5034#define B_BE_HR_SHIFT_DMA_CFG_ERR_INT_EN BIT(28)
5035#define B_BE_HR_DMA_PROCESS_ERR_INT_EN BIT(27)
5036#define B_BE_HR_TOTAL_LEN_UNDER_ERR_INT_EN BIT(26)
5037#define B_BE_HR_SHIFT_EN_ERR_INT_EN BIT(25)
5038#define B_BE_HR_AGG_CFG_ERR_INT_EN BIT(24)
5039#define B_BE_HR_PLD_LEN_ZERO_ERR_INT_EN BIT(22)
5040#define B_BE_HT_ILL_CH_ERR_INT_EN BIT(20)
5041#define B_BE_HT_ADDR_INFO_LEN_ERR_INT_EN BIT(18)
5042#define B_BE_HT_WD_LEN_OVER_ERR_INT_EN BIT(17)
5043#define B_BE_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN BIT(16)
5044#define B_BE_HT_PLD_CMD_OVERFLOW_ERR_INT_EN BIT(15)
5045#define B_BE_HT_WRFF_UNDERFLOW_ERR_INT_EN BIT(14)
5046#define B_BE_HT_WRFF_OVERFLOW_ERR_INT_EN BIT(13)
5047#define B_BE_HT_CHKSUM_FSM_ERR_INT_EN BIT(12)
5048#define B_BE_HT_NON_IDLE_PKT_STR_ERR_EN BIT(11)
5049#define B_BE_HT_PRE_SUB_ERR_INT_EN BIT(10)
5050#define B_BE_HT_WD_CHKSUM_ERR_INT_EN BIT(9)
5051#define B_BE_HT_CHANNEL_DMA_ERR_INT_EN BIT(8)
5052#define B_BE_HT_OFFSET_UNMATCH_ERR_INT_EN BIT(7)
5053#define B_BE_HT_PAYLOAD_UNDER_ERR_INT_EN BIT(6)
5054#define B_BE_HT_PAYLOAD_OVER_ERR_INT_EN BIT(5)
5055#define B_BE_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4)
5056#define B_BE_HT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3)
5057#define B_BE_HT_PKT_FAIL_ERR_INT_EN BIT(2)
5058#define B_BE_HT_CH_ID_ERR_INT_EN BIT(1)
5059#define B_BE_HT_EP_CH_DIFF_ERR_INT_EN BIT(0)
5060#define B_BE_DISP_HOST_IMR_CLR (B_BE_HT_EP_CH_DIFF_ERR_INT_EN | \
5061				B_BE_HT_CH_ID_ERR_INT_EN | \
5062				B_BE_HT_PKT_FAIL_ERR_INT_EN | \
5063				B_BE_HT_PERMU_FF_OVERFLOW_ERR_INT_EN | \
5064				B_BE_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \
5065				B_BE_HT_PAYLOAD_OVER_ERR_INT_EN | \
5066				B_BE_HT_PAYLOAD_UNDER_ERR_INT_EN | \
5067				B_BE_HT_OFFSET_UNMATCH_ERR_INT_EN | \
5068				B_BE_HT_CHANNEL_DMA_ERR_INT_EN | \
5069				B_BE_HT_WD_CHKSUM_ERR_INT_EN | \
5070				B_BE_HT_PRE_SUB_ERR_INT_EN | \
5071				B_BE_HT_NON_IDLE_PKT_STR_ERR_EN | \
5072				B_BE_HT_CHKSUM_FSM_ERR_INT_EN | \
5073				B_BE_HT_WRFF_OVERFLOW_ERR_INT_EN | \
5074				B_BE_HT_WRFF_UNDERFLOW_ERR_INT_EN | \
5075				B_BE_HT_PLD_CMD_OVERFLOW_ERR_INT_EN | \
5076				B_BE_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \
5077				B_BE_HT_WD_LEN_OVER_ERR_INT_EN | \
5078				B_BE_HT_ADDR_INFO_LEN_ERR_INT_EN | \
5079				B_BE_HT_ILL_CH_ERR_INT_EN | \
5080				B_BE_HR_PLD_LEN_ZERO_ERR_INT_EN | \
5081				B_BE_HR_AGG_CFG_ERR_INT_EN | \
5082				B_BE_HR_SHIFT_EN_ERR_INT_EN | \
5083				B_BE_HR_TOTAL_LEN_UNDER_ERR_INT_EN | \
5084				B_BE_HR_DMA_PROCESS_ERR_INT_EN | \
5085				B_BE_HR_SHIFT_DMA_CFG_ERR_INT_EN | \
5086				B_BE_HR_CHKSUM_FSM_ERR_INT_EN | \
5087				B_BE_HR_WRFF_OVERFLOW_ERR_INT_EN | \
5088				B_BE_HR_WRFF_UNDERFLOW_ERR_INT_EN)
5089#define B_BE_DISP_HOST_IMR_SET (B_BE_HT_EP_CH_DIFF_ERR_INT_EN | \
5090				B_BE_HT_PERMU_FF_OVERFLOW_ERR_INT_EN | \
5091				B_BE_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \
5092				B_BE_HT_PAYLOAD_OVER_ERR_INT_EN | \
5093				B_BE_HT_PAYLOAD_UNDER_ERR_INT_EN | \
5094				B_BE_HT_CHANNEL_DMA_ERR_INT_EN | \
5095				B_BE_HT_PRE_SUB_ERR_INT_EN | \
5096				B_BE_HT_WRFF_OVERFLOW_ERR_INT_EN | \
5097				B_BE_HT_WRFF_UNDERFLOW_ERR_INT_EN | \
5098				B_BE_HT_PLD_CMD_OVERFLOW_ERR_INT_EN | \
5099				B_BE_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \
5100				B_BE_HT_WD_LEN_OVER_ERR_INT_EN | \
5101				B_BE_HT_ILL_CH_ERR_INT_EN | \
5102				B_BE_HR_TOTAL_LEN_UNDER_ERR_INT_EN | \
5103				B_BE_HR_DMA_PROCESS_ERR_INT_EN | \
5104				B_BE_HR_WRFF_OVERFLOW_ERR_INT_EN | \
5105				B_BE_HR_WRFF_UNDERFLOW_ERR_INT_EN)
5106
5107#define R_BE_DISP_CPU_IMR 0x8878
5108#define B_BE_CR_PLD_LEN_ERR_INT_EN BIT(30)
5109#define B_BE_CR_WRFF_UNDERFLOW_ERR_INT_EN BIT(29)
5110#define B_BE_CR_WRFF_OVERFLOW_ERR_INT_EN BIT(28)
5111#define B_BE_CR_SHIFT_DMA_CFG_ERR_INT_EN BIT(27)
5112#define B_BE_CR_DMA_PROCESS_ERR_INT_EN BIT(26)
5113#define B_BE_CR_TOTAL_LEN_UNDER_ERR_INT_EN BIT(25)
5114#define B_BE_CR_SHIFT_EN_ERR_INT_EN BIT(24)
5115#define B_BE_REUSE_FIFO_B_UNDER_ERR_INT_EN BIT(22)
5116#define B_BE_REUSE_FIFO_B_OVER_ERR_INT_EN BIT(21)
5117#define B_BE_REUSE_FIFO_A_UNDER_ERR_INT_EN BIT(20)
5118#define B_BE_REUSE_FIFO_A_OVER_ERR_INT_EN BIT(19)
5119#define B_BE_CT_ADDR_INFO_LEN_MISS_ERR_INT_EN BIT(17)
5120#define B_BE_CT_WD_LEN_OVER_ERR_INT_EN BIT(16)
5121#define B_BE_CT_F2P_SEQ_ERR_INT_EN BIT(15)
5122#define B_BE_CT_F2P_QSEL_ERR_INT_EN BIT(14)
5123#define B_BE_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN BIT(13)
5124#define B_BE_CT_PLD_CMD_OVERFLOW_ERR_INT_EN BIT(12)
5125#define B_BE_CT_PRE_SUB_ERR_INT_EN BIT(11)
5126#define B_BE_CT_WD_CHKSUM_ERR_INT_EN BIT(10)
5127#define B_BE_CT_CHANNEL_DMA_ERR_INT_EN BIT(9)
5128#define B_BE_CT_OFFSET_UNMATCH_ERR_INT_EN BIT(8)
5129#define B_BE_CT_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7)
5130#define B_BE_CT_PAYLOAD_UNDER_ERR_INT_EN BIT(6)
5131#define B_BE_CT_PAYLOAD_OVER_ERR_INT_EN BIT(5)
5132#define B_BE_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4)
5133#define B_BE_CT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3)
5134#define B_BE_CT_CH_ID_ERR_INT_EN BIT(2)
5135#define B_BE_CT_PKT_FAIL_ERR_INT_EN BIT(1)
5136#define B_BE_CT_EP_CH_DIFF_ERR_INT_EN BIT(0)
5137#define B_BE_DISP_CPU_IMR_CLR (B_BE_CT_EP_CH_DIFF_ERR_INT_EN | \
5138			       B_BE_CT_CH_ID_ERR_INT_EN | \
5139			       B_BE_CT_PERMU_FF_OVERFLOW_ERR_INT_EN | \
5140			       B_BE_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \
5141			       B_BE_CT_PAYLOAD_OVER_ERR_INT_EN | \
5142			       B_BE_CT_PAYLOAD_UNDER_ERR_INT_EN | \
5143			       B_BE_CT_OFFSET_UNMATCH_ERR_INT_EN | \
5144			       B_BE_CT_CHANNEL_DMA_ERR_INT_EN | \
5145			       B_BE_CT_WD_CHKSUM_ERR_INT_EN | \
5146			       B_BE_CT_PRE_SUB_ERR_INT_EN | \
5147			       B_BE_CT_PLD_CMD_OVERFLOW_ERR_INT_EN | \
5148			       B_BE_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \
5149			       B_BE_CT_F2P_QSEL_ERR_INT_EN | \
5150			       B_BE_CT_F2P_SEQ_ERR_INT_EN | \
5151			       B_BE_CT_WD_LEN_OVER_ERR_INT_EN | \
5152			       B_BE_CT_ADDR_INFO_LEN_MISS_ERR_INT_EN | \
5153			       B_BE_REUSE_FIFO_A_OVER_ERR_INT_EN | \
5154			       B_BE_REUSE_FIFO_A_UNDER_ERR_INT_EN | \
5155			       B_BE_REUSE_FIFO_B_OVER_ERR_INT_EN | \
5156			       B_BE_REUSE_FIFO_B_UNDER_ERR_INT_EN | \
5157			       B_BE_CR_SHIFT_EN_ERR_INT_EN | \
5158			       B_BE_CR_DMA_PROCESS_ERR_INT_EN | \
5159			       B_BE_CR_SHIFT_DMA_CFG_ERR_INT_EN | \
5160			       B_BE_CR_WRFF_OVERFLOW_ERR_INT_EN | \
5161			       B_BE_CR_WRFF_UNDERFLOW_ERR_INT_EN | \
5162			       B_BE_CR_PLD_LEN_ERR_INT_EN)
5163#define B_BE_DISP_CPU_IMR_SET (B_BE_CT_EP_CH_DIFF_ERR_INT_EN | \
5164			       B_BE_CT_CH_ID_ERR_INT_EN | \
5165			       B_BE_CT_PERMU_FF_OVERFLOW_ERR_INT_EN | \
5166			       B_BE_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \
5167			       B_BE_CT_PAYLOAD_OVER_ERR_INT_EN | \
5168			       B_BE_CT_PAYLOAD_UNDER_ERR_INT_EN | \
5169			       B_BE_CT_PRE_SUB_ERR_INT_EN | \
5170			       B_BE_CT_PLD_CMD_OVERFLOW_ERR_INT_EN | \
5171			       B_BE_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \
5172			       B_BE_CT_WD_LEN_OVER_ERR_INT_EN | \
5173			       B_BE_REUSE_FIFO_A_OVER_ERR_INT_EN | \
5174			       B_BE_REUSE_FIFO_A_UNDER_ERR_INT_EN | \
5175			       B_BE_REUSE_FIFO_B_OVER_ERR_INT_EN | \
5176			       B_BE_REUSE_FIFO_B_UNDER_ERR_INT_EN | \
5177			       B_BE_CR_DMA_PROCESS_ERR_INT_EN | \
5178			       B_BE_CR_WRFF_OVERFLOW_ERR_INT_EN | \
5179			       B_BE_CR_WRFF_UNDERFLOW_ERR_INT_EN)
5180
5181#define R_BE_RX_STOP 0x8914
5182#define B_BE_CPU_RX_STOP BIT(17)
5183#define B_BE_HOST_RX_STOP BIT(16)
5184#define B_BE_CPU_RX_CH_STOP_MSK GENMASK(15, 8)
5185#define B_BE_HOST_RX_CH_STOP_MSK GENMASK(5, 0)
5186
5187#define R_BE_DISP_FWD_WLAN_0 0x8938
5188#define B_BE_FWD_WLAN_CPU_TYPE_13_MASK GENMASK(31, 30)
5189#define B_BE_FWD_WLAN_CPU_TYPE_12_MASK GENMASK(29, 28)
5190#define B_BE_FWD_WLAN_CPU_TYPE_11_MASK GENMASK(27, 26)
5191#define B_BE_FWD_WLAN_CPU_TYPE_10_MASK GENMASK(25, 24)
5192#define B_BE_FWD_WLAN_CPU_TYPE_9_MASK GENMASK(23, 22)
5193#define B_BE_FWD_WLAN_CPU_TYPE_8_MASK GENMASK(21, 20)
5194#define B_BE_FWD_WLAN_CPU_TYPE_7_MASK GENMASK(19, 18)
5195#define B_BE_FWD_WLAN_CPU_TYPE_6_MASK GENMASK(17, 16)
5196#define B_BE_FWD_WLAN_CPU_TYPE_5_MASK GENMASK(15, 14)
5197#define B_BE_FWD_WLAN_CPU_TYPE_4_MASK GENMASK(13, 12)
5198#define B_BE_FWD_WLAN_CPU_TYPE_3_MASK GENMASK(11, 10)
5199#define B_BE_FWD_WLAN_CPU_TYPE_2_MASK GENMASK(9, 8)
5200#define B_BE_FWD_WLAN_CPU_TYPE_1_MASK GENMASK(7, 6)
5201#define B_BE_FWD_WLAN_CPU_TYPE_0_CTL_MASK GENMASK(5, 4)
5202#define B_BE_FWD_WLAN_CPU_TYPE_0_MNG_MASK GENMASK(3, 2)
5203#define B_BE_FWD_WLAN_CPU_TYPE_0_DATA_MASK GENMASK(1, 0)
5204
5205#define R_BE_WDE_PKTBUF_CFG 0x8C08
5206#define B_BE_WDE_FREE_PAGE_NUM_MASK GENMASK(28, 16)
5207#define B_BE_WDE_START_BOUND_MASK GENMASK(14, 8)
5208#define B_BE_WDE_PAGE_SEL_MASK GENMASK(1, 0)
5209
5210#define R_BE_WDE_BUFMGN_CTL 0x8C10
5211#define B_BE_WDE_AVAL_UPD_REQ BIT(29)
5212#define B_BE_WDE_AVAL_UPD_QTAID_MASK GENMASK(27, 24)
5213#define B_BE_WDE_BUFMGN_FRZTMR_MODE BIT(0)
5214
5215#define R_BE_WDE_ERR_IMR 0x8C38
5216#define B_BE_WDE_DATCHN_CAMREQ_ERR_INT_EN BIT(29)
5217#define B_BE_WDE_DATCHN_ADRERR_ERR_INT_EN BIT(28)
5218#define B_BE_WDE_DATCHN_RRDY_ERR_INT_EN BIT(27)
5219#define B_BE_WDE_DATCHN_FRZTO_ERR_INT_EN BIT(26)
5220#define B_BE_WDE_DATCHN_NULLPG_ERR_INT_EN BIT(25)
5221#define B_BE_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24)
5222#define B_BE_WDE_QUEMGN_FRZTO_ERR_INT_EN BIT(23)
5223#define B_BE_WDE_NXTPKTLL_AD_ERR_INT_EN BIT(22)
5224#define B_BE_WDE_PREPKTLLT_AD_ERR_INT_EN BIT(21)
5225#define B_BE_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(20)
5226#define B_BE_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(19)
5227#define B_BE_WDE_QUE_SRCQUEID_ERR_INT_EN BIT(18)
5228#define B_BE_WDE_QUE_DSTQUEID_ERR_INT_EN BIT(17)
5229#define B_BE_WDE_QUE_CMDTYPE_ERR_INT_EN BIT(16)
5230#define B_BE_WDE_BUFMGN_MRG_SZLMT_ERR_INT_EN BIT(13)
5231#define B_BE_WDE_BUFMGN_MRG_QTAID_ERR_INT_EN BIT(12)
5232#define B_BE_WDE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN BIT(11)
5233#define B_BE_WDE_ERR_BUFMGN_MRG_STRPKTID_ERR_INT_EN BIT(10)
5234#define B_BE_WDE_BUFMGN_FRZTO_ERR_INT_EN BIT(9)
5235#define B_BE_WDE_GETNPG_PGOFST_ERR_INT_EN BIT(8)
5236#define B_BE_WDE_GETNPG_STRPG_ERR_INT_EN BIT(7)
5237#define B_BE_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(6)
5238#define B_BE_WDE_BUFRTN_SIZE_ERR_INT_EN BIT(5)
5239#define B_BE_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(4)
5240#define B_BE_WDE_BUFREQ_UNAVAL_ERR_INT_EN BIT(3)
5241#define B_BE_WDE_BUFREQ_SIZELMT_INT_EN BIT(2)
5242#define B_BE_WDE_BUFREQ_SIZE0_INT_EN BIT(1)
5243#define B_BE_WDE_BUFREQ_QTAID_ERR_INT_EN BIT(0)
5244#define B_BE_WDE_ERR_IMR_CLR (B_BE_WDE_BUFREQ_QTAID_ERR_INT_EN | \
5245			      B_BE_WDE_BUFREQ_SIZE0_INT_EN | \
5246			      B_BE_WDE_BUFREQ_SIZELMT_INT_EN | \
5247			      B_BE_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \
5248			      B_BE_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
5249			      B_BE_WDE_BUFRTN_SIZE_ERR_INT_EN | \
5250			      B_BE_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
5251			      B_BE_WDE_GETNPG_STRPG_ERR_INT_EN | \
5252			      B_BE_WDE_GETNPG_PGOFST_ERR_INT_EN | \
5253			      B_BE_WDE_BUFMGN_FRZTO_ERR_INT_EN | \
5254			      B_BE_WDE_ERR_BUFMGN_MRG_STRPKTID_ERR_INT_EN | \
5255			      B_BE_WDE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN | \
5256			      B_BE_WDE_BUFMGN_MRG_QTAID_ERR_INT_EN | \
5257			      B_BE_WDE_BUFMGN_MRG_SZLMT_ERR_INT_EN | \
5258			      B_BE_WDE_QUE_CMDTYPE_ERR_INT_EN | \
5259			      B_BE_WDE_QUE_DSTQUEID_ERR_INT_EN | \
5260			      B_BE_WDE_QUE_SRCQUEID_ERR_INT_EN | \
5261			      B_BE_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
5262			      B_BE_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
5263			      B_BE_WDE_PREPKTLLT_AD_ERR_INT_EN | \
5264			      B_BE_WDE_NXTPKTLL_AD_ERR_INT_EN | \
5265			      B_BE_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
5266			      B_BE_WDE_DATCHN_ARBT_ERR_INT_EN | \
5267			      B_BE_WDE_DATCHN_NULLPG_ERR_INT_EN | \
5268			      B_BE_WDE_DATCHN_FRZTO_ERR_INT_EN | \
5269			      B_BE_WDE_DATCHN_RRDY_ERR_INT_EN | \
5270			      B_BE_WDE_DATCHN_ADRERR_ERR_INT_EN | \
5271			      B_BE_WDE_DATCHN_CAMREQ_ERR_INT_EN)
5272#define B_BE_WDE_ERR_IMR_SET (B_BE_WDE_BUFREQ_QTAID_ERR_INT_EN | \
5273			      B_BE_WDE_BUFREQ_SIZE0_INT_EN | \
5274			      B_BE_WDE_BUFREQ_SIZELMT_INT_EN | \
5275			      B_BE_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \
5276			      B_BE_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
5277			      B_BE_WDE_BUFRTN_SIZE_ERR_INT_EN | \
5278			      B_BE_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
5279			      B_BE_WDE_GETNPG_STRPG_ERR_INT_EN | \
5280			      B_BE_WDE_GETNPG_PGOFST_ERR_INT_EN | \
5281			      B_BE_WDE_BUFMGN_FRZTO_ERR_INT_EN | \
5282			      B_BE_WDE_ERR_BUFMGN_MRG_STRPKTID_ERR_INT_EN | \
5283			      B_BE_WDE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN | \
5284			      B_BE_WDE_BUFMGN_MRG_QTAID_ERR_INT_EN | \
5285			      B_BE_WDE_BUFMGN_MRG_SZLMT_ERR_INT_EN | \
5286			      B_BE_WDE_QUE_CMDTYPE_ERR_INT_EN | \
5287			      B_BE_WDE_QUE_DSTQUEID_ERR_INT_EN | \
5288			      B_BE_WDE_QUE_SRCQUEID_ERR_INT_EN | \
5289			      B_BE_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
5290			      B_BE_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
5291			      B_BE_WDE_PREPKTLLT_AD_ERR_INT_EN | \
5292			      B_BE_WDE_NXTPKTLL_AD_ERR_INT_EN | \
5293			      B_BE_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
5294			      B_BE_WDE_DATCHN_ARBT_ERR_INT_EN | \
5295			      B_BE_WDE_DATCHN_NULLPG_ERR_INT_EN | \
5296			      B_BE_WDE_DATCHN_FRZTO_ERR_INT_EN | \
5297			      B_BE_WDE_DATCHN_RRDY_ERR_INT_EN | \
5298			      B_BE_WDE_DATCHN_ADRERR_ERR_INT_EN | \
5299			      B_BE_WDE_DATCHN_CAMREQ_ERR_INT_EN)
5300
5301#define R_BE_WDE_QTA0_CFG 0x8C40
5302#define B_BE_WDE_Q0_MAX_SIZE_MASK GENMASK(27, 16)
5303#define B_BE_WDE_Q0_MIN_SIZE_MASK GENMASK(11, 0)
5304
5305#define R_BE_WDE_QTA1_CFG 0x8C44
5306#define B_BE_WDE_Q1_MAX_SIZE_MASK GENMASK(27, 16)
5307#define B_BE_WDE_Q1_MIN_SIZE_MASK GENMASK(11, 0)
5308
5309#define R_BE_WDE_QTA2_CFG 0x8C48
5310#define B_BE_WDE_Q2_MAX_SIZE_MASK GENMASK(27, 16)
5311#define B_BE_WDE_Q2_MIN_SIZE_MASK GENMASK(11, 0)
5312
5313#define R_BE_WDE_QTA3_CFG 0x8C4C
5314#define B_BE_WDE_Q3_MAX_SIZE_MASK GENMASK(27, 16)
5315#define B_BE_WDE_Q3_MIN_SIZE_MASK GENMASK(11, 0)
5316
5317#define R_BE_WDE_QTA4_CFG 0x8C50
5318#define B_BE_WDE_Q4_MAX_SIZE_MASK GENMASK(27, 16)
5319#define B_BE_WDE_Q4_MIN_SIZE_MASK GENMASK(11, 0)
5320
5321#define R_BE_WDE_ERR1_IMR 0x8CC0
5322#define B_BE_WDE_QUEMGN_CMACACQ_DEQNTFY_INT_EN BIT(8)
5323#define B_BE_WDE_ERR1_IMR_CLR B_BE_WDE_QUEMGN_CMACACQ_DEQNTFY_INT_EN
5324#define B_BE_WDE_ERR1_IMR_SET B_BE_WDE_QUEMGN_CMACACQ_DEQNTFY_INT_EN
5325
5326#define R_BE_PLE_PKTBUF_CFG 0x9008
5327#define B_BE_PLE_FREE_PAGE_NUM_MASK GENMASK(28, 16)
5328#define B_BE_PLE_START_BOUND_MASK GENMASK(14, 8)
5329#define B_BE_PLE_PAGE_SEL_MASK GENMASK(1, 0)
5330
5331#define R_BE_PLE_BUFMGN_CTL 0x9010
5332#define B_BE_PLE_AVAL_UPD_REQ BIT(29)
5333#define B_BE_PLE_AVAL_UPD_QTAID_MASK GENMASK(27, 24)
5334#define B_BE_PLE_BUFMGN_FRZTMR_MODE BIT(0)
5335
5336#define R_BE_PLE_ERR_IMR 0x9038
5337#define B_BE_PLE_DATCHN_CAMREQ_ERR_INT_EN BIT(29)
5338#define B_BE_PLE_DATCHN_ADRERR_ERR_INT_EN BIT(28)
5339#define B_BE_PLE_DATCHN_RRDY_ERR_INT_EN BIT(27)
5340#define B_BE_PLE_DATCHN_FRZTO_ERR_INT_EN BIT(26)
5341#define B_BE_PLE_DATCHN_NULLPG_ERR_INT_EN BIT(25)
5342#define B_BE_PLE_DATCHN_ARBT_ERR_INT_EN BIT(24)
5343#define B_BE_PLE_QUEMGN_FRZTO_ERR_INT_EN BIT(23)
5344#define B_BE_PLE_NXTPKTLL_AD_ERR_INT_EN BIT(22)
5345#define B_BE_PLE_PREPKTLLT_AD_ERR_INT_EN BIT(21)
5346#define B_BE_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(20)
5347#define B_BE_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(19)
5348#define B_BE_PLE_QUE_SRCQUEID_ERR_INT_EN BIT(18)
5349#define B_BE_PLE_QUE_DSTQUEID_ERR_INT_EN BIT(17)
5350#define B_BE_PLE_QUE_CMDTYPE_ERR_INT_EN BIT(16)
5351#define B_BE_PLE_BUFMGN_MRG_SZLMT_ERR_INT_EN BIT(13)
5352#define B_BE_PLE_BUFMGN_MRG_QTAID_ERR_INT_EN BIT(12)
5353#define B_BE_PLE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN BIT(11)
5354#define B_BE_PLE_BUFMGN_MRG_STRPKTID_ERR_INT_EN BIT(10)
5355#define B_BE_PLE_BUFMGN_FRZTO_ERR_INT_EN BIT(9)
5356#define B_BE_PLE_GETNPG_PGOFST_ERR_INT_EN BIT(8)
5357#define B_BE_PLE_GETNPG_STRPG_ERR_INT_EN BIT(7)
5358#define B_BE_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(6)
5359#define B_BE_PLE_BUFRTN_SIZE_ERR_INT_EN BIT(5)
5360#define B_BE_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(4)
5361#define B_BE_PLE_BUFREQ_UNAVAL_ERR_INT_EN BIT(3)
5362#define B_BE_PLE_BUFREQ_SIZELMT_INT_EN BIT(2)
5363#define B_BE_PLE_BUFREQ_SIZE0_INT_EN BIT(1)
5364#define B_BE_PLE_BUFREQ_QTAID_ERR_INT_EN BIT(0)
5365#define B_BE_PLE_ERR_IMR_CLR (B_BE_PLE_BUFREQ_QTAID_ERR_INT_EN | \
5366			      B_BE_PLE_BUFREQ_SIZE0_INT_EN | \
5367			      B_BE_PLE_BUFREQ_SIZELMT_INT_EN | \
5368			      B_BE_PLE_BUFREQ_UNAVAL_ERR_INT_EN | \
5369			      B_BE_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
5370			      B_BE_PLE_BUFRTN_SIZE_ERR_INT_EN | \
5371			      B_BE_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
5372			      B_BE_PLE_GETNPG_STRPG_ERR_INT_EN | \
5373			      B_BE_PLE_GETNPG_PGOFST_ERR_INT_EN | \
5374			      B_BE_PLE_BUFMGN_FRZTO_ERR_INT_EN | \
5375			      B_BE_PLE_BUFMGN_MRG_STRPKTID_ERR_INT_EN | \
5376			      B_BE_PLE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN | \
5377			      B_BE_PLE_BUFMGN_MRG_QTAID_ERR_INT_EN | \
5378			      B_BE_PLE_BUFMGN_MRG_SZLMT_ERR_INT_EN | \
5379			      B_BE_PLE_QUE_CMDTYPE_ERR_INT_EN | \
5380			      B_BE_PLE_QUE_DSTQUEID_ERR_INT_EN | \
5381			      B_BE_PLE_QUE_SRCQUEID_ERR_INT_EN | \
5382			      B_BE_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
5383			      B_BE_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
5384			      B_BE_PLE_PREPKTLLT_AD_ERR_INT_EN | \
5385			      B_BE_PLE_NXTPKTLL_AD_ERR_INT_EN | \
5386			      B_BE_PLE_QUEMGN_FRZTO_ERR_INT_EN | \
5387			      B_BE_PLE_DATCHN_ARBT_ERR_INT_EN | \
5388			      B_BE_PLE_DATCHN_NULLPG_ERR_INT_EN | \
5389			      B_BE_PLE_DATCHN_FRZTO_ERR_INT_EN | \
5390			      B_BE_PLE_DATCHN_RRDY_ERR_INT_EN | \
5391			      B_BE_PLE_DATCHN_ADRERR_ERR_INT_EN | \
5392			      B_BE_PLE_DATCHN_CAMREQ_ERR_INT_EN)
5393#define B_BE_PLE_ERR_IMR_SET (B_BE_PLE_BUFREQ_QTAID_ERR_INT_EN | \
5394			      B_BE_PLE_BUFREQ_SIZE0_INT_EN | \
5395			      B_BE_PLE_BUFREQ_SIZELMT_INT_EN | \
5396			      B_BE_PLE_BUFREQ_UNAVAL_ERR_INT_EN | \
5397			      B_BE_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
5398			      B_BE_PLE_BUFRTN_SIZE_ERR_INT_EN | \
5399			      B_BE_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
5400			      B_BE_PLE_GETNPG_STRPG_ERR_INT_EN | \
5401			      B_BE_PLE_GETNPG_PGOFST_ERR_INT_EN | \
5402			      B_BE_PLE_BUFMGN_FRZTO_ERR_INT_EN | \
5403			      B_BE_PLE_BUFMGN_MRG_STRPKTID_ERR_INT_EN | \
5404			      B_BE_PLE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN | \
5405			      B_BE_PLE_BUFMGN_MRG_QTAID_ERR_INT_EN | \
5406			      B_BE_PLE_BUFMGN_MRG_SZLMT_ERR_INT_EN | \
5407			      B_BE_PLE_QUE_CMDTYPE_ERR_INT_EN | \
5408			      B_BE_PLE_QUE_DSTQUEID_ERR_INT_EN | \
5409			      B_BE_PLE_QUE_SRCQUEID_ERR_INT_EN | \
5410			      B_BE_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
5411			      B_BE_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
5412			      B_BE_PLE_PREPKTLLT_AD_ERR_INT_EN | \
5413			      B_BE_PLE_NXTPKTLL_AD_ERR_INT_EN | \
5414			      B_BE_PLE_QUEMGN_FRZTO_ERR_INT_EN | \
5415			      B_BE_PLE_DATCHN_ARBT_ERR_INT_EN | \
5416			      B_BE_PLE_DATCHN_NULLPG_ERR_INT_EN | \
5417			      B_BE_PLE_DATCHN_FRZTO_ERR_INT_EN | \
5418			      B_BE_PLE_DATCHN_RRDY_ERR_INT_EN | \
5419			      B_BE_PLE_DATCHN_ADRERR_ERR_INT_EN | \
5420			      B_BE_PLE_DATCHN_CAMREQ_ERR_INT_EN)
5421
5422#define R_BE_PLE_QTA0_CFG 0x9040
5423#define B_BE_PLE_Q0_MAX_SIZE_MASK GENMASK(27, 16)
5424#define B_BE_PLE_Q0_MIN_SIZE_MASK GENMASK(11, 0)
5425
5426#define R_BE_PLE_QTA1_CFG 0x9044
5427#define B_BE_PLE_Q1_MAX_SIZE_MASK GENMASK(27, 16)
5428#define B_BE_PLE_Q1_MIN_SIZE_MASK GENMASK(11, 0)
5429
5430#define R_BE_PLE_QTA2_CFG 0x9048
5431#define B_BE_PLE_Q2_MAX_SIZE_MASK GENMASK(27, 16)
5432#define B_BE_PLE_Q2_MIN_SIZE_MASK GENMASK(11, 0)
5433
5434#define R_BE_PLE_QTA3_CFG 0x904C
5435#define B_BE_PLE_Q3_MAX_SIZE_MASK GENMASK(27, 16)
5436#define B_BE_PLE_Q3_MIN_SIZE_MASK GENMASK(11, 0)
5437
5438#define R_BE_PLE_QTA4_CFG 0x9050
5439#define B_BE_PLE_Q4_MAX_SIZE_MASK GENMASK(27, 16)
5440#define B_BE_PLE_Q4_MIN_SIZE_MASK GENMASK(11, 0)
5441
5442#define R_BE_PLE_QTA5_CFG 0x9054
5443#define B_BE_PLE_Q5_MAX_SIZE_MASK GENMASK(27, 16)
5444#define B_BE_PLE_Q5_MIN_SIZE_MASK GENMASK(11, 0)
5445
5446#define R_BE_PLE_QTA6_CFG 0x9058
5447#define B_BE_PLE_Q6_MAX_SIZE_MASK GENMASK(27, 16)
5448#define B_BE_PLE_Q6_MIN_SIZE_MASK GENMASK(11, 0)
5449
5450#define R_BE_PLE_QTA7_CFG 0x905C
5451#define B_BE_PLE_Q7_MAX_SIZE_MASK GENMASK(27, 16)
5452#define B_BE_PLE_Q7_MIN_SIZE_MASK GENMASK(11, 0)
5453
5454#define R_BE_PLE_QTA8_CFG 0x9060
5455#define B_BE_PLE_Q8_MAX_SIZE_MASK GENMASK(27, 16)
5456#define B_BE_PLE_Q8_MIN_SIZE_MASK GENMASK(11, 0)
5457
5458#define R_BE_PLE_QTA9_CFG 0x9064
5459#define B_BE_PLE_Q9_MAX_SIZE_MASK GENMASK(27, 16)
5460#define B_BE_PLE_Q9_MIN_SIZE_MASK GENMASK(11, 0)
5461
5462#define R_BE_PLE_QTA10_CFG 0x9068
5463#define B_BE_PLE_Q10_MAX_SIZE_MASK GENMASK(27, 16)
5464#define B_BE_PLE_Q10_MIN_SIZE_MASK GENMASK(11, 0)
5465
5466#define R_BE_PLE_QTA11_CFG 0x906C
5467#define B_BE_PLE_Q11_MAX_SIZE_MASK GENMASK(27, 16)
5468#define B_BE_PLE_Q11_MIN_SIZE_MASK GENMASK(11, 0)
5469
5470#define R_BE_PLE_QTA12_CFG 0x9070
5471#define B_BE_PLE_Q12_MAX_SIZE_MASK GENMASK(27, 16)
5472#define B_BE_PLE_Q12_MIN_SIZE_MASK GENMASK(11, 0)
5473
5474#define R_BE_PLE_ERRFLAG1_IMR 0x90C0
5475#define B_BE_PLE_SRCHPG_PGOFST_IMR BIT(26)
5476#define B_BE_PLE_SRCHPG_STRPG_IMR BIT(25)
5477#define B_BE_PLE_SRCHPG_FRZTO_IMR BIT(24)
5478#define B_BE_PLE_ERRFLAG1_IMR_CLR (B_BE_PLE_SRCHPG_FRZTO_IMR | \
5479				   B_BE_PLE_SRCHPG_STRPG_IMR | \
5480				   B_BE_PLE_SRCHPG_PGOFST_IMR)
5481#define B_BE_PLE_ERRFLAG1_IMR_SET (B_BE_PLE_SRCHPG_FRZTO_IMR | \
5482				   B_BE_PLE_SRCHPG_STRPG_IMR | \
5483				   B_BE_PLE_SRCHPG_PGOFST_IMR)
5484
5485#define R_BE_PLE_DBG_FUN_INTF_CTL 0x9110
5486#define B_BE_PLE_DFI_ACTIVE BIT(31)
5487#define B_BE_PLE_DFI_TRGSEL_MASK GENMASK(19, 16)
5488#define B_BE_PLE_DFI_ADDR_MASK GENMASK(15, 0)
5489
5490#define R_BE_PLE_DBG_FUN_INTF_DATA 0x9114
5491#define B_BE_PLE_DFI_DATA_MASK GENMASK(31, 0)
5492
5493#define R_BE_WDRLS_CFG 0x9408
5494#define B_BE_WDRLS_DIS_AGAC BIT(31)
5495#define B_BE_RLSRPT_BUFREQ_TO_MASK GENMASK(15, 8)
5496#define B_BE_RLSRPT_BUFREQ_TO_SEL_MASK GENMASK(7, 6)
5497#define B_BE_WDRLS_MODE_MASK GENMASK(1, 0)
5498
5499#define R_BE_WDRLS_ERR_IMR 0x9430
5500#define B_BE_WDRLS_RPT3_FRZTO_ERR_INT_EN BIT(21)
5501#define B_BE_WDRLS_RPT3_AGGNUM0_ERR_INT_EN BIT(20)
5502#define B_BE_WDRLS_RPT2_FRZTO_ERR_INT_EN BIT(17)
5503#define B_BE_WDRLS_RPT2_AGGNUM0_ERR_INT_EN BIT(16)
5504#define B_BE_WDRLS_RPT1_FRZTO_ERR_INT_EN BIT(13)
5505#define B_BE_WDRLS_RPT1_AGGNUM0_ERR_INT_EN BIT(12)
5506#define B_BE_WDRLS_RPT0_FRZTO_ERR_INT_EN BIT(9)
5507#define B_BE_WDRLS_RPT0_AGGNUM0_ERR_INT_EN BIT(8)
5508#define B_BE_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN BIT(5)
5509#define B_BE_WDRLS_PLEBREQ_TO_ERR_INT_EN BIT(4)
5510#define B_BE_WDRLS_CTL_FRZTO_ERR_INT_EN BIT(2)
5511#define B_BE_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN BIT(1)
5512#define B_BE_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN BIT(0)
5513#define B_BE_WDRLS_ERR_IMR_CLR (B_BE_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \
5514				B_BE_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \
5515				B_BE_WDRLS_CTL_FRZTO_ERR_INT_EN | \
5516				B_BE_WDRLS_PLEBREQ_TO_ERR_INT_EN | \
5517				B_BE_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \
5518				B_BE_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \
5519				B_BE_WDRLS_RPT0_FRZTO_ERR_INT_EN | \
5520				B_BE_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \
5521				B_BE_WDRLS_RPT1_FRZTO_ERR_INT_EN)
5522#define B_BE_WDRLS_ERR_IMR_SET (B_BE_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \
5523				B_BE_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \
5524				B_BE_WDRLS_CTL_FRZTO_ERR_INT_EN | \
5525				B_BE_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \
5526				B_BE_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \
5527				B_BE_WDRLS_RPT0_FRZTO_ERR_INT_EN | \
5528				B_BE_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \
5529				B_BE_WDRLS_RPT1_FRZTO_ERR_INT_EN)
5530
5531#define R_BE_RLSRPT0_CFG1 0x9444
5532#define B_BE_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24)
5533#define S_BE_WDRLS_FLTR_TXOK 1
5534#define S_BE_WDRLS_FLTR_RTYLMT 2
5535#define S_BE_WDRLS_FLTR_LIFTIM 4
5536#define S_BE_WDRLS_FLTR_MACID 8
5537#define B_BE_RLSRPT0_TO_MASK GENMASK(23, 16)
5538#define B_BE_RLSRPT0_AGGNUM_MASK GENMASK(7, 0)
5539
5540#define R_BE_BBRPT_COM_ERR_IMR 0x9608
5541#define B_BE_BBRPT_COM_EVT01_ISR_EN BIT(1)
5542#define B_BE_BBRPT_COM_NULL_PLPKTID_ISR_EN BIT(0)
5543#define B_BE_BBRPT_COM_ERR_IMR_CLR (B_BE_BBRPT_COM_NULL_PLPKTID_ISR_EN | \
5544				    B_BE_BBRPT_COM_EVT01_ISR_EN)
5545#define B_BE_BBRPT_COM_ERR_IMR_SET B_BE_BBRPT_COM_NULL_PLPKTID_ISR_EN
5546
5547#define R_BE_BBRPT_CHINFO_ERR_IMR 0x9628
5548#define B_BE_ERR_BB_ONETEN_INT_EN BIT(1)
5549#define B_BE_ERR_GEN_FRZTO_INT_EN BIT(0)
5550#define B_BE_BBRPT_CHINFO_ERR_IMR_CLR (B_BE_ERR_GEN_FRZTO_INT_EN | \
5551				       B_BE_ERR_BB_ONETEN_INT_EN)
5552#define B_BE_BBRPT_CHINFO_ERR_IMR_SET (B_BE_ERR_GEN_FRZTO_INT_EN | \
5553				       B_BE_ERR_BB_ONETEN_INT_EN)
5554
5555#define R_BE_BBRPT_DFS_ERR_IMR 0x9638
5556#define B_BE_BBRPT_DFS_TO_ERR_INT_EN BIT(0)
5557#define B_BE_BBRPT_DFS_ERR_IMR_CLR B_BE_BBRPT_DFS_TO_ERR_INT_EN
5558#define B_BE_BBRPT_DFS_ERR_IMR_SET B_BE_BBRPT_DFS_TO_ERR_INT_EN
5559
5560#define R_BE_LA_ERRFLAG_IMR 0x9668
5561#define B_BE_LA_IMR_DATA_LOSS BIT(0)
5562#define B_BE_LA_ERRFLAG_IMR_CLR B_BE_LA_IMR_DATA_LOSS
5563#define B_BE_LA_ERRFLAG_IMR_SET B_BE_LA_IMR_DATA_LOSS
5564
5565#define R_BE_LA_ERRFLAG_ISR 0x966C
5566#define B_BE_LA_ISR_DATA_LOSS BIT(0)
5567
5568#define R_BE_CH_INFO_DBGFLAG_IMR 0x9688
5569#define B_BE_BCHN_EVT01_ISR_EN BIT(29)
5570#define B_BE_BCHN_REQTO_ISR_EN BIT(28)
5571#define B_BE_CHIF_RXDATA_AFACT_ISR_EN BIT(11)
5572#define B_BE_CHIF_RXDATA_BFACT_ISR_EN BIT(10)
5573#define B_BE_CHIF_HDR_SEGLEN_ISR_EN BIT(9)
5574#define B_BE_CHIF_HDR_INVLD_ISR_EN BIT(8)
5575#define B_BE_CHIF_BBONL_BFACT_ISR_EN BIT(4)
5576#define B_BE_CHIF_RPT_OVF_ISR_EN BIT(3)
5577#define B_BE_DBG_CHIF_DATA_LOSS_ISR_EN BIT(2)
5578#define B_BE_CHIF_DATA_WTOUT_ISR_EN BIT(1)
5579#define B_BE_CHIF_RPT_WTOUT_ISR_EN BIT(0)
5580#define B_BE_CH_INFO_DBGFLAG_IMR_CLR (B_BE_CHIF_RPT_WTOUT_ISR_EN | \
5581				      B_BE_CHIF_DATA_WTOUT_ISR_EN | \
5582				      B_BE_DBG_CHIF_DATA_LOSS_ISR_EN | \
5583				      B_BE_CHIF_RPT_OVF_ISR_EN | \
5584				      B_BE_CHIF_HDR_INVLD_ISR_EN | \
5585				      B_BE_CHIF_HDR_SEGLEN_ISR_EN | \
5586				      B_BE_CHIF_RXDATA_BFACT_ISR_EN | \
5587				      B_BE_CHIF_RXDATA_AFACT_ISR_EN)
5588#define B_BE_CH_INFO_DBGFLAG_IMR_SET 0
5589
5590#define R_BE_WD_BUF_REQ 0x9800
5591#define B_BE_WD_BUF_REQ_EXEC BIT(31)
5592#define B_BE_WD_BUF_REQ_QUOTA_ID_MASK GENMASK(23, 16)
5593#define B_BE_WD_BUF_REQ_LEN_MASK GENMASK(15, 0)
5594
5595#define R_BE_WD_BUF_STATUS 0x9804
5596#define B_BE_WD_BUF_STAT_DONE BIT(31)
5597#define B_BE_WD_BUF_STAT_PKTID_MASK GENMASK(11, 0)
5598
5599#define R_BE_WD_CPUQ_OP_0 0x9810
5600#define B_BE_WD_CPUQ_OP_EXEC BIT(31)
5601#define B_BE_WD_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24)
5602#define B_BE_WD_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0)
5603
5604#define R_BE_WD_CPUQ_OP_1 0x9814
5605#define B_BE_WD_CPUQ_OP_SRC_MACID_MASK GENMASK(19, 12)
5606#define B_BE_WD_CPUQ_OP_SRC_QID_MASK GENMASK(9, 4)
5607#define B_BE_WD_CPUQ_OP_SRC_PID_MASK GENMASK(2, 0)
5608
5609#define R_BE_WD_CPUQ_OP_2 0x9818
5610#define B_BE_WD_CPUQ_OP_DST_MACID_MASK GENMASK(19, 12)
5611#define B_BE_WD_CPUQ_OP_DST_QID_MASK GENMASK(9, 4)
5612#define B_BE_WD_CPUQ_OP_DST_PID_MASK GENMASK(2, 0)
5613
5614#define R_BE_WD_CPUQ_OP_3 0x981C
5615#define B_BE_WD_CPUQ_OP_STRT_PKTID_MASK GENMASK(27, 16)
5616#define B_BE_WD_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0)
5617
5618#define R_BE_WD_CPUQ_OP_STATUS 0x9820
5619#define B_BE_WD_CPUQ_OP_STAT_DONE BIT(31)
5620#define B_BE_WD_CPUQ_OP_PKTCNT_MASK GENMASK(27, 16)
5621#define B_BE_WD_CPUQ_OP_PKTID_MASK GENMASK(11, 0)
5622
5623#define R_BE_PL_BUF_REQ 0x9840
5624#define B_BE_PL_BUF_REQ_EXEC BIT(31)
5625#define B_BE_PL_BUF_REQ_QUOTA_ID_MASK GENMASK(19, 16)
5626#define B_BE_PL_BUF_REQ_LEN_MASK GENMASK(15, 0)
5627
5628#define R_BE_PL_BUF_STATUS 0x9844
5629#define B_BE_PL_BUF_STAT_DONE BIT(31)
5630#define B_BE_PL_BUF_STAT_PKTID_MASK GENMASK(11, 0)
5631
5632#define R_BE_PL_CPUQ_OP_0 0x9850
5633#define B_BE_PL_CPUQ_OP_EXEC BIT(31)
5634#define B_BE_PL_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24)
5635#define B_BE_PL_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0)
5636
5637#define R_BE_PL_CPUQ_OP_1 0x9854
5638#define B_BE_PL_CPUQ_OP_SRC_MACID_MASK GENMASK(19, 12)
5639#define B_BE_PL_CPUQ_OP_SRC_QID_MASK GENMASK(9, 4)
5640#define B_BE_PL_CPUQ_OP_SRC_PID_MASK GENMASK(2, 0)
5641
5642#define R_BE_PL_CPUQ_OP_2 0x9858
5643#define B_BE_PL_CPUQ_OP_DST_MACID_MASK GENMASK(19, 12)
5644#define B_BE_PL_CPUQ_OP_DST_QID_MASK GENMASK(9, 4)
5645#define B_BE_PL_CPUQ_OP_DST_PID_MASK GENMASK(2, 0)
5646
5647#define R_BE_PL_CPUQ_OP_3 0x985C
5648#define B_BE_PL_CPUQ_OP_STRT_PKTID_MASK GENMASK(27, 16)
5649#define B_BE_PL_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0)
5650
5651#define R_BE_PL_CPUQ_OP_STATUS 0x9860
5652#define B_BE_PL_CPUQ_OP_STAT_DONE BIT(31)
5653#define B_BE_PL_CPUQ_OP_PKTCNT_MASK GENMASK(27, 16)
5654#define B_BE_PL_CPUQ_OP_PKTID_MASK GENMASK(11, 0)
5655
5656#define R_BE_CPUIO_ERR_IMR 0x9888
5657#define B_BE_PLEQUE_OP_ERR_INT_EN BIT(12)
5658#define B_BE_PLEBUF_OP_ERR_INT_EN BIT(8)
5659#define B_BE_WDEQUE_OP_ERR_INT_EN BIT(4)
5660#define B_BE_WDEBUF_OP_ERR_INT_EN BIT(0)
5661#define B_BE_CPUIO_ERR_IMR_CLR (B_BE_WDEBUF_OP_ERR_INT_EN | \
5662				B_BE_WDEQUE_OP_ERR_INT_EN | \
5663				B_BE_PLEBUF_OP_ERR_INT_EN | \
5664				B_BE_PLEQUE_OP_ERR_INT_EN)
5665#define B_BE_CPUIO_ERR_IMR_SET (B_BE_WDEBUF_OP_ERR_INT_EN | \
5666				B_BE_WDEQUE_OP_ERR_INT_EN | \
5667				B_BE_PLEBUF_OP_ERR_INT_EN | \
5668				B_BE_PLEQUE_OP_ERR_INT_EN)
5669
5670#define R_BE_PKTIN_ERR_IMR 0x9A20
5671#define B_BE_SW_MERGE_ERR_INT_EN BIT(1)
5672#define B_BE_GET_NULL_PKTID_ERR_INT_EN BIT(0)
5673#define B_BE_PKTIN_ERR_IMR_CLR (B_BE_SW_MERGE_ERR_INT_EN | \
5674				B_BE_GET_NULL_PKTID_ERR_INT_EN)
5675#define B_BE_PKTIN_ERR_IMR_SET (B_BE_SW_MERGE_ERR_INT_EN | \
5676				B_BE_GET_NULL_PKTID_ERR_INT_EN)
5677
5678#define R_BE_HDR_SHCUT_SETTING 0x9B00
5679#define B_BE_TX_ADDR_MLD_TO_LIK BIT(4)
5680#define B_BE_TX_HW_SEC_HDR_EN BIT(3)
5681#define B_BE_TX_MAC_MPDU_PROC_EN BIT(2)
5682#define B_BE_TX_HW_ACK_POLICY_EN BIT(1)
5683#define B_BE_TX_HW_SEQ_EN BIT(0)
5684
5685#define R_BE_MPDU_TX_ERR_IMR 0x9BF4
5686#define B_BE_TX_TIMEOUT_ERR_EN BIT(0)
5687#define B_BE_MPDU_TX_ERR_IMR_CLR B_BE_TX_TIMEOUT_ERR_EN
5688#define B_BE_MPDU_TX_ERR_IMR_SET 0
5689
5690#define R_BE_MPDU_PROC 0x9C00
5691#define B_BE_PORT_SEL BIT(29)
5692#define B_BE_WPKT_WLANCPU_QSEL_MASK GENMASK(28, 27)
5693#define B_BE_WPKT_DATACPU_QSEL_MASK GENMASK(26, 25)
5694#define B_BE_WPKT_FW_RLS BIT(24)
5695#define B_BE_FWD_RPKT_MASK GENMASK(23, 16)
5696#define B_BE_FWD_WPKT_MASK GENMASK(15, 8)
5697#define B_BE_RXFWD_PRIO_MASK GENMASK(5, 4)
5698#define B_BE_RXFWD_EN BIT(3)
5699#define B_BE_DROP_NONDMA_PPDU BIT(2)
5700#define B_BE_APPEND_FCS BIT(0)
5701
5702#define R_BE_FWD_ERR 0x9C10
5703#define R_BE_FWD_ACTN0 0x9C14
5704#define R_BE_FWD_ACTN1 0x9C18
5705#define R_BE_FWD_ACTN2 0x9C1C
5706#define R_BE_FWD_TF0 0x9C20
5707#define R_BE_FWD_TF1 0x9C24
5708
5709#define R_BE_HW_PPDU_STATUS 0x9C30
5710#define B_BE_FWD_RPKTTYPE_MASK GENMASK(31, 26)
5711#define B_BE_FWD_PPDU_PRTID_MASK GENMASK(25, 23)
5712#define B_BE_FWD_PPDU_FW_RLS BIT(22)
5713#define B_BE_FWD_PPDU_QUEID_MASK GENMASK(21, 16)
5714#define B_BE_FWD_OTHER_RPKT_MASK GENMASK(15, 8)
5715#define B_BE_FWD_PPDU_STAT_MASK GENMASK(7, 0)
5716
5717#define R_BE_CUT_AMSDU_CTRL 0x9C94
5718#define B_BE_EN_CUT_AMSDU BIT(31)
5719#define B_BE_CUT_AMSDU_CHKLEN_EN BIT(30)
5720#define B_BE_CA_CHK_ADDRCAM_EN BIT(29)
5721#define B_BE_MPDU_CUT_CTRL_EN BIT(24)
5722#define B_BE_CUT_AMSDU_CHKLEN_L_TH_MASK GENMASK(23, 16)
5723#define B_BE_CUT_AMSDU_CHKLEN_H_TH_MASK GENMASK(15, 0)
5724
5725#define R_BE_WOW_CTRL 0x9CB8
5726#define B_BE_WOW_HCI BIT(5)
5727#define B_BE_WOW_DROP BIT(2)
5728#define B_BE_WOW_WOWEN BIT(1)
5729#define B_BE_WOW_FORCE_WAKEUP BIT(0)
5730
5731#define R_BE_RX_HDRTRNS 0x9CC0
5732#define B_BE_RX_MGN_MLD_ADDR_EN BIT(6)
5733#define B_BE_HDR_INFO_MASK GENMASK(5, 4)
5734#define B_BE_HC_ADDR_HIT_EN BIT(3)
5735#define B_BE_RX_ADDR_LINK_TO_MLO BIT(2)
5736#define B_BE_HDR_CNV BIT(1)
5737#define B_BE_RX_HDR_CNV_EN BIT(0)
5738#define TRXCFG_MPDU_PROC_RX_HDR_CONV	0x00000000
5739
5740#define R_BE_MPDU_RX_ERR_IMR 0x9CF4
5741#define B_BE_LEN_ERR_IMR BIT(3)
5742#define B_BE_TIMEOUT_ERR_IMR BIT(1)
5743#define B_BE_MPDU_RX_ERR_IMR_CLR B_BE_TIMEOUT_ERR_IMR
5744#define B_BE_MPDU_RX_ERR_IMR_SET 0
5745
5746#define R_BE_SEC_ENG_CTRL 0x9D00
5747#define B_BE_SEC_ENG_EN BIT(31)
5748#define B_BE_CCMP_SPP_MIC BIT(30)
5749#define B_BE_CCMP_SPP_CTR BIT(29)
5750#define B_BE_SEC_CAM_ACC BIT(28)
5751#define B_BE_WMAC_SEC_PN_SEL_MASK GENMASK(27, 26)
5752#define B_BE_WMAC_SEC_MASKIV BIT(25)
5753#define B_BE_WAPI_SPEC BIT(24)
5754#define B_BE_REVERT_TA_RA_MLD_EN BIT(23)
5755#define B_BE_SEC_DBG_SEL_MASK GENMASK(19, 16)
5756#define B_BE_CAM_FORCE_CLK BIT(15)
5757#define B_BE_SEC_FORCE_CLK BIT(14)
5758#define B_BE_SEC_RX_SHORT_ADD_ICVERR BIT(13)
5759#define B_BE_SRAM_IO_PROT BIT(12)
5760#define B_BE_SEC_PRE_ENQUE_TX BIT(11)
5761#define B_BE_CLK_EN_CGCMP BIT(10)
5762#define B_BE_CLK_EN_WAPI BIT(9)
5763#define B_BE_CLK_EN_WEP_TKIP BIT(8)
5764#define B_BE_BMC_MGNT_DEC BIT(5)
5765#define B_BE_UC_MGNT_DEC BIT(4)
5766#define B_BE_MC_DEC BIT(3)
5767#define B_BE_BC_DEC BIT(2)
5768#define B_BE_SEC_RX_DEC BIT(1)
5769#define B_BE_SEC_TX_ENC BIT(0)
5770
5771#define R_BE_SEC_MPDU_PROC 0x9D04
5772#define B_BE_DBG_ENGINE_SEL BIT(8)
5773#define B_BE_STOP_RX_PKT_HANDLE BIT(7)
5774#define B_BE_STOP_TX_PKT_HANDLE BIT(6)
5775#define B_BE_QUEUE_FOWARD_SEL BIT(5)
5776#define B_BE_RESP1_PROTECT BIT(4)
5777#define B_BE_RESP0_PROTECT BIT(3)
5778#define B_BE_TX_ACTIVE_PROTECT BIT(2)
5779#define B_BE_APPEND_ICV BIT(1)
5780#define B_BE_APPEND_MIC BIT(0)
5781
5782#define R_BE_SEC_CAM_ACCESS 0x9D10
5783#define B_BE_SEC_TIME_OUT_MASK GENMASK(31, 16)
5784#define B_BE_SEC_CAM_POLL BIT(15)
5785#define B_BE_SEC_CAM_RW BIT(14)
5786#define B_BE_SEC_CAM_ACC_FAIL BIT(13)
5787#define B_BE_SEC_CAM_OFFSET_MASK GENMASK(10, 0)
5788
5789#define R_BE_SEC_CAM_RDATA 0x9D14
5790#define B_BE_SEC_CAM_RDATA_MASK GENMASK(31, 0)
5791
5792#define R_BE_SEC_DEBUG2 0x9D28
5793#define B_BE_DBG_READ_MASK GENMASK(31, 0)
5794
5795#define R_BE_SEC_ERROR_IMR 0x9D2C
5796#define B_BE_QUEUE_OPERATION_HANG_IMR BIT(4)
5797#define B_BE_SEC1_RX_HANG_IMR BIT(3)
5798#define B_BE_SEC1_TX_HANG_IMR BIT(2)
5799#define B_BE_RX_HANG_IMR BIT(1)
5800#define B_BE_TX_HANG_IMR BIT(0)
5801#define B_BE_SEC_ERROR_IMR_CLR (B_BE_TX_HANG_IMR | \
5802				B_BE_RX_HANG_IMR | \
5803				B_BE_SEC1_TX_HANG_IMR | \
5804				B_BE_SEC1_RX_HANG_IMR | \
5805				B_BE_QUEUE_OPERATION_HANG_IMR)
5806#define B_BE_SEC_ERROR_IMR_SET (B_BE_TX_HANG_IMR | \
5807				B_BE_RX_HANG_IMR | \
5808				B_BE_SEC1_TX_HANG_IMR | \
5809				B_BE_SEC1_RX_HANG_IMR | \
5810				B_BE_QUEUE_OPERATION_HANG_IMR)
5811
5812#define R_BE_SEC_ERROR_FLAG 0x9D30
5813#define B_BE_TXD_DIFF_KEYCAM_TYPE_ERROR BIT(5)
5814#define B_BE_QUEUE_OPERATION_HANG_ERROR BIT(4)
5815#define B_BE_SEC1_RX_HANG_ERROR BIT(3)
5816#define B_BE_SEC1_TX_HANG_ERROR BIT(2)
5817#define B_BE_RX_HANG_ERROR BIT(1)
5818#define B_BE_TX_HANG_ERROR BIT(0)
5819
5820#define R_BE_TXPKTCTL_MPDUINFO_CFG 0x9F10
5821#define B_BE_MPDUINFO_FEN BIT(31)
5822#define B_BE_MPDUINFO_PKTID_MASK GENMASK(27, 16)
5823#define B_BE_MPDUINFO_B1_BADDR_MASK GENMASK(5, 0)
5824#define MPDU_INFO_B1_OFST 18
5825
5826#define R_BE_TXPKTCTL_B0_PRELD_CFG0 0x9F48
5827#define B_BE_B0_PRELD_FEN BIT(31)
5828#define B_BE_B0_PRELD_USEMAXSZ_MASK GENMASK(25, 16)
5829#define B_BE_B0_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)
5830#define B_BE_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
5831
5832#define R_BE_TXPKTCTL_B0_PRELD_CFG1 0x9F4C
5833#define B_BE_B0_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)
5834#define B_BE_B0_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
5835
5836#define R_BE_TXPKTCTL_B0_ERRFLAG_IMR 0x9F78
5837#define B_BE_B0_IMR_DBG_USRCTL_RLSBMPLEN BIT(25)
5838#define B_BE_B0_IMR_DBG_USRCTL_RDNRLSCMD BIT(24)
5839#define B_BE_B0_IMR_ERR_PRELD_ENTNUMCFG BIT(17)
5840#define B_BE_B0_IMR_ERR_PRELD_RLSPKTSZERR BIT(16)
5841#define B_BE_B0_IMR_ERR_CMDPSR_TBLSZ BIT(11)
5842#define B_BE_B0_IMR_ERR_CMDPSR_FRZTO BIT(10)
5843#define B_BE_B0_IMR_ERR_CMDPSR_CMDTYPE BIT(9)
5844#define B_BE_B0_IMR_ERR_CMDPSR_1STCMDERR BIT(8)
5845#define B_BE_B0_IMR_ERR_USRCTL_NOINIT BIT(1)
5846#define B_BE_B0_IMR_ERR_USRCTL_REINIT BIT(0)
5847#define B_BE_TXPKTCTL_B0_ERRFLAG_IMR_CLR (B_BE_B0_IMR_ERR_USRCTL_REINIT | \
5848					  B_BE_B0_IMR_ERR_USRCTL_NOINIT | \
5849					  B_BE_B0_IMR_DBG_USRCTL_RDNRLSCMD | \
5850					  B_BE_B0_IMR_DBG_USRCTL_RLSBMPLEN | \
5851					  B_BE_B0_IMR_ERR_CMDPSR_1STCMDERR | \
5852					  B_BE_B0_IMR_ERR_CMDPSR_CMDTYPE | \
5853					  B_BE_B0_IMR_ERR_CMDPSR_FRZTO | \
5854					  B_BE_B0_IMR_ERR_CMDPSR_TBLSZ | \
5855					  B_BE_B0_IMR_ERR_PRELD_RLSPKTSZERR | \
5856					  B_BE_B0_IMR_ERR_PRELD_ENTNUMCFG)
5857#define B_BE_TXPKTCTL_B0_ERRFLAG_IMR_SET (B_BE_B0_IMR_ERR_USRCTL_REINIT | \
5858					  B_BE_B0_IMR_ERR_USRCTL_NOINIT | \
5859					  B_BE_B0_IMR_ERR_CMDPSR_1STCMDERR | \
5860					  B_BE_B0_IMR_ERR_CMDPSR_CMDTYPE | \
5861					  B_BE_B0_IMR_ERR_CMDPSR_FRZTO | \
5862					  B_BE_B0_IMR_ERR_CMDPSR_TBLSZ | \
5863					  B_BE_B0_IMR_ERR_PRELD_RLSPKTSZERR | \
5864					  B_BE_B0_IMR_ERR_PRELD_ENTNUMCFG)
5865
5866#define R_BE_TXPKTCTL_B1_PRELD_CFG0 0x9F88
5867#define B_BE_B1_PRELD_FEN BIT(31)
5868#define B_BE_B1_PRELD_USEMAXSZ_MASK GENMASK(25, 16)
5869#define B_BE_B1_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)
5870#define B_BE_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
5871
5872#define R_BE_TXPKTCTL_B1_PRELD_CFG1 0x9F8C
5873#define B_BE_B1_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)
5874#define B_BE_B1_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
5875
5876#define R_BE_TXPKTCTL_B1_ERRFLAG_IMR 0x9FB8
5877#define B_BE_B1_IMR_DBG_USRCTL_RLSBMPLEN BIT(25)
5878#define B_BE_B1_IMR_DBG_USRCTL_RDNRLSCMD BIT(24)
5879#define B_BE_B1_IMR_ERR_PRELD_ENTNUMCFG BIT(17)
5880#define B_BE_B1_IMR_ERR_PRELD_RLSPKTSZERR BIT(16)
5881#define B_BE_B1_IMR_ERR_CMDPSR_TBLSZ BIT(11)
5882#define B_BE_B1_IMR_ERR_CMDPSR_FRZTO BIT(10)
5883#define B_BE_B1_IMR_ERR_CMDPSR_CMDTYPE BIT(9)
5884#define B_BE_B1_IMR_ERR_CMDPSR_1STCMDERR BIT(8)
5885#define B_BE_B1_IMR_ERR_USRCTL_NOINIT BIT(1)
5886#define B_BE_B1_IMR_ERR_USRCTL_REINIT BIT(0)
5887#define B_BE_TXPKTCTL_B1_ERRFLAG_IMR_CLR (B_BE_B1_IMR_ERR_USRCTL_REINIT | \
5888					  B_BE_B1_IMR_ERR_USRCTL_NOINIT | \
5889					  B_BE_B1_IMR_DBG_USRCTL_RDNRLSCMD | \
5890					  B_BE_B1_IMR_DBG_USRCTL_RLSBMPLEN | \
5891					  B_BE_B1_IMR_ERR_CMDPSR_1STCMDERR | \
5892					  B_BE_B1_IMR_ERR_CMDPSR_CMDTYPE | \
5893					  B_BE_B1_IMR_ERR_CMDPSR_FRZTO | \
5894					  B_BE_B1_IMR_ERR_CMDPSR_TBLSZ | \
5895					  B_BE_B1_IMR_ERR_PRELD_RLSPKTSZERR | \
5896					  B_BE_B1_IMR_ERR_PRELD_ENTNUMCFG)
5897#define B_BE_TXPKTCTL_B1_ERRFLAG_IMR_SET (B_BE_B1_IMR_ERR_USRCTL_REINIT | \
5898					  B_BE_B1_IMR_ERR_USRCTL_NOINIT | \
5899					  B_BE_B1_IMR_ERR_CMDPSR_1STCMDERR | \
5900					  B_BE_B1_IMR_ERR_CMDPSR_CMDTYPE | \
5901					  B_BE_B1_IMR_ERR_CMDPSR_FRZTO | \
5902					  B_BE_B1_IMR_ERR_CMDPSR_TBLSZ | \
5903					  B_BE_B1_IMR_ERR_PRELD_RLSPKTSZERR | \
5904					  B_BE_B1_IMR_ERR_PRELD_ENTNUMCFG)
5905
5906#define R_BE_MLO_INIT_CTL 0xA114
5907#define B_BE_MLO_TABLE_INIT_DONE BIT(31)
5908#define B_BE_MLO_TABLE_CLR_DONE BIT(30)
5909#define B_BE_MLO_TABLE_REINIT BIT(23)
5910#define B_BE_MLO_TABLE_HW_FLAG_CLR BIT(22)
5911
5912#define R_BE_MLO_ERR_IDCT_IMR 0xA128
5913#define B_BE_MLO_ERR_IDCT_IMR_0 BIT(31)
5914#define B_BE_MLO_ERR_IDCT_IMR_1 BIT(30)
5915#define B_BE_MLO_ERR_IDCT_IMR_2 BIT(29)
5916#define B_BE_MLO_ERR_IDCT_IMR_3 BIT(28)
5917#define B_BE_MLO_ERR_IDCT_IMR_CLR (B_BE_MLO_ERR_IDCT_IMR_2 | \
5918				   B_BE_MLO_ERR_IDCT_IMR_1 | \
5919				   B_BE_MLO_ERR_IDCT_IMR_0)
5920#define B_BE_MLO_ERR_IDCT_IMR_SET (B_BE_MLO_ERR_IDCT_IMR_2 | \
5921				   B_BE_MLO_ERR_IDCT_IMR_1 | \
5922				   B_BE_MLO_ERR_IDCT_IMR_0)
5923
5924#define R_BE_MLO_ERR_IDCT_ISR 0xA12C
5925#define B_BE_MLO_ISR_IDCT_0 BIT(31)
5926#define B_BE_MLO_ISR_IDCT_1 BIT(30)
5927#define B_BE_MLO_ISR_IDCT_2 BIT(29)
5928#define B_BE_MLO_ISR_IDCT_3 BIT(28)
5929
5930#define R_BE_PLRLS_ERR_IMR 0xA218
5931#define B_BE_PLRLS_CTL_FRZTO_IMR BIT(0)
5932#define B_BE_PLRLS_ERR_IMR_CLR B_BE_PLRLS_CTL_FRZTO_IMR
5933#define B_BE_PLRLS_ERR_IMR_SET B_BE_PLRLS_CTL_FRZTO_IMR
5934
5935#define R_BE_PLRLS_ERR_ISR 0xA21C
5936#define B_BE_PLRLS_CTL_EVT03_ISR BIT(3)
5937#define B_BE_PLRLS_CTL_EVT02_ISR BIT(2)
5938#define B_BE_PLRLS_CTL_EVT01_ISR BIT(1)
5939#define B_BE_PLRLS_CTL_FRZTO_ISR BIT(0)
5940
5941#define R_BE_SS_CTRL 0xA310
5942#define B_BE_SS_INIT_DONE BIT(31)
5943#define B_BE_WDE_STA_DIS BIT(30)
5944#define B_BE_WARM_INIT BIT(29)
5945#define B_BE_BAND_TRIG_EN BIT(28)
5946#define B_BE_RMAC_REQ_DIS BIT(27)
5947#define B_BE_DLYTX_SEL_MASK GENMASK(25, 24)
5948#define B_BE_WMM3_SWITCH_MASK GENMASK(23, 22)
5949#define B_BE_WMM2_SWITCH_MASK GENMASK(21, 20)
5950#define B_BE_WMM1_SWITCH_MASK GENMASK(19, 18)
5951#define B_BE_WMM0_SWITCH_MASK GENMASK(17, 16)
5952#define B_BE_STA_OPTION_CR BIT(15)
5953#define B_BE_EMLSR_STA_EMPTY_EN BIT(11)
5954#define B_BE_MLO_HW_CHGLINK_EN BIT(10)
5955#define B_BE_BAND1_TRIG_EN BIT(9)
5956#define B_BE_RMAC1_REQ_DIS BIT(8)
5957#define B_BE_MRT_SRAM_EN BIT(7)
5958#define B_BE_MRT_INIT_EN BIT(6)
5959#define B_BE_AVG_LENG_EN BIT(5)
5960#define B_BE_AVG_INIT_EN BIT(4)
5961#define B_BE_LENG_INIT_EN BIT(2)
5962#define B_BE_PMPA_INIT_EN BIT(1)
5963#define B_BE_SS_EN BIT(0)
5964
5965#define R_BE_INTERRUPT_MASK_REG 0xA3F0
5966#define B_BE_PLE_B_PKTID_ERR_IMR BIT(2)
5967#define B_BE_RPT_TIMEOUT_IMR BIT(1)
5968#define B_BE_SEARCH_TIMEOUT_IMR BIT(0)
5969#define B_BE_INTERRUPT_MASK_REG_CLR (B_BE_SEARCH_TIMEOUT_IMR | \
5970				     B_BE_RPT_TIMEOUT_IMR | \
5971				     B_BE_PLE_B_PKTID_ERR_IMR)
5972#define B_BE_INTERRUPT_MASK_REG_SET (B_BE_SEARCH_TIMEOUT_IMR | \
5973				     B_BE_RPT_TIMEOUT_IMR | \
5974				     B_BE_PLE_B_PKTID_ERR_IMR)
5975
5976#define R_BE_INTERRUPT_STS_REG 0xA3F4
5977#define B_BE_PLE_B_PKTID_ERR_ISR BIT(2)
5978#define B_BE_RPT_TIMEOUT_ISR BIT(1)
5979#define B_BE_SEARCH_TIMEOUT_ISR BIT(0)
5980
5981#define R_BE_HAXI_INIT_CFG1 0xB000
5982#define B_BE_CFG_WD_PERIOD_IDLE_MASK GENMASK(31, 28)
5983#define B_BE_CFG_WD_PERIOD_ACTIVE_MASK GENMASK(27, 24)
5984#define B_BE_EN_RO_IDX_UPD_BY_IO BIT(19)
5985#define B_BE_RST_KEEP_REG BIT(18)
5986#define B_BE_FLUSH_HAXI_MST BIT(17)
5987#define B_BE_SET_BDRAM_BOUND BIT(16)
5988#define B_BE_ADDRINFO_ALIGN4B_EN BIT(15)
5989#define B_BE_RXBD_DONE_MODE_MASK GENMASK(14, 13)
5990#define B_BE_RXQ_RXBD_MODE_MASK GENMASK(12, 11)
5991#define B_BE_DMA_MODE_MASK GENMASK(10, 8)
5992#define S_BE_DMA_MOD_PCIE_NO_DATA_CPU 0x0
5993#define S_BE_DMA_MOD_PCIE_DATA_CPU 0x1
5994#define S_BE_DMA_MOD_USB 0x4
5995#define S_BE_DMA_MOD_SDIO 0x6
5996#define B_BE_STOP_AXI_MST BIT(7)
5997#define B_BE_RXDMA_ALIGN64B_EN BIT(6)
5998#define B_BE_RXDMA_EN BIT(5)
5999#define B_BE_TXDMA_EN BIT(4)
6000#define B_BE_MAX_RXDMA_MASK GENMASK(3, 2)
6001#define B_BE_MAX_TXDMA_MASK GENMASK(1, 0)
6002
6003#define R_BE_HAXI_DMA_STOP1 0xB010
6004#define B_BE_STOP_WPDMA BIT(31)
6005#define B_BE_STOP_CH14 BIT(14)
6006#define B_BE_STOP_CH13 BIT(13)
6007#define B_BE_STOP_CH12 BIT(12)
6008#define B_BE_STOP_CH11 BIT(11)
6009#define B_BE_STOP_CH10 BIT(10)
6010#define B_BE_STOP_CH9 BIT(9)
6011#define B_BE_STOP_CH8 BIT(8)
6012#define B_BE_STOP_CH7 BIT(7)
6013#define B_BE_STOP_CH6 BIT(6)
6014#define B_BE_STOP_CH5 BIT(5)
6015#define B_BE_STOP_CH4 BIT(4)
6016#define B_BE_STOP_CH3 BIT(3)
6017#define B_BE_STOP_CH2 BIT(2)
6018#define B_BE_STOP_CH1 BIT(1)
6019#define B_BE_STOP_CH0 BIT(0)
6020
6021#define R_BE_HAXI_MST_WDT_TIMEOUT_SEL_V1 0xB02C
6022#define B_BE_HAXI_MST_WDT_TIMEOUT_SEL_MASK GENMASK(4, 0)
6023
6024#define R_BE_HAXI_IDCT_MSK 0xB0B8
6025#define B_BE_HAXI_RRESP_ERR_IDCT_MSK BIT(7)
6026#define B_BE_HAXI_BRESP_ERR_IDCT_MSK BIT(6)
6027#define B_BE_RXDMA_ERR_FLAG_IDCT_MSK BIT(5)
6028#define B_BE_SET_FC_ERROR_FLAG_IDCT_MSK BIT(4)
6029#define B_BE_TXBD_LEN0_ERR_IDCT_MSK BIT(3)
6030#define B_BE_TXBD_4KBOUND_ERR_IDCT_MSK BIT(2)
6031#define B_BE_RXMDA_STUCK_IDCT_MSK BIT(1)
6032#define B_BE_TXMDA_STUCK_IDCT_MSK BIT(0)
6033#define B_BE_HAXI_IDCT_MSK_CLR (B_BE_TXMDA_STUCK_IDCT_MSK | \
6034				B_BE_RXMDA_STUCK_IDCT_MSK | \
6035				B_BE_TXBD_LEN0_ERR_IDCT_MSK | \
6036				B_BE_SET_FC_ERROR_FLAG_IDCT_MSK | \
6037				B_BE_RXDMA_ERR_FLAG_IDCT_MSK | \
6038				B_BE_HAXI_BRESP_ERR_IDCT_MSK | \
6039				B_BE_HAXI_RRESP_ERR_IDCT_MSK)
6040#define B_BE_HAXI_IDCT_MSK_SET (B_BE_TXMDA_STUCK_IDCT_MSK | \
6041				B_BE_RXMDA_STUCK_IDCT_MSK | \
6042				B_BE_TXBD_LEN0_ERR_IDCT_MSK | \
6043				B_BE_SET_FC_ERROR_FLAG_IDCT_MSK | \
6044				B_BE_RXDMA_ERR_FLAG_IDCT_MSK | \
6045				B_BE_HAXI_BRESP_ERR_IDCT_MSK | \
6046				B_BE_HAXI_RRESP_ERR_IDCT_MSK)
6047
6048#define R_BE_HAXI_IDCT 0xB0BC
6049#define B_BE_HAXI_RRESP_ERR_IDCT BIT(7)
6050#define B_BE_HAXI_BRESP_ERR_IDCT BIT(6)
6051#define B_BE_RXDMA_ERR_FLAG_IDCT BIT(5)
6052#define B_BE_SET_FC_ERROR_FLAG_IDCT BIT(4)
6053#define B_BE__TXBD_LEN0_ERR_IDCT BIT(3)
6054#define B_BE__TXBD_4KBOUND_ERR_IDCT BIT(2)
6055#define B_BE_RXMDA_STUCK_IDCT BIT(1)
6056#define B_BE_TXMDA_STUCK_IDCT BIT(0)
6057
6058#define R_BE_HCI_FC_CTRL 0xB700
6059#define B_BE_WD_PAGE_MODE_MASK GENMASK(17, 16)
6060#define B_BE_HCI_FC_CH14_FULL_COND_MASK GENMASK(15, 14)
6061#define B_BE_HCI_FC_TWD_FULL_COND_MASK GENMASK(13, 12)
6062#define B_BE_HCI_FC_CH12_FULL_COND_MASK GENMASK(11, 10)
6063#define B_BE_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8)
6064#define B_BE_HCI_FC_WP_CH07_FULL_COND_MASK GENMASK(7, 6)
6065#define B_BE_HCI_FC_WD_FULL_COND_MASK GENMASK(5, 4)
6066#define B_BE_HCI_FC_CH12_EN BIT(3)
6067#define B_BE_HCI_FC_MODE_MASK GENMASK(2, 1)
6068#define B_BE_HCI_FC_EN BIT(0)
6069
6070#define R_BE_CH_PAGE_CTRL 0xB704
6071#define B_BE_PREC_PAGE_CH12_V1_MASK GENMASK(21, 16)
6072#define B_BE_PREC_PAGE_CH011_V1_MASK GENMASK(5, 0)
6073
6074#define R_BE_CH0_PAGE_CTRL 0xB718
6075#define B_BE_CH0_GRP BIT(31)
6076#define B_BE_CH0_MAX_PG_MASK GENMASK(28, 16)
6077#define B_BE_CH0_MIN_PG_MASK GENMASK(12, 0)
6078
6079#define R_BE_CH0_PAGE_INFO 0xB750
6080#define B_BE_CH0_AVAL_PG_MASK GENMASK(28, 16)
6081#define B_BE_CH0_USE_PG_MASK GENMASK(12, 0)
6082
6083#define R_BE_PUB_PAGE_INFO3 0xB78C
6084#define B_BE_G1_AVAL_PG_MASK GENMASK(28, 16)
6085#define B_BE_G0_AVAL_PG_MASK GENMASK(12, 0)
6086
6087#define R_BE_PUB_PAGE_CTRL1 0xB790
6088#define B_BE_PUBPG_G1_MASK GENMASK(28, 16)
6089#define B_BE_PUBPG_G0_MASK GENMASK(12, 0)
6090
6091#define R_BE_PUB_PAGE_CTRL2 0xB794
6092#define B_BE_PUBPG_ALL_MASK GENMASK(12, 0)
6093
6094#define R_BE_PUB_PAGE_INFO1 0xB79C
6095#define B_BE_G1_USE_PG_MASK GENMASK(28, 16)
6096#define B_BE_G0_USE_PG_MASK GENMASK(12, 0)
6097
6098#define R_BE_PUB_PAGE_INFO2 0xB7A0
6099#define B_BE_PUB_AVAL_PG_MASK GENMASK(12, 0)
6100
6101#define R_BE_WP_PAGE_CTRL1 0xB7A4
6102#define B_BE_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16)
6103#define B_BE_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0)
6104
6105#define R_BE_WP_PAGE_CTRL2 0xB7A8
6106#define B_BE_WP_THRD_MASK GENMASK(12, 0)
6107
6108#define R_BE_WP_PAGE_INFO1 0xB7AC
6109#define B_BE_WP_AVAL_PG_MASK GENMASK(28, 16)
6110
6111#define R_BE_LTPC_T0_PATH0 0xBA28
6112#define R_BE_LTPC_T0_PATH1 0xBB28
6113
6114#define R_BE_CMAC_SHARE_FUNC_EN 0x0E000
6115#define B_BE_CMAC_SHARE_CRPRT BIT(31)
6116#define B_BE_CMAC_SHARE_EN BIT(30)
6117#define B_BE_FORCE_BTCOEX_REG_GCKEN BIT(24)
6118#define B_BE_FORCE_CMAC_SHARE_COMMON_REG_GCKEN BIT(16)
6119#define B_BE_FORCE_CMAC_SHARE_REG_GCKEN BIT(15)
6120#define B_BE_RESPBA_EN BIT(2)
6121#define B_BE_ADDRSRCH_EN BIT(1)
6122#define B_BE_BTCOEX_EN BIT(0)
6123
6124#define R_BE_CMAC_SHARE_ACQCHK_CFG_0 0x0E010
6125#define B_BE_ACQCHK_ERR_FLAG_MASK GENMASK(31, 24)
6126#define B_BE_R_ACQCHK_ENTRY_IDX_SEL_MASK GENMASK(7, 4)
6127#define B_BE_MACID_ACQ_GRP1_CLR_P BIT(3)
6128#define B_BE_MACID_ACQ_GRP0_CLR_P BIT(2)
6129#define B_BE_R_MACID_ACQ_CHK_EN BIT(0)
6130
6131#define R_BE_BTC_CFG 0x0E300
6132#define R_BE_BT_BREAK_TABLE 0x0E344
6133
6134#define R_BE_GNT_SW_CTRL 0x0E348
6135#define B_BE_WL_ACT2_VAL BIT(25)
6136#define B_BE_WL_ACT2_SWCTRL BIT(24)
6137#define B_BE_WL_ACT_VAL BIT(23)
6138#define B_BE_WL_ACT_SWCTRL BIT(22)
6139#define B_BE_GNT_BT_RX_BB1_VAL BIT(21)
6140#define B_BE_GNT_BT_RX_BB1_SWCTRL BIT(20)
6141#define B_BE_GNT_BT_TX_BB1_VAL BIT(19)
6142#define B_BE_GNT_BT_TX_BB1_SWCTRL BIT(18)
6143#define B_BE_GNT_BT_RX_BB0_VAL BIT(17)
6144#define B_BE_GNT_BT_RX_BB0_SWCTRL BIT(16)
6145#define B_BE_GNT_BT_TX_BB0_VAL BIT(15)
6146#define B_BE_GNT_BT_TX_BB0_SWCTRL BIT(14)
6147#define B_BE_GNT_WL_RX_VAL BIT(13)
6148#define B_BE_GNT_WL_RX_SWCTRL BIT(12)
6149#define B_BE_GNT_WL_TX_VAL BIT(11)
6150#define B_BE_GNT_WL_TX_SWCTRL BIT(10)
6151#define B_BE_GNT_BT_BB1_VAL BIT(9)
6152#define B_BE_GNT_BT_BB1_SWCTRL BIT(8)
6153#define B_BE_GNT_WL_BB1_VAL BIT(7)
6154#define B_BE_GNT_WL_BB1_SWCTRL BIT(6)
6155#define B_BE_GNT_BT_BB0_VAL BIT(5)
6156#define B_BE_GNT_BT_BB0_SWCTRL BIT(4)
6157#define B_BE_GNT_WL_BB0_VAL BIT(3)
6158#define B_BE_GNT_WL_BB0_SWCTRL BIT(2)
6159#define B_BE_GNT_WL_BB_PWR_VAL BIT(1)
6160#define B_BE_GNT_WL_BB_PWR_SWCTRL BIT(0)
6161
6162#define R_BE_PWR_MACID_PATH_BASE 0x0E500
6163#define R_BE_PWR_MACID_LMT_BASE 0x0ED00
6164
6165#define R_BE_CMAC_FUNC_EN 0x10000
6166#define R_BE_CMAC_FUNC_EN_C1 0x14000
6167#define B_BE_CMAC_CRPRT BIT(31)
6168#define B_BE_CMAC_EN BIT(30)
6169#define B_BE_CMAC_TXEN BIT(29)
6170#define B_BE_CMAC_RXEN BIT(28)
6171#define B_BE_FORCE_RESP_PKTCTL_GCKEN BIT(26)
6172#define B_BE_FORCE_SIGB_REG_GCKEN BIT(25)
6173#define B_BE_FORCE_POWER_REG_GCKEN BIT(23)
6174#define B_BE_FORCE_RMAC_REG_GCKEN BIT(22)
6175#define B_BE_FORCE_TRXPTCL_REG_GCKEN BIT(21)
6176#define B_BE_FORCE_TMAC_REG_GCKEN BIT(20)
6177#define B_BE_FORCE_CMAC_DMA_REG_GCKEN BIT(19)
6178#define B_BE_FORCE_PTCL_REG_GCKEN BIT(18)
6179#define B_BE_FORCE_SCHEDULER_RREG_GCKEN BIT(17)
6180#define B_BE_FORCE_CMAC_COMMON_REG_GCKEN BIT(16)
6181#define B_BE_FORCE_CMACREG_GCKEN BIT(15)
6182#define B_BE_TXTIME_EN BIT(8)
6183#define B_BE_RESP_PKTCTL_EN BIT(7)
6184#define B_BE_SIGB_EN BIT(6)
6185#define B_BE_PHYINTF_EN BIT(5)
6186#define B_BE_CMAC_DMA_EN BIT(4)
6187#define B_BE_PTCLTOP_EN BIT(3)
6188#define B_BE_SCHEDULER_EN BIT(2)
6189#define B_BE_TMAC_EN BIT(1)
6190#define B_BE_RMAC_EN BIT(0)
6191#define B_BE_CMAC_FUNC_EN_SET (B_BE_CMAC_EN | B_BE_CMAC_TXEN | B_BE_CMAC_RXEN | \
6192			       B_BE_PHYINTF_EN | B_BE_CMAC_DMA_EN | B_BE_PTCLTOP_EN | \
6193			       B_BE_SCHEDULER_EN | B_BE_TMAC_EN | B_BE_RMAC_EN | \
6194			       B_BE_CMAC_CRPRT | B_BE_TXTIME_EN | B_BE_RESP_PKTCTL_EN | \
6195			       B_BE_SIGB_EN)
6196
6197#define R_BE_CK_EN 0x10004
6198#define R_BE_CK_EN_C1 0x14004
6199#define B_BE_CMAC_CKEN BIT(30)
6200#define B_BE_BCN_P1_P4_CKEN BIT(15)
6201#define B_BE_BCN_P0MB1_15_CKEN BIT(14)
6202#define B_BE_TXTIME_CKEN BIT(8)
6203#define B_BE_RESP_PKTCTL_CKEN BIT(7)
6204#define B_BE_SIGB_CKEN BIT(6)
6205#define B_BE_PHYINTF_CKEN BIT(5)
6206#define B_BE_CMAC_DMA_CKEN BIT(4)
6207#define B_BE_PTCLTOP_CKEN BIT(3)
6208#define B_BE_SCHEDULER_CKEN BIT(2)
6209#define B_BE_TMAC_CKEN BIT(1)
6210#define B_BE_RMAC_CKEN BIT(0)
6211#define B_BE_CK_EN_SET (B_BE_CMAC_CKEN | B_BE_PHYINTF_CKEN | B_BE_CMAC_DMA_CKEN | \
6212			B_BE_PTCLTOP_CKEN | B_BE_SCHEDULER_CKEN | B_BE_TMAC_CKEN | \
6213			B_BE_RMAC_CKEN | B_BE_TXTIME_CKEN | B_BE_RESP_PKTCTL_CKEN | \
6214			B_BE_SIGB_CKEN)
6215
6216#define R_BE_WMAC_RFMOD 0x10010
6217#define R_BE_WMAC_RFMOD_C1 0x14010
6218#define B_BE_CMAC_ASSERTION BIT(31)
6219#define B_BE_WMAC_RFMOD_MASK GENMASK(2, 0)
6220#define BE_WMAC_RFMOD_20M 0
6221#define BE_WMAC_RFMOD_40M 1
6222#define BE_WMAC_RFMOD_80M 2
6223#define BE_WMAC_RFMOD_160M 3
6224#define BE_WMAC_RFMOD_320M 4
6225
6226#define R_BE_TX_SUB_BAND_VALUE 0x10088
6227#define R_BE_TX_SUB_BAND_VALUE_C1 0x14088
6228#define B_BE_PRI20_BITMAP_MASK GENMASK(31, 16)
6229#define BE_PRI20_BITMAP_MAX 15
6230#define B_BE_TXSB_160M_MASK GENMASK(15, 12)
6231#define S_BE_TXSB_160M_0 0
6232#define S_BE_TXSB_160M_1 1
6233#define B_BE_TXSB_80M_MASK GENMASK(11, 8)
6234#define S_BE_TXSB_80M_0 0
6235#define S_BE_TXSB_80M_2 2
6236#define S_BE_TXSB_80M_4 4
6237#define B_BE_TXSB_40M_MASK GENMASK(7, 4)
6238#define S_BE_TXSB_40M_0 0
6239#define S_BE_TXSB_40M_1 1
6240#define S_BE_TXSB_40M_4 4
6241#define B_BE_TXSB_20M_MASK GENMASK(3, 0)
6242#define S_BE_TXSB_20M_8 8
6243#define S_BE_TXSB_20M_4 4
6244#define S_BE_TXSB_20M_2 2
6245
6246#define R_BE_PTCL_RRSR0 0x1008C
6247#define R_BE_PTCL_RRSR0_C1 0x1408C
6248#define B_BE_RRSR_HE_MASK GENMASK(31, 24)
6249#define B_BE_RRSR_VHT_MASK GENMASK(23, 16)
6250#define B_BE_RRSR_HT_MASK GENMASK(15, 8)
6251#define B_BE_RRSR_OFDM_MASK GENMASK(7, 0)
6252
6253#define R_BE_PTCL_RRSR1 0x10090
6254#define R_BE_PTCL_RRSR1_C1 0x14090
6255#define B_BE_RRSR_EHT_MASK GENMASK(23, 16)
6256#define B_BE_RRSR_RATE_EN_MASK GENMASK(12, 8)
6257#define B_BE_RSC_MASK GENMASK(7, 6)
6258#define B_BE_RRSR_CCK_MASK GENMASK(3, 0)
6259
6260#define R_BE_CMAC_ERR_IMR 0x10160
6261#define R_BE_CMAC_ERR_IMR_C1 0x14160
6262#define B_BE_CMAC_FW_ERR_IDCT_EN BIT(16)
6263#define B_BE_PTCL_TX_IDLETO_IDCT_EN BIT(9)
6264#define B_BE_WMAC_RX_IDLETO_IDCT_EN BIT(8)
6265#define B_BE_WMAC_TX_ERR_IND_EN BIT(7)
6266#define B_BE_WMAC_RX_ERR_IND_EN BIT(6)
6267#define B_BE_TXPWR_CTRL_ERR_IND_EN BIT(5)
6268#define B_BE_PHYINTF_ERR_IND_EN BIT(4)
6269#define B_BE_DMA_TOP_ERR_IND_EN BIT(3)
6270#define B_BE_RESP_PKTCTL_ERR_IND_EN BIT(2)
6271#define B_BE_PTCL_TOP_ERR_IND_EN BIT(1)
6272#define B_BE_SCHEDULE_TOP_ERR_IND_EN BIT(0)
6273
6274#define R_BE_CMAC_ERR_ISR 0x10164
6275#define R_BE_CMAC_ERR_ISR_C1 0x14164
6276#define B_BE_CMAC_FW_ERR_IDCT BIT(16)
6277#define B_BE_PTCL_TX_IDLETO_IDCT BIT(9)
6278#define B_BE_WMAC_RX_IDLETO_IDCT BIT(8)
6279#define B_BE_WMAC_TX_ERR_IND BIT(7)
6280#define B_BE_WMAC_RX_ERR_IND BIT(6)
6281#define B_BE_TXPWR_CTRL_ERR_IND BIT(5)
6282#define B_BE_PHYINTF_ERR_IND BIT(4)
6283#define B_BE_DMA_TOP_ERR_IND BIT(3)
6284#define B_BE_RESP_PKTCTL_ERR_IDCT BIT(2)
6285#define B_BE_PTCL_TOP_ERR_IND BIT(1)
6286#define B_BE_SCHEDULE_TOP_ERR_IND BIT(0)
6287
6288#define R_BE_CMAC_FW_TRIGGER_IDCT_ISR 0x10168
6289#define R_BE_CMAC_FW_TRIGGER_IDCT_ISR_C1 0x14168
6290#define B_BE_CMAC_FW_ERR_IDCT_IMR BIT(31)
6291#define B_BE_CMAC_FW_TRIG_IDCT BIT(0)
6292
6293#define R_BE_SER_L0_DBG_CNT 0x10170
6294#define R_BE_SER_L0_DBG_CNT_C1 0x14170
6295#define B_BE_SER_L0_PHYINTF_CNT_MASK GENMASK(31, 24)
6296#define B_BE_SER_L0_DMA_CNT_MASK GENMASK(23, 16)
6297#define B_BE_SER_L0_PTCL_CNT_MASK GENMASK(15, 8)
6298#define B_BE_SER_L0_SCH_CNT_MASK GENMASK(7, 0)
6299
6300#define R_BE_SER_L0_DBG_CNT1 0x10174
6301#define R_BE_SER_L0_DBG_CNT1_C1 0x14174
6302#define B_BE_SER_L0_TMAC_COUNTER_MASK GENMASK(23, 16)
6303#define B_BE_SER_L0_RMAC_COUNTER_MASK GENMASK(15, 8)
6304#define B_BE_SER_L0_TXPWR_COUNTER_MASK GENMASK(7, 0)
6305
6306#define R_BE_SER_L0_DBG_CNT2 0x10178
6307#define R_BE_SER_L0_DBG_CNT2_C1 0x14178
6308
6309#define R_BE_SER_L0_DBG_CNT3 0x1017C
6310#define R_BE_SER_L0_DBG_CNT3_C1 0x1417C
6311#define B_BE_SER_L0_SUBMODULE_BIT31_CNT BIT(31)
6312#define B_BE_SER_L0_SUBMODULE_BIT30_CNT BIT(30)
6313#define B_BE_SER_L0_SUBMODULE_BIT29_CNT BIT(29)
6314#define B_BE_SER_L0_SUBMODULE_BIT28_CNT BIT(28)
6315#define B_BE_SER_L0_SUBMODULE_BIT27_CNT BIT(27)
6316#define B_BE_SER_L0_SUBMODULE_BIT26_CNT BIT(26)
6317#define B_BE_SER_L0_SUBMODULE_BIT25_CNT BIT(25)
6318#define B_BE_SER_L0_SUBMODULE_BIT24_CNT BIT(24)
6319#define B_BE_SER_L0_SUBMODULE_BIT23_CNT BIT(23)
6320#define B_BE_SER_L0_SUBMODULE_BIT22_CNT BIT(22)
6321#define B_BE_SER_L0_SUBMODULE_BIT21_CNT BIT(21)
6322#define B_BE_SER_L0_SUBMODULE_BIT20_CNT BIT(20)
6323#define B_BE_SER_L0_SUBMODULE_BIT19_CNT BIT(19)
6324#define B_BE_SER_L0_SUBMODULE_BIT18_CNT BIT(18)
6325#define B_BE_SER_L0_SUBMODULE_BIT17_CNT BIT(17)
6326#define B_BE_SER_L0_SUBMODULE_BIT16_CNT BIT(16)
6327#define B_BE_SER_L0_SUBMODULE_BIT15_CNT BIT(15)
6328#define B_BE_SER_L0_SUBMODULE_BIT14_CNT BIT(14)
6329#define B_BE_SER_L0_SUBMODULE_BIT13_CNT BIT(13)
6330#define B_BE_SER_L0_SUBMODULE_BIT12_CNT BIT(12)
6331#define B_BE_SER_L0_SUBMODULE_BIT11_CNT BIT(11)
6332#define B_BE_SER_L0_SUBMODULE_BIT10_CNT BIT(10)
6333#define B_BE_SER_L0_SUBMODULE_BIT9_CNT BIT(9)
6334#define B_BE_SER_L0_SUBMODULE_BIT8_CNT BIT(8)
6335#define B_BE_SER_L0_SUBMODULE_BIT7_CNT BIT(7)
6336#define B_BE_SER_L0_SUBMODULE_BIT6_CNT BIT(6)
6337#define B_BE_SER_L0_SUBMODULE_BIT5_CNT BIT(5)
6338#define B_BE_SER_L0_SUBMODULE_BIT4_CNT BIT(4)
6339#define B_BE_SER_L0_SUBMODULE_BIT3_CNT BIT(3)
6340#define B_BE_SER_L0_SUBMODULE_BIT2_CNT BIT(2)
6341#define B_BE_SER_L0_SUBMODULE_BIT1_CNT BIT(1)
6342#define B_BE_SER_L0_SUBMODULE_BIT0_CNT BIT(0)
6343
6344#define R_BE_PORT_0_TSF_SYNC 0x102A0
6345#define R_BE_PORT_0_TSF_SYNC_C1 0x142A0
6346#define B_BE_P0_SYNC_NOW_P BIT(30)
6347#define B_BE_P0_SYNC_ONCE_P BIT(29)
6348#define B_BE_P0_AUTO_SYNC BIT(28)
6349#define B_BE_P0_SYNC_PORT_SRC_SEL_MASK GENMASK(26, 24)
6350#define B_BE_P0_TSFTR_SYNC_OFFSET_MASK GENMASK(18, 0)
6351
6352#define R_BE_EDCA_BCNQ_PARAM 0x10324
6353#define R_BE_EDCA_BCNQ_PARAM_C1 0x14324
6354#define B_BE_BCNQ_CW_MASK GENMASK(31, 24)
6355#define B_BE_BCNQ_AIFS_MASK GENMASK(23, 16)
6356#define BCN_IFS_25US 0x19
6357#define B_BE_PIFS_MASK GENMASK(15, 8)
6358#define B_BE_FORCE_BCN_IFS_MASK GENMASK(7, 0)
6359
6360#define R_BE_PREBKF_CFG_0 0x10338
6361#define R_BE_PREBKF_CFG_0_C1 0x14338
6362#define B_BE_100NS_TIME_MASK GENMASK(28, 24)
6363#define B_BE_RX_AIR_END_TIME_MASK GENMASK(22, 16)
6364#define B_BE_MACTX_LATENCY_MASK GENMASK(10, 8)
6365#define B_BE_PREBKF_TIME_MASK GENMASK(4, 0)
6366
6367#define R_BE_PREBKF_CFG_1 0x1033C
6368#define R_BE_PREBKF_CFG_1_C1 0x1433C
6369#define B_BE_SIFS_TIMEOUT_TB_AGGR_MASK GENMASK(31, 24)
6370#define B_BE_SIFS_PREBKF_MASK GENMASK(23, 16)
6371#define B_BE_SIFS_TIMEOUT_T2_MASK GENMASK(14, 8)
6372#define B_BE_SIFS_MACTXEN_T1_MASK GENMASK(6, 0)
6373
6374#define R_BE_CCA_CFG_0 0x10340
6375#define R_BE_CCA_CFG_0_C1 0x14340
6376#define B_BE_R_SIFS_AGGR_TIME_V1_MASK GENMASK(31, 24)
6377#define B_BE_EDCCA_SEC160_EN BIT(23)
6378#define B_BE_EDCCA_SEC80_EN BIT(22)
6379#define B_BE_EDCCA_SEC40_EN BIT(21)
6380#define B_BE_EDCCA_SEC20_EN BIT(20)
6381#define B_BE_SEC160_EN BIT(19)
6382#define B_BE_CCA_BITMAP_EN BIT(18)
6383#define B_BE_TXPKTCTL_RST_EDCA_EN BIT(17)
6384#define B_BE_WMAC_RST_EDCA_EN BIT(16)
6385#define B_BE_TXFAIL_BRK_TXOP_EN BIT(11)
6386#define B_BE_EDCCA_PER20_BITMAP_SIFS_EN BIT(10)
6387#define B_BE_NO_GNT_WL_BRK_TXOP_EN BIT(9)
6388#define B_BE_NAV_BRK_TXOP_EN BIT(8)
6389#define B_BE_TX_NAV_EN BIT(7)
6390#define B_BE_BCN_IGNORE_EDCCA BIT(6)
6391#define B_BE_NO_GNT_WL_EN BIT(5)
6392#define B_BE_EDCCA_EN BIT(4)
6393#define B_BE_SEC80_EN BIT(3)
6394#define B_BE_SEC40_EN BIT(2)
6395#define B_BE_SEC20_EN BIT(1)
6396#define B_BE_CCA_EN BIT(0)
6397
6398#define R_BE_CTN_CFG_0 0x1034C
6399#define R_BE_CTN_CFG_0_C1 0x1434C
6400#define B_BE_OTHER_LINK_BKF_BLK_TX_THD_MASK GENMASK(30, 24)
6401#define B_BE_CCK_SIFS_COMP_MASK GENMASK(22, 16)
6402#define B_BE_PIFS_TIMEUNIT_MASK GENMASK(15, 14)
6403#define B_BE_PREBKF_TIME_NONAC_MASK GENMASK(12, 8)
6404#define B_BE_SR_TX_EN BIT(2)
6405#define B_BE_NAV_BLK_MGQ BIT(1)
6406#define B_BE_NAV_BLK_HGQ BIT(0)
6407
6408#define R_BE_MUEDCA_BE_PARAM_0 0x10350
6409#define R_BE_MUEDCA_BK_PARAM_0 0x10354
6410#define R_BE_MUEDCA_VI_PARAM_0 0x10358
6411#define R_BE_MUEDCA_VO_PARAM_0 0x1035C
6412
6413#define R_BE_MUEDCA_EN 0x10370
6414#define R_BE_MUEDCA_EN_C1 0x14370
6415#define B_BE_SIFS_TIMEOUT_TB_T2_MASK GENMASK(30, 24)
6416#define B_BE_SIFS_MACTXEN_TB_T1_MASK GENMASK(22, 16)
6417#define B_BE_MUEDCA_WMM_SEL BIT(8)
6418#define B_BE_SET_MUEDCATIMER_TF_MASK GENMASK(5, 4)
6419#define B_BE_SET_MUEDCATIMER_TF_0 BIT(4)
6420#define B_BE_MUEDCA_EN_MASK GENMASK(1, 0)
6421#define B_BE_MUEDCA_EN_0 BIT(0)
6422
6423#define R_BE_CTN_DRV_TXEN 0x10398
6424#define R_BE_CTN_DRV_TXEN_C1 0x14398
6425#define B_BE_CTN_TXEN_TWT_3 BIT(17)
6426#define B_BE_CTN_TXEN_TWT_2 BIT(16)
6427#define B_BE_CTN_TXEN_TWT_1 BIT(15)
6428#define B_BE_CTN_TXEN_TWT_0 BIT(14)
6429#define B_BE_CTN_TXEN_ULQ BIT(13)
6430#define B_BE_CTN_TXEN_BCNQ BIT(12)
6431#define B_BE_CTN_TXEN_HGQ BIT(11)
6432#define B_BE_CTN_TXEN_CPUMGQ BIT(10)
6433#define B_BE_CTN_TXEN_MGQ1 BIT(9)
6434#define B_BE_CTN_TXEN_MGQ BIT(8)
6435#define B_BE_CTN_TXEN_VO_1 BIT(7)
6436#define B_BE_CTN_TXEN_VI_1 BIT(6)
6437#define B_BE_CTN_TXEN_BK_1 BIT(5)
6438#define B_BE_CTN_TXEN_BE_1 BIT(4)
6439#define B_BE_CTN_TXEN_VO_0 BIT(3)
6440#define B_BE_CTN_TXEN_VI_0 BIT(2)
6441#define B_BE_CTN_TXEN_BK_0 BIT(1)
6442#define B_BE_CTN_TXEN_BE_0 BIT(0)
6443#define B_BE_CTN_TXEN_ALL_MASK GENMASK(17, 0)
6444
6445#define R_BE_TB_CHK_CCA_NAV 0x103AC
6446#define R_BE_TB_CHK_CCA_NAV_C1 0x143AC
6447#define B_BE_TB_CHK_TX_NAV BIT(15)
6448#define B_BE_TB_CHK_INTRA_NAV BIT(14)
6449#define B_BE_TB_CHK_BASIC_NAV BIT(13)
6450#define B_BE_TB_CHK_NO_GNT_WL BIT(12)
6451#define B_BE_TB_CHK_EDCCA_S160 BIT(11)
6452#define B_BE_TB_CHK_EDCCA_S80 BIT(10)
6453#define B_BE_TB_CHK_EDCCA_S40 BIT(9)
6454#define B_BE_TB_CHK_EDCCA_S20 BIT(8)
6455#define B_BE_TB_CHK_CCA_S160 BIT(7)
6456#define B_BE_TB_CHK_CCA_S80 BIT(6)
6457#define B_BE_TB_CHK_CCA_S40 BIT(5)
6458#define B_BE_TB_CHK_CCA_S20 BIT(4)
6459#define B_BE_TB_CHK_EDCCA_BITMAP BIT(3)
6460#define B_BE_TB_CHK_CCA_BITMAP BIT(2)
6461#define B_BE_TB_CHK_EDCCA_P20 BIT(1)
6462#define B_BE_TB_CHK_CCA_P20 BIT(0)
6463
6464#define R_BE_HE_SIFS_CHK_CCA_NAV 0x103B4
6465#define R_BE_HE_SIFS_CHK_CCA_NAV_C1 0x143B4
6466#define B_BE_HE_SIFS_CHK_TX_NAV BIT(15)
6467#define B_BE_HE_SIFS_CHK_INTRA_NAV BIT(14)
6468#define B_BE_HE_SIFS_CHK_BASIC_NAV BIT(13)
6469#define B_BE_HE_SIFS_CHK_NO_GNT_WL BIT(12)
6470#define B_BE_HE_SIFS_CHK_EDCCA_S160 BIT(11)
6471#define B_BE_HE_SIFS_CHK_EDCCA_S80 BIT(10)
6472#define B_BE_HE_SIFS_CHK_EDCCA_S40 BIT(9)
6473#define B_BE_HE_SIFS_CHK_EDCCA_S20 BIT(8)
6474#define B_BE_HE_SIFS_CHK_CCA_S160 BIT(7)
6475#define B_BE_HE_SIFS_CHK_CCA_S80 BIT(6)
6476#define B_BE_HE_SIFS_CHK_CCA_S40 BIT(5)
6477#define B_BE_HE_SIFS_CHK_CCA_S20 BIT(4)
6478#define B_BE_HE_SIFS_CHK_EDCCA_BITMAP BIT(3)
6479#define B_BE_HE_SIFS_CHK_CCA_BITMAP BIT(2)
6480#define B_BE_HE_SIFS_CHK_EDCCA_P20 BIT(1)
6481#define B_BE_HE_SIFS_CHK_CCA_P20 BIT(0)
6482
6483#define R_BE_HE_CTN_CHK_CCA_NAV 0x103C4
6484#define R_BE_HE_CTN_CHK_CCA_NAV_C1 0x143C4
6485#define B_BE_HE_CTN_CHK_TX_NAV BIT(15)
6486#define B_BE_HE_CTN_CHK_INTRA_NAV BIT(14)
6487#define B_BE_HE_CTN_CHK_BASIC_NAV BIT(13)
6488#define B_BE_HE_CTN_CHK_NO_GNT_WL BIT(12)
6489#define B_BE_HE_CTN_CHK_EDCCA_S160 BIT(11)
6490#define B_BE_HE_CTN_CHK_EDCCA_S80 BIT(10)
6491#define B_BE_HE_CTN_CHK_EDCCA_S40 BIT(9)
6492#define B_BE_HE_CTN_CHK_EDCCA_S20 BIT(8)
6493#define B_BE_HE_CTN_CHK_CCA_S160 BIT(7)
6494#define B_BE_HE_CTN_CHK_CCA_S80 BIT(6)
6495#define B_BE_HE_CTN_CHK_CCA_S40 BIT(5)
6496#define B_BE_HE_CTN_CHK_CCA_S20 BIT(4)
6497#define B_BE_HE_CTN_CHK_EDCCA_BITMAP BIT(3)
6498#define B_BE_HE_CTN_CHK_CCA_BITMAP BIT(2)
6499#define B_BE_HE_CTN_CHK_EDCCA_P20 BIT(1)
6500#define B_BE_HE_CTN_CHK_CCA_P20 BIT(0)
6501
6502#define R_BE_SCHEDULE_ERR_IMR 0x103E8
6503#define R_BE_SCHEDULE_ERR_IMR_C1 0x143E8
6504#define B_BE_FSM_TIMEOUT_ERR_INT_EN BIT(0)
6505#define B_BE_SCHEDULE_ERR_IMR_CLR B_BE_FSM_TIMEOUT_ERR_INT_EN
6506#define B_BE_SCHEDULE_ERR_IMR_SET B_BE_FSM_TIMEOUT_ERR_INT_EN
6507
6508#define R_BE_SCHEDULE_ERR_ISR 0x103EC
6509#define R_BE_SCHEDULE_ERR_ISR_C1 0x143EC
6510#define B_BE_SORT_NON_IDLE_ERR_INT BIT(1)
6511#define B_BE_FSM_TIMEOUT_ERR_INT BIT(0)
6512
6513#define R_BE_PORT_CFG_P0 0x10400
6514#define R_BE_PORT_CFG_P0_C1 0x14400
6515#define B_BE_BCN_ERLY_SORT_EN_P0 BIT(18)
6516#define B_BE_PROHIB_END_CAL_EN_P0 BIT(17)
6517#define B_BE_BRK_SETUP_P0 BIT(16)
6518#define B_BE_TBTT_UPD_SHIFT_SEL_P0 BIT(15)
6519#define B_BE_BCN_DROP_ALLOW_P0 BIT(14)
6520#define B_BE_TBTT_PROHIB_EN_P0 BIT(13)
6521#define B_BE_BCNTX_EN_P0 BIT(12)
6522#define B_BE_NET_TYPE_P0_MASK GENMASK(11, 10)
6523#define B_BE_BCN_FORCETX_EN_P0 BIT(9)
6524#define B_BE_TXBCN_BTCCA_EN_P0 BIT(8)
6525#define B_BE_BCNERR_CNT_EN_P0 BIT(7)
6526#define B_BE_BCN_AGRES_P0 BIT(6)
6527#define B_BE_TSFTR_RST_P0 BIT(5)
6528#define B_BE_RX_BSSID_FIT_EN_P0 BIT(4)
6529#define B_BE_TSF_UDT_EN_P0 BIT(3)
6530#define B_BE_PORT_FUNC_EN_P0 BIT(2)
6531#define B_BE_TXBCN_RPT_EN_P0 BIT(1)
6532#define B_BE_RXBCN_RPT_EN_P0 BIT(0)
6533
6534#define R_BE_TBTT_PROHIB_P0 0x10404
6535#define R_BE_TBTT_PROHIB_P0_C1 0x14404
6536#define B_BE_TBTT_HOLD_P0_MASK GENMASK(27, 16)
6537#define B_BE_TBTT_SETUP_P0_MASK GENMASK(7, 0)
6538
6539#define R_BE_BCN_AREA_P0 0x10408
6540#define R_BE_BCN_AREA_P0_C1 0x14408
6541#define B_BE_BCN_MSK_AREA_P0_MSK 0xfff
6542#define B_BE_BCN_CTN_AREA_P0_MASK GENMASK(11, 0)
6543
6544#define R_BE_BCNERLYINT_CFG_P0 0x1040C
6545#define R_BE_BCNERLYINT_CFG_P0_C1 0x1440C
6546#define B_BE_BCNERLY_P0_MASK GENMASK(11, 0)
6547
6548#define R_BE_TBTTERLYINT_CFG_P0 0x1040E
6549#define R_BE_TBTTERLYINT_CFG_P0_C1 0x1440E
6550#define B_BE_TBTTERLY_P0_MASK GENMASK(11, 0)
6551
6552#define R_BE_TBTT_AGG_P0 0x10412
6553#define R_BE_TBTT_AGG_P0_C1 0x14412
6554#define B_BE_TBTT_AGG_NUM_P0_MASK GENMASK(15, 8)
6555
6556#define R_BE_BCN_SPACE_CFG_P0 0x10414
6557#define R_BE_BCN_SPACE_CFG_P0_C1 0x14414
6558#define B_BE_SUB_BCN_SPACE_P0_MASK GENMASK(23, 16)
6559#define B_BE_BCN_SPACE_P0_MASK GENMASK(15, 0)
6560
6561#define R_BE_BCN_FORCETX_P0 0x10418
6562#define R_BE_BCN_FORCETX_P0_C1 0x14418
6563#define B_BE_FORCE_BCN_NUM_P0_MASK GENMASK(15, 8)
6564#define B_BE_BCN_MAX_ERR_P0_MASK GENMASK(7, 0)
6565
6566#define R_BE_BCN_ERR_CNT_P0 0x10420
6567#define R_BE_BCN_ERR_CNT_P0_C1 0x14420
6568#define B_BE_BCN_ERR_CNT_SUM_P0_MASK GENMASK(31, 24)
6569#define B_BE_BCN_ERR_CNT_NAV_P0_MASK GENMASK(23, 16)
6570#define B_BE_BCN_ERR_CNT_EDCCA_P0_MASK GENMASK(15, 8)
6571#define B_BE_BCN_ERR_CNT_CCA_P0_MASK GENMASK(7, 0)
6572
6573#define R_BE_BCN_ERR_FLAG_P0 0x10424
6574#define R_BE_BCN_ERR_FLAG_P0_C1 0x14424
6575#define B_BE_BCN_ERR_FLAG_SRCHEND_P0 BIT(3)
6576#define B_BE_BCN_ERR_FLAG_INVALID_P0 BIT(2)
6577#define B_BE_BCN_ERR_FLAG_CMP_P0 BIT(1)
6578#define B_BE_BCN_ERR_FLAG_LOCK_P0 BIT(0)
6579
6580#define R_BE_DTIM_CTRL_P0 0x10426
6581#define R_BE_DTIM_CTRL_P0_C1 0x14426
6582#define B_BE_DTIM_NUM_P0_MASK GENMASK(15, 8)
6583#define B_BE_DTIM_CURRCNT_P0_MASK GENMASK(7, 0)
6584
6585#define R_BE_TBTT_SHIFT_P0 0x10428
6586#define R_BE_TBTT_SHIFT_P0_C1 0x14428
6587#define B_BE_TBTT_SHIFT_OFST_P0_SH 0
6588#define B_BE_TBTT_SHIFT_OFST_P0_MSK 0xfff
6589
6590#define R_BE_BCN_CNT_TMR_P0 0x10434
6591#define R_BE_BCN_CNT_TMR_P0_C1 0x14434
6592#define B_BE_BCN_CNT_TMR_P0_MASK GENMASK(31, 0)
6593
6594#define R_BE_TSFTR_LOW_P0 0x10438
6595#define R_BE_TSFTR_LOW_P0_C1 0x14438
6596#define B_BE_TSFTR_LOW_P0_MASK GENMASK(31, 0)
6597
6598#define R_BE_TSFTR_HIGH_P0 0x1043C
6599#define R_BE_TSFTR_HIGH_P0_C1 0x1443C
6600#define B_BE_TSFTR_HIGH_P0_MASK GENMASK(31, 0)
6601
6602#define R_BE_BCN_DROP_ALL0 0x10560
6603
6604#define R_BE_MBSSID_CTRL 0x10568
6605#define R_BE_MBSSID_CTRL_C1 0x14568
6606#define B_BE_MBSSID_MODE_SEL BIT(20)
6607#define B_BE_P0MB_NUM_MASK GENMASK(19, 16)
6608#define B_BE_P0MB15_EN BIT(15)
6609#define B_BE_P0MB14_EN BIT(14)
6610#define B_BE_P0MB13_EN BIT(13)
6611#define B_BE_P0MB12_EN BIT(12)
6612#define B_BE_P0MB11_EN BIT(11)
6613#define B_BE_P0MB10_EN BIT(10)
6614#define B_BE_P0MB9_EN BIT(9)
6615#define B_BE_P0MB8_EN BIT(8)
6616#define B_BE_P0MB7_EN BIT(7)
6617#define B_BE_P0MB6_EN BIT(6)
6618#define B_BE_P0MB5_EN BIT(5)
6619#define B_BE_P0MB4_EN BIT(4)
6620#define B_BE_P0MB3_EN BIT(3)
6621#define B_BE_P0MB2_EN BIT(2)
6622#define B_BE_P0MB1_EN BIT(1)
6623
6624#define R_BE_P0MB_HGQ_WINDOW_CFG_0 0x10590
6625#define R_BE_P0MB_HGQ_WINDOW_CFG_0_C1 0x14590
6626#define R_BE_PORT_HGQ_WINDOW_CFG 0x105A0
6627#define R_BE_PORT_HGQ_WINDOW_CFG_C1 0x145A0
6628
6629#define R_BE_PTCL_COMMON_SETTING_0 0x10800
6630#define R_BE_PTCL_COMMON_SETTING_0_C1 0x14800
6631#define B_BE_PCIE_MODE_MASK GENMASK(15, 14)
6632#define B_BE_CPUMGQ_LIFETIME_EN BIT(8)
6633#define B_BE_MGQ_LIFETIME_EN BIT(7)
6634#define B_BE_LIFETIME_EN BIT(6)
6635#define B_BE_DIS_PTCL_CLK_GATING BIT(5)
6636#define B_BE_PTCL_TRIGGER_SS_EN_UL BIT(4)
6637#define B_BE_PTCL_TRIGGER_SS_EN_1 BIT(3)
6638#define B_BE_PTCL_TRIGGER_SS_EN_0 BIT(2)
6639#define B_BE_CMAC_TX_MODE_1 BIT(1)
6640#define B_BE_CMAC_TX_MODE_0 BIT(0)
6641
6642#define R_BE_TB_PPDU_CTRL 0x1080C
6643#define R_BE_TB_PPDU_CTRL_C1 0x1480C
6644#define B_BE_TB_PPDU_BK_DIS BIT(15)
6645#define B_BE_TB_PPDU_BE_DIS BIT(14)
6646#define B_BE_TB_PPDU_VI_DIS BIT(13)
6647#define B_BE_TB_PPDU_VO_DIS BIT(12)
6648#define B_BE_QOSNULL_UPD_MUEDCA_EN BIT(3)
6649#define B_BE_TB_BYPASS_TXPWR BIT(2)
6650#define B_BE_SW_PREFER_AC_MASK GENMASK(1, 0)
6651
6652#define R_BE_AMPDU_AGG_LIMIT 0x10810
6653#define R_BE_AMPDU_AGG_LIMIT_C1 0x14810
6654#define B_BE_AMPDU_MAX_TIME_MASK GENMASK(31, 24)
6655#define AMPDU_MAX_TIME 0x9E
6656#define B_BE_RA_TRY_RATE_AGG_LMT_MASK GENMASK(23, 16)
6657#define B_BE_RTS_MAX_AGG_NUM_MASK GENMASK(15, 8)
6658#define B_BE_MAX_AGG_NUM_MASK GENMASK(7, 0)
6659
6660#define R_BE_AGG_LEN_HT_0 0x10814
6661#define R_BE_AGG_LEN_HT_0_C1 0x14814
6662#define B_BE_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16)
6663#define B_BE_RTS_TXTIME_TH_MASK GENMASK(15, 8)
6664#define B_BE_RTS_LEN_TH_MASK GENMASK(7, 0)
6665
6666#define R_BE_SIFS_SETTING 0x10824
6667#define R_BE_SIFS_SETTING_C1 0x14824
6668#define B_BE_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24)
6669#define B_BE_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK GENMASK(23, 18)
6670#define B_BE_HW_CTS2SELF_EN BIT(16)
6671#define B_BE_SPEC_SIFS_OFDM_PTCL_MASK GENMASK(15, 8)
6672#define B_BE_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0)
6673
6674#define R_BE_TXRATE_CHK 0x10828
6675#define R_BE_TXRATE_CHK_C1 0x14828
6676#define B_BE_LATENCY_PADDING_PKT_TH_MASK GENMASK(31, 24)
6677#define B_BE_PLCP_FETCH_BUFF_MASK GENMASK(23, 16)
6678#define B_BE_OFDM_CCK_ERR_PROC BIT(6)
6679#define B_BE_PKT_LAST_TX BIT(5)
6680#define B_BE_BAND_MODE BIT(4)
6681#define B_BE_MAX_TXNSS_MASK GENMASK(3, 2)
6682#define B_BE_RTS_LIMIT_IN_OFDM6 BIT(1)
6683#define B_BE_CHECK_CCK_EN BIT(0)
6684
6685#define R_BE_TXCNT 0x1082C
6686#define R_BE_TXCNT_C1 0x1482C
6687#define B_BE_ADD_TXCNT_BY BIT(31)
6688#define B_BE_TOTAL_TC_OPT BIT(30)
6689#define B_BE_S_TXCNT_LMT_MASK GENMASK(29, 24)
6690#define B_BE_L_TXCNT_LMT_MASK GENMASK(21, 16)
6691
6692#define R_BE_MBSSID_DROP_0 0x1083C
6693#define R_BE_MBSSID_DROP_0_C1 0x1483C
6694#define B_BE_GI_LTF_FB_SEL BIT(30)
6695#define B_BE_RATE_SEL_MASK GENMASK(29, 24)
6696#define B_BE_PORT_DROP_4_0_MASK GENMASK(20, 16)
6697#define B_BE_MBSSID_DROP_15_0_MASK GENMASK(15, 0)
6698
6699#define R_BE_BT_PLT 0x1087C
6700#define R_BE_BT_PLT_C1 0x1487C
6701#define B_BE_BT_PLT_PKT_CNT_MASK GENMASK(31, 16)
6702#define B_BE_BT_PLT_RST BIT(9)
6703#define B_BE_PLT_EN BIT(8)
6704#define B_BE_RX_PLT_GNT_LTE_RX BIT(7)
6705#define B_BE_RX_PLT_GNT_BT_RX BIT(6)
6706#define B_BE_RX_PLT_GNT_BT_TX BIT(5)
6707#define B_BE_RX_PLT_GNT_WL BIT(4)
6708#define B_BE_TX_PLT_GNT_LTE_RX BIT(3)
6709#define B_BE_TX_PLT_GNT_BT_RX BIT(2)
6710#define B_BE_TX_PLT_GNT_BT_TX BIT(1)
6711#define B_BE_TX_PLT_GNT_WL BIT(0)
6712
6713#define R_BE_PTCL_BSS_COLOR_0 0x108A0
6714#define R_BE_PTCL_BSS_COLOR_0_C1 0x148A0
6715#define B_BE_BSS_COLOB_BE_PORT_3_MASK GENMASK(29, 24)
6716#define B_BE_BSS_COLOB_BE_PORT_2_MASK GENMASK(21, 16)
6717#define B_BE_BSS_COLOB_BE_PORT_1_MASK GENMASK(13, 8)
6718#define B_BE_BSS_COLOB_BE_PORT_0_MASK GENMASK(5, 0)
6719
6720#define R_BE_PTCL_BSS_COLOR_1 0x108A4
6721#define R_BE_PTCL_BSS_COLOR_1_C1 0x148A4
6722#define B_BE_BSS_COLOB_BE_PORT_4_MASK GENMASK(5, 0)
6723
6724#define R_BE_PTCL_IMR_2 0x108B8
6725#define R_BE_PTCL_IMR_2_C1 0x148B8
6726#define B_BE_NO_TRX_TIMEOUT_IMR BIT(1)
6727#define B_BE_TX_IDLE_TIMEOUT_IMR BIT(0)
6728#define B_BE_PTCL_IMR_2_CLR B_BE_TX_IDLE_TIMEOUT_IMR
6729#define B_BE_PTCL_IMR_2_SET 0
6730
6731#define R_BE_PTCL_IMR0 0x108C0
6732#define R_BE_PTCL_IMR0_C1 0x148C0
6733#define B_BE_PTCL_ERROR_FLAG_IMR BIT(31)
6734#define B_BE_FSM1_TIMEOUT_ERR_INT_EN BIT(1)
6735#define B_BE_FSM_TIMEOUT_ERR_INT_EN BIT(0)
6736#define B_BE_PTCL_IMR0_CLR (B_BE_FSM_TIMEOUT_ERR_INT_EN | \
6737			    B_BE_FSM1_TIMEOUT_ERR_INT_EN | \
6738			    B_BE_PTCL_ERROR_FLAG_IMR)
6739#define B_BE_PTCL_IMR0_SET (B_BE_FSM_TIMEOUT_ERR_INT_EN | \
6740			    B_BE_FSM1_TIMEOUT_ERR_INT_EN | \
6741			    B_BE_PTCL_ERROR_FLAG_IMR)
6742
6743#define R_BE_PTCL_ISR0 0x108C4
6744#define R_BE_PTCL_ISR0_C1 0x148C4
6745#define B_BE_PTCL_ERROR_FLAG_ISR BIT(31)
6746#define B_BE_FSM1_TIMEOUT_ERR BIT(1)
6747#define B_BE_FSM_TIMEOUT_ERR BIT(0)
6748
6749#define R_BE_PTCL_IMR1 0x108C8
6750#define R_BE_PTCL_IMR1_C1 0x148C8
6751#define B_BE_F2PCMD_PKTID_IMR BIT(30)
6752#define B_BE_F2PCMD_RD_PKTID_IMR BIT(29)
6753#define B_BE_F2PCMD_ASSIGN_PKTID_IMR BIT(28)
6754#define B_BE_F2PCMD_USER_ALLC_IMR BIT(27)
6755#define B_BE_RX_SPF_U0_PKTID_IMR BIT(26)
6756#define B_BE_TX_SPF_U1_PKTID_IMR BIT(25)
6757#define B_BE_TX_SPF_U2_PKTID_IMR BIT(24)
6758#define B_BE_TX_SPF_U3_PKTID_IMR BIT(23)
6759#define B_BE_TX_RECORD_PKTID_IMR BIT(22)
6760#define B_BE_TWTSP_QSEL_IMR BIT(14)
6761#define B_BE_F2P_RLS_CTN_SEL_IMR BIT(13)
6762#define B_BE_BCNQ_ORDER_IMR BIT(12)
6763#define B_BE_Q_PKTID_IMR BIT(11)
6764#define B_BE_D_PKTID_IMR BIT(10)
6765#define B_BE_TXPRT_FULL_DROP_IMR BIT(9)
6766#define B_BE_F2PCMDRPT_FULL_DROP_IMR BIT(8)
6767#define B_BE_PTCL_IMR1_CLR (B_BE_F2PCMDRPT_FULL_DROP_IMR | \
6768			    B_BE_TXPRT_FULL_DROP_IMR | \
6769			    B_BE_D_PKTID_IMR | \
6770			    B_BE_Q_PKTID_IMR | \
6771			    B_BE_BCNQ_ORDER_IMR | \
6772			    B_BE_F2P_RLS_CTN_SEL_IMR | \
6773			    B_BE_TWTSP_QSEL_IMR | \
6774			    B_BE_TX_RECORD_PKTID_IMR | \
6775			    B_BE_TX_SPF_U3_PKTID_IMR | \
6776			    B_BE_TX_SPF_U2_PKTID_IMR | \
6777			    B_BE_TX_SPF_U1_PKTID_IMR | \
6778			    B_BE_RX_SPF_U0_PKTID_IMR | \
6779			    B_BE_F2PCMD_USER_ALLC_IMR | \
6780			    B_BE_F2PCMD_ASSIGN_PKTID_IMR | \
6781			    B_BE_F2PCMD_RD_PKTID_IMR | \
6782			    B_BE_F2PCMD_PKTID_IMR)
6783#define B_BE_PTCL_IMR1_SET B_BE_F2PCMD_USER_ALLC_IMR
6784
6785#define R_BE_PTCL_ISR1 0x108CC
6786#define R_BE_PTCL_ISR1_C1 0x148CC
6787#define B_BE_F2PCMD_PKTID_ERR BIT(30)
6788#define B_BE_F2PCMD_RD_PKTID_ERR BIT(29)
6789#define B_BE_F2PCMD_ASSIGN_PKTID_ERR BIT(28)
6790#define B_BE_F2PCMD_USER_ALLC_ERR BIT(27)
6791#define B_BE_RX_SPF_U0_PKTID_ERR BIT(26)
6792#define B_BE_TX_SPF_U1_PKTID_ERR BIT(25)
6793#define B_BE_TX_SPF_U2_PKTID_ERR BIT(24)
6794#define B_BE_TX_SPF_U3_PKTID_ERR BIT(23)
6795#define B_BE_TX_RECORD_PKTID_ERR BIT(22)
6796#define B_BE_TWTSP_QSEL_ERR BIT(14)
6797#define B_BE_F2P_RLS_CTN_SEL_ERR BIT(13)
6798#define B_BE_BCNQ_ORDER_ERR BIT(12)
6799#define B_BE_Q_PKTID_ERR BIT(11)
6800#define B_BE_D_PKTID_ERR BIT(10)
6801#define B_BE_TXPRT_FULL_DROP_ERR BIT(9)
6802#define B_BE_F2PCMDRPT_FULL_DROP_ERR BIT(8)
6803
6804#define R_BE_PTCL_FSM_MON 0x108E8
6805#define R_BE_PTCL_FSM_MON_C1 0x148E8
6806#define B_BE_PTCL_FSM2_TO_MODE BIT(30)
6807#define B_BE_PTCL_FSM2_TO_THR_MASK GENMASK(29, 24)
6808#define B_BE_PTCL_FSM1_TO_MODE BIT(22)
6809#define B_BE_PTCL_FSM1_TO_THR_MASK GENMASK(21, 16)
6810#define B_BE_PTCL_FSM0_TO_MODE BIT(14)
6811#define B_BE_PTCL_FSM0_TO_THR_MASK GENMASK(13, 8)
6812#define B_BE_PTCL_TX_ARB_TO_MODE BIT(6)
6813#define B_BE_PTCL_TX_ARB_TO_THR_MASK GENMASK(5, 0)
6814
6815#define R_BE_PTCL_TX_CTN_SEL 0x108EC
6816#define R_BE_PTCL_TX_CTN_SEL_C1 0x148EC
6817#define B_BE_PTCL_TXOP_STAT BIT(8)
6818#define B_BE_PTCL_BUSY BIT(7)
6819#define B_BE_PTCL_DROP BIT(5)
6820#define B_BE_PTCL_TX_QUEUE_IDX_MASK GENMASK(4, 0)
6821
6822#define R_BE_PTCL_DBG_INFO 0x108F0
6823
6824#define R_BE_PTCL_DBG 0x108F4
6825
6826#define R_BE_RX_ERROR_FLAG 0x10C00
6827#define R_BE_RX_ERROR_FLAG_C1 0x14C00
6828#define B_BE_RX_CSI_NOT_RELEASE_ERROR BIT(31)
6829#define B_BE_RX_GET_NULL_PKT_ERROR BIT(30)
6830#define B_BE_RX_RU0_FSM_HANG_ERROR BIT(29)
6831#define B_BE_RX_RU1_FSM_HANG_ERROR BIT(28)
6832#define B_BE_RX_RU2_FSM_HANG_ERROR BIT(27)
6833#define B_BE_RX_RU3_FSM_HANG_ERROR BIT(26)
6834#define B_BE_RX_RU4_FSM_HANG_ERROR BIT(25)
6835#define B_BE_RX_RU5_FSM_HANG_ERROR BIT(24)
6836#define B_BE_RX_RU6_FSM_HANG_ERROR BIT(23)
6837#define B_BE_RX_RU7_FSM_HANG_ERROR BIT(22)
6838#define B_BE_RX_RXSTS_FSM_HANG_ERROR BIT(21)
6839#define B_BE_RX_CSI_FSM_HANG_ERROR BIT(20)
6840#define B_BE_RX_TXRPT_FSM_HANG_ERROR BIT(19)
6841#define B_BE_RX_F2PCMD_FSM_HANG_ERROR BIT(18)
6842#define B_BE_RX_RU0_ZERO_LENGTH_ERROR BIT(17)
6843#define B_BE_RX_RU1_ZERO_LENGTH_ERROR BIT(16)
6844#define B_BE_RX_RU2_ZERO_LENGTH_ERROR BIT(15)
6845#define B_BE_RX_RU3_ZERO_LENGTH_ERROR BIT(14)
6846#define B_BE_RX_RU4_ZERO_LENGTH_ERROR BIT(13)
6847#define B_BE_RX_RU5_ZERO_LENGTH_ERROR BIT(12)
6848#define B_BE_RX_RU6_ZERO_LENGTH_ERROR BIT(11)
6849#define B_BE_RX_RU7_ZERO_LENGTH_ERROR BIT(10)
6850#define B_BE_RX_RXSTS_ZERO_LENGTH_ERROR BIT(9)
6851#define B_BE_RX_CSI_ZERO_LENGTH_ERROR BIT(8)
6852#define B_BE_PLE_DATA_OPT_FSM_HANG BIT(7)
6853#define B_BE_PLE_RXDATA_REQUEST_BUFFER_FSM_HANG BIT(6)
6854#define B_BE_PLE_TXRPT_REQUEST_BUFFER_FSM_HANG BIT(5)
6855#define B_BE_PLE_WD_OPT_FSM_HANG BIT(4)
6856#define B_BE_PLE_ENQ_FSM_HANG BIT(3)
6857#define B_BE_RXDATA_ENQUE_ORDER_ERROR BIT(2)
6858#define B_BE_RXSTS_ENQUE_ORDER_ERROR BIT(1)
6859#define B_BE_RX_CSI_PKT_NUM_ERROR BIT(0)
6860
6861#define R_BE_RX_ERROR_FLAG_IMR 0x10C04
6862#define R_BE_RX_ERROR_FLAG_IMR_C1 0x14C04
6863#define B_BE_RX_CSI_NOT_RELEASE_ERROR_IMR BIT(31)
6864#define B_BE_RX_GET_NULL_PKT_ERROR_IMR BIT(30)
6865#define B_BE_RX_RU0_FSM_HANG_ERROR_IMR BIT(29)
6866#define B_BE_RX_RU1_FSM_HANG_ERROR_IMR BIT(28)
6867#define B_BE_RX_RU2_FSM_HANG_ERROR_IMR BIT(27)
6868#define B_BE_RX_RU3_FSM_HANG_ERROR_IMR BIT(26)
6869#define B_BE_RX_RU4_FSM_HANG_ERROR_IMR BIT(25)
6870#define B_BE_RX_RU5_FSM_HANG_ERROR_IMR BIT(24)
6871#define B_BE_RX_RU6_FSM_HANG_ERROR_IMR BIT(23)
6872#define B_BE_RX_RU7_FSM_HANG_ERROR_IMR BIT(22)
6873#define B_BE_RX_RXSTS_FSM_HANG_ERROR_IMR BIT(21)
6874#define B_BE_RX_CSI_FSM_HANG_ERROR_IMR BIT(20)
6875#define B_BE_RX_TXRPT_FSM_HANG_ERROR_IMR BIT(19)
6876#define B_BE_RX_F2PCMD_FSM_HANG_ERROR_IMR BIT(18)
6877#define B_BE_RX_RU0_ZERO_LENGTH_ERROR_IMR BIT(17)
6878#define B_BE_RX_RU1_ZERO_LENGTH_ERROR_IMR BIT(16)
6879#define B_BE_RX_RU2_ZERO_LENGTH_ERROR_IMR BIT(15)
6880#define B_BE_RX_RU3_ZERO_LENGTH_ERROR_IMR BIT(14)
6881#define B_BE_RX_RU4_ZERO_LENGTH_ERROR_IMR BIT(13)
6882#define B_BE_RX_RU5_ZERO_LENGTH_ERROR_IMR BIT(12)
6883#define B_BE_RX_RU6_ZERO_LENGTH_ERROR_IMR BIT(11)
6884#define B_BE_RX_RU7_ZERO_LENGTH_ERROR_IMR BIT(10)
6885#define B_BE_RX_RXSTS_ZERO_LENGTH_ERROR_IMR BIT(9)
6886#define B_BE_RX_CSI_ZERO_LENGTH_ERROR_IMR BIT(8)
6887#define B_BE_PLE_DATA_OPT_FSM_HANG_IMR BIT(7)
6888#define B_BE_PLE_RXDATA_REQUEST_BUFFER_FSM_HANG_IMR BIT(6)
6889#define B_BE_PLE_TXRPT_REQUEST_BUFFER_FSM_HANG_IMR BIT(5)
6890#define B_BE_PLE_WD_OPT_FSM_HANG_IMR BIT(4)
6891#define B_BE_PLE_ENQ_FSM_HANG_IMR BIT(3)
6892#define B_BE_RXDATA_ENQUE_ORDER_ERROR_IMR BIT(2)
6893#define B_BE_RXSTS_ENQUE_ORDER_ERROR_IMR BIT(1)
6894#define B_BE_RX_CSI_PKT_NUM_ERROR_IMR BIT(0)
6895#define B_BE_RX_ERROR_FLAG_IMR_CLR (B_BE_RX_RXSTS_ZERO_LENGTH_ERROR_IMR | \
6896				    B_BE_RX_RU7_ZERO_LENGTH_ERROR_IMR | \
6897				    B_BE_RX_RU6_ZERO_LENGTH_ERROR_IMR | \
6898				    B_BE_RX_RU5_ZERO_LENGTH_ERROR_IMR | \
6899				    B_BE_RX_RU4_ZERO_LENGTH_ERROR_IMR | \
6900				    B_BE_RX_RU3_ZERO_LENGTH_ERROR_IMR | \
6901				    B_BE_RX_RU2_ZERO_LENGTH_ERROR_IMR | \
6902				    B_BE_RX_RU1_ZERO_LENGTH_ERROR_IMR | \
6903				    B_BE_RX_RU0_ZERO_LENGTH_ERROR_IMR | \
6904				    B_BE_RX_F2PCMD_FSM_HANG_ERROR_IMR | \
6905				    B_BE_RX_TXRPT_FSM_HANG_ERROR_IMR | \
6906				    B_BE_RX_CSI_FSM_HANG_ERROR_IMR | \
6907				    B_BE_RX_RXSTS_FSM_HANG_ERROR_IMR | \
6908				    B_BE_RX_RU7_FSM_HANG_ERROR_IMR | \
6909				    B_BE_RX_RU6_FSM_HANG_ERROR_IMR | \
6910				    B_BE_RX_RU5_FSM_HANG_ERROR_IMR | \
6911				    B_BE_RX_RU4_FSM_HANG_ERROR_IMR | \
6912				    B_BE_RX_RU3_FSM_HANG_ERROR_IMR | \
6913				    B_BE_RX_RU2_FSM_HANG_ERROR_IMR | \
6914				    B_BE_RX_RU1_FSM_HANG_ERROR_IMR | \
6915				    B_BE_RX_RU0_FSM_HANG_ERROR_IMR | \
6916				    B_BE_RX_GET_NULL_PKT_ERROR_IMR)
6917#define B_BE_RX_ERROR_FLAG_IMR_SET (B_BE_RX_RXSTS_ZERO_LENGTH_ERROR_IMR | \
6918				    B_BE_RX_RU7_ZERO_LENGTH_ERROR_IMR | \
6919				    B_BE_RX_RU6_ZERO_LENGTH_ERROR_IMR | \
6920				    B_BE_RX_RU5_ZERO_LENGTH_ERROR_IMR | \
6921				    B_BE_RX_RU4_ZERO_LENGTH_ERROR_IMR | \
6922				    B_BE_RX_RU3_ZERO_LENGTH_ERROR_IMR | \
6923				    B_BE_RX_RU2_ZERO_LENGTH_ERROR_IMR | \
6924				    B_BE_RX_RU1_ZERO_LENGTH_ERROR_IMR | \
6925				    B_BE_RX_RU0_ZERO_LENGTH_ERROR_IMR | \
6926				    B_BE_RX_F2PCMD_FSM_HANG_ERROR_IMR | \
6927				    B_BE_RX_TXRPT_FSM_HANG_ERROR_IMR | \
6928				    B_BE_RX_CSI_FSM_HANG_ERROR_IMR | \
6929				    B_BE_RX_RXSTS_FSM_HANG_ERROR_IMR | \
6930				    B_BE_RX_RU7_FSM_HANG_ERROR_IMR | \
6931				    B_BE_RX_RU6_FSM_HANG_ERROR_IMR | \
6932				    B_BE_RX_RU5_FSM_HANG_ERROR_IMR | \
6933				    B_BE_RX_RU4_FSM_HANG_ERROR_IMR | \
6934				    B_BE_RX_RU3_FSM_HANG_ERROR_IMR | \
6935				    B_BE_RX_RU2_FSM_HANG_ERROR_IMR | \
6936				    B_BE_RX_RU1_FSM_HANG_ERROR_IMR | \
6937				    B_BE_RX_RU0_FSM_HANG_ERROR_IMR | \
6938				    B_BE_RX_GET_NULL_PKT_ERROR_IMR)
6939
6940#define R_BE_RX_CTRL_1 0x10C0C
6941#define R_BE_RX_CTRL_1_C1 0x14C0C
6942#define B_BE_RXDMA_TXRPT_QUEUE_ID_SW_MASK GENMASK(30, 25)
6943#define B_BE_RXDMA_F2PCMDRPT_QUEUE_ID_SW_MASK GENMASK(23, 18)
6944#define B_BE_RXDMA_TXRPT_PORT_ID_SW_MASK GENMASK(17, 14)
6945#define B_BE_RXDMA_F2PCMDRPT_PORT_ID_SW_MASK GENMASK(13, 10)
6946#define B_BE_DBG_SEL_MASK GENMASK(1, 0)
6947#define WLCPU_RXCH2_QID 0xA
6948
6949#define R_BE_TX_ERROR_FLAG 0x10C6C
6950#define R_BE_TX_ERROR_FLAG_C1 0x14C6C
6951#define B_BE_TX_RU0_FSM_HANG_ERROR BIT(31)
6952#define B_BE_TX_RU1_FSM_HANG_ERROR BIT(30)
6953#define B_BE_TX_RU2_FSM_HANG_ERROR BIT(29)
6954#define B_BE_TX_RU3_FSM_HANG_ERROR BIT(28)
6955#define B_BE_TX_RU4_FSM_HANG_ERROR BIT(27)
6956#define B_BE_TX_RU5_FSM_HANG_ERROR BIT(26)
6957#define B_BE_TX_RU6_FSM_HANG_ERROR BIT(25)
6958#define B_BE_TX_RU7_FSM_HANG_ERROR BIT(24)
6959#define B_BE_TX_RU8_FSM_HANG_ERROR BIT(23)
6960#define B_BE_TX_RU9_FSM_HANG_ERROR BIT(22)
6961#define B_BE_TX_RU10_FSM_HANG_ERROR BIT(21)
6962#define B_BE_TX_RU11_FSM_HANG_ERROR BIT(20)
6963#define B_BE_TX_RU12_FSM_HANG_ERROR BIT(19)
6964#define B_BE_TX_RU13_FSM_HANG_ERROR BIT(18)
6965#define B_BE_TX_RU14_FSM_HANG_ERROR BIT(17)
6966#define B_BE_TX_RU15_FSM_HANG_ERROR BIT(16)
6967#define B_BE_TX_CSI_FSM_HANG_ERROR BIT(15)
6968#define B_BE_TX_WD_PLD_ID_FSM_HANG_ERROR BIT(14)
6969
6970#define R_BE_TX_ERROR_FLAG_IMR 0x10C70
6971#define R_BE_TX_ERROR_FLAG_IMR_C1 0x14C70
6972#define B_BE_TX_RU0_FSM_HANG_ERROR_IMR BIT(31)
6973#define B_BE_TX_RU1_FSM_HANG_ERROR_IMR BIT(30)
6974#define B_BE_TX_RU2_FSM_HANG_ERROR_IMR BIT(29)
6975#define B_BE_TX_RU3_FSM_HANG_ERROR_IMR BIT(28)
6976#define B_BE_TX_RU4_FSM_HANG_ERROR_IMR BIT(27)
6977#define B_BE_TX_RU5_FSM_HANG_ERROR_IMR BIT(26)
6978#define B_BE_TX_RU6_FSM_HANG_ERROR_IMR BIT(25)
6979#define B_BE_TX_RU7_FSM_HANG_ERROR_IMR BIT(24)
6980#define B_BE_TX_RU8_FSM_HANG_ERROR_IMR BIT(23)
6981#define B_BE_TX_RU9_FSM_HANG_ERROR_IMR BIT(22)
6982#define B_BE_TX_RU10_FSM_HANG_ERROR_IMR BIT(21)
6983#define B_BE_TX_RU11_FSM_HANG_ERROR_IMR BIT(20)
6984#define B_BE_TX_RU12_FSM_HANG_ERROR_IMR BIT(19)
6985#define B_BE_TX_RU13_FSM_HANG_ERROR_IMR BIT(18)
6986#define B_BE_TX_RU14_FSM_HANG_ERROR_IMR BIT(17)
6987#define B_BE_TX_RU15_FSM_HANG_ERROR_IMR BIT(16)
6988#define B_BE_TX_CSI_FSM_HANG_ERROR_IMR BIT(15)
6989#define B_BE_TX_WD_PLD_ID_FSM_HANG_ERROR_IMR BIT(14)
6990#define B_BE_TX_ERROR_FLAG_IMR_CLR (B_BE_TX_WD_PLD_ID_FSM_HANG_ERROR_IMR | \
6991				    B_BE_TX_CSI_FSM_HANG_ERROR_IMR | \
6992				    B_BE_TX_RU15_FSM_HANG_ERROR_IMR | \
6993				    B_BE_TX_RU14_FSM_HANG_ERROR_IMR | \
6994				    B_BE_TX_RU13_FSM_HANG_ERROR_IMR | \
6995				    B_BE_TX_RU12_FSM_HANG_ERROR_IMR | \
6996				    B_BE_TX_RU11_FSM_HANG_ERROR_IMR | \
6997				    B_BE_TX_RU10_FSM_HANG_ERROR_IMR | \
6998				    B_BE_TX_RU9_FSM_HANG_ERROR_IMR | \
6999				    B_BE_TX_RU8_FSM_HANG_ERROR_IMR | \
7000				    B_BE_TX_RU7_FSM_HANG_ERROR_IMR | \
7001				    B_BE_TX_RU6_FSM_HANG_ERROR_IMR | \
7002				    B_BE_TX_RU5_FSM_HANG_ERROR_IMR | \
7003				    B_BE_TX_RU4_FSM_HANG_ERROR_IMR | \
7004				    B_BE_TX_RU3_FSM_HANG_ERROR_IMR | \
7005				    B_BE_TX_RU2_FSM_HANG_ERROR_IMR | \
7006				    B_BE_TX_RU1_FSM_HANG_ERROR_IMR | \
7007				    B_BE_TX_RU0_FSM_HANG_ERROR_IMR)
7008#define B_BE_TX_ERROR_FLAG_IMR_SET (B_BE_TX_WD_PLD_ID_FSM_HANG_ERROR_IMR | \
7009				    B_BE_TX_CSI_FSM_HANG_ERROR_IMR | \
7010				    B_BE_TX_RU15_FSM_HANG_ERROR_IMR | \
7011				    B_BE_TX_RU14_FSM_HANG_ERROR_IMR | \
7012				    B_BE_TX_RU13_FSM_HANG_ERROR_IMR | \
7013				    B_BE_TX_RU12_FSM_HANG_ERROR_IMR | \
7014				    B_BE_TX_RU11_FSM_HANG_ERROR_IMR | \
7015				    B_BE_TX_RU10_FSM_HANG_ERROR_IMR | \
7016				    B_BE_TX_RU9_FSM_HANG_ERROR_IMR | \
7017				    B_BE_TX_RU8_FSM_HANG_ERROR_IMR | \
7018				    B_BE_TX_RU7_FSM_HANG_ERROR_IMR | \
7019				    B_BE_TX_RU6_FSM_HANG_ERROR_IMR | \
7020				    B_BE_TX_RU5_FSM_HANG_ERROR_IMR | \
7021				    B_BE_TX_RU4_FSM_HANG_ERROR_IMR | \
7022				    B_BE_TX_RU3_FSM_HANG_ERROR_IMR | \
7023				    B_BE_TX_RU2_FSM_HANG_ERROR_IMR | \
7024				    B_BE_TX_RU1_FSM_HANG_ERROR_IMR | \
7025				    B_BE_TX_RU0_FSM_HANG_ERROR_IMR)
7026
7027#define R_BE_RX_ERROR_FLAG_1 0x10C84
7028#define R_BE_RX_ERROR_FLAG_1_C1 0x14C84
7029#define B_BE_RX_RU8_FSM_HANG_ERROR BIT(29)
7030#define B_BE_RX_RU9_FSM_HANG_ERROR BIT(28)
7031#define B_BE_RX_RU10_FSM_HANG_ERROR BIT(27)
7032#define B_BE_RX_RU11_FSM_HANG_ERROR BIT(26)
7033#define B_BE_RX_RU12_FSM_HANG_ERROR BIT(25)
7034#define B_BE_RX_RU13_FSM_HANG_ERROR BIT(24)
7035#define B_BE_RX_RU14_FSM_HANG_ERROR BIT(23)
7036#define B_BE_RX_RU15_FSM_HANG_ERROR BIT(22)
7037#define B_BE_RX_RU8_ZERO_LENGTH_ERROR BIT(17)
7038#define B_BE_RX_RU9_ZERO_LENGTH_ERROR BIT(16)
7039#define B_BE_RX_RU10_ZERO_LENGTH_ERROR BIT(15)
7040#define B_BE_RX_RU11_ZERO_LENGTH_ERROR BIT(14)
7041#define B_BE_RX_RU12_ZERO_LENGTH_ERROR BIT(13)
7042#define B_BE_RX_RU13_ZERO_LENGTH_ERROR BIT(12)
7043#define B_BE_RX_RU14_ZERO_LENGTH_ERROR BIT(11)
7044#define B_BE_RX_RU15_ZERO_LENGTH_ERROR BIT(10)
7045
7046#define R_BE_RX_ERROR_FLAG_IMR_1 0x10C88
7047#define R_BE_RX_ERROR_FLAG_IMR_1_C1 0x14C88
7048#define B_BE_RX_RU8_FSM_HANG_ERROR_IMR BIT(29)
7049#define B_BE_RX_RU9_FSM_HANG_ERROR_IMR BIT(28)
7050#define B_BE_RX_RU10_FSM_HANG_ERROR_IMR BIT(27)
7051#define B_BE_RX_RU11_FSM_HANG_ERROR_IMR BIT(26)
7052#define B_BE_RX_RU12_FSM_HANG_ERROR_IMR BIT(25)
7053#define B_BE_RX_RU13_FSM_HANG_ERROR_IMR BIT(24)
7054#define B_BE_RX_RU14_FSM_HANG_ERROR_IMR BIT(23)
7055#define B_BE_RX_RU15_FSM_HANG_ERROR_IMR BIT(22)
7056#define B_BE_RX_RU8_ZERO_LENGTH_ERROR_IMR BIT(17)
7057#define B_BE_RX_RU9_ZERO_LENGTH_ERROR_IMR BIT(16)
7058#define B_BE_RX_RU10_ZERO_LENGTH_ERROR_IMR BIT(15)
7059#define B_BE_RX_RU11_ZERO_LENGTH_ERROR_IMR BIT(14)
7060#define B_BE_RX_RU12_ZERO_LENGTH_ERROR_IMR BIT(13)
7061#define B_BE_RX_RU13_ZERO_LENGTH_ERROR_IMR BIT(12)
7062#define B_BE_RX_RU14_ZERO_LENGTH_ERROR_IMR BIT(11)
7063#define B_BE_RX_RU15_ZERO_LENGTH_ERROR_IMR BIT(10)
7064#define B_BE_TX_ERROR_FLAG_IMR_1_CLR (B_BE_RX_RU8_FSM_HANG_ERROR_IMR | \
7065				      B_BE_RX_RU9_FSM_HANG_ERROR_IMR | \
7066				      B_BE_RX_RU10_FSM_HANG_ERROR_IMR | \
7067				      B_BE_RX_RU11_FSM_HANG_ERROR_IMR | \
7068				      B_BE_RX_RU12_FSM_HANG_ERROR_IMR | \
7069				      B_BE_RX_RU13_FSM_HANG_ERROR_IMR | \
7070				      B_BE_RX_RU14_FSM_HANG_ERROR_IMR | \
7071				      B_BE_RX_RU15_FSM_HANG_ERROR_IMR | \
7072				      B_BE_RX_RU8_ZERO_LENGTH_ERROR_IMR | \
7073				      B_BE_RX_RU9_ZERO_LENGTH_ERROR_IMR | \
7074				      B_BE_RX_RU10_ZERO_LENGTH_ERROR_IMR | \
7075				      B_BE_RX_RU11_ZERO_LENGTH_ERROR_IMR | \
7076				      B_BE_RX_RU12_ZERO_LENGTH_ERROR_IMR | \
7077				      B_BE_RX_RU13_ZERO_LENGTH_ERROR_IMR | \
7078				      B_BE_RX_RU14_ZERO_LENGTH_ERROR_IMR | \
7079				      B_BE_RX_RU15_ZERO_LENGTH_ERROR_IMR)
7080#define B_BE_TX_ERROR_FLAG_IMR_1_SET (B_BE_RX_RU8_FSM_HANG_ERROR_IMR | \
7081				      B_BE_RX_RU9_FSM_HANG_ERROR_IMR | \
7082				      B_BE_RX_RU10_FSM_HANG_ERROR_IMR | \
7083				      B_BE_RX_RU11_FSM_HANG_ERROR_IMR | \
7084				      B_BE_RX_RU12_FSM_HANG_ERROR_IMR | \
7085				      B_BE_RX_RU13_FSM_HANG_ERROR_IMR | \
7086				      B_BE_RX_RU14_FSM_HANG_ERROR_IMR | \
7087				      B_BE_RX_RU15_FSM_HANG_ERROR_IMR | \
7088				      B_BE_RX_RU8_ZERO_LENGTH_ERROR_IMR | \
7089				      B_BE_RX_RU9_ZERO_LENGTH_ERROR_IMR | \
7090				      B_BE_RX_RU10_ZERO_LENGTH_ERROR_IMR | \
7091				      B_BE_RX_RU11_ZERO_LENGTH_ERROR_IMR | \
7092				      B_BE_RX_RU12_ZERO_LENGTH_ERROR_IMR | \
7093				      B_BE_RX_RU13_ZERO_LENGTH_ERROR_IMR | \
7094				      B_BE_RX_RU14_ZERO_LENGTH_ERROR_IMR | \
7095				      B_BE_RX_RU15_ZERO_LENGTH_ERROR_IMR)
7096
7097#define R_BE_WMTX_MOREDATA_TSFT_STMP_CTL 0x10E08
7098#define R_BE_WMTX_MOREDATA_TSFT_STMP_CTL_C1 0x14E08
7099#define B_BE_TSFT_OFS_MASK GENMASK(31, 16)
7100#define B_BE_STMP_THSD_MASK GENMASK(15, 8)
7101#define B_BE_UPD_HGQMD BIT(1)
7102#define B_BE_UPD_TIMIE BIT(0)
7103
7104#define R_BE_WMTX_POWER_BE_BIT_CTL 0x10E0C
7105#define R_BE_WMTX_POWER_BE_BIT_CTL_C1 0x14E0C
7106
7107#define R_BE_WMTX_TCR_BE_4 0x10E2C
7108#define R_BE_WMTX_TCR_BE_4_C1 0x14E2C
7109#define B_BE_UL_EHT_MUMIMO_LTF_MODE BIT(30)
7110#define B_BE_UL_HE_MUMIMO_LTF_MODE BIT(29)
7111#define B_BE_EHT_HE_PPDU_4XLTF_ZLD_USTIMER_MASK GENMASK(28, 24)
7112#define B_BE_EHT_HE_PPDU_2XLTF_ZLD_USTIMER_MASK GENMASK(20, 16)
7113#define B_BE_NON_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(12, 8)
7114#define B_BE_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(4, 0)
7115
7116#define R_BE_RSP_CHK_SIG 0x11000
7117#define R_BE_RSP_CHK_SIG_C1 0x15000
7118#define B_BE_RSP_STATIC_RTS_CHK_SERV_BW_EN BIT(30)
7119#define B_BE_RSP_TBPPDU_CHK_PWR BIT(29)
7120#define B_BE_RESP_PAIR_MACID_LEN_EN BIT(25)
7121#define B_BE_RESP_TX_ABORT_TEST_EN BIT(24)
7122#define B_BE_RESP_ER_SU_RU106_EN BIT(23)
7123#define B_BE_RESP_ER_SU_EN BIT(22)
7124#define B_BE_TXDATA_END_PS_OPT BIT(18)
7125#define B_BE_CHECK_SOUNDING_SEQ BIT(17)
7126#define B_BE_RXBA_IGNOREA2 BIT(16)
7127#define B_BE_ACKTO_CCK_MASK GENMASK(15, 8)
7128#define B_BE_ACKTO_MASK GENMASK(8, 0)
7129
7130#define R_BE_TRXPTCL_RESP_0 0x11004
7131#define R_BE_TRXPTCL_RESP_0_C1 0x15004
7132#define B_BE_WMAC_RESP_STBC_EN BIT(31)
7133#define B_BE_WMAC_RXFTM_TXACK_SB BIT(30)
7134#define B_BE_WMAC_RXFTM_TXACKBWEQ BIT(29)
7135#define B_BE_RESP_TB_CHK_TXTIME BIT(24)
7136#define B_BE_RSP_CHK_CCA BIT(23)
7137#define B_BE_WMAC_LDPC_EN BIT(22)
7138#define B_BE_WMAC_SGIEN BIT(21)
7139#define B_BE_WMAC_SPLCPEN BIT(20)
7140#define B_BE_RESP_EHT_MCS15_REF BIT(19)
7141#define B_BE_RESP_EHT_MCS14_REF BIT(18)
7142#define B_BE_WMAC_BESP_EARLY_TXBA BIT(17)
7143#define B_BE_WMAC_MBA_DUR_FORCE BIT(16)
7144#define B_BE_WMAC_SPEC_SIFS_OFDM_MASK GENMASK(15, 8)
7145#define WMAC_SPEC_SIFS_OFDM_1115E 0x11
7146#define B_BE_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0)
7147
7148#define R_BE_TRXPTCL_RESP_1 0x11008
7149#define R_BE_TRXPTCL_RESP_1_C1 0x15008
7150#define B_BE_WMAC_RESP_SR_MODE_EN BIT(31)
7151#define B_BE_FTM_RRSR_RATE_EN_MASK GENMASK(28, 24)
7152#define B_BE_NESS_MASK GENMASK(23, 22)
7153#define B_BE_WMAC_RESP_DOPPLEB_BE_EN BIT(21)
7154#define B_BE_WMAC_RESP_DCM_EN BIT(20)
7155#define B_BE_WMAC_CLR_ABORT_RESP_TX_CNT BIT(15)
7156#define B_BE_WMAC_RESP_REF_RATE_SEL BIT(12)
7157#define B_BE_WMAC_RESP_REF_RATE_MASK GENMASK(11, 0)
7158
7159#define R_BE_MAC_LOOPBACK 0x11020
7160#define R_BE_MAC_LOOPBACK_C1 0x15020
7161#define B_BE_MACLBK_DIS_GCLK BIT(30)
7162#define B_BE_MACLBK_STS_EN BIT(29)
7163#define B_BE_MACLBK_RDY_PERIOD_MASK GENMASK(28, 17)
7164#define B_BE_MACLBK_PLCP_DLY_MASK GENMASK(16, 8)
7165#define S_BE_MACLBK_PLCP_DLY_DEF 0x28
7166#define B_BE_MACLBK_RDY_NUM_MASK GENMASK(7, 3)
7167#define B_BE_MACLBK_EN BIT(0)
7168
7169#define R_BE_CLIENT_OM_CTRL 0x11040
7170#define R_BE_CLIENT_OM_CTRL_C1 0x15040
7171#define B_BE_TRIG_DIS_EHTTB BIT(24)
7172
7173#define R_BE_WMAC_NAV_CTL 0x11080
7174#define R_BE_WMAC_NAV_CTL_C1 0x15080
7175#define B_BE_WMAC_NAV_UPPER_EN BIT(26)
7176#define B_BE_WMAC_0P125US_TIMER_MASK GENMASK(25, 18)
7177#define B_BE_WMAC_PLCP_UP_NAV_EN BIT(17)
7178#define B_BE_WMAC_TF_UP_NAV_EN BIT(16)
7179#define B_BE_WMAC_NAV_UPPER_MASK GENMASK(15, 8)
7180#define NAV_25MS 0xC4
7181#define B_BE_WMAC_RTS_RST_DUR_MASK GENMASK(7, 0)
7182
7183#define R_BE_RXTRIG_TEST_USER_2 0x110B0
7184#define R_BE_RXTRIG_TEST_USER_2_C1 0x150B0
7185#define B_BE_RXTRIG_MACID_MASK GENMASK(31, 24)
7186#define B_BE_RXTRIG_RU26_DIS BIT(21)
7187#define B_BE_RXTRIG_FCSCHK_EN BIT(20)
7188#define B_BE_RXTRIG_PORT_SEL_MASK GENMASK(19, 17)
7189#define B_BE_RXTRIG_EN BIT(16)
7190#define B_BE_RXTRIG_USERINFO_2_MASK GENMASK(15, 0)
7191
7192#define R_BE_TRXPTCL_ERROR_INDICA_MASK 0x110BC
7193#define R_BE_TRXPTCL_ERROR_INDICA_MASK_C1 0x150BC
7194#define B_BE_WMAC_FTM_TIMEOUT_MODE BIT(30)
7195#define B_BE_WMAC_FTM_TIMEOUT_THR_MASK GENMASK(29, 24)
7196#define B_BE_WMAC_MODE BIT(22)
7197#define B_BE_WMAC_TIMETOUT_THR_MASK GENMASK(21, 16)
7198#define B_BE_RMAC_BFMER BIT(9)
7199#define B_BE_RMAC_FTM BIT(8)
7200#define B_BE_RMAC_CSI BIT(7)
7201#define B_BE_TMAC_MIMO_CTRL BIT(6)
7202#define B_BE_TMAC_RXTB BIT(5)
7203#define B_BE_TMAC_HWSIGB_GEN BIT(4)
7204#define B_BE_TMAC_TXPLCP BIT(3)
7205#define B_BE_TMAC_RESP BIT(2)
7206#define B_BE_TMAC_TXCTL BIT(1)
7207#define B_BE_TMAC_MACTX BIT(0)
7208#define B_BE_TRXPTCL_ERROR_INDICA_MASK_CLR (B_BE_TMAC_MACTX | \
7209					    B_BE_TMAC_TXCTL | \
7210					    B_BE_TMAC_RESP | \
7211					    B_BE_TMAC_TXPLCP | \
7212					    B_BE_TMAC_HWSIGB_GEN | \
7213					    B_BE_TMAC_RXTB | \
7214					    B_BE_TMAC_MIMO_CTRL | \
7215					    B_BE_RMAC_CSI | \
7216					    B_BE_RMAC_FTM | \
7217					    B_BE_RMAC_BFMER)
7218#define B_BE_TRXPTCL_ERROR_INDICA_MASK_SET (B_BE_TMAC_MACTX | \
7219					    B_BE_TMAC_TXCTL | \
7220					    B_BE_TMAC_RESP | \
7221					    B_BE_TMAC_TXPLCP | \
7222					    B_BE_TMAC_HWSIGB_GEN | \
7223					    B_BE_TMAC_RXTB | \
7224					    B_BE_TMAC_MIMO_CTRL | \
7225					    B_BE_RMAC_CSI | \
7226					    B_BE_RMAC_FTM | \
7227					    B_BE_RMAC_BFMER)
7228
7229#define R_BE_TRXPTCL_ERROR_INDICA 0x110C0
7230#define R_BE_TRXPTCL_ERROR_INDICA_C1 0x150C0
7231#define B_BE_BFMER_ERR_FLAG BIT(9)
7232#define B_BE_FTM_ERROR_FLAG_CLR BIT(8)
7233#define B_BE_CSI_ERROR_FLAG_CLR BIT(7)
7234#define B_BE_MIMOCTRL_ERROR_FLAG_CLR BIT(6)
7235#define B_BE_RXTB_ERROR_FLAG_CLR BIT(5)
7236#define B_BE_HWSIGB_GEN_ERROR_FLAG_CLR BIT(4)
7237#define B_BE_TXPLCP_ERROR_FLAG_CLR BIT(3)
7238#define B_BE_RESP_ERROR_FLAG_CLR BIT(2)
7239#define B_BE_TXCTL_ERROR_FLAG_CLR BIT(1)
7240#define B_BE_MACTX_ERROR_FLAG_CLR BIT(0)
7241
7242#define R_BE_DBGSEL_TRXPTCL 0x110F4
7243#define R_BE_DBGSEL_TRXPTCL_C1 0x150F4
7244#define B_BE_WMAC_CHNSTS_STATE_MASK GENMASK(19, 16)
7245#define B_BE_DBGSEL_TRIGCMD_SEL_MASK GENMASK(11, 8)
7246#define B_BE_DBGSEL_TRXPTCL_MASK GENMASK(7, 0)
7247
7248#define R_BE_PHYINFO_ERR_IMR_V1 0x110F8
7249#define R_BE_PHYINFO_ERR_IMR_V1_C1 0x150F8
7250#define B_BE_PHYINTF_RXTB_WIDTH_MASK GENMASK(31, 30)
7251#define B_BE_PHYINTF_RXTB_EN_PHASE_MASK GENMASK(29, 28)
7252#define B_BE_PHYINTF_MIMO_WIDTH_MASK GENMASK(27, 26)
7253#define B_BE_PHYINTF_MIMO_EN_PHASE_MASK GENMASK(25, 24)
7254#define B_BE_PHYINTF_TIMEOUT_THR_V1_MASK GENMASK(21, 16)
7255#define B_BE_CSI_ON_TIMEOUT_EN BIT(5)
7256#define B_BE_STS_ON_TIMEOUT_EN BIT(4)
7257#define B_BE_DATA_ON_TIMEOUT_EN BIT(3)
7258#define B_BE_OFDM_CCA_TIMEOUT_EN BIT(2)
7259#define B_BE_CCK_CCA_TIMEOUT_EN BIT(1)
7260#define B_BE_PHY_TXON_TIMEOUT_EN BIT(0)
7261#define  B_BE_PHYINFO_ERR_IMR_V1_CLR (B_BE_PHY_TXON_TIMEOUT_EN | \
7262				      B_BE_CCK_CCA_TIMEOUT_EN | \
7263				      B_BE_OFDM_CCA_TIMEOUT_EN | \
7264				      B_BE_DATA_ON_TIMEOUT_EN | \
7265				      B_BE_STS_ON_TIMEOUT_EN | \
7266				      B_BE_CSI_ON_TIMEOUT_EN)
7267#define B_BE_PHYINFO_ERR_IMR_V1_SET 0
7268
7269#define R_BE_PHYINFO_ERR_ISR 0x110FC
7270#define R_BE_PHYINFO_ERR_ISR_C1 0x150FC
7271#define B_BE_CSI_ON_TIMEOUT_ERR BIT(5)
7272#define B_BE_STS_ON_TIMEOUT_ERR BIT(4)
7273#define B_BE_DATA_ON_TIMEOUT_ERR BIT(3)
7274#define B_BE_OFDM_CCA_TIMEOUT_ERR BIT(2)
7275#define B_BE_CCK_CCA_TIMEOUT_ERR BIT(1)
7276#define B_BE_PHY_TXON_TIMEOUT_ERR BIT(0)
7277
7278#define R_BE_BFMEE_RESP_OPTION 0x11180
7279#define R_BE_BFMEE_RESP_OPTION_C1 0x15180
7280#define B_BE_BFMEE_CSI_SEC_TYPE_SH 20
7281#define B_BE_BFMEE_CSI_SEC_TYPE_MSK 0xf
7282#define B_BE_BFMEE_BFRPT_SEG_SIZE_SH 16
7283#define B_BE_BFMEE_BFRPT_SEG_SIZE_MSK 0x3
7284#define B_BE_BFMEE_MIMO_EN_SEL BIT(8)
7285#define B_BE_BFMEE_MU_BFEE_DIS BIT(7)
7286#define B_BE_BFMEE_CHECK_RPTPOLL_MACID_DIS BIT(6)
7287#define B_BE_BFMEE_NOCHK_BFPOLL_BMP BIT(5)
7288#define B_BE_BFMEE_VHTBFRPT_CHK BIT(4)
7289#define B_BE_BFMEE_EHT_NDPA_EN BIT(3)
7290#define B_BE_BFMEE_HE_NDPA_EN BIT(2)
7291#define B_BE_BFMEE_VHT_NDPA_EN BIT(1)
7292#define B_BE_BFMEE_HT_NDPA_EN BIT(0)
7293
7294#define R_BE_TRXPTCL_RESP_CSI_CTRL_0 0x11188
7295#define R_BE_TRXPTCL_RESP_CSI_CTRL_0_C1 0x15188
7296#define B_BE_BFMEE_CSISEQ_SEL BIT(29)
7297#define B_BE_BFMEE_BFPARAM_SEL BIT(28)
7298#define B_BE_BFMEE_OFDM_LEN_TH_MASK GENMASK(27, 24)
7299#define B_BE_BFMEE_BF_PORT_SEL BIT(23)
7300#define B_BE_BFMEE_USE_NSTS BIT(22)
7301#define B_BE_BFMEE_CSI_RATE_FB_EN BIT(21)
7302#define B_BE_BFMEE_CSI_GID_SEL BIT(20)
7303#define B_BE_BFMEE_CSI_RSC_MASK GENMASK(19, 18)
7304#define B_BE_BFMEE_CSI_FORCE_RETE_EN BIT(17)
7305#define B_BE_BFMEE_CSI_USE_NDPARATE BIT(16)
7306#define B_BE_BFMEE_CSI_WITHHTC_EN BIT(15)
7307#define B_BE_BFMEE_CSIINFO0_BF_EN BIT(14)
7308#define B_BE_BFMEE_CSIINFO0_STBC_EN BIT(13)
7309#define B_BE_BFMEE_CSIINFO0_LDPC_EN BIT(12)
7310#define B_BE_BFMEE_CSIINFO0_CS_MASK GENMASK(11, 10)
7311#define B_BE_BFMEE_CSIINFO0_CB_MASK GENMASK(9, 8)
7312#define B_BE_BFMEE_CSIINFO0_NG_MASK GENMASK(7, 6)
7313#define B_BE_BFMEE_CSIINFO0_NR_MASK GENMASK(5, 3)
7314#define B_BE_BFMEE_CSIINFO0_NC_MASK GENMASK(2, 0)
7315#define CSI_RX_BW_CFG 0x1
7316#define R_BE_TRXPTCL_RESP_CSI_CTRL_1 0x11194
7317#define R_BE_TRXPTCL_RESP_CSI_CTRL_1_C1 0x15194
7318#define B_BE_BFMEE_BE_CSI_RRSC_BITMAP_MASK GENMASK(31, 24)
7319#define CSI_RRSC_BITMAP_CFG 0x2A
7320
7321#define R_BE_TRXPTCL_RESP_CSI_RRSC 0x1118C
7322#define R_BE_TRXPTCL_RESP_CSI_RRSC_C1 0x1518C
7323#define CSI_RRSC_BMAP_BE 0x2A2AFF
7324
7325#define R_BE_TRXPTCL_RESP_CSI_RATE 0x11190
7326#define R_BE_TRXPTCL_RESP_CSI_RATE_C1 0x15190
7327#define B_BE_BFMEE_EHT_CSI_RATE_MASK GENMASK(31, 24)
7328#define B_BE_BFMEE_HE_CSI_RATE_MASK GENMASK(23, 16)
7329#define B_BE_BFMEE_VHT_CSI_RATE_MASK GENMASK(15, 8)
7330#define B_BE_BFMEE_HT_CSI_RATE_MASK GENMASK(7, 0)
7331#define CSI_INIT_RATE_EHT 0x3
7332
7333#define R_BE_WMAC_ACK_BA_RESP_LEGACY 0x11200
7334#define R_BE_WMAC_ACK_BA_RESP_LEGACY_C1 0x15200
7335#define B_BE_ACK_BA_RESP_LEGACY_CHK_NSTR BIT(16)
7336#define B_BE_ACK_BA_RESP_LEGACY_CHK_TX_NAV BIT(15)
7337#define B_BE_ACK_BA_RESP_LEGACY_CHK_INTRA_NAV BIT(14)
7338#define B_BE_ACK_BA_RESP_LEGACY_CHK_BASIC_NAV BIT(13)
7339#define B_BE_ACK_BA_RESP_LEGACY_CHK_BTCCA BIT(12)
7340#define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_EDCCA160 BIT(11)
7341#define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_EDCCA80 BIT(10)
7342#define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_EDCCA40 BIT(9)
7343#define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_EDCCA20 BIT(8)
7344#define B_BE_ACK_BA_RESP_LEGACY_CHK_EDCCA_PER20_BMP BIT(7)
7345#define B_BE_ACK_BA_RESP_LEGACY_CHK_CCA_PER20_BMP BIT(6)
7346#define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_CCA160 BIT(5)
7347#define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_CCA80 BIT(4)
7348#define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_CCA40 BIT(3)
7349#define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_CCA20 BIT(2)
7350#define B_BE_ACK_BA_RESP_LEGACY_CHK_EDCCA BIT(1)
7351#define B_BE_ACK_BA_RESP_LEGACY_CHK_CCA BIT(0)
7352
7353#define R_BE_WMAC_ACK_BA_RESP_HE 0x11204
7354#define R_BE_WMAC_ACK_BA_RESP_HE_C1 0x15204
7355#define B_BE_ACK_BA_RESP_HE_CHK_NSTR BIT(16)
7356#define B_BE_ACK_BA_RESP_HE_CHK_TX_NAV BIT(15)
7357#define B_BE_ACK_BA_RESP_HE_CHK_INTRA_NAV BIT(14)
7358#define B_BE_ACK_BA_RESP_HE_CHK_BASIC_NAV BIT(13)
7359#define B_BE_ACK_BA_RESP_HE_CHK_BTCCA BIT(12)
7360#define B_BE_ACK_BA_RESP_HE_CHK_SEC_EDCCA160 BIT(11)
7361#define B_BE_ACK_BA_RESP_HE_CHK_SEC_EDCCA80 BIT(10)
7362#define B_BE_ACK_BA_RESP_HE_CHK_SEC_EDCCA40 BIT(9)
7363#define B_BE_ACK_BA_RESP_HE_CHK_SEC_EDCCA20 BIT(8)
7364#define B_BE_ACK_BA_RESP_HE_CHK_EDCCA_PER20_BMP BIT(7)
7365#define B_BE_ACK_BA_RESP_HE_CHK_CCA_PER20_BMP BIT(6)
7366#define B_BE_ACK_BA_RESP_HE_CHK_SEC_CCA160 BIT(5)
7367#define B_BE_ACK_BA_RESP_HE_CHK_SEC_CCA80 BIT(4)
7368#define B_BE_ACK_BA_RESP_HE_CHK_SEC_CCA40 BIT(3)
7369#define B_BE_ACK_BA_RESP_HE_CHK_SEC_CCA20 BIT(2)
7370#define B_BE_ACK_BA_RESP_HE_CHK_EDCCA BIT(1)
7371#define B_BE_ACK_BA_RESP_HE_CHK_CCA BIT(0)
7372
7373#define R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC 0x11208
7374#define R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC_C1 0x15208
7375#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_NSTR BIT(16)
7376#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_TX_NAV BIT(15)
7377#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_INTRA_NAV BIT(14)
7378#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_BASIC_NAV BIT(13)
7379#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_BTCCA BIT(12)
7380#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_EDCCA160 BIT(11)
7381#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_EDCCA80 BIT(10)
7382#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_EDCCA40 BIT(9)
7383#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_EDCCA20 BIT(8)
7384#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_EDCCA_PER20_BMP BIT(7)
7385#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_CCA_PER20_BMP BIT(6)
7386#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_CCA160 BIT(5)
7387#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_CCA80 BIT(4)
7388#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_CCA40 BIT(3)
7389#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_CCA20 BIT(2)
7390#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_EDCCA BIT(1)
7391#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_CCA BIT(0)
7392
7393#define R_BE_RCR 0x11400
7394#define R_BE_RCR_C1 0x15400
7395#define B_BE_BUSY_CHKSN BIT(15)
7396#define B_BE_DYN_CHEN BIT(14)
7397#define B_BE_AUTO_RST BIT(13)
7398#define B_BE_TIMER_SEL BIT(12)
7399#define B_BE_STOP_RX_IN BIT(11)
7400#define B_BE_PSR_RDY_CHKDIS BIT(10)
7401#define B_BE_DRV_INFO_SZ_MASK GENMASK(9, 8)
7402#define B_BE_HDR_CNV_SZ_MASK GENMASK(7, 6)
7403#define B_BE_PHY_RPT_SZ_MASK GENMASK(5, 4)
7404#define B_BE_CH_EN BIT(0)
7405
7406#define R_BE_DLK_PROTECT_CTL 0x11402
7407#define R_BE_DLK_PROTECT_CTL_C1 0x15402
7408#define B_BE_RX_DLK_CCA_TIME_MASK GENMASK(15, 8)
7409#define TRXCFG_RMAC_CCA_TO 32
7410#define B_BE_RX_DLK_DATA_TIME_MASK GENMASK(7, 4)
7411#define TRXCFG_RMAC_DATA_TO 15
7412#define B_BE_RX_DLK_RST_FSM BIT(3)
7413#define B_BE_RX_DLK_RST_SKIPDMA BIT(2)
7414#define B_BE_RX_DLK_RST_EN BIT(1)
7415#define B_BE_RX_DLK_INT_EN BIT(0)
7416
7417#define R_BE_PLCP_HDR_FLTR 0x11404
7418#define R_BE_PLCP_HDR_FLTR_C1 0x15404
7419#define B_BE_PLCP_RXFA_RESET_TYPE_MASK GENMASK(15, 12)
7420#define B_BE_PLCP_RXFA_RESET_EN BIT(11)
7421#define B_BE_DIS_CHK_MIN_LEN BIT(8)
7422#define B_BE_HE_SIGB_CRC_CHK BIT(6)
7423#define B_BE_VHT_MU_SIGB_CRC_CHK BIT(5)
7424#define B_BE_VHT_SU_SIGB_CRC_CHK BIT(4)
7425#define B_BE_SIGA_CRC_CHK BIT(3)
7426#define B_BE_LSIG_PARITY_CHK_EN BIT(2)
7427#define B_BE_CCK_SIG_CHK BIT(1)
7428#define B_BE_CCK_CRC_CHK BIT(0)
7429
7430#define R_BE_RX_FLTR_OPT 0x11420
7431#define R_BE_RX_FLTR_OPT_C1 0x15420
7432#define B_BE_UID_FILTER_MASK GENMASK(31, 24)
7433#define B_BE_UNSPT_TYPE BIT(22)
7434#define B_BE_RX_MPDU_MAX_LEN_MASK GENMASK(21, 16)
7435#define B_BE_A_FTM_REQ BIT(14)
7436#define B_BE_A_ERR_PKT BIT(13)
7437#define B_BE_A_UNSUP_PKT BIT(12)
7438#define B_BE_A_CRC32_ERR BIT(11)
7439#define B_BE_A_BCN_CHK_RULE_MASK GENMASK(9, 8)
7440#define B_BE_A_BCN_CHK_EN BIT(7)
7441#define B_BE_A_MC_LIST_CAM_MATCH BIT(6)
7442#define B_BE_A_BC_CAM_MATCH BIT(5)
7443#define B_BE_A_UC_CAM_MATCH BIT(4)
7444#define B_BE_A_MC BIT(3)
7445#define B_BE_A_BC BIT(2)
7446#define B_BE_A_A1_MATCH BIT(1)
7447#define B_BE_SNIFFER_MODE BIT(0)
7448
7449#define R_BE_CTRL_FLTR 0x11424
7450#define R_BE_CTRL_FLTR_C1 0x15424
7451#define B_BE_CTRL_STYPE_MASK GENMASK(15, 0)
7452#define RX_FLTR_FRAME_DROP_BE 0x0000
7453#define RX_FLTR_FRAME_ACCEPT_BE 0xFFFF
7454
7455#define R_BE_MGNT_FLTR 0x11428
7456#define R_BE_MGNT_FLTR_C1 0x15428
7457#define B_BE_MGNT_STYPE_MASK GENMASK(15, 0)
7458
7459#define R_BE_DATA_FLTR 0x1142C
7460#define R_BE_DATA_FLTR_C1 0x1542C
7461#define B_BE_DATA_STYPE_MASK GENMASK(15, 0)
7462
7463#define R_BE_ADDR_CAM_CTRL 0x11434
7464#define R_BE_ADDR_CAM_CTRL_C1 0x15434
7465#define B_BE_ADDR_CAM_RANGE_MASK GENMASK(23, 16)
7466#define ADDR_CAM_SERCH_RANGE  0x7f
7467#define B_BE_ADDR_CAM_CMPLIMT_MASK GENMASK(15, 12)
7468#define B_BE_ADDR_CAM_IORST BIT(10)
7469#define B_BE_DIS_ADDR_CLK_GATED BIT(9)
7470#define B_BE_ADDR_CAM_CLR BIT(8)
7471#define B_BE_ADDR_CAM_A2_B0_CHK BIT(2)
7472#define B_BE_ADDR_CAM_SRCH_PERPKT BIT(1)
7473#define B_BE_ADDR_CAM_EN BIT(0)
7474
7475#define R_BE_RESPBA_CAM_CTRL 0x1143C
7476#define R_BE_RESPBA_CAM_CTRL_C1 0x1543C
7477#define B_BE_BACAM_SKIP_ALL_QOSNULL BIT(24)
7478#define B_BE_BACAM_STD_SSN_SEL BIT(20)
7479#define B_BE_BACAM_TEMP_SZ_MASK GENMASK(17, 16)
7480#define B_BE_BACAM_RST_IDX_MASK GENMASK(15, 8)
7481#define B_BE_BACAM_SHIFT_POLL BIT(7)
7482#define B_BE_BACAM_IORST BIT(6)
7483#define B_BE_BACAM_GCK_DIS BIT(5)
7484#define B_BE_COMPL_VAL BIT(3)
7485#define B_BE_SSN_SEL BIT(2)
7486#define B_BE_BACAM_RST_MASK GENMASK(1, 0)
7487#define S_BE_BACAM_RST_DONE 0
7488#define S_BE_BACAM_RST_ENT 1
7489#define S_BE_BACAM_RST_ALL 2
7490
7491#define R_BE_PPDU_STAT 0x11440
7492#define R_BE_PPDU_STAT_C1 0x15440
7493#define B_BE_STAT_IORST BIT(13)
7494#define B_BE_STAT_GCKDIS BIT(12)
7495#define B_BE_PPDU_STAT_WR_BW_MASK GENMASK(11, 10)
7496#define B_BE_PPDU_STAT_RPT_TRIG BIT(8)
7497#define B_BE_PPDU_STAT_RPT_DMA BIT(6)
7498#define B_BE_PPDU_STAT_RPT_CRC32 BIT(5)
7499#define B_BE_PPDU_STAT_RPT_ADDR BIT(4)
7500#define B_BE_APP_PLCP_HDR_RPT BIT(3)
7501#define B_BE_APP_RX_CNT_RPT BIT(2)
7502#define B_BE_PPDU_STAT_RPT_EN BIT(0)
7503
7504#define R_BE_RX_SR_CTRL 0x1144A
7505#define R_BE_RX_SR_CTRL_C1 0x1544A
7506#define B_BE_SR_OP_MODE_MASK GENMASK(5, 4)
7507#define B_BE_SRG_CHK_EN BIT(2)
7508#define B_BE_SR_CTRL_PLCP_EN BIT(1)
7509#define B_BE_SR_EN BIT(0)
7510
7511#define R_BE_BSSID_SRC_CTRL 0x1144B
7512#define R_BE_BSSID_SRC_CTRL_C1 0x1544B
7513#define B_BE_BSSID_MATCH BIT(3)
7514#define B_BE_PARTIAL_AID_MATCH BIT(2)
7515#define B_BE_BSSCOLOR_MATCH BIT(1)
7516#define B_BE_PLCP_SRC_EN BIT(0)
7517
7518#define R_BE_CSIRPT_OPTION 0x11464
7519#define R_BE_CSIRPT_OPTION_C1 0x15464
7520#define B_BE_CSIPRT_EHTSU_AID_EN BIT(26)
7521#define B_BE_CSIPRT_HESU_AID_EN BIT(25)
7522#define B_BE_CSIPRT_VHTSU_AID_EN BIT(24)
7523
7524#define R_BE_DRV_INFO_OPTION 0x11470
7525#define R_BE_DRV_INFO_OPTION_C1 0x15470
7526#define B_BE_DRV_INFO_PHYRPT_EN BIT(0)
7527
7528#define R_BE_BCN_PSR_RPT_P0 0x11484
7529#define R_BE_BCN_PSR_RPT_P0_C1 0x15484
7530#define B_BE_BCAID_P0_MASK GENMASK(10, 0)
7531
7532#define R_BE_RX_ERR_ISR 0x114F4
7533#define R_BE_RX_ERR_ISR_C1 0x154F4
7534#define B_BE_RX_ERR_TRIG_ACT_TO BIT(9)
7535#define B_BE_RX_ERR_STS_ACT_TO BIT(8)
7536#define B_BE_RX_ERR_CSI_ACT_TO BIT(7)
7537#define B_BE_RX_ERR_ACT_TO BIT(6)
7538#define B_BE_CSI_DATAON_ASSERT_TO BIT(5)
7539#define B_BE_DATAON_ASSERT_TO BIT(4)
7540#define B_BE_CCA_ASSERT_TO BIT(3)
7541#define B_BE_RX_ERR_DMA_TO BIT(2)
7542#define B_BE_RX_ERR_DATA_TO BIT(1)
7543#define B_BE_RX_ERR_CCA_TO BIT(0)
7544
7545#define R_BE_RX_ERR_IMR 0x114F8
7546#define R_BE_RX_ERR_IMR_C1 0x154F8
7547#define B_BE_RX_ERR_TRIG_ACT_TO_MSK BIT(9)
7548#define B_BE_RX_ERR_STS_ACT_TO_MSK BIT(8)
7549#define B_BE_RX_ERR_CSI_ACT_TO_MSK BIT(7)
7550#define B_BE_RX_ERR_ACT_TO_MSK BIT(6)
7551#define B_BE_CSI_DATAON_ASSERT_TO_MSK BIT(5)
7552#define B_BE_DATAON_ASSERT_TO_MSK BIT(4)
7553#define B_BE_CCA_ASSERT_TO_MSK BIT(3)
7554#define B_BE_RX_ERR_DMA_TO_MSK BIT(2)
7555#define B_BE_RX_ERR_DATA_TO_MSK BIT(1)
7556#define B_BE_RX_ERR_CCA_TO_MSK BIT(0)
7557#define B_BE_RX_ERR_IMR_CLR (B_BE_RX_ERR_CCA_TO_MSK | \
7558			     B_BE_RX_ERR_DATA_TO_MSK | \
7559			     B_BE_RX_ERR_DMA_TO_MSK | \
7560			     B_BE_CCA_ASSERT_TO_MSK | \
7561			     B_BE_DATAON_ASSERT_TO_MSK | \
7562			     B_BE_CSI_DATAON_ASSERT_TO_MSK | \
7563			     B_BE_RX_ERR_ACT_TO_MSK | \
7564			     B_BE_RX_ERR_CSI_ACT_TO_MSK | \
7565			     B_BE_RX_ERR_STS_ACT_TO_MSK | \
7566			     B_BE_RX_ERR_TRIG_ACT_TO_MSK)
7567#define B_BE_RX_ERR_IMR_SET (B_BE_RX_ERR_ACT_TO_MSK | \
7568			     B_BE_RX_ERR_STS_ACT_TO_MSK | \
7569			     B_BE_RX_ERR_TRIG_ACT_TO_MSK)
7570
7571#define R_BE_RX_PLCP_EXT_OPTION_1 0x11514
7572#define R_BE_RX_PLCP_EXT_OPTION_1_C1 0x15514
7573#define B_BE_PLCP_CLOSE_RX_UNSPUUORT BIT(19)
7574#define B_BE_PLCP_CLOSE_RX_BB_BRK BIT(18)
7575#define B_BE_PLCP_CLOSE_RX_PSDU_PRES BIT(17)
7576#define B_BE_PLCP_CLOSE_RX_NDP BIT(16)
7577#define B_BE_PLCP_NSS_SRC BIT(11)
7578#define B_BE_PLCP_DOPPLEB_BE_SRC BIT(10)
7579#define B_BE_PLCP_STBC_SRC BIT(9)
7580#define B_BE_PLCP_SU_PSDU_LEN_SRC BIT(8)
7581#define B_BE_PLCP_RXSB_SRC BIT(7)
7582#define B_BE_PLCP_BW_SRC_MASK GENMASK(6, 5)
7583#define B_BE_PLCP_GILTF_SRC BIT(4)
7584#define B_BE_PLCP_NSTS_SRC BIT(3)
7585#define B_BE_PLCP_MCS_SRC BIT(2)
7586#define B_BE_PLCP_CH20_WIDATA_SRC BIT(1)
7587#define B_BE_PLCP_PPDU_TYPE_SRC BIT(0)
7588
7589#define R_BE_RESP_CSI_RESERVED_PAGE 0x11810
7590#define R_BE_RESP_CSI_RESERVED_PAGE_C1 0x15810
7591#define B_BE_CSI_RESERVED_PAGE_NUM_MASK GENMASK(27, 16)
7592#define B_BE_CSI_RESERVED_START_PAGE_MASK GENMASK(11, 0)
7593
7594#define R_BE_RESP_IMR 0x11884
7595#define R_BE_RESP_IMR_C1 0x15884
7596#define B_BE_RESP_TBL_FLAG_ERR_ISR_EN BIT(17)
7597#define B_BE_RESP_SEC_DOUBLE_HIT_ERR_ISR_EN BIT(16)
7598#define B_BE_RESP_WRPTR_CROSS_ERR_ISR_EN BIT(15)
7599#define B_BE_RESP_TOO_MANY_PLD_ERR_ISR_EN BIT(14)
7600#define B_BE_RESP_TXDMA_READ_DATA_ERR_ISR_EN BIT(13)
7601#define B_BE_RESP_PLDID_RDY_ERR_ISR_EN BIT(12)
7602#define B_BE_RESP_RX_OVERWRITE_ERR_ISR_EN BIT(11)
7603#define B_BE_RESP_RXDMA_WRPTR_INVLD_ERR_ISR_EN BIT(10)
7604#define B_BE_RESP_RXDMA_REQ_INVLD_ERR_ISR_EN BIT(9)
7605#define B_BE_RESP_RXDMA_REQ_MACID_ERR_ISR_EN BIT(8)
7606#define B_BE_RESP_TXCMD_TX_ST_ABORT_ERR_ISR_EN BIT(6)
7607#define B_BE_RESP_TXCMD_DMAC_PROC_ERR_ISR_EN BIT(5)
7608#define B_BE_RESP_TXCMD_TBL_ERR_ISR_EN BIT(4)
7609#define B_BE_RESP_INITCMD_RX_ST_ABORT_ERR_ISR_EN BIT(3)
7610#define B_BE_RESP_INITCMD_RESERVD_PAGE_ABORT_ERR_ISR_EN BIT(2)
7611#define B_BE_RESP_INITCMD_TX_ST_ABORT_ERR_ISR_EN BIT(1)
7612#define B_BE_RESP_DMAC_PROC_ERR_ISR_EN BIT(0)
7613#define B_BE_RESP_IMR_CLR (B_BE_RESP_DMAC_PROC_ERR_ISR_EN | \
7614			   B_BE_RESP_INITCMD_TX_ST_ABORT_ERR_ISR_EN | \
7615			   B_BE_RESP_INITCMD_RX_ST_ABORT_ERR_ISR_EN | \
7616			   B_BE_RESP_TXCMD_TBL_ERR_ISR_EN | \
7617			   B_BE_RESP_TXCMD_DMAC_PROC_ERR_ISR_EN | \
7618			   B_BE_RESP_TXCMD_TX_ST_ABORT_ERR_ISR_EN | \
7619			   B_BE_RESP_RXDMA_REQ_MACID_ERR_ISR_EN | \
7620			   B_BE_RESP_RXDMA_REQ_INVLD_ERR_ISR_EN | \
7621			   B_BE_RESP_RXDMA_WRPTR_INVLD_ERR_ISR_EN | \
7622			   B_BE_RESP_RX_OVERWRITE_ERR_ISR_EN | \
7623			   B_BE_RESP_PLDID_RDY_ERR_ISR_EN | \
7624			   B_BE_RESP_TXDMA_READ_DATA_ERR_ISR_EN | \
7625			   B_BE_RESP_TOO_MANY_PLD_ERR_ISR_EN | \
7626			   B_BE_RESP_WRPTR_CROSS_ERR_ISR_EN | \
7627			   B_BE_RESP_SEC_DOUBLE_HIT_ERR_ISR_EN)
7628#define B_BE_RESP_IMR_SET (B_BE_RESP_DMAC_PROC_ERR_ISR_EN | \
7629			   B_BE_RESP_INITCMD_TX_ST_ABORT_ERR_ISR_EN | \
7630			   B_BE_RESP_INITCMD_RX_ST_ABORT_ERR_ISR_EN | \
7631			   B_BE_RESP_TXCMD_TBL_ERR_ISR_EN | \
7632			   B_BE_RESP_TXCMD_DMAC_PROC_ERR_ISR_EN | \
7633			   B_BE_RESP_TXCMD_TX_ST_ABORT_ERR_ISR_EN | \
7634			   B_BE_RESP_RX_OVERWRITE_ERR_ISR_EN | \
7635			   B_BE_RESP_PLDID_RDY_ERR_ISR_EN | \
7636			   B_BE_RESP_WRPTR_CROSS_ERR_ISR_EN | \
7637			   B_BE_RESP_SEC_DOUBLE_HIT_ERR_ISR_EN)
7638
7639#define R_BE_PWR_MODULE 0x11900
7640#define R_BE_PWR_MODULE_C1 0x15900
7641#define R_BE_PWR_LISTEN_PATH 0x11988
7642#define B_BE_PWR_LISTEN_PATH_EN GENMASK(31, 28)
7643
7644#define R_BE_PWR_REF_CTRL 0x11A20
7645#define B_BE_PWR_REF_CTRL_OFDM GENMASK(9, 1)
7646#define B_BE_PWR_REF_CTRL_CCK GENMASK(18, 10)
7647#define B_BE_PWR_OFST_LMT_DB GENMASK(27, 19)
7648#define R_BE_PWR_OFST_LMTBF 0x11A24
7649#define B_BE_PWR_OFST_LMTBF_DB GENMASK(8, 0)
7650#define R_BE_PWR_FORCE_LMT 0x11A28
7651#define B_BE_PWR_FORCE_LMT_ON BIT(6)
7652
7653#define R_BE_PWR_RATE_CTRL 0x11A2C
7654#define B_BE_PWR_OFST_BYRATE_DB GENMASK(8, 0)
7655#define B_BE_FORCE_PWR_BY_RATE_EN BIT(19)
7656#define B_BE_FORCE_PWR_BY_RATE_VAL GENMASK(28, 20)
7657
7658#define R_BE_PWR_RATE_OFST_CTRL 0x11A30
7659#define R_BE_PWR_RATE_OFST_END 0x11A38
7660#define R_BE_PWR_RULMT_START 0x12048
7661#define R_BE_PWR_RULMT_END 0x120e4
7662
7663#define R_BE_PWR_BOOST 0x11A40
7664#define B_BE_PWR_CTRL_SEL BIT(16)
7665#define B_BE_PWR_FORCE_RATE_ON BIT(29)
7666#define R_BE_PWR_OFST_RULMT 0x11A44
7667#define B_BE_PWR_OFST_RULMT_DB GENMASK(17, 9)
7668#define B_BE_PWR_FORCE_RU_ON BIT(18)
7669#define B_BE_PWR_FORCE_RU_ENON BIT(28)
7670#define R_BE_PWR_FORCE_MACID 0x11A48
7671#define B_BE_PWR_FORCE_MACID_DBM_ON BIT(9)
7672#define B_BE_PWR_FORCE_MACID_DBM_VAL GENMASK(17, 10)
7673#define B_BE_PWR_FORCE_MACID_EN_VAL BIT(18)
7674#define B_BE_PWR_FORCE_MACID_EN_ON BIT(19)
7675#define B_BE_PWR_FORCE_MACID_ALL \
7676	(B_BE_PWR_FORCE_MACID_DBM_ON | \
7677	 B_BE_PWR_FORCE_MACID_DBM_VAL | \
7678	 B_BE_PWR_FORCE_MACID_EN_VAL | \
7679	 B_BE_PWR_FORCE_MACID_EN_ON)
7680
7681#define R_BE_PWR_REG_CTRL 0x11A50
7682#define B_BE_PWR_BT_EN BIT(23)
7683
7684#define R_BE_PWR_COEX_CTRL 0x11A54
7685#define B_BE_PWR_BT_VAL GENMASK(8, 0)
7686#define B_BE_PWR_FORCE_COEX_ON GENMASK(29, 27)
7687
7688#define R_BE_PWR_TH 0x11A78
7689#define R_BE_PWR_RSSI_TARGET_LMT 0x11A84
7690
7691#define R_BE_PWR_OFST_SW 0x11AE8
7692#define B_BE_PWR_OFST_SW_DB GENMASK(27, 24)
7693
7694#define R_BE_PWR_FTM 0x11B00
7695#define R_BE_PWR_FTM_SS 0x11B04
7696
7697#define R_BE_PWR_BY_RATE 0x11E00
7698#define R_BE_PWR_BY_RATE_MAX 0x11FA8
7699#define R_BE_PWR_LMT 0x11FAC
7700#define R_BE_PWR_LMT_MAX 0x12040
7701#define R_BE_PWR_BY_RATE_END 0x12044
7702#define R_BE_PWR_RU_LMT 0x12048
7703#define R_BE_PWR_RU_LMT_MAX 0x120E4
7704
7705#define R_BE_C0_TXPWR_IMR 0x128E0
7706#define R_BE_C0_TXPWR_IMR_C1 0x168E0
7707#define B_BE_FSM_TIMEOUT_ERR_INT_EN BIT(0)
7708#define B_BE_C0_TXPWR_IMR_CLR B_BE_FSM_TIMEOUT_ERR_INT_EN
7709#define B_BE_C0_TXPWR_IMR_SET B_BE_FSM_TIMEOUT_ERR_INT_EN
7710
7711#define R_BE_TXPWR_ERR_FLAG 0x128E4
7712#define R_BE_TXPWR_ERR_IMR 0x128E0
7713#define R_BE_TXPWR_ERR_FLAG_C1 0x158E4
7714#define R_BE_TXPWR_ERR_IMR_C1 0x158E0
7715
7716#define CMAC1_START_ADDR_BE 0x14000
7717#define CMAC1_END_ADDR_BE 0x17FFF
7718
7719#define RR_MOD 0x00
7720#define RR_MOD_V1 0x10000
7721#define RR_MOD_IQK GENMASK(19, 4)
7722#define RR_MOD_DPK GENMASK(19, 5)
7723#define RR_MOD_MASK GENMASK(19, 16)
7724#define RR_MOD_DCK GENMASK(14, 10)
7725#define RR_MOD_RGM GENMASK(13, 4)
7726#define RR_MOD_RXB GENMASK(9, 5)
7727#define RR_MOD_V_DOWN 0x0
7728#define RR_MOD_V_STANDBY 0x1
7729#define RR_TXAGC 0x10001
7730#define RR_MOD_V_TX 0x2
7731#define RR_MOD_V_RX 0x3
7732#define RR_MOD_V_TXIQK 0x4
7733#define RR_MOD_V_DPK 0x5
7734#define RR_MOD_V_RXK1 0x6
7735#define RR_MOD_V_RXK2 0x7
7736#define RR_MOD_NBW GENMASK(15, 14)
7737#define RR_MOD_M_RXG GENMASK(13, 4)
7738#define RR_MOD_M_RXBB GENMASK(9, 5)
7739#define RR_MOD_LO_SEL BIT(1)
7740#define RR_MODOPT 0x01
7741#define RR_TXG_SEL GENMASK(19, 17)
7742#define RR_MODOPT_M_TXPWR GENMASK(5, 0)
7743#define RR_WLSEL 0x02
7744#define RR_WLSEL_AG GENMASK(18, 16)
7745#define RR_RSV1 0x05
7746#define RR_RSV1_RST BIT(0)
7747#define RR_BBDC 0x10005
7748#define RR_BBDC_SEL BIT(0)
7749#define RR_DTXLOK 0x08
7750#define RR_RSV2 0x09
7751#define RR_LOKVB 0x0a
7752#define RR_LOKVB_COI GENMASK(19, 14)
7753#define RR_LOKVB_COQ GENMASK(9, 4)
7754#define RR_TXIG 0x11
7755#define RR_TXIG_TG GENMASK(16, 12)
7756#define RR_TXIG_GR1 GENMASK(6, 4)
7757#define RR_TXIG_GR0 GENMASK(1, 0)
7758#define RR_CHTR 0x17
7759#define RR_CHTR_MOD GENMASK(11, 10)
7760#define RR_CHTR_TXRX GENMASK(9, 0)
7761#define RR_CFGCH 0x18
7762#define RR_CFGCH_V1 0x10018
7763#define RR_CFGCH_BAND1 GENMASK(17, 16)
7764#define CFGCH_BAND1_2G 0
7765#define CFGCH_BAND1_5G 1
7766#define CFGCH_BAND1_6G 3
7767#define RR_CFGCH_POW_LCK BIT(15)
7768#define RR_CFGCH_TRX_AH BIT(14)
7769#define RR_CFGCH_BCN BIT(13)
7770#define RR_CFGCH_BW2 BIT(12)
7771#define RR_CFGCH_BAND0 GENMASK(9, 8)
7772#define CFGCH_BAND0_2G 0
7773#define CFGCH_BAND0_5G 1
7774#define CFGCH_BAND0_6G 0
7775#define RR_CFGCH_BW_V2 GENMASK(12, 10)
7776#define CFGCH_BW_V2_20M 0
7777#define CFGCH_BW_V2_40M 1
7778#define CFGCH_BW_V2_80M 2
7779#define CFGCH_BW_V2_160M 3
7780#define CFGCH_BW_V2_320M 4
7781#define RR_CFGCH_BW GENMASK(11, 10)
7782#define RR_CFGCH_CH GENMASK(7, 0)
7783#define CFGCH_BW_20M 3
7784#define CFGCH_BW_40M 2
7785#define CFGCH_BW_80M 1
7786#define CFGCH_BW_160M 0
7787#define RR_APK 0x19
7788#define RR_APK_MOD GENMASK(5, 4)
7789#define RR_BTC 0x1a
7790#define RR_BTC_TXBB GENMASK(14, 12)
7791#define RR_BTC_RXBB GENMASK(11, 10)
7792#define RR_RCKC 0x1b
7793#define RR_RCKC_CA GENMASK(14, 10)
7794#define RR_RCKS 0x1c
7795#define RR_RCKO 0x1d
7796#define RR_RCKO_OFF GENMASK(13, 9)
7797#define RR_RXKPLL 0x1e
7798#define RR_RXKPLL_OFF GENMASK(5, 0)
7799#define RR_RXKPLL_POW BIT(19)
7800#define RR_RSV4 0x1f
7801#define RR_RSV4_AGH GENMASK(17, 16)
7802#define RR_RSV4_PLLCH GENMASK(9, 0)
7803#define RR_RXK 0x20
7804#define RR_RXK_SEL2G BIT(8)
7805#define RR_RXK_SEL5G BIT(7)
7806#define RR_RXK_PLLEN BIT(5)
7807#define RR_LUTWA 0x33
7808#define RR_LUTWA_MASK GENMASK(9, 0)
7809#define RR_LUTWA_M1 GENMASK(7, 0)
7810#define RR_LUTWA_M2 GENMASK(4, 0)
7811#define RR_LUTWD1 0x3e
7812#define RR_LUTWD0 0x3f
7813#define RR_LUTWD0_MB GENMASK(11, 6)
7814#define RR_LUTWD0_LB GENMASK(5, 0)
7815#define RR_TM 0x42
7816#define RR_TM_TRI BIT(19)
7817#define RR_TM_VAL_V1 GENMASK(7, 0)
7818#define RR_TM_VAL GENMASK(6, 1)
7819#define RR_TM2 0x43
7820#define RR_TM2_OFF GENMASK(19, 16)
7821#define RR_TXG1 0x51
7822#define RR_TXG1_ATT2 BIT(19)
7823#define RR_TXG1_ATT1 BIT(11)
7824#define RR_TXG2 0x52
7825#define RR_TXG2_ATT0 BIT(11)
7826#define RR_BSPAD 0x54
7827#define RR_TXGA 0x55
7828#define RR_TXGA_TRK_EN BIT(7)
7829#define RR_TXGA_LOK_EXT GENMASK(4, 0)
7830#define RR_TXGA_LOK_EN BIT(0)
7831#define RR_TXGA_V1 0x10055
7832#define RR_TXGA_V1_TRK_EN BIT(7)
7833#define RR_GAINTX 0x56
7834#define RR_GAINTX_ALL GENMASK(15, 0)
7835#define RR_GAINTX_PAD GENMASK(9, 5)
7836#define RR_GAINTX_BB GENMASK(4, 0)
7837#define RR_TXMO 0x58
7838#define RR_TXMO_COI GENMASK(19, 15)
7839#define RR_TXMO_COQ GENMASK(14, 10)
7840#define RR_TXMO_FII GENMASK(9, 6)
7841#define RR_TXMO_FIQ GENMASK(5, 2)
7842#define RR_TXA 0x5d
7843#define RR_TXA_TRK GENMASK(19, 14)
7844#define RR_TXRSV 0x5c
7845#define RR_TXRSV_GAPK BIT(19)
7846#define RR_BIAS 0x5e
7847#define RR_BIAS_GAPK BIT(19)
7848#define RR_TXAC 0x5f
7849#define RR_TXAC_IQG GENMASK(3, 0)
7850#define RR_BIASA 0x60
7851#define RR_BIASA_TXA GENMASK(19, 16)
7852#define RR_BIASA_TXG GENMASK(15, 12)
7853#define RR_BIASD_TXA_V1 GENMASK(15, 12)
7854#define RR_BIASA_TXA_V1 GENMASK(11, 8)
7855#define RR_BIASD_TXG_V1 GENMASK(7, 4)
7856#define RR_BIASA_TXG_V1 GENMASK(3, 0)
7857#define RR_BIASA_A GENMASK(2, 0)
7858#define RR_BIASA2 0x63
7859#define RR_BIASA2_LB GENMASK(4, 2)
7860#define RR_TXATANK 0x64
7861#define RR_TXATANK_LBSW2 GENMASK(17, 15)
7862#define RR_TXATANK_LBSW GENMASK(16, 15)
7863#define RR_TXA2 0x65
7864#define RR_TXA2_LDO GENMASK(19, 16)
7865#define RR_TRXIQ 0x66
7866#define RR_RSV6 0x6d
7867#define RR_TXVBUF 0x7c
7868#define RR_TXVBUF_DACEN BIT(5)
7869#define RR_TXPOW 0x7f
7870#define RR_TXPOW_TXA BIT(8)
7871#define RR_TXPOW_TXAS BIT(7)
7872#define RR_TXPOW_TXG BIT(1)
7873#define RR_RXPOW 0x80
7874#define RR_RXPOW_IQK GENMASK(17, 16)
7875#define RR_RXBB 0x83
7876#define RR_RXBB_VOBUF GENMASK(15, 12)
7877#define RR_RXBB_C2G GENMASK(16, 10)
7878#define RR_RXBB_C2 GENMASK(11, 8)
7879#define RR_RXBB_C1G GENMASK(9, 8)
7880#define RR_RXBB_FATT GENMASK(7, 0)
7881#define RR_RXBB_ATTR GENMASK(7, 4)
7882#define RR_RXBB_ATTC GENMASK(2, 0)
7883#define RR_RXG 0x84
7884#define RR_RXG_IQKMOD GENMASK(19, 16)
7885#define RR_XGLNA2 0x85
7886#define RR_XGLNA2_SW GENMASK(1, 0)
7887#define RR_RXAE 0x89
7888#define RR_RXAE_IQKMOD GENMASK(3, 0)
7889#define RR_RXA 0x8a
7890#define RR_RXA_DPK GENMASK(9, 8)
7891#define RR_RXA_LNA 0x8b
7892#define RR_RXA2 0x8c
7893#define RR_RAA2_SATT GENMASK(15, 13)
7894#define RR_RAA2_SWATT GENMASK(15, 9)
7895#define RR_RXA2_C1 GENMASK(12, 10)
7896#define RR_RXA2_C2 GENMASK(9, 3)
7897#define RR_RXA2_CC2 GENMASK(8, 7)
7898#define RR_RXA2_IATT GENMASK(7, 4)
7899#define RR_RXA2_HATT GENMASK(6, 0)
7900#define RR_RXA2_ATT GENMASK(3, 0)
7901#define RR_RXIQGEN 0x8d
7902#define RR_RXIQGEN_ATTL GENMASK(12, 8)
7903#define RR_RXIQGEN_ATTH GENMASK(14, 13)
7904#define RR_RXBB2 0x8f
7905#define RR_RXBB2_DAC_EN BIT(13)
7906#define RR_RXBB2_CKT BIT(12)
7907#define RR_EN_TIA_IDA GENMASK(11, 10)
7908#define RR_RXBB2_IDAC GENMASK(11, 9)
7909#define RR_RXBB2_EBW GENMASK(6, 5)
7910#define RR_XALNA2 0x90
7911#define RR_XALNA2_SW2 GENMASK(9, 8)
7912#define RR_XALNA2_SW GENMASK(1, 0)
7913#define RR_DCK 0x92
7914#define RR_DCK_S1 GENMASK(19, 16)
7915#define RR_DCK_TIA GENMASK(15, 9)
7916#define RR_DCK_DONE GENMASK(7, 5)
7917#define RR_DCK_FINE BIT(1)
7918#define RR_DCK_LV BIT(0)
7919#define RR_DCK1 0x93
7920#define RR_DCK1_S1 GENMASK(19, 16)
7921#define RR_DCK1_TIA GENMASK(15, 9)
7922#define RR_DCK1_DONE BIT(5)
7923#define RR_DCK1_CLR GENMASK(3, 0)
7924#define RR_DCK1_SEL BIT(3)
7925#define RR_DCK2 0x94
7926#define RR_DCK2_CYCLE GENMASK(7, 2)
7927#define RR_DCKC 0x95
7928#define RR_DCKC_CHK BIT(3)
7929#define RR_IQGEN 0x97
7930#define RR_IQGEN_BIAS GENMASK(11, 8)
7931#define RR_TXIQK 0x98
7932#define RR_TXIQK_ATT2 GENMASK(15, 12)
7933#define RR_TXIQK_ATT1 GENMASK(6, 0)
7934#define RR_TIA 0x9e
7935#define RR_TIA_N6 BIT(8)
7936#define RR_MIXER 0x9f
7937#define RR_MIXER_GN GENMASK(4, 3)
7938#define RR_POW 0xa0
7939#define RR_POW_SYN GENMASK(3, 2)
7940#define RR_POW_SYN_V1 GENMASK(3, 0)
7941#define RR_LOGEN 0xa3
7942#define RR_LOGEN_RPT GENMASK(19, 16)
7943#define RR_SX 0xaf
7944#define RR_IBD 0xc9
7945#define RR_IBD_VAL GENMASK(4, 0)
7946#define RR_LDO 0xb1
7947#define RR_LDO_SEL GENMASK(8, 6)
7948#define RR_VCO 0xb2
7949#define RR_VCO_SEL GENMASK(9, 8)
7950#define RR_VCI 0xb3
7951#define RR_VCI_ON BIT(7)
7952#define RR_LPF 0xb7
7953#define RR_LPF_BUSY BIT(8)
7954#define RR_XTALX2 0xb8
7955#define RR_MALSEL 0xbe
7956#define RR_SYNFB 0xc5
7957#define RR_SYNFB_LK BIT(15)
7958#define RR_AACK 0xca
7959#define RR_LCKST 0xcf
7960#define RR_LCKST_BIN BIT(0)
7961#define RR_LCK_TRG 0xd3
7962#define RR_LCK_TRGSEL BIT(8)
7963#define RR_LCK_ST BIT(4)
7964#define RR_MMD 0xd5
7965#define RR_MMD_RST_EN BIT(8)
7966#define RR_MMD_RST_SYN BIT(6)
7967#define RR_SMD 0xd6
7968#define RR_VCO2 BIT(19)
7969#define RR_IQKPLL 0xdc
7970#define RR_IQKPLL_MOD GENMASK(9, 8)
7971#define RR_SYNLUT 0xdd
7972#define RR_SYNLUT_MOD BIT(4)
7973#define RR_RCKD 0xde
7974#define RR_RCKD_POW GENMASK(19, 13)
7975#define RR_RCKD_BW BIT(2)
7976#define RR_TXADBG 0xde
7977#define RR_LUTDBG 0xdf
7978#define RR_LUTDBG_TIA BIT(12)
7979#define RR_LUTDBG_LOK BIT(2)
7980#define RR_LUTPLL 0xec
7981#define RR_CAL_RW BIT(19)
7982#define RR_LUTWE2 0xee
7983#define RR_LUTWE2_RTXBW BIT(2)
7984#define RR_LUTWE2_DIS BIT(6)
7985#define RR_LUTWE 0xef
7986#define RR_LUTWE_LOK BIT(2)
7987#define RR_RFC 0xf0
7988#define RR_WCAL BIT(16)
7989#define RR_RFC_CKEN BIT(1)
7990
7991#define R_UPD_P0 0x0000
7992#define R_BBCLK 0x0000
7993#define B_CLK_640M BIT(2)
7994#define R_RSTB_WATCH_DOG 0x000C
7995#define B_P0_RSTB_WATCH_DOG BIT(0)
7996#define B_P1_RSTB_WATCH_DOG BIT(1)
7997#define B_UPD_P0_EN BIT(31)
7998#define R_EMLSR 0x0044
7999#define B_EMLSR_PARM GENMASK(27, 12)
8000#define R_CHK_LPS_STAT 0x0058
8001#define B_CHK_LPS_STAT BIT(0)
8002#define R_SPOOF_CG 0x00B4
8003#define B_SPOOF_CG_EN BIT(17)
8004#define R_CHINFO_SEG 0x00B4
8005#define B_CHINFO_SEG_LEN GENMASK(2, 0)
8006#define B_CHINFO_SEG GENMASK(16, 7)
8007#define R_DFS_FFT_CG 0x00B8
8008#define B_DFS_CG_EN BIT(1)
8009#define B_DFS_FFT_EN BIT(0)
8010#define R_CHINFO_DATA 0x00C0
8011#define B_CHINFO_DATA_BITMAP GENMASK(22, 0)
8012#define R_ANAPAR_PW15 0x030C
8013#define B_ANAPAR_PW15 GENMASK(31, 24)
8014#define B_ANAPAR_PW15_H GENMASK(27, 24)
8015#define B_ANAPAR_PW15_H2 GENMASK(27, 26)
8016#define R_ANAPAR 0x032C
8017#define B_ANAPAR_15 GENMASK(31, 16)
8018#define B_ANAPAR_EN1 BIT(31)
8019#define B_ANAPAR_ADCCLK BIT(30)
8020#define B_ANAPAR_FLTRST BIT(22)
8021#define B_ANAPAR_CRXBB GENMASK(18, 16)
8022#define B_ANAPAR_EN BIT(16)
8023#define B_ANAPAR_14 GENMASK(15, 0)
8024#define R_RFE_E_A2 0x0334
8025#define R_RFE_O_SEL_A2 0x0338
8026#define R_RFE_SEL0_A2 0x033C
8027#define B_RFE_SEL0_MASK GENMASK(1, 0)
8028#define R_RFE_SEL32_A2 0x0340
8029#define R_CIRST 0x035c
8030#define B_CIRST_SYN GENMASK(11, 10)
8031#define R_SWSI_DATA_V1 0x0370
8032#define B_SWSI_DATA_VAL_V1 GENMASK(19, 0)
8033#define B_SWSI_DATA_ADDR_V1 GENMASK(27, 20)
8034#define B_SWSI_DATA_PATH_V1 GENMASK(30, 28)
8035#define B_SWSI_DATA_BIT_MASK_EN_V1 BIT(31)
8036#define R_SWSI_BIT_MASK_V1 0x0374
8037#define B_SWSI_BIT_MASK_V1 GENMASK(19, 0)
8038#define R_SWSI_READ_ADDR_V1 0x0378
8039#define B_SWSI_READ_ADDR_ADDR_V1 GENMASK(7, 0)
8040#define B_SWSI_READ_ADDR_PATH_V1 GENMASK(10, 8)
8041#define B_SWSI_READ_ADDR_V1 GENMASK(10, 0)
8042#define R_BRK_R 0x0418
8043#define B_VHTMCS_LMT GENMASK(22, 21)
8044#define B_HTMCS_LMT GENMASK(9, 8)
8045#define R_BRK_EHT 0x0474
8046#define B_RXEHT_NSS_MAX GENMASK(4, 2)
8047#define R_BRK_RXEHT 0x0478
8048#define B_RXEHT_N_USER_MAX GENMASK(31, 24)
8049#define B_RXEHTTB_NSS_MAX GENMASK(16, 14)
8050#define R_EN_SND_WO_NDP 0x047c
8051#define R_EN_SND_WO_NDP_C1 0x147c
8052#define B_EN_SND_WO_NDP BIT(1)
8053#define R_BRK_HE 0x0480
8054#define B_TB_NSS_MAX GENMASK(25, 23)
8055#define B_NSS_MAX GENMASK(16, 14)
8056#define B_N_USR_MAX GENMASK(13, 6)
8057#define R_RXCCA_BE1 0x0520
8058#define B_RXCCA_BE1_DIS BIT(0)
8059#define R_UPD_CLK_ADC 0x0700
8060#define B_UPD_GEN_ON BIT(27)
8061#define B_UPD_CLK_ADC_VAL GENMASK(26, 25)
8062#define B_UPD_CLK_ADC_ON BIT(24)
8063#define B_ENABLE_CCK BIT(5)
8064#define R_RSTB_ASYNC 0x0704
8065#define B_RSTB_ASYNC_BW80 GENMASK(9, 8)
8066#define B_RSTB_ASYNC_ALL BIT(1)
8067#define R_P0_ANT_SW 0x0728
8068#define B_P0_HW_ANTSW_DIS_BY_GNT_BT BIT(12)
8069#define B_P0_TRSW_TX_EXTEND GENMASK(3, 0)
8070#define R_MAC_PIN_SEL 0x0734
8071#define B_CH_IDX_SEG0 GENMASK(23, 16)
8072#define R_PLCP_HISTOGRAM 0x0738
8073#define B_STS_PARSING_TIME GENMASK(19, 16)
8074#define B_STS_DIS_TRIG_BY_FAIL BIT(3)
8075#define B_STS_DIS_TRIG_BY_BRK BIT(2)
8076#define R_PHY_STS_BITMAP_ADDR_START R_PHY_STS_BITMAP_SEARCH_FAIL
8077#define B_PHY_STS_BITMAP_ADDR_MASK GENMASK(6, 2)
8078#define R_PHY_STS_BITMAP_SEARCH_FAIL 0x073C
8079#define B_PHY_STS_BITMAP_MSK_52A 0x337cff3f
8080#define R_PHY_STS_BITMAP_R2T 0x0740
8081#define R_PHY_STS_BITMAP_CCA_SPOOF 0x0744
8082#define R_PHY_STS_BITMAP_OFDM_BRK 0x0748
8083#define R_PHY_STS_BITMAP_CCK_BRK 0x074C
8084#define R_PHY_STS_BITMAP_DL_MU_SPOOF 0x0750
8085#define R_PHY_STS_BITMAP_HE_MU 0x0754
8086#define R_PHY_STS_BITMAP_VHT_MU 0x0758
8087#define R_PHY_STS_BITMAP_UL_TB_SPOOF 0x075C
8088#define R_PHY_STS_BITMAP_TRIGBASE 0x0760
8089#define R_PHY_STS_BITMAP_CCK 0x0764
8090#define R_PHY_STS_BITMAP_LEGACY 0x0768
8091#define R_PHY_STS_BITMAP_HT 0x076C
8092#define R_PHY_STS_BITMAP_VHT 0x0770
8093#define R_PHY_STS_BITMAP_HE 0x0774
8094#define R_PHY_STS_BITMAP_EHT 0x0788
8095#define R_EDCCA_RPTREG_SEL_BE 0x078C
8096#define B_EDCCA_RPTREG_SEL_BE_MSK GENMASK(22, 20)
8097#define R_PMAC_GNT 0x0980
8098#define B_PMAC_GNT_TXEN BIT(0)
8099#define B_PMAC_GNT_RXEN BIT(16)
8100#define B_PMAC_GNT_P1 GENMASK(20, 17)
8101#define B_PMAC_GNT_P2 GENMASK(29, 26)
8102#define R_PMAC_RX_CFG1 0x0988
8103#define B_PMAC_OPT1_MSK GENMASK(11, 0)
8104#define R_PMAC_RXMOD 0x0994
8105#define B_PMAC_RXMOD_MSK GENMASK(7, 4)
8106#define R_MAC_SEL 0x09A4
8107#define B_MAC_SEL_OFDM_TRI_FILTER BIT(31)
8108#define B_MAC_SEL GENMASK(19, 17)
8109#define B_MAC_SEL_PWR_EN BIT(16)
8110#define B_MAC_SEL_DPD_EN BIT(10)
8111#define B_MAC_SEL_MOD GENMASK(4, 2)
8112#define R_PMAC_TX_CTRL 0x09C0
8113#define B_PMAC_TXEN_DIS BIT(0)
8114#define R_PMAC_TX_PRD 0x09C4
8115#define B_PMAC_TX_PRD_MSK GENMASK(31, 8)
8116#define B_PMAC_CTX_EN BIT(0)
8117#define B_PMAC_PTX_EN BIT(4)
8118#define R_PMAC_TX_CNT 0x09C8
8119#define B_PMAC_TX_CNT_MSK GENMASK(31, 0)
8120#define R_P80_AT_HIGH_FREQ 0x09D8
8121#define B_P80_AT_HIGH_FREQ BIT(26)
8122#define R_DBCC_80P80_SEL_EVM_RPT 0x0A10
8123#define B_DBCC_80P80_SEL_EVM_RPT_EN BIT(0)
8124#define R_CCX 0x0C00
8125#define B_CCX_EDCCA_OPT_MSK GENMASK(6, 4)
8126#define B_CCX_EDCCA_OPT_MSK_V1 GENMASK(7, 4)
8127#define B_MEASUREMENT_TRIG_MSK BIT(2)
8128#define B_CCX_TRIG_OPT_MSK BIT(1)
8129#define B_CCX_EN_MSK BIT(0)
8130#define R_NHM_CFG 0x0C08
8131#define B_NHM_PERIOD_MSK GENMASK(15, 0)
8132#define B_NHM_COUNTER_MSK GENMASK(17, 16)
8133#define B_NHM_EN_MSK BIT(18)
8134#define B_NHM_INCLUDE_CCA_MSK BIT(19)
8135#define B_NHM_TH0_MSK GENMASK(31, 24)
8136#define R_NHM_TH1 0x0C0C
8137#define B_NHM_TH1_MSK GENMASK(7, 0)
8138#define B_NHM_TH2_MSK GENMASK(15, 8)
8139#define B_NHM_TH3_MSK GENMASK(23, 16)
8140#define B_NHM_TH4_MSK GENMASK(31, 24)
8141#define R_NHM_TH5 0x0C10
8142#define B_NHM_TH5_MSK GENMASK(7, 0)
8143#define B_NHM_TH6_MSK GENMASK(15, 8)
8144#define B_NHM_TH7_MSK GENMASK(23, 16)
8145#define B_NHM_TH8_MSK GENMASK(31, 24)
8146#define R_NHM_TH9 0x0C14
8147#define B_NHM_TH9_MSK GENMASK(7, 0)
8148#define B_NHM_TH10_MSK GENMASK(15, 8)
8149#define B_NHM_PWDB_METHOD_MSK GENMASK(17, 16)
8150#define R_FAHM 0x0C1C
8151#define B_RXTD_CKEN BIT(2)
8152#define R_IFS_COUNTER 0x0C28
8153#define B_IFS_CLM_PERIOD_MSK GENMASK(31, 16)
8154#define B_IFS_CLM_COUNTER_UNIT_MSK GENMASK(15, 14)
8155#define B_IFS_COUNTER_CLR_MSK BIT(13)
8156#define B_IFS_COLLECT_EN BIT(12)
8157#define R_IFS_T1 0x0C2C
8158#define B_IFS_T1_TH_HIGH_MSK GENMASK(31, 16)
8159#define B_IFS_T1_EN_MSK BIT(15)
8160#define B_IFS_T1_TH_LOW_MSK GENMASK(14, 0)
8161#define R_IFS_T2 0x0C30
8162#define B_IFS_T2_TH_HIGH_MSK GENMASK(31, 16)
8163#define B_IFS_T2_EN_MSK BIT(15)
8164#define B_IFS_T2_TH_LOW_MSK GENMASK(14, 0)
8165#define R_IFS_T3 0x0C34
8166#define B_IFS_T3_TH_HIGH_MSK GENMASK(31, 16)
8167#define B_IFS_T3_EN_MSK BIT(15)
8168#define B_IFS_T3_TH_LOW_MSK GENMASK(14, 0)
8169#define R_IFS_T4 0x0C38
8170#define B_IFS_T4_TH_HIGH_MSK GENMASK(31, 16)
8171#define B_IFS_T4_EN_MSK BIT(15)
8172#define B_IFS_T4_TH_LOW_MSK GENMASK(14, 0)
8173#define R_PD_CTRL 0x0C3C
8174#define B_PD_HIT_DIS BIT(9)
8175#define R_IOQ_IQK_DPK 0x0C60
8176#define B_IOQ_IQK_DPK_CLKEN GENMASK(1, 0)
8177#define B_IOQ_IQK_DPK_EN BIT(1)
8178#define R_GNT_BT_WGT_EN 0x0C6C
8179#define B_GNT_BT_WGT_EN BIT(21)
8180#define R_IQK_DPK_RST 0x0C6C
8181#define R_IQK_DPK_RST_C1 0x1C6C
8182#define B_IQK_DPK_RST BIT(0)
8183#define R_TX_COLLISION_T2R_ST 0x0C70
8184#define B_TX_COLLISION_T2R_ST_M GENMASK(25, 20)
8185#define B_TXRX_FORCE_VAL GENMASK(9, 0)
8186#define R_TXGATING 0x0C74
8187#define B_TXGATING_EN BIT(4)
8188#define R_TXRFC 0x0C7C
8189#define R_TXRFC_C1 0x1C7C
8190#define B_TXRFC_RST GENMASK(23, 21)
8191#define R_PD_ARBITER_OFF 0x0C80
8192#define B_PD_ARBITER_OFF BIT(31)
8193#define R_SNDCCA_A1 0x0C9C
8194#define B_SNDCCA_A1_EN GENMASK(19, 12)
8195#define R_SNDCCA_A2 0x0CA0
8196#define B_SNDCCA_A2_VAL GENMASK(19, 12)
8197#define R_UDP_COEEF 0x0CBC
8198#define B_UDP_COEEF BIT(19)
8199#define R_TX_COLLISION_T2R_ST_BE 0x0CC8
8200#define B_TX_COLLISION_T2R_ST_BE_M GENMASK(13, 8)
8201#define R_RXHT_MCS_LIMIT 0x0D18
8202#define B_RXHT_MCS_LIMIT GENMASK(9, 8)
8203#define R_RXVHT_MCS_LIMIT 0x0D18
8204#define B_RXVHT_MCS_LIMIT GENMASK(22, 21)
8205#define R_P0_EN_SOUND_WO_NDP 0x0D7C
8206#define B_P0_EN_SOUND_WO_NDP BIT(1)
8207#define R_RXHE 0x0D80
8208#define B_RXHETB_MAX_NSS GENMASK(25, 23)
8209#define B_RXHE_MAX_NSS GENMASK(16, 14)
8210#define B_RXHE_USER_MAX GENMASK(13, 6)
8211#define R_SPOOF_ASYNC_RST 0x0D84
8212#define B_SPOOF_ASYNC_RST BIT(15)
8213#define R_NDP_BRK0 0xDA0
8214#define R_NDP_BRK1 0xDA4
8215#define B_NDP_RU_BRK BIT(0)
8216#define R_BRK_ASYNC_RST_EN_1 0x0DC0
8217#define R_BRK_ASYNC_RST_EN_2 0x0DC4
8218#define R_BRK_ASYNC_RST_EN_3 0x0DC8
8219#define R_NHM_BE 0x0EA4
8220#define B_NHM_READY_BE_MSK BIT(16)
8221#define R_CTLTOP 0x1008
8222#define B_CTLTOP_ON BIT(23)
8223#define B_CTLTOP_VAL GENMASK(15, 12)
8224#define R_CLK_GCK 0x1008
8225#define B_CLK_GCK GENMASK(24, 0)
8226#define R_EDCCA_RPT_SEL_BE 0x10CC
8227#define R_ADC_FIFO_V1 0x10FC
8228#define B_ADC_FIFO_EN_V1 GENMASK(31, 24)
8229#define R_S0_HW_SI_DIS 0x1200
8230#define B_S0_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
8231#define R_P0_RXCK 0x12A0
8232#define B_P0_RXCK_ADJ GENMASK(31, 23)
8233#define B_P0_RXCK_BW3 BIT(30)
8234#define B_P0_TXCK_ALL GENMASK(19, 12)
8235#define B_P0_RXCK_ON BIT(19)
8236#define B_P0_RXCK_VAL GENMASK(18, 16)
8237#define B_P0_TXCK_ON BIT(15)
8238#define B_P0_TXCK_VAL GENMASK(14, 12)
8239#define R_P0_RFMODE 0x12AC
8240#define B_P0_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
8241#define B_P0_RFMODE_MUX GENMASK(11, 4)
8242#define R_P0_RFMODE_ORI_RX 0x12AC
8243#define B_P0_RFMODE_ORI_RX_ALL GENMASK(23, 12)
8244#define R_P0_RFMODE_FTM_RX 0x12B0
8245#define B_P0_RFMODE_FTM_RX GENMASK(11, 0)
8246#define R_P0_NRBW 0x12B8
8247#define B_P0_NRBW_DBG BIT(30)
8248#define B_P0_NRBW_RSTB BIT(28)
8249#define R_S0_RXDC 0x12D4
8250#define B_S0_RXDC_I GENMASK(25, 16)
8251#define B_S0_RXDC_Q GENMASK(31, 26)
8252#define R_S0_RXDC2 0x12D8
8253#define B_S0_RXDC2_SEL GENMASK(9, 8)
8254#define B_S0_RXDC2_AVG GENMASK(7, 6)
8255#define B_S0_RXDC2_MEN GENMASK(5, 4)
8256#define B_S0_RXDC2_Q2 GENMASK(3, 0)
8257#define R_CFO_COMP_SEG0_L 0x1384
8258#define R_CFO_COMP_SEG0_H 0x1388
8259#define R_CFO_COMP_SEG0_CTRL 0x138C
8260#define R_DBG32_D 0x1730
8261#define R_EDCCA_RPT_A 0x1738
8262#define R_EDCCA_RPT_B 0x173c
8263#define B_EDCCA_RPT_B_FB BIT(7)
8264#define B_EDCCA_RPT_B_P20 BIT(6)
8265#define B_EDCCA_RPT_B_S20 BIT(5)
8266#define B_EDCCA_RPT_B_S40 BIT(4)
8267#define B_EDCCA_RPT_B_S80 BIT(3)
8268#define B_EDCCA_RPT_B_PATH_MASK GENMASK(2, 1)
8269#define R_EDCCA_RPT_P1_A 0x1740
8270#define R_EDCCA_RPT_P1_B 0x1744
8271#define R_SWSI_V1 0x174C
8272#define B_SWSI_W_BUSY_V1 BIT(24)
8273#define B_SWSI_R_BUSY_V1 BIT(25)
8274#define B_SWSI_R_DATA_DONE_V1 BIT(26)
8275#define R_TX_COUNTER 0x1A40
8276#define R_NHM_CNT0 0x1A88
8277#define B_NHM_CNT0_MSK GENMASK(15, 0)
8278#define B_NHM_CNT1_MSK GENMASK(31, 16)
8279#define R_NHM_CNT2 0x1A8C
8280#define B_NHM_CNT2_MSK GENMASK(15, 0)
8281#define B_NHM_CNT3_MSK GENMASK(31, 16)
8282#define R_NHM_CNT4 0x1A90
8283#define B_NHM_CNT4_MSK GENMASK(15, 0)
8284#define B_NHM_CNT5_MSK GENMASK(31, 16)
8285#define R_NHM_CNT6 0x1A94
8286#define B_NHM_CNT6_MSK GENMASK(15, 0)
8287#define B_NHM_CNT7_MSK GENMASK(31, 16)
8288#define R_NHM_CNT8 0x1A98
8289#define B_NHM_CNT8_MSK GENMASK(15, 0)
8290#define B_NHM_CNT9_MSK GENMASK(31, 16)
8291#define R_NHM_CNT10 0x1A9C
8292#define B_NHM_CNT10_MSK GENMASK(15, 0)
8293#define B_NHM_CNT11_MSK GENMASK(31, 16)
8294#define R_NHM_AX 0x1AA4
8295#define B_NHM_READY_MSK BIT(16)
8296#define R_IFS_CLM_TX_CNT 0x1ACC
8297#define R_IFS_CLM_TX_CNT_V1 0x0ECC
8298#define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16)
8299#define B_IFS_CLM_TX_CNT_MSK GENMASK(15, 0)
8300#define R_IFS_CLM_CCA 0x1AD0
8301#define R_IFS_CLM_CCA_V1 0x0ED0
8302#define B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK GENMASK(31, 16)
8303#define B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK GENMASK(15, 0)
8304#define R_IFS_CLM_FA 0x1AD4
8305#define R_IFS_CLM_FA_V1 0x0ED4
8306#define B_IFS_CLM_OFDM_FA_MSK GENMASK(31, 16)
8307#define B_IFS_CLM_CCK_FA_MSK GENMASK(15, 0)
8308#define R_IFS_HIS 0x1AD8
8309#define R_IFS_HIS_V1 0x0ED8
8310#define B_IFS_T4_HIS_MSK GENMASK(31, 24)
8311#define B_IFS_T3_HIS_MSK GENMASK(23, 16)
8312#define B_IFS_T2_HIS_MSK GENMASK(15, 8)
8313#define B_IFS_T1_HIS_MSK GENMASK(7, 0)
8314#define R_IFS_AVG_L 0x1ADC
8315#define R_IFS_AVG_L_V1 0x0EDC
8316#define B_IFS_T2_AVG_MSK GENMASK(31, 16)
8317#define B_IFS_T1_AVG_MSK GENMASK(15, 0)
8318#define R_IFS_AVG_H 0x1AE0
8319#define R_IFS_AVG_H_V1 0x0EE0
8320#define B_IFS_T4_AVG_MSK GENMASK(31, 16)
8321#define B_IFS_T3_AVG_MSK GENMASK(15, 0)
8322#define R_IFS_CCA_L 0x1AE4
8323#define R_IFS_CCA_L_V1 0x0EE4
8324#define B_IFS_T2_CCA_MSK GENMASK(31, 16)
8325#define B_IFS_T1_CCA_MSK GENMASK(15, 0)
8326#define R_IFS_CCA_H 0x1AE8
8327#define R_IFS_CCA_H_V1 0x0EE8
8328#define B_IFS_T4_CCA_MSK GENMASK(31, 16)
8329#define B_IFS_T3_CCA_MSK GENMASK(15, 0)
8330#define R_IFSCNT 0x1AEC
8331#define R_IFSCNT_V1 0x0EEC
8332#define B_IFSCNT_DONE_MSK BIT(16)
8333#define B_IFSCNT_TOTAL_CNT_MSK GENMASK(15, 0)
8334#define R_TXAGC_TP 0x1C04
8335#define B_TXAGC_TP GENMASK(2, 0)
8336#define R_TSSI_THER 0x1C10
8337#define B_TSSI_THER GENMASK(29, 24)
8338#define R_TSSI_CWRPT 0x1C18
8339#define B_TSSI_CWRPT_RDY BIT(16)
8340#define B_TSSI_CWRPT GENMASK(8, 0)
8341#define R_TXAGC_BTP 0x1CA0
8342#define B_TXAGC_BTP GENMASK(31, 24)
8343#define R_TXAGC_BB 0x1C60
8344#define B_TXAGC_BB_OFT GENMASK(31, 16)
8345#define B_TXAGC_BB GENMASK(31, 24)
8346#define B_TXAGC_RF GENMASK(5, 0)
8347#define R_PATH0_TXPWR 0x1C78
8348#define B_PATH0_TXPWR GENMASK(8, 0)
8349#define R_S0_ADDCK 0x1E00
8350#define B_S0_ADDCK_I GENMASK(9, 0)
8351#define B_S0_ADDCK_Q GENMASK(19, 10)
8352#define R_TXCKEN_FORCE 0x2008
8353#define B_TXCKEN_FORCE_ALL GENMASK(24, 0)
8354#define R_EDCCA_RPT_SEL 0x20CC
8355#define B_EDCCA_RPT_SEL_MSK GENMASK(2, 0)
8356#define B_EDCCA_RPT_SEL_P1_MSK GENMASK(5, 3)
8357#define R_ADC_FIFO 0x20fc
8358#define B_ADC_FIFO_RST GENMASK(31, 24)
8359#define B_ADC_FIFO_RXK GENMASK(31, 16)
8360#define B_ADC_FIFO_A3 BIT(28)
8361#define B_ADC_FIFO_A2 BIT(24)
8362#define B_ADC_FIFO_A1 BIT(20)
8363#define B_ADC_FIFO_A0 BIT(16)
8364#define R_TXFIR0 0x2300
8365#define B_TXFIR_C01 GENMASK(23, 0)
8366#define R_TXFIR2 0x2304
8367#define B_TXFIR_C23 GENMASK(23, 0)
8368#define R_TXFIR4 0x2308
8369#define B_TXFIR_C45 GENMASK(23, 0)
8370#define R_TXFIR6 0x230c
8371#define B_TXFIR_C67 GENMASK(23, 0)
8372#define R_TXFIR8 0x2310
8373#define B_TXFIR_C89 GENMASK(23, 0)
8374#define R_TXFIRA 0x2314
8375#define B_TXFIR_CAB GENMASK(23, 0)
8376#define R_TXFIRC 0x2318
8377#define B_TXFIR_CCD GENMASK(23, 0)
8378#define R_TXFIRE 0x231c
8379#define B_TXFIR_CEF GENMASK(23, 0)
8380#define R_11B_RX_V1 0x2320
8381#define B_11B_RXCCA_DIS_V1 BIT(0)
8382#define R_RPL_OFST 0x2340
8383#define B_RPL_OFST_MASK GENMASK(14, 8)
8384#define R_RXCCA 0x2344
8385#define B_RXCCA_DIS BIT(31)
8386#define R_RXCCA_V1 0x2320
8387#define B_RXCCA_DIS_V1 BIT(0)
8388#define R_RXSC 0x237C
8389#define B_RXSC_EN BIT(0)
8390#define R_RX_RPL_OFST 0x23AC
8391#define B_RX_RPL_OFST_CCK_MASK GENMASK(6, 0)
8392#define R_RXSCOBC 0x23B0
8393#define B_RXSCOBC_TH GENMASK(18, 0)
8394#define R_RXSCOCCK 0x23B4
8395#define B_RXSCOCCK_TH GENMASK(18, 0)
8396#define R_P80_AT_HIGH_FREQ_RU_ALLOC 0x2410
8397#define B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1 BIT(14)
8398#define B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0 BIT(13)
8399#define R_DBCC_80P80_SEL_EVM_RPT2 0x2A10
8400#define B_DBCC_80P80_SEL_EVM_RPT2_EN BIT(0)
8401#define R_AFEDAC0 0x2A5C
8402#define B_AFEDAC0 GENMASK(31, 27)
8403#define R_AFEDAC1 0x2A60
8404#define B_AFEDAC1 GENMASK(2, 0)
8405#define R_IQKDPK_HC 0x2AB8
8406#define B_IQKDPK_HC BIT(28)
8407#define R_HWSI_ADD0 0x2ADC
8408#define R_HWSI_ADD1 0x2BDC
8409#define B_HWSI_ADD_MASK GENMASK(11, 4)
8410#define B_HWSI_ADD_CTL_MASK GENMASK(2, 0)
8411#define B_HWSI_ADD_RD BIT(2)
8412#define B_HWSI_ADD_POLL_MASK GENMASK(1, 0)
8413#define B_HWSI_ADD_RUN BIT(1)
8414#define B_HWSI_ADD_BUSY BIT(0)
8415#define R_HWSI_DATA 0x2AE0
8416#define B_HWSI_DATA_VAL GENMASK(27, 8)
8417#define B_HWSI_DATA_ADDR GENMASK(7, 0)
8418#define R_HWSI_VAL0 0x2C24
8419#define R_HWSI_VAL1 0x2D24
8420#define B_HWSI_VAL_RDONE BIT(31)
8421#define B_HWSI_VAL_BUSY BIT(29)
8422#define R_P1_EN_SOUND_WO_NDP 0x2D7C
8423#define B_P1_EN_SOUND_WO_NDP BIT(1)
8424#define R_EDCCA_RPT_A_BE 0x2E38
8425#define R_EDCCA_RPT_B_BE 0x2E3C
8426#define R_EDCCA_RPT_P1_A_BE 0x2E40
8427#define R_EDCCA_RPT_P1_B_BE 0x2E44
8428#define R_S1_HW_SI_DIS 0x3200
8429#define B_S1_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
8430#define R_P1_RXCK 0x32A0
8431#define B_P1_RXCK_BW3 BIT(30)
8432#define B_P1_TXCK_ALL GENMASK(19, 12)
8433#define B_P1_RXCK_ON BIT(19)
8434#define B_P1_RXCK_VAL GENMASK(18, 16)
8435#define R_P1_RFMODE 0x32AC
8436#define B_P1_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
8437#define B_P1_RFMODE_MUX GENMASK(11, 4)
8438#define R_P1_RFMODE_ORI_RX 0x32AC
8439#define B_P1_RFMODE_ORI_RX_ALL GENMASK(23, 12)
8440#define R_P1_RFMODE_FTM_RX 0x32B0
8441#define B_P1_RFMODE_FTM_RX GENMASK(11, 0)
8442#define R_P1_DBGMOD 0x32B8
8443#define B_P1_DBGMOD_ON BIT(30)
8444#define R_S1_RXDC 0x32D4
8445#define B_S1_RXDC_I GENMASK(25, 16)
8446#define B_S1_RXDC_Q GENMASK(31, 26)
8447#define R_S1_RXDC2 0x32D8
8448#define B_S1_RXDC2_EN GENMASK(5, 4)
8449#define B_S1_RXDC2_SEL GENMASK(9, 8)
8450#define B_S1_RXDC2_Q2 GENMASK(3, 0)
8451#define R_TXAGC_BB_S1 0x3C60
8452#define B_TXAGC_BB_S1_OFT GENMASK(31, 16)
8453#define B_TXAGC_BB_S1 GENMASK(31, 24)
8454#define R_PATH1_TXPWR 0x3C78
8455#define B_PATH1_TXPWR GENMASK(8, 0)
8456#define R_S1_ADDCK 0x3E00
8457#define B_S1_ADDCK_I GENMASK(9, 0)
8458#define B_S1_ADDCK_Q GENMASK(19, 10)
8459#define R_OP1DB_A 0x40B0
8460#define B_OP1DB_A GENMASK(31, 24)
8461#define R_OP1DB1_A 0x40BC
8462#define B_TIA10_A GENMASK(15, 0)
8463#define B_TIA1_A GENMASK(15, 8)
8464#define B_TIA0_A GENMASK(7, 0)
8465#define R_BKOFF_A 0x40E0
8466#define B_BKOFF_IBADC_A GENMASK(23, 18)
8467#define R_BACKOFF_A 0x40E4
8468#define B_LNA_IBADC_A GENMASK(29, 18)
8469#define B_BACKOFF_LNA_A GENMASK(29, 24)
8470#define B_BACKOFF_IBADC_A GENMASK(23, 18)
8471#define R_RXBY_WBADC_A 0x40F4
8472#define B_RXBY_WBADC_A GENMASK(14, 10)
8473#define R_MUIC 0x40F8
8474#define B_MUIC_EN BIT(0)
8475#define R_BT_RXBY_WBADC_A 0x4160
8476#define B_BT_RXBY_WBADC_A BIT(31)
8477#define R_BT_SHARE_A 0x4164
8478#define B_BT_SHARE_A BIT(0)
8479#define B_BT_TRK_OFF_A BIT(1)
8480#define B_BTG_PATH_A BIT(4)
8481#define R_FORCE_FIR_A 0x418C
8482#define B_FORCE_FIR_A GENMASK(1, 0)
8483#define R_DCFO 0x4264
8484#define B_DCFO GENMASK(7, 0)
8485#define R_SEG0CSI 0x42AC
8486#define R_SEG0CSI_V1 0x42B0
8487#define B_SEG0CSI_IDX GENMASK(10, 0)
8488#define R_SEG0CSI_EN 0x42C4
8489#define R_SEG0CSI_EN_V1 0x42C8
8490#define B_SEG0CSI_EN BIT(23)
8491#define R_BSS_CLR_MAP 0x43ac
8492#define R_BSS_CLR_MAP_V1 0x43B0
8493#define R_BSS_CLR_MAP_V2 0x4EB0
8494#define B_BSS_CLR_MAP_VLD0 BIT(28)
8495#define B_BSS_CLR_MAP_TGT GENMASK(27, 22)
8496#define B_BSS_CLR_MAP_STAID GENMASK(21, 11)
8497#define R_CFO_TRK0 0x4404
8498#define R_CFO_TRK1 0x440C
8499#define B_CFO_TRK_MSK GENMASK(14, 10)
8500#define R_T2F_GI_COMB 0x4424
8501#define B_T2F_GI_COMB_EN BIT(2)
8502#define R_BT_DYN_DC_EST_EN 0x441C
8503#define R_BT_DYN_DC_EST_EN_V1 0x4420
8504#define B_BT_DYN_DC_EST_EN_MSK BIT(31)
8505#define R_ASSIGN_SBD_OPT_V1 0x4440
8506#define B_ASSIGN_SBD_OPT_EN_V1 BIT(31)
8507#define R_ASSIGN_SBD_OPT 0x4450
8508#define B_ASSIGN_SBD_OPT_EN BIT(24)
8509#define R_DCFO_COMP_S0 0x448C
8510#define B_DCFO_COMP_S0_MSK GENMASK(11, 0)
8511#define R_DCFO_WEIGHT 0x4490
8512#define B_DAC_CLK_IDX BIT(31)
8513#define B_DCFO_WEIGHT_MSK GENMASK(27, 24)
8514#define R_DCFO_OPT 0x4494
8515#define B_DCFO_OPT_EN BIT(29)
8516#define B_TXSHAPE_TRIANGULAR_CFG GENMASK(25, 24)
8517#define R_BANDEDGE 0x4498
8518#define B_BANDEDGE_EN BIT(30)
8519#define R_DPD_BF 0x44a0
8520#define B_DPD_BF_OFDM GENMASK(16, 12)
8521#define B_DPD_BF_SCA GENMASK(6, 0)
8522#define R_LNA_OP 0x44B0
8523#define B_LNA6 GENMASK(31, 24)
8524#define R_LNA_TIA 0x44BC
8525#define B_TIA10_B GENMASK(15, 0)
8526#define B_TIA1_B GENMASK(15, 8)
8527#define B_TIA0_B GENMASK(7, 0)
8528#define R_BKOFF_B 0x44E0
8529#define B_BKOFF_IBADC_B GENMASK(23, 18)
8530#define R_BACKOFF_B 0x44E4
8531#define B_LNA_IBADC_B GENMASK(29, 18)
8532#define B_BACKOFF_LNA_B GENMASK(29, 24)
8533#define B_BACKOFF_IBADC_B GENMASK(23, 18)
8534#define R_RXBY_WBADC_B 0x44F4
8535#define B_RXBY_WBADC_B GENMASK(14, 10)
8536#define R_BT_RXBY_WBADC_B 0x4560
8537#define B_BT_RXBY_WBADC_B BIT(31)
8538#define R_BT_SHARE_B 0x4564
8539#define B_BT_SHARE_B BIT(0)
8540#define B_BT_TRK_OFF_B BIT(1)
8541#define B_BTG_PATH_B BIT(4)
8542#define R_TXPATH_SEL 0x458C
8543#define B_TXPATH_SEL_MSK GENMASK(31, 28)
8544#define R_FORCE_FIR_B 0x458C
8545#define B_FORCE_FIR_B GENMASK(1, 0)
8546#define R_TXPWR 0x4594
8547#define B_TXPWR_MSK GENMASK(30, 22)
8548#define R_TXNSS_MAP 0x45B4
8549#define B_TXNSS_MAP_MSK GENMASK(20, 17)
8550#define R_PCOEFF0_V1 0x45BC
8551#define B_PCOEFF01_MSK_V1 GENMASK(23, 0)
8552#define R_PCOEFF2_V1 0x45CC
8553#define B_PCOEFF23_MSK_V1 GENMASK(23, 0)
8554#define R_PCOEFF4_V1 0x45D0
8555#define B_PCOEFF45_MSK_V1 GENMASK(23, 0)
8556#define R_PCOEFF6_V1 0x45D4
8557#define B_PCOEFF67_MSK_V1 GENMASK(23, 0)
8558#define R_PCOEFF8_V1 0x45D8
8559#define B_PCOEFF89_MSK_V1 GENMASK(23, 0)
8560#define R_PCOEFFA_V1 0x45C0
8561#define B_PCOEFFAB_MSK_V1 GENMASK(23, 0)
8562#define R_PCOEFFC_V1 0x45C4
8563#define B_PCOEFFCD_MSK_V1 GENMASK(23, 0)
8564#define R_PCOEFFE_V1 0x45C8
8565#define B_PCOEFFEF_MSK_V1 GENMASK(23, 0)
8566#define R_PATH0_IB_PKPW 0x4628
8567#define B_PATH0_IB_PKPW_MSK GENMASK(11, 6)
8568#define R_PATH0_LNA_ERR1 0x462C
8569#define B_PATH0_LNA_ERR_G1_A_MSK GENMASK(29, 24)
8570#define B_PATH0_LNA_ERR_G0_G_MSK GENMASK(17, 12)
8571#define B_PATH0_LNA_ERR_G0_A_MSK GENMASK(11, 6)
8572#define R_PATH0_LNA_ERR2 0x4630
8573#define B_PATH0_LNA_ERR_G2_G_MSK GENMASK(23, 18)
8574#define B_PATH0_LNA_ERR_G2_A_MSK GENMASK(17, 12)
8575#define B_PATH0_LNA_ERR_G1_G_MSK GENMASK(5, 0)
8576#define R_PATH0_LNA_ERR3 0x4634
8577#define B_PATH0_LNA_ERR_G4_G_MSK GENMASK(29, 24)
8578#define B_PATH0_LNA_ERR_G4_A_MSK GENMASK(23, 18)
8579#define B_PATH0_LNA_ERR_G3_G_MSK GENMASK(11, 6)
8580#define B_PATH0_LNA_ERR_G3_A_MSK GENMASK(5, 0)
8581#define R_PATH0_LNA_ERR4 0x4638
8582#define B_PATH0_LNA_ERR_G6_A_MSK GENMASK(29, 24)
8583#define B_PATH0_LNA_ERR_G5_G_MSK GENMASK(17, 12)
8584#define B_PATH0_LNA_ERR_G5_A_MSK GENMASK(11, 6)
8585#define R_PATH0_LNA_ERR5 0x463C
8586#define B_PATH0_LNA_ERR_G6_G_MSK GENMASK(5, 0)
8587#define R_PATH0_TIA_ERR_G0 0x4640
8588#define B_PATH0_TIA_ERR_G0_G_MSK GENMASK(23, 18)
8589#define B_PATH0_TIA_ERR_G0_A_MSK GENMASK(17, 12)
8590#define R_PATH0_TIA_ERR_G1 0x4644
8591#define B_PATH0_TIA_ERR_G1_SEL GENMASK(31, 30)
8592#define B_PATH0_TIA_ERR_G1_G_MSK GENMASK(11, 6)
8593#define B_PATH0_TIA_ERR_G1_A_MSK GENMASK(5, 0)
8594#define R_PATH0_IB_PBK 0x4650
8595#define B_PATH0_IB_PBK_MSK GENMASK(14, 10)
8596#define R_PATH0_RXB_INIT 0x4658
8597#define B_PATH0_RXB_INIT_IDX_MSK GENMASK(9, 5)
8598#define R_PATH0_LNA_INIT 0x4668
8599#define R_PATH0_LNA_INIT_V1 0x472C
8600#define B_PATH0_LNA_INIT_IDX_MSK GENMASK(26, 24)
8601#define R_PATH0_BTG 0x466C
8602#define B_PATH0_BTG_SHEN GENMASK(18, 17)
8603#define R_PATH0_TIA_INIT 0x4674
8604#define B_PATH0_TIA_INIT_IDX_MSK BIT(17)
8605#define R_PATH0_P20_FOLLOW_BY_PAGCUGC 0x46A0
8606#define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1 0x4C24
8607#define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2 0x46E8
8608#define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V3 0x41C8
8609#define B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
8610#define R_PATH0_S20_FOLLOW_BY_PAGCUGC 0x46A4
8611#define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1 0x4C28
8612#define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2 0x46EC
8613#define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V3 0x41CC
8614#define B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
8615#define R_PATH0_RXB_INIT_V1 0x46A8
8616#define B_PATH0_RXB_INIT_IDX_MSK_V1 GENMASK(14, 10)
8617#define R_PATH0_G_LNA6_OP1DB_V1 0x4688
8618#define B_PATH0_G_LNA6_OP1DB_V1 GENMASK(31, 24)
8619#define R_PATH0_G_TIA0_LNA6_OP1DB_V1 0x4694
8620#define B_PATH0_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
8621#define R_PATH0_G_TIA1_LNA6_OP1DB_V1 0x4694
8622#define B_PATH0_R_G_OFST_MASK GENMASK(23, 16)
8623#define B_PATH0_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8)
8624#define R_CDD_EVM_CHK_EN 0x46C0
8625#define B_CDD_EVM_CHK_EN BIT(0)
8626#define R_PATH0_BAND_SEL_V1 0x4738
8627#define B_PATH0_BAND_SEL_MSK_V1 BIT(17)
8628#define B_PATH0_BAND_NRBW_EN_V1 BIT(16)
8629#define R_PATH0_BT_SHARE_V1 0x4738
8630#define B_PATH0_BT_SHARE_V1 BIT(19)
8631#define R_PATH0_BTG_PATH_V1 0x4738
8632#define B_PATH0_BTG_PATH_V1 BIT(22)
8633#define R_P0_NBIIDX 0x469C
8634#define B_P0_NBIIDX_VAL GENMASK(11, 0)
8635#define B_P0_NBIIDX_NOTCH_EN BIT(12)
8636#define R_P0_BACKOFF_IBADC_V1 0x469C
8637#define B_P0_BACKOFF_IBADC_V1 GENMASK(31, 26)
8638#define B_P0_NBIIDX_NOTCH_EN_V1 BIT(12)
8639#define R_P1_MODE 0x4718
8640#define B_P1_MODE_SEL GENMASK(31, 30)
8641#define R_P0_AGC_CTL 0x4730
8642#define B_P0_AGC_EN BIT(31)
8643#define R_PATH1_LNA_INIT 0x473C
8644#define R_PATH1_LNA_INIT_V1 0x4A80
8645#define B_PATH1_LNA_INIT_IDX_MSK GENMASK(26, 24)
8646#define R_PATH0_TIA_INIT_V1 0x473C
8647#define B_PATH0_TIA_INIT_IDX_MSK_V1 BIT(9)
8648#define R_PATH1_TIA_INIT 0x4748
8649#define B_PATH1_TIA_INIT_IDX_MSK BIT(17)
8650#define R_PATH1_BTG 0x4740
8651#define B_PATH1_BTG_SHEN GENMASK(18, 17)
8652#define R_PATH1_RXB_INIT 0x472C
8653#define B_PATH1_RXB_INIT_IDX_MSK GENMASK(9, 5)
8654#define R_PATH1_G_LNA6_OP1DB_V1 0x476C
8655#define B_PATH1_G_LNA6_OP1DB_V1 GENMASK(31, 24)
8656#define R_PATH1_P20_FOLLOW_BY_PAGCUGC 0x4774
8657#define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1 0x4CE8
8658#define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2 0x47A8
8659#define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V3 0x45C8
8660#define B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
8661#define R_PATH1_S20_FOLLOW_BY_PAGCUGC 0x4778
8662#define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1 0x4CEC
8663#define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2 0x47AC
8664#define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V3 0x45CC
8665#define B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
8666#define R_PATH1_G_TIA0_LNA6_OP1DB_V1 0x4778
8667#define B_PATH1_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
8668#define R_PATH1_G_TIA1_LNA6_OP1DB_V1 0x4778
8669#define B_PATH1_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8)
8670#define R_PATH1_BAND_SEL_V1 0x4AA4
8671#define B_PATH1_BAND_SEL_MSK_V1 BIT(17)
8672#define B_PATH1_BAND_NRBW_EN_V1 BIT(16)
8673#define R_PATH1_BT_SHARE_V1 0x4AA4
8674#define B_PATH1_BT_SHARE_V1 BIT(19)
8675#define R_PATH1_BTG_PATH_V1 0x4AA4
8676#define B_PATH1_BTG_PATH_V1 BIT(22)
8677#define R_P1_NBIIDX 0x4770
8678#define B_P1_NBIIDX_VAL GENMASK(11, 0)
8679#define B_P1_NBIIDX_NOTCH_EN BIT(12)
8680#define R_PKT_CTRL 0x47D4
8681#define B_PKT_POP_EN BIT(8)
8682#define R_SEG0R_PD 0x481C
8683#define R_SEG0R_PD_V1 0x4860
8684#define R_SEG0R_PD_V2 0x6A74
8685#define R_SEG0R_EDCCA_LVL 0x4840
8686#define R_SEG0R_EDCCA_LVL_V1 0x4884
8687#define B_EDCCA_LVL_MSK3 GENMASK(31, 24)
8688#define B_EDCCA_LVL_MSK1 GENMASK(15, 8)
8689#define B_EDCCA_LVL_MSK0 GENMASK(7, 0)
8690#define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1 BIT(30)
8691#define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK BIT(29)
8692#define B_SEG0R_PD_LOWER_BOUND_MSK GENMASK(10, 6)
8693#define R_PWOFST 0x488C
8694#define B_PWOFST GENMASK(21, 17)
8695#define R_2P4G_BAND 0x4970
8696#define B_2P4G_BAND_SEL BIT(1)
8697#define R_FC0_BW 0x4974
8698#define R_FC0_BW_V1 0x49C0
8699#define B_FC0_BW_SET GENMASK(31, 30)
8700#define B_ANT_RX_BT_SEG0 GENMASK(25, 22)
8701#define B_ANT_RX_1RCCA_SEG1 GENMASK(21, 18)
8702#define B_ANT_RX_1RCCA_SEG0 GENMASK(17, 14)
8703#define B_FC0_BW_INV GENMASK(6, 0)
8704#define R_Q_MATRIX_00 0x497C
8705#define B_Q_MATRIX_00_IMAGINARY GENMASK(15, 0)
8706#define B_Q_MATRIX_00_REAL GENMASK(31, 16)
8707#define R_CHBW_MOD 0x4978
8708#define R_CHBW_MOD_V1 0x49C4
8709#define B_BT_SHARE BIT(14)
8710#define B_CHBW_MOD_SBW GENMASK(13, 12)
8711#define B_CHBW_MOD_PRICH GENMASK(11, 8)
8712#define B_ANT_RX_SEG0 GENMASK(3, 0)
8713#define R_Q_MATRIX_11 0x4988
8714#define B_Q_MATRIX_11_IMAGINARY GENMASK(15, 0)
8715#define B_Q_MATRIX_11_REAL GENMASK(31, 16)
8716#define R_CUSTOMIZE_Q_MATRIX 0x498C
8717#define B_CUSTOMIZE_Q_MATRIX_EN BIT(0)
8718#define R_P0_RPL1 0x49B0
8719#define B_P0_RPL1_41_MASK GENMASK(31, 24)
8720#define B_P0_RPL1_40_MASK GENMASK(23, 16)
8721#define B_P0_RPL1_20_MASK GENMASK(15, 8)
8722#define B_P0_RPL1_MASK (B_P0_RPL1_41_MASK | B_P0_RPL1_40_MASK | B_P0_RPL1_20_MASK)
8723#define B_P0_RPL1_SHIFT 8
8724#define B_P0_RPL1_BIAS_MASK GENMASK(7, 0)
8725#define R_P0_RPL2 0x49B4
8726#define B_P0_RTL2_8A_MASK GENMASK(31, 24)
8727#define B_P0_RTL2_81_MASK GENMASK(23, 16)
8728#define B_P0_RTL2_80_MASK GENMASK(15, 8)
8729#define B_P0_RTL2_42_MASK GENMASK(7, 0)
8730#define R_P0_RPL3 0x49B8
8731#define B_P0_RTL3_89_MASK GENMASK(31, 24)
8732#define B_P0_RTL3_84_MASK GENMASK(23, 16)
8733#define B_P0_RTL3_83_MASK GENMASK(15, 8)
8734#define B_P0_RTL3_82_MASK GENMASK(7, 0)
8735#define R_PD_BOOST_EN 0x49E8
8736#define B_PD_BOOST_EN BIT(7)
8737#define R_P1_BACKOFF_IBADC_V1 0x49F0
8738#define B_P1_BACKOFF_IBADC_V1 GENMASK(31, 26)
8739#define R_P1_RPL1 0x4A00
8740#define R_P1_RPL2 0x4A04
8741#define R_P1_RPL3 0x4A08
8742#define R_BK_FC0_INV_V1 0x4A1C
8743#define B_BK_FC0_INV_MSK_V1 GENMASK(18, 0)
8744#define R_CCK_FC0_INV_V1 0x4A20
8745#define B_CCK_FC0_INV_MSK_V1 GENMASK(18, 0)
8746#define R_PATH1_RXB_INIT_V1 0x4A5C
8747#define B_PATH1_RXB_INIT_IDX_MSK_V1 GENMASK(14, 10)
8748#define R_P1_AGC_CTL 0x4A9C
8749#define B_P1_AGC_EN BIT(31)
8750#define R_PATH1_TIA_INIT_V1 0x4AA8
8751#define B_PATH1_TIA_INIT_IDX_MSK_V1 BIT(9)
8752#define R_P0_AGC_RSVD 0x4ACC
8753#define R_PATH0_RXBB_V1 0x4AD4
8754#define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0)
8755#define R_P1_AGC_RSVD 0x4AD8
8756#define R_PATH1_RXBB_V1 0x4AE0
8757#define B_PATH1_RXBB_MSK_V1 GENMASK(31, 0)
8758#define R_PATH0_BT_BACKOFF_V1 0x4AE4
8759#define B_PATH0_BT_BACKOFF_V1 GENMASK(23, 0)
8760#define R_PATH1_BT_BACKOFF_V1 0x4AEC
8761#define B_PATH1_BT_BACKOFF_V1 GENMASK(23, 0)
8762#define R_DCFO_COMP_S0_V2 0x4B20
8763#define B_DCFO_COMP_S0_MSK_V2 GENMASK(13, 0)
8764#define R_PATH0_TX_CFR 0x4B30
8765#define B_PATH0_TX_CFR_LGC1 GENMASK(19, 10)
8766#define B_PATH0_TX_CFR_LGC0 GENMASK(9, 0)
8767#define R_PATH0_TX_POLAR_CLIPPING 0x4B3C
8768#define B_PATH0_TX_POLAR_CLIPPING_LGC1 GENMASK(19, 16)
8769#define B_PATH0_TX_POLAR_CLIPPING_LGC0 GENMASK(15, 12)
8770#define R_PATH0_FRC_FIR_TYPE_V1 0x4C00
8771#define B_PATH0_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)
8772#define R_PATH0_NOTCH 0x4C14
8773#define B_PATH0_NOTCH_EN BIT(12)
8774#define B_PATH0_NOTCH_VAL GENMASK(11, 0)
8775#define R_PATH0_NOTCH2 0x4C20
8776#define B_PATH0_NOTCH2_EN BIT(12)
8777#define B_PATH0_NOTCH2_VAL GENMASK(11, 0)
8778#define R_PATH0_5MDET 0x4C4C
8779#define R_PATH0_5MDET_V1 0x46F8
8780#define B_PATH0_5MDET_EN BIT(12)
8781#define B_PATH0_5MDET_SB2 BIT(8)
8782#define B_PATH0_5MDET_SB0 BIT(6)
8783#define B_PATH0_5MDET_TH GENMASK(5, 0)
8784#define R_PATH1_FRC_FIR_TYPE_V1 0x4CC4
8785#define B_PATH1_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)
8786#define R_PATH1_NOTCH 0x4CD8
8787#define B_PATH1_NOTCH_EN BIT(12)
8788#define B_PATH1_NOTCH_VAL GENMASK(11, 0)
8789#define R_PATH1_NOTCH2 0x4CE4
8790#define B_PATH1_NOTCH2_EN BIT(12)
8791#define B_PATH1_NOTCH2_VAL GENMASK(11, 0)
8792#define R_PATH1_5MDET 0x4D10
8793#define R_PATH1_5MDET_V1 0x47B8
8794#define B_PATH1_5MDET_EN BIT(12)
8795#define B_PATH1_5MDET_SB2 BIT(8)
8796#define B_PATH1_5MDET_SB0 BIT(6)
8797#define B_PATH1_5MDET_TH GENMASK(5, 0)
8798#define R_S0S1_CSI_WGT 0x4D34
8799#define B_S0S1_CSI_WGT_EN BIT(0)
8800#define B_S0S1_CSI_WGT_TONE_IDX GENMASK(31, 20)
8801#define R_CHINFO_ELM_SRC 0x4D84
8802#define B_CHINFO_ELM_BITMAP GENMASK(22, 0)
8803#define B_CHINFO_SRC GENMASK(31, 30)
8804#define R_CHINFO_TYPE_SCAL 0x4D88
8805#define B_CHINFO_TYPE GENMASK(2, 1)
8806#define B_CHINFO_SCAL BIT(8)
8807#define R_RPL_BIAS_COMP 0x4DF0
8808#define B_RPL_BIAS_COMP_MASK GENMASK(7, 0)
8809#define R_RPL_PATHAB 0x4E0C
8810#define B_RPL_PATHB_MASK GENMASK(23, 16)
8811#define B_RPL_PATHA_MASK GENMASK(15, 8)
8812#define R_RSSI_M_PATHAB 0x4E2C
8813#define B_RSSI_M_PATHB_MASK GENMASK(15, 8)
8814#define B_RSSI_M_PATHA_MASK GENMASK(7, 0)
8815#define R_FC0_V1 0x4E30
8816#define B_FC0_MSK_V1 GENMASK(12, 0)
8817#define R_RX_BW40_2XFFT_EN_V1 0x4E30
8818#define B_RX_BW40_2XFFT_EN_MSK_V1 BIT(26)
8819#define R_DCFO_COMP_S0_V1 0x4A40
8820#define B_DCFO_COMP_S0_V1_MSK GENMASK(13, 0)
8821#define R_BMODE_PDTH_V1 0x4B64
8822#define R_BMODE_PDTH_V2 0x6708
8823#define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24)
8824#define R_BMODE_PDTH_EN_V1 0x4B74
8825#define R_BMODE_PDTH_EN_V2 0x6718
8826#define B_BMODE_PDTH_LIMIT_EN_MSK_V1 BIT(30)
8827#define R_BSS_CLR_VLD_V2 0x4EBC
8828#define B_BSS_CLR_VLD0_V2 BIT(2)
8829#define R_CFO_COMP_SEG1_L 0x5384
8830#define R_CFO_COMP_SEG1_H 0x5388
8831#define R_CFO_COMP_SEG1_CTRL 0x538C
8832#define B_CFO_COMP_VALID_BIT BIT(29)
8833#define B_CFO_COMP_WEIGHT_MSK GENMASK(27, 24)
8834#define B_CFO_COMP_VAL_MSK GENMASK(11, 0)
8835#define R_TSSI_PA_K1 0x5600
8836#define R_TSSI_PA_K2 0x5604
8837#define R_P0_TSSI_ALIM1 0x5630
8838#define B_P0_TSSI_ALIM1 GENMASK(29, 0)
8839#define B_P0_TSSI_ALIM11 GENMASK(29, 20)
8840#define B_P0_TSSI_ALIM12 GENMASK(19, 10)
8841#define B_P0_TSSI_ALIM13 GENMASK(9, 0)
8842#define R_P0_TSSI_ALIM3 0x5634
8843#define B_P0_TSSI_ALIM31 GENMASK(9, 0)
8844#define R_TSSI_PA_K5 0x5638
8845#define R_P0_TSSI_ALIM2 0x563c
8846#define B_P0_TSSI_ALIM2 GENMASK(29, 0)
8847#define R_P0_TSSI_ALIM4 0x5640
8848#define R_TSSI_PA_K8 0x5644
8849#define R_P0_TSSI_ADC_CLK 0x566c
8850#define B_P0_TSSI_ADC_CLK GENMASK(17, 16)
8851#define R_UPD_CLK 0x5670
8852#define B_DAC_VAL BIT(31)
8853#define B_ACK_VAL GENMASK(30, 29)
8854#define B_DPD_DIS BIT(14)
8855#define B_DPD_GDIS BIT(13)
8856#define B_IQK_RFC_ON BIT(1)
8857#define R_TXPWRB 0x56CC
8858#define R_P1_TXPWRB 0x76CC
8859#define B_TXPWRB_ON BIT(28)
8860#define B_TXPWRB_VAL GENMASK(27, 19)
8861#define B_TXPWRB_MAX GENMASK(8, 0)
8862#define R_DPD_OFT_EN 0x5800
8863#define B_DPD_OFT_EN BIT(28)
8864#define B_DPD_TSSI_CW GENMASK(26, 18)
8865#define B_DPD_PWR_CW GENMASK(17, 9)
8866#define B_DPD_REF GENMASK(8, 0)
8867#define R_P0_TSSIC 0x5814
8868#define B_P0_TSSIC_BYPASS BIT(11)
8869#define R_DPD_OFT_ADDR 0x5804
8870#define B_DPD_OFT_ADDR GENMASK(31, 27)
8871#define R_TXPWRB_H 0x580c
8872#define B_TXPWRB_RDY BIT(15)
8873#define R_P0_TMETER 0x5810
8874#define B_P0_TMETER GENMASK(15, 10)
8875#define B_P0_TMETER_DIS BIT(16)
8876#define B_P0_TMETER_TRK BIT(24)
8877#define R_P0_ADCFF_EN 0x58C8
8878#define B_P0_ADCFF_EN BIT(24)
8879#define R_P1_TSSIC 0x7814
8880#define B_P1_TSSIC_BYPASS BIT(11)
8881#define R_P0_TSSI_TRK 0x5818
8882#define B_P0_TSSI_TRK_EN BIT(30)
8883#define B_P0_TSSI_RFC GENMASK(28, 27)
8884#define B_P0_TSSI_OFT_EN BIT(28)
8885#define B_P0_TSSI_OFT GENMASK(7, 0)
8886#define R_P0_TSSI_SLOPE_CAL 0x581c
8887#define B_P0_TSSI_SLOPE_CAL_EN BIT(20)
8888#define R_P0_TSSI_AVG 0x5820
8889#define B_P0_TSSI_EN BIT(31)
8890#define B_P0_TSSI_AVG GENMASK(15, 12)
8891#define R_P0_RFCTM 0x5864
8892#define B_P0_CLKG_FORCE GENMASK(31, 30)
8893#define B_P0_RFCTM_EN BIT(29)
8894#define B_P0_GOT_TXRX GENMASK(28, 27)
8895#define B_P0_RFCTM_VAL GENMASK(25, 20)
8896#define R_P0_RFCTM_RDY BIT(26)
8897#define R_P0_TRSW 0x5868
8898#define B_P0_BT_FORCE_ANTIDX_EN BIT(12)
8899#define B_P0_TRSW_X BIT(2)
8900#define B_P0_TRSW_A BIT(1)
8901#define B_P0_TX_ANT_SEL BIT(1)
8902#define B_P0_TRSW_B BIT(0)
8903#define B_P0_ANT_TRAIN_EN BIT(0)
8904#define B_P0_TRSW_SO_A2 GENMASK(7, 5)
8905#define R_P0_ANTSEL 0x586C
8906#define B_P0_ANTSEL_SW_5G BIT(25)
8907#define B_P0_ANTSEL_SW_2G BIT(23)
8908#define B_P0_ANTSEL_BTG_TRX BIT(21)
8909#define B_P0_ANTSEL_CGCS_CTRL BIT(17)
8910#define B_P0_ANTSEL_HW_CTRL BIT(16)
8911#define B_P0_ANTSEL_TX_ORI GENMASK(15, 12)
8912#define B_P0_ANTSEL_RX_ALT GENMASK(11, 8)
8913#define B_P0_ANTSEL_RX_ORI GENMASK(7, 4)
8914#define R_RFSW_CTRL_ANT0_BASE 0x5870
8915#define B_RFSW_CTRL_ANT_MAPPING GENMASK(15, 0)
8916#define R_RFE_SEL0_BASE 0x5880
8917#define B_RFE_SEL0_SRC_MASK GENMASK(3, 0)
8918#define R_RFE_SEL32_BASE 0x5884
8919#define RFE_SEL0_SRC_ANTSEL_0 8
8920#define R_RFE_INV0 0x5890
8921#define R_P0_RFM 0x5894
8922#define B_P0_RFM_DIS_WL BIT(7)
8923#define B_P0_RFM_TX_OPT BIT(6)
8924#define B_P0_RFM_BT_EN BIT(5)
8925#define B_P0_RFM_OUT GENMASK(4, 0)
8926#define R_P0_PATH_RST 0x58AC
8927#define B_P0_PATH_RST BIT(27)
8928#define R_P0_TXDPD 0x58D4
8929#define B_P0_TXDPD GENMASK(31, 28)
8930#define R_P0_TXPW_RSTB 0x58DC
8931#define B_P0_TXPW_RSTB_MANON BIT(30)
8932#define B_P0_TXPW_RSTB_TSSI BIT(31)
8933#define R_P0_TSSI_MV_AVG 0x58E4
8934#define B_P0_TXPW_RSTB GENMASK(28, 27)
8935#define B_P0_TSSI_MV_MIX GENMASK(19, 11)
8936#define B_P0_TSSI_MV_AVG GENMASK(13, 11)
8937#define B_P0_TSSI_MV_CLR BIT(14)
8938#define R_TXGAIN_SCALE 0x58F0
8939#define B_TXGAIN_SCALE_EN BIT(19)
8940#define B_TXGAIN_SCALE_OFT GENMASK(31, 24)
8941#define R_P0_DAC_COMP_POST_DPD_EN 0x58F8
8942#define B_P0_DAC_COMP_POST_DPD_EN BIT(31)
8943#define R_P0_TSSI_BASE 0x5C00
8944#define R_S0_DACKI 0x5E00
8945#define B_S0_DACKI_AR GENMASK(31, 28)
8946#define B_S0_DACKI_EN BIT(3)
8947#define R_S0_DACKI2 0x5E30
8948#define B_S0_DACKI2_K GENMASK(21, 12)
8949#define R_S0_DACKI7 0x5E44
8950#define B_S0_DACKI7_K GENMASK(15, 8)
8951#define R_S0_DACKI8 0x5E48
8952#define B_S0_DACKI8_K GENMASK(15, 8)
8953#define R_S0_DACKQ 0x5E50
8954#define B_S0_DACKQ_AR GENMASK(31, 28)
8955#define B_S0_DACKQ_EN BIT(3)
8956#define R_S0_DACKQ2 0x5E80
8957#define B_S0_DACKQ2_K GENMASK(21, 12)
8958#define R_S0_DACKQ7 0x5E94
8959#define B_S0_DACKQ7_K GENMASK(15, 8)
8960#define R_S0_DACKQ8 0x5E98
8961#define B_S0_DACKQ8_K GENMASK(15, 8)
8962#define R_DCFO_WEIGHT_V1 0x6244
8963#define B_DCFO_WEIGHT_MSK_V1 GENMASK(31, 28)
8964#define R_DAC_CLK 0x625C
8965#define B_DAC_CLK GENMASK(31, 30)
8966#define R_DCFO_OPT_V1 0x6260
8967#define B_DCFO_OPT_EN_V1 BIT(17)
8968#define R_TXFCTR 0x627C
8969#define B_TXFCTR_THD GENMASK(19, 10)
8970#define R_TXSCALE 0x6284
8971#define B_TXFCTR_EN BIT(19)
8972#define R_PCOEFF01 0x6684
8973#define B_PCOEFF01 GENMASK(23, 0)
8974#define R_PCOEFF23 0x6688
8975#define B_PCOEFF23 GENMASK(23, 0)
8976#define R_PCOEFF45 0x668c
8977#define B_PCOEFF45 GENMASK(23, 0)
8978#define R_PCOEFF67 0x6690
8979#define B_PCOEFF67 GENMASK(23, 0)
8980#define R_PCOEFF89 0x6694
8981#define B_PCOEFF89 GENMASK(23, 0)
8982#define R_PCOEFFAB 0x6698
8983#define B_PCOEFFAB GENMASK(23, 0)
8984#define R_PCOEFFCD 0x669c
8985#define B_PCOEFFCD GENMASK(23, 0)
8986#define R_PCOEFFEF 0x66a0
8987#define B_PCOEFFEF GENMASK(23, 0)
8988#define R_MGAIN_BIAS 0x672c
8989#define B_MGAIN_BIAS_BW20 GENMASK(3, 0)
8990#define B_MGAIN_BIAS_BW40 GENMASK(7, 4)
8991#define R_CCK_RPL_OFST 0x6750
8992#define B_CCK_RPL_OFST GENMASK(7, 0)
8993#define R_BK_FC0INV 0x6758
8994#define B_BK_FC0INV GENMASK(18, 0)
8995#define R_CCK_FC0INV 0x675c
8996#define B_CCK_FC0INV GENMASK(18, 0)
8997#define R_SEG0R_EDCCA_LVL_BE 0x69EC
8998#define R_SEG0R_PPDU_LVL_BE 0x69F0
8999#define R_SEGSND 0x6A14
9000#define B_SEGSND_EN BIT(31)
9001#define R_DBCC 0x6B48
9002#define B_DBCC_EN BIT(0)
9003#define R_FC0 0x6B4C
9004#define B_BW40_2XFFT BIT(31)
9005#define B_FC0 GENMASK(12, 0)
9006#define R_FC0INV_SBW 0x6B50
9007#define B_SMALLBW GENMASK(31, 30)
9008#define B_RX_BT_SG0 GENMASK(25, 22)
9009#define B_RX_1RCCA GENMASK(17, 14)
9010#define B_FC0_INV GENMASK(6, 0)
9011#define R_ANT_CHBW 0x6B54
9012#define B_ANT_BT_SHARE BIT(16)
9013#define B_CHBW_BW GENMASK(14, 12)
9014#define B_CHBW_PRICH GENMASK(11, 8)
9015#define B_ANT_RX_SG0 GENMASK(3, 0)
9016#define R_SLOPE 0x6B6C
9017#define B_EHT_RATE_TH GENMASK(31, 28)
9018#define B_SLOPE_B GENMASK(27, 14)
9019#define B_SLOPE_A GENMASK(13, 0)
9020#define R_SC_CORNER 0x6B70
9021#define B_SC_CORNER GENMASK(10, 0)
9022#define R_MAG_A 0x6BF4
9023#define B_MGA_AEND GENMASK(31, 24)
9024#define R_MAG_AB 0x6BF8
9025#define B_BY_SLOPE GENMASK(31, 24)
9026#define B_MAG_AB GENMASK(23, 0)
9027#define R_BEDGE 0x6BFC
9028#define B_EHT_MCS14 BIT(31)
9029#define B_HE_RATE_TH GENMASK(30, 27)
9030#define R_BEDGE2 0x6C00
9031#define B_EHT_MCS15 BIT(31)
9032#define B_HT_VHT_TH GENMASK(11, 0)
9033#define R_BEDGE3 0x6C04
9034#define B_TB_EN BIT(23)
9035#define B_HEMU_EN BIT(21)
9036#define B_HEERSU_EN BIT(19)
9037#define B_EHTTB_EN BIT(15)
9038#define B_BEDGE_CFG GENMASK(1, 0)
9039#define R_SU_PUNC 0x6C08
9040#define B_SU_PUNC_EN BIT(1)
9041#define R_BEDGE5 0x6C10
9042#define B_HWGEN_EN BIT(25)
9043#define B_PWROFST_COMP BIT(20)
9044#define R_RPL_BIAS_COMP1 0x6DF0
9045#define B_RPL_BIAS_COMP1_MASK GENMASK(7, 0)
9046#define R_DBCC_FA 0x703C
9047#define B_DBCC_FA BIT(12)
9048#define R_P1_TSSI_ALIM1 0x7630
9049#define B_P1_TSSI_ALIM1 GENMASK(29, 0)
9050#define B_P1_TSSI_ALIM11 GENMASK(29, 20)
9051#define B_P1_TSSI_ALIM12 GENMASK(19, 10)
9052#define B_P1_TSSI_ALIM13 GENMASK(9, 0)
9053#define R_P1_TSSI_ALIM3 0x7634
9054#define B_P1_TSSI_ALIM31 GENMASK(9, 0)
9055#define R_P1_TSSI_ALIM2 0x763c
9056#define B_P1_TSSI_ALIM2 GENMASK(29, 0)
9057#define R_P1_TSSI_ADC_CLK 0x766c
9058#define B_P1_TSSI_ADC_CLK GENMASK(17, 16)
9059#define R_P1_TXAGC_TH 0x7800
9060#define B_P1_TXAGC_MAXMIN GENMASK(15, 0)
9061#define R_P1_TXPW_FORCE 0x780C
9062#define B_P1_TXPW_RDY BIT(15)
9063#define R_P1_TSSIC 0x7814
9064#define B_P1_TSSIC_BYPASS BIT(11)
9065#define R_P1_TMETER 0x7810
9066#define B_P1_TMETER GENMASK(15, 10)
9067#define B_P1_TMETER_DIS BIT(16)
9068#define B_P1_TMETER_TRK BIT(24)
9069#define R_P1_TSSI_TRK 0x7818
9070#define B_P1_TSSI_TRK_EN BIT(30)
9071#define B_P1_TSSI_RFC GENMASK(28, 27)
9072#define B_P1_TSSI_OFT_EN BIT(28)
9073#define B_P1_TSSI_OFT GENMASK(7, 0)
9074#define R_P1_TSSI_AVG 0x7820
9075#define B_P1_TSSI_EN BIT(31)
9076#define B_P1_TSSI_AVG GENMASK(15, 12)
9077#define R_P1_RFCTM 0x7864
9078#define B_P1_CLKG_FORCE GENMASK(31, 30)
9079#define B_P1_GOT_TXRX GENMASK(28, 27)
9080#define R_P1_RFCTM_RDY BIT(26)
9081#define B_P1_RFCTM_VAL GENMASK(25, 20)
9082#define B_P1_RFCTM_DEL GENMASK(19, 11)
9083#define R_P1_PATH_RST 0x78AC
9084#define B_P1_PATH_RST BIT(27)
9085#define R_P1_ADCFF_EN 0x78C8
9086#define B_P1_ADCFF_EN BIT(24)
9087#define R_P1_TXPW_RSTB 0x78DC
9088#define B_P1_TXPW_RSTB_MANON BIT(30)
9089#define B_P1_TXPW_RSTB_TSSI BIT(31)
9090#define R_P1_TSSI_MV_AVG 0x78E4
9091#define B_P1_TXPW_RSTB GENMASK(28, 27)
9092#define B_P1_TSSI_MV_MIX GENMASK(19, 11)
9093#define B_P1_TSSI_MV_AVG GENMASK(13, 11)
9094#define B_P1_TSSI_MV_CLR BIT(14)
9095#define R_P1_DAC_COMP_POST_DPD_EN 0x78F8
9096#define B_P1_DAC_COMP_POST_DPD_EN BIT(31)
9097#define R_TSSI_THOF 0x7C00
9098#define R_S1_DACKI 0x7E00
9099#define B_S1_DACKI_AR GENMASK(31, 28)
9100#define B_S1_DACKI_EN BIT(3)
9101#define R_S1_DACKI2 0x7E30
9102#define B_S1_DACKI2_K GENMASK(21, 12)
9103#define R_S1_DACKI7 0x7E44
9104#define B_S1_DACKI_K GENMASK(15, 8)
9105#define R_S1_DACKI8 0x7E48
9106#define B_S1_DACKI8_K GENMASK(15, 8)
9107#define R_S1_DACKQ 0x7E50
9108#define B_S1_DACKQ_AR GENMASK(31, 28)
9109#define B_S1_DACKQ_EN BIT(3)
9110#define R_S1_DACKQ2 0x7E80
9111#define B_S1_DACKQ2_K GENMASK(21, 12)
9112#define R_S1_DACKQ7 0x7E94
9113#define B_S1_DACKQ7_K GENMASK(15, 8)
9114#define R_S1_DACKQ8 0x7E98
9115#define B_S1_DACKQ8_K GENMASK(15, 8)
9116#define R_NCTL_CFG 0x8000
9117#define B_NCTL_CFG_SPAGE GENMASK(2, 1)
9118#define R_NCTL_RPT 0x8008
9119#define B_NCTL_RPT_FLG BIT(26)
9120#define R_NCTL_N1 0x8010
9121#define B_NCTL_N1_CIP GENMASK(7, 0)
9122#define R_NCTL_N2 0x8014
9123#define R_IQK_COM 0x8018
9124#define R_IQK_DIF 0x801C
9125#define B_IQK_DIF_TRX GENMASK(1, 0)
9126#define R_IQK_DIF1 0x8020
9127#define B_IQK_DIF1_TXPI GENMASK(19, 0)
9128#define R_IQK_DIF2 0x8024
9129#define B_IQK_DIF2_RXPI GENMASK(19, 0)
9130#define R_IQK_DIF4 0x802C
9131#define B_IQK_DIF4_RXT GENMASK(27, 16)
9132#define B_IQK_DIF4_TXT GENMASK(11, 0)
9133#define IQK_DF4_TXT_8_25MHZ 0x021
9134#define R_IQK_CFG 0x8034
9135#define B_IQK_CFG_SET GENMASK(5, 4)
9136#define R_IQK_RXA 0x8044
9137#define B_IQK_RXAGC GENMASK(15, 13)
9138#define R_TPG_SEL 0x8068
9139#define R_TPG_MOD 0x806C
9140#define B_TPG_MOD_F GENMASK(2, 1)
9141#define R_MDPK_SYNC 0x8070
9142#define B_MDPK_SYNC_SEL BIT(31)
9143#define B_MDPK_SYNC_MAN GENMASK(31, 28)
9144#define B_MDPK_SYNC_DMAN GENMASK(30, 28)
9145#define R_MDPK_RX_DCK 0x8074
9146#define B_MDPK_RX_DCK_EN BIT(31)
9147#define R_KIP_MOD 0x8078
9148#define B_KIP_MOD GENMASK(19, 0)
9149#define R_NCTL_RW 0x8080
9150#define R_KIP_SYSCFG 0x8088
9151#define R_KIP_CLK 0x808C
9152#define R_DPK_IDL 0x809C
9153#define B_DPK_IDL_SEL GENMASK(10, 9)
9154#define B_DPK_IDL BIT(8)
9155#define R_LDL_NORM 0x80A0
9156#define B_LDL_NORM_MA BIT(16)
9157#define B_LDL_NORM_PN GENMASK(12, 8)
9158#define B_LDL_NORM_OP GENMASK(1, 0)
9159#define R_DPK_CTL 0x80B0
9160#define B_DPK_CTL_EN BIT(28)
9161#define R_DPK_CFG 0x80B8
9162#define B_DPK_CFG_IDX GENMASK(14, 12)
9163#define R_DPK_CFG2 0x80BC
9164#define B_DPK_CFG2_ST BIT(14)
9165#define R_DPK_CFG3 0x80C0
9166#define R_KPATH_CFG 0x80D0
9167#define B_KPATH_CFG_ED GENMASK(21, 20)
9168#define R_KIP_RPT1 0x80D4
9169#define B_KIP_RPT1_SEL GENMASK(21, 16)
9170#define B_KIP_RPT1_SEL_V1 GENMASK(19, 16)
9171#define R_SRAM_IQRX 0x80D8
9172#define R_IDL_MPA 0x80DC
9173#define B_IDL_DN BIT(31)
9174#define B_IDL_MD530 BIT(1)
9175#define B_IDL_MD500 BIT(0)
9176#define R_GAPK 0x80E0
9177#define B_GAPK_ADR BIT(0)
9178#define R_SRAM_IQRX2 0x80E8
9179#define R_DPK_MPA 0x80EC
9180#define B_DPK_MPA_T0 BIT(10)
9181#define B_DPK_MPA_T1 BIT(9)
9182#define B_DPK_MPA_T2 BIT(8)
9183#define R_DPK_WR 0x80F4
9184#define B_DPK_WR_ST BIT(29)
9185#define R_DPK_TRK 0x80f0
9186#define B_DPK_TRK_DIS BIT(31)
9187#define R_RPT_COM 0x80FC
9188#define B_PRT_COM_SYNERR BIT(30)
9189#define B_PRT_COM_DCI GENMASK(27, 16)
9190#define B_PRT_COM_CORV GENMASK(15, 8)
9191#define B_RPT_COM_RDY GENMASK(15, 0)
9192#define B_PRT_COM_DCQ GENMASK(11, 0)
9193#define B_PRT_COM_RXOV BIT(8)
9194#define B_PRT_COM_GL GENMASK(7, 4)
9195#define B_PRT_COM_CORI GENMASK(7, 0)
9196#define B_PRT_COM_RXBB GENMASK(5, 0)
9197#define B_PRT_COM_RXBB_V1 GENMASK(4, 0)
9198#define B_PRT_COM_DONE BIT(0)
9199#define R_COEF_SEL 0x8104
9200#define R_COEF_SEL_C1 0x8204
9201#define B_COEF_SEL_IQC BIT(0)
9202#define B_COEF_SEL_IQC_V1 GENMASK(1, 0)
9203#define B_COEF_SEL_MDPD BIT(8)
9204#define B_COEF_SEL_MDPD_V1 GENMASK(9, 8)
9205#define B_COEF_SEL_EN BIT(31)
9206#define R_CFIR_COEF 0x810c
9207#define R_CFIR_SYS 0x8120
9208#define R_IQK_RES 0x8124
9209#define B_IQK_RES_K BIT(28)
9210#define B_IQK_RES_TXCFIR GENMASK(11, 8)
9211#define B_IQK_RES_RXCFIR GENMASK(3, 0)
9212#define R_TXIQC 0x8138
9213#define R_RXIQC 0x813c
9214#define B_RXIQC_BYPASS BIT(0)
9215#define B_RXIQC_BYPASS2 BIT(2)
9216#define B_RXIQC_NEWP GENMASK(19, 8)
9217#define B_RXIQC_NEWX GENMASK(31, 20)
9218#define R_KIP 0x8140
9219#define B_KIP_DBCC BIT(0)
9220#define B_KIP_RFGAIN BIT(8)
9221#define R_RFGAIN 0x8144
9222#define B_RFGAIN_PAD GENMASK(4, 0)
9223#define B_RFGAIN_TXBB GENMASK(12, 8)
9224#define R_RFGAIN_BND 0x8148
9225#define B_RFGAIN_BND GENMASK(4, 0)
9226#define R_CFIR_MAP 0x8150
9227#define R_CFIR_LUT 0x8154
9228#define R_CFIR_LUT_C1 0x8254
9229#define B_CFIR_LUT_SEL BIT(8)
9230#define B_CFIR_LUT_SET BIT(4)
9231#define B_CFIR_LUT_G5 BIT(5)
9232#define B_CFIR_LUT_G3 BIT(3)
9233#define B_CFIR_LUT_G2 BIT(2)
9234#define B_CFIR_LUT_GP_V1 GENMASK(2, 0)
9235#define B_CFIR_LUT_GP GENMASK(1, 0)
9236#define R_DPK_GN 0x819C
9237#define B_DPK_GN_EN GENMASK(17, 16)
9238#define B_DPK_GN_AG GENMASK(9, 0)
9239#define R_DPD_V1 0x81a0
9240#define B_DPD_LBK BIT(7)
9241#define R_DPD_CH0 0x81AC
9242#define R_DPD_BND 0x81B4
9243#define B_DPD_BND_1 GENMASK(24, 16)
9244#define B_DPD_BND_0 GENMASK(8, 0)
9245#define R_DPD_CH0A 0x81BC
9246#define B_DPD_MEN GENMASK(31, 28)
9247#define B_DPD_ORDER GENMASK(26, 24)
9248#define B_DPD_ORDER_V1 GENMASK(26, 25)
9249#define B_DPD_CFG GENMASK(22, 0)
9250#define B_DPD_SEL GENMASK(13, 8)
9251#define R_TXAGC_RFK 0x81C4
9252#define B_TXAGC_RFK_CH0 GENMASK(5, 0)
9253#define R_DPD_COM 0x81C8
9254#define B_DPD_COM_OF BIT(15)
9255#define R_KIP_IQP 0x81CC
9256#define B_KIP_IQP_SW GENMASK(13, 12)
9257#define B_KIP_IQP_IQSW GENMASK(5, 0)
9258#define R_KIP_RPT 0x81D4
9259#define B_KIP_RPT_SEL GENMASK(21, 16)
9260#define R_W_COEF 0x81D8
9261#define R_LOAD_COEF 0x81DC
9262#define B_LOAD_COEF_MDPD BIT(16)
9263#define B_LOAD_COEF_CFIR GENMASK(1, 0)
9264#define B_LOAD_COEF_DI BIT(1)
9265#define B_LOAD_COEF_AUTO BIT(0)
9266#define R_DPK_GL 0x81F0
9267#define B_DPK_GL_A0 GENMASK(31, 28)
9268#define B_DPK_GL_A1 GENMASK(17, 0)
9269#define R_RPT_PER 0x81FC
9270#define B_RPT_PER_KSET GENMASK(31, 29)
9271#define B_RPT_PER_TSSI GENMASK(28, 16)
9272#define B_RPT_PER_OF GENMASK(15, 8)
9273#define B_RPT_PER_TH GENMASK(5, 0)
9274#define R_IQRSN 0x8220
9275#define B_IQRSN_K1 BIT(28)
9276#define B_IQRSN_K2 BIT(16)
9277#define R_DPD_CH0B 0x82BC
9278#define R_RXCFIR_P0C0 0x8D40
9279#define R_RXCFIR_P0C1 0x8D84
9280#define R_RXCFIR_P0C2 0x8DC8
9281#define R_RXCFIR_P0C3 0x8E0C
9282#define R_TXCFIR_P0C0 0x8F50
9283#define R_TXCFIR_P0C1 0x8F84
9284#define R_TXCFIR_P0C2 0x8FB8
9285#define R_TXCFIR_P0C3 0x8FEC
9286#define R_RXCFIR_P1C0 0x9140
9287#define R_RXCFIR_P1C1 0x9184
9288#define R_RXCFIR_P1C2 0x91C8
9289#define R_RXCFIR_P1C3 0x920C
9290#define R_TXCFIR_P1C0 0x9350
9291#define R_TXCFIR_P1C1 0x9384
9292#define R_TXCFIR_P1C2 0x93B8
9293#define R_TXCFIR_P1C3 0x93EC
9294#define R_IQKINF 0x9FE0
9295#define B_IQKINF_VER GENMASK(31, 24)
9296#define B_IQKINF_FAIL_RXGRP GENMASK(23, 16)
9297#define B_IQKINF_FAIL_TXGRP GENMASK(15, 8)
9298#define B_IQKINF_FAIL GENMASK(3, 0)
9299#define B_IQKINF_F_RX BIT(3)
9300#define B_IQKINF_FTX BIT(2)
9301#define B_IQKINF_FFIN BIT(1)
9302#define B_IQKINF_FCOR BIT(0)
9303#define R_IQKCH 0x9FE4
9304#define B_IQKCH_CH GENMASK(15, 8)
9305#define B_IQKCH_BW GENMASK(7, 4)
9306#define B_IQKCH_BAND GENMASK(3, 0)
9307#define R_IQKINF2 0x9FE8
9308#define B_IQKINF2_FCNT GENMASK(23, 16)
9309#define B_IQKINF2_KCNT GENMASK(15, 8)
9310#define B_IQKINF2_NCTLV GENMASK(7, 0)
9311#define R_TXAGC_REF_DBM_RF1_P0 0xBC04
9312#define B_TXAGC_OFDM_REF_DBM_RF1_P0 GENMASK(10, 2)
9313#define B_TXAGC_CCK_REF_DBM_RF1_P0 GENMASK(19, 11)
9314#define R_TSSI_K_RF1_P0 0xBC28
9315#define B_TSSI_K_OFDM_RF1_P0 GENMASK(9, 0)
9316#define R_TXAGC_REF_DBM_RF1_P1 0xBD04
9317#define B_TXAGC_OFDM_REF_DBM_RF1_P1 GENMASK(10, 2)
9318#define B_TXAGC_CCK_REF_DBM_RF1_P1 GENMASK(19, 11)
9319#define R_TSSI_K_RF1_P1 0xBD28
9320#define B_TSSI_K_OFDM_RF1_P1 GENMASK(9, 0)
9321#define R_RFK_ST 0xBFF8
9322#define R_DCOF0 0xC000
9323#define B_DCOF0_RST BIT(17)
9324#define B_DCOF0_V GENMASK(4, 1)
9325#define R_DCOF1 0xC004
9326#define B_DCOF1_VAL GENMASK(31, 20)
9327#define B_DCOF1_RST BIT(17)
9328#define B_DCOF1_S BIT(0)
9329#define R_DCOF8 0xC020
9330#define B_DCOF8_V GENMASK(4, 1)
9331#define R_DCOF9 0xC024
9332#define B_DCOF9_VAL GENMASK(31, 20)
9333#define B_DCOF9_RST BIT(17)
9334#define R_DACK_S0P0 0xC040
9335#define B_DACK_S0P0_OK BIT(31)
9336#define R_DACK_BIAS00 0xc048
9337#define B_DACK_BIAS00 GENMASK(11, 2)
9338#define R_DACK_S0P2 0xC05C
9339#define B_DACK_S0M0 GENMASK(31, 24)
9340#define B_DACK_S0P2_OK BIT(2)
9341#define R_DACK_DADCK00 0xC060
9342#define B_DACK_DADCK00 GENMASK(31, 24)
9343#define R_DACK_S0P1 0xC064
9344#define B_DACK_S0P1_OK BIT(31)
9345#define R_DACK_BIAS01 0xC06C
9346#define B_DACK_BIAS01 GENMASK(11, 2)
9347#define R_DACK_S0P3 0xC080
9348#define B_DACK_S0M1 GENMASK(31, 24)
9349#define B_DACK_S0P3_OK BIT(2)
9350#define R_DACK_DADCK01 0xC084
9351#define B_DACK_DADCK01 GENMASK(31, 24)
9352#define R_DRCK_FH 0xC094
9353#define B_DRCK_LAT BIT(9)
9354#define R_DRCK 0xC0C4
9355#define B_DRCK_MUL GENMASK(21, 17)
9356#define B_DRCK_IDLE BIT(9)
9357#define B_DRCK_EN BIT(6)
9358#define B_DRCK_VAL GENMASK(4, 0)
9359#define R_DRCK_RES 0xC0C8
9360#define B_DRCK_RES GENMASK(19, 15)
9361#define B_DRCK_POL BIT(3)
9362#define R_DRCK_V1 0xC0CC
9363#define B_DRCK_V1_SEL BIT(9)
9364#define B_DRCK_V1_KICK BIT(6)
9365#define B_DRCK_V1_CV GENMASK(4, 0)
9366#define R_DRCK_RS 0xC0D0
9367#define B_DRCK_RS_LPS GENMASK(19, 15)
9368#define B_DRCK_RS_DONE BIT(3)
9369#define R_PATH0_SAMPL_DLY_T_V1 0xC0D4
9370#define B_PATH0_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
9371#define R_P0_CFCH_BW0 0xC0D4
9372#define B_P0_CFCH_BW0 GENMASK(27, 26)
9373#define B_P0_CFCH_EN GENMASK(14, 11)
9374#define B_P0_CFCH_CTL GENMASK(10, 7)
9375#define R_P0_CFCH_BW1 0xC0D8
9376#define B_P0_CFCH_EX BIT(13)
9377#define B_P0_CFCH_BW1 GENMASK(8, 5)
9378#define R_WDADC 0xC0E4
9379#define B_WDADC_SEL GENMASK(5, 4)
9380#define R_ADCMOD 0xC0E8
9381#define B_ADCMOD_LP GENMASK(31, 16)
9382#define B_ADCMOD_AUTO_RST BIT(6)
9383#define R_DCIM 0xC0EC
9384#define B_DCIM_RC GENMASK(23, 16)
9385#define B_DCIM_FR GENMASK(14, 13)
9386#define R_ADDCK0D 0xC0F0
9387#define B_ADDCK0D_VAL2 GENMASK(31, 26)
9388#define B_ADDCK0D_VAL GENMASK(25, 16)
9389#define B_ADDCK_DS BIT(16)
9390#define R_ADDCK0 0xC0F4
9391#define B_ADDCK0_TRG BIT(11)
9392#define B_ADDCK0_IQ BIT(10)
9393#define B_ADDCK0 GENMASK(9, 8)
9394#define B_ADDCK0_MAN GENMASK(5, 4)
9395#define B_ADDCK0_EN BIT(4)
9396#define B_ADDCK0_VAL GENMASK(3, 0)
9397#define B_ADDCK0_RST BIT(2)
9398#define R_ADDCK0_RL 0xC0F8
9399#define B_ADDCK0_RLS GENMASK(29, 28)
9400#define B_ADDCK0_RL1 GENMASK(27, 18)
9401#define B_ADDCK0_RL0 GENMASK(17, 8)
9402#define R_ADDCKR0 0xC0FC
9403#define B_ADDCKR0_A0 GENMASK(19, 10)
9404#define B_ADDCKR0_DC GENMASK(15, 4)
9405#define B_ADDCKR0_A1 GENMASK(9, 0)
9406#define R_DACK10 0xC100
9407#define B_DACK10_RST BIT(17)
9408#define B_DACK10 GENMASK(4, 1)
9409#define R_DACK1_K 0xc104
9410#define B_DACK1_VAL GENMASK(31, 20)
9411#define B_DACK1_RST BIT(17)
9412#define B_DACK1_EN BIT(0)
9413#define R_DACK11 0xC120
9414#define B_DACK11 GENMASK(4, 1)
9415#define R_DACK2_K 0xC124
9416#define B_DACK2_VAL GENMASK(31, 20)
9417#define B_DACK2_RST BIT(17)
9418#define B_DACK2_EN BIT(0)
9419#define R_DACK_S1P0 0xC140
9420#define B_DACK_S1P0_OK BIT(31)
9421#define R_DACK_BIAS10 0xC148
9422#define B_DACK_BIAS10 GENMASK(11, 2)
9423#define R_DACK10S 0xC15C
9424#define B_DACK10S GENMASK(31, 24)
9425#define R_DACK_S1P2 0xC15C
9426#define B_DACK_S1P2_OK BIT(2)
9427#define R_DACK_DADCK10 0xC160
9428#define B_DACK_DADCK10 GENMASK(31, 24)
9429#define R_DACK_S1P1 0xC164
9430#define B_DACK_S1P1_OK BIT(31)
9431#define R_DACK_BIAS11 0xC16C
9432#define B_DACK_BIAS11 GENMASK(11, 2)
9433#define R_DACK11S 0xC180
9434#define B_DACK11S GENMASK(31, 24)
9435#define R_DACK_S1P3 0xC180
9436#define B_DACK_S1P3_OK BIT(2)
9437#define R_DACK_DADCK11 0xC184
9438#define B_DACK_DADCK11 GENMASK(31, 24)
9439#define R_PATH1_SAMPL_DLY_T_V1 0xC1D4
9440#define B_PATH1_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
9441#define R_PATH0_BW_SEL_V1 0xC0D8
9442#define B_PATH0_BW_SEL_MSK_V1 GENMASK(8, 5)
9443#define R_PATH1_BW_SEL_V1 0xC1D8
9444#define B_PATH1_BW_SEL_EX BIT(13)
9445#define B_PATH1_BW_SEL_MSK_V1 GENMASK(8, 5)
9446#define R_ADDCK1D 0xC1F0
9447#define B_ADDCK1D_VAL2 GENMASK(31, 26)
9448#define B_ADDCK1D_VAL GENMASK(25, 16)
9449#define R_ADDCK1 0xC1F4
9450#define B_ADDCK1_TRG BIT(11)
9451#define B_ADDCK1 GENMASK(9, 8)
9452#define B_ADDCK1_MAN GENMASK(5, 4)
9453#define B_ADDCK1_EN BIT(4)
9454#define B_ADDCK1_RST BIT(2)
9455#define R_ADDCK1_RL 0xC1F8
9456#define B_ADDCK1_RLS GENMASK(29, 28)
9457#define B_ADDCK1_RL1 GENMASK(27, 18)
9458#define B_ADDCK1_RL0 GENMASK(17, 8)
9459#define R_ADDCKR1 0xC1fC
9460#define B_ADDCKR1_A0 GENMASK(19, 10)
9461#define B_ADDCKR1_A1 GENMASK(9, 0)
9462#define R_DACKN0_CTL 0xC210
9463#define B_DACKN0_EN BIT(0)
9464#define B_DACKN0_V GENMASK(21, 14)
9465#define R_DACKN1_CTL 0xC224
9466#define B_DACKN1_V GENMASK(21, 14)
9467#define B_DACKN1_ON BIT(0)
9468#define R_DACKN2_CTL 0xC238
9469#define B_DACKN2_ON BIT(0)
9470#define R_DACKN3_CTL 0xC24C
9471#define B_DACKN3_ON BIT(0)
9472#define R_GAIN_MAP0 0xE44C
9473#define B_GAIN_MAP0_EN BIT(0)
9474#define R_GAIN_MAP1 0xE54C
9475#define B_GAIN_MAP1_EN BIT(0)
9476#define R_GOTX_IQKDPK_C0 0xE464
9477#define R_GOTX_IQKDPK_C1 0xE564
9478#define B_GOTX_IQKDPK GENMASK(28, 27)
9479#define R_IQK_DPK_PRST 0xE4AC
9480#define R_IQK_DPK_PRST_C1 0xE5AC
9481#define B_IQK_DPK_PRST BIT(27)
9482#define R_TXPWR_RSTA 0xE60C
9483#define B_TXPWR_RSTA BIT(16)
9484#define R_TSSI_PWR_P0 0xE610
9485#define R_TSSI_PWR_P1 0xE710
9486#define B_TSSI_CONT_EN BIT(3)
9487#define R_P0_TXPWRB_BE 0xE61C
9488#define R_P1_TXPWRB_BE 0xE71C
9489#define B_TXPWRB_MAX_BE GENMASK(20, 12)
9490#define R_TSSI_MAP_OFST_P0 0xE620
9491#define R_TSSI_MAP_OFST_P1 0xE720
9492#define B_TSSI_MAP_OFST_OFDM GENMASK(17, 9)
9493#define B_TSSI_MAP_OFST_CCK GENMASK(26, 18)
9494#define R_TXAGC_REF_DBM_P0 0xE628
9495#define B_TXAGC_OFDM_REF_DBM_P0 GENMASK(8, 0)
9496#define B_TXAGC_CCK_REF_DBM_P0 GENMASK(17, 9)
9497#define R_TSSI_K_P0 0xE6A0
9498#define B_TSSI_K_OFDM_P0 GENMASK(29, 20)
9499#define R_TXPWR_RSTB 0xE70C
9500#define B_TXPWR_RSTB BIT(16)
9501#define R_TXAGC_REF_DBM_P1 0xE728
9502#define B_TXAGC_OFDM_REF_DBM_P1 GENMASK(8, 0)
9503#define B_TXAGC_CCK_REF_DBM_P1 GENMASK(17, 9)
9504#define R_TSSI_K_P1 0xE7A0
9505#define B_TSSI_K_OFDM_P1 GENMASK(29, 20)
9506
9507/* WiFi CPU local domain */
9508#define R_AX_WDT_CTRL 0x0040
9509#define B_AX_WDT_EN BIT(31)
9510#define B_AX_WDT_OPT_RESET_PLATFORM_EN BIT(29)
9511#define B_AX_IO_HANG_IMR BIT(27)
9512#define B_AX_IO_HANG_CMAC_RDATA_EN BIT(26)
9513#define B_AX_IO_HANG_DMAC_EN BIT(25)
9514#define B_AX_WDT_CLR BIT(16)
9515#define B_AX_WDT_COUNT_MASK GENMASK(15, 0)
9516#define WDT_CTRL_ALL_DIS 0
9517
9518#define R_AX_WDT_STATUS 0x0044
9519#define B_AX_FS_WDT_INT BIT(8)
9520#define B_AX_FS_WDT_INT_MSK BIT(0)
9521
9522#endif