phy.h

   1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2/* Copyright(c) 2019-2020  Realtek Corporation
   3 */
   4
   5#ifndef __RTW89_PHY_H__
   6#define __RTW89_PHY_H__
   7
   8#include "core.h"
   9
  10#define RTW89_BBMCU_ADDR_OFFSET	0x30000
  11#define RTW89_RF_ADDR_ADSEL_MASK  BIT(16)
  12
  13#define get_phy_headline(addr)		FIELD_GET(GENMASK(31, 28), addr)
  14#define PHY_HEADLINE_VALID	0xf
  15#define get_phy_target(addr)		FIELD_GET(GENMASK(27, 0), addr)
  16#define get_phy_compare(rfe, cv)	(FIELD_PREP(GENMASK(23, 16), rfe) | \
  17					 FIELD_PREP(GENMASK(7, 0), cv))
  18
  19#define get_phy_cond(addr)		FIELD_GET(GENMASK(31, 28), addr)
  20#define get_phy_cond_rfe(addr)		FIELD_GET(GENMASK(23, 16), addr)
  21#define get_phy_cond_pkg(addr)		FIELD_GET(GENMASK(15, 8), addr)
  22#define get_phy_cond_cv(addr)		FIELD_GET(GENMASK(7, 0), addr)
  23#define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; })
  24#define PHY_COND_BRANCH_IF	0x8
  25#define PHY_COND_BRANCH_ELIF	0x9
  26#define PHY_COND_BRANCH_ELSE	0xa
  27#define PHY_COND_BRANCH_END	0xb
  28#define PHY_COND_CHECK		0x4
  29#define PHY_COND_DONT_CARE	0xff
  30
  31#define RA_MASK_CCK_RATES	GENMASK_ULL(3, 0)
  32#define RA_MASK_OFDM_RATES	GENMASK_ULL(11, 4)
  33#define RA_MASK_SUBCCK_RATES	0x5ULL
  34#define RA_MASK_SUBOFDM_RATES	0x10ULL
  35#define RA_MASK_HT_1SS_RATES	GENMASK_ULL(19, 12)
  36#define RA_MASK_HT_2SS_RATES	GENMASK_ULL(31, 24)
  37#define RA_MASK_HT_3SS_RATES	GENMASK_ULL(43, 36)
  38#define RA_MASK_HT_4SS_RATES	GENMASK_ULL(55, 48)
  39#define RA_MASK_HT_RATES	GENMASK_ULL(55, 12)
  40#define RA_MASK_VHT_1SS_RATES	GENMASK_ULL(21, 12)
  41#define RA_MASK_VHT_2SS_RATES	GENMASK_ULL(33, 24)
  42#define RA_MASK_VHT_3SS_RATES	GENMASK_ULL(45, 36)
  43#define RA_MASK_VHT_4SS_RATES	GENMASK_ULL(57, 48)
  44#define RA_MASK_VHT_RATES	GENMASK_ULL(57, 12)
  45#define RA_MASK_HE_1SS_RATES	GENMASK_ULL(23, 12)
  46#define RA_MASK_HE_2SS_RATES	GENMASK_ULL(35, 24)
  47#define RA_MASK_HE_3SS_RATES	GENMASK_ULL(47, 36)
  48#define RA_MASK_HE_4SS_RATES	GENMASK_ULL(59, 48)
  49#define RA_MASK_HE_RATES	GENMASK_ULL(59, 12)
  50#define RA_MASK_EHT_1SS_RATES	GENMASK_ULL(27, 12)
  51#define RA_MASK_EHT_2SS_RATES	GENMASK_ULL(43, 28)
  52#define RA_MASK_EHT_3SS_RATES	GENMASK_ULL(59, 44)
  53#define RA_MASK_EHT_4SS_RATES	GENMASK_ULL(62, 60)
  54#define RA_MASK_EHT_1SS_MCS0_11	GENMASK_ULL(23, 12)
  55#define RA_MASK_EHT_2SS_MCS0_11	GENMASK_ULL(39, 28)
  56#define RA_MASK_EHT_3SS_MCS0_11	GENMASK_ULL(55, 44)
  57#define RA_MASK_EHT_4SS_MCS0_11	GENMASK_ULL(62, 60)
  58#define RA_MASK_EHT_RATES	GENMASK_ULL(62, 12)
  59
  60#define CFO_TRK_ENABLE_TH (2 << 2)
  61#define CFO_TRK_STOP_TH_4 (30 << 2)
  62#define CFO_TRK_STOP_TH_3 (20 << 2)
  63#define CFO_TRK_STOP_TH_2 (10 << 2)
  64#define CFO_TRK_STOP_TH_1 (03 << 2)
  65#define CFO_TRK_STOP_TH (2 << 2)
  66#define CFO_SW_COMP_FINE_TUNE (2 << 2)
  67#define CFO_PERIOD_CNT 15
  68#define CFO_BOUND 64
  69#define CFO_TP_UPPER 100
  70#define CFO_TP_LOWER 50
  71#define CFO_COMP_PERIOD 250
  72#define CFO_COMP_WEIGHT 8
  73#define MAX_CFO_TOLERANCE 30
  74#define CFO_TF_CNT_TH 300
  75
  76#define UL_TB_TF_CNT_L2H_TH 100
  77#define UL_TB_TF_CNT_H2L_TH 70
  78
  79#define ANTDIV_TRAINNING_CNT 2
  80#define ANTDIV_TRAINNING_INTVL 30
  81#define ANTDIV_DELAY 110
  82#define ANTDIV_TP_DIFF_TH_HIGH 100
  83#define ANTDIV_TP_DIFF_TH_LOW 5
  84#define ANTDIV_EVM_DIFF_TH 8
  85#define ANTDIV_RSSI_DIFF_TH 3
  86
  87#define CCX_MAX_PERIOD 2097
  88#define CCX_MAX_PERIOD_UNIT 32
  89#define MS_TO_4US_RATIO 250
  90#define ENV_MNTR_FAIL_DWORD 0xffffffff
  91#define ENV_MNTR_IFSCLM_HIS_MAX 127
  92#define PERMIL 1000
  93#define PERCENT 100
  94#define IFS_CLM_TH0_UPPER 64
  95#define IFS_CLM_TH_MUL 4
  96#define IFS_CLM_TH_START_IDX 0
  97
  98#define TIA0_GAIN_A 12
  99#define TIA0_GAIN_G 16
 100#define LNA0_GAIN (-24)
 101#define U4_MAX_BIT 3
 102#define U8_MAX_BIT 7
 103#define DIG_GAIN_SHIFT 2
 104#define DIG_GAIN 8
 105
 106#define LNA_IDX_MAX 6
 107#define LNA_IDX_MIN 0
 108#define TIA_IDX_MAX 1
 109#define TIA_IDX_MIN 0
 110#define RXB_IDX_MAX 31
 111#define RXB_IDX_MIN 0
 112
 113#define IGI_RSSI_MAX 110
 114#define PD_TH_MAX_RSSI 70
 115#define PD_TH_MIN_RSSI 8
 116#define CCKPD_TH_MIN_RSSI (-18)
 117#define PD_TH_BW160_CMP_VAL 9
 118#define PD_TH_BW80_CMP_VAL 6
 119#define PD_TH_BW40_CMP_VAL 3
 120#define PD_TH_BW20_CMP_VAL 0
 121#define PD_TH_CMP_VAL 3
 122#define PD_TH_SB_FLTR_CMP_VAL 7
 123
 124#define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT)
 125#define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL)
 126#define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA)
 127#define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD)
 128#define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA)
 129
 130#define EDCCA_MAX 249
 131#define EDCCA_TH_L2H_LB 66
 132#define EDCCA_TH_REF 3
 133#define EDCCA_HL_DIFF_NORMAL 8
 134#define RSSI_UNIT_CONVER 110
 135#define EDCCA_UNIT_CONVER 128
 136#define EDCCA_PWROFST_DEFAULT 18
 137
 138enum rtw89_phy_c2h_ra_func {
 139	RTW89_PHY_C2H_FUNC_STS_RPT,
 140	RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT,
 141	RTW89_PHY_C2H_FUNC_TXSTS,
 142	RTW89_PHY_C2H_FUNC_RA_MAX,
 143};
 144
 145enum rtw89_phy_c2h_rfk_log_func {
 146	RTW89_PHY_C2H_RFK_LOG_FUNC_IQK = 0,
 147	RTW89_PHY_C2H_RFK_LOG_FUNC_DPK = 1,
 148	RTW89_PHY_C2H_RFK_LOG_FUNC_DACK = 2,
 149	RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK = 3,
 150	RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI = 4,
 151	RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK = 5,
 152	RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR = 9,
 153
 154	RTW89_PHY_C2H_RFK_LOG_FUNC_NUM,
 155};
 156
 157enum rtw89_phy_c2h_rfk_report_func {
 158	RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE = 0,
 159	RTW89_PHY_C2H_RFK_REPORT_FUNC_TAS_PWR = 6,
 160};
 161
 162enum rtw89_phy_c2h_dm_func {
 163	RTW89_PHY_C2H_DM_FUNC_FW_TEST,
 164	RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT,
 165	RTW89_PHY_C2H_DM_FUNC_SIGB,
 166	RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY,
 167	RTW89_PHY_C2H_DM_FUNC_MCC_DIG,
 168	RTW89_PHY_C2H_DM_FUNC_FW_SCAN = 0xc,
 169	RTW89_PHY_C2H_DM_FUNC_NUM,
 170};
 171
 172enum rtw89_phy_c2h_class {
 173	RTW89_PHY_C2H_CLASS_RUA,
 174	RTW89_PHY_C2H_CLASS_RA,
 175	RTW89_PHY_C2H_CLASS_DM,
 176	RTW89_PHY_C2H_RFK_LOG = 0x8,
 177	RTW89_PHY_C2H_RFK_REPORT = 0x9,
 178	RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10,
 179	RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17,
 180	RTW89_PHY_C2H_CLASS_MAX,
 181};
 182
 183enum rtw89_env_monitor_result_level {
 184	RTW89_PHY_ENV_MON_CCX_FAIL = 0,
 185	RTW89_PHY_ENV_MON_NHM = BIT(0),
 186	RTW89_PHY_ENV_MON_CLM = BIT(1),
 187	RTW89_PHY_ENV_MON_FAHM = BIT(2),
 188	RTW89_PHY_ENV_MON_IFS_CLM = BIT(3),
 189	RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4),
 190};
 191
 192#define RTW89_NHM_WEIGHT_OFFSET 2
 193#define RTW89_NHM_WA_TH (109 << 1)
 194#define RTW89_NOISE_DEFAULT -96
 195#define RTW89_NHM_MNTR_TIME 40
 196#define RTW89_NHM_TH_FACTOR 1
 197
 198#define CCX_US_BASE_RATIO 4
 199enum rtw89_ccx_unit {
 200	RTW89_CCX_4_US = 0,
 201	RTW89_CCX_8_US = 1,
 202	RTW89_CCX_16_US = 2,
 203	RTW89_CCX_32_US = 3
 204};
 205
 206enum rtw89_phy_status_ie_type {
 207	RTW89_PHYSTS_IE00_CMN_CCK			= 0,
 208	RTW89_PHYSTS_IE01_CMN_OFDM			= 1,
 209	RTW89_PHYSTS_IE02_CMN_EXT_AX			= 2,
 210	RTW89_PHYSTS_IE03_CMN_EXT_SEG_1			= 3,
 211	RTW89_PHYSTS_IE04_CMN_EXT_PATH_A		= 4,
 212	RTW89_PHYSTS_IE05_CMN_EXT_PATH_B		= 5,
 213	RTW89_PHYSTS_IE06_CMN_EXT_PATH_C		= 6,
 214	RTW89_PHYSTS_IE07_CMN_EXT_PATH_D		= 7,
 215	RTW89_PHYSTS_IE08_FTR_CH			= 8,
 216	RTW89_PHYSTS_IE09_FTR_0				= 9,
 217	RTW89_PHYSTS_IE10_FTR_PLCP_EXT			= 10,
 218	RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM		= 11,
 219	RTW89_PHYSTS_IE12_MU_EIGEN_INFO			= 12,
 220	RTW89_PHYSTS_IE13_DL_MU_DEF			= 13,
 221	RTW89_PHYSTS_IE14_TB_UL_CQI			= 14,
 222	RTW89_PHYSTS_IE15_TB_UL_DEF			= 15,
 223	RTW89_PHYSTS_IE16_RSVD16			= 16,
 224	RTW89_PHYSTS_IE17_TB_UL_CTRL			= 17,
 225	RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN		= 18,
 226	RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN		= 19,
 227	RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0	= 20,
 228	RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1	= 21,
 229	RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC		= 22,
 230	RTW89_PHYSTS_IE23_RSVD23			= 23,
 231	RTW89_PHYSTS_IE24_OFDM_TD_PATH_A		= 24,
 232	RTW89_PHYSTS_IE25_OFDM_TD_PATH_B		= 25,
 233	RTW89_PHYSTS_IE26_OFDM_TD_PATH_C		= 26,
 234	RTW89_PHYSTS_IE27_OFDM_TD_PATH_D		= 27,
 235	RTW89_PHYSTS_IE28_DBG_CCK_PATH_A		= 28,
 236	RTW89_PHYSTS_IE29_DBG_CCK_PATH_B		= 29,
 237	RTW89_PHYSTS_IE30_DBG_CCK_PATH_C		= 30,
 238	RTW89_PHYSTS_IE31_DBG_CCK_PATH_D		= 31,
 239
 240	/* keep last */
 241	RTW89_PHYSTS_IE_NUM,
 242	RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1
 243};
 244
 245enum rtw89_phy_status_bitmap {
 246	RTW89_TD_SEARCH_FAIL  = 0,
 247	RTW89_BRK_BY_TX_PKT   = 1,
 248	RTW89_CCA_SPOOF       = 2,
 249	RTW89_OFDM_BRK        = 3,
 250	RTW89_CCK_BRK         = 4,
 251	RTW89_DL_MU_SPOOFING  = 5,
 252	RTW89_HE_MU           = 6,
 253	RTW89_VHT_MU          = 7,
 254	RTW89_UL_TB_SPOOFING  = 8,
 255	RTW89_RSVD_9          = 9,
 256	RTW89_TRIG_BASE_PPDU  = 10,
 257	RTW89_CCK_PKT         = 11,
 258	RTW89_LEGACY_OFDM_PKT = 12,
 259	RTW89_HT_PKT          = 13,
 260	RTW89_VHT_PKT         = 14,
 261	RTW89_HE_PKT          = 15,
 262	RTW89_EHT_PKT         = 16,
 263
 264	RTW89_PHYSTS_BITMAP_NUM
 265};
 266
 267enum rtw89_dig_gain_type {
 268	RTW89_DIG_GAIN_LNA_G = 0,
 269	RTW89_DIG_GAIN_TIA_G = 1,
 270	RTW89_DIG_GAIN_LNA_A = 2,
 271	RTW89_DIG_GAIN_TIA_A = 3,
 272	RTW89_DIG_GAIN_MAX = 4
 273};
 274
 275enum rtw89_dig_gain_lna_idx {
 276	RTW89_DIG_GAIN_LNA_IDX1 = 1,
 277	RTW89_DIG_GAIN_LNA_IDX2 = 2,
 278	RTW89_DIG_GAIN_LNA_IDX3 = 3,
 279	RTW89_DIG_GAIN_LNA_IDX4 = 4,
 280	RTW89_DIG_GAIN_LNA_IDX5 = 5,
 281	RTW89_DIG_GAIN_LNA_IDX6 = 6
 282};
 283
 284enum rtw89_dig_gain_tia_idx {
 285	RTW89_DIG_GAIN_TIA_IDX0 = 0,
 286	RTW89_DIG_GAIN_TIA_IDX1 = 1
 287};
 288
 289enum rtw89_tssi_bandedge_cfg {
 290	RTW89_TSSI_BANDEDGE_FLAT,
 291	RTW89_TSSI_BANDEDGE_LOW,
 292	RTW89_TSSI_BANDEDGE_MID,
 293	RTW89_TSSI_BANDEDGE_HIGH,
 294
 295	RTW89_TSSI_CFG_NUM,
 296};
 297
 298enum rtw89_tssi_sbw_idx {
 299	RTW89_TSSI_SBW20,
 300	RTW89_TSSI_SBW40_0,
 301	RTW89_TSSI_SBW40_1,
 302	RTW89_TSSI_SBW80_0,
 303	RTW89_TSSI_SBW80_1,
 304	RTW89_TSSI_SBW80_2,
 305	RTW89_TSSI_SBW80_3,
 306	RTW89_TSSI_SBW160_0,
 307	RTW89_TSSI_SBW160_1,
 308	RTW89_TSSI_SBW160_2,
 309	RTW89_TSSI_SBW160_3,
 310	RTW89_TSSI_SBW160_4,
 311	RTW89_TSSI_SBW160_5,
 312	RTW89_TSSI_SBW160_6,
 313	RTW89_TSSI_SBW160_7,
 314
 315	RTW89_TSSI_SBW_NUM,
 316};
 317
 318struct rtw89_txpwr_byrate_cfg {
 319	enum rtw89_band band;
 320	enum rtw89_nss nss;
 321	enum rtw89_rate_section rs;
 322	u8 shf;
 323	u8 len;
 324	u32 data;
 325};
 326
 327struct rtw89_txpwr_track_cfg {
 328	const s8 (*delta_swingidx_6gb_n)[DELTA_SWINGIDX_SIZE];
 329	const s8 (*delta_swingidx_6gb_p)[DELTA_SWINGIDX_SIZE];
 330	const s8 (*delta_swingidx_6ga_n)[DELTA_SWINGIDX_SIZE];
 331	const s8 (*delta_swingidx_6ga_p)[DELTA_SWINGIDX_SIZE];
 332	const s8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE];
 333	const s8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE];
 334	const s8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE];
 335	const s8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE];
 336	const s8 *delta_swingidx_2gb_n;
 337	const s8 *delta_swingidx_2gb_p;
 338	const s8 *delta_swingidx_2ga_n;
 339	const s8 *delta_swingidx_2ga_p;
 340	const s8 *delta_swingidx_2g_cck_b_n;
 341	const s8 *delta_swingidx_2g_cck_b_p;
 342	const s8 *delta_swingidx_2g_cck_a_n;
 343	const s8 *delta_swingidx_2g_cck_a_p;
 344};
 345
 346struct rtw89_phy_dig_gain_cfg {
 347	const struct rtw89_reg_def *table;
 348	u8 size;
 349};
 350
 351struct rtw89_phy_dig_gain_table {
 352	const struct rtw89_phy_dig_gain_cfg *cfg_lna_g;
 353	const struct rtw89_phy_dig_gain_cfg *cfg_tia_g;
 354	const struct rtw89_phy_dig_gain_cfg *cfg_lna_a;
 355	const struct rtw89_phy_dig_gain_cfg *cfg_tia_a;
 356};
 357
 358struct rtw89_phy_tssi_dbw_table {
 359	u32 data[RTW89_TSSI_CFG_NUM][RTW89_TSSI_SBW_NUM];
 360};
 361
 362struct rtw89_phy_reg3_tbl {
 363	const struct rtw89_reg3_def *reg3;
 364	int size;
 365};
 366
 367#define DECLARE_PHY_REG3_TBL(_name)			\
 368const struct rtw89_phy_reg3_tbl _name ## _tbl = {	\
 369	.reg3 = _name,					\
 370	.size = ARRAY_SIZE(_name),			\
 371}
 372
 373struct rtw89_nbi_reg_def {
 374	struct rtw89_reg_def notch1_idx;
 375	struct rtw89_reg_def notch1_frac_idx;
 376	struct rtw89_reg_def notch1_en;
 377	struct rtw89_reg_def notch2_idx;
 378	struct rtw89_reg_def notch2_frac_idx;
 379	struct rtw89_reg_def notch2_en;
 380};
 381
 382struct rtw89_ccx_regs {
 383	u32 setting_addr;
 384	u32 edcca_opt_mask;
 385	u32 measurement_trig_mask;
 386	u32 trig_opt_mask;
 387	u32 en_mask;
 388	u32 ifs_cnt_addr;
 389	u32 ifs_clm_period_mask;
 390	u32 ifs_clm_cnt_unit_mask;
 391	u32 ifs_clm_cnt_clear_mask;
 392	u32 ifs_collect_en_mask;
 393	u32 ifs_t1_addr;
 394	u32 ifs_t1_th_h_mask;
 395	u32 ifs_t1_en_mask;
 396	u32 ifs_t1_th_l_mask;
 397	u32 ifs_t2_addr;
 398	u32 ifs_t2_th_h_mask;
 399	u32 ifs_t2_en_mask;
 400	u32 ifs_t2_th_l_mask;
 401	u32 ifs_t3_addr;
 402	u32 ifs_t3_th_h_mask;
 403	u32 ifs_t3_en_mask;
 404	u32 ifs_t3_th_l_mask;
 405	u32 ifs_t4_addr;
 406	u32 ifs_t4_th_h_mask;
 407	u32 ifs_t4_en_mask;
 408	u32 ifs_t4_th_l_mask;
 409	u32 ifs_clm_tx_cnt_addr;
 410	u32 ifs_clm_edcca_excl_cca_fa_mask;
 411	u32 ifs_clm_tx_cnt_msk;
 412	u32 ifs_clm_cca_addr;
 413	u32 ifs_clm_ofdmcca_excl_fa_mask;
 414	u32 ifs_clm_cckcca_excl_fa_mask;
 415	u32 ifs_clm_fa_addr;
 416	u32 ifs_clm_ofdm_fa_mask;
 417	u32 ifs_clm_cck_fa_mask;
 418	u32 ifs_his_addr;
 419	u32 ifs_t4_his_mask;
 420	u32 ifs_t3_his_mask;
 421	u32 ifs_t2_his_mask;
 422	u32 ifs_t1_his_mask;
 423	u32 ifs_avg_l_addr;
 424	u32 ifs_t2_avg_mask;
 425	u32 ifs_t1_avg_mask;
 426	u32 ifs_avg_h_addr;
 427	u32 ifs_t4_avg_mask;
 428	u32 ifs_t3_avg_mask;
 429	u32 ifs_cca_l_addr;
 430	u32 ifs_t2_cca_mask;
 431	u32 ifs_t1_cca_mask;
 432	u32 ifs_cca_h_addr;
 433	u32 ifs_t4_cca_mask;
 434	u32 ifs_t3_cca_mask;
 435	u32 ifs_total_addr;
 436	u32 ifs_cnt_done_mask;
 437	u32 ifs_total_mask;
 438	u32 nhm;
 439	u32 nhm_ready;
 440	u32 nhm_config;
 441	u32 nhm_period_mask;
 442	u32 nhm_unit_mask;
 443	u32 nhm_include_cca_mask;
 444	u32 nhm_en_mask;
 445	u32 nhm_method;
 446	u32 nhm_pwr_method_msk;
 447};
 448
 449struct rtw89_physts_regs {
 450	u32 setting_addr;
 451	u32 dis_trigger_fail_mask;
 452	u32 dis_trigger_brk_mask;
 453};
 454
 455struct rtw89_cfo_regs {
 456	u32 comp;
 457	u32 weighting_mask;
 458	u32 comp_seg0;
 459	u32 valid_0_mask;
 460};
 461
 462enum rtw89_bandwidth_section_num_ax {
 463	RTW89_BW20_SEC_NUM_AX = 8,
 464	RTW89_BW40_SEC_NUM_AX = 4,
 465	RTW89_BW80_SEC_NUM_AX = 2,
 466};
 467
 468enum rtw89_bandwidth_section_num_be {
 469	RTW89_BW20_SEC_NUM_BE = 16,
 470	RTW89_BW40_SEC_NUM_BE = 8,
 471	RTW89_BW80_SEC_NUM_BE = 4,
 472	RTW89_BW160_SEC_NUM_BE = 2,
 473};
 474
 475#define RTW89_TXPWR_LMT_PAGE_SIZE_AX 40
 476
 477struct rtw89_txpwr_limit_ax {
 478	s8 cck_20m[RTW89_BF_NUM];
 479	s8 cck_40m[RTW89_BF_NUM];
 480	s8 ofdm[RTW89_BF_NUM];
 481	s8 mcs_20m[RTW89_BW20_SEC_NUM_AX][RTW89_BF_NUM];
 482	s8 mcs_40m[RTW89_BW40_SEC_NUM_AX][RTW89_BF_NUM];
 483	s8 mcs_80m[RTW89_BW80_SEC_NUM_AX][RTW89_BF_NUM];
 484	s8 mcs_160m[RTW89_BF_NUM];
 485	s8 mcs_40m_0p5[RTW89_BF_NUM];
 486	s8 mcs_40m_2p5[RTW89_BF_NUM];
 487};
 488
 489#define RTW89_TXPWR_LMT_PAGE_SIZE_BE 76
 490
 491struct rtw89_txpwr_limit_be {
 492	s8 cck_20m[RTW89_BF_NUM];
 493	s8 cck_40m[RTW89_BF_NUM];
 494	s8 ofdm[RTW89_BF_NUM];
 495	s8 mcs_20m[RTW89_BW20_SEC_NUM_BE][RTW89_BF_NUM];
 496	s8 mcs_40m[RTW89_BW40_SEC_NUM_BE][RTW89_BF_NUM];
 497	s8 mcs_80m[RTW89_BW80_SEC_NUM_BE][RTW89_BF_NUM];
 498	s8 mcs_160m[RTW89_BW160_SEC_NUM_BE][RTW89_BF_NUM];
 499	s8 mcs_320m[RTW89_BF_NUM];
 500	s8 mcs_40m_0p5[RTW89_BF_NUM];
 501	s8 mcs_40m_2p5[RTW89_BF_NUM];
 502	s8 mcs_40m_4p5[RTW89_BF_NUM];
 503	s8 mcs_40m_6p5[RTW89_BF_NUM];
 504};
 505
 506#define RTW89_RU_SEC_NUM_AX 8
 507
 508#define RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX 24
 509
 510struct rtw89_txpwr_limit_ru_ax {
 511	s8 ru26[RTW89_RU_SEC_NUM_AX];
 512	s8 ru52[RTW89_RU_SEC_NUM_AX];
 513	s8 ru106[RTW89_RU_SEC_NUM_AX];
 514};
 515
 516#define RTW89_RU_SEC_NUM_BE 16
 517
 518#define RTW89_TXPWR_LMT_RU_PAGE_SIZE_BE 80
 519
 520struct rtw89_txpwr_limit_ru_be {
 521	s8 ru26[RTW89_RU_SEC_NUM_BE];
 522	s8 ru52[RTW89_RU_SEC_NUM_BE];
 523	s8 ru106[RTW89_RU_SEC_NUM_BE];
 524	s8 ru52_26[RTW89_RU_SEC_NUM_BE];
 525	s8 ru106_26[RTW89_RU_SEC_NUM_BE];
 526};
 527
 528struct rtw89_phy_rfk_log_fmt {
 529	const struct rtw89_fw_element_hdr *elm[RTW89_PHY_C2H_RFK_LOG_FUNC_NUM];
 530};
 531
 532struct rtw89_phy_gen_def {
 533	u32 cr_base;
 534	const struct rtw89_ccx_regs *ccx;
 535	const struct rtw89_physts_regs *physts;
 536	const struct rtw89_cfo_regs *cfo;
 537	u32 (*phy0_phy1_offset)(struct rtw89_dev *rtwdev, u32 addr);
 538	void (*config_bb_gain)(struct rtw89_dev *rtwdev,
 539			       const struct rtw89_reg2_def *reg,
 540			       enum rtw89_rf_path rf_path,
 541			       void *extra_data);
 542	void (*preinit_rf_nctl)(struct rtw89_dev *rtwdev);
 543	void (*bb_wrap_init)(struct rtw89_dev *rtwdev);
 544	void (*ch_info_init)(struct rtw89_dev *rtwdev);
 545
 546	void (*set_txpwr_byrate)(struct rtw89_dev *rtwdev,
 547				 const struct rtw89_chan *chan,
 548				 enum rtw89_phy_idx phy_idx);
 549	void (*set_txpwr_offset)(struct rtw89_dev *rtwdev,
 550				 const struct rtw89_chan *chan,
 551				 enum rtw89_phy_idx phy_idx);
 552	void (*set_txpwr_limit)(struct rtw89_dev *rtwdev,
 553				const struct rtw89_chan *chan,
 554				enum rtw89_phy_idx phy_idx);
 555	void (*set_txpwr_limit_ru)(struct rtw89_dev *rtwdev,
 556				   const struct rtw89_chan *chan,
 557				   enum rtw89_phy_idx phy_idx);
 558};
 559
 560extern const struct rtw89_phy_gen_def rtw89_phy_gen_ax;
 561extern const struct rtw89_phy_gen_def rtw89_phy_gen_be;
 562
 563static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev,
 564				    u32 addr, u8 data)
 565{
 566	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
 567
 568	rtw89_write8(rtwdev, addr + phy->cr_base, data);
 569}
 570
 571static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev,
 572				     u32 addr, u16 data)
 573{
 574	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
 575
 576	rtw89_write16(rtwdev, addr + phy->cr_base, data);
 577}
 578
 579static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev,
 580				     u32 addr, u32 data)
 581{
 582	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
 583
 584	rtw89_write32(rtwdev, addr + phy->cr_base, data);
 585}
 586
 587static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev,
 588					 u32 addr, u32 bits)
 589{
 590	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
 591
 592	rtw89_write32_set(rtwdev, addr + phy->cr_base, bits);
 593}
 594
 595static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev,
 596					 u32 addr, u32 bits)
 597{
 598	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
 599
 600	rtw89_write32_clr(rtwdev, addr + phy->cr_base, bits);
 601}
 602
 603static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev,
 604					  u32 addr, u32 mask, u32 data)
 605{
 606	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
 607
 608	rtw89_write32_mask(rtwdev, addr + phy->cr_base, mask, data);
 609}
 610
 611static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr)
 612{
 613	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
 614
 615	return rtw89_read8(rtwdev, addr + phy->cr_base);
 616}
 617
 618static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr)
 619{
 620	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
 621
 622	return rtw89_read16(rtwdev, addr + phy->cr_base);
 623}
 624
 625static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr)
 626{
 627	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
 628
 629	return rtw89_read32(rtwdev, addr + phy->cr_base);
 630}
 631
 632static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev,
 633					u32 addr, u32 mask)
 634{
 635	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
 636
 637	return rtw89_read32_mask(rtwdev, addr + phy->cr_base, mask);
 638}
 639
 640static inline void rtw89_bbmcu_write32(struct rtw89_dev *rtwdev,
 641				       u32 addr, u32 data, enum rtw89_phy_idx phy_idx)
 642{
 643	if (phy_idx && addr < 0x10000)
 644		addr += 0x20000;
 645
 646	rtw89_write32(rtwdev, addr + RTW89_BBMCU_ADDR_OFFSET, data);
 647}
 648
 649static inline
 650enum rtw89_gain_offset rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband)
 651{
 652	switch (subband) {
 653	default:
 654	case RTW89_CH_2G:
 655		return RTW89_GAIN_OFFSET_2G_OFDM;
 656	case RTW89_CH_5G_BAND_1:
 657		return RTW89_GAIN_OFFSET_5G_LOW;
 658	case RTW89_CH_5G_BAND_3:
 659		return RTW89_GAIN_OFFSET_5G_MID;
 660	case RTW89_CH_5G_BAND_4:
 661		return RTW89_GAIN_OFFSET_5G_HIGH;
 662	case RTW89_CH_6G_BAND_IDX0:
 663		return RTW89_GAIN_OFFSET_6G_L0;
 664	case RTW89_CH_6G_BAND_IDX1:
 665		return RTW89_GAIN_OFFSET_6G_L1;
 666	case RTW89_CH_6G_BAND_IDX2:
 667		return RTW89_GAIN_OFFSET_6G_M0;
 668	case RTW89_CH_6G_BAND_IDX3:
 669		return RTW89_GAIN_OFFSET_6G_M1;
 670	case RTW89_CH_6G_BAND_IDX4:
 671		return RTW89_GAIN_OFFSET_6G_H0;
 672	case RTW89_CH_6G_BAND_IDX5:
 673		return RTW89_GAIN_OFFSET_6G_H1;
 674	case RTW89_CH_6G_BAND_IDX6:
 675		return RTW89_GAIN_OFFSET_6G_UH0;
 676	case RTW89_CH_6G_BAND_IDX7:
 677		return RTW89_GAIN_OFFSET_6G_UH1;
 678	}
 679}
 680
 681static inline
 682enum rtw89_phy_bb_gain_band rtw89_subband_to_bb_gain_band(enum rtw89_subband subband)
 683{
 684	switch (subband) {
 685	default:
 686	case RTW89_CH_2G:
 687		return RTW89_BB_GAIN_BAND_2G;
 688	case RTW89_CH_5G_BAND_1:
 689		return RTW89_BB_GAIN_BAND_5G_L;
 690	case RTW89_CH_5G_BAND_3:
 691		return RTW89_BB_GAIN_BAND_5G_M;
 692	case RTW89_CH_5G_BAND_4:
 693		return RTW89_BB_GAIN_BAND_5G_H;
 694	case RTW89_CH_6G_BAND_IDX0:
 695	case RTW89_CH_6G_BAND_IDX1:
 696		return RTW89_BB_GAIN_BAND_6G_L;
 697	case RTW89_CH_6G_BAND_IDX2:
 698	case RTW89_CH_6G_BAND_IDX3:
 699		return RTW89_BB_GAIN_BAND_6G_M;
 700	case RTW89_CH_6G_BAND_IDX4:
 701	case RTW89_CH_6G_BAND_IDX5:
 702		return RTW89_BB_GAIN_BAND_6G_H;
 703	case RTW89_CH_6G_BAND_IDX6:
 704	case RTW89_CH_6G_BAND_IDX7:
 705		return RTW89_BB_GAIN_BAND_6G_UH;
 706	}
 707}
 708
 709static inline
 710enum rtw89_phy_gain_band_be rtw89_subband_to_gain_band_be(enum rtw89_subband subband)
 711{
 712	switch (subband) {
 713	default:
 714	case RTW89_CH_2G:
 715		return RTW89_BB_GAIN_BAND_2G_BE;
 716	case RTW89_CH_5G_BAND_1:
 717		return RTW89_BB_GAIN_BAND_5G_L_BE;
 718	case RTW89_CH_5G_BAND_3:
 719		return RTW89_BB_GAIN_BAND_5G_M_BE;
 720	case RTW89_CH_5G_BAND_4:
 721		return RTW89_BB_GAIN_BAND_5G_H_BE;
 722	case RTW89_CH_6G_BAND_IDX0:
 723		return RTW89_BB_GAIN_BAND_6G_L0_BE;
 724	case RTW89_CH_6G_BAND_IDX1:
 725		return RTW89_BB_GAIN_BAND_6G_L1_BE;
 726	case RTW89_CH_6G_BAND_IDX2:
 727		return RTW89_BB_GAIN_BAND_6G_M0_BE;
 728	case RTW89_CH_6G_BAND_IDX3:
 729		return RTW89_BB_GAIN_BAND_6G_M1_BE;
 730	case RTW89_CH_6G_BAND_IDX4:
 731		return RTW89_BB_GAIN_BAND_6G_H0_BE;
 732	case RTW89_CH_6G_BAND_IDX5:
 733		return RTW89_BB_GAIN_BAND_6G_H1_BE;
 734	case RTW89_CH_6G_BAND_IDX6:
 735		return RTW89_BB_GAIN_BAND_6G_UH0_BE;
 736	case RTW89_CH_6G_BAND_IDX7:
 737		return RTW89_BB_GAIN_BAND_6G_UH1_BE;
 738	}
 739}
 740
 741struct rtw89_rfk_chan_desc {
 742	/* desc is valid iff ch is non-zero */
 743	u8 ch;
 744
 745	/* To avoid us from extending old chip code every time, each new
 746	 * field must be defined along with a bool flag in positivte way.
 747	 */
 748	bool has_band;
 749	u8 band;
 750	bool has_bw;
 751	u8 bw;
 752};
 753
 754enum rtw89_rfk_flag {
 755	RTW89_RFK_F_WRF = 0,
 756	RTW89_RFK_F_WM = 1,
 757	RTW89_RFK_F_WS = 2,
 758	RTW89_RFK_F_WC = 3,
 759	RTW89_RFK_F_DELAY = 4,
 760	RTW89_RFK_F_NUM,
 761};
 762
 763struct rtw89_rfk_tbl {
 764	const struct rtw89_reg5_def *defs;
 765	u32 size;
 766};
 767
 768#define RTW89_DECLARE_RFK_TBL(_name)		\
 769const struct rtw89_rfk_tbl _name ## _tbl = {	\
 770	.defs = _name,				\
 771	.size = ARRAY_SIZE(_name),		\
 772}
 773
 774#define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data)	\
 775	{.flag = RTW89_RFK_F_WRF,			\
 776	 .path = _path,					\
 777	 .addr = _addr,					\
 778	 .mask = _mask,					\
 779	 .data = _data,}
 780
 781#define RTW89_DECL_RFK_WM(_addr, _mask, _data)	\
 782	{.flag = RTW89_RFK_F_WM,		\
 783	 .addr = _addr,				\
 784	 .mask = _mask,				\
 785	 .data = _data,}
 786
 787#define RTW89_DECL_RFK_WS(_addr, _mask)	\
 788	{.flag = RTW89_RFK_F_WS,	\
 789	 .addr = _addr,			\
 790	 .mask = _mask,}
 791
 792#define RTW89_DECL_RFK_WC(_addr, _mask)	\
 793	{.flag = RTW89_RFK_F_WC,	\
 794	 .addr = _addr,			\
 795	 .mask = _mask,}
 796
 797#define RTW89_DECL_RFK_DELAY(_data)	\
 798	{.flag = RTW89_RFK_F_DELAY,	\
 799	 .data = _data,}
 800
 801void
 802rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl);
 803
 804#define rtw89_rfk_parser_by_cond(dev, cond, tbl_t, tbl_f)	\
 805	do {							\
 806		typeof(dev) __dev = (dev);			\
 807		if (cond)					\
 808			rtw89_rfk_parser(__dev, (tbl_t));	\
 809		else						\
 810			rtw89_rfk_parser(__dev, (tbl_f));	\
 811	} while (0)
 812
 813void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
 814			      const struct rtw89_phy_reg3_tbl *tbl);
 815u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
 816		      const struct rtw89_chan *chan,
 817		      enum rtw89_bandwidth dbw);
 818u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
 819		      enum rtw89_bandwidth dbw);
 820u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
 821		      u32 addr, u32 mask);
 822u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
 823			 u32 addr, u32 mask);
 824u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
 825			 u32 addr, u32 mask);
 826bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
 827			u32 addr, u32 mask, u32 data);
 828bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
 829			   u32 addr, u32 mask, u32 data);
 830bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
 831			   u32 addr, u32 mask, u32 data);
 832void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev);
 833void rtw89_phy_init_bb_afe(struct rtw89_dev *rtwdev);
 834void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio);
 835void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
 836				const struct rtw89_reg2_def *reg,
 837				enum rtw89_rf_path rf_path,
 838				void *extra_data);
 839void rtw89_phy_dm_init(struct rtw89_dev *rtwdev);
 840void rtw89_phy_dm_reinit(struct rtw89_dev *rtwdev);
 841void rtw89_phy_dm_init_data(struct rtw89_dev *rtwdev);
 842void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
 843			   u32 data, enum rtw89_phy_idx phy_idx);
 844void rtw89_phy_write32_idx_set(struct rtw89_dev *rtwdev, u32 addr, u32 bits,
 845			       enum rtw89_phy_idx phy_idx);
 846void rtw89_phy_write32_idx_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bits,
 847			       enum rtw89_phy_idx phy_idx);
 848u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
 849			 enum rtw89_phy_idx phy_idx);
 850s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev,
 851			   struct rtw89_txpwr_byrate *head,
 852			   const struct rtw89_rate_desc *desc);
 853s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw,
 854			       const struct rtw89_rate_desc *rate_desc);
 855void rtw89_phy_ant_gain_init(struct rtw89_dev *rtwdev);
 856s16 rtw89_phy_ant_gain_pwr_offset(struct rtw89_dev *rtwdev,
 857				  const struct rtw89_chan *chan);
 858int rtw89_print_ant_gain(struct rtw89_dev *rtwdev, char *buf, size_t bufsz,
 859			 const struct rtw89_chan *chan);
 860void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
 861				 const struct rtw89_txpwr_table *tbl);
 862s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
 863			      u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch);
 864s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band,
 865				 u8 ru, u8 ntx, u8 ch);
 866
 867static inline void rtw89_phy_preinit_rf_nctl(struct rtw89_dev *rtwdev)
 868{
 869	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
 870
 871	phy->preinit_rf_nctl(rtwdev);
 872}
 873
 874static inline void rtw89_phy_bb_wrap_init(struct rtw89_dev *rtwdev)
 875{
 876	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
 877
 878	if (phy->bb_wrap_init)
 879		phy->bb_wrap_init(rtwdev);
 880}
 881
 882static inline void rtw89_phy_ch_info_init(struct rtw89_dev *rtwdev)
 883{
 884	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
 885
 886	if (phy->ch_info_init)
 887		phy->ch_info_init(rtwdev);
 888}
 889
 890static inline
 891void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev,
 892				const struct rtw89_chan *chan,
 893				enum rtw89_phy_idx phy_idx)
 894{
 895	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
 896
 897	phy->set_txpwr_byrate(rtwdev, chan, phy_idx);
 898}
 899
 900static inline
 901void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev,
 902				const struct rtw89_chan *chan,
 903				enum rtw89_phy_idx phy_idx)
 904{
 905	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
 906
 907	phy->set_txpwr_offset(rtwdev, chan, phy_idx);
 908}
 909
 910static inline
 911void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev,
 912			       const struct rtw89_chan *chan,
 913			       enum rtw89_phy_idx phy_idx)
 914{
 915	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
 916
 917	phy->set_txpwr_limit(rtwdev, chan, phy_idx);
 918}
 919
 920static inline
 921void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev,
 922				  const struct rtw89_chan *chan,
 923				  enum rtw89_phy_idx phy_idx)
 924{
 925	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
 926
 927	phy->set_txpwr_limit_ru(rtwdev, chan, phy_idx);
 928}
 929
 930static inline s8 rtw89_phy_txpwr_rf_to_bb(struct rtw89_dev *rtwdev, s8 txpwr_rf)
 931{
 932	const struct rtw89_chip_info *chip = rtwdev->chip;
 933
 934	return txpwr_rf << (chip->txpwr_factor_bb - chip->txpwr_factor_rf);
 935}
 936
 937static inline s8 rtw89_phy_txpwr_bb_to_rf(struct rtw89_dev *rtwdev, s8 txpwr_bb)
 938{
 939	const struct rtw89_chip_info *chip = rtwdev->chip;
 940
 941	return txpwr_bb >> (chip->txpwr_factor_bb - chip->txpwr_factor_rf);
 942}
 943
 944static inline s8 rtw89_phy_txpwr_rf_to_mac(struct rtw89_dev *rtwdev, s8 txpwr_rf)
 945{
 946	const struct rtw89_chip_info *chip = rtwdev->chip;
 947
 948	return txpwr_rf >> (chip->txpwr_factor_rf - chip->txpwr_factor_mac);
 949}
 950
 951static inline s8 rtw89_phy_txpwr_dbm_to_mac(struct rtw89_dev *rtwdev, s8 dbm)
 952{
 953	const struct rtw89_chip_info *chip = rtwdev->chip;
 954
 955	return clamp_t(s16, dbm << chip->txpwr_factor_mac, -64, 63);
 956}
 957
 958static inline s16 rtw89_phy_txpwr_mac_to_rf(struct rtw89_dev *rtwdev, s8 txpwr_mac)
 959{
 960	const struct rtw89_chip_info *chip = rtwdev->chip;
 961
 962	return txpwr_mac << (chip->txpwr_factor_rf - chip->txpwr_factor_mac);
 963}
 964
 965static inline s16 rtw89_phy_txpwr_mac_to_bb(struct rtw89_dev *rtwdev, s8 txpwr_mac)
 966{
 967	const struct rtw89_chip_info *chip = rtwdev->chip;
 968
 969	return txpwr_mac << (chip->txpwr_factor_bb - chip->txpwr_factor_mac);
 970}
 971
 972void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link);
 973void rtw89_phy_ra_update(struct rtw89_dev *rtwdev);
 974void rtw89_phy_ra_update_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta,
 975			     u32 changed);
 976void rtw89_phy_ra_update_sta_link(struct rtw89_dev *rtwdev,
 977				  struct rtw89_sta_link *rtwsta_link,
 978				  u32 changed);
 979void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
 980				struct ieee80211_vif *vif,
 981				const struct cfg80211_bitrate_mask *mask);
 982bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func);
 983void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
 984			  u32 len, u8 class, u8 func);
 985int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev,
 986				    enum rtw89_phy_idx phy_idx,
 987				    unsigned int ms);
 988int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev,
 989				enum rtw89_phy_idx phy_idx,
 990				const struct rtw89_chan *chan,
 991				enum rtw89_tssi_mode tssi_mode,
 992				unsigned int ms);
 993int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev,
 994			       enum rtw89_phy_idx phy_idx,
 995			       const struct rtw89_chan *chan,
 996			       unsigned int ms);
 997int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev,
 998			       enum rtw89_phy_idx phy_idx,
 999			       const struct rtw89_chan *chan,
1000			       unsigned int ms);
1001int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev,
1002				  enum rtw89_phy_idx phy_idx,
1003				  const struct rtw89_chan *chan,
1004				  unsigned int ms);
1005int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev,
1006				enum rtw89_phy_idx phy_idx,
1007				const struct rtw89_chan *chan,
1008				unsigned int ms);
1009int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev,
1010				 enum rtw89_phy_idx phy_idx,
1011				 const struct rtw89_chan *chan,
1012				 bool is_chl_k, unsigned int ms);
1013void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev,
1014					       enum rtw89_phy_idx phy,
1015					       const struct rtw89_chan *chan,
1016					       struct rtw89_h2c_rf_tssi *h2c);
1017void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev,
1018					      enum rtw89_phy_idx phy,
1019					      const struct rtw89_chan *chan,
1020					      struct rtw89_h2c_rf_tssi *h2c);
1021void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev);
1022void rtw89_phy_cfo_track_work(struct wiphy *wiphy, struct wiphy_work *work);
1023void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,
1024			 struct rtw89_rx_phy_ppdu *phy_ppdu);
1025void rtw89_phy_stat_track(struct rtw89_dev *rtwdev);
1026void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev);
1027void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1028			    u32 val);
1029void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb);
1030void rtw89_phy_dig(struct rtw89_dev *rtwdev);
1031void rtw89_phy_dig_suspend(struct rtw89_dev *rtwdev);
1032void rtw89_phy_dig_resume(struct rtw89_dev *rtwdev, bool restore);
1033void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev);
1034void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev,
1035			    struct rtw89_rx_phy_ppdu *phy_ppdu);
1036void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev);
1037void rtw89_phy_antdiv_work(struct wiphy *wiphy, struct wiphy_work *work);
1038void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev,
1039			     struct rtw89_vif_link *rtwvif_link);
1040void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
1041					  enum rtw89_mac_idx mac_idx,
1042					  enum rtw89_tssi_bandedge_cfg bandedge_cfg);
1043void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
1044void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev);
1045u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band);
1046void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx,
1047			   u8 *ch, enum nl80211_band *band);
1048void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev,
1049			    struct rtw89_bb_ctx *bb, bool scan);
1050void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev);
1051void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb);
1052enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev,
1053					   enum rtw89_phy_idx phy_idx);
1054enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev,
1055					 enum rtw89_phy_idx phy_idx);
1056u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev,
1057			 const struct rtw89_rfk_chan_desc *desc, u8 desc_nr,
1058			 const struct rtw89_chan *target_chan);
1059void rtw89_phy_nhm_setting_init(struct rtw89_dev *rtwdev);
1060void rtw89_phy_nhm_get_result(struct rtw89_dev *rtwdev, enum rtw89_band hw_band,
1061			      u16 ch_hw_value);
1062void rtw89_phy_nhm_trigger(struct rtw89_dev *rtwdev);
1063
1064#endif