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linux-6.19.14/drivers/net/wireless/realtek/rtw89/pci.h C 
   1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2/* Copyright(c) 2020  Realtek Corporation
   3 */
   4
   5#ifndef __RTW89_PCI_H__
   6#define __RTW89_PCI_H__
   7
   8#include "txrx.h"
   9
  10#define MDIO_PG0_G1 0
  11#define MDIO_PG1_G1 1
  12#define MDIO_PG0_G2 2
  13#define MDIO_PG1_G2 3
  14#define RAC_CTRL_PPR			0x00
  15#define RAC_ANA03			0x03
  16#define OOBS_SEN_MASK			GENMASK(5, 1)
  17#define RAC_ANA09			0x09
  18#define BAC_OOBS_SEL			BIT(4)
  19#define RAC_ANA0A			0x0A
  20#define B_BAC_EQ_SEL			BIT(5)
  21#define RAC_ANA0B			0x0B
  22#define MANUAL_LVL_MASK			GENMASK(8, 5)
  23#define RAC_ANA0C			0x0C
  24#define B_PCIE_BIT_PSAVE		BIT(15)
  25#define RAC_ANA0D			0x0D
  26#define OFFSET_CAL_MODE			BIT(13)
  27#define BAC_RX_TEST_EN			BIT(6)
  28#define RAC_ANA10			0x10
  29#define ADDR_SEL_MASK		        GENMASK(9, 4)
  30#define ADDR_SEL_VAL		        0x3C
  31#define ADDR_SEL_PINOUT_DIS_VAL		0x3C4
  32#define B_PCIE_BIT_PINOUT_DIS		BIT(3)
  33#define RAC_REG_REV2			0x1B
  34#define BAC_CMU_EN_DLY_MASK		GENMASK(15, 12)
  35#define PCIE_DPHY_DLY_25US		0x1
  36#define RAC_ANA19			0x19
  37#define B_PCIE_BIT_RD_SEL		BIT(2)
  38#define RAC_REG_FLD_0			0x1D
  39#define BAC_AUTOK_N_MASK		GENMASK(3, 2)
  40#define PCIE_AUTOK_4			0x3
  41#define RAC_ANA1E			0x1E
  42#define RAC_ANA1E_G1_VAL		0x66EA
  43#define RAC_ANA1E_G2_VAL		0x6EEA
  44#define RAC_ANA1F			0x1F
  45#define OOBS_LEVEL_MASK			GENMASK(12, 8)
  46#define OFFSET_CAL_MASK		        GENMASK(7, 4)
  47#define RAC_ANA24			0x24
  48#define B_AX_DEGLITCH			GENMASK(11, 8)
  49#define RAC_ANA26			0x26
  50#define B_AX_RXEN			GENMASK(15, 14)
  51#define RAC_ANA2E			0x2E
  52#define RAC_ANA2E_VAL			0xFFFE
  53#define RAC_CTRL_PPR_V1			0x30
  54#define B_AX_CLK_CALIB_EN		BIT(12)
  55#define B_AX_CALIB_EN			BIT(13)
  56#define B_AX_DIV			GENMASK(15, 14)
  57#define RAC_SET_PPR_V1			0x31
  58
  59#define R_AX_DBI_FLAG			0x1090
  60#define B_AX_DBI_RFLAG			BIT(17)
  61#define B_AX_DBI_WFLAG			BIT(16)
  62#define B_AX_DBI_WREN_MSK		GENMASK(15, 12)
  63#define B_AX_DBI_ADDR_MSK		GENMASK(11, 2)
  64#define B_AX_DBI_2LSB			GENMASK(1, 0)
  65#define R_AX_DBI_WDATA			0x1094
  66#define R_AX_DBI_RDATA			0x1098
  67
  68#define R_AX_MDIO_WDATA			0x10A4
  69#define R_AX_MDIO_RDATA			0x10A6
  70
  71#define R_AX_PCIE_PS_CTRL_V1		0x3008
  72#define B_AX_CMAC_EXIT_L1_EN		BIT(7)
  73#define B_AX_DMAC0_EXIT_L1_EN		BIT(6)
  74#define B_AX_SEL_XFER_PENDING		BIT(3)
  75#define B_AX_SEL_REQ_ENTR_L1		BIT(2)
  76#define B_AX_SEL_REQ_EXIT_L1		BIT(0)
  77
  78#define R_AX_PCIE_MIX_CFG_V1		0x300C
  79#define B_AX_ASPM_CTRL_L1		BIT(17)
  80#define B_AX_ASPM_CTRL_L0		BIT(16)
  81#define B_AX_ASPM_CTRL_MASK		GENMASK(17, 16)
  82#define B_AX_XFER_PENDING_FW		BIT(11)
  83#define B_AX_XFER_PENDING		BIT(10)
  84#define B_AX_REQ_EXIT_L1		BIT(9)
  85#define B_AX_REQ_ENTR_L1		BIT(8)
  86#define B_AX_L1SUB_DISABLE		BIT(0)
  87
  88#define R_AX_L1_CLK_CTRL		0x3010
  89#define B_AX_CLK_REQ_N			BIT(1)
  90
  91#define R_AX_PCIE_BG_CLR		0x303C
  92#define B_AX_BG_CLR_ASYNC_M3		BIT(4)
  93
  94#define R_AX_PCIE_LAT_CTRL		0x3044
  95#define B_AX_CLK_REQ_SEL_OPT		BIT(1)
  96#define B_AX_CLK_REQ_SEL		BIT(0)
  97
  98#define R_AX_PCIE_IO_RCY_M1 0x3100
  99#define B_AX_PCIE_IO_RCY_P_M1 BIT(5)
 100#define B_AX_PCIE_IO_RCY_WDT_P_M1 BIT(4)
 101#define B_AX_PCIE_IO_RCY_WDT_MODE_M1 BIT(3)
 102#define B_AX_PCIE_IO_RCY_TRIG_M1 BIT(0)
 103
 104#define R_AX_PCIE_WDT_TIMER_M1 0x3104
 105#define B_AX_PCIE_WDT_TIMER_M1_MASK GENMASK(31, 0)
 106
 107#define R_AX_PCIE_IO_RCY_M2 0x310C
 108#define B_AX_PCIE_IO_RCY_P_M2 BIT(5)
 109#define B_AX_PCIE_IO_RCY_WDT_P_M2 BIT(4)
 110#define B_AX_PCIE_IO_RCY_WDT_MODE_M2 BIT(3)
 111#define B_AX_PCIE_IO_RCY_TRIG_M2 BIT(0)
 112
 113#define R_AX_PCIE_WDT_TIMER_M2 0x3110
 114#define B_AX_PCIE_WDT_TIMER_M2_MASK GENMASK(31, 0)
 115
 116#define R_AX_PCIE_IO_RCY_E0 0x3118
 117#define B_AX_PCIE_IO_RCY_P_E0 BIT(5)
 118#define B_AX_PCIE_IO_RCY_WDT_P_E0 BIT(4)
 119#define B_AX_PCIE_IO_RCY_WDT_MODE_E0 BIT(3)
 120#define B_AX_PCIE_IO_RCY_TRIG_E0 BIT(0)
 121
 122#define R_AX_PCIE_WDT_TIMER_E0 0x311C
 123#define B_AX_PCIE_WDT_TIMER_E0_MASK GENMASK(31, 0)
 124
 125#define R_AX_PCIE_IO_RCY_S1 0x3124
 126#define B_AX_PCIE_IO_RCY_RP_S1 BIT(7)
 127#define B_AX_PCIE_IO_RCY_WP_S1 BIT(6)
 128#define B_AX_PCIE_IO_RCY_WDT_RP_S1 BIT(5)
 129#define B_AX_PCIE_IO_RCY_WDT_WP_S1 BIT(4)
 130#define B_AX_PCIE_IO_RCY_WDT_MODE_S1 BIT(3)
 131#define B_AX_PCIE_IO_RCY_RTRIG_S1 BIT(1)
 132#define B_AX_PCIE_IO_RCY_WTRIG_S1 BIT(0)
 133
 134#define R_AX_PCIE_WDT_TIMER_S1 0x3128
 135#define B_AX_PCIE_WDT_TIMER_S1_MASK GENMASK(31, 0)
 136
 137#define R_RAC_DIRECT_OFFSET_G1 0x3800
 138#define FILTER_OUT_EQ_MASK GENMASK(14, 10)
 139#define R_RAC_DIRECT_OFFSET_G2 0x3880
 140#define REG_FILTER_OUT_MASK GENMASK(6, 2)
 141#define RAC_MULT 2
 142
 143#define R_RAC_DIRECT_OFFSET_BE_LANE0_G1 0x3800
 144#define R_RAC_DIRECT_OFFSET_BE_LANE1_G1 0x3880
 145#define R_RAC_DIRECT_OFFSET_BE_LANE0_G2 0x3900
 146#define R_RAC_DIRECT_OFFSET_BE_LANE1_G2 0x3980
 147
 148#define RTW89_PCI_WR_RETRY_CNT		20
 149
 150/* Interrupts */
 151#define R_AX_HIMR0 0x01A0
 152#define B_AX_WDT_TIMEOUT_INT_EN BIT(22)
 153#define B_AX_HALT_C2H_INT_EN BIT(21)
 154#define R_AX_HISR0 0x01A4
 155
 156#define R_AX_HIMR1 0x01A8
 157#define B_AX_GPIO18_INT_EN BIT(2)
 158#define B_AX_GPIO17_INT_EN BIT(1)
 159#define B_AX_GPIO16_INT_EN BIT(0)
 160
 161#define R_AX_HISR1 0x01AC
 162#define B_AX_GPIO18_INT BIT(2)
 163#define B_AX_GPIO17_INT BIT(1)
 164#define B_AX_GPIO16_INT BIT(0)
 165
 166#define R_AX_MDIO_CFG			0x10A0
 167#define B_AX_MDIO_PHY_ADDR_MASK		GENMASK(13, 12)
 168#define B_AX_MDIO_RFLAG			BIT(9)
 169#define B_AX_MDIO_WFLAG			BIT(8)
 170#define B_AX_MDIO_ADDR_MASK		GENMASK(4, 0)
 171
 172#define R_AX_PCIE_HIMR00	0x10B0
 173#define R_AX_HAXI_HIMR00 0x10B0
 174#define B_AX_HC00ISR_IND_INT_EN		BIT(27)
 175#define B_AX_HD1ISR_IND_INT_EN		BIT(26)
 176#define B_AX_HD0ISR_IND_INT_EN		BIT(25)
 177#define B_AX_HS0ISR_IND_INT_EN		BIT(24)
 178#define B_AX_HS0ISR_IND_INT_EN_WKARND	BIT(23)
 179#define B_AX_RETRAIN_INT_EN		BIT(21)
 180#define B_AX_RPQBD_FULL_INT_EN		BIT(20)
 181#define B_AX_RDU_INT_EN			BIT(19)
 182#define B_AX_RXDMA_STUCK_INT_EN		BIT(18)
 183#define B_AX_TXDMA_STUCK_INT_EN		BIT(17)
 184#define B_AX_PCIE_HOTRST_INT_EN		BIT(16)
 185#define B_AX_PCIE_FLR_INT_EN		BIT(15)
 186#define B_AX_PCIE_PERST_INT_EN		BIT(14)
 187#define B_AX_TXDMA_CH12_INT_EN		BIT(13)
 188#define B_AX_TXDMA_CH9_INT_EN		BIT(12)
 189#define B_AX_TXDMA_CH8_INT_EN		BIT(11)
 190#define B_AX_TXDMA_ACH7_INT_EN		BIT(10)
 191#define B_AX_TXDMA_ACH6_INT_EN		BIT(9)
 192#define B_AX_TXDMA_ACH5_INT_EN		BIT(8)
 193#define B_AX_TXDMA_ACH4_INT_EN		BIT(7)
 194#define B_AX_TXDMA_ACH3_INT_EN		BIT(6)
 195#define B_AX_TXDMA_ACH2_INT_EN		BIT(5)
 196#define B_AX_TXDMA_ACH1_INT_EN		BIT(4)
 197#define B_AX_TXDMA_ACH0_INT_EN		BIT(3)
 198#define B_AX_RPQDMA_INT_EN		BIT(2)
 199#define B_AX_RXP1DMA_INT_EN		BIT(1)
 200#define B_AX_RXDMA_INT_EN		BIT(0)
 201
 202#define R_AX_PCIE_HISR00	0x10B4
 203#define R_AX_HAXI_HISR00 0x10B4
 204#define B_AX_HC00ISR_IND_INT		BIT(27)
 205#define B_AX_HD1ISR_IND_INT		BIT(26)
 206#define B_AX_HD0ISR_IND_INT		BIT(25)
 207#define B_AX_HS0ISR_IND_INT		BIT(24)
 208#define B_AX_RETRAIN_INT		BIT(21)
 209#define B_AX_RPQBD_FULL_INT		BIT(20)
 210#define B_AX_RDU_INT			BIT(19)
 211#define B_AX_RXDMA_STUCK_INT		BIT(18)
 212#define B_AX_TXDMA_STUCK_INT		BIT(17)
 213#define B_AX_PCIE_HOTRST_INT		BIT(16)
 214#define B_AX_PCIE_FLR_INT		BIT(15)
 215#define B_AX_PCIE_PERST_INT		BIT(14)
 216#define B_AX_TXDMA_CH12_INT		BIT(13)
 217#define B_AX_TXDMA_CH9_INT		BIT(12)
 218#define B_AX_TXDMA_CH8_INT		BIT(11)
 219#define B_AX_TXDMA_ACH7_INT		BIT(10)
 220#define B_AX_TXDMA_ACH6_INT		BIT(9)
 221#define B_AX_TXDMA_ACH5_INT		BIT(8)
 222#define B_AX_TXDMA_ACH4_INT		BIT(7)
 223#define B_AX_TXDMA_ACH3_INT		BIT(6)
 224#define B_AX_TXDMA_ACH2_INT		BIT(5)
 225#define B_AX_TXDMA_ACH1_INT		BIT(4)
 226#define B_AX_TXDMA_ACH0_INT		BIT(3)
 227#define B_AX_RPQDMA_INT			BIT(2)
 228#define B_AX_RXP1DMA_INT		BIT(1)
 229#define B_AX_RXDMA_INT			BIT(0)
 230
 231#define R_AX_HAXI_IDCT_MSK 0x10B8
 232#define B_AX_TXBD_LEN0_ERR_IDCT_MSK BIT(3)
 233#define B_AX_TXBD_4KBOUND_ERR_IDCT_MSK BIT(2)
 234#define B_AX_RXMDA_STUCK_IDCT_MSK BIT(1)
 235#define B_AX_TXMDA_STUCK_IDCT_MSK BIT(0)
 236
 237#define R_AX_HAXI_IDCT 0x10BC
 238#define B_AX_TXBD_LEN0_ERR_IDCT BIT(3)
 239#define B_AX_TXBD_4KBOUND_ERR_IDCT BIT(2)
 240#define B_AX_RXMDA_STUCK_IDCT BIT(1)
 241#define B_AX_TXMDA_STUCK_IDCT BIT(0)
 242
 243#define R_AX_HAXI_HIMR10 0x11E0
 244#define B_AX_TXDMA_CH11_INT_EN_V1 BIT(1)
 245#define B_AX_TXDMA_CH10_INT_EN_V1 BIT(0)
 246
 247#define R_AX_PCIE_HIMR10	0x13B0
 248#define B_AX_HC10ISR_IND_INT_EN		BIT(28)
 249#define B_AX_TXDMA_CH11_INT_EN		BIT(12)
 250#define B_AX_TXDMA_CH10_INT_EN		BIT(11)
 251
 252#define R_AX_PCIE_HISR10	0x13B4
 253#define B_AX_HC10ISR_IND_INT		BIT(28)
 254#define B_AX_TXDMA_CH11_INT		BIT(12)
 255#define B_AX_TXDMA_CH10_INT		BIT(11)
 256
 257#define R_AX_PCIE_HIMR00_V1 0x30B0
 258#define B_AX_HCI_AXIDMA_INT_EN BIT(29)
 259#define B_AX_HC00ISR_IND_INT_EN_V1 BIT(28)
 260#define B_AX_HD1ISR_IND_INT_EN_V1 BIT(27)
 261#define B_AX_HD0ISR_IND_INT_EN_V1 BIT(26)
 262#define B_AX_HS1ISR_IND_INT_EN BIT(25)
 263#define B_AX_PCIE_DBG_STE_INT_EN BIT(13)
 264
 265#define R_AX_PCIE_HISR00_V1 0x30B4
 266#define B_AX_HCI_AXIDMA_INT BIT(29)
 267#define B_AX_HC00ISR_IND_INT_V1 BIT(28)
 268#define B_AX_HD1ISR_IND_INT_V1 BIT(27)
 269#define B_AX_HD0ISR_IND_INT_V1 BIT(26)
 270#define B_AX_HS1ISR_IND_INT BIT(25)
 271#define B_AX_PCIE_DBG_STE_INT BIT(13)
 272
 273#define R_BE_PCIE_FRZ_CLK 0x3004
 274#define B_BE_PCIE_FRZ_MAC_HW_RST BIT(31)
 275#define B_BE_PCIE_FRZ_CFG_SPC_RST BIT(30)
 276#define B_BE_PCIE_FRZ_ELBI_RST BIT(29)
 277#define B_BE_PCIE_MAC_IS_ACTIVE BIT(28)
 278#define B_BE_PCIE_FRZ_RTK_HW_RST BIT(27)
 279#define B_BE_PCIE_FRZ_REG_RST BIT(26)
 280#define B_BE_PCIE_FRZ_ANA_RST BIT(25)
 281#define B_BE_PCIE_FRZ_WLAN_RST BIT(24)
 282#define B_BE_PCIE_FRZ_FLR_RST BIT(23)
 283#define B_BE_PCIE_FRZ_RET_NON_STKY_RST BIT(22)
 284#define B_BE_PCIE_FRZ_RET_STKY_RST BIT(21)
 285#define B_BE_PCIE_FRZ_NON_STKY_RST BIT(20)
 286#define B_BE_PCIE_FRZ_STKY_RST BIT(19)
 287#define B_BE_PCIE_FRZ_RET_CORE_RST BIT(18)
 288#define B_BE_PCIE_FRZ_PWR_RST BIT(17)
 289#define B_BE_PCIE_FRZ_PERST_RST BIT(16)
 290#define B_BE_PCIE_FRZ_PHY_ALOAD BIT(15)
 291#define B_BE_PCIE_FRZ_PHY_HW_RST BIT(14)
 292#define B_BE_PCIE_DBG_CLK BIT(4)
 293#define B_BE_PCIE_EN_CLK BIT(3)
 294#define B_BE_PCIE_DBI_ACLK_ACT BIT(2)
 295#define B_BE_PCIE_S1_ACLK_ACT BIT(1)
 296#define B_BE_PCIE_EN_AUX_CLK BIT(0)
 297
 298#define R_BE_PCIE_PS_CTRL 0x3008
 299#define B_BE_RSM_L0S_EN BIT(8)
 300#define B_BE_CMAC_EXIT_L1_EN BIT(7)
 301#define B_BE_DMAC0_EXIT_L1_EN BIT(6)
 302#define B_BE_FORCE_L0 BIT(5)
 303#define B_BE_DBI_RO_WR_DISABLE BIT(4)
 304#define B_BE_SEL_XFER_PENDING BIT(3)
 305#define B_BE_SEL_REQ_ENTR_L1 BIT(2)
 306#define B_BE_PCIE_EN_SWENT_L23 BIT(1)
 307#define B_BE_SEL_REQ_EXIT_L1 BIT(0)
 308
 309#define R_BE_PCIE_MIX_CFG 0x300C
 310#define B_BE_L1SS_TIMEOUT_CTRL BIT(18)
 311#define B_BE_ASPM_CTRL_L1 BIT(17)
 312#define B_BE_ASPM_CTRL_L0 BIT(16)
 313#define B_BE_RTK_ASPM_CTRL_MASK GENMASK(17, 16)
 314#define B_BE_XFER_PENDING_FW BIT(11)
 315#define B_BE_XFER_PENDING BIT(10)
 316#define B_BE_REQ_EXIT_L1 BIT(9)
 317#define B_BE_REQ_ENTR_L1 BIT(8)
 318#define B_BE_L1SUB_ENABLE BIT(0)
 319
 320#define R_BE_L1_CLK_CTRL 0x3010
 321#define B_BE_RAS_SD_HOLD_LTSSM BIT(12)
 322#define B_BE_CLK_REQ_N BIT(1)
 323#define B_BE_CLK_PM_EN BIT(0)
 324
 325#define R_BE_PCIE_LAT_CTRL 0x3044
 326#define B_BE_ELBI_PHY_REMAP_MASK GENMASK(29, 24)
 327#define B_BE_SYS_SUS_L12_EN BIT(17)
 328#define B_BE_MDIO_S_EN BIT(16)
 329#define B_BE_SYM_AUX_CLK_SEL BIT(15)
 330#define B_BE_RTK_LDO_POWER_LATENCY_MASK GENMASK(11, 10)
 331#define B_BE_RTK_LDO_BIAS_LATENCY_MASK GENMASK(9, 8)
 332#define B_BE_CLK_REQ_LAT_MASK GENMASK(7, 4)
 333#define B_BE_RTK_PM_SEL_OPT BIT(1)
 334#define B_BE_CLK_REQ_SEL BIT(0)
 335
 336#define R_BE_PCIE_HIMR0 0x30B0
 337#define B_BE_PCIE_HB1_IND_INTA_IMR BIT(31)
 338#define B_BE_PCIE_HB0_IND_INTA_IMR BIT(30)
 339#define B_BE_HCI_AXIDMA_INTA_IMR BIT(29)
 340#define B_BE_HC0_IND_INTA_IMR BIT(28)
 341#define B_BE_HD1_IND_INTA_IMR BIT(27)
 342#define B_BE_HD0_IND_INTA_IMR BIT(26)
 343#define B_BE_HS1_IND_INTA_IMR BIT(25)
 344#define B_BE_HS0_IND_INTA_IMR BIT(24)
 345#define B_BE_PCIE_HOTRST_INT_EN BIT(16)
 346#define B_BE_PCIE_FLR_INT_EN BIT(15)
 347#define B_BE_PCIE_PERST_INT_EN BIT(14)
 348#define B_BE_PCIE_DBG_STE_INT_EN BIT(13)
 349#define B_BE_HB1_IND_INT_EN0 BIT(9)
 350#define B_BE_HB0_IND_INT_EN0 BIT(8)
 351#define B_BE_HC1_IND_INT_EN0 BIT(7)
 352#define B_BE_HCI_AXIDMA_INT_EN0 BIT(5)
 353#define B_BE_HC0_IND_INT_EN0 BIT(4)
 354#define B_BE_HD1_IND_INT_EN0 BIT(3)
 355#define B_BE_HD0_IND_INT_EN0 BIT(2)
 356#define B_BE_HS1_IND_INT_EN0 BIT(1)
 357#define B_BE_HS0_IND_INT_EN0 BIT(0)
 358
 359#define R_BE_PCIE_HISR 0x30B4
 360#define B_BE_PCIE_HOTRST_INT BIT(16)
 361#define B_BE_PCIE_FLR_INT BIT(15)
 362#define B_BE_PCIE_PERST_INT BIT(14)
 363#define B_BE_PCIE_DBG_STE_INT BIT(13)
 364#define B_BE_HB1IMR_IND BIT(9)
 365#define B_BE_HB0IMR_IND BIT(8)
 366#define B_BE_HC1ISR_IND_INT BIT(7)
 367#define B_BE_HCI_AXIDMA_INT BIT(5)
 368#define B_BE_HC0ISR_IND_INT BIT(4)
 369#define B_BE_HD1ISR_IND_INT BIT(3)
 370#define B_BE_HD0ISR_IND_INT BIT(2)
 371#define B_BE_HS1ISR_IND_INT BIT(1)
 372#define B_BE_HS0ISR_IND_INT BIT(0)
 373
 374#define R_BE_PCIE_DMA_IMR_0_V1 0x30B8
 375#define B_BE_PCIE_RDU_CH7_IMR BIT(31)
 376#define B_BE_PCIE_RDU_CH6_IMR BIT(30)
 377#define B_BE_PCIE_RDU_CH5_IMR BIT(29)
 378#define B_BE_PCIE_RDU_CH4_IMR BIT(28)
 379#define B_BE_PCIE_RDU_CH3_IMR BIT(27)
 380#define B_BE_PCIE_RDU_CH2_IMR BIT(26)
 381#define B_BE_PCIE_RDU_CH1_IMR BIT(25)
 382#define B_BE_PCIE_RDU_CH0_IMR BIT(24)
 383#define B_BE_PCIE_RX_RX1P1_IMR0_V1 BIT(23)
 384#define B_BE_PCIE_RX_RX0P1_IMR0_V1 BIT(22)
 385#define B_BE_PCIE_RX_ROQ1_IMR0_V1 BIT(21)
 386#define B_BE_PCIE_RX_RPQ1_IMR0_V1 BIT(20)
 387#define B_BE_PCIE_RX_RX1P2_IMR0_V1 BIT(19)
 388#define B_BE_PCIE_RX_ROQ0_IMR0_V1 BIT(18)
 389#define B_BE_PCIE_RX_RPQ0_IMR0_V1 BIT(17)
 390#define B_BE_PCIE_RX_RX0P2_IMR0_V1 BIT(16)
 391#define B_BE_PCIE_TX_CH14_IMR0 BIT(14)
 392#define B_BE_PCIE_TX_CH13_IMR0 BIT(13)
 393#define B_BE_PCIE_TX_CH12_IMR0 BIT(12)
 394#define B_BE_PCIE_TX_CH11_IMR0 BIT(11)
 395#define B_BE_PCIE_TX_CH10_IMR0 BIT(10)
 396#define B_BE_PCIE_TX_CH9_IMR0 BIT(9)
 397#define B_BE_PCIE_TX_CH8_IMR0 BIT(8)
 398#define B_BE_PCIE_TX_CH7_IMR0 BIT(7)
 399#define B_BE_PCIE_TX_CH6_IMR0 BIT(6)
 400#define B_BE_PCIE_TX_CH5_IMR0 BIT(5)
 401#define B_BE_PCIE_TX_CH4_IMR0 BIT(4)
 402#define B_BE_PCIE_TX_CH3_IMR0 BIT(3)
 403#define B_BE_PCIE_TX_CH2_IMR0 BIT(2)
 404#define B_BE_PCIE_TX_CH1_IMR0 BIT(1)
 405#define B_BE_PCIE_TX_CH0_IMR0 BIT(0)
 406
 407#define R_BE_PCIE_DMA_ISR 0x30BC
 408#define B_BE_PCIE_RDU_CH7_INT BIT(31)
 409#define B_BE_PCIE_RDU_CH6_INT BIT(30)
 410#define B_BE_PCIE_RDU_CH5_INT BIT(29)
 411#define B_BE_PCIE_RDU_CH4_INT BIT(28)
 412#define B_BE_PCIE_RDU_CH3_INT BIT(27)
 413#define B_BE_PCIE_RDU_CH2_INT BIT(26)
 414#define B_BE_PCIE_RDU_CH1_INT BIT(25)
 415#define B_BE_PCIE_RDU_CH0_INT BIT(24)
 416#define B_BE_PCIE_RX_RX1P1_ISR_V1 BIT(23)
 417#define B_BE_PCIE_RX_RX0P1_ISR_V1 BIT(22)
 418#define B_BE_PCIE_RX_ROQ1_ISR_V1 BIT(21)
 419#define B_BE_PCIE_RX_RPQ1_ISR_V1 BIT(20)
 420#define B_BE_PCIE_RX_RX1P2_ISR_V1 BIT(19)
 421#define B_BE_PCIE_RX_ROQ0_ISR_V1 BIT(18)
 422#define B_BE_PCIE_RX_RPQ0_ISR_V1 BIT(17)
 423#define B_BE_PCIE_RX_RX0P2_ISR_V1 BIT(16)
 424#define B_BE_PCIE_TX_CH14_ISR BIT(14)
 425#define B_BE_PCIE_TX_CH13_ISR BIT(13)
 426#define B_BE_PCIE_TX_CH12_ISR BIT(12)
 427#define B_BE_PCIE_TX_CH11_ISR BIT(11)
 428#define B_BE_PCIE_TX_CH10_ISR BIT(10)
 429#define B_BE_PCIE_TX_CH9_ISR BIT(9)
 430#define B_BE_PCIE_TX_CH8_ISR BIT(8)
 431#define B_BE_PCIE_TX_CH7_ISR BIT(7)
 432#define B_BE_PCIE_TX_CH6_ISR BIT(6)
 433#define B_BE_PCIE_TX_CH5_ISR BIT(5)
 434#define B_BE_PCIE_TX_CH4_ISR BIT(4)
 435#define B_BE_PCIE_TX_CH3_ISR BIT(3)
 436#define B_BE_PCIE_TX_CH2_ISR BIT(2)
 437#define B_BE_PCIE_TX_CH1_ISR BIT(1)
 438#define B_BE_PCIE_TX_CH0_ISR BIT(0)
 439
 440#define R_BE_HAXI_HIMR00 0xB0B0
 441#define B_BE_RDU_CH5_INT_IMR_V1 BIT(30)
 442#define B_BE_RDU_CH4_INT_IMR_V1 BIT(29)
 443#define B_BE_RDU_CH3_INT_IMR_V1 BIT(28)
 444#define B_BE_RDU_CH2_INT_IMR_V1 BIT(27)
 445#define B_BE_RDU_CH1_INT_EN_V2 BIT(27)
 446#define B_BE_RDU_CH1_INT_IMR_V1 BIT(26)
 447#define B_BE_RDU_CH0_INT_EN_V2 BIT(26)
 448#define B_BE_RDU_CH0_INT_IMR_V1 BIT(25)
 449#define B_BE_RXDMA_STUCK_INT_EN_V2 BIT(25)
 450#define B_BE_RXDMA_STUCK_INT_EN_V1 BIT(24)
 451#define B_BE_TXDMA_STUCK_INT_EN_V2 BIT(24)
 452#define B_BE_TXDMA_STUCK_INT_EN_V1 BIT(23)
 453#define B_BE_TXDMA_CH14_INT_EN_V1 BIT(22)
 454#define B_BE_TXDMA_CH13_INT_EN_V1 BIT(21)
 455#define B_BE_TXDMA_CH12_INT_EN_V1 BIT(20)
 456#define B_BE_TXDMA_CH11_INT_EN_V1 BIT(19)
 457#define B_BE_TXDMA_CH10_INT_EN_V1 BIT(18)
 458#define B_BE_TXDMA_CH9_INT_EN_V1 BIT(17)
 459#define B_BE_TXDMA_CH8_INT_EN_V1 BIT(16)
 460#define B_BE_TXDMA_CH7_INT_EN_V1 BIT(15)
 461#define B_BE_TXDMA_CH6_INT_EN_V1 BIT(14)
 462#define B_BE_TXDMA_CH5_INT_EN_V1 BIT(13)
 463#define B_BE_TXDMA_CH4_INT_EN_V1 BIT(12)
 464#define B_BE_TXDMA_CH3_INT_EN_V1 BIT(11)
 465#define B_BE_TXDMA_CH2_INT_EN_V1 BIT(10)
 466#define B_BE_TXDMA_CH1_INT_EN_V1 BIT(9)
 467#define B_BE_TXDMA_CH0_INT_EN_V1 BIT(8)
 468#define B_BE_RX1P1DMA_INT_EN_V1 BIT(7)
 469#define B_BE_RX0P1DMA_INT_EN_V1 BIT(6)
 470#define B_BE_RO1DMA_INT_EN BIT(5)
 471#define B_BE_RP1DMA_INT_EN BIT(4)
 472#define B_BE_RX1DMA_INT_EN BIT(3)
 473#define B_BE_RO0DMA_INT_EN BIT(2)
 474#define B_BE_RP0DMA_INT_EN BIT(1)
 475#define B_BE_RX0DMA_INT_EN BIT(0)
 476
 477#define R_BE_HAXI_HISR00 0xB0B4
 478#define B_BE_RDU_CH5_INT_V1 BIT(30)
 479#define B_BE_RDU_CH4_INT_V1 BIT(29)
 480#define B_BE_RDU_CH3_INT_V1 BIT(28)
 481#define B_BE_RDU_CH2_INT_V1 BIT(27)
 482#define B_BE_RDU_CH1_INT_V2 BIT(27)
 483#define B_BE_RDU_CH1_INT_V1 BIT(26)
 484#define B_BE_RDU_CH0_INT_V2 BIT(26)
 485#define B_BE_RDU_CH0_INT_V1 BIT(25)
 486#define B_BE_RXDMA_STUCK_INT_V2 BIT(25)
 487#define B_BE_RXDMA_STUCK_INT_V1 BIT(24)
 488#define B_BE_TXDMA_STUCK_INT_V2 BIT(24)
 489#define B_BE_TXDMA_STUCK_INT_V1 BIT(23)
 490#define B_BE_TXDMA_CH14_INT_V1 BIT(22)
 491#define B_BE_TXDMA_CH13_INT_V1 BIT(21)
 492#define B_BE_TXDMA_CH12_INT_V1 BIT(20)
 493#define B_BE_TXDMA_CH11_INT_V1 BIT(19)
 494#define B_BE_TXDMA_CH10_INT_V1 BIT(18)
 495#define B_BE_TXDMA_CH9_INT_V1 BIT(17)
 496#define B_BE_TXDMA_CH8_INT_V1 BIT(16)
 497#define B_BE_TXDMA_CH7_INT_V1 BIT(15)
 498#define B_BE_TXDMA_CH6_INT_V1 BIT(14)
 499#define B_BE_TXDMA_CH5_INT_V1 BIT(13)
 500#define B_BE_TXDMA_CH4_INT_V1 BIT(12)
 501#define B_BE_TXDMA_CH3_INT_V1 BIT(11)
 502#define B_BE_TXDMA_CH2_INT_V1 BIT(10)
 503#define B_BE_TXDMA_CH1_INT_V1 BIT(9)
 504#define B_BE_TXDMA_CH0_INT_V1 BIT(8)
 505#define B_BE_RX1P1DMA_INT_V1 BIT(7)
 506#define B_BE_RX0P1DMA_INT_V1 BIT(6)
 507#define B_BE_RO1DMA_INT BIT(5)
 508#define B_BE_RP1DMA_INT BIT(4)
 509#define B_BE_RX1DMA_INT BIT(3)
 510#define B_BE_RO0DMA_INT BIT(2)
 511#define B_BE_RP0DMA_INT BIT(1)
 512#define B_BE_RX0DMA_INT BIT(0)
 513
 514/* TX/RX */
 515#define R_AX_DRV_FW_HSK_0	0x01B0
 516#define R_AX_DRV_FW_HSK_1	0x01B4
 517#define R_AX_DRV_FW_HSK_2	0x01B8
 518#define R_AX_DRV_FW_HSK_3	0x01BC
 519#define R_AX_DRV_FW_HSK_4	0x01C0
 520#define R_AX_DRV_FW_HSK_5	0x01C4
 521#define R_AX_DRV_FW_HSK_6	0x01C8
 522#define R_AX_DRV_FW_HSK_7	0x01CC
 523
 524#define R_AX_RXQ_RXBD_IDX	0x1050
 525#define R_AX_RPQ_RXBD_IDX	0x1054
 526#define R_AX_ACH0_TXBD_IDX	0x1058
 527#define R_AX_ACH1_TXBD_IDX	0x105C
 528#define R_AX_ACH2_TXBD_IDX	0x1060
 529#define R_AX_ACH3_TXBD_IDX	0x1064
 530#define R_AX_ACH4_TXBD_IDX	0x1068
 531#define R_AX_ACH5_TXBD_IDX	0x106C
 532#define R_AX_ACH6_TXBD_IDX	0x1070
 533#define R_AX_ACH7_TXBD_IDX	0x1074
 534#define R_AX_CH8_TXBD_IDX	0x1078 /* Management Queue band 0 */
 535#define R_AX_CH9_TXBD_IDX	0x107C /* HI Queue band 0 */
 536#define R_AX_CH10_TXBD_IDX	0x137C /* Management Queue band 1 */
 537#define R_AX_CH11_TXBD_IDX	0x1380 /* HI Queue band 1 */
 538#define R_AX_CH12_TXBD_IDX	0x1080 /* FWCMD Queue */
 539#define R_AX_CH10_TXBD_IDX_V1	0x11D0
 540#define R_AX_CH11_TXBD_IDX_V1	0x11D4
 541#define R_AX_RXQ_RXBD_IDX_V1	0x1218
 542#define R_AX_RPQ_RXBD_IDX_V1	0x121C
 543#define TXBD_HW_IDX_MASK	GENMASK(27, 16)
 544#define TXBD_HOST_IDX_MASK	GENMASK(11, 0)
 545
 546#define R_AX_ACH0_TXBD_DESA_L	0x1110
 547#define R_AX_ACH0_TXBD_DESA_H	0x1114
 548#define R_AX_ACH1_TXBD_DESA_L	0x1118
 549#define R_AX_ACH1_TXBD_DESA_H	0x111C
 550#define R_AX_ACH2_TXBD_DESA_L	0x1120
 551#define R_AX_ACH2_TXBD_DESA_H	0x1124
 552#define R_AX_ACH3_TXBD_DESA_L	0x1128
 553#define R_AX_ACH3_TXBD_DESA_H	0x112C
 554#define R_AX_ACH4_TXBD_DESA_L	0x1130
 555#define R_AX_ACH4_TXBD_DESA_H	0x1134
 556#define R_AX_ACH5_TXBD_DESA_L	0x1138
 557#define R_AX_ACH5_TXBD_DESA_H	0x113C
 558#define R_AX_ACH6_TXBD_DESA_L	0x1140
 559#define R_AX_ACH6_TXBD_DESA_H	0x1144
 560#define R_AX_ACH7_TXBD_DESA_L	0x1148
 561#define R_AX_ACH7_TXBD_DESA_H	0x114C
 562#define R_AX_CH8_TXBD_DESA_L	0x1150
 563#define R_AX_CH8_TXBD_DESA_H	0x1154
 564#define R_AX_CH9_TXBD_DESA_L	0x1158
 565#define R_AX_CH9_TXBD_DESA_H	0x115C
 566#define R_AX_CH10_TXBD_DESA_L	0x1358
 567#define R_AX_CH10_TXBD_DESA_H	0x135C
 568#define R_AX_CH11_TXBD_DESA_L	0x1360
 569#define R_AX_CH11_TXBD_DESA_H	0x1364
 570#define R_AX_CH12_TXBD_DESA_L	0x1160
 571#define R_AX_CH12_TXBD_DESA_H	0x1164
 572#define R_AX_RXQ_RXBD_DESA_L	0x1100
 573#define R_AX_RXQ_RXBD_DESA_H	0x1104
 574#define R_AX_RPQ_RXBD_DESA_L	0x1108
 575#define R_AX_RPQ_RXBD_DESA_H	0x110C
 576#define R_AX_RXQ_RXBD_DESA_L_V1 0x1220
 577#define R_AX_RXQ_RXBD_DESA_H_V1 0x1224
 578#define R_AX_RPQ_RXBD_DESA_L_V1 0x1228
 579#define R_AX_RPQ_RXBD_DESA_H_V1 0x122C
 580#define R_AX_ACH0_TXBD_DESA_L_V1 0x1230
 581#define R_AX_ACH0_TXBD_DESA_H_V1 0x1234
 582#define R_AX_ACH1_TXBD_DESA_L_V1 0x1238
 583#define R_AX_ACH1_TXBD_DESA_H_V1 0x123C
 584#define R_AX_ACH2_TXBD_DESA_L_V1 0x1240
 585#define R_AX_ACH2_TXBD_DESA_H_V1 0x1244
 586#define R_AX_ACH3_TXBD_DESA_L_V1 0x1248
 587#define R_AX_ACH3_TXBD_DESA_H_V1 0x124C
 588#define R_AX_ACH4_TXBD_DESA_L_V1 0x1250
 589#define R_AX_ACH4_TXBD_DESA_H_V1 0x1254
 590#define R_AX_ACH5_TXBD_DESA_L_V1 0x1258
 591#define R_AX_ACH5_TXBD_DESA_H_V1 0x125C
 592#define R_AX_ACH6_TXBD_DESA_L_V1 0x1260
 593#define R_AX_ACH6_TXBD_DESA_H_V1 0x1264
 594#define R_AX_ACH7_TXBD_DESA_L_V1 0x1268
 595#define R_AX_ACH7_TXBD_DESA_H_V1 0x126C
 596#define R_AX_CH8_TXBD_DESA_L_V1 0x1270
 597#define R_AX_CH8_TXBD_DESA_H_V1 0x1274
 598#define R_AX_CH9_TXBD_DESA_L_V1 0x1278
 599#define R_AX_CH9_TXBD_DESA_H_V1 0x127C
 600#define R_AX_CH12_TXBD_DESA_L_V1 0x1280
 601#define R_AX_CH12_TXBD_DESA_H_V1 0x1284
 602#define R_AX_CH10_TXBD_DESA_L_V1 0x1458
 603#define R_AX_CH10_TXBD_DESA_H_V1 0x145C
 604#define R_AX_CH11_TXBD_DESA_L_V1 0x1460
 605#define R_AX_CH11_TXBD_DESA_H_V1 0x1464
 606#define B_AX_DESC_NUM_MSK		GENMASK(11, 0)
 607
 608#define R_AX_RXQ_RXBD_NUM	0x1020
 609#define R_AX_RPQ_RXBD_NUM	0x1022
 610#define R_AX_ACH0_TXBD_NUM	0x1024
 611#define R_AX_ACH1_TXBD_NUM	0x1026
 612#define R_AX_ACH2_TXBD_NUM	0x1028
 613#define R_AX_ACH3_TXBD_NUM	0x102A
 614#define R_AX_ACH4_TXBD_NUM	0x102C
 615#define R_AX_ACH5_TXBD_NUM	0x102E
 616#define R_AX_ACH6_TXBD_NUM	0x1030
 617#define R_AX_ACH7_TXBD_NUM	0x1032
 618#define R_AX_CH8_TXBD_NUM	0x1034
 619#define R_AX_CH9_TXBD_NUM	0x1036
 620#define R_AX_CH10_TXBD_NUM	0x1338
 621#define R_AX_CH11_TXBD_NUM	0x133A
 622#define R_AX_CH12_TXBD_NUM	0x1038
 623#define R_AX_RXQ_RXBD_NUM_V1	0x1210
 624#define R_AX_RPQ_RXBD_NUM_V1	0x1212
 625#define R_AX_CH10_TXBD_NUM_V1	0x1438
 626#define R_AX_CH11_TXBD_NUM_V1	0x143A
 627
 628#define R_AX_ACH0_BDRAM_CTRL	0x1200
 629#define R_AX_ACH1_BDRAM_CTRL	0x1204
 630#define R_AX_ACH2_BDRAM_CTRL	0x1208
 631#define R_AX_ACH3_BDRAM_CTRL	0x120C
 632#define R_AX_ACH4_BDRAM_CTRL	0x1210
 633#define R_AX_ACH5_BDRAM_CTRL	0x1214
 634#define R_AX_ACH6_BDRAM_CTRL	0x1218
 635#define R_AX_ACH7_BDRAM_CTRL	0x121C
 636#define R_AX_CH8_BDRAM_CTRL	0x1220
 637#define R_AX_CH9_BDRAM_CTRL	0x1224
 638#define R_AX_CH10_BDRAM_CTRL	0x1320
 639#define R_AX_CH11_BDRAM_CTRL	0x1324
 640#define R_AX_CH12_BDRAM_CTRL	0x1228
 641#define R_AX_ACH0_BDRAM_CTRL_V1 0x1300
 642#define R_AX_ACH1_BDRAM_CTRL_V1 0x1304
 643#define R_AX_ACH2_BDRAM_CTRL_V1 0x1308
 644#define R_AX_ACH3_BDRAM_CTRL_V1 0x130C
 645#define R_AX_ACH4_BDRAM_CTRL_V1 0x1310
 646#define R_AX_ACH5_BDRAM_CTRL_V1 0x1314
 647#define R_AX_ACH6_BDRAM_CTRL_V1 0x1318
 648#define R_AX_ACH7_BDRAM_CTRL_V1 0x131C
 649#define R_AX_CH8_BDRAM_CTRL_V1 0x1320
 650#define R_AX_CH9_BDRAM_CTRL_V1 0x1324
 651#define R_AX_CH12_BDRAM_CTRL_V1 0x1328
 652#define R_AX_CH10_BDRAM_CTRL_V1 0x1420
 653#define R_AX_CH11_BDRAM_CTRL_V1 0x1424
 654#define BDRAM_SIDX_MASK		GENMASK(7, 0)
 655#define BDRAM_MAX_MASK		GENMASK(15, 8)
 656#define BDRAM_MIN_MASK		GENMASK(23, 16)
 657
 658#define R_AX_PCIE_INIT_CFG1	0x1000
 659#define B_AX_PCIE_RXRST_KEEP_REG	BIT(23)
 660#define B_AX_PCIE_TXRST_KEEP_REG	BIT(22)
 661#define B_AX_PCIE_PERST_KEEP_REG	BIT(21)
 662#define B_AX_PCIE_FLR_KEEP_REG		BIT(20)
 663#define B_AX_PCIE_TRAIN_KEEP_REG	BIT(19)
 664#define B_AX_RXBD_MODE			BIT(18)
 665#define B_AX_PCIE_MAX_RXDMA_MASK	GENMASK(16, 14)
 666#define B_AX_RXHCI_EN			BIT(13)
 667#define B_AX_LATENCY_CONTROL		BIT(12)
 668#define B_AX_TXHCI_EN			BIT(11)
 669#define B_AX_PCIE_MAX_TXDMA_MASK	GENMASK(10, 8)
 670#define B_AX_TX_TRUNC_MODE		BIT(5)
 671#define B_AX_RX_TRUNC_MODE		BIT(4)
 672#define B_AX_RST_BDRAM			BIT(3)
 673#define B_AX_DIS_RXDMA_PRE		BIT(2)
 674
 675#define R_AX_TXDMA_ADDR_H	0x10F0
 676#define R_AX_RXDMA_ADDR_H	0x10F4
 677
 678#define R_AX_PCIE_DMA_STOP1	0x1010
 679#define B_AX_STOP_PCIEIO		BIT(20)
 680#define B_AX_STOP_WPDMA			BIT(19)
 681#define B_AX_STOP_CH12			BIT(18)
 682#define B_AX_STOP_CH9			BIT(17)
 683#define B_AX_STOP_CH8			BIT(16)
 684#define B_AX_STOP_ACH7			BIT(15)
 685#define B_AX_STOP_ACH6			BIT(14)
 686#define B_AX_STOP_ACH5			BIT(13)
 687#define B_AX_STOP_ACH4			BIT(12)
 688#define B_AX_STOP_ACH3			BIT(11)
 689#define B_AX_STOP_ACH2			BIT(10)
 690#define B_AX_STOP_ACH1			BIT(9)
 691#define B_AX_STOP_ACH0			BIT(8)
 692#define B_AX_STOP_RPQ			BIT(1)
 693#define B_AX_STOP_RXQ			BIT(0)
 694#define B_AX_TX_STOP1_ALL		GENMASK(18, 8)
 695#define B_AX_TX_STOP1_MASK		(B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | \
 696					 B_AX_STOP_ACH2 | B_AX_STOP_ACH3 | \
 697					 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | \
 698					 B_AX_STOP_ACH6 | B_AX_STOP_ACH7 | \
 699					 B_AX_STOP_CH8 | B_AX_STOP_CH9 | \
 700					 B_AX_STOP_CH12)
 701#define B_AX_TX_STOP1_MASK_V1		(B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | \
 702					 B_AX_STOP_ACH2 | B_AX_STOP_ACH3 | \
 703					 B_AX_STOP_CH8 | B_AX_STOP_CH9 | \
 704					 B_AX_STOP_CH12)
 705
 706#define R_AX_PCIE_DMA_STOP2	0x1310
 707#define B_AX_STOP_CH11			BIT(1)
 708#define B_AX_STOP_CH10			BIT(0)
 709#define B_AX_TX_STOP2_ALL		GENMASK(1, 0)
 710
 711#define R_AX_TXBD_RWPTR_CLR1	0x1014
 712#define B_AX_CLR_CH12_IDX		BIT(10)
 713#define B_AX_CLR_CH9_IDX		BIT(9)
 714#define B_AX_CLR_CH8_IDX		BIT(8)
 715#define B_AX_CLR_ACH7_IDX		BIT(7)
 716#define B_AX_CLR_ACH6_IDX		BIT(6)
 717#define B_AX_CLR_ACH5_IDX		BIT(5)
 718#define B_AX_CLR_ACH4_IDX		BIT(4)
 719#define B_AX_CLR_ACH3_IDX		BIT(3)
 720#define B_AX_CLR_ACH2_IDX		BIT(2)
 721#define B_AX_CLR_ACH1_IDX		BIT(1)
 722#define B_AX_CLR_ACH0_IDX		BIT(0)
 723#define B_AX_TXBD_CLR1_ALL		GENMASK(10, 0)
 724
 725#define R_AX_RXBD_RWPTR_CLR	0x1018
 726#define B_AX_CLR_RPQ_IDX		BIT(1)
 727#define B_AX_CLR_RXQ_IDX		BIT(0)
 728#define B_AX_RXBD_CLR_ALL		GENMASK(1, 0)
 729
 730#define R_AX_TXBD_RWPTR_CLR2	0x1314
 731#define B_AX_CLR_CH11_IDX		BIT(1)
 732#define B_AX_CLR_CH10_IDX		BIT(0)
 733#define B_AX_TXBD_CLR2_ALL		GENMASK(1, 0)
 734
 735#define R_AX_PCIE_DMA_BUSY1	0x101C
 736#define B_AX_PCIEIO_RX_BUSY		BIT(22)
 737#define B_AX_PCIEIO_TX_BUSY		BIT(21)
 738#define B_AX_PCIEIO_BUSY		BIT(20)
 739#define B_AX_WPDMA_BUSY			BIT(19)
 740#define B_AX_CH12_BUSY			BIT(18)
 741#define B_AX_CH9_BUSY			BIT(17)
 742#define B_AX_CH8_BUSY			BIT(16)
 743#define B_AX_ACH7_BUSY			BIT(15)
 744#define B_AX_ACH6_BUSY			BIT(14)
 745#define B_AX_ACH5_BUSY			BIT(13)
 746#define B_AX_ACH4_BUSY			BIT(12)
 747#define B_AX_ACH3_BUSY			BIT(11)
 748#define B_AX_ACH2_BUSY			BIT(10)
 749#define B_AX_ACH1_BUSY			BIT(9)
 750#define B_AX_ACH0_BUSY			BIT(8)
 751#define B_AX_RPQ_BUSY			BIT(1)
 752#define B_AX_RXQ_BUSY			BIT(0)
 753#define DMA_BUSY1_CHECK		(B_AX_ACH0_BUSY | B_AX_ACH1_BUSY | B_AX_ACH2_BUSY | \
 754				 B_AX_ACH3_BUSY | B_AX_ACH4_BUSY | B_AX_ACH5_BUSY | \
 755				 B_AX_ACH6_BUSY | B_AX_ACH7_BUSY | B_AX_CH8_BUSY | \
 756				 B_AX_CH9_BUSY | B_AX_CH12_BUSY)
 757#define DMA_BUSY1_CHECK_V1	(B_AX_ACH0_BUSY | B_AX_ACH1_BUSY | B_AX_ACH2_BUSY | \
 758				 B_AX_ACH3_BUSY | B_AX_CH8_BUSY | B_AX_CH9_BUSY | \
 759				 B_AX_CH12_BUSY)
 760
 761#define R_AX_PCIE_DMA_BUSY2	0x131C
 762#define B_AX_CH11_BUSY			BIT(1)
 763#define B_AX_CH10_BUSY			BIT(0)
 764
 765#define R_AX_WP_ADDR_H_SEL0_3 0x1334
 766#define R_AX_WP_ADDR_H_SEL4_7 0x1338
 767#define R_AX_WP_ADDR_H_SEL8_11 0x133C
 768#define R_AX_WP_ADDR_H_SEL12_15 0x1340
 769
 770#define R_BE_HAXI_DMA_STOP1 0xB010
 771#define B_BE_STOP_WPDMA BIT(31)
 772#define B_BE_STOP_CH14 BIT(14)
 773#define B_BE_STOP_CH13 BIT(13)
 774#define B_BE_STOP_CH12 BIT(12)
 775#define B_BE_STOP_CH11 BIT(11)
 776#define B_BE_STOP_CH10 BIT(10)
 777#define B_BE_STOP_CH9 BIT(9)
 778#define B_BE_STOP_CH8 BIT(8)
 779#define B_BE_STOP_CH7 BIT(7)
 780#define B_BE_STOP_CH6 BIT(6)
 781#define B_BE_STOP_CH5 BIT(5)
 782#define B_BE_STOP_CH4 BIT(4)
 783#define B_BE_STOP_CH3 BIT(3)
 784#define B_BE_STOP_CH2 BIT(2)
 785#define B_BE_STOP_CH1 BIT(1)
 786#define B_BE_STOP_CH0 BIT(0)
 787#define B_BE_TX_STOP1_MASK (B_BE_STOP_CH0 | B_BE_STOP_CH1 | \
 788			    B_BE_STOP_CH2 | B_BE_STOP_CH3 | \
 789			    B_BE_STOP_CH4 | B_BE_STOP_CH5 | \
 790			    B_BE_STOP_CH6 | B_BE_STOP_CH7 | \
 791			    B_BE_STOP_CH8 | B_BE_STOP_CH9 | \
 792			    B_BE_STOP_CH10 | B_BE_STOP_CH11 | \
 793			    B_BE_STOP_CH12)
 794
 795#define R_BE_CH0_TXBD_NUM_V1 0xB030
 796#define R_BE_CH1_TXBD_NUM_V1 0xB032
 797#define R_BE_CH2_TXBD_NUM_V1 0xB034
 798#define R_BE_CH3_TXBD_NUM_V1 0xB036
 799#define R_BE_CH4_TXBD_NUM_V1 0xB038
 800#define R_BE_CH5_TXBD_NUM_V1 0xB03A
 801#define R_BE_CH6_TXBD_NUM_V1 0xB03C
 802#define R_BE_CH7_TXBD_NUM_V1 0xB03E
 803#define R_BE_CH8_TXBD_NUM_V1 0xB040
 804#define R_BE_CH9_TXBD_NUM_V1 0xB042
 805#define R_BE_CH10_TXBD_NUM_V1 0xB044
 806#define R_BE_CH11_TXBD_NUM_V1 0xB046
 807#define R_BE_CH12_TXBD_NUM_V1 0xB048
 808#define R_BE_CH13_TXBD_NUM_V1 0xB04C
 809#define R_BE_CH14_TXBD_NUM_V1 0xB04E
 810
 811#define R_BE_CH0_TXBD_CFG 0xB030
 812#define R_BE_CH2_TXBD_CFG 0xB034
 813#define R_BE_CH4_TXBD_CFG 0xB038
 814#define R_BE_CH6_TXBD_CFG 0xB03C
 815#define R_BE_CH8_TXBD_CFG 0xB040
 816#define R_BE_CH10_TXBD_CFG 0xB044
 817#define R_BE_CH12_TXBD_CFG 0xB048
 818#define B_BE_TX_FLAG BIT(14)
 819#define B_BE_TX_START_OFFSET_MASK GENMASK(12, 4)
 820#define B_BE_TX_NUM_SEL_MASK GENMASK(2, 0)
 821
 822#define R_BE_RXQ0_RXBD_NUM_V1 0xB050
 823#define R_BE_RPQ0_RXBD_NUM_V1 0xB052
 824
 825#define R_BE_RX_CH0_RXBD_CONFIG 0xB050
 826#define R_BE_RX_CH1_RXBD_CONFIG 0xB052
 827#define B_BE_RX_START_OFFSET_MASK GENMASK(11, 4)
 828#define B_BE_RX_NUM_SEL_MASK GENMASK(2, 0)
 829
 830#define R_BE_CH0_TXBD_IDX_V1 0xB100
 831#define R_BE_CH1_TXBD_IDX_V1 0xB104
 832#define R_BE_CH2_TXBD_IDX_V1 0xB108
 833#define R_BE_CH3_TXBD_IDX_V1 0xB10C
 834#define R_BE_CH4_TXBD_IDX_V1 0xB110
 835#define R_BE_CH5_TXBD_IDX_V1 0xB114
 836#define R_BE_CH6_TXBD_IDX_V1 0xB118
 837#define R_BE_CH7_TXBD_IDX_V1 0xB11C
 838#define R_BE_CH8_TXBD_IDX_V1 0xB120
 839#define R_BE_CH9_TXBD_IDX_V1 0xB124
 840#define R_BE_CH10_TXBD_IDX_V1 0xB128
 841#define R_BE_CH11_TXBD_IDX_V1 0xB12C
 842#define R_BE_CH12_TXBD_IDX_V1 0xB130
 843#define R_BE_CH13_TXBD_IDX_V1 0xB134
 844#define R_BE_CH14_TXBD_IDX_V1 0xB138
 845
 846#define R_BE_RXQ0_RXBD_IDX_V1 0xB160
 847#define R_BE_RPQ0_RXBD_IDX_V1 0xB164
 848
 849#define R_BE_CH0_TXBD_DESA_L_V1 0xB200
 850#define R_BE_CH0_TXBD_DESA_H_V1 0xB204
 851#define R_BE_CH1_TXBD_DESA_L_V1 0xB208
 852#define R_BE_CH1_TXBD_DESA_H_V1 0xB20C
 853#define R_BE_CH2_TXBD_DESA_L_V1 0xB210
 854#define R_BE_CH2_TXBD_DESA_H_V1 0xB214
 855#define R_BE_CH3_TXBD_DESA_L_V1 0xB218
 856#define R_BE_CH3_TXBD_DESA_H_V1 0xB21C
 857#define R_BE_CH4_TXBD_DESA_L_V1 0xB220
 858#define R_BE_CH4_TXBD_DESA_H_V1 0xB224
 859#define R_BE_CH5_TXBD_DESA_L_V1 0xB228
 860#define R_BE_CH5_TXBD_DESA_H_V1 0xB22C
 861#define R_BE_CH6_TXBD_DESA_L_V1 0xB230
 862#define R_BE_CH6_TXBD_DESA_H_V1 0xB234
 863#define R_BE_CH7_TXBD_DESA_L_V1 0xB238
 864#define R_BE_CH7_TXBD_DESA_H_V1 0xB23C
 865#define R_BE_CH8_TXBD_DESA_L_V1 0xB240
 866#define R_BE_CH8_TXBD_DESA_H_V1 0xB244
 867#define R_BE_CH9_TXBD_DESA_L_V1 0xB248
 868#define R_BE_CH9_TXBD_DESA_H_V1 0xB24C
 869#define R_BE_CH10_TXBD_DESA_L_V1 0xB250
 870#define R_BE_CH10_TXBD_DESA_H_V1 0xB254
 871#define R_BE_CH11_TXBD_DESA_L_V1 0xB258
 872#define R_BE_CH11_TXBD_DESA_H_V1 0xB25C
 873#define R_BE_CH12_TXBD_DESA_L_V1 0xB260
 874#define R_BE_CH12_TXBD_DESA_H_V1 0xB264
 875#define R_BE_CH13_TXBD_DESA_L_V1 0xB268
 876#define R_BE_CH13_TXBD_DESA_H_V1 0xB26C
 877#define R_BE_CH14_TXBD_DESA_L_V1 0xB270
 878#define R_BE_CH14_TXBD_DESA_H_V1 0xB274
 879
 880#define R_BE_ACQ_TXBD_DESA_L 0xB200
 881#define B_BE_TX_ACQ_DESA_L_MASK GENMASK(31, 3)
 882#define R_BE_ACQ_TXBD_DESA_H 0xB204
 883#define B_BE_TX_ACQ_DESA_H_MASK GENMASK(7, 0)
 884#define R_BE_NACQ_TXBD_DESA_L 0xB240
 885#define B_BE_TX_NACQ_DESA_L_MASK GENMASK(31, 3)
 886#define R_BE_NACQ_TXBD_DESA_H 0xB244
 887#define B_BE_TX_NACQ_DESA_H_MASK GENMASK(7, 0)
 888
 889#define R_BE_RXQ0_RXBD_DESA_L_V1 0xB300
 890#define R_BE_RXQ0_RXBD_DESA_H_V1 0xB304
 891#define R_BE_RPQ0_RXBD_DESA_L_V1 0xB308
 892#define R_BE_RPQ0_RXBD_DESA_H_V1 0xB30C
 893
 894#define R_BE_HOST0_RXBD_DESA_L 0xB300
 895#define B_BE_RX_HOST0_DESA_L_MASK GENMASK(31, 3)
 896#define R_BE_HOST0_RXBD_DESA_H 0xB304
 897#define B_BE_RX_HOST0_DESA_H_MASK GENMASK(7, 0)
 898
 899#define R_BE_WP_ADDR_H_SEL0_3_V1 0xB420
 900#define R_BE_WP_ADDR_H_SEL4_7_V1 0xB424
 901#define R_BE_WP_ADDR_H_SEL8_11_V1 0xB428
 902#define R_BE_WP_ADDR_H_SEL12_15_V1 0xB42C
 903
 904/* Configure */
 905#define R_AX_PCIE_INIT_CFG2		0x1004
 906#define B_AX_WD_ITVL_IDLE		GENMASK(27, 24)
 907#define B_AX_WD_ITVL_ACT		GENMASK(19, 16)
 908#define B_AX_PCIE_RX_APPLEN_MASK	GENMASK(13, 0)
 909
 910#define R_AX_PCIE_PS_CTRL		0x1008
 911#define B_AX_L1OFF_PWR_OFF_EN		BIT(5)
 912
 913#define R_AX_INT_MIT_RX			0x10D4
 914#define B_AX_RXMIT_RXP2_SEL		BIT(19)
 915#define B_AX_RXMIT_RXP1_SEL		BIT(18)
 916#define B_AX_RXTIMER_UNIT_MASK		GENMASK(17, 16)
 917#define AX_RXTIMER_UNIT_64US		0
 918#define AX_RXTIMER_UNIT_128US		1
 919#define AX_RXTIMER_UNIT_256US		2
 920#define AX_RXTIMER_UNIT_512US		3
 921#define B_AX_RXCOUNTER_MATCH_MASK	GENMASK(15, 8)
 922#define B_AX_RXTIMER_MATCH_MASK		GENMASK(7, 0)
 923
 924#define R_AX_DBG_ERR_FLAG_V1 0x1104
 925
 926#define R_AX_INT_MIT_RX_V1 0x1184
 927#define B_AX_RXMIT_RXP2_SEL_V1 BIT(19)
 928#define B_AX_RXMIT_RXP1_SEL_V1 BIT(18)
 929#define B_AX_MIT_RXTIMER_UNIT_MASK GENMASK(17, 16)
 930#define B_AX_MIT_RXCOUNTER_MATCH_MASK GENMASK(15, 8)
 931#define B_AX_MIT_RXTIMER_MATCH_MASK GENMASK(7, 0)
 932
 933#define R_AX_DBG_ERR_FLAG		0x11C4
 934#define B_AX_PCIE_RPQ_FULL		BIT(29)
 935#define B_AX_PCIE_RXQ_FULL		BIT(28)
 936#define B_AX_CPL_STATUS_MASK		GENMASK(27, 25)
 937#define B_AX_RX_STUCK			BIT(22)
 938#define B_AX_TX_STUCK			BIT(21)
 939#define B_AX_PCIEDBG_TXERR0		BIT(16)
 940#define B_AX_PCIE_RXP1_ERR0		BIT(4)
 941#define B_AX_PCIE_TXBD_LEN0		BIT(1)
 942#define B_AX_PCIE_TXBD_4KBOUD_LENERR	BIT(0)
 943
 944#define R_AX_TXBD_RWPTR_CLR2_V1		0x11C4
 945#define B_AX_CLR_CH11_IDX		BIT(1)
 946#define B_AX_CLR_CH10_IDX		BIT(0)
 947
 948#define R_AX_LBC_WATCHDOG		0x11D8
 949#define B_AX_LBC_TIMER			GENMASK(7, 4)
 950#define B_AX_LBC_FLAG			BIT(1)
 951#define B_AX_LBC_EN			BIT(0)
 952
 953#define R_AX_RXBD_RWPTR_CLR_V1		0x1200
 954#define B_AX_CLR_RPQ_IDX		BIT(1)
 955#define B_AX_CLR_RXQ_IDX		BIT(0)
 956
 957#define R_AX_HAXI_EXP_CTRL		0x1204
 958#define B_AX_MAX_TAG_NUM_V1_MASK	GENMASK(2, 0)
 959
 960#define R_AX_PCIE_EXP_CTRL		0x13F0
 961#define B_AX_EN_CHKDSC_NO_RX_STUCK	BIT(20)
 962#define B_AX_MAX_TAG_NUM		GENMASK(18, 16)
 963#define B_AX_SIC_EN_FORCE_CLKREQ	BIT(4)
 964
 965#define R_AX_PCIE_RX_PREF_ADV		0x13F4
 966#define B_AX_RXDMA_PREF_ADV_EN		BIT(0)
 967
 968#define R_AX_PCIE_HRPWM_V1		0x30C0
 969#define R_AX_PCIE_CRPWM			0x30C4
 970
 971#define R_AX_LBC_WATCHDOG_V1 0x30D8
 972
 973#define R_BE_PCIE_HRPWM 0x30C0
 974#define R_BE_PCIE_CRPWM 0x30C4
 975
 976#define R_BE_L1_2_CTRL_HCILDO 0x3110
 977#define B_BE_PCIE_DIS_L1_2_CTRL_HCILDO BIT(0)
 978
 979#define R_BE_PL1_DBG_INFO 0x3120
 980#define B_BE_END_PL1_CNT_MASK GENMASK(23, 16)
 981#define B_BE_START_PL1_CNT_MASK GENMASK(7, 0)
 982
 983#define R_BE_PCIE_MIT0_TMR 0x3330
 984#define B_BE_PCIE_MIT0_RX_TMR_MASK GENMASK(5, 4)
 985#define BE_MIT0_TMR_UNIT_1MS 0
 986#define BE_MIT0_TMR_UNIT_2MS 1
 987#define BE_MIT0_TMR_UNIT_4MS 2
 988#define BE_MIT0_TMR_UNIT_8MS 3
 989#define B_BE_PCIE_MIT0_TX_TMR_MASK GENMASK(1, 0)
 990
 991#define R_BE_PCIE_MIT0_CNT 0x3334
 992#define B_BE_PCIE_RX_MIT0_CNT_MASK GENMASK(31, 24)
 993#define B_BE_PCIE_TX_MIT0_CNT_MASK GENMASK(23, 16)
 994#define B_BE_PCIE_RX_MIT0_TMR_CNT_MASK GENMASK(15, 8)
 995#define B_BE_PCIE_TX_MIT0_TMR_CNT_MASK GENMASK(7, 0)
 996
 997#define R_BE_PCIE_MIT_CH_EN 0x3338
 998#define B_BE_PCIE_MIT_RX1P1_EN BIT(23)
 999#define B_BE_PCIE_MIT_RX0P1_EN BIT(22)
1000#define B_BE_PCIE_MIT_ROQ1_EN BIT(21)
1001#define B_BE_PCIE_MIT_RPQ1_EN BIT(20)
1002#define B_BE_PCIE_MIT_RX1P2_EN BIT(19)
1003#define B_BE_PCIE_MIT_ROQ0_EN BIT(18)
1004#define B_BE_PCIE_MIT_RPQ0_EN BIT(17)
1005#define B_BE_PCIE_MIT_RX0P2_EN BIT(16)
1006#define B_BE_PCIE_MIT_TXCH14_EN BIT(14)
1007#define B_BE_PCIE_MIT_TXCH13_EN BIT(13)
1008#define B_BE_PCIE_MIT_TXCH12_EN BIT(12)
1009#define B_BE_PCIE_MIT_TXCH11_EN BIT(11)
1010#define B_BE_PCIE_MIT_TXCH10_EN BIT(10)
1011#define B_BE_PCIE_MIT_TXCH9_EN BIT(9)
1012#define B_BE_PCIE_MIT_TXCH8_EN BIT(8)
1013#define B_BE_PCIE_MIT_TXCH7_EN BIT(7)
1014#define B_BE_PCIE_MIT_TXCH6_EN BIT(6)
1015#define B_BE_PCIE_MIT_TXCH5_EN BIT(5)
1016#define B_BE_PCIE_MIT_TXCH4_EN BIT(4)
1017#define B_BE_PCIE_MIT_TXCH3_EN BIT(3)
1018#define B_BE_PCIE_MIT_TXCH2_EN BIT(2)
1019#define B_BE_PCIE_MIT_TXCH1_EN BIT(1)
1020#define B_BE_PCIE_MIT_TXCH0_EN BIT(0)
1021
1022#define R_BE_SER_PL1_CTRL 0x34A8
1023#define B_BE_PL1_SER_PL1_EN BIT(31)
1024#define B_BE_PL1_IGNORE_HOT_RST BIT(30)
1025#define B_BE_PL1_TIMER_UNIT_MASK GENMASK(19, 17)
1026#define B_BE_PL1_TIMER_CLEAR BIT(0)
1027
1028#define R_BE_REG_PL1_MASK 0x34B0
1029#define B_BE_SER_PCLKREQ_ACK_MASK BIT(5)
1030#define B_BE_SER_PM_CLK_MASK BIT(4)
1031#define B_BE_SER_LTSSM_IMR BIT(3)
1032#define B_BE_SER_PM_MASTER_IMR BIT(2)
1033#define B_BE_SER_L1SUB_IMR BIT(1)
1034#define B_BE_SER_PMU_IMR BIT(0)
1035
1036#define R_BE_REG_PL1_ISR 0x34B4
1037
1038#define R_BE_RX_APPEND_MODE 0x8920
1039#define B_BE_APPEND_OFFSET_MASK GENMASK(23, 16)
1040#define B_BE_APPEND_LEN_MASK GENMASK(15, 0)
1041
1042#define R_BE_TXBD_RWPTR_CLR1 0xB014
1043#define B_BE_CLR_CH14_IDX BIT(14)
1044#define B_BE_CLR_CH13_IDX BIT(13)
1045#define B_BE_CLR_CH12_IDX BIT(12)
1046#define B_BE_CLR_CH11_IDX BIT(11)
1047#define B_BE_CLR_CH10_IDX BIT(10)
1048#define B_BE_CLR_CH9_IDX BIT(9)
1049#define B_BE_CLR_CH8_IDX BIT(8)
1050#define B_BE_CLR_CH7_IDX BIT(7)
1051#define B_BE_CLR_CH6_IDX BIT(6)
1052#define B_BE_CLR_CH5_IDX BIT(5)
1053#define B_BE_CLR_CH4_IDX BIT(4)
1054#define B_BE_CLR_CH3_IDX BIT(3)
1055#define B_BE_CLR_CH2_IDX BIT(2)
1056#define B_BE_CLR_CH1_IDX BIT(1)
1057#define B_BE_CLR_CH0_IDX BIT(0)
1058
1059#define R_BE_RXBD_RWPTR_CLR1_V1 0xB018
1060#define B_BE_CLR_ROQ1_IDX_V1 BIT(5)
1061#define B_BE_CLR_RPQ1_IDX_V1 BIT(4)
1062#define B_BE_CLR_RXQ1_IDX_V1 BIT(3)
1063#define B_BE_CLR_ROQ0_IDX BIT(2)
1064#define B_BE_CLR_RPQ0_IDX BIT(1)
1065#define B_BE_CLR_RXQ0_IDX BIT(0)
1066
1067#define R_BE_HAXI_DMA_BUSY1 0xB01C
1068#define B_BE_HAXI_MST_BUSY BIT(31)
1069#define B_BE_HAXI_RX_IDLE BIT(25)
1070#define B_BE_HAXI_TX_IDLE BIT(24)
1071#define B_BE_ROQ1_BUSY_V1 BIT(21)
1072#define B_BE_RPQ1_BUSY_V1 BIT(20)
1073#define B_BE_RXQ1_BUSY_V1 BIT(19)
1074#define B_BE_ROQ0_BUSY_V1 BIT(18)
1075#define B_BE_RPQ0_BUSY_V1 BIT(17)
1076#define B_BE_RXQ0_BUSY_V1 BIT(16)
1077#define B_BE_WPDMA_BUSY BIT(15)
1078#define B_BE_CH14_BUSY BIT(14)
1079#define B_BE_CH13_BUSY BIT(13)
1080#define B_BE_CH12_BUSY BIT(12)
1081#define B_BE_CH11_BUSY BIT(11)
1082#define B_BE_CH10_BUSY BIT(10)
1083#define B_BE_CH9_BUSY BIT(9)
1084#define B_BE_CH8_BUSY BIT(8)
1085#define B_BE_CH7_BUSY BIT(7)
1086#define B_BE_CH6_BUSY BIT(6)
1087#define B_BE_CH5_BUSY BIT(5)
1088#define B_BE_CH4_BUSY BIT(4)
1089#define B_BE_CH3_BUSY BIT(3)
1090#define B_BE_CH2_BUSY BIT(2)
1091#define B_BE_CH1_BUSY BIT(1)
1092#define B_BE_CH0_BUSY BIT(0)
1093#define DMA_BUSY1_CHECK_BE (B_BE_CH0_BUSY | B_BE_CH1_BUSY | B_BE_CH2_BUSY | \
1094			    B_BE_CH3_BUSY | B_BE_CH4_BUSY | B_BE_CH5_BUSY | \
1095			    B_BE_CH6_BUSY | B_BE_CH7_BUSY | B_BE_CH8_BUSY | \
1096			    B_BE_CH9_BUSY | B_BE_CH10_BUSY | B_BE_CH11_BUSY | \
1097			    B_BE_CH12_BUSY | B_BE_CH13_BUSY | B_BE_CH14_BUSY)
1098
1099#define R_BE_HAXI_EXP_CTRL_V1 0xB020
1100#define B_BE_R_NO_SEC_ACCESS BIT(31)
1101#define B_BE_FORCE_EN_DMA_RX_GCLK BIT(5)
1102#define B_BE_FORCE_EN_DMA_TX_GCLK BIT(4)
1103#define B_BE_MAX_TAG_NUM_MASK GENMASK(3, 0)
1104
1105#define RTW89_PCI_TXBD_NUM_MAX		256
1106#define RTW89_PCI_RXBD_NUM_MAX		256
1107#define RTW89_PCI_TXWD_NUM_MAX		512
1108#define RTW89_PCI_TXWD_PAGE_SIZE	128
1109#define RTW89_PCI_ADDRINFO_MAX		4
1110/* +40 for rtw89_rxdesc_long_v2; +4 for rtw89_pci_rxbd_info */
1111#define RTW89_PCI_RX_BUF_SIZE		(11454 + 40 + 4)
1112
1113#define RTW89_PCI_POLL_BDRAM_RST_CNT	100
1114#define RTW89_PCI_MULTITAG		8
1115
1116/* PCIE CFG register */
1117#define RTW89_PCIE_CAPABILITY_SPEED	0x7C
1118#define RTW89_PCIE_SUPPORT_GEN_MASK	GENMASK(3, 0)
1119#define RTW89_PCIE_L1_STS_V1		0x80
1120#define RTW89_BCFG_LINK_SPEED_MASK	GENMASK(19, 16)
1121#define RTW89_PCIE_GEN1_SPEED		0x01
1122#define RTW89_PCIE_GEN2_SPEED		0x02
1123#define RTW89_PCIE_PHY_RATE		0x82
1124#define RTW89_PCIE_PHY_RATE_MASK	GENMASK(1, 0)
1125#define RTW89_PCIE_LINK_CHANGE_SPEED	0xA0
1126#define RTW89_PCIE_L1SS_STS_V1		0x0168
1127#define RTW89_PCIE_BIT_ASPM_L11		BIT(3)
1128#define RTW89_PCIE_BIT_ASPM_L12		BIT(2)
1129#define RTW89_PCIE_BIT_PCI_L11		BIT(1)
1130#define RTW89_PCIE_BIT_PCI_L12		BIT(0)
1131#define RTW89_PCIE_ASPM_CTRL		0x070F
1132#define RTW89_L1DLY_MASK		GENMASK(5, 3)
1133#define RTW89_L0DLY_MASK		GENMASK(2, 0)
1134#define RTW89_PCIE_TIMER_CTRL		0x0718
1135#define RTW89_PCIE_BIT_L1SUB		BIT(5)
1136#define RTW89_PCIE_L1_CTRL		0x0719
1137#define RTW89_PCIE_BIT_EN_64BITS	BIT(5)
1138#define RTW89_PCIE_BIT_CLK		BIT(4)
1139#define RTW89_PCIE_BIT_L1		BIT(3)
1140#define RTW89_PCIE_CLK_CTRL		0x0725
1141#define RTW89_PCIE_FTS			0x080C
1142#define RTW89_PCIE_POLLING_BIT		BIT(17)
1143#define RTW89_PCIE_RST_MSTATE		0x0B48
1144#define RTW89_PCIE_BIT_CFG_RST_MSTATE	BIT(0)
1145
1146#define INTF_INTGRA_MINREF_V1	90
1147#define INTF_INTGRA_HOSTREF_V1	100
1148
1149enum rtw89_pcie_phy {
1150	PCIE_PHY_GEN1,
1151	PCIE_PHY_GEN2,
1152	PCIE_PHY_GEN1_UNDEFINE = 0x7F,
1153};
1154
1155enum rtw89_pcie_l0sdly {
1156	PCIE_L0SDLY_1US = 0,
1157	PCIE_L0SDLY_2US = 1,
1158	PCIE_L0SDLY_3US = 2,
1159	PCIE_L0SDLY_4US = 3,
1160	PCIE_L0SDLY_5US = 4,
1161	PCIE_L0SDLY_6US = 5,
1162	PCIE_L0SDLY_7US = 6,
1163};
1164
1165enum rtw89_pcie_l1dly {
1166	PCIE_L1DLY_16US = 4,
1167	PCIE_L1DLY_32US = 5,
1168	PCIE_L1DLY_64US = 6,
1169	PCIE_L1DLY_HW_INFI = 7,
1170};
1171
1172enum rtw89_pcie_clkdly_hw {
1173	PCIE_CLKDLY_HW_0 = 0,
1174	PCIE_CLKDLY_HW_30US = 0x1,
1175	PCIE_CLKDLY_HW_50US = 0x2,
1176	PCIE_CLKDLY_HW_100US = 0x3,
1177	PCIE_CLKDLY_HW_150US = 0x4,
1178	PCIE_CLKDLY_HW_200US = 0x5,
1179};
1180
1181enum rtw89_pcie_clkdly_hw_v1 {
1182	PCIE_CLKDLY_HW_V1_0 = 0,
1183	PCIE_CLKDLY_HW_V1_16US = 0x1,
1184	PCIE_CLKDLY_HW_V1_32US = 0x2,
1185	PCIE_CLKDLY_HW_V1_64US = 0x3,
1186	PCIE_CLKDLY_HW_V1_80US = 0x4,
1187	PCIE_CLKDLY_HW_V1_96US = 0x5,
1188};
1189
1190enum mac_ax_bd_trunc_mode {
1191	MAC_AX_BD_NORM,
1192	MAC_AX_BD_TRUNC,
1193	MAC_AX_BD_DEF = 0xFE
1194};
1195
1196enum mac_ax_rxbd_mode {
1197	MAC_AX_RXBD_PKT,
1198	MAC_AX_RXBD_SEP,
1199	MAC_AX_RXBD_DEF = 0xFE
1200};
1201
1202enum mac_ax_tag_mode {
1203	MAC_AX_TAG_SGL,
1204	MAC_AX_TAG_MULTI,
1205	MAC_AX_TAG_DEF = 0xFE
1206};
1207
1208enum mac_ax_tx_burst {
1209	MAC_AX_TX_BURST_16B = 0,
1210	MAC_AX_TX_BURST_32B = 1,
1211	MAC_AX_TX_BURST_64B = 2,
1212	MAC_AX_TX_BURST_V1_64B = 0,
1213	MAC_AX_TX_BURST_128B = 3,
1214	MAC_AX_TX_BURST_V1_128B = 1,
1215	MAC_AX_TX_BURST_256B = 4,
1216	MAC_AX_TX_BURST_V1_256B = 2,
1217	MAC_AX_TX_BURST_512B = 5,
1218	MAC_AX_TX_BURST_1024B = 6,
1219	MAC_AX_TX_BURST_2048B = 7,
1220	MAC_AX_TX_BURST_DEF = 0xFE
1221};
1222
1223enum mac_ax_rx_burst {
1224	MAC_AX_RX_BURST_16B = 0,
1225	MAC_AX_RX_BURST_32B = 1,
1226	MAC_AX_RX_BURST_64B = 2,
1227	MAC_AX_RX_BURST_V1_64B = 0,
1228	MAC_AX_RX_BURST_128B = 3,
1229	MAC_AX_RX_BURST_V1_128B = 1,
1230	MAC_AX_RX_BURST_V1_256B = 0,
1231	MAC_AX_RX_BURST_DEF = 0xFE
1232};
1233
1234enum mac_ax_wd_dma_intvl {
1235	MAC_AX_WD_DMA_INTVL_0S,
1236	MAC_AX_WD_DMA_INTVL_256NS,
1237	MAC_AX_WD_DMA_INTVL_512NS,
1238	MAC_AX_WD_DMA_INTVL_768NS,
1239	MAC_AX_WD_DMA_INTVL_1US,
1240	MAC_AX_WD_DMA_INTVL_1_5US,
1241	MAC_AX_WD_DMA_INTVL_2US,
1242	MAC_AX_WD_DMA_INTVL_4US,
1243	MAC_AX_WD_DMA_INTVL_8US,
1244	MAC_AX_WD_DMA_INTVL_16US,
1245	MAC_AX_WD_DMA_INTVL_DEF = 0xFE
1246};
1247
1248enum mac_ax_multi_tag_num {
1249	MAC_AX_TAG_NUM_1,
1250	MAC_AX_TAG_NUM_2,
1251	MAC_AX_TAG_NUM_3,
1252	MAC_AX_TAG_NUM_4,
1253	MAC_AX_TAG_NUM_5,
1254	MAC_AX_TAG_NUM_6,
1255	MAC_AX_TAG_NUM_7,
1256	MAC_AX_TAG_NUM_8,
1257	MAC_AX_TAG_NUM_DEF = 0xFE
1258};
1259
1260enum mac_ax_lbc_tmr {
1261	MAC_AX_LBC_TMR_8US = 0,
1262	MAC_AX_LBC_TMR_16US,
1263	MAC_AX_LBC_TMR_32US,
1264	MAC_AX_LBC_TMR_64US,
1265	MAC_AX_LBC_TMR_128US,
1266	MAC_AX_LBC_TMR_256US,
1267	MAC_AX_LBC_TMR_512US,
1268	MAC_AX_LBC_TMR_1MS,
1269	MAC_AX_LBC_TMR_2MS,
1270	MAC_AX_LBC_TMR_4MS,
1271	MAC_AX_LBC_TMR_8MS,
1272	MAC_AX_LBC_TMR_DEF = 0xFE
1273};
1274
1275enum mac_ax_pcie_func_ctrl {
1276	MAC_AX_PCIE_DISABLE = 0,
1277	MAC_AX_PCIE_ENABLE = 1,
1278	MAC_AX_PCIE_DEFAULT = 0xFE,
1279	MAC_AX_PCIE_IGNORE = 0xFF
1280};
1281
1282enum mac_ax_io_rcy_tmr {
1283	MAC_AX_IO_RCY_ANA_TMR_2MS = 24000,
1284	MAC_AX_IO_RCY_ANA_TMR_4MS = 48000,
1285	MAC_AX_IO_RCY_ANA_TMR_6MS = 72000,
1286	MAC_AX_IO_RCY_ANA_TMR_DEF = 0xFE
1287};
1288
1289enum rtw89_pci_intr_mask_cfg {
1290	RTW89_PCI_INTR_MASK_RESET,
1291	RTW89_PCI_INTR_MASK_NORMAL,
1292	RTW89_PCI_INTR_MASK_LOW_POWER,
1293	RTW89_PCI_INTR_MASK_RECOVERY_START,
1294	RTW89_PCI_INTR_MASK_RECOVERY_COMPLETE,
1295};
1296
1297struct rtw89_pci_isrs;
1298struct rtw89_pci;
1299
1300struct rtw89_pci_bd_idx_addr {
1301	u32 tx_bd_addrs[RTW89_TXCH_NUM];
1302	u32 rx_bd_addrs[RTW89_RXCH_NUM];
1303};
1304
1305struct rtw89_pci_ch_dma_addr {
1306	u32 num; /* also `offset` addr for group_bd_addr design */
1307	u32 idx;
1308	u32 bdram;
1309	u32 desa_l;
1310	u32 desa_h;
1311};
1312
1313struct rtw89_pci_ch_dma_addr_set {
1314	struct rtw89_pci_ch_dma_addr tx[RTW89_TXCH_NUM];
1315	struct rtw89_pci_ch_dma_addr rx[RTW89_RXCH_NUM];
1316};
1317
1318struct rtw89_pci_bd_ram {
1319	u8 start_idx;
1320	u8 max_num;
1321	u8 min_num;
1322};
1323
1324struct rtw89_pci_isr_def {
1325	u32 isr_rdu;
1326	u32 isr_halt_c2h;
1327	u32 isr_wdt_timeout;
1328	struct rtw89_reg2_def isr_clear_rpq;
1329	struct rtw89_reg2_def isr_clear_rxq;
1330};
1331
1332struct rtw89_pci_gen_def {
1333	int (*mac_pre_init)(struct rtw89_dev *rtwdev);
1334	int (*mac_pre_deinit)(struct rtw89_dev *rtwdev);
1335	int (*mac_post_init)(struct rtw89_dev *rtwdev);
1336
1337	void (*clr_idx_all)(struct rtw89_dev *rtwdev);
1338	int (*rst_bdram)(struct rtw89_dev *rtwdev);
1339
1340	int (*lv1rst_stop_dma)(struct rtw89_dev *rtwdev);
1341	int (*lv1rst_start_dma)(struct rtw89_dev *rtwdev);
1342
1343	void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable);
1344	void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable);
1345	int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev);
1346
1347	void (*aspm_set)(struct rtw89_dev *rtwdev, bool enable);
1348	void (*clkreq_set)(struct rtw89_dev *rtwdev, bool enable);
1349	void (*l1ss_set)(struct rtw89_dev *rtwdev, bool enable);
1350
1351	void (*disable_eq)(struct rtw89_dev *rtwdev);
1352	void (*power_wake)(struct rtw89_dev *rtwdev, bool pwr_up);
1353};
1354
1355#define RTW89_PCI_SSID(v, d, ssv, ssd, cust) \
1356	.vendor = v, .device = d, .subsystem_vendor = ssv, .subsystem_device = ssd, \
1357	.custid = RTW89_CUSTID_ ##cust
1358
1359struct rtw89_pci_ssid_quirk {
1360	unsigned short vendor;
1361	unsigned short device;
1362	unsigned short subsystem_vendor;
1363	unsigned short subsystem_device;
1364	enum rtw89_custid custid;
1365	unsigned long bitmap; /* bitmap of rtw89_quirks */
1366};
1367
1368struct rtw89_pci_rpp_info {
1369	u16 seq;
1370	u8 qsel;
1371	u8 tx_status;
1372	u8 txch;
1373};
1374
1375struct rtw89_pci_info {
1376	const struct rtw89_pci_gen_def *gen_def;
1377	const struct rtw89_pci_isr_def *isr_def;
1378	enum mac_ax_bd_trunc_mode txbd_trunc_mode;
1379	enum mac_ax_bd_trunc_mode rxbd_trunc_mode;
1380	enum mac_ax_rxbd_mode rxbd_mode;
1381	enum mac_ax_tag_mode tag_mode;
1382	enum mac_ax_tx_burst tx_burst;
1383	enum mac_ax_rx_burst rx_burst;
1384	enum mac_ax_wd_dma_intvl wd_dma_idle_intvl;
1385	enum mac_ax_wd_dma_intvl wd_dma_act_intvl;
1386	enum mac_ax_multi_tag_num multi_tag_num;
1387	enum mac_ax_pcie_func_ctrl lbc_en;
1388	enum mac_ax_lbc_tmr lbc_tmr;
1389	enum mac_ax_pcie_func_ctrl autok_en;
1390	enum mac_ax_pcie_func_ctrl io_rcy_en;
1391	enum mac_ax_io_rcy_tmr io_rcy_tmr;
1392	bool rx_ring_eq_is_full;
1393	bool check_rx_tag;
1394	bool no_rxbd_fs;
1395	bool group_bd_addr;
1396	u32 rpp_fmt_size;
1397
1398	u32 init_cfg_reg;
1399	u32 txhci_en_bit;
1400	u32 rxhci_en_bit;
1401	u32 rxbd_mode_bit;
1402	u32 exp_ctrl_reg;
1403	u32 max_tag_num_mask;
1404	u32 rxbd_rwptr_clr_reg;
1405	u32 txbd_rwptr_clr2_reg;
1406	struct rtw89_reg_def dma_io_stop;
1407	struct rtw89_reg_def dma_stop1;
1408	struct rtw89_reg_def dma_stop2;
1409	struct rtw89_reg_def dma_busy1;
1410	u32 dma_busy2_reg;
1411	u32 dma_busy3_reg;
1412
1413	u32 rpwm_addr;
1414	u32 cpwm_addr;
1415	u32 mit_addr;
1416	u32 wp_sel_addr;
1417	u32 tx_dma_ch_mask;
1418	const struct rtw89_pci_bd_idx_addr *bd_idx_addr_low_power;
1419	const struct rtw89_pci_ch_dma_addr_set *dma_addr_set;
1420	const struct rtw89_pci_bd_ram (*bd_ram_table)[RTW89_TXCH_NUM];
1421
1422	int (*ltr_set)(struct rtw89_dev *rtwdev, bool en);
1423	u32 (*fill_txaddr_info)(struct rtw89_dev *rtwdev,
1424				void *txaddr_info_addr, u32 total_len,
1425				dma_addr_t dma, u8 *add_info_nr);
1426	void (*parse_rpp)(struct rtw89_dev *rtwdev, void *rpp,
1427			  struct rtw89_pci_rpp_info *rpp_info);
1428	void (*config_intr_mask)(struct rtw89_dev *rtwdev);
1429	void (*enable_intr)(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1430	void (*disable_intr)(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1431	void (*recognize_intrs)(struct rtw89_dev *rtwdev,
1432				struct rtw89_pci *rtwpci,
1433				struct rtw89_pci_isrs *isrs);
1434
1435	const struct rtw89_pci_ssid_quirk *ssid_quirks;
1436};
1437
1438struct rtw89_pci_tx_data {
1439	dma_addr_t dma;
1440};
1441
1442struct rtw89_pci_rx_info {
1443	dma_addr_t dma;
1444	u32 fs:1, ls:1, tag:13, len:14;
1445};
1446
1447struct rtw89_pci_tx_bd_32 {
1448	__le16 length;
1449	__le16 opt;
1450#define RTW89_PCI_TXBD_OPT_LS		BIT(14)
1451#define RTW89_PCI_TXBD_OPT_DMA_HI	GENMASK(13, 6)
1452	__le32 dma;
1453} __packed;
1454
1455#define RTW89_PCI_TXWP_VALID		BIT(15)
1456
1457struct rtw89_pci_tx_wp_info {
1458	__le16 seq0;
1459	__le16 seq1;
1460	__le16 seq2;
1461	__le16 seq3;
1462} __packed;
1463
1464#define RTW89_PCI_ADDR_MSDU_LS		BIT(15)
1465#define RTW89_PCI_ADDR_LS		BIT(14)
1466#define RTW89_PCI_ADDR_HIGH_MASK	GENMASK(13, 6)
1467#define RTW89_PCI_ADDR_NUM(x)		((x) & GENMASK(5, 0))
1468
1469struct rtw89_pci_tx_addr_info_32 {
1470	__le16 length;
1471	__le16 option;
1472	__le32 dma;
1473} __packed;
1474
1475#define RTW89_TXADDR_INFO_NR_V1		10
1476
1477struct rtw89_pci_tx_addr_info_32_v1 {
1478	__le16 length_opt;
1479#define B_PCIADDR_LEN_V1_MASK		GENMASK(10, 0)
1480#define B_PCIADDR_HIGH_SEL_V1_MASK	GENMASK(14, 11)
1481#define B_PCIADDR_LS_V1_MASK		BIT(15)
1482#define TXADDR_INFO_LENTHG_V1_MAX	ALIGN_DOWN(BIT(11) - 1, 4)
1483	__le16 dma_low_lsb;
1484	__le16 dma_low_msb;
1485} __packed;
1486
1487#define RTW89_PCI_RPP_POLLUTED		BIT(31)
1488#define RTW89_PCI_RPP_SEQ		GENMASK(30, 16)
1489#define RTW89_PCI_RPP_TX_STATUS		GENMASK(15, 13)
1490#define RTW89_PCI_RPP_QSEL		GENMASK(12, 8)
1491#define RTW89_PCI_RPP_MACID		GENMASK(7, 0)
1492
1493struct rtw89_pci_rpp_fmt {
1494	__le32 dword;
1495} __packed;
1496
1497#define RTW89_PCI_RPP_W0_MACID_V1_MASK		GENMASK(9, 0)
1498#define RTW89_PCI_RPP_W0_DMA_CH_MASK		GENMASK(13, 10)
1499#define RTW89_PCI_RPP_W0_TX_STATUS_V1_MASK	GENMASK(16, 14)
1500#define RTW89_PCI_RPP_W0_PCIE_SEQ_V1_MASK	GENMASK(31, 17)
1501#define RTW89_PCI_RPP_W1_QSEL_V1_MASK		GENMASK(5, 0)
1502#define RTW89_PCI_RPP_W1_TID_IND		BIT(6)
1503#define RTW89_PCI_RPP_W1_CHANGE_LINK		BIT(7)
1504
1505struct rtw89_pci_rpp_fmt_v1 {
1506	__le32 w0;
1507	__le32 w1;
1508} __packed;
1509
1510struct rtw89_pci_rx_bd_32 {
1511	__le16 buf_size;
1512	__le16 opt;
1513#define RTW89_PCI_RXBD_OPT_DMA_HI	GENMASK(13, 6)
1514	__le32 dma;
1515} __packed;
1516
1517#define RTW89_PCI_RXBD_FS		BIT(15)
1518#define RTW89_PCI_RXBD_LS		BIT(14)
1519#define RTW89_PCI_RXBD_WRITE_SIZE	GENMASK(13, 0)
1520#define RTW89_PCI_RXBD_TAG		GENMASK(28, 16)
1521
1522struct rtw89_pci_rxbd_info {
1523	__le32 dword;
1524};
1525
1526struct rtw89_pci_tx_wd {
1527	struct list_head list;
1528	struct sk_buff_head queue;
1529
1530	void *vaddr;
1531	dma_addr_t paddr;
1532	u32 len;
1533	u32 seq;
1534};
1535
1536struct rtw89_pci_dma_ring {
1537	void *head;
1538	u8 desc_size;
1539	dma_addr_t dma;
1540
1541	struct rtw89_pci_ch_dma_addr addr;
1542
1543	u32 len;
1544	u32 wp; /* host idx */
1545	u32 rp; /* hw idx */
1546};
1547
1548struct rtw89_pci_dma_pool {
1549	void *head;
1550	dma_addr_t dma;
1551	u32 size;
1552};
1553
1554struct rtw89_pci_tx_wd_ring {
1555	void *head;
1556	dma_addr_t dma;
1557
1558	struct rtw89_pci_tx_wd pages[RTW89_PCI_TXWD_NUM_MAX];
1559	struct list_head free_pages;
1560
1561	u32 page_size;
1562	u32 page_num;
1563	u32 curr_num;
1564};
1565
1566#define RTW89_RX_TAG_MAX		0x1fff
1567
1568struct rtw89_pci_tx_ring {
1569	struct rtw89_pci_tx_wd_ring wd_ring;
1570	struct rtw89_pci_dma_ring bd_ring;
1571	struct list_head busy_pages;
1572	u8 txch;
1573	bool dma_enabled;
1574	u16 tag; /* range from 0x0001 ~ 0x1fff */
1575
1576	u64 tx_cnt;
1577	u64 tx_acked;
1578	u64 tx_retry_lmt;
1579	u64 tx_life_time;
1580	u64 tx_mac_id_drop;
1581};
1582
1583struct rtw89_pci_tx_rings {
1584	struct rtw89_pci_tx_ring rings[RTW89_TXCH_NUM];
1585	struct rtw89_pci_dma_pool bd_pool;
1586};
1587
1588struct rtw89_pci_rx_ring {
1589	struct rtw89_pci_dma_ring bd_ring;
1590	struct sk_buff *buf[RTW89_PCI_RXBD_NUM_MAX];
1591	u32 buf_sz;
1592	struct sk_buff *diliver_skb;
1593	struct rtw89_rx_desc_info diliver_desc;
1594	u32 target_rx_tag:13;
1595};
1596
1597struct rtw89_pci_rx_rings {
1598	struct rtw89_pci_rx_ring rings[RTW89_RXCH_NUM];
1599	struct rtw89_pci_dma_pool bd_pool;
1600};
1601
1602struct rtw89_pci_isrs {
1603	u32 ind_isrs;
1604	u32 halt_c2h_isrs;
1605	u32 isrs[2];
1606};
1607
1608struct rtw89_pci {
1609	struct pci_dev *pdev;
1610
1611	/* protect HW irq related registers */
1612	spinlock_t irq_lock;
1613	/* protect TRX resources (exclude RXQ) */
1614	spinlock_t trx_lock;
1615	bool running;
1616	bool low_power;
1617	bool under_recovery;
1618	bool enable_dac;
1619	struct rtw89_pci_tx_rings tx;
1620	struct rtw89_pci_rx_rings rx;
1621	struct sk_buff_head h2c_queue;
1622	struct sk_buff_head h2c_release_queue;
1623	DECLARE_BITMAP(kick_map, RTW89_TXCH_NUM);
1624
1625	u32 ind_intrs;
1626	u32 halt_c2h_intrs;
1627	u32 intrs[2];
1628	void __iomem *mmap;
1629};
1630
1631static inline struct rtw89_pci_rx_info *RTW89_PCI_RX_SKB_CB(struct sk_buff *skb)
1632{
1633	BUILD_BUG_ON(sizeof(struct rtw89_pci_rx_info) > sizeof(skb->cb));
1634
1635	return (struct rtw89_pci_rx_info *)skb->cb;
1636}
1637
1638static inline struct rtw89_pci_rx_bd_32 *
1639RTW89_PCI_RX_BD(struct rtw89_pci_rx_ring *rx_ring, u32 idx)
1640{
1641	struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
1642	u8 *head = bd_ring->head;
1643	u32 desc_size = bd_ring->desc_size;
1644	u32 offset = idx * desc_size;
1645
1646	return (struct rtw89_pci_rx_bd_32 *)(head + offset);
1647}
1648
1649static inline void
1650rtw89_pci_rxbd_increase(struct rtw89_pci_rx_ring *rx_ring, u32 cnt)
1651{
1652	struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
1653
1654	bd_ring->wp += cnt;
1655
1656	if (bd_ring->wp >= bd_ring->len)
1657		bd_ring->wp -= bd_ring->len;
1658}
1659
1660static inline struct rtw89_pci_tx_data *RTW89_PCI_TX_SKB_CB(struct sk_buff *skb)
1661{
1662	struct rtw89_tx_skb_data *data = RTW89_TX_SKB_CB(skb);
1663
1664	BUILD_BUG_ON(sizeof(struct rtw89_tx_skb_data) +
1665		     sizeof(struct rtw89_pci_tx_data) >
1666		     sizeof_field(struct ieee80211_tx_info, driver_data));
1667
1668	return (struct rtw89_pci_tx_data *)data->hci_priv;
1669}
1670
1671static inline struct rtw89_pci_tx_bd_32 *
1672rtw89_pci_get_next_txbd(struct rtw89_pci_tx_ring *tx_ring)
1673{
1674	struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring;
1675	struct rtw89_pci_tx_bd_32 *tx_bd, *head;
1676
1677	head = bd_ring->head;
1678	tx_bd = head + bd_ring->wp;
1679
1680	return tx_bd;
1681}
1682
1683static inline struct rtw89_pci_tx_wd *
1684rtw89_pci_dequeue_txwd(struct rtw89_pci_tx_ring *tx_ring)
1685{
1686	struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
1687	struct rtw89_pci_tx_wd *txwd;
1688
1689	txwd = list_first_entry_or_null(&wd_ring->free_pages,
1690					struct rtw89_pci_tx_wd, list);
1691	if (!txwd)
1692		return NULL;
1693
1694	list_del_init(&txwd->list);
1695	txwd->len = 0;
1696	wd_ring->curr_num--;
1697
1698	return txwd;
1699}
1700
1701static inline void
1702rtw89_pci_enqueue_txwd(struct rtw89_pci_tx_ring *tx_ring,
1703		       struct rtw89_pci_tx_wd *txwd)
1704{
1705	struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
1706
1707	memset(txwd->vaddr, 0, wd_ring->page_size);
1708	list_add_tail(&txwd->list, &wd_ring->free_pages);
1709	wd_ring->curr_num++;
1710}
1711
1712static inline bool rtw89_pci_ltr_is_err_reg_val(u32 val)
1713{
1714	return val == 0xffffffff || val == 0xeaeaeaea;
1715}
1716
1717extern const struct dev_pm_ops rtw89_pm_ops;
1718extern const struct dev_pm_ops rtw89_pm_ops_be;
1719extern const struct pci_error_handlers rtw89_pci_err_handler;
1720extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set;
1721extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_v1;
1722extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_be;
1723extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_be_v1;
1724extern const struct rtw89_pci_bd_ram rtw89_bd_ram_table_dual[RTW89_TXCH_NUM];
1725extern const struct rtw89_pci_bd_ram rtw89_bd_ram_table_single[RTW89_TXCH_NUM];
1726extern const struct rtw89_pci_isr_def rtw89_pci_isr_ax;
1727extern const struct rtw89_pci_isr_def rtw89_pci_isr_be;
1728extern const struct rtw89_pci_isr_def rtw89_pci_isr_be_v1;
1729extern const struct rtw89_pci_gen_def rtw89_pci_gen_ax;
1730extern const struct rtw89_pci_gen_def rtw89_pci_gen_be;
1731
1732struct pci_device_id;
1733
1734int rtw89_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
1735void rtw89_pci_remove(struct pci_dev *pdev);
1736void rtw89_pci_basic_cfg(struct rtw89_dev *rtwdev, bool resume);
1737void rtw89_pci_ops_reset(struct rtw89_dev *rtwdev);
1738int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev, bool en);
1739int rtw89_pci_ltr_set_v1(struct rtw89_dev *rtwdev, bool en);
1740int rtw89_pci_ltr_set_v2(struct rtw89_dev *rtwdev, bool en);
1741u32 rtw89_pci_fill_txaddr_info(struct rtw89_dev *rtwdev,
1742			       void *txaddr_info_addr, u32 total_len,
1743			       dma_addr_t dma, u8 *add_info_nr);
1744u32 rtw89_pci_fill_txaddr_info_v1(struct rtw89_dev *rtwdev,
1745				  void *txaddr_info_addr, u32 total_len,
1746				  dma_addr_t dma, u8 *add_info_nr);
1747void rtw89_pci_parse_rpp(struct rtw89_dev *rtwdev, void *_rpp,
1748			 struct rtw89_pci_rpp_info *rpp_info);
1749void rtw89_pci_parse_rpp_v1(struct rtw89_dev *rtwdev, void *_rpp,
1750			    struct rtw89_pci_rpp_info *rpp_info);
1751void rtw89_pci_ctrl_dma_all(struct rtw89_dev *rtwdev, bool enable);
1752void rtw89_pci_config_intr_mask(struct rtw89_dev *rtwdev);
1753void rtw89_pci_config_intr_mask_v1(struct rtw89_dev *rtwdev);
1754void rtw89_pci_config_intr_mask_v2(struct rtw89_dev *rtwdev);
1755void rtw89_pci_config_intr_mask_v3(struct rtw89_dev *rtwdev);
1756void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1757void rtw89_pci_disable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1758void rtw89_pci_enable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1759void rtw89_pci_disable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1760void rtw89_pci_enable_intr_v2(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1761void rtw89_pci_disable_intr_v2(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1762void rtw89_pci_enable_intr_v3(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1763void rtw89_pci_disable_intr_v3(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1764void rtw89_pci_recognize_intrs(struct rtw89_dev *rtwdev,
1765			       struct rtw89_pci *rtwpci,
1766			       struct rtw89_pci_isrs *isrs);
1767void rtw89_pci_recognize_intrs_v1(struct rtw89_dev *rtwdev,
1768				  struct rtw89_pci *rtwpci,
1769				  struct rtw89_pci_isrs *isrs);
1770void rtw89_pci_recognize_intrs_v2(struct rtw89_dev *rtwdev,
1771				  struct rtw89_pci *rtwpci,
1772				  struct rtw89_pci_isrs *isrs);
1773void rtw89_pci_recognize_intrs_v3(struct rtw89_dev *rtwdev,
1774				  struct rtw89_pci *rtwpci,
1775				  struct rtw89_pci_isrs *isrs);
1776
1777static inline
1778u32 rtw89_chip_fill_txaddr_info(struct rtw89_dev *rtwdev,
1779				void *txaddr_info_addr, u32 total_len,
1780				dma_addr_t dma, u8 *add_info_nr)
1781{
1782	const struct rtw89_pci_info *info = rtwdev->pci_info;
1783
1784	return info->fill_txaddr_info(rtwdev, txaddr_info_addr, total_len,
1785				      dma, add_info_nr);
1786}
1787
1788static inline void rtw89_chip_config_intr_mask(struct rtw89_dev *rtwdev,
1789					       enum rtw89_pci_intr_mask_cfg cfg)
1790{
1791	struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1792	const struct rtw89_pci_info *info = rtwdev->pci_info;
1793
1794	switch (cfg) {
1795	default:
1796	case RTW89_PCI_INTR_MASK_RESET:
1797		rtwpci->low_power = false;
1798		rtwpci->under_recovery = false;
1799		break;
1800	case RTW89_PCI_INTR_MASK_NORMAL:
1801		rtwpci->low_power = false;
1802		break;
1803	case RTW89_PCI_INTR_MASK_LOW_POWER:
1804		rtwpci->low_power = true;
1805		break;
1806	case RTW89_PCI_INTR_MASK_RECOVERY_START:
1807		rtwpci->under_recovery = true;
1808		break;
1809	case RTW89_PCI_INTR_MASK_RECOVERY_COMPLETE:
1810		rtwpci->under_recovery = false;
1811		break;
1812	}
1813
1814	rtw89_debug(rtwdev, RTW89_DBG_HCI,
1815		    "Configure PCI interrupt mask mode low_power=%d under_recovery=%d\n",
1816		    rtwpci->low_power, rtwpci->under_recovery);
1817
1818	info->config_intr_mask(rtwdev);
1819}
1820
1821static inline
1822void rtw89_chip_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
1823{
1824	const struct rtw89_pci_info *info = rtwdev->pci_info;
1825
1826	info->enable_intr(rtwdev, rtwpci);
1827}
1828
1829static inline
1830void rtw89_chip_disable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
1831{
1832	const struct rtw89_pci_info *info = rtwdev->pci_info;
1833
1834	info->disable_intr(rtwdev, rtwpci);
1835}
1836
1837static inline
1838void rtw89_chip_recognize_intrs(struct rtw89_dev *rtwdev,
1839				struct rtw89_pci *rtwpci,
1840				struct rtw89_pci_isrs *isrs)
1841{
1842	const struct rtw89_pci_info *info = rtwdev->pci_info;
1843
1844	info->recognize_intrs(rtwdev, rtwpci, isrs);
1845}
1846
1847static inline int rtw89_pci_ops_mac_pre_init(struct rtw89_dev *rtwdev)
1848{
1849	const struct rtw89_pci_info *info = rtwdev->pci_info;
1850	const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1851
1852	return gen_def->mac_pre_init(rtwdev);
1853}
1854
1855static inline int rtw89_pci_ops_mac_pre_deinit(struct rtw89_dev *rtwdev)
1856{
1857	const struct rtw89_pci_info *info = rtwdev->pci_info;
1858	const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1859
1860	if (!gen_def->mac_pre_deinit)
1861		return 0;
1862
1863	return gen_def->mac_pre_deinit(rtwdev);
1864}
1865
1866static inline int rtw89_pci_ops_mac_post_init(struct rtw89_dev *rtwdev)
1867{
1868	const struct rtw89_pci_info *info = rtwdev->pci_info;
1869	const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1870
1871	return gen_def->mac_post_init(rtwdev);
1872}
1873
1874static inline void rtw89_pci_clr_idx_all(struct rtw89_dev *rtwdev)
1875{
1876	const struct rtw89_pci_info *info = rtwdev->pci_info;
1877	const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1878
1879	gen_def->clr_idx_all(rtwdev);
1880}
1881
1882static inline int rtw89_pci_reset_bdram(struct rtw89_dev *rtwdev)
1883{
1884	const struct rtw89_pci_info *info = rtwdev->pci_info;
1885	const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1886
1887	return gen_def->rst_bdram(rtwdev);
1888}
1889
1890static inline void rtw89_pci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable)
1891{
1892	const struct rtw89_pci_info *info = rtwdev->pci_info;
1893	const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1894
1895	return gen_def->ctrl_txdma_ch(rtwdev, enable);
1896}
1897
1898static inline void rtw89_pci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable)
1899{
1900	const struct rtw89_pci_info *info = rtwdev->pci_info;
1901	const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1902
1903	return gen_def->ctrl_txdma_fw_ch(rtwdev, enable);
1904}
1905
1906static inline int rtw89_pci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev)
1907{
1908	const struct rtw89_pci_info *info = rtwdev->pci_info;
1909	const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1910
1911	return gen_def->poll_txdma_ch_idle(rtwdev);
1912}
1913
1914static inline void rtw89_pci_disable_eq(struct rtw89_dev *rtwdev)
1915{
1916	const struct rtw89_pci_info *info = rtwdev->pci_info;
1917	const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1918
1919	gen_def->disable_eq(rtwdev);
1920}
1921
1922static inline void rtw89_pci_power_wake(struct rtw89_dev *rtwdev, bool pwr_up)
1923{
1924	const struct rtw89_pci_info *info = rtwdev->pci_info;
1925	const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1926
1927	gen_def->power_wake(rtwdev, pwr_up);
1928}
1929
1930#endif
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