mac.h

   1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2/* Copyright(c) 2019-2020  Realtek Corporation
   3 */
   4
   5#ifndef __RTW89_MAC_H__
   6#define __RTW89_MAC_H__
   7
   8#include "core.h"
   9#include "fw.h"
  10#include "reg.h"
  11
  12#define MAC_MEM_DUMP_PAGE_SIZE_AX 0x40000
  13#define MAC_MEM_DUMP_PAGE_SIZE_BE 0x80000
  14
  15#define ADDR_CAM_ENT_SIZE  0x40
  16#define ADDR_CAM_ENT_SHORT_SIZE 0x20
  17#define BSSID_CAM_ENT_SIZE 0x08
  18#define HFC_PAGE_UNIT 64
  19#define RPWM_TRY_CNT 3
  20
  21enum rtw89_mac_hwmod_sel {
  22	RTW89_DMAC_SEL = 0,
  23	RTW89_CMAC_SEL = 1,
  24
  25	RTW89_MAC_INVALID,
  26};
  27
  28enum rtw89_mac_fwd_target {
  29	RTW89_FWD_DONT_CARE    = 0,
  30	RTW89_FWD_TO_HOST      = 1,
  31	RTW89_FWD_TO_WLAN_CPU  = 2
  32};
  33
  34enum rtw89_mac_wd_dma_intvl {
  35	RTW89_MAC_WD_DMA_INTVL_0S,
  36	RTW89_MAC_WD_DMA_INTVL_256NS,
  37	RTW89_MAC_WD_DMA_INTVL_512NS,
  38	RTW89_MAC_WD_DMA_INTVL_768NS,
  39	RTW89_MAC_WD_DMA_INTVL_1US,
  40	RTW89_MAC_WD_DMA_INTVL_1_5US,
  41	RTW89_MAC_WD_DMA_INTVL_2US,
  42	RTW89_MAC_WD_DMA_INTVL_4US,
  43	RTW89_MAC_WD_DMA_INTVL_8US,
  44	RTW89_MAC_WD_DMA_INTVL_16US,
  45	RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE
  46};
  47
  48enum rtw89_mac_multi_tag_num {
  49	RTW89_MAC_TAG_NUM_1,
  50	RTW89_MAC_TAG_NUM_2,
  51	RTW89_MAC_TAG_NUM_3,
  52	RTW89_MAC_TAG_NUM_4,
  53	RTW89_MAC_TAG_NUM_5,
  54	RTW89_MAC_TAG_NUM_6,
  55	RTW89_MAC_TAG_NUM_7,
  56	RTW89_MAC_TAG_NUM_8,
  57	RTW89_MAC_TAG_NUM_DEF = 0xFE
  58};
  59
  60enum rtw89_mac_lbc_tmr {
  61	RTW89_MAC_LBC_TMR_8US = 0,
  62	RTW89_MAC_LBC_TMR_16US,
  63	RTW89_MAC_LBC_TMR_32US,
  64	RTW89_MAC_LBC_TMR_64US,
  65	RTW89_MAC_LBC_TMR_128US,
  66	RTW89_MAC_LBC_TMR_256US,
  67	RTW89_MAC_LBC_TMR_512US,
  68	RTW89_MAC_LBC_TMR_1MS,
  69	RTW89_MAC_LBC_TMR_2MS,
  70	RTW89_MAC_LBC_TMR_4MS,
  71	RTW89_MAC_LBC_TMR_8MS,
  72	RTW89_MAC_LBC_TMR_DEF = 0xFE
  73};
  74
  75enum rtw89_mac_cpuio_op_cmd_type {
  76	CPUIO_OP_CMD_GET_1ST_PID = 0,
  77	CPUIO_OP_CMD_GET_NEXT_PID = 1,
  78	CPUIO_OP_CMD_ENQ_TO_TAIL = 4,
  79	CPUIO_OP_CMD_ENQ_TO_HEAD = 5,
  80	CPUIO_OP_CMD_DEQ = 8,
  81	CPUIO_OP_CMD_DEQ_ENQ_ALL = 9,
  82	CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12
  83};
  84
  85enum rtw89_mac_wde_dle_port_id {
  86	WDE_DLE_PORT_ID_DISPATCH = 0,
  87	WDE_DLE_PORT_ID_PKTIN = 1,
  88	WDE_DLE_PORT_ID_CMAC0 = 3,
  89	WDE_DLE_PORT_ID_CMAC1 = 4,
  90	WDE_DLE_PORT_ID_CPU_IO = 6,
  91	WDE_DLE_PORT_ID_WDRLS = 7,
  92	WDE_DLE_PORT_ID_END = 8
  93};
  94
  95enum rtw89_mac_wde_dle_queid_wdrls {
  96	WDE_DLE_QUEID_TXOK = 0,
  97	WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1,
  98	WDE_DLE_QUEID_DROP_LIFETIME_TO = 2,
  99	WDE_DLE_QUEID_DROP_MACID_DROP = 3,
 100	WDE_DLE_QUEID_NO_REPORT = 4
 101};
 102
 103enum rtw89_mac_ple_dle_port_id {
 104	PLE_DLE_PORT_ID_DISPATCH = 0,
 105	PLE_DLE_PORT_ID_MPDU = 1,
 106	PLE_DLE_PORT_ID_SEC = 2,
 107	PLE_DLE_PORT_ID_CMAC0 = 3,
 108	PLE_DLE_PORT_ID_CMAC1 = 4,
 109	PLE_DLE_PORT_ID_WDRLS = 5,
 110	PLE_DLE_PORT_ID_CPU_IO = 6,
 111	PLE_DLE_PORT_ID_PLRLS = 7,
 112	PLE_DLE_PORT_ID_END = 8
 113};
 114
 115enum rtw89_mac_ple_dle_queid_plrls {
 116	PLE_DLE_QUEID_NO_REPORT = 0x0
 117};
 118
 119enum rtw89_machdr_frame_type {
 120	RTW89_MGNT = 0,
 121	RTW89_CTRL = 1,
 122	RTW89_DATA = 2,
 123};
 124
 125enum rtw89_mac_dle_dfi_type {
 126	DLE_DFI_TYPE_FREEPG	= 0,
 127	DLE_DFI_TYPE_QUOTA	= 1,
 128	DLE_DFI_TYPE_PAGELLT	= 2,
 129	DLE_DFI_TYPE_PKTINFO	= 3,
 130	DLE_DFI_TYPE_PREPKTLLT	= 4,
 131	DLE_DFI_TYPE_NXTPKTLLT	= 5,
 132	DLE_DFI_TYPE_QLNKTBL	= 6,
 133	DLE_DFI_TYPE_QEMPTY	= 7,
 134};
 135
 136enum rtw89_mac_dle_wde_quota_id {
 137	WDE_QTAID_HOST_IF = 0,
 138	WDE_QTAID_WLAN_CPU = 1,
 139	WDE_QTAID_DATA_CPU = 2,
 140	WDE_QTAID_PKTIN = 3,
 141	WDE_QTAID_CPUIO = 4,
 142};
 143
 144enum rtw89_mac_dle_ple_quota_id {
 145	PLE_QTAID_B0_TXPL = 0,
 146	PLE_QTAID_B1_TXPL = 1,
 147	PLE_QTAID_C2H = 2,
 148	PLE_QTAID_H2C = 3,
 149	PLE_QTAID_WLAN_CPU = 4,
 150	PLE_QTAID_MPDU = 5,
 151	PLE_QTAID_CMAC0_RX = 6,
 152	PLE_QTAID_CMAC1_RX = 7,
 153	PLE_QTAID_CMAC1_BBRPT = 8,
 154	PLE_QTAID_WDRLS = 9,
 155	PLE_QTAID_CPUIO = 10,
 156};
 157
 158enum rtw89_mac_dle_ctrl_type {
 159	DLE_CTRL_TYPE_WDE = 0,
 160	DLE_CTRL_TYPE_PLE = 1,
 161	DLE_CTRL_TYPE_NUM = 2,
 162};
 163
 164enum rtw89_mac_ax_l0_to_l1_event {
 165	MAC_AX_L0_TO_L1_CHIF_IDLE = 0,
 166	MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1,
 167	MAC_AX_L0_TO_L1_RLS_PKID = 2,
 168	MAC_AX_L0_TO_L1_PTCL_IDLE = 3,
 169	MAC_AX_L0_TO_L1_RX_QTA_LOST = 4,
 170	MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5,
 171	MAC_AX_L0_TO_L1_PCIE_STUCK = 6,
 172	MAC_AX_L0_TO_L1_EVENT_MAX = 15,
 173};
 174
 175enum rtw89_mac_phy_rpt_size {
 176	MAC_AX_PHY_RPT_SIZE_0 = 0,
 177	MAC_AX_PHY_RPT_SIZE_8 = 1,
 178	MAC_AX_PHY_RPT_SIZE_16 = 2,
 179	MAC_AX_PHY_RPT_SIZE_24 = 3,
 180};
 181
 182enum rtw89_mac_hdr_cnv_size {
 183	MAC_AX_HDR_CNV_SIZE_0 = 0,
 184	MAC_AX_HDR_CNV_SIZE_32 = 1,
 185	MAC_AX_HDR_CNV_SIZE_64 = 2,
 186	MAC_AX_HDR_CNV_SIZE_96 = 3,
 187};
 188
 189enum rtw89_mac_wow_fw_status {
 190	WOWLAN_NOT_READY = 0x00,
 191	WOWLAN_SLEEP_READY = 0x01,
 192	WOWLAN_RESUME_READY = 0x02,
 193};
 194
 195#define RTW89_PORT_OFFSET_TU_TO_32US(shift_tu) ((shift_tu) * 1024 / 32)
 196
 197enum rtw89_mac_dbg_port_sel {
 198	/* CMAC 0 related */
 199	RTW89_DBG_PORT_SEL_PTCL_C0 = 0,
 200	RTW89_DBG_PORT_SEL_SCH_C0,
 201	RTW89_DBG_PORT_SEL_TMAC_C0,
 202	RTW89_DBG_PORT_SEL_RMAC_C0,
 203	RTW89_DBG_PORT_SEL_RMACST_C0,
 204	RTW89_DBG_PORT_SEL_RMAC_PLCP_C0,
 205	RTW89_DBG_PORT_SEL_TRXPTCL_C0,
 206	RTW89_DBG_PORT_SEL_TX_INFOL_C0,
 207	RTW89_DBG_PORT_SEL_TX_INFOH_C0,
 208	RTW89_DBG_PORT_SEL_TXTF_INFOL_C0,
 209	RTW89_DBG_PORT_SEL_TXTF_INFOH_C0,
 210	/* CMAC 1 related */
 211	RTW89_DBG_PORT_SEL_PTCL_C1,
 212	RTW89_DBG_PORT_SEL_SCH_C1,
 213	RTW89_DBG_PORT_SEL_TMAC_C1,
 214	RTW89_DBG_PORT_SEL_RMAC_C1,
 215	RTW89_DBG_PORT_SEL_RMACST_C1,
 216	RTW89_DBG_PORT_SEL_RMAC_PLCP_C1,
 217	RTW89_DBG_PORT_SEL_TRXPTCL_C1,
 218	RTW89_DBG_PORT_SEL_TX_INFOL_C1,
 219	RTW89_DBG_PORT_SEL_TX_INFOH_C1,
 220	RTW89_DBG_PORT_SEL_TXTF_INFOL_C1,
 221	RTW89_DBG_PORT_SEL_TXTF_INFOH_C1,
 222	/* DLE related */
 223	RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG,
 224	RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA,
 225	RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT,
 226	RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO,
 227	RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT,
 228	RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT,
 229	RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL,
 230	RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY,
 231	RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG,
 232	RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA,
 233	RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT,
 234	RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO,
 235	RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT,
 236	RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT,
 237	RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL,
 238	RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY,
 239	RTW89_DBG_PORT_SEL_PKTINFO,
 240	/* DISPATCHER related */
 241	RTW89_DBG_PORT_SEL_DSPT_HDT_TX0,
 242	RTW89_DBG_PORT_SEL_DSPT_HDT_TX1,
 243	RTW89_DBG_PORT_SEL_DSPT_HDT_TX2,
 244	RTW89_DBG_PORT_SEL_DSPT_HDT_TX3,
 245	RTW89_DBG_PORT_SEL_DSPT_HDT_TX4,
 246	RTW89_DBG_PORT_SEL_DSPT_HDT_TX5,
 247	RTW89_DBG_PORT_SEL_DSPT_HDT_TX6,
 248	RTW89_DBG_PORT_SEL_DSPT_HDT_TX7,
 249	RTW89_DBG_PORT_SEL_DSPT_HDT_TX8,
 250	RTW89_DBG_PORT_SEL_DSPT_HDT_TX9,
 251	RTW89_DBG_PORT_SEL_DSPT_HDT_TXA,
 252	RTW89_DBG_PORT_SEL_DSPT_HDT_TXB,
 253	RTW89_DBG_PORT_SEL_DSPT_HDT_TXC,
 254	RTW89_DBG_PORT_SEL_DSPT_HDT_TXD,
 255	RTW89_DBG_PORT_SEL_DSPT_HDT_TXE,
 256	RTW89_DBG_PORT_SEL_DSPT_HDT_TXF,
 257	RTW89_DBG_PORT_SEL_DSPT_CDT_TX0,
 258	RTW89_DBG_PORT_SEL_DSPT_CDT_TX1,
 259	RTW89_DBG_PORT_SEL_DSPT_CDT_TX3,
 260	RTW89_DBG_PORT_SEL_DSPT_CDT_TX4,
 261	RTW89_DBG_PORT_SEL_DSPT_CDT_TX5,
 262	RTW89_DBG_PORT_SEL_DSPT_CDT_TX6,
 263	RTW89_DBG_PORT_SEL_DSPT_CDT_TX7,
 264	RTW89_DBG_PORT_SEL_DSPT_CDT_TX8,
 265	RTW89_DBG_PORT_SEL_DSPT_CDT_TX9,
 266	RTW89_DBG_PORT_SEL_DSPT_CDT_TXA,
 267	RTW89_DBG_PORT_SEL_DSPT_CDT_TXB,
 268	RTW89_DBG_PORT_SEL_DSPT_CDT_TXC,
 269	RTW89_DBG_PORT_SEL_DSPT_HDT_RX0,
 270	RTW89_DBG_PORT_SEL_DSPT_HDT_RX1,
 271	RTW89_DBG_PORT_SEL_DSPT_HDT_RX2,
 272	RTW89_DBG_PORT_SEL_DSPT_HDT_RX3,
 273	RTW89_DBG_PORT_SEL_DSPT_HDT_RX4,
 274	RTW89_DBG_PORT_SEL_DSPT_HDT_RX5,
 275	RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0,
 276	RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0,
 277	RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1,
 278	RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2,
 279	RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1,
 280	RTW89_DBG_PORT_SEL_DSPT_STF_CTRL,
 281	RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL,
 282	RTW89_DBG_PORT_SEL_DSPT_WDE_INTF,
 283	RTW89_DBG_PORT_SEL_DSPT_PLE_INTF,
 284	RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL,
 285	/* PCIE related */
 286	RTW89_DBG_PORT_SEL_PCIE_TXDMA,
 287	RTW89_DBG_PORT_SEL_PCIE_RXDMA,
 288	RTW89_DBG_PORT_SEL_PCIE_CVT,
 289	RTW89_DBG_PORT_SEL_PCIE_CXPL,
 290	RTW89_DBG_PORT_SEL_PCIE_IO,
 291	RTW89_DBG_PORT_SEL_PCIE_MISC,
 292	RTW89_DBG_PORT_SEL_PCIE_MISC2,
 293
 294	/* keep last */
 295	RTW89_DBG_PORT_SEL_LAST,
 296	RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST,
 297	RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST,
 298};
 299
 300/* SRAM mem dump */
 301#define R_AX_INDIR_ACCESS_ENTRY 0x40000
 302#define R_BE_INDIR_ACCESS_ENTRY 0x80000
 303
 304#define	AXIDMA_BASE_ADDR		0x18006000
 305#define	STA_SCHED_BASE_ADDR		0x18808000
 306#define	RXPLD_FLTR_CAM_BASE_ADDR	0x18813000
 307#define	SECURITY_CAM_BASE_ADDR		0x18814000
 308#define	WOW_CAM_BASE_ADDR		0x18815000
 309#define	CMAC_TBL_BASE_ADDR		0x18840000
 310#define	ADDR_CAM_BASE_ADDR		0x18850000
 311#define	BSSID_CAM_BASE_ADDR		0x18853000
 312#define	BA_CAM_BASE_ADDR		0x18854000
 313#define	BCN_IE_CAM0_BASE_ADDR		0x18855000
 314#define	SHARED_BUF_BASE_ADDR		0x18700000
 315#define	DMAC_TBL_BASE_ADDR		0x18800000
 316#define	SHCUT_MACHDR_BASE_ADDR		0x18800800
 317#define	BCN_IE_CAM1_BASE_ADDR		0x188A0000
 318#define	TXD_FIFO_0_BASE_ADDR		0x18856200
 319#define	TXD_FIFO_1_BASE_ADDR		0x188A1080
 320#define	TXD_FIFO_0_BASE_ADDR_V1		0x18856400 /* for 8852C */
 321#define	TXD_FIFO_1_BASE_ADDR_V1		0x188A1080 /* for 8852C */
 322#define	TXDATA_FIFO_0_BASE_ADDR		0x18856000
 323#define	TXDATA_FIFO_1_BASE_ADDR		0x188A1000
 324#define	CPU_LOCAL_BASE_ADDR		0x18003000
 325
 326#define WD_PAGE_BASE_ADDR_BE		0x0
 327#define CPU_LOCAL_BASE_ADDR_BE		0x18003000
 328#define AXIDMA_BASE_ADDR_BE		0x18006000
 329#define SHARED_BUF_BASE_ADDR_BE		0x18700000
 330#define DMAC_TBL_BASE_ADDR_BE		0x18800000
 331#define SHCUT_MACHDR_BASE_ADDR_BE	0x18800800
 332#define STA_SCHED_BASE_ADDR_BE		0x18818000
 333#define NAT25_CAM_BASE_ADDR_BE		0x18820000
 334#define RXPLD_FLTR_CAM_BASE_ADDR_BE	0x18823000
 335#define SEC_CAM_BASE_ADDR_BE		0x18824000
 336#define WOW_CAM_BASE_ADDR_BE		0x18828000
 337#define MLD_TBL_BASE_ADDR_BE		0x18829000
 338#define RX_CLSF_CAM_BASE_ADDR_BE	0x1882A000
 339#define CMAC_TBL_BASE_ADDR_BE		0x18840000
 340#define ADDR_CAM_BASE_ADDR_BE		0x18850000
 341#define BSSID_CAM_BASE_ADDR_BE		0x18858000
 342#define BA_CAM_BASE_ADDR_BE		0x18859000
 343#define BCN_IE_CAM0_BASE_ADDR_BE	0x18860000
 344#define TXDATA_FIFO_0_BASE_ADDR_BE	0x18861000
 345#define TXD_FIFO_0_BASE_ADDR_BE		0x18862000
 346#define BCN_IE_CAM1_BASE_ADDR_BE	0x18880000
 347#define TXDATA_FIFO_1_BASE_ADDR_BE	0x18881000
 348#define TXD_FIFO_1_BASE_ADDR_BE		0x18881800
 349#define DCPU_LOCAL_BASE_ADDR_BE		0x19C02000
 350
 351#define CCTL_INFO_SIZE		32
 352
 353enum rtw89_mac_mem_sel {
 354	RTW89_MAC_MEM_AXIDMA,
 355	RTW89_MAC_MEM_SHARED_BUF,
 356	RTW89_MAC_MEM_DMAC_TBL,
 357	RTW89_MAC_MEM_SHCUT_MACHDR,
 358	RTW89_MAC_MEM_STA_SCHED,
 359	RTW89_MAC_MEM_RXPLD_FLTR_CAM,
 360	RTW89_MAC_MEM_SECURITY_CAM,
 361	RTW89_MAC_MEM_WOW_CAM,
 362	RTW89_MAC_MEM_CMAC_TBL,
 363	RTW89_MAC_MEM_ADDR_CAM,
 364	RTW89_MAC_MEM_BA_CAM,
 365	RTW89_MAC_MEM_BCN_IE_CAM0,
 366	RTW89_MAC_MEM_BCN_IE_CAM1,
 367	RTW89_MAC_MEM_TXD_FIFO_0,
 368	RTW89_MAC_MEM_TXD_FIFO_1,
 369	RTW89_MAC_MEM_TXDATA_FIFO_0,
 370	RTW89_MAC_MEM_TXDATA_FIFO_1,
 371	RTW89_MAC_MEM_CPU_LOCAL,
 372	RTW89_MAC_MEM_BSSID_CAM,
 373	RTW89_MAC_MEM_TXD_FIFO_0_V1,
 374	RTW89_MAC_MEM_TXD_FIFO_1_V1,
 375	RTW89_MAC_MEM_WD_PAGE,
 376	RTW89_MAC_MEM_MLD_TBL,
 377
 378	/* keep last */
 379	RTW89_MAC_MEM_NUM,
 380};
 381
 382enum rtw89_rpwm_req_pwr_state {
 383	RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0,
 384	RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1,
 385	RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2,
 386	RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3,
 387	RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4,
 388	RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5,
 389	RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6,
 390	RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7,
 391	RTW89_MAC_RPWM_REQ_PWR_STATE_MAX,
 392};
 393
 394struct rtw89_pwr_cfg {
 395	u16 addr;
 396	u8 cv_msk;
 397	u8 intf_msk;
 398	u8 base:4;
 399	u8 cmd:4;
 400	u8 msk;
 401	u8 val;
 402};
 403
 404enum rtw89_mac_c2h_ofld_func {
 405	RTW89_MAC_C2H_FUNC_EFUSE_DUMP,
 406	RTW89_MAC_C2H_FUNC_READ_RSP,
 407	RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP,
 408	RTW89_MAC_C2H_FUNC_BCN_RESEND,
 409	RTW89_MAC_C2H_FUNC_MACID_PAUSE,
 410	RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6,
 411	RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9,
 412	RTW89_MAC_C2H_FUNC_TX_DUTY_RPT = 0xa,
 413	RTW89_MAC_C2H_FUNC_BCNFLTR_RPT = 0xd,
 414	RTW89_MAC_C2H_FUNC_OFLD_MAX,
 415};
 416
 417enum rtw89_mac_c2h_info_func {
 418	RTW89_MAC_C2H_FUNC_REC_ACK,
 419	RTW89_MAC_C2H_FUNC_DONE_ACK,
 420	RTW89_MAC_C2H_FUNC_C2H_LOG,
 421	RTW89_MAC_C2H_FUNC_BCN_CNT,
 422	RTW89_MAC_C2H_FUNC_BCN_UPD_DONE = 0x06,
 423	RTW89_MAC_C2H_FUNC_INFO_MAX,
 424};
 425
 426enum rtw89_mac_c2h_mcc_func {
 427	RTW89_MAC_C2H_FUNC_MCC_RCV_ACK = 0,
 428	RTW89_MAC_C2H_FUNC_MCC_REQ_ACK = 1,
 429	RTW89_MAC_C2H_FUNC_MCC_TSF_RPT = 2,
 430	RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT = 3,
 431
 432	NUM_OF_RTW89_MAC_C2H_FUNC_MCC,
 433};
 434
 435enum rtw89_mac_c2h_misc_func {
 436	RTW89_MAC_C2H_FUNC_TX_REPORT = 1,
 437
 438	NUM_OF_RTW89_MAC_C2H_FUNC_MISC,
 439};
 440
 441enum rtw89_mac_c2h_mlo_func {
 442	RTW89_MAC_C2H_FUNC_MLO_GET_TBL			= 0x0,
 443	RTW89_MAC_C2H_FUNC_MLO_EMLSR_TRANS_DONE		= 0x1,
 444	RTW89_MAC_C2H_FUNC_MLO_EMLSR_STA_CFG_DONE	= 0x2,
 445	RTW89_MAC_C2H_FUNC_MCMLO_RELINK_RPT		= 0x3,
 446	RTW89_MAC_C2H_FUNC_MCMLO_SN_SYNC_RPT		= 0x4,
 447	RTW89_MAC_C2H_FUNC_MLO_LINK_CFG_STAT		= 0x5,
 448	RTW89_MAC_C2H_FUNC_MLO_DM_DBG_DUMP		= 0x6,
 449
 450	NUM_OF_RTW89_MAC_C2H_FUNC_MLO,
 451};
 452
 453enum rtw89_mac_c2h_mrc_func {
 454	RTW89_MAC_C2H_FUNC_MRC_TSF_RPT = 0,
 455	RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT = 1,
 456
 457	NUM_OF_RTW89_MAC_C2H_FUNC_MRC,
 458};
 459
 460enum rtw89_mac_c2h_wow_func {
 461	RTW89_MAC_C2H_FUNC_AOAC_REPORT,
 462
 463	NUM_OF_RTW89_MAC_C2H_FUNC_WOW,
 464};
 465
 466enum rtw89_mac_c2h_ap_func {
 467	RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY = 0,
 468
 469	NUM_OF_RTW89_MAC_C2H_FUNC_AP,
 470};
 471
 472enum rtw89_mac_c2h_class {
 473	RTW89_MAC_C2H_CLASS_INFO = 0x0,
 474	RTW89_MAC_C2H_CLASS_OFLD = 0x1,
 475	RTW89_MAC_C2H_CLASS_TWT = 0x2,
 476	RTW89_MAC_C2H_CLASS_WOW = 0x3,
 477	RTW89_MAC_C2H_CLASS_MCC = 0x4,
 478	RTW89_MAC_C2H_CLASS_FWDBG = 0x5,
 479	RTW89_MAC_C2H_CLASS_MISC = 0x9,
 480	RTW89_MAC_C2H_CLASS_MLO = 0xc,
 481	RTW89_MAC_C2H_CLASS_MRC = 0xe,
 482	RTW89_MAC_C2H_CLASS_AP = 0x18,
 483	RTW89_MAC_C2H_CLASS_ROLE = 0x1b,
 484	RTW89_MAC_C2H_CLASS_MAX,
 485};
 486
 487enum rtw89_mac_mcc_status {
 488	RTW89_MAC_MCC_ADD_ROLE_OK = 0,
 489	RTW89_MAC_MCC_START_GROUP_OK = 1,
 490	RTW89_MAC_MCC_STOP_GROUP_OK = 2,
 491	RTW89_MAC_MCC_DEL_GROUP_OK = 3,
 492	RTW89_MAC_MCC_RESET_GROUP_OK = 4,
 493	RTW89_MAC_MCC_SWITCH_CH_OK = 5,
 494	RTW89_MAC_MCC_TXNULL0_OK = 6,
 495	RTW89_MAC_MCC_TXNULL1_OK = 7,
 496
 497	RTW89_MAC_MCC_SWITCH_EARLY = 10,
 498	RTW89_MAC_MCC_TBTT = 11,
 499	RTW89_MAC_MCC_DURATION_START = 12,
 500	RTW89_MAC_MCC_DURATION_END = 13,
 501
 502	RTW89_MAC_MCC_ADD_ROLE_FAIL = 20,
 503	RTW89_MAC_MCC_START_GROUP_FAIL = 21,
 504	RTW89_MAC_MCC_STOP_GROUP_FAIL = 22,
 505	RTW89_MAC_MCC_DEL_GROUP_FAIL = 23,
 506	RTW89_MAC_MCC_RESET_GROUP_FAIL = 24,
 507	RTW89_MAC_MCC_SWITCH_CH_FAIL = 25,
 508	RTW89_MAC_MCC_TXNULL0_FAIL = 26,
 509	RTW89_MAC_MCC_TXNULL1_FAIL = 27,
 510};
 511
 512enum rtw89_mac_mrc_status {
 513	RTW89_MAC_MRC_START_SCH_OK = 0,
 514	RTW89_MAC_MRC_STOP_SCH_OK = 1,
 515	RTW89_MAC_MRC_DEL_SCH_OK = 2,
 516	RTW89_MAC_MRC_EMPTY_SCH_FAIL = 16,
 517	RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL = 17,
 518	RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL = 18,
 519	RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL = 19,
 520	RTW89_MAC_MRC_ALT_ROLE_FAIL = 20,
 521	RTW89_MAC_MRC_ADD_PSTIMER_FAIL = 21,
 522	RTW89_MAC_MRC_MALLOC_FAIL = 22,
 523	RTW89_MAC_MRC_SWITCH_CH_FAIL = 23,
 524	RTW89_MAC_MRC_TXNULL0_FAIL = 24,
 525	RTW89_MAC_MRC_PORT_FUNC_EN_FAIL = 25,
 526};
 527
 528struct rtw89_mac_ax_coex {
 529#define RTW89_MAC_AX_COEX_RTK_MODE 0
 530#define RTW89_MAC_AX_COEX_CSR_MODE 1
 531	u8 pta_mode;
 532#define RTW89_MAC_AX_COEX_INNER 0
 533#define RTW89_MAC_AX_COEX_OUTPUT 1
 534#define RTW89_MAC_AX_COEX_INPUT 2
 535	u8 direction;
 536};
 537
 538struct rtw89_mac_ax_plt {
 539#define RTW89_MAC_AX_PLT_LTE_RX BIT(0)
 540#define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1)
 541#define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2)
 542#define RTW89_MAC_AX_PLT_GNT_WL BIT(3)
 543	u8 band;
 544	u8 tx;
 545	u8 rx;
 546};
 547
 548enum rtw89_mac_bf_rrsc_rate {
 549	RTW89_MAC_BF_RRSC_6M = 0,
 550	RTW89_MAC_BF_RRSC_9M = 1,
 551	RTW89_MAC_BF_RRSC_12M,
 552	RTW89_MAC_BF_RRSC_18M,
 553	RTW89_MAC_BF_RRSC_24M,
 554	RTW89_MAC_BF_RRSC_36M,
 555	RTW89_MAC_BF_RRSC_48M,
 556	RTW89_MAC_BF_RRSC_54M,
 557	RTW89_MAC_BF_RRSC_HT_MSC0,
 558	RTW89_MAC_BF_RRSC_HT_MSC1,
 559	RTW89_MAC_BF_RRSC_HT_MSC2,
 560	RTW89_MAC_BF_RRSC_HT_MSC3,
 561	RTW89_MAC_BF_RRSC_HT_MSC4,
 562	RTW89_MAC_BF_RRSC_HT_MSC5,
 563	RTW89_MAC_BF_RRSC_HT_MSC6,
 564	RTW89_MAC_BF_RRSC_HT_MSC7,
 565	RTW89_MAC_BF_RRSC_VHT_MSC0,
 566	RTW89_MAC_BF_RRSC_VHT_MSC1,
 567	RTW89_MAC_BF_RRSC_VHT_MSC2,
 568	RTW89_MAC_BF_RRSC_VHT_MSC3,
 569	RTW89_MAC_BF_RRSC_VHT_MSC4,
 570	RTW89_MAC_BF_RRSC_VHT_MSC5,
 571	RTW89_MAC_BF_RRSC_VHT_MSC6,
 572	RTW89_MAC_BF_RRSC_VHT_MSC7,
 573	RTW89_MAC_BF_RRSC_HE_MSC0,
 574	RTW89_MAC_BF_RRSC_HE_MSC1,
 575	RTW89_MAC_BF_RRSC_HE_MSC2,
 576	RTW89_MAC_BF_RRSC_HE_MSC3,
 577	RTW89_MAC_BF_RRSC_HE_MSC4,
 578	RTW89_MAC_BF_RRSC_HE_MSC5,
 579	RTW89_MAC_BF_RRSC_HE_MSC6,
 580	RTW89_MAC_BF_RRSC_HE_MSC7 = 31,
 581	RTW89_MAC_BF_RRSC_MAX = 32
 582};
 583
 584#define MAC_REG_POOL_COUNT	10
 585#define ACCESS_CMAC(_addr) \
 586	({typeof(_addr) __addr = (_addr); \
 587	  __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; })
 588#define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000
 589#define RTW89_MAC_BE_BAND_REG_OFFSET 0x4000
 590
 591#define PTCL_IDLE_POLL_CNT	10000
 592#define SW_CVR_DUR_US	8
 593#define SW_CVR_CNT	8
 594
 595#define DLE_BOUND_UNIT (8 * 1024)
 596#define DLE_WAIT_CNT 2000
 597#define TRXCFG_WAIT_CNT	2000
 598
 599#define RTW89_WDE_PG_64		64
 600#define RTW89_WDE_PG_128	128
 601#define RTW89_WDE_PG_256	256
 602
 603#define S_AX_WDE_PAGE_SEL_64	0
 604#define S_AX_WDE_PAGE_SEL_128	1
 605#define S_AX_WDE_PAGE_SEL_256	2
 606
 607#define RTW89_PLE_PG_64		64
 608#define RTW89_PLE_PG_128	128
 609#define RTW89_PLE_PG_256	256
 610
 611#define S_AX_PLE_PAGE_SEL_64	0
 612#define S_AX_PLE_PAGE_SEL_128	1
 613#define S_AX_PLE_PAGE_SEL_256	2
 614
 615#define B_CMAC0_MGQ_NORMAL	BIT(2)
 616#define B_CMAC0_MGQ_NO_PWRSAV	BIT(3)
 617#define B_CMAC0_CPUMGQ		BIT(4)
 618#define B_CMAC1_MGQ_NORMAL	BIT(10)
 619#define B_CMAC1_MGQ_NO_PWRSAV	BIT(11)
 620#define B_CMAC1_CPUMGQ		BIT(12)
 621
 622#define B_CMAC0_MGQ_NORMAL_BE	BIT(2)
 623#define B_CMAC1_MGQ_NORMAL_BE	BIT(30)
 624
 625#define QEMP_ACQ_GRP_MACID_NUM	8
 626#define QEMP_ACQ_GRP_QSEL_SH	4
 627#define QEMP_ACQ_GRP_QSEL_MASK	0xF
 628
 629#define SDIO_LOCAL_BASE_ADDR    0x80000000
 630
 631#define	PWR_CMD_WRITE		0
 632#define	PWR_CMD_POLL		1
 633#define	PWR_CMD_DELAY		2
 634#define	PWR_CMD_END		3
 635
 636#define	PWR_INTF_MSK_SDIO	BIT(0)
 637#define	PWR_INTF_MSK_USB	BIT(1)
 638#define	PWR_INTF_MSK_PCIE	BIT(2)
 639#define	PWR_INTF_MSK_ALL	0x7
 640
 641#define PWR_BASE_MAC		0
 642#define PWR_BASE_USB		1
 643#define PWR_BASE_PCIE		2
 644#define PWR_BASE_SDIO		3
 645
 646#define	PWR_CV_MSK_A		BIT(0)
 647#define	PWR_CV_MSK_B		BIT(1)
 648#define	PWR_CV_MSK_C		BIT(2)
 649#define	PWR_CV_MSK_D		BIT(3)
 650#define	PWR_CV_MSK_E		BIT(4)
 651#define	PWR_CV_MSK_F		BIT(5)
 652#define	PWR_CV_MSK_G		BIT(6)
 653#define	PWR_CV_MSK_TEST		BIT(7)
 654#define	PWR_CV_MSK_ALL		0xFF
 655
 656#define	PWR_DELAY_US		0
 657#define	PWR_DELAY_MS		1
 658
 659/* STA scheduler */
 660#define SS_MACID_SH		8
 661#define SS_TX_LEN_MSK		0x1FFFFF
 662#define SS_CTRL1_R_TX_LEN	5
 663#define SS_CTRL1_R_NEXT_LINK	20
 664#define SS_LINK_SIZE		256
 665
 666/* MAC debug port */
 667#define TMAC_DBG_SEL_C0 0xA5
 668#define RMAC_DBG_SEL_C0 0xA6
 669#define TRXPTCL_DBG_SEL_C0 0xA7
 670#define TMAC_DBG_SEL_C1 0xB5
 671#define RMAC_DBG_SEL_C1 0xB6
 672#define TRXPTCL_DBG_SEL_C1 0xB7
 673#define FW_PROG_CNTR_DBG_SEL 0xF2
 674#define PCIE_TXDMA_DBG_SEL 0x30
 675#define PCIE_RXDMA_DBG_SEL 0x31
 676#define PCIE_CVT_DBG_SEL 0x32
 677#define PCIE_CXPL_DBG_SEL 0x33
 678#define PCIE_IO_DBG_SEL 0x37
 679#define PCIE_MISC_DBG_SEL 0x38
 680#define PCIE_MISC2_DBG_SEL 0x00
 681#define MAC_DBG_SEL 1
 682#define RMAC_CMAC_DBG_SEL 1
 683
 684/* TRXPTCL dbg port sel */
 685#define TRXPTRL_DBG_SEL_TMAC 0
 686#define TRXPTRL_DBG_SEL_RMAC 1
 687
 688struct rtw89_cpuio_ctrl {
 689	u16 pkt_num;
 690	u16 start_pktid;
 691	u16 end_pktid;
 692	u8 cmd_type;
 693	u8 macid;
 694	u8 src_pid;
 695	u8 src_qid;
 696	u8 dst_pid;
 697	u8 dst_qid;
 698	u16 pktid;
 699};
 700
 701struct rtw89_mac_dbg_port_info {
 702	u32 sel_addr;
 703	u8 sel_byte;
 704	u32 sel_msk;
 705	u32 srt;
 706	u32 end;
 707	u32 rd_addr;
 708	u8 rd_byte;
 709	u32 rd_msk;
 710};
 711
 712#define QLNKTBL_ADDR_INFO_SEL BIT(0)
 713#define QLNKTBL_ADDR_INFO_SEL_0 0
 714#define QLNKTBL_ADDR_INFO_SEL_1 1
 715#define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1)
 716#define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0)
 717
 718struct rtw89_mac_dle_dfi_ctrl {
 719	enum rtw89_mac_dle_ctrl_type type;
 720	u32 target;
 721	u32 addr;
 722	u32 out_data;
 723};
 724
 725struct rtw89_mac_dle_dfi_quota {
 726	enum rtw89_mac_dle_ctrl_type dle_type;
 727	u32 qtaid;
 728	u16 rsv_pgnum;
 729	u16 use_pgnum;
 730};
 731
 732struct rtw89_mac_dle_dfi_qempty {
 733	enum rtw89_mac_dle_ctrl_type dle_type;
 734	u32 grpsel;
 735	u32 qempty;
 736};
 737
 738enum rtw89_mac_dle_rsvd_qt_type {
 739	DLE_RSVD_QT_MPDU_INFO,
 740	DLE_RSVD_QT_B0_CSI,
 741	DLE_RSVD_QT_B1_CSI,
 742	DLE_RSVD_QT_B0_LMR,
 743	DLE_RSVD_QT_B1_LMR,
 744	DLE_RSVD_QT_B0_FTM,
 745	DLE_RSVD_QT_B1_FTM,
 746};
 747
 748struct rtw89_mac_dle_rsvd_qt_cfg {
 749	u16 pktid;
 750	u16 pg_num;
 751	u32 size;
 752};
 753
 754enum rtw89_mac_error_scenario {
 755	RTW89_RXI300_ERROR		= 1,
 756	RTW89_WCPU_CPU_EXCEPTION	= 2,
 757	RTW89_WCPU_ASSERTION		= 3,
 758};
 759
 760#define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28)
 761
 762/* Define DBG and recovery enum */
 763enum mac_ax_err_info {
 764	/* Get error info */
 765
 766	/* L0 */
 767	MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001,
 768	MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002,
 769	MAC_AX_ERR_L0_RESET_DONE = 0x0003,
 770	MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010,
 771
 772	/* L1 */
 773	MAC_AX_ERR_L1_PREERR_DMAC = 0x999,
 774	MAC_AX_ERR_L1_ERR_DMAC = 0x1000,
 775	MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001,
 776	MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002,
 777	MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010,
 778	MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011,
 779
 780	/* L2 */
 781	/* address hole (master) */
 782	MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000,
 783	MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010,
 784	MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020,
 785	MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030,
 786	MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040,
 787	MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050,
 788	MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060,
 789	MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070,
 790
 791	/* AHB bridge timeout (master) */
 792	MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100,
 793	MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110,
 794	MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120,
 795	MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130,
 796	MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140,
 797	MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150,
 798	MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160,
 799	MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170,
 800
 801	/* APB_SA bridge timeout (master + slave) */
 802	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200,
 803	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201,
 804	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202,
 805	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203,
 806	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204,
 807	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205,
 808	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206,
 809	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207,
 810	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208,
 811	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209,
 812	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A,
 813	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210,
 814	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211,
 815	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212,
 816	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213,
 817	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214,
 818	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215,
 819	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216,
 820	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218,
 821	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219,
 822	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A,
 823	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220,
 824	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221,
 825	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222,
 826	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223,
 827	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224,
 828	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225,
 829	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226,
 830	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227,
 831	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228,
 832	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229,
 833	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A,
 834	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230,
 835	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231,
 836	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232,
 837	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233,
 838	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234,
 839	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235,
 840	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236,
 841	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237,
 842	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238,
 843	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239,
 844	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A,
 845	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240,
 846	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241,
 847	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242,
 848	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243,
 849	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244,
 850	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245,
 851	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246,
 852	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247,
 853	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248,
 854	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249,
 855	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A,
 856	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250,
 857	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251,
 858	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252,
 859	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253,
 860	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254,
 861	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255,
 862	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256,
 863	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257,
 864	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258,
 865	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259,
 866	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A,
 867	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260,
 868	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261,
 869	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262,
 870	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263,
 871	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264,
 872	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265,
 873	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266,
 874	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267,
 875	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268,
 876	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269,
 877	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A,
 878	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270,
 879	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271,
 880	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272,
 881	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273,
 882	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274,
 883	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275,
 884	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276,
 885	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277,
 886	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278,
 887	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279,
 888	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A,
 889
 890	/* APB_BBRF bridge timeout (master) */
 891	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300,
 892	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310,
 893	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320,
 894	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330,
 895	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340,
 896	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350,
 897	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360,
 898	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370,
 899	MAC_AX_ERR_L2_RESET_DONE = 0x2400,
 900	MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599,
 901	MAC_AX_ERR_CPU_EXCEPTION = 0x3000,
 902	MAC_AX_ERR_ASSERTION = 0x4000,
 903	MAC_AX_ERR_RXI300 = 0x5000,
 904	MAC_AX_GET_ERR_MAX,
 905	MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000,
 906
 907	/* set error info */
 908	MAC_AX_ERR_L1_DISABLE_EN = 0x0001,
 909	MAC_AX_ERR_L1_RCVY_EN = 0x0002,
 910	MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003,
 911	MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004,
 912	MAC_AX_ERR_L1_RESET_START_DMAC = 0x000A,
 913	MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010,
 914	MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011,
 915	MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012,
 916	MAC_AX_ERR_L0_RCVY_EN = 0x0013,
 917	MAC_AX_SET_ERR_MAX,
 918};
 919
 920struct rtw89_mac_size_set {
 921	const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie;
 922	const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c0;
 923	const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c2;
 924	const struct rtw89_dle_size wde_size0;
 925	const struct rtw89_dle_size wde_size1;
 926	const struct rtw89_dle_size wde_size0_v1;
 927	const struct rtw89_dle_size wde_size4;
 928	const struct rtw89_dle_size wde_size4_v1;
 929	const struct rtw89_dle_size wde_size6;
 930	const struct rtw89_dle_size wde_size7;
 931	const struct rtw89_dle_size wde_size9;
 932	const struct rtw89_dle_size wde_size17;
 933	const struct rtw89_dle_size wde_size18;
 934	const struct rtw89_dle_size wde_size19;
 935	const struct rtw89_dle_size wde_size23;
 936	const struct rtw89_dle_size wde_size25;
 937	const struct rtw89_dle_size wde_size31;
 938	const struct rtw89_dle_size ple_size0;
 939	const struct rtw89_dle_size ple_size1;
 940	const struct rtw89_dle_size ple_size0_v1;
 941	const struct rtw89_dle_size ple_size3_v1;
 942	const struct rtw89_dle_size ple_size4;
 943	const struct rtw89_dle_size ple_size6;
 944	const struct rtw89_dle_size ple_size8;
 945	const struct rtw89_dle_size ple_size9;
 946	const struct rtw89_dle_size ple_size17;
 947	const struct rtw89_dle_size ple_size18;
 948	const struct rtw89_dle_size ple_size19;
 949	const struct rtw89_dle_size ple_size32;
 950	const struct rtw89_dle_size ple_size33;
 951	const struct rtw89_dle_size ple_size34;
 952	const struct rtw89_wde_quota wde_qt0;
 953	const struct rtw89_wde_quota wde_qt1;
 954	const struct rtw89_wde_quota wde_qt0_v1;
 955	const struct rtw89_wde_quota wde_qt4;
 956	const struct rtw89_wde_quota wde_qt6;
 957	const struct rtw89_wde_quota wde_qt7;
 958	const struct rtw89_wde_quota wde_qt16;
 959	const struct rtw89_wde_quota wde_qt17;
 960	const struct rtw89_wde_quota wde_qt18;
 961	const struct rtw89_wde_quota wde_qt23;
 962	const struct rtw89_wde_quota wde_qt25;
 963	const struct rtw89_wde_quota wde_qt31;
 964	const struct rtw89_ple_quota ple_qt0;
 965	const struct rtw89_ple_quota ple_qt1;
 966	const struct rtw89_ple_quota ple_qt4;
 967	const struct rtw89_ple_quota ple_qt5;
 968	const struct rtw89_ple_quota ple_qt9;
 969	const struct rtw89_ple_quota ple_qt13;
 970	const struct rtw89_ple_quota ple_qt18;
 971	const struct rtw89_ple_quota ple_qt25;
 972	const struct rtw89_ple_quota ple_qt26;
 973	const struct rtw89_ple_quota ple_qt42;
 974	const struct rtw89_ple_quota ple_qt43;
 975	const struct rtw89_ple_quota ple_qt44;
 976	const struct rtw89_ple_quota ple_qt45;
 977	const struct rtw89_ple_quota ple_qt46;
 978	const struct rtw89_ple_quota ple_qt47;
 979	const struct rtw89_ple_quota ple_qt57;
 980	const struct rtw89_ple_quota ple_qt58;
 981	const struct rtw89_ple_quota ple_qt59;
 982	const struct rtw89_ple_quota ple_qt72;
 983	const struct rtw89_ple_quota ple_qt73;
 984	const struct rtw89_ple_quota ple_qt74;
 985	const struct rtw89_ple_quota ple_qt75;
 986	const struct rtw89_ple_quota ple_qt78;
 987	const struct rtw89_ple_quota ple_qt79;
 988	const struct rtw89_ple_quota ple_qt_52a_wow;
 989	const struct rtw89_ple_quota ple_qt_52b_wow;
 990	const struct rtw89_ple_quota ple_qt_52bt_wow;
 991	const struct rtw89_ple_quota ple_qt_51b_wow;
 992	const struct rtw89_rsvd_quota ple_rsvd_qt0;
 993	const struct rtw89_rsvd_quota ple_rsvd_qt1;
 994	const struct rtw89_dle_rsvd_size rsvd0_size0;
 995	const struct rtw89_dle_rsvd_size rsvd1_size0;
 996};
 997
 998extern const struct rtw89_mac_size_set rtw89_mac_size;
 999
1000struct rtw89_mac_gen_def {
1001	u32 band1_offset;
1002	u32 filter_model_addr;
1003	u32 indir_access_addr;
1004	const u32 *mem_base_addrs;
1005	u32 mem_page_size;
1006	u32 rx_fltr;
1007	const struct rtw89_port_reg *port_base;
1008	u32 agg_len_ht;
1009	u32 ps_status;
1010
1011	struct rtw89_reg_def muedca_ctrl;
1012	struct rtw89_reg_def bfee_ctrl;
1013	struct rtw89_reg_def narrow_bw_ru_dis;
1014	struct rtw89_reg_def wow_ctrl;
1015	struct rtw89_reg_def agg_limit;
1016	struct rtw89_reg_def txcnt_limit;
1017
1018	int (*check_mac_en)(struct rtw89_dev *rtwdev, u8 band,
1019			    enum rtw89_mac_hwmod_sel sel);
1020	int (*sys_init)(struct rtw89_dev *rtwdev);
1021	int (*trx_init)(struct rtw89_dev *rtwdev);
1022	void (*err_imr_ctrl)(struct rtw89_dev *rtwdev, bool en);
1023	void (*hci_func_en)(struct rtw89_dev *rtwdev);
1024	void (*dmac_func_pre_en)(struct rtw89_dev *rtwdev);
1025	void (*dle_func_en)(struct rtw89_dev *rtwdev, bool enable);
1026	void (*dle_clk_en)(struct rtw89_dev *rtwdev, bool enable);
1027	void (*bf_assoc)(struct rtw89_dev *rtwdev,
1028			 struct rtw89_vif_link *rtwvif_link,
1029			 struct rtw89_sta_link *rtwsta_link);
1030
1031	int (*typ_fltr_opt)(struct rtw89_dev *rtwdev,
1032			    enum rtw89_machdr_frame_type type,
1033			    enum rtw89_mac_fwd_target fwd_target,
1034			    u8 mac_idx);
1035	int (*cfg_ppdu_status)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable);
1036	void (*cfg_phy_rpt)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable);
1037
1038	int (*dle_mix_cfg)(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg);
1039	int (*chk_dle_rdy)(struct rtw89_dev *rtwdev, bool wde_or_ple);
1040	int (*dle_buf_req)(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id);
1041	void (*hfc_func_en)(struct rtw89_dev *rtwdev, bool en, bool h2c_en);
1042	void (*hfc_h2c_cfg)(struct rtw89_dev *rtwdev);
1043	void (*hfc_mix_cfg)(struct rtw89_dev *rtwdev);
1044	void (*hfc_get_mix_info)(struct rtw89_dev *rtwdev);
1045	void (*wde_quota_cfg)(struct rtw89_dev *rtwdev,
1046			      const struct rtw89_wde_quota *min_cfg,
1047			      const struct rtw89_wde_quota *max_cfg,
1048			      u16 ext_wde_min_qt_wcpu);
1049	void (*ple_quota_cfg)(struct rtw89_dev *rtwdev,
1050			      const struct rtw89_ple_quota *min_cfg,
1051			      const struct rtw89_ple_quota *max_cfg);
1052	int (*set_cpuio)(struct rtw89_dev *rtwdev,
1053			 struct rtw89_cpuio_ctrl *ctrl_para, bool wd);
1054	int (*dle_quota_change)(struct rtw89_dev *rtwdev, bool band1_en);
1055
1056	void (*disable_cpu)(struct rtw89_dev *rtwdev);
1057	int (*fwdl_enable_wcpu)(struct rtw89_dev *rtwdev, u8 boot_reason,
1058				bool dlfw, bool include_bb);
1059	u8 (*fwdl_get_status)(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);
1060	int (*fwdl_check_path_ready)(struct rtw89_dev *rtwdev, bool h2c_or_fwdl);
1061	void (*fwdl_secure_idmem_share_mode)(struct rtw89_dev *rtwdev, u8 mode);
1062	int (*parse_efuse_map)(struct rtw89_dev *rtwdev);
1063	int (*parse_phycap_map)(struct rtw89_dev *rtwdev);
1064	int (*cnv_efuse_state)(struct rtw89_dev *rtwdev, bool idle);
1065	int (*efuse_read_fw_secure)(struct rtw89_dev *rtwdev);
1066
1067	int (*cfg_plt)(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt);
1068	u16 (*get_plt_cnt)(struct rtw89_dev *rtwdev, u8 band);
1069
1070	bool (*get_txpwr_cr)(struct rtw89_dev *rtwdev,
1071			     enum rtw89_phy_idx phy_idx,
1072			     u32 reg_base, u32 *cr);
1073
1074	int (*write_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask);
1075	int (*read_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 *val);
1076
1077	void (*dump_qta_lost)(struct rtw89_dev *rtwdev);
1078	void (*dump_err_status)(struct rtw89_dev *rtwdev,
1079				enum mac_ax_err_info err);
1080
1081	bool (*is_txq_empty)(struct rtw89_dev *rtwdev);
1082
1083	int (*prep_chan_list)(struct rtw89_dev *rtwdev,
1084			      struct rtw89_vif_link *rtwvif_link);
1085	void (*free_chan_list)(struct rtw89_dev *rtwdev);
1086	int (*add_chan_list)(struct rtw89_dev *rtwdev,
1087			     struct rtw89_vif_link *rtwvif_link);
1088	int (*add_chan_list_pno)(struct rtw89_dev *rtwdev,
1089				 struct rtw89_vif_link *rtwvif_link);
1090	int (*scan_offload)(struct rtw89_dev *rtwdev,
1091			    struct rtw89_scan_option *option,
1092			    struct rtw89_vif_link *rtwvif_link,
1093			    bool wowlan);
1094
1095	int (*wow_config_mac)(struct rtw89_dev *rtwdev, bool enable_wow);
1096};
1097
1098extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax;
1099extern const struct rtw89_mac_gen_def rtw89_mac_gen_be;
1100
1101static inline
1102u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band)
1103{
1104	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1105
1106	return band == 0 ? reg_base : (reg_base + mac->band1_offset);
1107}
1108
1109static inline
1110u32 rtw89_mac_reg_by_port(struct rtw89_dev *rtwdev, u32 base, u8 port, u8 mac_idx)
1111{
1112	return rtw89_mac_reg_by_idx(rtwdev, base + port * 0x40, mac_idx);
1113}
1114
1115static inline u32
1116rtw89_read32_port(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, u32 base)
1117{
1118	u32 reg;
1119
1120	reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1121				    rtwvif_link->mac_idx);
1122	return rtw89_read32(rtwdev, reg);
1123}
1124
1125static inline u32
1126rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1127		       u32 base, u32 mask)
1128{
1129	u32 reg;
1130
1131	reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1132				    rtwvif_link->mac_idx);
1133	return rtw89_read32_mask(rtwdev, reg, mask);
1134}
1135
1136static inline void
1137rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, u32 base,
1138		   u32 data)
1139{
1140	u32 reg;
1141
1142	reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1143				    rtwvif_link->mac_idx);
1144	rtw89_write32(rtwdev, reg, data);
1145}
1146
1147static inline void
1148rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1149			u32 base, u32 mask, u32 data)
1150{
1151	u32 reg;
1152
1153	reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1154				    rtwvif_link->mac_idx);
1155	rtw89_write32_mask(rtwdev, reg, mask, data);
1156}
1157
1158static inline void
1159rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1160			u32 base, u32 mask, u16 data)
1161{
1162	u32 reg;
1163
1164	reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1165				    rtwvif_link->mac_idx);
1166	rtw89_write16_mask(rtwdev, reg, mask, data);
1167}
1168
1169static inline void
1170rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1171		       u32 base, u32 bit)
1172{
1173	u32 reg;
1174
1175	reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1176				    rtwvif_link->mac_idx);
1177	rtw89_write32_clr(rtwdev, reg, bit);
1178}
1179
1180static inline void
1181rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1182		       u32 base, u16 bit)
1183{
1184	u32 reg;
1185
1186	reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1187				    rtwvif_link->mac_idx);
1188	rtw89_write16_clr(rtwdev, reg, bit);
1189}
1190
1191static inline void
1192rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1193		       u32 base, u32 bit)
1194{
1195	u32 reg;
1196
1197	reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1198				    rtwvif_link->mac_idx);
1199	rtw89_write32_set(rtwdev, reg, bit);
1200}
1201
1202int rtw89_mac_pwr_on(struct rtw89_dev *rtwdev);
1203void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev);
1204int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb);
1205int rtw89_mac_preinit(struct rtw89_dev *rtwdev);
1206int rtw89_mac_init(struct rtw89_dev *rtwdev);
1207int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
1208		       enum rtw89_qta_mode ext_mode);
1209int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en);
1210int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
1211			   enum rtw89_qta_mode mode);
1212bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode);
1213static inline
1214int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band,
1215			   enum rtw89_mac_hwmod_sel sel)
1216{
1217	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1218
1219	return mac->check_mac_en(rtwdev, band, sel);
1220}
1221
1222int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val);
1223int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val);
1224int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl);
1225int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev,
1226				struct rtw89_mac_dle_dfi_quota *quota);
1227void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev);
1228int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev,
1229				 struct rtw89_mac_dle_dfi_qempty *qempty);
1230void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev,
1231			     enum mac_ax_err_info err);
1232int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif);
1233int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
1234void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev,
1235			     struct rtw89_vif_link *rtwvif_link,
1236			     struct rtw89_vif_link *rtwvif_src,
1237			     u16 offset_tu);
1238int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1239			   u64 *tsf);
1240void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev,
1241				struct rtw89_vif_link *rtwvif_link, bool en);
1242void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev,
1243					struct rtw89_vif_link *rtwvif_link);
1244void rtw89_mac_set_he_tb(struct rtw89_dev *rtwdev,
1245			 struct rtw89_vif_link *rtwvif_link);
1246void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
1247void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en);
1248int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif);
1249int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev);
1250int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev);
1251
1252static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev)
1253{
1254	const struct rtw89_chip_info *chip = rtwdev->chip;
1255
1256	return chip->ops->enable_bb_rf(rtwdev);
1257}
1258
1259static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev)
1260{
1261	const struct rtw89_chip_info *chip = rtwdev->chip;
1262
1263	return chip->ops->disable_bb_rf(rtwdev);
1264}
1265
1266static inline int rtw89_chip_reset_bb_rf(struct rtw89_dev *rtwdev)
1267{
1268	int ret;
1269
1270	if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
1271		return 0;
1272
1273	ret = rtw89_chip_disable_bb_rf(rtwdev);
1274	if (ret)
1275		return ret;
1276	ret = rtw89_chip_enable_bb_rf(rtwdev);
1277	if (ret)
1278		return ret;
1279
1280	return 0;
1281}
1282
1283u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev);
1284int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err);
1285bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
1286			      u8 class, u8 func);
1287void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
1288			  u32 len, u8 class, u8 func);
1289int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev);
1290int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
1291			  u32 *tx_en, enum rtw89_sch_tx_sel sel);
1292int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
1293			     u32 *tx_en, enum rtw89_sch_tx_sel sel);
1294int rtw89_mac_stop_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx,
1295			     u32 *tx_en, enum rtw89_sch_tx_sel sel);
1296int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
1297int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
1298int rtw89_mac_resume_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
1299void rtw89_mac_cfg_phy_rpt_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable);
1300
1301static inline
1302void rtw89_mac_cfg_phy_rpt(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
1303{
1304	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1305
1306	if (mac->cfg_phy_rpt)
1307		mac->cfg_phy_rpt(rtwdev, mac_idx, enable);
1308}
1309
1310static inline
1311void rtw89_mac_cfg_phy_rpt_bands(struct rtw89_dev *rtwdev, bool enable)
1312{
1313	rtw89_mac_cfg_phy_rpt(rtwdev, RTW89_MAC_0, enable);
1314
1315	if (!rtwdev->dbcc_en)
1316		return;
1317
1318	rtw89_mac_cfg_phy_rpt(rtwdev, RTW89_MAC_1, enable);
1319}
1320
1321static inline
1322int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
1323{
1324	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1325
1326	return mac->cfg_ppdu_status(rtwdev, mac_idx, enable);
1327}
1328
1329static inline
1330int rtw89_mac_cfg_ppdu_status_bands(struct rtw89_dev *rtwdev, bool enable)
1331{
1332	int ret;
1333
1334	ret = rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, enable);
1335	if (ret)
1336		return ret;
1337
1338	if (!rtwdev->dbcc_en)
1339		return 0;
1340
1341	return rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_1, enable);
1342}
1343
1344void rtw89_mac_set_rx_fltr(struct rtw89_dev *rtwdev, u8 mac_idx, u32 rx_fltr);
1345void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev);
1346void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop);
1347int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex);
1348int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev,
1349			   const struct rtw89_mac_ax_coex *coex);
1350int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
1351		      const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1352int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev,
1353			 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1354int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev,
1355			 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1356
1357static inline
1358int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt)
1359{
1360	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1361
1362	return mac->cfg_plt(rtwdev, plt);
1363}
1364
1365static inline
1366u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band)
1367{
1368	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1369
1370	return mac->get_plt_cnt(rtwdev, band);
1371}
1372
1373void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val);
1374u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev);
1375bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev);
1376int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl);
1377int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl);
1378int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl);
1379void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter);
1380void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev);
1381
1382static inline
1383void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev,
1384			struct rtw89_vif_link *rtwvif_link,
1385			struct rtw89_sta_link *rtwsta_link)
1386{
1387	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1388
1389	if (mac->bf_assoc)
1390		mac->bf_assoc(rtwdev, rtwvif_link, rtwsta_link);
1391}
1392
1393void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev,
1394			   struct rtw89_vif_link *rtwvif_link,
1395			   struct rtw89_sta_link *rtwsta_link);
1396void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1397				struct ieee80211_bss_conf *conf);
1398void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev,
1399			       struct rtw89_sta_link *rtwsta_link,
1400			       bool disconnect);
1401void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev);
1402void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en);
1403int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
1404int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
1405int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
1406				 struct rtw89_vif_link *rtwvif_link, bool en);
1407int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause);
1408
1409static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)
1410{
1411	if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
1412		return;
1413
1414	if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags))
1415		return;
1416
1417	_rtw89_mac_bf_monitor_track(rtwdev);
1418}
1419
1420static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev,
1421					 enum rtw89_phy_idx phy_idx,
1422					 u32 reg_base, u32 *val)
1423{
1424	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1425	u32 cr;
1426
1427	if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1428		return -EINVAL;
1429
1430	*val = rtw89_read32(rtwdev, cr);
1431	return 0;
1432}
1433
1434static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev,
1435					  enum rtw89_phy_idx phy_idx,
1436					  u32 reg_base, u32 val)
1437{
1438	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1439	u32 cr;
1440
1441	if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1442		return -EINVAL;
1443
1444	rtw89_write32(rtwdev, cr, val);
1445	return 0;
1446}
1447
1448static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev,
1449					       enum rtw89_phy_idx phy_idx,
1450					       u32 reg_base, u32 mask, u32 val)
1451{
1452	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1453	u32 cr;
1454
1455	if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1456		return -EINVAL;
1457
1458	rtw89_write32_mask(rtwdev, cr, mask, val);
1459	return 0;
1460}
1461
1462static inline void rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev *rtwdev,
1463					     bool enable)
1464{
1465	const struct rtw89_chip_info *chip = rtwdev->chip;
1466
1467	if (enable)
1468		rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1469				  B_AX_HCI_TXDMA_EN);
1470	else
1471		rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1472				  B_AX_HCI_TXDMA_EN);
1473}
1474
1475static inline void rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev *rtwdev,
1476					     bool enable)
1477{
1478	const struct rtw89_chip_info *chip = rtwdev->chip;
1479
1480	if (enable)
1481		rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1482				  B_AX_HCI_RXDMA_EN);
1483	else
1484		rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1485				  B_AX_HCI_RXDMA_EN);
1486}
1487
1488static inline void rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev *rtwdev,
1489					      bool enable)
1490{
1491	const struct rtw89_chip_info *chip = rtwdev->chip;
1492
1493	if (enable)
1494		rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1495				  B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
1496	else
1497		rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1498				  B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
1499}
1500
1501static inline bool rtw89_mac_get_power_state(struct rtw89_dev *rtwdev)
1502{
1503	u32 val;
1504
1505	val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE,
1506				B_AX_WLMAC_PWR_STE_MASK);
1507
1508	return !!val;
1509}
1510
1511int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link,
1512			  bool resume, u32 tx_time);
1513int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link,
1514			  u32 *tx_time);
1515int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev,
1516				 struct rtw89_sta_link *rtwsta_link,
1517				 bool resume, u8 tx_retry);
1518int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
1519				 struct rtw89_sta_link *rtwsta_link, u8 *tx_retry);
1520
1521enum rtw89_mac_xtal_si_offset {
1522	XTAL0 = 0x0,
1523	XTAL3 = 0x3,
1524	XTAL_SI_XTAL_SC_XI = 0x04,
1525#define XTAL_SC_XI_MASK		GENMASK(7, 0)
1526	XTAL_SI_XTAL_SC_XO = 0x05,
1527#define XTAL_SC_XO_MASK		GENMASK(7, 0)
1528	XTAL_SI_XREF_MODE = 0x0B,
1529	XTAL_SI_PWR_CUT = 0x10,
1530#define XTAL_SI_SMALL_PWR_CUT	BIT(0)
1531#define XTAL_SI_BIG_PWR_CUT	BIT(1)
1532	XTAL_SI_XTAL_DRV = 0x15,
1533#define XTAL_SI_DRV_LATCH	BIT(4)
1534	XTAL_SI_XTAL_PLL = 0x16,
1535	XTAL_SI_XTAL_XMD_2 = 0x24,
1536#define XTAL_SI_LDO_LPS		GENMASK(6, 4)
1537	XTAL_SI_XTAL_XMD_4 = 0x26,
1538#define XTAL_SI_LPS_CAP		GENMASK(3, 0)
1539	XTAL_SI_XREF_RF1 = 0x2D,
1540	XTAL_SI_XREF_RF2 = 0x2E,
1541	XTAL_SI_CV = 0x41,
1542#define XTAL_SI_ACV_MASK	GENMASK(3, 0)
1543	XTAL_SI_LOW_ADDR = 0x62,
1544#define XTAL_SI_LOW_ADDR_MASK	GENMASK(7, 0)
1545	XTAL_SI_CTRL = 0x63,
1546#define XTAL_SI_MODE_SEL_MASK	GENMASK(7, 6)
1547#define XTAL_SI_RDY		BIT(5)
1548#define XTAL_SI_HIGH_ADDR_MASK	GENMASK(2, 0)
1549	XTAL_SI_READ_VAL = 0x7A,
1550	XTAL_SI_WL_RFC_S0 = 0x80,
1551#define XTAL_SI_RF00S_EN	GENMASK(2, 0)
1552#define XTAL_SI_RF00		BIT(0)
1553	XTAL_SI_WL_RFC_S1 = 0x81,
1554#define XTAL_SI_RF10S_EN	GENMASK(2, 0)
1555#define XTAL_SI_RF10		BIT(0)
1556	XTAL_SI_ANAPAR_WL = 0x90,
1557#define XTAL_SI_SRAM2RFC	BIT(7)
1558#define XTAL_SI_GND_SHDN_WL	BIT(6)
1559#define XTAL_SI_SHDN_WL		BIT(5)
1560#define XTAL_SI_RFC2RF		BIT(4)
1561#define XTAL_SI_OFF_EI		BIT(3)
1562#define XTAL_SI_OFF_WEI		BIT(2)
1563#define XTAL_SI_PON_EI		BIT(1)
1564#define XTAL_SI_PON_WEI		BIT(0)
1565	XTAL_SI_SRAM_CTRL = 0xA1,
1566#define XTAL_SI_SRAM_DIS	BIT(1)
1567#define FULL_BIT_MASK		GENMASK(7, 0)
1568	XTAL_SI_APBT = 0xD1,
1569	XTAL_SI_PLL = 0xE0,
1570	XTAL_SI_PLL_1 = 0xE1,
1571};
1572
1573static inline
1574int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
1575{
1576	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1577
1578	return mac->write_xtal_si(rtwdev, offset, val, mask);
1579}
1580
1581static inline
1582int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
1583{
1584	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1585
1586	return mac->read_xtal_si(rtwdev, offset, val);
1587}
1588
1589void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1590int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow);
1591int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,
1592					enum rtw89_mac_idx band);
1593void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow);
1594int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
1595			       bool band1_en);
1596int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev,
1597				  enum rtw89_mac_dle_rsvd_qt_type type,
1598				  struct rtw89_mac_dle_rsvd_qt_cfg *cfg);
1599int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable);
1600
1601static inline
1602void rtw89_fwdl_secure_idmem_share_mode(struct rtw89_dev *rtwdev, u8 mode)
1603{
1604	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1605
1606	if (!mac->fwdl_secure_idmem_share_mode)
1607		return;
1608
1609	return mac->fwdl_secure_idmem_share_mode(rtwdev, mode);
1610}
1611
1612static inline
1613int rtw89_mac_scan_offload(struct rtw89_dev *rtwdev,
1614			   struct rtw89_scan_option *option,
1615			   struct rtw89_vif_link *rtwvif_link,
1616			   bool wowlan)
1617{
1618	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1619	int ret;
1620
1621	ret = mac->scan_offload(rtwdev, option, rtwvif_link, wowlan);
1622
1623	if (option->enable) {
1624		/*
1625		 * At this point, new scan request is acknowledged by firmware,
1626		 * so scan events of previous scan request become obsoleted.
1627		 * Purge the queued scan events to prevent interference to
1628		 * current new request.
1629		 */
1630		rtw89_fw_c2h_purge_obsoleted_scan_events(rtwdev);
1631	}
1632
1633	return ret;
1634}
1635
1636static inline
1637void rtw89_tx_rpt_init(struct rtw89_dev *rtwdev,
1638		       struct rtw89_core_tx_request *tx_req)
1639{
1640	struct rtw89_tx_rpt *tx_rpt = &rtwdev->tx_rpt;
1641
1642	if (!rtwdev->hci.tx_rpt_enabled)
1643		return;
1644
1645	tx_req->desc_info.report = true;
1646	/* firmware maintains a 4-bit sequence number */
1647	tx_req->desc_info.sn = atomic_inc_return(&tx_rpt->sn) &
1648			       RTW89_MAX_TX_RPTS_MASK;
1649	tx_req->desc_info.tx_cnt_lmt_en = true;
1650	tx_req->desc_info.tx_cnt_lmt = 8;
1651}
1652
1653static inline
1654bool rtw89_is_tx_rpt_skb(struct rtw89_dev *rtwdev, struct sk_buff *skb)
1655{
1656	struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb);
1657	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1658
1659	return rtw89_core_is_tx_wait(rtwdev, skb_data) ||
1660	       (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS);
1661}
1662
1663static inline
1664void rtw89_tx_rpt_tx_status(struct rtw89_dev *rtwdev, struct sk_buff *skb,
1665			    u8 tx_status)
1666{
1667	struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb);
1668	struct ieee80211_tx_info *info;
1669
1670	if (rtw89_core_tx_wait_complete(rtwdev, skb_data, tx_status))
1671		return;
1672
1673	info = IEEE80211_SKB_CB(skb);
1674	ieee80211_tx_info_clear_status(info);
1675
1676	if (tx_status == RTW89_TX_DONE)
1677		info->flags |= IEEE80211_TX_STAT_ACK;
1678	else
1679		info->flags &= ~IEEE80211_TX_STAT_ACK;
1680
1681	ieee80211_tx_status_irqsafe(rtwdev->hw, skb);
1682}
1683
1684static inline
1685void rtw89_tx_rpt_skb_add(struct rtw89_dev *rtwdev, struct sk_buff *skb)
1686{
1687	struct rtw89_tx_rpt *tx_rpt = &rtwdev->tx_rpt;
1688	struct rtw89_tx_skb_data *skb_data;
1689	u8 idx;
1690
1691	skb_data = RTW89_TX_SKB_CB(skb);
1692	idx = skb_data->tx_rpt_sn;
1693
1694	scoped_guard(spinlock_irqsave, &tx_rpt->skb_lock) {
1695		/* if skb having the similar seq number is still in the queue,
1696		 * this means the queue is overflowed - it isn't normal and
1697		 * should indicate firmware doesn't provide TX reports in time;
1698		 * report the old skb as dropped, we can't do much more here
1699		 */
1700		if (tx_rpt->skbs[idx])
1701			rtw89_tx_rpt_tx_status(rtwdev, tx_rpt->skbs[idx],
1702					       RTW89_TX_MACID_DROP);
1703		tx_rpt->skbs[idx] = skb;
1704	}
1705}
1706
1707static inline
1708void rtw89_tx_rpt_skbs_purge(struct rtw89_dev *rtwdev)
1709{
1710	struct rtw89_tx_rpt *tx_rpt = &rtwdev->tx_rpt;
1711	struct sk_buff *skbs[RTW89_MAX_TX_RPTS];
1712
1713	scoped_guard(spinlock_irqsave, &tx_rpt->skb_lock) {
1714		memcpy(skbs, tx_rpt->skbs, sizeof(tx_rpt->skbs));
1715		memset(tx_rpt->skbs, 0, sizeof(tx_rpt->skbs));
1716	}
1717
1718	for (int i = 0; i < ARRAY_SIZE(skbs); i++)
1719		if (skbs[i])
1720			rtw89_tx_rpt_tx_status(rtwdev, skbs[i],
1721					       RTW89_TX_MACID_DROP);
1722}
1723#endif