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fw.h
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linux-6.19.14/drivers/net/wireless/realtek/rtw89/fw.h
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2/* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5#ifndef __RTW89_FW_H__ 6#define __RTW89_FW_H__ 7 8#include "core.h" 9 10enum rtw89_fw_dl_status { 11 RTW89_FWDL_INITIAL_STATE = 0, 12 RTW89_FWDL_FWDL_ONGOING = 1, 13 RTW89_FWDL_CHECKSUM_FAIL = 2, 14 RTW89_FWDL_SECURITY_FAIL = 3, 15 RTW89_FWDL_CV_NOT_MATCH = 4, 16 RTW89_FWDL_RSVD0 = 5, 17 RTW89_FWDL_WCPU_FWDL_RDY = 6, 18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7 19}; 20 21struct rtw89_c2hreg_hdr { 22 u32 w0; 23}; 24 25#define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0) 26#define RTW89_C2HREG_HDR_ACK BIT(7) 27#define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8) 28#define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12) 29 30struct rtw89_c2hreg_phycap { 31 u32 w0; 32 u32 w1; 33 u32 w2; 34 u32 w3; 35} __packed; 36 37#define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0) 38#define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7) 39#define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8) 40#define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12) 41#define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16) 42#define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24) 43#define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0) 44#define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8) 45#define RTW89_C2HREG_PHYCAP_W1_PROT_11N 1 46#define RTW89_C2HREG_PHYCAP_W1_PROT_11AC 2 47#define RTW89_C2HREG_PHYCAP_W1_PROT_11AX 3 48#define RTW89_C2HREG_PHYCAP_W1_PROT_11BE 4 49#define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16) 50#define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24) 51#define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0) 52#define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8) 53#define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16) 54#define RTW89_C2HREG_PHYCAP_W3_BAND_SEL GENMASK(31, 24) 55 56#define RTW89_C2HREG_PHYCAP_P1_W0_B1_RX_NSS GENMASK(23, 16) 57#define RTW89_C2HREG_PHYCAP_P1_W0_B1_BW GENMASK(31, 24) 58#define RTW89_C2HREG_PHYCAP_P1_W1_B1_TX_NSS GENMASK(7, 0) 59#define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_TX_NUM GENMASK(15, 8) 60#define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_RX_NUM GENMASK(23, 16) 61#define RTW89_C2HREG_PHYCAP_P1_W1_B1_BAND_SEL GENMASK(31, 24) 62#define RTW89_C2HREG_PHYCAP_P1_W2_QAM GENMASK(7, 0) 63#define RTW89_C2HREG_PHYCAP_P1_W2_QAM_256 0x1 64#define RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024 0x2 65#define RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096 0x3 66#define RTW89_C2HREG_PHYCAP_P1_W2_B1_QAM GENMASK(15, 8) 67 68#define RTW89_C2HREG_AOAC_RPT_1_W0_KEY_IDX GENMASK(23, 16) 69#define RTW89_C2HREG_AOAC_RPT_1_W1_IV_0 GENMASK(7, 0) 70#define RTW89_C2HREG_AOAC_RPT_1_W1_IV_1 GENMASK(15, 8) 71#define RTW89_C2HREG_AOAC_RPT_1_W1_IV_2 GENMASK(23, 16) 72#define RTW89_C2HREG_AOAC_RPT_1_W1_IV_3 GENMASK(31, 24) 73#define RTW89_C2HREG_AOAC_RPT_1_W2_IV_4 GENMASK(7, 0) 74#define RTW89_C2HREG_AOAC_RPT_1_W2_IV_5 GENMASK(15, 8) 75#define RTW89_C2HREG_AOAC_RPT_1_W2_IV_6 GENMASK(23, 16) 76#define RTW89_C2HREG_AOAC_RPT_1_W2_IV_7 GENMASK(31, 24) 77#define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_0 GENMASK(7, 0) 78#define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_1 GENMASK(15, 8) 79#define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_2 GENMASK(23, 16) 80#define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_3 GENMASK(31, 24) 81#define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_4 GENMASK(23, 16) 82#define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_5 GENMASK(31, 24) 83#define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_6 GENMASK(7, 0) 84#define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_7 GENMASK(15, 8) 85#define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_0 GENMASK(23, 16) 86#define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_1 GENMASK(31, 24) 87#define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_2 GENMASK(7, 0) 88#define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_3 GENMASK(15, 8) 89#define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_4 GENMASK(23, 16) 90#define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_5 GENMASK(31, 24) 91#define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_6 GENMASK(7, 0) 92#define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_7 GENMASK(15, 8) 93 94#define RTW89_C2HREG_PS_LEAVE_ACK_RET GENMASK(7, 0) 95#define RTW89_C2HREG_PS_LEAVE_ACK_MACID GENMASK(31, 16) 96 97struct rtw89_h2creg_hdr { 98 u32 w0; 99}; 100 101#define RTW89_H2CREG_HDR_FUNC_MASK GENMASK(6, 0) 102#define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8) 103 104struct rtw89_h2creg_sch_tx_en { 105 u32 w0; 106 u32 w1; 107} __packed; 108 109#define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16) 110#define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0) 111#define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16) 112 113#define RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN GENMASK(23, 16) 114 115#define RTW89_H2CREG_GET_FEATURE_PART_NUM GENMASK(23, 16) 116 117#define RTW89_H2CREG_MAX 4 118#define RTW89_C2HREG_MAX 4 119#define RTW89_C2HREG_HDR_LEN 2 120#define RTW89_H2CREG_HDR_LEN 2 121#define RTW89_C2H_TIMEOUT 1000000 122#define RTW89_C2H_TIMEOUT_USB 4000 123 124struct rtw89_mac_c2h_info { 125 u8 id; 126 u8 content_len; 127 union { 128 u32 c2hreg[RTW89_C2HREG_MAX]; 129 struct rtw89_c2hreg_hdr hdr; 130 struct rtw89_c2hreg_phycap phycap; 131 } u; 132}; 133 134struct rtw89_mac_h2c_info { 135 u8 id; 136 u8 content_len; 137 union { 138 u32 h2creg[RTW89_H2CREG_MAX]; 139 struct rtw89_h2creg_hdr hdr; 140 struct rtw89_h2creg_sch_tx_en sch_tx_en; 141 } u; 142}; 143 144enum rtw89_mac_h2c_type { 145 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0, 146 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD, 147 RTW89_FWCMD_H2CREG_FUNC_FWERR, 148 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE, 149 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM, 150 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN, 151 RTW89_FWCMD_H2CREG_FUNC_WOW_TRX_STOP, 152 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_1, 153 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_2, 154 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_3_REQ, 155 RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL, 156}; 157 158enum rtw89_mac_c2h_type { 159 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0, 160 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT, 161 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG, 162 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP, 163 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT, 164 RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK = 0xA, 165 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP_PART1 = 0xC, 166 RTW89_FWCMD_C2HREG_FUNC_PS_LEAVE_ACK = 0xD, 167 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF, 168}; 169 170enum rtw89_fw_c2h_category { 171 RTW89_C2H_CAT_TEST, 172 RTW89_C2H_CAT_MAC, 173 RTW89_C2H_CAT_OUTSRC, 174}; 175 176enum rtw89_fw_log_level { 177 RTW89_FW_LOG_LEVEL_OFF, 178 RTW89_FW_LOG_LEVEL_CRT, 179 RTW89_FW_LOG_LEVEL_SER, 180 RTW89_FW_LOG_LEVEL_WARN, 181 RTW89_FW_LOG_LEVEL_LOUD, 182 RTW89_FW_LOG_LEVEL_TR, 183}; 184 185enum rtw89_fw_log_path { 186 RTW89_FW_LOG_LEVEL_UART, 187 RTW89_FW_LOG_LEVEL_C2H, 188 RTW89_FW_LOG_LEVEL_SNI, 189}; 190 191enum rtw89_fw_log_comp { 192 RTW89_FW_LOG_COMP_VER, 193 RTW89_FW_LOG_COMP_INIT, 194 RTW89_FW_LOG_COMP_TASK, 195 RTW89_FW_LOG_COMP_CNS, 196 RTW89_FW_LOG_COMP_H2C, 197 RTW89_FW_LOG_COMP_C2H, 198 RTW89_FW_LOG_COMP_TX, 199 RTW89_FW_LOG_COMP_RX, 200 RTW89_FW_LOG_COMP_IPSEC, 201 RTW89_FW_LOG_COMP_TIMER, 202 RTW89_FW_LOG_COMP_DBGPKT, 203 RTW89_FW_LOG_COMP_PS, 204 RTW89_FW_LOG_COMP_ERROR, 205 RTW89_FW_LOG_COMP_WOWLAN, 206 RTW89_FW_LOG_COMP_SECURE_BOOT, 207 RTW89_FW_LOG_COMP_BTC, 208 RTW89_FW_LOG_COMP_BB, 209 RTW89_FW_LOG_COMP_TWT, 210 RTW89_FW_LOG_COMP_RF, 211 RTW89_FW_LOG_COMP_MCC = 20, 212 RTW89_FW_LOG_COMP_MLO = 26, 213 RTW89_FW_LOG_COMP_SCAN = 28, 214}; 215 216enum rtw89_pkt_offload_op { 217 RTW89_PKT_OFLD_OP_ADD, 218 RTW89_PKT_OFLD_OP_DEL, 219 RTW89_PKT_OFLD_OP_READ, 220 221 NUM_OF_RTW89_PKT_OFFLOAD_OP, 222}; 223 224#define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) \ 225 ((pkt_id) * NUM_OF_RTW89_PKT_OFFLOAD_OP + (pkt_op)) 226 227enum rtw89_scanofld_notify_reason { 228 RTW89_SCAN_DWELL_NOTIFY, 229 RTW89_SCAN_PRE_TX_NOTIFY, 230 RTW89_SCAN_POST_TX_NOTIFY, 231 RTW89_SCAN_ENTER_CH_NOTIFY, 232 RTW89_SCAN_LEAVE_CH_NOTIFY, 233 RTW89_SCAN_END_SCAN_NOTIFY, 234 RTW89_SCAN_REPORT_NOTIFY, 235 RTW89_SCAN_CHKPT_NOTIFY, 236 RTW89_SCAN_ENTER_OP_NOTIFY, 237 RTW89_SCAN_LEAVE_OP_NOTIFY, 238}; 239 240enum rtw89_scanofld_status { 241 RTW89_SCAN_STATUS_NOTIFY, 242 RTW89_SCAN_STATUS_SUCCESS, 243 RTW89_SCAN_STATUS_FAIL, 244}; 245 246enum rtw89_chan_type { 247 RTW89_CHAN_OPERATE = 0, 248 RTW89_CHAN_ACTIVE, 249 RTW89_CHAN_DFS, 250 RTW89_CHAN_EXTRA_OP, 251}; 252 253enum rtw89_p2pps_action { 254 RTW89_P2P_ACT_INIT = 0, 255 RTW89_P2P_ACT_UPDATE = 1, 256 RTW89_P2P_ACT_REMOVE = 2, 257 RTW89_P2P_ACT_TERMINATE = 3, 258}; 259 260#define RTW89_DEFAULT_CQM_HYST 4 261#define RTW89_DEFAULT_CQM_THOLD -70 262 263enum rtw89_bcn_fltr_offload_mode { 264 RTW89_BCN_FLTR_OFFLOAD_MODE_0 = 0, 265 RTW89_BCN_FLTR_OFFLOAD_MODE_1, 266 RTW89_BCN_FLTR_OFFLOAD_MODE_2, 267 RTW89_BCN_FLTR_OFFLOAD_MODE_3, 268 269 RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT = RTW89_BCN_FLTR_OFFLOAD_MODE_0, 270}; 271 272enum rtw89_bcn_fltr_type { 273 RTW89_BCN_FLTR_BEACON_LOSS, 274 RTW89_BCN_FLTR_RSSI, 275 RTW89_BCN_FLTR_NOTIFY, 276}; 277 278enum rtw89_bcn_fltr_rssi_event { 279 RTW89_BCN_FLTR_RSSI_NOT_CHANGED, 280 RTW89_BCN_FLTR_RSSI_HIGH, 281 RTW89_BCN_FLTR_RSSI_LOW, 282}; 283 284#define FWDL_SECTION_MAX_NUM 10 285#define FWDL_SECTION_CHKSUM_LEN 8 286#define FWDL_SECTION_PER_PKT_LEN 2020 287 288struct rtw89_fw_hdr_section_info { 289 u8 redl; 290 const u8 *addr; 291 u32 len; 292 u32 len_override; 293 u32 dladdr; 294 u32 mssc; 295 u8 type; 296 bool ignore; 297 const u8 *key_addr; 298 u32 key_len; 299 u32 key_idx; 300}; 301 302struct rtw89_fw_bin_info { 303 u8 section_num; 304 u32 part_size; 305 u32 hdr_len; 306 bool dynamic_hdr_en; 307 u32 dynamic_hdr_len; 308 u8 idmem_share_mode; 309 bool dsp_checksum; 310 bool secure_section_exist; 311 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM]; 312}; 313 314struct rtw89_fw_macid_pause_grp { 315 __le32 pause_grp[4]; 316 __le32 mask_grp[4]; 317} __packed; 318 319struct rtw89_fw_macid_pause_sleep_grp { 320 struct { 321 __le32 pause_grp[4]; 322 __le32 pause_mask_grp[4]; 323 __le32 sleep_grp[4]; 324 __le32 sleep_mask_grp[4]; 325 } __packed n[4]; 326} __packed; 327 328#define RTW89_H2C_MAX_SIZE 2048 329#define RTW89_CHANNEL_TIME 45 330#define RTW89_CHANNEL_TIME_6G 20 331#define RTW89_CHANNEL_TIME_EXTRA_OP 30 332#define RTW89_DFS_CHAN_TIME 105 333#define RTW89_OFF_CHAN_TIME 100 334#define RTW89_P2P_CHAN_TIME 105 335#define RTW89_DWELL_TIME 20 336#define RTW89_DWELL_TIME_6G 10 337#define RTW89_SCAN_WIDTH 0 338#define RTW89_SCANOFLD_MAX_SSID 8 339#define RTW89_SCANOFLD_MAX_IE_LEN 512 340#define RTW89_SCANOFLD_PKT_NONE 0xFF 341#define RTW89_SCANOFLD_DEBUG_MASK 0x1F 342#define RTW89_CHAN_INVALID 0xFF 343#define RTW89_MAC_CHINFO_SIZE 28 344#define RTW89_MAC_CHINFO_SIZE_BE 32 345#define RTW89_SCAN_LIST_GUARD 4 346#define RTW89_SCAN_LIST_LIMIT(size) \ 347 ((RTW89_H2C_MAX_SIZE / (size)) - RTW89_SCAN_LIST_GUARD) 348#define RTW89_SCAN_LIST_LIMIT_AX RTW89_SCAN_LIST_LIMIT(RTW89_MAC_CHINFO_SIZE) 349#define RTW89_SCAN_LIST_LIMIT_BE RTW89_SCAN_LIST_LIMIT(RTW89_MAC_CHINFO_SIZE_BE) 350 351#define RTW89_BCN_LOSS_CNT 60 352 353struct rtw89_mac_chinfo_ax { 354 u8 period; 355 u8 dwell_time; 356 u8 central_ch; 357 u8 pri_ch; 358 u8 bw:3; 359 u8 notify_action:5; 360 u8 num_pkt:4; 361 u8 tx_pkt:1; 362 u8 pause_data:1; 363 u8 ch_band:2; 364 u8 probe_id; 365 u8 dfs_ch:1; 366 u8 tx_null:1; 367 u8 rand_seq_num:1; 368 u8 cfg_tx_pwr:1; 369 u8 macid_tx: 1; 370 u8 rsvd0: 3; 371 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID]; 372 u16 tx_pwr_idx; 373 u8 rsvd1; 374 struct list_head list; 375 bool is_psc; 376}; 377 378struct rtw89_mac_chinfo_be { 379 u8 period; 380 u8 dwell_time; 381 u8 central_ch; 382 u8 pri_ch; 383 u8 bw:3; 384 u8 ch_band:2; 385 u8 dfs_ch:1; 386 u8 pause_data:1; 387 u8 tx_null:1; 388 u8 rand_seq_num:1; 389 u8 notify_action:5; 390 u8 probe_id; 391 u8 leave_crit; 392 u8 chkpt_timer; 393 u8 leave_time; 394 u8 leave_th; 395 u16 tx_pkt_ctrl; 396 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID]; 397 u8 sw_def; 398 u16 fw_probe0_ssids; 399 u16 fw_probe0_shortssids; 400 u16 fw_probe0_bssids; 401 402 struct list_head list; 403 bool is_psc; 404}; 405 406struct rtw89_pktofld_info { 407 struct list_head list; 408 u8 id; 409 bool wildcard_6ghz; 410 411 /* Below fields are for WiFi 6 chips 6 GHz RNR use only */ 412 u8 ssid[IEEE80211_MAX_SSID_LEN]; 413 u8 ssid_len; 414 u8 bssid[ETH_ALEN]; 415 u16 channel_6ghz; 416 bool cancel; 417}; 418 419struct rtw89_h2c_ra { 420 __le32 w0; 421 __le32 w1; 422 __le32 w2; 423 __le32 w3; 424} __packed; 425 426#define RTW89_H2C_RA_W0_IS_DIS BIT(0) 427#define RTW89_H2C_RA_W0_MODE GENMASK(5, 1) 428#define RTW89_H2C_RA_W0_BW_CAP GENMASK(7, 6) 429#define RTW89_H2C_RA_W0_MACID GENMASK(15, 8) 430#define RTW89_H2C_RA_W0_DCM BIT(16) 431#define RTW89_H2C_RA_W0_ER BIT(17) 432#define RTW89_H2C_RA_W0_INIT_RATE_LV GENMASK(19, 18) 433#define RTW89_H2C_RA_W0_UPD_ALL BIT(20) 434#define RTW89_H2C_RA_W0_SGI BIT(21) 435#define RTW89_H2C_RA_W0_LDPC BIT(22) 436#define RTW89_H2C_RA_W0_STBC BIT(23) 437#define RTW89_H2C_RA_W0_SS_NUM GENMASK(26, 24) 438#define RTW89_H2C_RA_W0_GILTF GENMASK(29, 27) 439#define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK BIT(30) 440#define RTW89_H2C_RA_W0_UPD_MASK BIT(31) 441#define RTW89_H2C_RA_W1_RAMASK_LO32 GENMASK(31, 0) 442#define RTW89_H2C_RA_W2_RAMASK_HI32 GENMASK(30, 0) 443#define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31) 444#define RTW89_H2C_RA_W3_BAND_NUM GENMASK(7, 0) 445#define RTW89_H2C_RA_W3_RA_CSI_RATE_EN BIT(8) 446#define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN BIT(9) 447#define RTW89_H2C_RA_W3_CR_TBL_SEL BIT(10) 448#define RTW89_H2C_RA_W3_FIX_GILTF_EN BIT(11) 449#define RTW89_H2C_RA_W3_FIX_GILTF GENMASK(14, 12) 450#define RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX GENMASK(23, 16) 451#define RTW89_H2C_RA_W3_FIXED_CSI_MODE GENMASK(25, 24) 452#define RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF GENMASK(28, 26) 453#define RTW89_H2C_RA_W3_FIXED_CSI_BW GENMASK(31, 29) 454#define RTW89_H2C_RA_V1_W3_PARTIAL_BW_SU_ER BIT(15) 455#define RTW89_H2C_RA_V1_W3_FIXED_CSI_RATE_L GENMASK(23, 16) 456#define RTW89_H2C_RA_V1_W3_IS_NOISY BIT(24) 457#define RTW89_H2C_RA_V1_W3_PSRA_EN BIT(25) 458#define RTW89_H2C_RA_V1_W3_MACID_MSB GENMASK(28, 27) 459#define RTW89_H2C_RA_V1_W3_BAND GENMASK(30, 29) 460#define RTW89_H2C_RA_V1_W3_NEW_DBGREG BIT(31) 461 462struct rtw89_h2c_ra_v1 { 463 struct rtw89_h2c_ra v0; 464 __le32 w4; 465 __le32 w5; 466} __packed; 467 468#define RTW89_H2C_RA_V1_W4_MODE_EHT GENMASK(6, 0) 469#define RTW89_H2C_RA_V1_W4_BW_EHT GENMASK(10, 8) 470#define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16) 471#define RTW89_H2C_RA_V1_W5_RAMASK_UHH16 GENMASK(15, 0) 472 473static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val) 474{ 475 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)); 476} 477 478static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val) 479{ 480 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); 481} 482 483static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val) 484{ 485 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)); 486} 487 488static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val) 489{ 490 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0)); 491} 492 493static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val) 494{ 495 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4)); 496} 497 498static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val) 499{ 500 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5)); 501} 502 503static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val) 504{ 505 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0)); 506} 507 508static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val) 509{ 510 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0)); 511} 512 513static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val) 514{ 515 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0)); 516} 517 518static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val) 519{ 520 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0)); 521} 522 523static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val) 524{ 525 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0)); 526} 527 528static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val) 529{ 530 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3)); 531} 532 533static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val) 534{ 535 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4)); 536} 537 538static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val) 539{ 540 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5)); 541} 542 543static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val) 544{ 545 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0)); 546} 547#define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16) 548#define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12) 549#define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8) 550#define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0) 551 552#define FWDL_SECURITY_SECTION_TYPE 9 553#define FWDL_SECURITY_SIGLEN 512 554#define FWDL_SECURITY_CHKSUM_LEN 8 555 556struct rtw89_fw_dynhdr_sec { 557 __le32 w0; 558 u8 content[]; 559} __packed; 560 561struct rtw89_fw_dynhdr_hdr { 562 __le32 hdr_len; 563 __le32 setcion_count; 564 /* struct rtw89_fw_dynhdr_sec (nested flexible structures) */ 565} __packed; 566 567struct rtw89_fw_hdr_section { 568 __le32 w0; 569 __le32 w1; 570 __le32 w2; 571 __le32 w3; 572} __packed; 573 574#define FWSECTION_HDR_W0_DL_ADDR GENMASK(31, 0) 575#define FWSECTION_HDR_W1_METADATA GENMASK(31, 24) 576#define FWSECTION_HDR_W1_SECTIONTYPE GENMASK(27, 24) 577#define FWSECTION_HDR_W1_SEC_SIZE GENMASK(23, 0) 578#define FWSECTION_HDR_W1_CHECKSUM BIT(28) 579#define FWSECTION_HDR_W1_REDL BIT(29) 580#define FWSECTION_HDR_W2_MSSC GENMASK(31, 0) 581 582struct rtw89_fw_hdr { 583 __le32 w0; 584 __le32 w1; 585 __le32 w2; 586 __le32 w3; 587 __le32 w4; 588 __le32 w5; 589 __le32 w6; 590 __le32 w7; 591 struct rtw89_fw_hdr_section sections[]; 592 /* struct rtw89_fw_dynhdr_hdr (optional) */ 593} __packed; 594 595#define FW_HDR_W1_MAJOR_VERSION GENMASK(7, 0) 596#define FW_HDR_W1_MINOR_VERSION GENMASK(15, 8) 597#define FW_HDR_W1_SUBVERSION GENMASK(23, 16) 598#define FW_HDR_W1_SUBINDEX GENMASK(31, 24) 599#define FW_HDR_W2_COMMITID GENMASK(31, 0) 600#define FW_HDR_W3_LEN GENMASK(23, 16) 601#define FW_HDR_W3_HDR_VER GENMASK(31, 24) 602#define FW_HDR_W4_MONTH GENMASK(7, 0) 603#define FW_HDR_W4_DATE GENMASK(15, 8) 604#define FW_HDR_W4_HOUR GENMASK(23, 16) 605#define FW_HDR_W4_MIN GENMASK(31, 24) 606#define FW_HDR_W5_YEAR GENMASK(31, 0) 607#define FW_HDR_W6_SEC_NUM GENMASK(15, 8) 608#define FW_HDR_W7_PART_SIZE GENMASK(15, 0) 609#define FW_HDR_W7_DYN_HDR BIT(16) 610#define FW_HDR_W7_IDMEM_SHARE_MODE GENMASK(21, 18) 611#define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24) 612 613struct rtw89_fw_hdr_section_v1 { 614 __le32 w0; 615 __le32 w1; 616 __le32 w2; 617 __le32 w3; 618} __packed; 619 620#define FWSECTION_HDR_V1_W0_DL_ADDR GENMASK(31, 0) 621#define FWSECTION_HDR_V1_W1_METADATA GENMASK(31, 24) 622#define FWSECTION_HDR_V1_W1_SECTIONTYPE GENMASK(27, 24) 623#define FWSECTION_HDR_V1_W1_SEC_SIZE GENMASK(23, 0) 624#define FWSECTION_HDR_V1_W1_CHECKSUM BIT(28) 625#define FWSECTION_HDR_V1_W1_REDL BIT(29) 626#define FWSECTION_HDR_V1_W2_MSSC GENMASK(7, 0) 627#define FORMATTED_MSSC 0xFF 628#define FORMATTED_MSSC_MASK GENMASK(7, 0) 629#define FWSECTION_HDR_V1_W2_BBMCU_IDX GENMASK(27, 24) 630 631struct rtw89_fw_hdr_v1 { 632 __le32 w0; 633 __le32 w1; 634 __le32 w2; 635 __le32 w3; 636 __le32 w4; 637 __le32 w5; 638 __le32 w6; 639 __le32 w7; 640 __le32 w8; 641 __le32 w9; 642 __le32 w10; 643 __le32 w11; 644 struct rtw89_fw_hdr_section_v1 sections[]; 645} __packed; 646 647#define FW_HDR_V1_W1_MAJOR_VERSION GENMASK(7, 0) 648#define FW_HDR_V1_W1_MINOR_VERSION GENMASK(15, 8) 649#define FW_HDR_V1_W1_SUBVERSION GENMASK(23, 16) 650#define FW_HDR_V1_W1_SUBINDEX GENMASK(31, 24) 651#define FW_HDR_V1_W2_COMMITID GENMASK(31, 0) 652#define FW_HDR_V1_W3_CMD_VERSERION GENMASK(23, 16) 653#define FW_HDR_V1_W3_HDR_VER GENMASK(31, 24) 654#define FW_HDR_V1_W4_MONTH GENMASK(7, 0) 655#define FW_HDR_V1_W4_DATE GENMASK(15, 8) 656#define FW_HDR_V1_W4_HOUR GENMASK(23, 16) 657#define FW_HDR_V1_W4_MIN GENMASK(31, 24) 658#define FW_HDR_V1_W5_YEAR GENMASK(15, 0) 659#define FW_HDR_V1_W5_HDR_SIZE GENMASK(31, 16) 660#define FW_HDR_V1_W6_SEC_NUM GENMASK(15, 8) 661#define FW_HDR_V1_W6_DSP_CHKSUM BIT(24) 662#define FW_HDR_V1_W7_PART_SIZE GENMASK(15, 0) 663#define FW_HDR_V1_W7_DYN_HDR BIT(16) 664#define FW_HDR_V1_W7_IDMEM_SHARE_MODE GENMASK(21, 18) 665 666enum rtw89_fw_mss_pool_rmp_tbl_type { 667 MSS_POOL_RMP_TBL_BITMASK = 0x0, 668 MSS_POOL_RMP_TBL_RECORD = 0x1, 669}; 670 671#define FWDL_MSS_POOL_DEFKEYSETS_SIZE 8 672 673struct rtw89_fw_mss_pool_hdr { 674 u8 signature[8]; /* equal to mss_signature[] */ 675 __le32 rmp_tbl_offset; 676 __le32 key_raw_offset; 677 u8 defen; 678 u8 rsvd[3]; 679 u8 rmpfmt; /* enum rtw89_fw_mss_pool_rmp_tbl_type */ 680 u8 mssdev_max; 681 __le16 keypair_num; 682 __le16 msscust_max; 683 __le16 msskey_num_max; 684 __le32 rsvd3; 685 u8 rmp_tbl[]; 686} __packed; 687 688union rtw89_fw_section_mssc_content { 689 struct { 690 u8 pad[0x20]; 691 u8 bit_in_chip_list; 692 u8 ver; 693 } __packed blacklist; 694 struct { 695 u8 pad[58]; 696 __le32 v; 697 } __packed sb_sel_ver; 698 struct { 699 u8 pad[60]; 700 __le16 v; 701 } __packed key_sign_len; 702} __packed; 703 704struct rtw89_fw_blacklist { 705 u8 ver; 706 u8 list[32]; 707}; 708 709extern const struct rtw89_fw_blacklist rtw89_fw_blacklist_default; 710 711static inline void SET_CTRL_INFO_MACID(void *table, u32 val) 712{ 713 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)); 714} 715 716static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val) 717{ 718 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); 719} 720#define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0) 721static inline void SET_CMC_TBL_DATARATE(void *table, u32 val) 722{ 723 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0)); 724 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE, 725 GENMASK(8, 0)); 726} 727#define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0) 728static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val) 729{ 730 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9)); 731 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP, 732 BIT(9)); 733} 734#define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0) 735static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val) 736{ 737 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10)); 738 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW, 739 GENMASK(11, 10)); 740} 741#define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0) 742static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val) 743{ 744 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12)); 745 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF, 746 GENMASK(14, 12)); 747} 748#define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0) 749static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val) 750{ 751 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); 752 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX, 753 BIT(15)); 754} 755#define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0) 756static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val) 757{ 758 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16)); 759 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL, 760 GENMASK(19, 16)); 761} 762#define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0) 763static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val) 764{ 765 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20)); 766 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN, 767 BIT(20)); 768} 769#define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0) 770static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val) 771{ 772 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21)); 773 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN, 774 BIT(21)); 775} 776#define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0) 777static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val) 778{ 779 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22)); 780 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN, 781 BIT(22)); 782} 783#define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0) 784static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val) 785{ 786 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23)); 787 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN, 788 BIT(23)); 789} 790#define SET_CMC_TBL_MASK_DISRTSFB BIT(0) 791static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val) 792{ 793 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25)); 794 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB, 795 BIT(25)); 796} 797#define SET_CMC_TBL_MASK_DISDATAFB BIT(0) 798static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val) 799{ 800 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26)); 801 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB, 802 BIT(26)); 803} 804#define SET_CMC_TBL_MASK_TRYRATE BIT(0) 805static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val) 806{ 807 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27)); 808 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE, 809 BIT(27)); 810} 811#define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0) 812static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val) 813{ 814 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28)); 815 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY, 816 GENMASK(31, 28)); 817} 818#define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0) 819static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val) 820{ 821 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0)); 822 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE, 823 GENMASK(8, 0)); 824} 825#define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0) 826static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val) 827{ 828 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9)); 829 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL, 830 BIT(9)); 831} 832#define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0) 833static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val) 834{ 835 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10)); 836 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL, 837 BIT(10)); 838} 839#define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0) 840static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val) 841{ 842 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11)); 843 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL, 844 BIT(11)); 845} 846#define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0) 847static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val) 848{ 849 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12)); 850 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT, 851 GENMASK(15, 12)); 852} 853#define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0) 854static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val) 855{ 856 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16)); 857 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE, 858 GENMASK(24, 16)); 859} 860#define SET_CMC_TBL_MASK_VCS_STBC BIT(0) 861static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val) 862{ 863 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27)); 864 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC, 865 BIT(27)); 866} 867#define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0) 868static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val) 869{ 870 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28)); 871 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE, 872 GENMASK(31, 28)); 873} 874#define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0) 875static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val) 876{ 877 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0)); 878 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT, 879 GENMASK(5, 0)); 880} 881#define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0) 882static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val) 883{ 884 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6)); 885 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL, 886 BIT(6)); 887} 888#define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0) 889static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val) 890{ 891 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7)); 892 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL, 893 BIT(7)); 894} 895#define SET_CMC_TBL_MASK_RTS_EN BIT(0) 896static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val) 897{ 898 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8)); 899 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN, 900 BIT(8)); 901} 902#define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0) 903static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val) 904{ 905 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9)); 906 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN, 907 BIT(9)); 908} 909#define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0) 910static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val) 911{ 912 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10)); 913 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS, 914 GENMASK(11, 10)); 915} 916#define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0) 917static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val) 918{ 919 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12)); 920 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN, 921 BIT(12)); 922} 923#define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0) 924static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val) 925{ 926 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13)); 927 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE, 928 GENMASK(14, 13)); 929} 930#define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0) 931static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val) 932{ 933 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16)); 934 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN, 935 GENMASK(26, 16)); 936} 937#define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0) 938static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val) 939{ 940 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); 941 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS, 942 BIT(27)); 943} 944#define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0) 945static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val) 946{ 947 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28)); 948 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME, 949 GENMASK(31, 28)); 950} 951#define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0) 952static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val) 953{ 954 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0)); 955 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM, 956 GENMASK(7, 0)); 957} 958#define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0) 959static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val) 960{ 961 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8)); 962 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP, 963 GENMASK(9, 8)); 964} 965#define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0) 966static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val) 967{ 968 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16)); 969 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL, 970 GENMASK(18, 16)); 971} 972#define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0) 973static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val) 974{ 975 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19)); 976 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL, 977 GENMASK(21, 19)); 978} 979#define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0) 980static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val) 981{ 982 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22)); 983 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL, 984 GENMASK(24, 22)); 985} 986#define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0) 987static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val) 988{ 989 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25)); 990 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL, 991 GENMASK(27, 25)); 992} 993#define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0) 994static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val) 995{ 996 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28)); 997 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE, 998 GENMASK(31, 28)); 999} 1000#define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0) 1001static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val) 1002{ 1003 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0)); 1004 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID, 1005 GENMASK(2, 0)); 1006} 1007#define SET_CMC_TBL_MASK_BMC BIT(0) 1008static inline void SET_CMC_TBL_BMC(void *table, u32 val) 1009{ 1010 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3)); 1011 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC, 1012 BIT(3)); 1013} 1014#define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0) 1015static inline void SET_CMC_TBL_MBSSID(void *table, u32 val) 1016{ 1017 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4)); 1018 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID, 1019 GENMASK(7, 4)); 1020} 1021#define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0) 1022static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val) 1023{ 1024 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); 1025 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR, 1026 BIT(8)); 1027} 1028#define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0) 1029static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val) 1030{ 1031 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9)); 1032 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE, 1033 GENMASK(11, 9)); 1034} 1035#define SET_CMC_TBL_MASK_DATA_DCM BIT(0) 1036static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val) 1037{ 1038 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12)); 1039 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM, 1040 BIT(12)); 1041} 1042#define SET_CMC_TBL_MASK_DATA_ER BIT(0) 1043static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val) 1044{ 1045 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13)); 1046 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER, 1047 BIT(13)); 1048} 1049#define SET_CMC_TBL_MASK_DATA_LDPC BIT(0) 1050static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val) 1051{ 1052 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14)); 1053 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC, 1054 BIT(14)); 1055} 1056#define SET_CMC_TBL_MASK_DATA_STBC BIT(0) 1057static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val) 1058{ 1059 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); 1060 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC, 1061 BIT(15)); 1062} 1063#define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0) 1064static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val) 1065{ 1066 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16)); 1067 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR, 1068 BIT(16)); 1069} 1070#define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0) 1071static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val) 1072{ 1073 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17)); 1074 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH, 1075 BIT(17)); 1076} 1077#define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0) 1078static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val) 1079{ 1080 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18)); 1081 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR, 1082 BIT(18)); 1083} 1084#define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0) 1085static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val) 1086{ 1087 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19)); 1088 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS, 1089 BIT(19)); 1090} 1091#define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0) 1092static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val) 1093{ 1094 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20)); 1095 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER, 1096 BIT(20)); 1097} 1098#define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0) 1099static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val) 1100{ 1101 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21)); 1102 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN, 1103 BIT(21)); 1104} 1105#define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0) 1106static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val) 1107{ 1108 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27)); 1109 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD, 1110 BIT(27)); 1111} 1112#define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0) 1113static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val) 1114{ 1115 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28)); 1116 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT, 1117 GENMASK(31, 28)); 1118} 1119#define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0) 1120static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val) 1121{ 1122 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0)); 1123 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE, 1124 GENMASK(8, 0)); 1125} 1126#define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0) 1127static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val) 1128{ 1129 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12)); 1130 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT, 1131 BIT(12)); 1132} 1133#define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0) 1134static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val) 1135{ 1136 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13)); 1137 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT, 1138 BIT(13)); 1139} 1140#define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0) 1141static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val) 1142{ 1143 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16)); 1144 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN, 1145 GENMASK(19, 16)); 1146} 1147#define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0) 1148static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val) 1149{ 1150 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20)); 1151 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A, 1152 GENMASK(21, 20)); 1153} 1154#define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0) 1155static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val) 1156{ 1157 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22)); 1158 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B, 1159 GENMASK(23, 22)); 1160} 1161#define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0) 1162static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val) 1163{ 1164 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24)); 1165 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C, 1166 GENMASK(25, 24)); 1167} 1168#define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0) 1169static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val) 1170{ 1171 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26)); 1172 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D, 1173 GENMASK(27, 26)); 1174} 1175#define SET_CMC_TBL_MASK_ANTSEL_A BIT(0) 1176static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val) 1177{ 1178 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28)); 1179 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A, 1180 BIT(28)); 1181} 1182#define SET_CMC_TBL_MASK_ANTSEL_B BIT(0) 1183static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val) 1184{ 1185 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29)); 1186 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B, 1187 BIT(29)); 1188} 1189#define SET_CMC_TBL_MASK_ANTSEL_C BIT(0) 1190static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val) 1191{ 1192 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30)); 1193 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C, 1194 BIT(30)); 1195} 1196#define SET_CMC_TBL_MASK_ANTSEL_D BIT(0) 1197static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val) 1198{ 1199 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31)); 1200 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D, 1201 BIT(31)); 1202} 1203 1204#define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0) 1205static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val) 1206{ 1207 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0)); 1208 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1209 GENMASK(1, 0)); 1210} 1211 1212static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val) 1213{ 1214 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2)); 1215 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1216 GENMASK(3, 2)); 1217} 1218 1219static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val) 1220{ 1221 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4)); 1222 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1223 GENMASK(5, 4)); 1224} 1225 1226static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val) 1227{ 1228 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6)); 1229 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1230 GENMASK(7, 6)); 1231} 1232 1233#define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0) 1234static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val) 1235{ 1236 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); 1237 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX, 1238 GENMASK(7, 0)); 1239} 1240#define SET_CMC_TBL_MASK_PAID GENMASK(8, 0) 1241static inline void SET_CMC_TBL_PAID(void *table, u32 val) 1242{ 1243 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8)); 1244 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID, 1245 GENMASK(16, 8)); 1246} 1247#define SET_CMC_TBL_MASK_ULDL BIT(0) 1248static inline void SET_CMC_TBL_ULDL(void *table, u32 val) 1249{ 1250 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17)); 1251 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL, 1252 BIT(17)); 1253} 1254#define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0) 1255static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val) 1256{ 1257 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18)); 1258 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL, 1259 GENMASK(19, 18)); 1260} 1261static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val) 1262{ 1263 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20)); 1264 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1265 GENMASK(21, 20)); 1266} 1267 1268static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val) 1269{ 1270 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22)); 1271 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1272 GENMASK(23, 22)); 1273} 1274#define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0) 1275static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val) 1276{ 1277 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24)); 1278 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE, 1279 GENMASK(27, 24)); 1280} 1281 1282static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val) 1283{ 1284 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30)); 1285 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1286 GENMASK(31, 30)); 1287} 1288#define SET_CMC_TBL_MASK_NC GENMASK(2, 0) 1289static inline void SET_CMC_TBL_NC(void *table, u32 val) 1290{ 1291 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0)); 1292 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC, 1293 GENMASK(2, 0)); 1294} 1295#define SET_CMC_TBL_MASK_NR GENMASK(2, 0) 1296static inline void SET_CMC_TBL_NR(void *table, u32 val) 1297{ 1298 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3)); 1299 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR, 1300 GENMASK(5, 3)); 1301} 1302#define SET_CMC_TBL_MASK_NG GENMASK(1, 0) 1303static inline void SET_CMC_TBL_NG(void *table, u32 val) 1304{ 1305 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6)); 1306 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG, 1307 GENMASK(7, 6)); 1308} 1309#define SET_CMC_TBL_MASK_CB GENMASK(1, 0) 1310static inline void SET_CMC_TBL_CB(void *table, u32 val) 1311{ 1312 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8)); 1313 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB, 1314 GENMASK(9, 8)); 1315} 1316#define SET_CMC_TBL_MASK_CS GENMASK(1, 0) 1317static inline void SET_CMC_TBL_CS(void *table, u32 val) 1318{ 1319 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10)); 1320 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS, 1321 GENMASK(11, 10)); 1322} 1323#define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0) 1324static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val) 1325{ 1326 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12)); 1327 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN, 1328 BIT(12)); 1329} 1330#define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0) 1331static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val) 1332{ 1333 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13)); 1334 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN, 1335 BIT(13)); 1336} 1337#define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0) 1338static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val) 1339{ 1340 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14)); 1341 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN, 1342 BIT(14)); 1343} 1344#define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0) 1345static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val) 1346{ 1347 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15)); 1348 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN, 1349 BIT(15)); 1350} 1351#define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0) 1352static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val) 1353{ 1354 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16)); 1355 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE, 1356 GENMASK(24, 16)); 1357} 1358#define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0) 1359static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val) 1360{ 1361 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25)); 1362 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF, 1363 GENMASK(27, 25)); 1364} 1365 1366static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val) 1367{ 1368 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28)); 1369 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1370 GENMASK(29, 28)); 1371} 1372 1373#define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0) 1374static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val) 1375{ 1376 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30)); 1377 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW, 1378 GENMASK(31, 30)); 1379} 1380 1381struct rtw89_h2c_cctlinfo_ud_g7 { 1382 __le32 c0; 1383 __le32 w0; 1384 __le32 w1; 1385 __le32 w2; 1386 __le32 w3; 1387 __le32 w4; 1388 __le32 w5; 1389 __le32 w6; 1390 __le32 w7; 1391 __le32 w8; 1392 __le32 w9; 1393 __le32 w10; 1394 __le32 w11; 1395 __le32 w12; 1396 __le32 w13; 1397 __le32 w14; 1398 __le32 w15; 1399 __le32 m0; 1400 __le32 m1; 1401 __le32 m2; 1402 __le32 m3; 1403 __le32 m4; 1404 __le32 m5; 1405 __le32 m6; 1406 __le32 m7; 1407 __le32 m8; 1408 __le32 m9; 1409 __le32 m10; 1410 __le32 m11; 1411 __le32 m12; 1412 __le32 m13; 1413 __le32 m14; 1414 __le32 m15; 1415} __packed; 1416 1417#define CCTLINFO_G7_C0_MACID GENMASK(6, 0) 1418#define CCTLINFO_G7_C0_OP BIT(7) 1419 1420#define CCTLINFO_G7_W0_DATARATE GENMASK(11, 0) 1421#define CCTLINFO_G7_W0_DATA_GI_LTF GENMASK(14, 12) 1422#define CCTLINFO_G7_W0_TRYRATE BIT(15) 1423#define CCTLINFO_G7_W0_ARFR_CTRL GENMASK(17, 16) 1424#define CCTLINFO_G7_W0_DIS_HE1SS_STBC BIT(18) 1425#define CCTLINFO_G7_W0_ACQ_RPT_EN BIT(20) 1426#define CCTLINFO_G7_W0_MGQ_RPT_EN BIT(21) 1427#define CCTLINFO_G7_W0_ULQ_RPT_EN BIT(22) 1428#define CCTLINFO_G7_W0_TWTQ_RPT_EN BIT(23) 1429#define CCTLINFO_G7_W0_FORCE_TXOP BIT(24) 1430#define CCTLINFO_G7_W0_DISRTSFB BIT(25) 1431#define CCTLINFO_G7_W0_DISDATAFB BIT(26) 1432#define CCTLINFO_G7_W0_NSTR_EN BIT(27) 1433#define CCTLINFO_G7_W0_AMPDU_DENSITY GENMASK(31, 28) 1434#define CCTLINFO_G7_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0)) 1435#define CCTLINFO_G7_W1_DATA_RTY_LOWEST_RATE GENMASK(11, 0) 1436#define CCTLINFO_G7_W1_RTS_TXCNT_LMT GENMASK(15, 12) 1437#define CCTLINFO_G7_W1_RTSRATE GENMASK(27, 16) 1438#define CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE GENMASK(31, 28) 1439#define CCTLINFO_G7_W1_ALL GENMASK(31, 0) 1440#define CCTLINFO_G7_W2_DATA_TX_CNT_LMT GENMASK(5, 0) 1441#define CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL BIT(6) 1442#define CCTLINFO_G7_W2_MAX_AGG_NUM_SEL BIT(7) 1443#define CCTLINFO_G7_W2_RTS_EN BIT(8) 1444#define CCTLINFO_G7_W2_CTS2SELF_EN BIT(9) 1445#define CCTLINFO_G7_W2_CCA_RTS GENMASK(11, 10) 1446#define CCTLINFO_G7_W2_HW_RTS_EN BIT(12) 1447#define CCTLINFO_G7_W2_RTS_DROP_DATA_MODE GENMASK(14, 13) 1448#define CCTLINFO_G7_W2_PRELD_EN BIT(15) 1449#define CCTLINFO_G7_W2_AMPDU_MAX_LEN GENMASK(26, 16) 1450#define CCTLINFO_G7_W2_UL_MU_DIS BIT(27) 1451#define CCTLINFO_G7_W2_AMPDU_MAX_TIME GENMASK(31, 28) 1452#define CCTLINFO_G7_W2_ALL GENMASK(31, 0) 1453#define CCTLINFO_G7_W3_MAX_AGG_NUM GENMASK(7, 0) 1454#define CCTLINFO_G7_W3_DATA_BW GENMASK(10, 8) 1455#define CCTLINFO_G7_W3_DATA_BW_ER BIT(11) 1456#define CCTLINFO_G7_W3_BA_BMAP GENMASK(14, 12) 1457#define CCTLINFO_G7_W3_VCS_STBC BIT(15) 1458#define CCTLINFO_G7_W3_VO_LFTIME_SEL GENMASK(18, 16) 1459#define CCTLINFO_G7_W3_VI_LFTIME_SEL GENMASK(21, 19) 1460#define CCTLINFO_G7_W3_BE_LFTIME_SEL GENMASK(24, 22) 1461#define CCTLINFO_G7_W3_BK_LFTIME_SEL GENMASK(27, 25) 1462#define CCTLINFO_G7_W3_AMPDU_TIME_SEL BIT(28) 1463#define CCTLINFO_G7_W3_AMPDU_LEN_SEL BIT(29) 1464#define CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL BIT(30) 1465#define CCTLINFO_G7_W3_LSIG_TXOP_EN BIT(31) 1466#define CCTLINFO_G7_W3_ALL GENMASK(31, 0) 1467#define CCTLINFO_G7_W4_MULTI_PORT_ID GENMASK(2, 0) 1468#define CCTLINFO_G7_W4_BYPASS_PUNC BIT(3) 1469#define CCTLINFO_G7_W4_MBSSID GENMASK(7, 4) 1470#define CCTLINFO_G7_W4_DATA_DCM BIT(8) 1471#define CCTLINFO_G7_W4_DATA_ER BIT(9) 1472#define CCTLINFO_G7_W4_DATA_LDPC BIT(10) 1473#define CCTLINFO_G7_W4_DATA_STBC BIT(11) 1474#define CCTLINFO_G7_W4_A_CTRL_BQR BIT(12) 1475#define CCTLINFO_G7_W4_A_CTRL_BSR BIT(14) 1476#define CCTLINFO_G7_W4_A_CTRL_CAS BIT(15) 1477#define CCTLINFO_G7_W4_ACT_SUBCH_CBW GENMASK(31, 16) 1478#define CCTLINFO_G7_W4_ALL (GENMASK(31, 14) | GENMASK(12, 0)) 1479#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING0 GENMASK(1, 0) 1480#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING1 GENMASK(3, 2) 1481#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING2 GENMASK(5, 4) 1482#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING3 GENMASK(7, 6) 1483#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING4 GENMASK(9, 8) 1484#define CCTLINFO_G7_W5_SR_RATE GENMASK(14, 10) 1485#define CCTLINFO_G7_W5_TID_DISABLE GENMASK(23, 16) 1486#define CCTLINFO_G7_W5_ADDR_CAM_INDEX GENMASK(31, 24) 1487#define CCTLINFO_G7_W5_ALL (GENMASK(31, 16) | GENMASK(14, 0)) 1488#define CCTLINFO_G7_W6_AID12_PAID GENMASK(11, 0) 1489#define CCTLINFO_G7_W6_RESP_REF_RATE GENMASK(23, 12) 1490#define CCTLINFO_G7_W6_ULDL BIT(31) 1491#define CCTLINFO_G7_W6_ALL (BIT(31) | GENMASK(23, 0)) 1492#define CCTLINFO_G7_W7_NC GENMASK(2, 0) 1493#define CCTLINFO_G7_W7_NR GENMASK(5, 3) 1494#define CCTLINFO_G7_W7_NG GENMASK(7, 6) 1495#define CCTLINFO_G7_W7_CB GENMASK(9, 8) 1496#define CCTLINFO_G7_W7_CS GENMASK(11, 10) 1497#define CCTLINFO_G7_W7_CSI_STBC_EN BIT(13) 1498#define CCTLINFO_G7_W7_CSI_LDPC_EN BIT(14) 1499#define CCTLINFO_G7_W7_CSI_PARA_EN BIT(15) 1500#define CCTLINFO_G7_W7_CSI_FIX_RATE GENMASK(27, 16) 1501#define CCTLINFO_G7_W7_CSI_BW GENMASK(31, 29) 1502#define CCTLINFO_G7_W7_ALL (GENMASK(31, 29) | GENMASK(27, 13) | GENMASK(11, 0)) 1503#define CCTLINFO_G7_W8_ALL_ACK_SUPPORT BIT(0) 1504#define CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT BIT(1) 1505#define CCTLINFO_G7_W8_BSR_OM_UPD_EN BIT(2) 1506#define CCTLINFO_G7_W8_MACID_FWD_IDC BIT(3) 1507#define CCTLINFO_G7_W8_AZ_SEC_EN BIT(4) 1508#define CCTLINFO_G7_W8_CSI_SEC_EN BIT(5) 1509#define CCTLINFO_G7_W8_FIX_UL_ADDRCAM_IDX BIT(6) 1510#define CCTLINFO_G7_W8_CTRL_CNT_VLD BIT(7) 1511#define CCTLINFO_G7_W8_CTRL_CNT GENMASK(11, 8) 1512#define CCTLINFO_G7_W8_RESP_SEC_TYPE GENMASK(15, 12) 1513#define CCTLINFO_G7_W8_ALL GENMASK(15, 0) 1514/* W9~13 are reserved */ 1515#define CCTLINFO_G7_W14_VO_CURR_RATE GENMASK(11, 0) 1516#define CCTLINFO_G7_W14_VI_CURR_RATE GENMASK(23, 12) 1517#define CCTLINFO_G7_W14_BE_CURR_RATE_L GENMASK(31, 24) 1518#define CCTLINFO_G7_W14_ALL GENMASK(31, 0) 1519#define CCTLINFO_G7_W15_BE_CURR_RATE_H GENMASK(3, 0) 1520#define CCTLINFO_G7_W15_BK_CURR_RATE GENMASK(15, 4) 1521#define CCTLINFO_G7_W15_MGNT_CURR_RATE GENMASK(27, 16) 1522#define CCTLINFO_G7_W15_ALL GENMASK(27, 0) 1523 1524struct rtw89_h2c_bcn_upd { 1525 __le32 w0; 1526 __le32 w1; 1527 __le32 w2; 1528} __packed; 1529 1530#define RTW89_H2C_BCN_UPD_W0_PORT GENMASK(7, 0) 1531#define RTW89_H2C_BCN_UPD_W0_MBSSID GENMASK(15, 8) 1532#define RTW89_H2C_BCN_UPD_W0_BAND GENMASK(23, 16) 1533#define RTW89_H2C_BCN_UPD_W0_GRP_IE_OFST GENMASK(31, 24) 1534#define RTW89_H2C_BCN_UPD_W1_MACID GENMASK(7, 0) 1535#define RTW89_H2C_BCN_UPD_W1_SSN_SEL GENMASK(9, 8) 1536#define RTW89_H2C_BCN_UPD_W1_SSN_MODE GENMASK(11, 10) 1537#define RTW89_H2C_BCN_UPD_W1_RATE GENMASK(20, 12) 1538#define RTW89_H2C_BCN_UPD_W1_TXPWR GENMASK(23, 21) 1539#define RTW89_H2C_BCN_UPD_W2_TXINFO_CTRL_EN BIT(0) 1540#define RTW89_H2C_BCN_UPD_W2_NTX_PATH_EN GENMASK(4, 1) 1541#define RTW89_H2C_BCN_UPD_W2_PATH_MAP_A GENMASK(6, 5) 1542#define RTW89_H2C_BCN_UPD_W2_PATH_MAP_B GENMASK(8, 7) 1543#define RTW89_H2C_BCN_UPD_W2_PATH_MAP_C GENMASK(10, 9) 1544#define RTW89_H2C_BCN_UPD_W2_PATH_MAP_D GENMASK(12, 11) 1545#define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_A BIT(13) 1546#define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_B BIT(14) 1547#define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_C BIT(15) 1548#define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_D BIT(16) 1549#define RTW89_H2C_BCN_UPD_W2_CSA_OFST GENMASK(31, 17) 1550 1551struct rtw89_h2c_bcn_upd_be { 1552 __le32 w0; 1553 __le32 w1; 1554 __le32 w2; 1555 __le32 w3; 1556 __le32 w4; 1557 __le32 w5; 1558 __le32 w6; 1559 __le32 w7; 1560 __le32 w8; 1561 __le32 w9; 1562 __le32 w10; 1563 __le32 w11; 1564 __le32 w12; 1565 __le32 w13; 1566 __le32 w14; 1567 __le32 w15; 1568 __le32 w16; 1569 __le32 w17; 1570 __le32 w18; 1571 __le32 w19; 1572 __le32 w20; 1573 __le32 w21; 1574 __le32 w22; 1575 __le32 w23; 1576 __le32 w24; 1577 __le32 w25; 1578 __le32 w26; 1579 __le32 w27; 1580 __le32 w28; 1581 __le32 w29; 1582} __packed; 1583 1584#define RTW89_H2C_BCN_UPD_BE_W0_PORT GENMASK(7, 0) 1585#define RTW89_H2C_BCN_UPD_BE_W0_MBSSID GENMASK(15, 8) 1586#define RTW89_H2C_BCN_UPD_BE_W0_BAND GENMASK(23, 16) 1587#define RTW89_H2C_BCN_UPD_BE_W0_GRP_IE_OFST GENMASK(31, 24) 1588#define RTW89_H2C_BCN_UPD_BE_W1_MACID GENMASK(7, 0) 1589#define RTW89_H2C_BCN_UPD_BE_W1_SSN_SEL GENMASK(9, 8) 1590#define RTW89_H2C_BCN_UPD_BE_W1_SSN_MODE GENMASK(11, 10) 1591#define RTW89_H2C_BCN_UPD_BE_W1_RATE GENMASK(20, 12) 1592#define RTW89_H2C_BCN_UPD_BE_W1_TXPWR GENMASK(23, 21) 1593#define RTW89_H2C_BCN_UPD_BE_W1_MACID_EXT GENMASK(31, 24) 1594#define RTW89_H2C_BCN_UPD_BE_W2_TXINFO_CTRL_EN BIT(0) 1595#define RTW89_H2C_BCN_UPD_BE_W2_NTX_PATH_EN GENMASK(4, 1) 1596#define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_A GENMASK(6, 5) 1597#define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_B GENMASK(8, 7) 1598#define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_C GENMASK(10, 9) 1599#define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_D GENMASK(12, 11) 1600#define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_A BIT(13) 1601#define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_B BIT(14) 1602#define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_C BIT(15) 1603#define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_D BIT(16) 1604#define RTW89_H2C_BCN_UPD_BE_W2_CSA_OFST GENMASK(31, 17) 1605#define RTW89_H2C_BCN_UPD_BE_W3_MLIE_CSA_OFST GENMASK(15, 0) 1606#define RTW89_H2C_BCN_UPD_BE_W3_CRITICAL_UPD_FLAG_OFST GENMASK(31, 16) 1607#define RTW89_H2C_BCN_UPD_BE_W4_VAP1_DTIM_CNT_OFST GENMASK(15, 0) 1608#define RTW89_H2C_BCN_UPD_BE_W4_VAP2_DTIM_CNT_OFST GENMASK(31, 16) 1609#define RTW89_H2C_BCN_UPD_BE_W5_VAP3_DTIM_CNT_OFST GENMASK(15, 0) 1610#define RTW89_H2C_BCN_UPD_BE_W5_VAP4_DTIM_CNT_OFST GENMASK(31, 16) 1611#define RTW89_H2C_BCN_UPD_BE_W6_VAP5_DTIM_CNT_OFST GENMASK(15, 0) 1612#define RTW89_H2C_BCN_UPD_BE_W6_VAP6_DTIM_CNT_OFST GENMASK(31, 16) 1613#define RTW89_H2C_BCN_UPD_BE_W7_VAP7_DTIM_CNT_OFST GENMASK(15, 0) 1614#define RTW89_H2C_BCN_UPD_BE_W7_ECSA_OFST GENMASK(30, 16) 1615#define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID BIT(31) 1616 1617struct rtw89_h2c_tbtt_tuning { 1618 __le32 w0; 1619 __le32 w1; 1620} __packed; 1621 1622#define RTW89_H2C_TBTT_TUNING_W0_BAND GENMASK(3, 0) 1623#define RTW89_H2C_TBTT_TUNING_W0_PORT GENMASK(7, 4) 1624#define RTW89_H2C_TBTT_TUNING_W1_SHIFT GENMASK(31, 0) 1625 1626struct rtw89_h2c_pwr_lvl { 1627 __le32 w0; 1628 __le32 w1; 1629} __packed; 1630 1631#define RTW89_H2C_PWR_LVL_W0_MACID GENMASK(7, 0) 1632#define RTW89_H2C_PWR_LVL_W0_BCN_TO_VAL GENMASK(15, 8) 1633#define RTW89_H2C_PWR_LVL_W0_PS_LVL GENMASK(19, 16) 1634#define RTW89_H2C_PWR_LVL_W0_TRX_LVL GENMASK(23, 20) 1635#define RTW89_H2C_PWR_LVL_W0_BCN_TO_LVL GENMASK(27, 24) 1636#define RTW89_H2C_PWR_LVL_W0_DTIM_TO_VAL GENMASK(31, 28) 1637#define RTW89_H2C_PWR_LVL_W1_MACID_EXT GENMASK(7, 0) 1638 1639struct rtw89_h2c_role_maintain { 1640 __le32 w0; 1641}; 1642 1643#define RTW89_H2C_ROLE_MAINTAIN_W0_MACID GENMASK(7, 0) 1644#define RTW89_H2C_ROLE_MAINTAIN_W0_SELF_ROLE GENMASK(9, 8) 1645#define RTW89_H2C_ROLE_MAINTAIN_W0_UPD_MODE GENMASK(12, 10) 1646#define RTW89_H2C_ROLE_MAINTAIN_W0_WIFI_ROLE GENMASK(16, 13) 1647#define RTW89_H2C_ROLE_MAINTAIN_W0_BAND GENMASK(18, 17) 1648#define RTW89_H2C_ROLE_MAINTAIN_W0_PORT GENMASK(21, 19) 1649#define RTW89_H2C_ROLE_MAINTAIN_W0_MACID_EXT GENMASK(31, 24) 1650 1651enum rtw89_fw_sta_type { /* value of RTW89_H2C_JOININFO_W1_STA_TYPE */ 1652 RTW89_FW_N_AC_STA = 0, 1653 RTW89_FW_AX_STA = 1, 1654 RTW89_FW_BE_STA = 2, 1655}; 1656 1657struct rtw89_h2c_join { 1658 __le32 w0; 1659} __packed; 1660 1661struct rtw89_h2c_join_v1 { 1662 __le32 w0; 1663 __le32 w1; 1664 __le32 w2; 1665} __packed; 1666 1667#define RTW89_H2C_JOININFO_W0_MACID GENMASK(7, 0) 1668#define RTW89_H2C_JOININFO_W0_OP BIT(8) 1669#define RTW89_H2C_JOININFO_W0_BAND BIT(9) 1670#define RTW89_H2C_JOININFO_W0_WMM GENMASK(11, 10) 1671#define RTW89_H2C_JOININFO_W0_TGR BIT(12) 1672#define RTW89_H2C_JOININFO_W0_ISHESTA BIT(13) 1673#define RTW89_H2C_JOININFO_W0_DLBW GENMASK(15, 14) 1674#define RTW89_H2C_JOININFO_W0_TF_MAC_PAD GENMASK(17, 16) 1675#define RTW89_H2C_JOININFO_W0_DL_T_PE GENMASK(20, 18) 1676#define RTW89_H2C_JOININFO_W0_PORT_ID GENMASK(23, 21) 1677#define RTW89_H2C_JOININFO_W0_NET_TYPE GENMASK(25, 24) 1678#define RTW89_H2C_JOININFO_W0_WIFI_ROLE GENMASK(29, 26) 1679#define RTW89_H2C_JOININFO_W0_SELF_ROLE GENMASK(31, 30) 1680#define RTW89_H2C_JOININFO_W1_STA_TYPE GENMASK(2, 0) 1681#define RTW89_H2C_JOININFO_W1_IS_MLD BIT(3) 1682#define RTW89_H2C_JOININFO_W1_MAIN_MACID GENMASK(11, 4) 1683#define RTW89_H2C_JOININFO_W1_MLO_MODE BIT(12) 1684#define RTW89_H2C_JOININFO_MLO_MODE_MLMR 0 1685#define RTW89_H2C_JOININFO_MLO_MODE_MLSR 1 1686#define RTW89_H2C_JOININFO_W1_EMLSR_CAB BIT(13) 1687#define RTW89_H2C_JOININFO_W1_NSTR_EN BIT(14) 1688#define RTW89_H2C_JOININFO_W1_INIT_PWR_STATE BIT(15) 1689#define RTW89_H2C_JOININFO_W1_EMLSR_PADDING GENMASK(18, 16) 1690#define RTW89_H2C_JOININFO_W1_EMLSR_TRANS_DELAY GENMASK(21, 19) 1691#define RTW89_H2C_JOININFO_W2_MACID_EXT GENMASK(7, 0) 1692#define RTW89_H2C_JOININFO_W2_MAIN_MACID_EXT GENMASK(15, 8) 1693 1694struct rtw89_h2c_notify_dbcc { 1695 __le32 w0; 1696} __packed; 1697 1698#define RTW89_H2C_NOTIFY_DBCC_EN BIT(0) 1699 1700static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val) 1701{ 1702 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1703} 1704 1705static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val) 1706{ 1707 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1708} 1709 1710static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val) 1711{ 1712 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1713} 1714 1715static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val) 1716{ 1717 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1718} 1719 1720static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val) 1721{ 1722 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1723} 1724 1725static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val) 1726{ 1727 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); 1728} 1729 1730static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val) 1731{ 1732 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1733} 1734 1735static inline void SET_LOG_CFG_PATH(void *h2c, u32 val) 1736{ 1737 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1738} 1739 1740static inline void SET_LOG_CFG_COMP(void *h2c, u32 val) 1741{ 1742 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)); 1743} 1744 1745static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val) 1746{ 1747 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0)); 1748} 1749 1750struct rtw89_h2c_ba_cam { 1751 __le32 w0; 1752 __le32 w1; 1753} __packed; 1754 1755#define RTW89_H2C_BA_CAM_W0_VALID BIT(0) 1756#define RTW89_H2C_BA_CAM_W0_INIT_REQ BIT(1) 1757#define RTW89_H2C_BA_CAM_W0_ENTRY_IDX GENMASK(3, 2) 1758#define RTW89_H2C_BA_CAM_W0_TID GENMASK(7, 4) 1759#define RTW89_H2C_BA_CAM_W0_MACID GENMASK(15, 8) 1760#define RTW89_H2C_BA_CAM_W0_BMAP_SIZE GENMASK(19, 16) 1761#define RTW89_H2C_BA_CAM_W0_SSN GENMASK(31, 20) 1762#define RTW89_H2C_BA_CAM_W1_UID GENMASK(7, 0) 1763#define RTW89_H2C_BA_CAM_W1_STD_EN BIT(8) 1764#define RTW89_H2C_BA_CAM_W1_BAND BIT(9) 1765#define RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1 GENMASK(31, 28) 1766 1767struct rtw89_h2c_ba_cam_v1 { 1768 __le32 w0; 1769 __le32 w1; 1770} __packed; 1771 1772#define RTW89_H2C_BA_CAM_V1_W0_VALID BIT(0) 1773#define RTW89_H2C_BA_CAM_V1_W0_INIT_REQ BIT(1) 1774#define RTW89_H2C_BA_CAM_V1_W0_TID_MASK GENMASK(7, 4) 1775#define RTW89_H2C_BA_CAM_V1_W0_MACID_MASK GENMASK(15, 8) 1776#define RTW89_H2C_BA_CAM_V1_W0_BMAP_SIZE_MASK GENMASK(19, 16) 1777#define RTW89_H2C_BA_CAM_V1_W0_SSN_MASK GENMASK(31, 20) 1778#define RTW89_H2C_BA_CAM_V1_W1_UID_VALUE_MASK GENMASK(7, 0) 1779#define RTW89_H2C_BA_CAM_V1_W1_STD_ENTRY_EN BIT(8) 1780#define RTW89_H2C_BA_CAM_V1_W1_BAND_SEL BIT(9) 1781#define RTW89_H2C_BA_CAM_V1_W1_MLD_EN BIT(10) 1782#define RTW89_H2C_BA_CAM_V1_W1_ENTRY_IDX_MASK GENMASK(31, 24) 1783 1784struct rtw89_h2c_ba_cam_init { 1785 __le32 w0; 1786} __packed; 1787 1788#define RTW89_H2C_BA_CAM_INIT_USERS_MASK GENMASK(7, 0) 1789#define RTW89_H2C_BA_CAM_INIT_OFFSET_MASK GENMASK(19, 12) 1790#define RTW89_H2C_BA_CAM_INIT_BAND_SEL BIT(24) 1791 1792static inline void SET_LPS_PARM_MACID(void *h2c, u32 val) 1793{ 1794 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1795} 1796 1797static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val) 1798{ 1799 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1800} 1801 1802static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val) 1803{ 1804 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); 1805} 1806 1807static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val) 1808{ 1809 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20)); 1810} 1811 1812static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val) 1813{ 1814 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1815} 1816 1817static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val) 1818{ 1819 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0)); 1820} 1821 1822static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val) 1823{ 1824 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1)); 1825} 1826 1827static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val) 1828{ 1829 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2)); 1830} 1831 1832static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val) 1833{ 1834 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3)); 1835} 1836 1837static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val) 1838{ 1839 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); 1840} 1841 1842struct rtw89_h2c_lps_ch_info { 1843 struct { 1844 u8 pri_ch; 1845 u8 central_ch; 1846 u8 bw; 1847 u8 band; 1848 } __packed info[2]; 1849 1850 __le32 mlo_dbcc_mode_lps; 1851} __packed; 1852 1853struct rtw89_h2c_lps_ml_cmn_info { 1854 u8 fmt_id; 1855 u8 rfe_type; 1856 u8 rsvd0[2]; 1857 __le32 mlo_dbcc_mode; 1858 u8 central_ch[RTW89_PHY_NUM]; 1859 u8 pri_ch[RTW89_PHY_NUM]; 1860 u8 bw[RTW89_PHY_NUM]; 1861 u8 band[RTW89_PHY_NUM]; 1862 u8 bcn_rate_type[RTW89_PHY_NUM]; 1863 u8 rsvd1[2]; 1864 __le16 tia_gain[RTW89_PHY_NUM][TIA_GAIN_NUM]; 1865 u8 lna_gain[RTW89_PHY_NUM][LNA_GAIN_NUM]; 1866 u8 rsvd2[2]; 1867 u8 tia_lna_op1db[RTW89_PHY_NUM][LNA_GAIN_NUM + 1]; 1868 u8 lna_op1db[RTW89_PHY_NUM][LNA_GAIN_NUM]; 1869 u8 dup_bcn_ofst[RTW89_PHY_NUM]; 1870} __packed; 1871 1872struct rtw89_h2c_trig_cpu_except { 1873 __le32 w0; 1874} __packed; 1875 1876#define RTW89_H2C_CPU_EXCEPTION_TYPE GENMASK(31, 0) 1877 1878static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val) 1879{ 1880 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 1881} 1882 1883static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val) 1884{ 1885 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 1886} 1887 1888static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val) 1889{ 1890 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 1891} 1892 1893static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val) 1894{ 1895 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 1896} 1897 1898static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val) 1899{ 1900 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0)); 1901} 1902 1903static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val) 1904{ 1905 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8)); 1906} 1907 1908static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val) 1909{ 1910 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 1911} 1912 1913static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val) 1914{ 1915 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0)); 1916} 1917 1918static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val) 1919{ 1920 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0)); 1921} 1922 1923static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val) 1924{ 1925 le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0)); 1926} 1927 1928static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val) 1929{ 1930 le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0)); 1931} 1932 1933static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val) 1934{ 1935 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1936} 1937 1938static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val) 1939{ 1940 le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16)); 1941} 1942 1943static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val) 1944{ 1945 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1946} 1947 1948static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val) 1949{ 1950 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 1951} 1952 1953static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val) 1954{ 1955 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 1956} 1957 1958static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val) 1959{ 1960 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); 1961} 1962 1963static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val) 1964{ 1965 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1966} 1967 1968static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val) 1969{ 1970 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1971} 1972 1973static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val) 1974{ 1975 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1976} 1977 1978static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val) 1979{ 1980 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1981} 1982 1983struct rtw89_h2c_wow_global { 1984 __le32 w0; 1985 struct rtw89_wow_key_info key_info; 1986} __packed; 1987 1988#define RTW89_H2C_WOW_GLOBAL_W0_ENABLE BIT(0) 1989#define RTW89_H2C_WOW_GLOBAL_W0_DROP_ALL_PKT BIT(1) 1990#define RTW89_H2C_WOW_GLOBAL_W0_RX_PARSE_AFTER_WAKE BIT(2) 1991#define RTW89_H2C_WOW_GLOBAL_W0_WAKE_BAR_PULLED BIT(3) 1992#define RTW89_H2C_WOW_GLOBAL_W0_MAC_ID GENMASK(15, 8) 1993#define RTW89_H2C_WOW_GLOBAL_W0_PAIRWISE_SEC_ALGO GENMASK(23, 16) 1994#define RTW89_H2C_WOW_GLOBAL_W0_GROUP_SEC_ALGO GENMASK(31, 24) 1995 1996#define RTW89_MAX_SUPPORT_NL_NUM 16 1997struct rtw89_h2c_cfg_nlo { 1998 __le32 w0; 1999 u8 nlo_cnt; 2000 u8 rsvd[3]; 2001 __le32 patterncheck; 2002 __le32 rsvd1; 2003 __le32 rsvd2; 2004 u8 ssid_len[RTW89_MAX_SUPPORT_NL_NUM]; 2005 u8 chiper[RTW89_MAX_SUPPORT_NL_NUM]; 2006 u8 rsvd3[24]; 2007 u8 ssid[RTW89_MAX_SUPPORT_NL_NUM][IEEE80211_MAX_SSID_LEN]; 2008} __packed; 2009 2010#define RTW89_H2C_NLO_W0_ENABLE BIT(0) 2011#define RTW89_H2C_NLO_W0_IGNORE_CIPHER BIT(2) 2012#define RTW89_H2C_NLO_W0_MACID GENMASK(31, 24) 2013 2014static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val) 2015{ 2016 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 2017} 2018 2019static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val) 2020{ 2021 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 2022} 2023 2024static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val) 2025{ 2026 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); 2027} 2028 2029static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val) 2030{ 2031 le32p_replace_bits((__le32 *)h2c, val, BIT(3)); 2032} 2033 2034static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val) 2035{ 2036 le32p_replace_bits((__le32 *)h2c, val, BIT(4)); 2037} 2038 2039static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val) 2040{ 2041 le32p_replace_bits((__le32 *)h2c, val, BIT(5)); 2042} 2043 2044static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val) 2045{ 2046 le32p_replace_bits((__le32 *)h2c, val, BIT(6)); 2047} 2048 2049static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val) 2050{ 2051 le32p_replace_bits((__le32 *)h2c, val, BIT(7)); 2052} 2053 2054static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val) 2055{ 2056 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 2057} 2058 2059static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val) 2060{ 2061 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 2062} 2063 2064static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val) 2065{ 2066 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1)); 2067} 2068 2069static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val) 2070{ 2071 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0)); 2072} 2073 2074static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val) 2075{ 2076 le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0)); 2077} 2078 2079static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val) 2080{ 2081 le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0)); 2082} 2083 2084static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val) 2085{ 2086 le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0)); 2087} 2088 2089static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val) 2090{ 2091 le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0)); 2092} 2093 2094static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val) 2095{ 2096 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22)); 2097} 2098 2099static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val) 2100{ 2101 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23)); 2102} 2103 2104static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val) 2105{ 2106 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24)); 2107} 2108 2109static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val) 2110{ 2111 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25)); 2112} 2113 2114static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val) 2115{ 2116 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26)); 2117} 2118 2119static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val) 2120{ 2121 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31)); 2122} 2123 2124struct rtw89_h2c_wow_gtk_ofld { 2125 __le32 w0; 2126 __le32 w1; 2127 struct rtw89_wow_gtk_info gtk_info; 2128} __packed; 2129 2130#define RTW89_H2C_WOW_GTK_OFLD_W0_EN BIT(0) 2131#define RTW89_H2C_WOW_GTK_OFLD_W0_TKIP_EN BIT(1) 2132#define RTW89_H2C_WOW_GTK_OFLD_W0_IEEE80211W_EN BIT(2) 2133#define RTW89_H2C_WOW_GTK_OFLD_W0_PAIRWISE_WAKEUP BIT(3) 2134#define RTW89_H2C_WOW_GTK_OFLD_W0_NOREKEY_WAKEUP BIT(4) 2135#define RTW89_H2C_WOW_GTK_OFLD_W0_MAC_ID GENMASK(23, 16) 2136#define RTW89_H2C_WOW_GTK_OFLD_W0_GTK_RSP_ID GENMASK(31, 24) 2137#define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_SA_QUERY_ID GENMASK(7, 0) 2138#define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_BIP_SEC_ALGO GENMASK(9, 8) 2139#define RTW89_H2C_WOW_GTK_OFLD_W1_ALGO_AKM_SUIT GENMASK(17, 10) 2140 2141struct rtw89_h2c_arp_offload { 2142 __le32 w0; 2143 __le32 w1; 2144} __packed; 2145 2146#define RTW89_H2C_ARP_OFFLOAD_W0_ENABLE BIT(0) 2147#define RTW89_H2C_ARP_OFFLOAD_W0_ACTION BIT(1) 2148#define RTW89_H2C_ARP_OFFLOAD_W0_MACID GENMASK(23, 16) 2149#define RTW89_H2C_ARP_OFFLOAD_W0_PKT_ID GENMASK(31, 24) 2150#define RTW89_H2C_ARP_OFFLOAD_W1_CONTENT GENMASK(31, 0) 2151 2152enum rtw89_btc_btf_h2c_class { 2153 BTFC_SET = 0x10, 2154 BTFC_GET = 0x11, 2155 BTFC_FW_EVENT = 0x12, 2156}; 2157 2158enum rtw89_btc_btf_set { 2159 SET_REPORT_EN = 0x0, 2160 SET_SLOT_TABLE, 2161 SET_MREG_TABLE, 2162 SET_CX_POLICY, 2163 SET_GPIO_DBG, 2164 SET_DRV_INFO, 2165 SET_DRV_EVENT, 2166 SET_BT_WREG_ADDR, 2167 SET_BT_WREG_VAL, 2168 SET_BT_RREG_ADDR, 2169 SET_BT_WL_CH_INFO, 2170 SET_BT_INFO_REPORT, 2171 SET_BT_IGNORE_WLAN_ACT, 2172 SET_BT_TX_PWR, 2173 SET_BT_LNA_CONSTRAIN, 2174 SET_BT_QUERY_DEV_LIST, 2175 SET_BT_QUERY_DEV_INFO, 2176 SET_BT_PSD_REPORT, 2177 SET_H2C_TEST, 2178 SET_IOFLD_RF, 2179 SET_IOFLD_BB, 2180 SET_IOFLD_MAC, 2181 SET_IOFLD_SCBD, 2182 SET_H2C_MACRO, 2183 SET_MAX1, 2184}; 2185 2186enum rtw89_btc_cxdrvinfo { 2187 CXDRVINFO_INIT = 0, 2188 CXDRVINFO_ROLE, 2189 CXDRVINFO_DBCC, 2190 CXDRVINFO_SMAP, 2191 CXDRVINFO_RFK, 2192 CXDRVINFO_RUN, 2193 CXDRVINFO_CTRL, 2194 CXDRVINFO_SCAN, 2195 CXDRVINFO_TRX, /* WL traffic to WL fw */ 2196 CXDRVINFO_TXPWR, 2197 CXDRVINFO_FDDT, 2198 CXDRVINFO_MLO, 2199 CXDRVINFO_OSI, 2200 CXDRVINFO_MAX, 2201}; 2202 2203enum rtw89_scan_mode { 2204 RTW89_SCAN_IMMEDIATE, 2205 RTW89_SCAN_DELAY, 2206}; 2207 2208enum rtw89_scan_type { 2209 RTW89_SCAN_ONCE, 2210 RTW89_SCAN_NORMAL, 2211 RTW89_SCAN_NORMAL_SLOW, 2212 RTW89_SCAN_SEAMLESS, 2213 RTW89_SCAN_MAX, 2214}; 2215 2216static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val) 2217{ 2218 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0)); 2219} 2220 2221static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val) 2222{ 2223 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0)); 2224} 2225 2226struct rtw89_h2c_cxhdr { 2227 u8 type; 2228 u8 len; 2229} __packed; 2230 2231struct rtw89_h2c_cxhdr_v7 { 2232 u8 type; 2233 u8 ver; 2234 u8 len; 2235} __packed; 2236 2237struct rtw89_h2c_cxctrl_v7 { 2238 struct rtw89_h2c_cxhdr_v7 hdr; 2239 struct rtw89_btc_ctrl_v7 ctrl; 2240} __packed; 2241 2242#define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr) 2243#define H2C_LEN_CXDRVHDR_V7 sizeof(struct rtw89_h2c_cxhdr_v7) 2244 2245struct rtw89_btc_wl_role_info_v7_u8 { 2246 u8 connect_cnt; 2247 u8 link_mode; 2248 u8 link_mode_chg; 2249 u8 p2p_2g; 2250 2251 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER]; 2252} __packed; 2253 2254struct rtw89_btc_wl_role_info_v7_u32 { 2255 __le32 role_map; 2256 __le32 mrole_type; 2257 __le32 mrole_noa_duration; 2258 __le32 dbcc_en; 2259 __le32 dbcc_chg; 2260 __le32 dbcc_2g_phy; 2261} __packed; 2262 2263struct rtw89_h2c_cxrole_v7 { 2264 struct rtw89_h2c_cxhdr_v7 hdr; 2265 struct rtw89_btc_wl_role_info_v7_u8 _u8; 2266 struct rtw89_btc_wl_role_info_v7_u32 _u32; 2267} __packed; 2268 2269struct rtw89_btc_wl_role_info_v8_u8 { 2270 u8 connect_cnt; 2271 u8 link_mode; 2272 u8 link_mode_chg; 2273 u8 p2p_2g; 2274 2275 u8 pta_req_band; 2276 u8 dbcc_en; 2277 u8 dbcc_chg; 2278 u8 dbcc_2g_phy; 2279 2280 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 2281} __packed; 2282 2283struct rtw89_btc_wl_role_info_v8_u32 { 2284 __le32 role_map; 2285 __le32 mrole_type; 2286 __le32 mrole_noa_duration; 2287} __packed; 2288 2289struct rtw89_h2c_cxrole_v8 { 2290 struct rtw89_h2c_cxhdr_v7 hdr; 2291 struct rtw89_btc_wl_role_info_v8_u8 _u8; 2292 struct rtw89_btc_wl_role_info_v8_u32 _u32; 2293} __packed; 2294 2295struct rtw89_h2c_cxosi { 2296 struct rtw89_h2c_cxhdr_v7 hdr; 2297 struct rtw89_btc_fbtc_outsrc_set_info osi; 2298} __packed; 2299 2300struct rtw89_h2c_cxinit { 2301 struct rtw89_h2c_cxhdr hdr; 2302 u8 ant_type; 2303 u8 ant_num; 2304 u8 ant_iso; 2305 u8 ant_info; 2306 u8 mod_rfe; 2307 u8 mod_cv; 2308 u8 mod_info; 2309 u8 mod_adie_kt; 2310 u8 wl_gch; 2311 u8 info; 2312 u8 rsvd; 2313 u8 rsvd1; 2314} __packed; 2315 2316#define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0) 2317#define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1) 2318#define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2) 2319#define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4) 2320 2321#define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0) 2322#define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1) 2323#define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2) 2324#define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3) 2325 2326#define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0) 2327#define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1) 2328#define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2) 2329#define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3) 2330#define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4) 2331 2332struct rtw89_h2c_cxinit_v7 { 2333 struct rtw89_h2c_cxhdr_v7 hdr; 2334 struct rtw89_btc_init_info_v7 init; 2335} __packed; 2336 2337static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val) 2338{ 2339 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)); 2340} 2341 2342static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val) 2343{ 2344 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)); 2345} 2346 2347static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val) 2348{ 2349 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0)); 2350} 2351 2352static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val) 2353{ 2354 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1)); 2355} 2356 2357static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val) 2358{ 2359 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2)); 2360} 2361 2362static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val) 2363{ 2364 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3)); 2365} 2366 2367static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val) 2368{ 2369 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4)); 2370} 2371 2372static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val) 2373{ 2374 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5)); 2375} 2376 2377static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val) 2378{ 2379 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6)); 2380} 2381 2382static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val) 2383{ 2384 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7)); 2385} 2386 2387static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val) 2388{ 2389 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8)); 2390} 2391 2392static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val) 2393{ 2394 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9)); 2395} 2396 2397static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val) 2398{ 2399 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10)); 2400} 2401 2402static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val) 2403{ 2404 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11)); 2405} 2406 2407static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset) 2408{ 2409 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0)); 2410} 2411 2412static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset) 2413{ 2414 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1)); 2415} 2416 2417static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset) 2418{ 2419 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4)); 2420} 2421 2422static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset) 2423{ 2424 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5)); 2425} 2426 2427static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset) 2428{ 2429 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6)); 2430} 2431 2432static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset) 2433{ 2434 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0)); 2435} 2436 2437static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset) 2438{ 2439 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1)); 2440} 2441 2442static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset) 2443{ 2444 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0)); 2445} 2446 2447static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset) 2448{ 2449 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0)); 2450} 2451 2452static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset) 2453{ 2454 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0)); 2455} 2456 2457static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset) 2458{ 2459 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0)); 2460} 2461 2462static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset) 2463{ 2464 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0)); 2465} 2466 2467static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset) 2468{ 2469 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0)); 2470} 2471 2472static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset) 2473{ 2474 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0)); 2475} 2476 2477static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset) 2478{ 2479 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0)); 2480} 2481 2482static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset) 2483{ 2484 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1)); 2485} 2486 2487static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset) 2488{ 2489 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4)); 2490} 2491 2492static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset) 2493{ 2494 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5)); 2495} 2496 2497static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset) 2498{ 2499 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6)); 2500} 2501 2502static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset) 2503{ 2504 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0)); 2505} 2506 2507static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset) 2508{ 2509 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1)); 2510} 2511 2512static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset) 2513{ 2514 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0)); 2515} 2516 2517static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset) 2518{ 2519 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0)); 2520} 2521 2522static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset) 2523{ 2524 le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0)); 2525} 2526 2527static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset) 2528{ 2529 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0)); 2530} 2531 2532static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset) 2533{ 2534 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0)); 2535} 2536 2537static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset) 2538{ 2539 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0)); 2540} 2541 2542static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset) 2543{ 2544 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1)); 2545} 2546 2547static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset) 2548{ 2549 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2)); 2550} 2551 2552static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset) 2553{ 2554 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4)); 2555} 2556 2557static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val) 2558{ 2559 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0)); 2560} 2561 2562static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val) 2563{ 2564 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1)); 2565} 2566 2567static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val) 2568{ 2569 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2)); 2570} 2571 2572static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val) 2573{ 2574 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3)); 2575} 2576 2577static inline void RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val) 2578{ 2579 u8p_replace_bits((u8 *)cmd + 2, val, GENMASK(7, 0)); 2580} 2581 2582static inline void RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val) 2583{ 2584 u8p_replace_bits((u8 *)cmd + 3, val, GENMASK(7, 0)); 2585} 2586 2587static inline void RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val) 2588{ 2589 u8p_replace_bits((u8 *)cmd + 4, val, GENMASK(7, 0)); 2590} 2591 2592static inline void RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val) 2593{ 2594 u8p_replace_bits((u8 *)cmd + 5, val, GENMASK(7, 0)); 2595} 2596 2597static inline void RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val) 2598{ 2599 u8p_replace_bits((u8 *)cmd + 6, val, GENMASK(7, 0)); 2600} 2601 2602static inline void RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val) 2603{ 2604 u8p_replace_bits((u8 *)cmd + 7, val, GENMASK(7, 0)); 2605} 2606 2607static inline void RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val) 2608{ 2609 u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0)); 2610} 2611 2612static inline void RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val) 2613{ 2614 u8p_replace_bits((u8 *)cmd + 9, val, GENMASK(7, 0)); 2615} 2616 2617static inline void RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val) 2618{ 2619 u8p_replace_bits((u8 *)cmd + 10, val, GENMASK(7, 0)); 2620} 2621 2622static inline void RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val) 2623{ 2624 u8p_replace_bits((u8 *)cmd + 11, val, GENMASK(7, 0)); 2625} 2626 2627static inline void RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val) 2628{ 2629 u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0)); 2630} 2631 2632static inline void RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val) 2633{ 2634 u8p_replace_bits((u8 *)cmd + 13, val, GENMASK(7, 0)); 2635} 2636 2637static inline void RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val) 2638{ 2639 le16p_replace_bits((__le16 *)((u8 *)cmd + 14), val, GENMASK(15, 0)); 2640} 2641 2642static inline void RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val) 2643{ 2644 le16p_replace_bits((__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0)); 2645} 2646 2647static inline void RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val) 2648{ 2649 le32p_replace_bits((__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0)); 2650} 2651 2652static inline void RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val) 2653{ 2654 le32p_replace_bits((__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0)); 2655} 2656 2657static inline void RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val) 2658{ 2659 le32p_replace_bits((__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0)); 2660} 2661 2662static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val) 2663{ 2664 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0)); 2665} 2666 2667static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val) 2668{ 2669 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2)); 2670} 2671 2672static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val) 2673{ 2674 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6)); 2675} 2676 2677static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val) 2678{ 2679 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8)); 2680} 2681 2682static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val) 2683{ 2684 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10)); 2685} 2686 2687static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val) 2688{ 2689 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2690} 2691 2692static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val) 2693{ 2694 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8)); 2695} 2696 2697static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val) 2698{ 2699 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16)); 2700} 2701 2702struct rtw89_h2c_chinfo_elem { 2703 __le32 w0; 2704 __le32 w1; 2705 __le32 w2; 2706 __le32 w3; 2707 __le32 w4; 2708 __le32 w5; 2709 __le32 w6; 2710} __packed; 2711 2712#define RTW89_H2C_CHINFO_W0_PERIOD GENMASK(7, 0) 2713#define RTW89_H2C_CHINFO_W0_DWELL GENMASK(15, 8) 2714#define RTW89_H2C_CHINFO_W0_CENTER_CH GENMASK(23, 16) 2715#define RTW89_H2C_CHINFO_W0_PRI_CH GENMASK(31, 24) 2716#define RTW89_H2C_CHINFO_W1_BW GENMASK(2, 0) 2717#define RTW89_H2C_CHINFO_W1_ACTION GENMASK(7, 3) 2718#define RTW89_H2C_CHINFO_W1_NUM_PKT GENMASK(11, 8) 2719#define RTW89_H2C_CHINFO_W1_TX BIT(12) 2720#define RTW89_H2C_CHINFO_W1_PAUSE_DATA BIT(13) 2721#define RTW89_H2C_CHINFO_W1_BAND GENMASK(15, 14) 2722#define RTW89_H2C_CHINFO_W1_PKT_ID GENMASK(23, 16) 2723#define RTW89_H2C_CHINFO_W1_DFS BIT(24) 2724#define RTW89_H2C_CHINFO_W1_TX_NULL BIT(25) 2725#define RTW89_H2C_CHINFO_W1_RANDOM BIT(26) 2726#define RTW89_H2C_CHINFO_W1_CFG_TX BIT(27) 2727#define RTW89_H2C_CHINFO_W1_MACID_TX BIT(29) 2728#define RTW89_H2C_CHINFO_W2_PKT0 GENMASK(7, 0) 2729#define RTW89_H2C_CHINFO_W2_PKT1 GENMASK(15, 8) 2730#define RTW89_H2C_CHINFO_W2_PKT2 GENMASK(23, 16) 2731#define RTW89_H2C_CHINFO_W2_PKT3 GENMASK(31, 24) 2732#define RTW89_H2C_CHINFO_W3_PKT4 GENMASK(7, 0) 2733#define RTW89_H2C_CHINFO_W3_PKT5 GENMASK(15, 8) 2734#define RTW89_H2C_CHINFO_W3_PKT6 GENMASK(23, 16) 2735#define RTW89_H2C_CHINFO_W3_PKT7 GENMASK(31, 24) 2736#define RTW89_H2C_CHINFO_W4_POWER_IDX GENMASK(15, 0) 2737 2738struct rtw89_h2c_chinfo_elem_be { 2739 __le32 w0; 2740 __le32 w1; 2741 __le32 w2; 2742 __le32 w3; 2743 __le32 w4; 2744 __le32 w5; 2745 __le32 w6; 2746 __le32 w7; 2747} __packed; 2748 2749#define RTW89_H2C_CHINFO_BE_W0_PERIOD GENMASK(7, 0) 2750#define RTW89_H2C_CHINFO_BE_W0_DWELL GENMASK(15, 8) 2751#define RTW89_H2C_CHINFO_BE_W0_CENTER_CH GENMASK(23, 16) 2752#define RTW89_H2C_CHINFO_BE_W0_PRI_CH GENMASK(31, 24) 2753#define RTW89_H2C_CHINFO_BE_W1_BW GENMASK(2, 0) 2754#define RTW89_H2C_CHINFO_BE_W1_CH_BAND GENMASK(4, 3) 2755#define RTW89_H2C_CHINFO_BE_W1_DFS BIT(5) 2756#define RTW89_H2C_CHINFO_BE_W1_PAUSE_DATA BIT(6) 2757#define RTW89_H2C_CHINFO_BE_W1_TX_NULL BIT(7) 2758#define RTW89_H2C_CHINFO_BE_W1_RANDOM BIT(8) 2759#define RTW89_H2C_CHINFO_BE_W1_NOTIFY GENMASK(13, 9) 2760#define RTW89_H2C_CHINFO_BE_W1_PROBE BIT(14) 2761#define RTW89_H2C_CHINFO_BE_W1_EARLY_LEAVE_CRIT GENMASK(17, 15) 2762#define RTW89_H2C_CHINFO_BE_W1_CHKPT_TIMER GENMASK(31, 24) 2763#define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TIME GENMASK(7, 0) 2764#define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TH GENMASK(15, 8) 2765#define RTW89_H2C_CHINFO_BE_W2_TX_PKT_CTRL GENMASK(31, 16) 2766#define RTW89_H2C_CHINFO_BE_W3_PKT0 GENMASK(7, 0) 2767#define RTW89_H2C_CHINFO_BE_W3_PKT1 GENMASK(15, 8) 2768#define RTW89_H2C_CHINFO_BE_W3_PKT2 GENMASK(23, 16) 2769#define RTW89_H2C_CHINFO_BE_W3_PKT3 GENMASK(31, 24) 2770#define RTW89_H2C_CHINFO_BE_W4_PKT4 GENMASK(7, 0) 2771#define RTW89_H2C_CHINFO_BE_W4_PKT5 GENMASK(15, 8) 2772#define RTW89_H2C_CHINFO_BE_W4_PKT6 GENMASK(23, 16) 2773#define RTW89_H2C_CHINFO_BE_W4_PKT7 GENMASK(31, 24) 2774#define RTW89_H2C_CHINFO_BE_W5_SW_DEF GENMASK(7, 0) 2775#define RTW89_H2C_CHINFO_BE_W5_FW_PROBE0_SSIDS GENMASK(31, 16) 2776#define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_SHORTSSIDS GENMASK(15, 0) 2777#define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_BSSIDS GENMASK(31, 16) 2778#define RTW89_H2C_CHINFO_BE_W7_PERIOD_V1 GENMASK(15, 0) 2779 2780struct rtw89_h2c_chinfo { 2781 u8 ch_num; 2782 u8 elem_size; 2783 u8 arg; 2784 u8 rsvd0; 2785 struct rtw89_h2c_chinfo_elem elem[] __counted_by(ch_num); 2786} __packed; 2787 2788struct rtw89_h2c_chinfo_be { 2789 u8 ch_num; 2790 u8 elem_size; 2791 u8 arg; 2792 u8 rsvd0; 2793 struct rtw89_h2c_chinfo_elem_be elem[] __counted_by(ch_num); 2794} __packed; 2795 2796#define RTW89_H2C_CHINFO_ARG_MAC_IDX_MASK BIT(0) 2797#define RTW89_H2C_CHINFO_ARG_APPEND_MASK BIT(1) 2798 2799struct rtw89_h2c_scanofld { 2800 __le32 w0; 2801 __le32 w1; 2802 __le32 w2; 2803 __le32 tsf_high; 2804 __le32 tsf_low; 2805 __le32 w5; 2806 __le32 w6; 2807} __packed; 2808 2809#define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0) 2810#define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8) 2811#define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16) 2812#define RTW89_H2C_SCANOFLD_W0_BAND BIT(19) 2813#define RTW89_H2C_SCANOFLD_W0_OPERATION GENMASK(21, 20) 2814#define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND GENMASK(23, 22) 2815#define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0) 2816#define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1) 2817#define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2) 2818#define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE GENMASK(4, 3) 2819#define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5) 2820#define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8) 2821#define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16) 2822#define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24) 2823#define RTW89_H2C_SCANOFLD_W2_NORM_PD GENMASK(15, 0) 2824#define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16) 2825#define RTW89_H2C_SCANOFLD_W3_TSF_HIGH GENMASK(31, 0) 2826#define RTW89_H2C_SCANOFLD_W4_TSF_LOW GENMASK(31, 0) 2827#define RTW89_H2C_SCANOFLD_W6_SECOND_MACID GENMASK(31, 24) 2828 2829struct rtw89_h2c_scanofld_be_macc_role { 2830 __le32 w0; 2831} __packed; 2832 2833#define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_BAND GENMASK(1, 0) 2834#define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_PORT GENMASK(4, 2) 2835#define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_MACID GENMASK(23, 8) 2836#define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_OPCH_END GENMASK(31, 24) 2837 2838struct rtw89_h2c_scanofld_be_opch { 2839 __le32 w0; 2840 __le32 w1; 2841 __le32 w2; 2842 __le32 w3; 2843 __le32 w4; 2844} __packed; 2845 2846#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_MACID GENMASK(15, 0) 2847#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_BAND GENMASK(17, 16) 2848#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_PORT GENMASK(20, 18) 2849#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY GENMASK(22, 21) 2850#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_TXNULL BIT(23) 2851#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY_VAL GENMASK(31, 24) 2852#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_DURATION GENMASK(7, 0) 2853#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CH_BAND GENMASK(9, 8) 2854#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_BW GENMASK(12, 10) 2855#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_NOTIFY GENMASK(14, 13) 2856#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_PRI_CH GENMASK(23, 16) 2857#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CENTRAL_CH GENMASK(31, 24) 2858#define RTW89_H2C_SCANOFLD_BE_OPCH_W2_PKTS_CTRL GENMASK(7, 0) 2859#define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SW_DEF GENMASK(15, 8) 2860#define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SS GENMASK(18, 16) 2861#define RTW89_H2C_SCANOFLD_BE_OPCH_W2_TXBCN BIT(19) 2862#define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT0 GENMASK(7, 0) 2863#define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT1 GENMASK(15, 8) 2864#define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT2 GENMASK(23, 16) 2865#define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT3 GENMASK(31, 24) 2866#define RTW89_H2C_SCANOFLD_BE_OPCH_W4_DURATION_V1 GENMASK(15, 0) 2867 2868struct rtw89_h2c_scanofld_be { 2869 __le32 w0; 2870 __le32 w1; 2871 __le32 w2; 2872 __le32 w3; 2873 __le32 w4; 2874 __le32 w5; 2875 __le32 w6; 2876 __le32 w7; 2877 __le32 w8; 2878 __le32 w9; /* Added after SCAN_OFFLOAD_BE_V1 */ 2879 /* struct rtw89_h2c_scanofld_be_macc_role (flexible number) */ 2880 /* struct rtw89_h2c_scanofld_be_opch (flexible number) */ 2881} __packed; 2882 2883#define RTW89_H2C_SCANOFLD_BE_W0_OP GENMASK(1, 0) 2884#define RTW89_H2C_SCANOFLD_BE_W0_SCAN_MODE GENMASK(3, 2) 2885#define RTW89_H2C_SCANOFLD_BE_W0_REPEAT GENMASK(5, 4) 2886#define RTW89_H2C_SCANOFLD_BE_W0_NOTIFY_END BIT(6) 2887#define RTW89_H2C_SCANOFLD_BE_W0_LEARN_CH BIT(7) 2888#define RTW89_H2C_SCANOFLD_BE_W0_MACID GENMASK(23, 8) 2889#define RTW89_H2C_SCANOFLD_BE_W0_PORT GENMASK(26, 24) 2890#define RTW89_H2C_SCANOFLD_BE_W0_BAND GENMASK(28, 27) 2891#define RTW89_H2C_SCANOFLD_BE_W0_PROBE_WITH_RATE BIT(29) 2892#define RTW89_H2C_SCANOFLD_BE_W1_NUM_MACC_ROLE GENMASK(7, 0) 2893#define RTW89_H2C_SCANOFLD_BE_W1_NUM_OP GENMASK(15, 8) 2894#define RTW89_H2C_SCANOFLD_BE_W1_NORM_PD GENMASK(31, 16) 2895#define RTW89_H2C_SCANOFLD_BE_W2_SLOW_PD GENMASK(15, 0) 2896#define RTW89_H2C_SCANOFLD_BE_W2_NORM_CY GENMASK(23, 16) 2897#define RTW89_H2C_SCANOFLD_BE_W2_OPCH_END GENMASK(31, 24) 2898#define RTW89_H2C_SCANOFLD_BE_W3_NUM_SSID GENMASK(7, 0) 2899#define RTW89_H2C_SCANOFLD_BE_W3_NUM_SHORT_SSID GENMASK(15, 8) 2900#define RTW89_H2C_SCANOFLD_BE_W3_NUM_BSSID GENMASK(23, 16) 2901#define RTW89_H2C_SCANOFLD_BE_W3_PROBEID GENMASK(31, 24) 2902#define RTW89_H2C_SCANOFLD_BE_W4_PROBE_5G GENMASK(7, 0) 2903#define RTW89_H2C_SCANOFLD_BE_W4_PROBE_6G GENMASK(15, 8) 2904#define RTW89_H2C_SCANOFLD_BE_W4_DELAY_START GENMASK(31, 16) 2905#define RTW89_H2C_SCANOFLD_BE_W5_MLO_MODE GENMASK(31, 0) 2906#define RTW89_H2C_SCANOFLD_BE_W6_CHAN_PROHIB_LOW GENMASK(31, 0) 2907#define RTW89_H2C_SCANOFLD_BE_W7_CHAN_PROHIB_HIGH GENMASK(31, 0) 2908#define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_2GHZ GENMASK(7, 0) 2909#define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_5GHZ GENMASK(15, 8) 2910#define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_6GHZ GENMASK(23, 16) 2911#define RTW89_H2C_SCANOFLD_BE_W9_SIZE_CFG GENMASK(7, 0) 2912#define RTW89_H2C_SCANOFLD_BE_W9_SIZE_MACC GENMASK(15, 8) 2913#define RTW89_H2C_SCANOFLD_BE_W9_SIZE_OP GENMASK(23, 16) 2914 2915struct rtw89_h2c_fwips { 2916 __le32 w0; 2917} __packed; 2918 2919#define RTW89_H2C_FW_IPS_W0_MACID GENMASK(7, 0) 2920#define RTW89_H2C_FW_IPS_W0_ENABLE BIT(8) 2921 2922struct rtw89_h2c_mlo_link_cfg { 2923 __le32 w0; 2924}; 2925 2926#define RTW89_H2C_MLO_LINK_CFG_W0_MACID GENMASK(15, 0) 2927#define RTW89_H2C_MLO_LINK_CFG_W0_OPTION GENMASK(19, 16) 2928 2929static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val) 2930{ 2931 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 2932} 2933 2934static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val) 2935{ 2936 le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8)); 2937} 2938 2939static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val) 2940{ 2941 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12)); 2942} 2943 2944static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val) 2945{ 2946 le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16)); 2947} 2948 2949static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val) 2950{ 2951 le32p_replace_bits((__le32 *)cmd, val, BIT(20)); 2952} 2953 2954static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val) 2955{ 2956 le32p_replace_bits((__le32 *)cmd, val, BIT(21)); 2957} 2958 2959static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val) 2960{ 2961 *((__le32 *)cmd + 1) = val; 2962} 2963 2964static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val) 2965{ 2966 *((__le32 *)cmd + 2) = val; 2967} 2968 2969static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val) 2970{ 2971 *((__le32 *)cmd + 3) = val; 2972} 2973 2974static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val) 2975{ 2976 le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0)); 2977} 2978 2979static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val) 2980{ 2981 u8 ctwnd; 2982 2983 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT)) 2984 return; 2985 ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val); 2986 le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8)); 2987} 2988 2989static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val) 2990{ 2991 le32p_replace_bits((__le32 *)cmd, val, BIT(0)); 2992} 2993 2994static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val) 2995{ 2996 le32p_replace_bits((__le32 *)cmd, val, BIT(1)); 2997} 2998 2999static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val) 3000{ 3001 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2)); 3002} 3003 3004static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val) 3005{ 3006 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16)); 3007} 3008 3009enum rtw89_fw_mcc_c2h_rpt_cfg { 3010 RTW89_FW_MCC_C2H_RPT_OFF = 0, 3011 RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1, 3012 RTW89_FW_MCC_C2H_RPT_ALL = 2, 3013}; 3014 3015struct rtw89_fw_mcc_add_req { 3016 u8 macid; 3017 u8 central_ch_seg0; 3018 u8 central_ch_seg1; 3019 u8 primary_ch; 3020 enum rtw89_bandwidth bandwidth: 4; 3021 u32 group: 2; 3022 u32 c2h_rpt: 2; 3023 u32 dis_tx_null: 1; 3024 u32 dis_sw_retry: 1; 3025 u32 in_curr_ch: 1; 3026 u32 sw_retry_count: 3; 3027 u32 tx_null_early: 4; 3028 u32 btc_in_2g: 1; 3029 u32 pta_en: 1; 3030 u32 rfk_by_pass: 1; 3031 u32 ch_band_type: 2; 3032 u32 rsvd0: 9; 3033 u32 duration; 3034 u8 courtesy_en; 3035 u8 courtesy_num; 3036 u8 courtesy_target; 3037 u8 rsvd1; 3038}; 3039 3040static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val) 3041{ 3042 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 3043} 3044 3045static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val) 3046{ 3047 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3048} 3049 3050static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val) 3051{ 3052 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3053} 3054 3055static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val) 3056{ 3057 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 3058} 3059 3060static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val) 3061{ 3062 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0)); 3063} 3064 3065static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val) 3066{ 3067 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4)); 3068} 3069 3070static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val) 3071{ 3072 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6)); 3073} 3074 3075static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val) 3076{ 3077 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8)); 3078} 3079 3080static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val) 3081{ 3082 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9)); 3083} 3084 3085static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val) 3086{ 3087 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10)); 3088} 3089 3090static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val) 3091{ 3092 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11)); 3093} 3094 3095static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val) 3096{ 3097 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14)); 3098} 3099 3100static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val) 3101{ 3102 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18)); 3103} 3104 3105static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val) 3106{ 3107 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19)); 3108} 3109 3110static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val) 3111{ 3112 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20)); 3113} 3114 3115static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val) 3116{ 3117 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21)); 3118} 3119 3120static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val) 3121{ 3122 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 3123} 3124 3125static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val) 3126{ 3127 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0)); 3128} 3129 3130static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val) 3131{ 3132 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8)); 3133} 3134 3135static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val) 3136{ 3137 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16)); 3138} 3139 3140enum rtw89_fw_mcc_old_group_actions { 3141 RTW89_FW_MCC_OLD_GROUP_ACT_NONE = 0, 3142 RTW89_FW_MCC_OLD_GROUP_ACT_REPLACE = 1, 3143}; 3144 3145struct rtw89_fw_mcc_start_req { 3146 u32 group: 2; 3147 u32 btc_in_group: 1; 3148 u32 old_group_action: 2; 3149 u32 old_group: 2; 3150 u32 rsvd0: 9; 3151 u32 notify_cnt: 3; 3152 u32 rsvd1: 2; 3153 u32 notify_rxdbg_en: 1; 3154 u32 rsvd2: 2; 3155 u32 macid: 8; 3156 u32 tsf_low; 3157 u32 tsf_high; 3158}; 3159 3160static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val) 3161{ 3162 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3163} 3164 3165static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val) 3166{ 3167 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 3168} 3169 3170static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val) 3171{ 3172 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3)); 3173} 3174 3175static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val) 3176{ 3177 le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5)); 3178} 3179 3180static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val) 3181{ 3182 le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16)); 3183} 3184 3185static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val) 3186{ 3187 le32p_replace_bits((__le32 *)cmd, val, BIT(21)); 3188} 3189 3190static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val) 3191{ 3192 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 3193} 3194 3195static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val) 3196{ 3197 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0)); 3198} 3199 3200static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val) 3201{ 3202 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 3203} 3204 3205static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val) 3206{ 3207 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 3208} 3209 3210static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val) 3211{ 3212 le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8)); 3213} 3214 3215static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val) 3216{ 3217 le32p_replace_bits((__le32 *)cmd, val, BIT(10)); 3218} 3219 3220static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val) 3221{ 3222 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3223} 3224 3225static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val) 3226{ 3227 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 3228} 3229 3230static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val) 3231{ 3232 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3233} 3234 3235struct rtw89_fw_mcc_tsf_req { 3236 u8 group: 2; 3237 u8 rsvd0: 6; 3238 u8 macid_x; 3239 u8 macid_y; 3240 u8 rsvd1; 3241}; 3242 3243static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val) 3244{ 3245 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3246} 3247 3248static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val) 3249{ 3250 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3251} 3252 3253static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val) 3254{ 3255 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3256} 3257 3258static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val) 3259{ 3260 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3261} 3262 3263static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val) 3264{ 3265 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3266} 3267 3268static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val) 3269{ 3270 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3271} 3272 3273static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd, 3274 u8 *bitmap, u8 len) 3275{ 3276 memcpy((__le32 *)cmd + 1, bitmap, len); 3277} 3278 3279static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val) 3280{ 3281 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3282} 3283 3284static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val) 3285{ 3286 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3287} 3288 3289static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val) 3290{ 3291 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3292} 3293 3294static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val) 3295{ 3296 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 3297} 3298 3299struct rtw89_fw_mcc_duration { 3300 u32 group: 2; 3301 u32 btc_in_group: 1; 3302 u32 rsvd0: 5; 3303 u32 start_macid: 8; 3304 u32 macid_x: 8; 3305 u32 macid_y: 8; 3306 u32 start_tsf_low; 3307 u32 start_tsf_high; 3308 u32 duration_x; 3309 u32 duration_y; 3310}; 3311 3312static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val) 3313{ 3314 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3315} 3316 3317static 3318inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val) 3319{ 3320 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 3321} 3322 3323static 3324inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val) 3325{ 3326 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3327} 3328 3329static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val) 3330{ 3331 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3332} 3333 3334static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val) 3335{ 3336 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 3337} 3338 3339static 3340inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val) 3341{ 3342 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0)); 3343} 3344 3345static 3346inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val) 3347{ 3348 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 3349} 3350 3351static 3352inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val) 3353{ 3354 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0)); 3355} 3356 3357static 3358inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val) 3359{ 3360 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0)); 3361} 3362 3363enum rtw89_h2c_mrc_sch_types { 3364 RTW89_H2C_MRC_SCH_BAND0_ONLY = 0, 3365 RTW89_H2C_MRC_SCH_BAND1_ONLY = 1, 3366 RTW89_H2C_MRC_SCH_DUAL_BAND = 2, 3367}; 3368 3369enum rtw89_h2c_mrc_role_types { 3370 RTW89_H2C_MRC_ROLE_WIFI = 0, 3371 RTW89_H2C_MRC_ROLE_BT = 1, 3372 RTW89_H2C_MRC_ROLE_EMPTY = 2, 3373}; 3374 3375#define RTW89_MAC_MRC_MAX_ADD_SLOT_NUM 3 3376#define RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT 1 /* before MLO */ 3377 3378struct rtw89_fw_mrc_add_slot_arg { 3379 u16 duration; /* unit: TU */ 3380 bool courtesy_en; 3381 u8 courtesy_period; 3382 u8 courtesy_target; /* slot idx */ 3383 3384 unsigned int role_num; 3385 struct { 3386 enum rtw89_h2c_mrc_role_types role_type; 3387 bool is_master; 3388 bool en_tx_null; 3389 enum rtw89_band band; 3390 enum rtw89_bandwidth bw; 3391 u8 macid; 3392 u8 central_ch; 3393 u8 primary_ch; 3394 u8 null_early; /* unit: TU */ 3395 3396 /* if MLD, for macid: [0, chip::support_mld_num) 3397 * otherwise, for macid: [0, 32) 3398 */ 3399 u32 macid_main_bitmap; 3400 /* for MLD, bit X maps to macid: X + chip::support_mld_num */ 3401 u32 macid_paired_bitmap; 3402 } roles[RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT]; 3403}; 3404 3405struct rtw89_fw_mrc_add_arg { 3406 u8 sch_idx; 3407 enum rtw89_h2c_mrc_sch_types sch_type; 3408 bool btc_in_sch; 3409 3410 unsigned int slot_num; 3411 struct rtw89_fw_mrc_add_slot_arg slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM]; 3412}; 3413 3414struct rtw89_h2c_mrc_add_role { 3415 __le32 w0; 3416 __le32 w1; 3417 __le32 w2; 3418 __le32 macid_main_bitmap; 3419 __le32 macid_paired_bitmap; 3420} __packed; 3421 3422#define RTW89_H2C_MRC_ADD_ROLE_W0_MACID GENMASK(15, 0) 3423#define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_TYPE GENMASK(23, 16) 3424#define RTW89_H2C_MRC_ADD_ROLE_W0_IS_MASTER BIT(24) 3425#define RTW89_H2C_MRC_ADD_ROLE_W0_IS_ALT_ROLE BIT(25) 3426#define RTW89_H2C_MRC_ADD_ROLE_W0_TX_NULL_EN BIT(26) 3427#define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_ALT_EN BIT(27) 3428#define RTW89_H2C_MRC_ADD_ROLE_W1_CENTRAL_CH_SEG GENMASK(7, 0) 3429#define RTW89_H2C_MRC_ADD_ROLE_W1_PRI_CH GENMASK(15, 8) 3430#define RTW89_H2C_MRC_ADD_ROLE_W1_BW GENMASK(19, 16) 3431#define RTW89_H2C_MRC_ADD_ROLE_W1_CH_BAND_TYPE GENMASK(21, 20) 3432#define RTW89_H2C_MRC_ADD_ROLE_W1_RFK_BY_PASS BIT(22) 3433#define RTW89_H2C_MRC_ADD_ROLE_W1_CAN_BTC BIT(23) 3434#define RTW89_H2C_MRC_ADD_ROLE_W1_NULL_EARLY GENMASK(31, 24) 3435#define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_PERIOD GENMASK(7, 0) 3436#define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_TYPE GENMASK(15, 8) 3437#define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_MACID GENMASK(23, 16) 3438 3439struct rtw89_h2c_mrc_add_slot { 3440 __le32 w0; 3441 __le32 w1; 3442 struct rtw89_h2c_mrc_add_role roles[]; 3443} __packed; 3444 3445#define RTW89_H2C_MRC_ADD_SLOT_W0_DURATION GENMASK(15, 0) 3446#define RTW89_H2C_MRC_ADD_SLOT_W0_COURTESY_EN BIT(17) 3447#define RTW89_H2C_MRC_ADD_SLOT_W0_ROLE_NUM GENMASK(31, 24) 3448#define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_PERIOD GENMASK(7, 0) 3449#define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_TARGET GENMASK(15, 8) 3450 3451struct rtw89_h2c_mrc_add { 3452 __le32 w0; 3453 /* Logically append flexible struct rtw89_h2c_mrc_add_slot, but there 3454 * are other flexible array inside it. We cannot access them correctly 3455 * through this struct. So, in case misusing, we don't really declare 3456 * it here. 3457 */ 3458} __packed; 3459 3460#define RTW89_H2C_MRC_ADD_W0_SCH_IDX GENMASK(3, 0) 3461#define RTW89_H2C_MRC_ADD_W0_SCH_TYPE GENMASK(7, 4) 3462#define RTW89_H2C_MRC_ADD_W0_SLOT_NUM GENMASK(15, 8) 3463#define RTW89_H2C_MRC_ADD_W0_BTC_IN_SCH BIT(16) 3464 3465enum rtw89_h2c_mrc_start_actions { 3466 RTW89_H2C_MRC_START_ACTION_START_NEW = 0, 3467 RTW89_H2C_MRC_START_ACTION_REPLACE_OLD = 1, 3468}; 3469 3470struct rtw89_fw_mrc_start_arg { 3471 u8 sch_idx; 3472 u8 old_sch_idx; 3473 u64 start_tsf; 3474 enum rtw89_h2c_mrc_start_actions action; 3475}; 3476 3477struct rtw89_h2c_mrc_start { 3478 __le32 w0; 3479 __le32 start_tsf_low; 3480 __le32 start_tsf_high; 3481} __packed; 3482 3483#define RTW89_H2C_MRC_START_W0_SCH_IDX GENMASK(3, 0) 3484#define RTW89_H2C_MRC_START_W0_OLD_SCH_IDX GENMASK(7, 4) 3485#define RTW89_H2C_MRC_START_W0_ACTION GENMASK(15, 8) 3486 3487struct rtw89_h2c_mrc_del { 3488 __le32 w0; 3489} __packed; 3490 3491#define RTW89_H2C_MRC_DEL_W0_SCH_IDX GENMASK(3, 0) 3492#define RTW89_H2C_MRC_DEL_W0_DEL_ALL BIT(4) 3493#define RTW89_H2C_MRC_DEL_W0_STOP_ONLY BIT(5) 3494#define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_EN BIT(6) 3495#define RTW89_H2C_MRC_DEL_W0_STOP_SLOT_IDX GENMASK(15, 8) 3496#define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_MACID GENMASK(31, 16) 3497 3498#define RTW89_MAC_MRC_MAX_REQ_TSF_NUM 2 3499 3500struct rtw89_fw_mrc_req_tsf_arg { 3501 unsigned int num; 3502 struct { 3503 u8 band; 3504 u8 port; 3505 } infos[RTW89_MAC_MRC_MAX_REQ_TSF_NUM]; 3506}; 3507 3508struct rtw89_h2c_mrc_req_tsf { 3509 u8 req_tsf_num; 3510 u8 infos[] __counted_by(req_tsf_num); 3511} __packed; 3512 3513#define RTW89_H2C_MRC_REQ_TSF_INFO_BAND GENMASK(3, 0) 3514#define RTW89_H2C_MRC_REQ_TSF_INFO_PORT GENMASK(7, 4) 3515 3516enum rtw89_h2c_mrc_upd_bitmap_actions { 3517 RTW89_H2C_MRC_UPD_BITMAP_ACTION_DEL = 0, 3518 RTW89_H2C_MRC_UPD_BITMAP_ACTION_ADD = 1, 3519}; 3520 3521struct rtw89_fw_mrc_upd_bitmap_arg { 3522 u8 sch_idx; 3523 u8 macid; 3524 u8 client_macid; 3525 enum rtw89_h2c_mrc_upd_bitmap_actions action; 3526}; 3527 3528struct rtw89_h2c_mrc_upd_bitmap { 3529 __le32 w0; 3530 __le32 w1; 3531} __packed; 3532 3533#define RTW89_H2C_MRC_UPD_BITMAP_W0_SCH_IDX GENMASK(3, 0) 3534#define RTW89_H2C_MRC_UPD_BITMAP_W0_ACTION BIT(4) 3535#define RTW89_H2C_MRC_UPD_BITMAP_W0_MACID GENMASK(31, 16) 3536#define RTW89_H2C_MRC_UPD_BITMAP_W1_CLIENT_MACID GENMASK(15, 0) 3537 3538struct rtw89_fw_mrc_sync_arg { 3539 u8 offset; /* unit: TU */ 3540 struct { 3541 u8 band; 3542 u8 port; 3543 } src, dest; 3544}; 3545 3546struct rtw89_h2c_mrc_sync { 3547 __le32 w0; 3548 __le32 w1; 3549} __packed; 3550 3551#define RTW89_H2C_MRC_SYNC_W0_SYNC_EN BIT(0) 3552#define RTW89_H2C_MRC_SYNC_W0_SRC_PORT GENMASK(11, 8) 3553#define RTW89_H2C_MRC_SYNC_W0_SRC_BAND GENMASK(15, 12) 3554#define RTW89_H2C_MRC_SYNC_W0_DEST_PORT GENMASK(19, 16) 3555#define RTW89_H2C_MRC_SYNC_W0_DEST_BAND GENMASK(23, 20) 3556#define RTW89_H2C_MRC_SYNC_W1_OFFSET GENMASK(15, 0) 3557 3558struct rtw89_fw_mrc_upd_duration_arg { 3559 u8 sch_idx; 3560 u64 start_tsf; 3561 3562 unsigned int slot_num; 3563 struct { 3564 u8 slot_idx; 3565 u16 duration; /* unit: TU */ 3566 } slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM]; 3567}; 3568 3569struct rtw89_h2c_mrc_upd_duration { 3570 __le32 w0; 3571 __le32 start_tsf_low; 3572 __le32 start_tsf_high; 3573 __le32 slots[]; 3574} __packed; 3575 3576#define RTW89_H2C_MRC_UPD_DURATION_W0_SCH_IDX GENMASK(3, 0) 3577#define RTW89_H2C_MRC_UPD_DURATION_W0_SLOT_NUM GENMASK(15, 8) 3578#define RTW89_H2C_MRC_UPD_DURATION_W0_BTC_IN_SCH BIT(16) 3579#define RTW89_H2C_MRC_UPD_DURATION_SLOT_SLOT_IDX GENMASK(7, 0) 3580#define RTW89_H2C_MRC_UPD_DURATION_SLOT_DURATION GENMASK(31, 16) 3581 3582struct rtw89_h2c_wow_aoac { 3583 __le32 w0; 3584} __packed; 3585 3586struct rtw89_h2c_ap_info { 3587 __le32 w0; 3588} __packed; 3589 3590#define RTW89_H2C_AP_INFO_W0_PWR_INT_EN BIT(0) 3591 3592#define RTW89_C2H_HEADER_LEN 8 3593 3594struct rtw89_c2h_hdr { 3595 __le32 w0; 3596 __le32 w1; 3597} __packed; 3598 3599#define RTW89_C2H_HDR_W0_CATEGORY GENMASK(1, 0) 3600#define RTW89_C2H_HDR_W0_CLASS GENMASK(7, 2) 3601#define RTW89_C2H_HDR_W0_FUNC GENMASK(15, 8) 3602#define RTW89_C2H_HDR_W1_LEN GENMASK(13, 0) 3603 3604struct rtw89_fw_c2h_attr { 3605 u8 category; 3606 u8 class; 3607 u8 func; 3608 u16 len; 3609 u8 is_scan_event: 1; 3610 u8 scan_seq: 2; 3611}; 3612 3613static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb) 3614{ 3615 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr)); 3616 3617 return (struct rtw89_fw_c2h_attr *)skb->cb; 3618} 3619 3620struct rtw89_c2h_done_ack { 3621 __le32 w0; 3622 __le32 w1; 3623 __le32 w2; 3624} __packed; 3625 3626#define RTW89_C2H_DONE_ACK_W2_CAT GENMASK(1, 0) 3627#define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2) 3628#define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8) 3629#define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16) 3630#define RTW89_C2H_SCAN_DONE_ACK_RETURN GENMASK(5, 0) 3631#define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24) 3632 3633#define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \ 3634 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3635#define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \ 3636 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 3637#define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \ 3638 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3639#define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \ 3640 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 3641 3642struct rtw89_fw_c2h_log_fmt { 3643 __le16 signature; 3644 u8 feature; 3645 u8 syntax; 3646 __le32 fmt_id; 3647 u8 file_num; 3648 __le16 line_num; 3649 u8 argc; 3650 union { 3651 DECLARE_FLEX_ARRAY(u8, raw); 3652 DECLARE_FLEX_ARRAY(__le32, argv); 3653 } __packed u; 3654} __packed; 3655 3656#define RTW89_C2H_FW_FORMATTED_LOG_MIN_LEN 11 3657#define RTW89_C2H_FW_LOG_FEATURE_PARA_INT BIT(2) 3658#define RTW89_C2H_FW_LOG_MAX_PARA_NUM 16 3659#define RTW89_C2H_FW_LOG_SIGNATURE 0xA5A5 3660#define RTW89_C2H_FW_LOG_STR_BUF_SIZE 512 3661 3662struct rtw89_c2h_bcn_upd_done { 3663 struct rtw89_c2h_hdr hdr; 3664 __le32 w2; 3665} __packed; 3666 3667#define RTW89_C2H_BCN_UPD_DONE_W2_PORT GENMASK(2, 0) 3668#define RTW89_C2H_BCN_UPD_DONE_W2_MBSSID GENMASK(6, 3) 3669#define RTW89_C2H_BCN_UPD_DONE_W2_BAND_IDX BIT(7) 3670 3671struct rtw89_c2h_mac_bcnfltr_rpt { 3672 __le32 w0; 3673 __le32 w1; 3674 __le32 w2; 3675} __packed; 3676 3677#define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0) 3678#define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8) 3679#define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10) 3680#define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16) 3681 3682struct rtw89_c2h_ra_rpt { 3683 struct rtw89_c2h_hdr hdr; 3684 __le32 w2; 3685 __le32 w3; 3686} __packed; 3687 3688#define RTW89_C2H_RA_RPT_W2_MACID GENMASK(15, 0) 3689#define RTW89_C2H_RA_RPT_W2_RETRY_RATIO GENMASK(23, 16) 3690#define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31) 3691#define RTW89_C2H_RA_RPT_W3_MCSNSS GENMASK(6, 0) 3692#define RTW89_C2H_RA_RPT_W3_MD_SEL GENMASK(9, 8) 3693#define RTW89_C2H_RA_RPT_W3_GILTF GENMASK(12, 10) 3694#define RTW89_C2H_RA_RPT_W3_BW GENMASK(14, 13) 3695#define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15) 3696#define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16) 3697 3698struct rtw89_c2h_fw_scan_rpt { 3699 struct rtw89_c2h_hdr hdr; 3700 u8 phy_idx; 3701 u8 band; 3702 u8 center_ch; 3703 u8 ofdm_pd_idx; /* in unit of 2 dBm */ 3704#define PD_LOWER_BOUND_BASE 102 3705 s8 cck_pd_idx; 3706 u8 rsvd0; 3707 u8 rsvd1; 3708 u8 rsvd2; 3709} __packed; 3710 3711/* For WiFi 6 chips: 3712 * VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS 3713 * HT-new: [6:5]: NA, [4:0]: MCS 3714 * For WiFi 7 chips (V1): 3715 * HT, VHT, HE, EHT: [7:5]: NSS, [4:0]: MCS 3716 */ 3717#define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4) 3718#define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0) 3719#define RTW89_RA_RATE_MASK_NSS_V1 GENMASK(7, 5) 3720#define RTW89_RA_RATE_MASK_MCS_V1 GENMASK(4, 0) 3721#define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0) 3722#define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \ 3723 FIELD_PREP(GENMASK(2, 0), mcs)) 3724 3725#define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \ 3726 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 3727#define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \ 3728 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8)) 3729#define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \ 3730 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16)) 3731 3732struct rtw89_c2h_scanofld { 3733 __le32 w0; 3734 __le32 w1; 3735 __le32 w2; 3736 __le32 w3; 3737 __le32 w4; 3738 __le32 w5; 3739 __le32 w6; 3740 __le32 w7; 3741 __le32 w8; 3742} __packed; 3743 3744#define RTW89_C2H_SCANOFLD_W2_PRI_CH GENMASK(7, 0) 3745#define RTW89_C2H_SCANOFLD_W2_RSN GENMASK(19, 16) 3746#define RTW89_C2H_SCANOFLD_W2_STATUS GENMASK(23, 20) 3747#define RTW89_C2H_SCANOFLD_W2_PERIOD GENMASK(31, 24) 3748#define RTW89_C2H_SCANOFLD_W5_TX_FAIL GENMASK(3, 0) 3749#define RTW89_C2H_SCANOFLD_W5_AIR_DENSITY GENMASK(7, 4) 3750#define RTW89_C2H_SCANOFLD_W5_BAND GENMASK(25, 24) 3751#define RTW89_C2H_SCANOFLD_W5_MAC_IDX BIT(26) 3752#define RTW89_C2H_SCANOFLD_W6_SW_DEF GENMASK(7, 0) 3753#define RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD GENMASK(15, 8) 3754#define RTW89_C2H_SCANOFLD_W6_FW_DEF GENMASK(23, 16) 3755#define RTW89_C2H_SCANOFLD_W7_REPORT_TSF GENMASK(31, 0) 3756#define RTW89_C2H_SCANOFLD_W8_PERIOD_V1 GENMASK(15, 0) 3757#define RTW89_C2H_SCANOFLD_W8_EXPECT_PERIOD_V1 GENMASK(31, 16) 3758 3759#define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \ 3760 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3761#define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \ 3762 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3763 3764#define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \ 3765 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3766#define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \ 3767 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 3768#define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \ 3769 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3770 3771struct rtw89_c2h_mac_tx_rpt { 3772 struct rtw89_c2h_hdr hdr; 3773 __le32 w2; 3774 __le32 w3; 3775 __le32 w4; 3776 __le32 w5; 3777 __le32 w6; 3778 __le32 w7; 3779} __packed; 3780 3781#define RTW89_C2H_MAC_TX_RPT_W2_TX_STATE GENMASK(7, 6) 3782#define RTW89_C2H_MAC_TX_RPT_W2_SW_DEFINE GENMASK(11, 8) 3783#define RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT GENMASK(13, 8) 3784#define RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT_V1 GENMASK(15, 10) 3785 3786struct rtw89_c2h_mac_tx_rpt_v2 { 3787 struct rtw89_c2h_hdr hdr; 3788 __le32 w2; 3789 __le32 w3; 3790 __le32 w4; 3791 __le32 w5; 3792 __le32 w6; 3793 __le32 w7; 3794 __le32 w8; 3795 __le32 w9; 3796 __le32 w10; 3797 __le32 w11; 3798 __le32 w12; 3799 __le32 w13; 3800 __le32 w14; 3801 __le32 w15; 3802 __le32 w16; 3803 __le32 w17; 3804 __le32 w18; 3805 __le32 w19; 3806} __packed; 3807 3808#define RTW89_C2H_MAC_TX_RPT_W12_TX_STATE_V2 GENMASK(9, 8) 3809#define RTW89_C2H_MAC_TX_RPT_W12_SW_DEFINE_V2 GENMASK(15, 12) 3810#define RTW89_C2H_MAC_TX_RPT_W14_DATA_TX_CNT_V2 GENMASK(15, 10) 3811 3812struct rtw89_mac_mcc_tsf_rpt { 3813 u32 macid_x; 3814 u32 macid_y; 3815 u32 tsf_x_low; 3816 u32 tsf_x_high; 3817 u32 tsf_y_low; 3818 u32 tsf_y_high; 3819}; 3820 3821static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE); 3822 3823#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \ 3824 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 3825#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \ 3826 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3827#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \ 3828 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16)) 3829#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \ 3830 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0)) 3831#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \ 3832 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0)) 3833#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \ 3834 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0)) 3835#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \ 3836 le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0)) 3837 3838#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \ 3839 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0)) 3840#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \ 3841 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6)) 3842#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \ 3843 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3844#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \ 3845 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0)) 3846#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \ 3847 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0)) 3848 3849struct rtw89_c2h_mlo_link_cfg_rpt { 3850 struct rtw89_c2h_hdr hdr; 3851 __le32 w2; 3852} __packed; 3853 3854#define RTW89_C2H_MLO_LINK_CFG_RPT_W2_MACID GENMASK(15, 0) 3855#define RTW89_C2H_MLO_LINK_CFG_RPT_W2_STATUS GENMASK(19, 16) 3856 3857enum rtw89_c2h_mlo_link_status { 3858 RTW89_C2H_MLO_LINK_CFG_IDLE = 0, 3859 RTW89_C2H_MLO_LINK_CFG_DONE = 1, 3860 RTW89_C2H_MLO_LINK_CFG_ISSUE_NULL_FAIL = 2, 3861 RTW89_C2H_MLO_LINK_CFG_TX_NULL_FAIL = 3, 3862 RTW89_C2H_MLO_LINK_CFG_ROLE_NOT_EXIST = 4, 3863 RTW89_C2H_MLO_LINK_CFG_NULL_1_TIMEOUT = 5, 3864 RTW89_C2H_MLO_LINK_CFG_NULL_0_TIMEOUT = 6, 3865 RTW89_C2H_MLO_LINK_CFG_RUNNING = 0xff, 3866}; 3867 3868struct rtw89_mac_mrc_tsf_rpt { 3869 unsigned int num; 3870 u64 tsfs[RTW89_MAC_MRC_MAX_REQ_TSF_NUM]; 3871}; 3872 3873static_assert(sizeof(struct rtw89_mac_mrc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE); 3874 3875struct rtw89_c2h_mrc_tsf_rpt_info { 3876 __le32 tsf_low; 3877 __le32 tsf_high; 3878} __packed; 3879 3880struct rtw89_c2h_mrc_tsf_rpt { 3881 struct rtw89_c2h_hdr hdr; 3882 __le32 w2; 3883 struct rtw89_c2h_mrc_tsf_rpt_info infos[]; 3884} __packed; 3885 3886#define RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM GENMASK(7, 0) 3887 3888struct rtw89_c2h_mrc_status_rpt { 3889 struct rtw89_c2h_hdr hdr; 3890 __le32 w2; 3891 __le32 tsf_low; 3892 __le32 tsf_high; 3893} __packed; 3894 3895#define RTW89_C2H_MRC_STATUS_RPT_W2_STATUS GENMASK(5, 0) 3896#define RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX GENMASK(7, 6) 3897 3898struct rtw89_c2h_pkt_ofld_rsp { 3899 __le32 w0; 3900 __le32 w1; 3901 __le32 w2; 3902} __packed; 3903 3904#define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0) 3905#define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8) 3906#define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16) 3907 3908struct rtw89_c2h_tx_duty_rpt { 3909 struct rtw89_c2h_hdr c2h_hdr; 3910 __le32 w2; 3911} __packed; 3912 3913#define RTW89_C2H_TX_DUTY_RPT_W2_TIMER_ERR GENMASK(2, 0) 3914 3915struct rtw89_c2h_wow_aoac_report { 3916 struct rtw89_c2h_hdr c2h_hdr; 3917 u8 rpt_ver; 3918 u8 sec_type; 3919 u8 key_idx; 3920 u8 pattern_idx; 3921 u8 rekey_ok; 3922 u8 rsvd1[3]; 3923 u8 ptk_tx_iv[8]; 3924 u8 eapol_key_replay_count[8]; 3925 u8 gtk[32]; 3926 u8 ptk_rx_iv[8]; 3927 u8 gtk_rx_iv[4][8]; 3928 __le64 igtk_key_id; 3929 __le64 igtk_ipn; 3930 u8 igtk[32]; 3931 u8 csa_pri_ch; 3932 u8 csa_bw_ch_offset; 3933 u8 csa_ch_band_chsw_failed; 3934 u8 csa_rsvd1; 3935} __packed; 3936 3937#define RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX BIT(0) 3938 3939struct rtw89_c2h_pwr_int_notify { 3940 struct rtw89_c2h_hdr hdr; 3941 __le32 w2; 3942} __packed; 3943 3944#define RTW89_C2H_PWR_INT_NOTIFY_W2_MACID GENMASK(15, 0) 3945#define RTW89_C2H_PWR_INT_NOTIFY_W2_PWR_STATUS BIT(16) 3946 3947struct rtw89_h2c_tx_duty { 3948 __le32 w0; 3949 __le32 w1; 3950} __packed; 3951 3952#define RTW89_H2C_TX_DUTY_W0_PAUSE_INTVL_MASK GENMASK(15, 0) 3953#define RTW89_H2C_TX_DUTY_W0_TX_INTVL_MASK GENMASK(31, 16) 3954#define RTW89_H2C_TX_DUTY_W1_STOP BIT(0) 3955 3956struct rtw89_h2c_bcnfltr { 3957 __le32 w0; 3958} __packed; 3959 3960#define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0) 3961#define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1) 3962#define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2) 3963#define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3) 3964#define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT_H3 GENMASK(7, 5) 3965#define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT_L4 GENMASK(11, 8) 3966#define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12) 3967#define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16) 3968#define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24) 3969 3970struct rtw89_h2c_ofld_rssi { 3971 __le32 w0; 3972 __le32 w1; 3973} __packed; 3974 3975#define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0) 3976#define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8) 3977#define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0) 3978 3979struct rtw89_h2c_ofld { 3980 __le32 w0; 3981} __packed; 3982 3983#define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0) 3984#define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8) 3985#define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18) 3986 3987#define RTW89_MFW_SIG 0xFF 3988 3989struct rtw89_mfw_info { 3990 u8 cv; 3991 u8 type; /* enum rtw89_fw_type */ 3992 u8 mp; 3993 u8 rsvd; 3994 __le32 shift; 3995 __le32 size; 3996 u8 rsvd2[4]; 3997} __packed; 3998 3999struct rtw89_mfw_hdr { 4000 u8 sig; /* RTW89_MFW_SIG */ 4001 u8 fw_nr; 4002 u8 rsvd0[2]; 4003 struct { 4004 u8 major; 4005 u8 minor; 4006 u8 sub; 4007 u8 idx; 4008 } ver; 4009 u8 rsvd1[8]; 4010 struct rtw89_mfw_info info[]; 4011} __packed; 4012 4013struct rtw89_fw_logsuit_hdr { 4014 __le32 rsvd; 4015 __le32 count; 4016 __le32 ids[]; 4017} __packed; 4018 4019#define RTW89_FW_ELEMENT_ALIGN 16 4020 4021enum rtw89_fw_element_id { 4022 RTW89_FW_ELEMENT_ID_BBMCU0 = 0, 4023 RTW89_FW_ELEMENT_ID_BBMCU1 = 1, 4024 RTW89_FW_ELEMENT_ID_BB_REG = 2, 4025 RTW89_FW_ELEMENT_ID_BB_GAIN = 3, 4026 RTW89_FW_ELEMENT_ID_RADIO_A = 4, 4027 RTW89_FW_ELEMENT_ID_RADIO_B = 5, 4028 RTW89_FW_ELEMENT_ID_RADIO_C = 6, 4029 RTW89_FW_ELEMENT_ID_RADIO_D = 7, 4030 RTW89_FW_ELEMENT_ID_RF_NCTL = 8, 4031 RTW89_FW_ELEMENT_ID_TXPWR_BYRATE = 9, 4032 RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ = 10, 4033 RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ = 11, 4034 RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ = 12, 4035 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ = 13, 4036 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ = 14, 4037 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ = 15, 4038 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT = 16, 4039 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU = 17, 4040 RTW89_FW_ELEMENT_ID_TXPWR_TRK = 18, 4041 RTW89_FW_ELEMENT_ID_RFKLOG_FMT = 19, 4042 RTW89_FW_ELEMENT_ID_REGD = 20, 4043 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_2GHZ = 21, 4044 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_5GHZ = 22, 4045 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_6GHZ = 23, 4046 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_2GHZ = 24, 4047 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_5GHZ = 25, 4048 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_6GHZ = 26, 4049 RTW89_FW_ELEMENT_ID_AFE_PWR_SEQ = 27, 4050 RTW89_FW_ELEMENT_ID_DIAG_MAC = 28, 4051 4052 RTW89_FW_ELEMENT_ID_NUM, 4053}; 4054 4055#define BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ \ 4056 (BIT(RTW89_FW_ELEMENT_ID_TXPWR_BYRATE) | \ 4057 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ) | \ 4058 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ) | \ 4059 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ) | \ 4060 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ) | \ 4061 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT) | \ 4062 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU)) 4063 4064#define BITS_OF_RTW89_TXPWR_FW_ELEMENTS \ 4065 (BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ | \ 4066 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ) | \ 4067 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ)) 4068 4069#define RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_NO_6GHZ \ 4070 (BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \ 4071 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \ 4072 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \ 4073 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \ 4074 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \ 4075 BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ) 4076 4077#define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS (BIT(RTW89_FW_ELEMENT_ID_BBMCU0) | \ 4078 BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \ 4079 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \ 4080 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \ 4081 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \ 4082 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \ 4083 BITS_OF_RTW89_TXPWR_FW_ELEMENTS) 4084 4085struct __rtw89_fw_txpwr_element { 4086 u8 rsvd0; 4087 u8 rsvd1; 4088 u8 rfe_type; 4089 u8 ent_sz; 4090 __le32 num_ents; 4091 u8 content[]; 4092} __packed; 4093 4094struct __rtw89_fw_regd_element { 4095 u8 rsvd0; 4096 u8 rsvd1; 4097 u8 rsvd2; 4098 u8 ent_sz; 4099 __le32 num_ents; 4100 u8 content[]; 4101} __packed; 4102 4103enum rtw89_fw_txpwr_trk_type { 4104 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_START = 0, 4105 RTW89_FW_TXPWR_TRK_TYPE_6GB_N = 0, 4106 RTW89_FW_TXPWR_TRK_TYPE_6GB_P = 1, 4107 RTW89_FW_TXPWR_TRK_TYPE_6GA_N = 2, 4108 RTW89_FW_TXPWR_TRK_TYPE_6GA_P = 3, 4109 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_MAX = 3, 4110 4111 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_START = 4, 4112 RTW89_FW_TXPWR_TRK_TYPE_5GB_N = 4, 4113 RTW89_FW_TXPWR_TRK_TYPE_5GB_P = 5, 4114 RTW89_FW_TXPWR_TRK_TYPE_5GA_N = 6, 4115 RTW89_FW_TXPWR_TRK_TYPE_5GA_P = 7, 4116 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_MAX = 7, 4117 4118 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_START = 8, 4119 RTW89_FW_TXPWR_TRK_TYPE_2GB_N = 8, 4120 RTW89_FW_TXPWR_TRK_TYPE_2GB_P = 9, 4121 RTW89_FW_TXPWR_TRK_TYPE_2GA_N = 10, 4122 RTW89_FW_TXPWR_TRK_TYPE_2GA_P = 11, 4123 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N = 12, 4124 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P = 13, 4125 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N = 14, 4126 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P = 15, 4127 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_MAX = 15, 4128 4129 RTW89_FW_TXPWR_TRK_TYPE_NR, 4130}; 4131 4132struct rtw89_fw_txpwr_track_cfg { 4133 const s8 (*delta[RTW89_FW_TXPWR_TRK_TYPE_NR])[DELTA_SWINGIDX_SIZE]; 4134}; 4135 4136#define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_6GHZ \ 4137 (BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_N) | \ 4138 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_P) | \ 4139 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_N) | \ 4140 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_P)) 4141#define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_5GHZ \ 4142 (BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_N) | \ 4143 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_P) | \ 4144 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_N) | \ 4145 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_P)) 4146#define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_2GHZ \ 4147 (BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_N) | \ 4148 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_P) | \ 4149 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_N) | \ 4150 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_P) | \ 4151 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N) | \ 4152 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P) | \ 4153 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N) | \ 4154 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P)) 4155 4156enum rtw89_fw_afe_action { 4157 RTW89_FW_AFE_ACTION_WRITE = 0, 4158 RTW89_FW_AFE_ACTION_DELAY = 1, 4159 RTW89_FW_AFE_ACTION_POLL = 2, 4160}; 4161 4162enum rtw89_fw_afe_cat { 4163 RTW89_FW_AFE_CAT_BB = 0, 4164 RTW89_FW_AFE_CAT_BB1 = 1, 4165 RTW89_FW_AFE_CAT_MAC = 2, 4166 RTW89_FW_AFE_CAT_MAC1 = 3, 4167 RTW89_FW_AFE_CAT_AFEDIG = 4, 4168 RTW89_FW_AFE_CAT_AFEDIG1 = 5, 4169}; 4170 4171enum rtw89_fw_afe_class { 4172 RTW89_FW_AFE_CLASS_P0 = 0, 4173 RTW89_FW_AFE_CLASS_P1 = 1, 4174 RTW89_FW_AFE_CLASS_P2 = 2, 4175 RTW89_FW_AFE_CLASS_P3 = 3, 4176 RTW89_FW_AFE_CLASS_P4 = 4, 4177 RTW89_FW_AFE_CLASS_CMN = 5, 4178}; 4179 4180struct rtw89_fw_element_hdr { 4181 __le32 id; /* enum rtw89_fw_element_id */ 4182 __le32 size; /* exclude header size */ 4183 u8 ver[4]; 4184 __le32 rsvd0; 4185 __le32 rsvd1; 4186 __le32 rsvd2; 4187 union { 4188 struct { 4189 u8 priv[8]; 4190 u8 contents[]; 4191 } __packed common; 4192 struct { 4193 u8 idx; 4194 u8 rsvd[7]; 4195 struct { 4196 __le32 addr; 4197 __le32 data; 4198 } __packed regs[]; 4199 } __packed reg2; 4200 struct { 4201 u8 cv; 4202 u8 priv[7]; 4203 u8 contents[]; 4204 } __packed bbmcu; 4205 struct { 4206 __le32 bitmap; /* bitmap of enum rtw89_fw_txpwr_trk_type */ 4207 __le32 rsvd; 4208 s8 contents[][DELTA_SWINGIDX_SIZE]; 4209 } __packed txpwr_trk; 4210 struct { 4211 u8 nr; 4212 u8 rsvd[3]; 4213 u8 rfk_id; /* enum rtw89_phy_c2h_rfk_log_func */ 4214 u8 rsvd1[3]; 4215 __le16 offset[]; 4216 } __packed rfk_log_fmt; 4217 struct { 4218 u8 rsvd[8]; 4219 struct rtw89_phy_afe_info { 4220 __le32 action; /* enum rtw89_fw_afe_action */ 4221 __le32 cat; /* enum rtw89_fw_afe_cat */ 4222 __le32 class; /* enum rtw89_fw_afe_class */ 4223 __le32 addr; 4224 __le32 mask; 4225 __le32 val; 4226 } __packed infos[]; 4227 } __packed afe; 4228 struct { 4229 __le32 rule_size; 4230 u8 rsvd[4]; 4231 u8 rules_and_msgs[]; 4232 } __packed diag_mac; 4233 struct __rtw89_fw_txpwr_element txpwr; 4234 struct __rtw89_fw_regd_element regd; 4235 } __packed u; 4236} __packed; 4237 4238struct fwcmd_hdr { 4239 __le32 hdr0; 4240 __le32 hdr1; 4241}; 4242 4243union rtw89_compat_fw_hdr { 4244 struct rtw89_mfw_hdr mfw_hdr; 4245 struct rtw89_fw_hdr fw_hdr; 4246}; 4247 4248static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf) 4249{ 4250 const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf; 4251 4252 if (compat->mfw_hdr.sig == RTW89_MFW_SIG) 4253 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr); 4254 else 4255 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr); 4256} 4257 4258static inline void rtw89_fw_get_filename(char *buf, size_t size, 4259 const char *fw_basename, int fw_format) 4260{ 4261 if (fw_format <= 0) 4262 snprintf(buf, size, "%s.bin", fw_basename); 4263 else 4264 snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format); 4265} 4266 4267#define RTW89_H2C_RF_PAGE_SIZE 500 4268#define RTW89_H2C_RF_PAGE_NUM 3 4269struct rtw89_fw_h2c_rf_reg_info { 4270 enum rtw89_rf_path rf_path; 4271 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE]; 4272 u16 curr_idx; 4273}; 4274 4275#define H2C_SEC_CAM_LEN 24 4276 4277#define H2C_HEADER_LEN 8 4278#define H2C_HDR_CAT GENMASK(1, 0) 4279#define H2C_HDR_CLASS GENMASK(7, 2) 4280#define H2C_HDR_FUNC GENMASK(15, 8) 4281#define H2C_HDR_DEL_TYPE GENMASK(19, 16) 4282#define H2C_HDR_H2C_SEQ GENMASK(31, 24) 4283#define H2C_HDR_TOTAL_LEN GENMASK(13, 0) 4284#define H2C_HDR_REC_ACK BIT(14) 4285#define H2C_HDR_DONE_ACK BIT(15) 4286 4287#define FWCMD_TYPE_H2C 0 4288 4289#define H2C_CAT_TEST 0x0 4290 4291/* CLASS 5 - FW STATUS TEST */ 4292#define H2C_CL_FW_STATUS_TEST 0x5 4293#define H2C_FUNC_CPU_EXCEPTION 0x1 4294 4295#define H2C_CAT_MAC 0x1 4296 4297/* CLASS 0 - FW INFO */ 4298#define H2C_CL_FW_INFO 0x0 4299#define H2C_FUNC_LOG_CFG 0x0 4300#define H2C_FUNC_MAC_GENERAL_PKT 0x1 4301 4302/* CLASS 1 - WOW */ 4303#define H2C_CL_MAC_WOW 0x1 4304enum rtw89_wow_h2c_func { 4305 H2C_FUNC_KEEP_ALIVE = 0x0, 4306 H2C_FUNC_DISCONNECT_DETECT = 0x1, 4307 H2C_FUNC_WOW_GLOBAL = 0x2, 4308 H2C_FUNC_GTK_OFLD = 0x3, 4309 H2C_FUNC_ARP_OFLD = 0x4, 4310 H2C_FUNC_NLO = 0x7, 4311 H2C_FUNC_WAKEUP_CTRL = 0x8, 4312 H2C_FUNC_WOW_CAM_UPD = 0xC, 4313 H2C_FUNC_AOAC_REPORT_REQ = 0xD, 4314 4315 NUM_OF_RTW89_WOW_H2C_FUNC, 4316}; 4317 4318#define RTW89_WOW_WAIT_COND(tag, func) \ 4319 ((tag) * NUM_OF_RTW89_WOW_H2C_FUNC + (func)) 4320 4321#define RTW89_WOW_WAIT_COND_AOAC \ 4322 RTW89_WOW_WAIT_COND(0 /* don't care */, H2C_FUNC_AOAC_REPORT_REQ) 4323 4324/* CLASS 2 - PS */ 4325#define H2C_CL_MAC_PS 0x2 4326enum rtw89_ps_h2c_func { 4327 H2C_FUNC_MAC_LPS_PARM = 0x0, 4328 H2C_FUNC_P2P_ACT = 0x1, 4329 H2C_FUNC_IPS_CFG = 0x3, 4330 H2C_FUNC_PS_POWER_LEVEL = 0x7, 4331 H2C_FUNC_TBTT_TUNING = 0xA, 4332 4333 NUM_OF_RTW89_PS_H2C_FUNC, 4334}; 4335 4336#define RTW89_PS_WAIT_COND(tag, func) \ 4337 ((tag) * NUM_OF_RTW89_PS_H2C_FUNC + (func)) 4338 4339#define RTW89_PS_WAIT_COND_IPS_CFG \ 4340 RTW89_PS_WAIT_COND(0 /* don't care */, H2C_FUNC_IPS_CFG) 4341 4342/* CLASS 3 - FW download */ 4343#define H2C_CL_MAC_FWDL 0x3 4344#define H2C_FUNC_MAC_FWHDR_DL 0x0 4345 4346/* CLASS 5 - Frame Exchange */ 4347#define H2C_CL_MAC_FR_EXCHG 0x5 4348#define H2C_FUNC_MAC_CCTLINFO_UD 0x2 4349#define H2C_FUNC_MAC_BCN_UPD 0x5 4350#define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9 4351#define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa 4352#define H2C_FUNC_MAC_DCTLINFO_UD_V2 0xc 4353#define H2C_FUNC_MAC_BCN_UPD_BE 0xd 4354#define H2C_FUNC_MAC_CCTLINFO_UD_G7 0x11 4355 4356/* CLASS 6 - Address CAM */ 4357#define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6 4358#define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0 4359 4360/* CLASS 8 - Media Status Report */ 4361#define H2C_CL_MAC_MEDIA_RPT 0x8 4362#define H2C_FUNC_MAC_JOININFO 0x0 4363#define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4 4364#define H2C_FUNC_NOTIFY_DBCC 0x5 4365 4366/* CLASS 9 - FW offload */ 4367#define H2C_CL_MAC_FW_OFLD 0x9 4368enum rtw89_fw_ofld_h2c_func { 4369 H2C_FUNC_PACKET_OFLD = 0x1, 4370 H2C_FUNC_MAC_MACID_PAUSE = 0x8, 4371 H2C_FUNC_USR_EDCA = 0xF, 4372 H2C_FUNC_TSF32_TOGL = 0x10, 4373 H2C_FUNC_OFLD_CFG = 0x14, 4374 H2C_FUNC_ADD_SCANOFLD_CH = 0x16, 4375 H2C_FUNC_SCANOFLD = 0x17, 4376 H2C_FUNC_TX_DUTY = 0x18, 4377 H2C_FUNC_PKT_DROP = 0x1b, 4378 H2C_FUNC_CFG_BCNFLTR = 0x1e, 4379 H2C_FUNC_OFLD_RSSI = 0x1f, 4380 H2C_FUNC_OFLD_TP = 0x20, 4381 H2C_FUNC_MAC_MACID_PAUSE_SLEEP = 0x28, 4382 H2C_FUNC_SCANOFLD_BE = 0x2c, 4383 4384 NUM_OF_RTW89_FW_OFLD_H2C_FUNC, 4385}; 4386 4387#define RTW89_FW_OFLD_WAIT_COND(tag, func) \ 4388 ((tag) * NUM_OF_RTW89_FW_OFLD_H2C_FUNC + (func)) 4389 4390#define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \ 4391 RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \ 4392 H2C_FUNC_PACKET_OFLD) 4393 4394#define RTW89_SCANOFLD_WAIT_COND_ADD_CH RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_ADD_SCANOFLD_CH) 4395 4396#define RTW89_SCANOFLD_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD) 4397#define RTW89_SCANOFLD_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD) 4398#define RTW89_SCANOFLD_BE_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD_BE) 4399#define RTW89_SCANOFLD_BE_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD_BE) 4400 4401 4402/* CLASS 10 - Security CAM */ 4403#define H2C_CL_MAC_SEC_CAM 0xa 4404#define H2C_FUNC_MAC_SEC_UPD 0x1 4405 4406/* CLASS 12 - BA CAM */ 4407#define H2C_CL_BA_CAM 0xc 4408#define H2C_FUNC_MAC_BA_CAM 0x0 4409#define H2C_FUNC_MAC_BA_CAM_V1 0x1 4410#define H2C_FUNC_MAC_BA_CAM_INIT 0x2 4411 4412/* CLASS 14 - MCC */ 4413#define H2C_CL_MCC 0xe 4414enum rtw89_mcc_h2c_func { 4415 H2C_FUNC_ADD_MCC = 0x0, 4416 H2C_FUNC_START_MCC = 0x1, 4417 H2C_FUNC_STOP_MCC = 0x2, 4418 H2C_FUNC_DEL_MCC_GROUP = 0x3, 4419 H2C_FUNC_RESET_MCC_GROUP = 0x4, 4420 H2C_FUNC_MCC_REQ_TSF = 0x5, 4421 H2C_FUNC_MCC_MACID_BITMAP = 0x6, 4422 H2C_FUNC_MCC_SYNC = 0x7, 4423 H2C_FUNC_MCC_SET_DURATION = 0x8, 4424 4425 NUM_OF_RTW89_MCC_H2C_FUNC, 4426}; 4427 4428#define RTW89_MCC_WAIT_COND(group, func) \ 4429 ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func)) 4430 4431/* CLASS 20 - MLO */ 4432#define H2C_CL_MLO 0x14 4433enum rtw89_mlo_h2c_func { 4434 H2C_FUNC_MLO_TBL_CFG = 0x0, 4435 H2C_FUNC_MLO_STA_CFG = 0x1, 4436 H2C_FUNC_MLO_TTLM = 0x2, 4437 H2C_FUNC_MLO_DM_CFG = 0x3, 4438 H2C_FUNC_MLO_EMLSR_STA_CFG = 0x4, 4439 H2C_FUNC_MLO_MCMLO_RELINK_DROP = 0x5, 4440 H2C_FUNC_MLO_MCMLO_SN_SYNC = 0x6, 4441 H2C_FUNC_MLO_RELINK = 0x7, 4442 H2C_FUNC_MLO_LINK_CFG = 0x8, 4443 H2C_FUNC_MLO_DM_DBG = 0x9, 4444 4445 NUM_OF_RTW89_MLO_H2C_FUNC, 4446}; 4447 4448#define RTW89_MLO_WAIT_COND(macid, func) \ 4449 ((macid) * NUM_OF_RTW89_MLO_H2C_FUNC + (func)) 4450 4451/* CLASS 24 - MRC */ 4452#define H2C_CL_MRC 0x18 4453enum rtw89_mrc_h2c_func { 4454 H2C_FUNC_MRC_REQ_TSF = 0x0, 4455 H2C_FUNC_ADD_MRC = 0x1, 4456 H2C_FUNC_START_MRC = 0x2, 4457 H2C_FUNC_DEL_MRC = 0x3, 4458 H2C_FUNC_MRC_SYNC = 0x4, 4459 H2C_FUNC_MRC_UPD_DURATION = 0x5, 4460 H2C_FUNC_MRC_UPD_BITMAP = 0x6, 4461 4462 NUM_OF_RTW89_MRC_H2C_FUNC, 4463}; 4464 4465/* can consider MRC's sch_idx as MCC's group */ 4466#define RTW89_MRC_WAIT_COND(sch_idx, func) \ 4467 ((sch_idx) * NUM_OF_RTW89_MRC_H2C_FUNC + (func)) 4468 4469#define RTW89_MRC_WAIT_COND_REQ_TSF \ 4470 RTW89_MRC_WAIT_COND(0 /* don't care */, H2C_FUNC_MRC_REQ_TSF) 4471 4472/* CLASS 36 - AP */ 4473#define H2C_CL_AP 0x24 4474#define H2C_FUNC_AP_INFO 0x0 4475 4476#define H2C_CAT_OUTSRC 0x2 4477 4478#define H2C_CL_OUTSRC_RA 0x1 4479#define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0 4480 4481#define H2C_CL_OUTSRC_DM 0x2 4482#define H2C_FUNC_FW_MCC_DIG 0x6 4483#define H2C_FUNC_FW_LPS_CH_INFO 0xb 4484#define H2C_FUNC_FW_LPS_ML_CMN_INFO 0xe 4485 4486#define H2C_CL_OUTSRC_RF_REG_A 0x8 4487#define H2C_CL_OUTSRC_RF_REG_B 0x9 4488#define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa 4489#define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2 4490#define H2C_FUNC_OUTSRC_RF_PS_INFO 0x10 4491#define H2C_CL_OUTSRC_RF_FW_RFK 0xb 4492 4493enum rtw89_rfk_offload_h2c_func { 4494 H2C_FUNC_RFK_TSSI_OFFLOAD = 0x0, 4495 H2C_FUNC_RFK_IQK_OFFLOAD = 0x1, 4496 H2C_FUNC_RFK_DPK_OFFLOAD = 0x3, 4497 H2C_FUNC_RFK_TXGAPK_OFFLOAD = 0x4, 4498 H2C_FUNC_RFK_DACK_OFFLOAD = 0x5, 4499 H2C_FUNC_RFK_RXDCK_OFFLOAD = 0x6, 4500 H2C_FUNC_RFK_PRE_NOTIFY = 0x8, 4501 H2C_FUNC_RFK_TAS_OFFLOAD = 0x9, 4502}; 4503 4504struct rtw89_fw_h2c_rf_get_mccch { 4505 __le32 ch_0_0; 4506 __le32 ch_0_1; 4507 __le32 ch_1_0; 4508 __le32 ch_1_1; 4509 __le32 current_channel; 4510} __packed; 4511 4512struct rtw89_fw_h2c_rf_get_mccch_v0 { 4513 __le32 ch_0; 4514 __le32 ch_1; 4515 __le32 band_0; 4516 __le32 band_1; 4517 __le32 current_channel; 4518 __le32 current_band_type; 4519} __packed; 4520 4521struct rtw89_h2c_mcc_dig { 4522 __le32 w0; 4523 __le32 w1; 4524 __le32 w2; 4525} __packed; 4526 4527#define RTW89_H2C_MCC_DIG_W0_REG_CNT GENMASK(7, 0) 4528#define RTW89_H2C_MCC_DIG_W0_DM_EN BIT(8) 4529#define RTW89_H2C_MCC_DIG_W0_IDX GENMASK(10, 9) 4530#define RTW89_H2C_MCC_DIG_W0_SET BIT(11) 4531#define RTW89_H2C_MCC_DIG_W0_PHY0_EN BIT(12) 4532#define RTW89_H2C_MCC_DIG_W0_PHY1_EN BIT(13) 4533#define RTW89_H2C_MCC_DIG_W0_CENTER_CH GENMASK(23, 16) 4534#define RTW89_H2C_MCC_DIG_W0_BAND_TYPE GENMASK(31, 24) 4535#define RTW89_H2C_MCC_DIG_W1_ADDR_LSB GENMASK(7, 0) 4536#define RTW89_H2C_MCC_DIG_W1_ADDR_MSB GENMASK(15, 8) 4537#define RTW89_H2C_MCC_DIG_W1_BMASK_LSB GENMASK(23, 16) 4538#define RTW89_H2C_MCC_DIG_W1_BMASK_MSB GENMASK(31, 24) 4539#define RTW89_H2C_MCC_DIG_W2_VAL_LSB GENMASK(7, 0) 4540#define RTW89_H2C_MCC_DIG_W2_VAL_MSB GENMASK(15, 8) 4541 4542#define NUM_OF_RTW89_FW_RFK_PATH 2 4543#define NUM_OF_RTW89_FW_RFK_TBL 3 4544 4545struct rtw89_h2c_rf_ps_info { 4546 __le32 rf18[NUM_OF_RTW89_FW_RFK_PATH]; 4547 __le32 mlo_mode; 4548 u8 pri_ch[NUM_OF_RTW89_FW_RFK_PATH]; 4549} __packed; 4550 4551struct rtw89_fw_h2c_rfk_pre_info_common { 4552 struct { 4553 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL]; 4554 __le32 band[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL]; 4555 } __packed dbcc; 4556 4557 __le32 mlo_mode; 4558 struct { 4559 __le32 cur_ch[NUM_OF_RTW89_FW_RFK_PATH]; 4560 __le32 cur_band[NUM_OF_RTW89_FW_RFK_PATH]; 4561 } __packed tbl; 4562 4563 __le32 phy_idx; 4564} __packed; 4565 4566struct rtw89_fw_h2c_rfk_pre_info_v0 { 4567 struct rtw89_fw_h2c_rfk_pre_info_common common; 4568 4569 __le32 cur_band; 4570 __le32 cur_bw; 4571 __le32 cur_center_ch; 4572 4573 __le32 ktbl_sel0; 4574 __le32 ktbl_sel1; 4575 __le32 rfmod0; 4576 __le32 rfmod1; 4577 4578 __le32 mlo_1_1; 4579 __le32 rfe_type; 4580 __le32 drv_mode; 4581 4582 struct { 4583 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH]; 4584 __le32 band[NUM_OF_RTW89_FW_RFK_PATH]; 4585 } __packed mlo; 4586} __packed; 4587 4588struct rtw89_fw_h2c_rfk_pre_info_v1 { 4589 struct rtw89_fw_h2c_rfk_pre_info_common common; 4590 __le32 mlo_1_1; 4591} __packed; 4592 4593struct rtw89_fw_h2c_rfk_pre_info { 4594 struct rtw89_fw_h2c_rfk_pre_info_v1 base_v1; 4595 __le32 cur_bandwidth[NUM_OF_RTW89_FW_RFK_PATH]; 4596} __packed; 4597 4598struct rtw89_h2c_rf_tssi { 4599 __le16 len; 4600 u8 phy; 4601 u8 ch; 4602 u8 bw; 4603 u8 band; 4604 u8 hwtx_en; 4605 u8 cv; 4606 s8 curr_tssi_cck_de[2]; 4607 s8 curr_tssi_cck_de_20m[2]; 4608 s8 curr_tssi_cck_de_40m[2]; 4609 s8 curr_tssi_efuse_cck_de[2]; 4610 s8 curr_tssi_ofdm_de[2]; 4611 s8 curr_tssi_ofdm_de_20m[2]; 4612 s8 curr_tssi_ofdm_de_40m[2]; 4613 s8 curr_tssi_ofdm_de_80m[2]; 4614 s8 curr_tssi_ofdm_de_160m[2]; 4615 s8 curr_tssi_ofdm_de_320m[2]; 4616 s8 curr_tssi_efuse_ofdm_de[2]; 4617 s8 curr_tssi_ofdm_de_diff_20m[2]; 4618 s8 curr_tssi_ofdm_de_diff_80m[2]; 4619 s8 curr_tssi_ofdm_de_diff_160m[2]; 4620 s8 curr_tssi_ofdm_de_diff_320m[2]; 4621 s8 curr_tssi_trim_de[2]; 4622 u8 pg_thermal[2]; 4623 u8 ftable[2][128]; 4624 u8 tssi_mode; 4625 u8 rfe_type; 4626} __packed; 4627 4628struct rtw89_h2c_rf_iqk_v0 { 4629 __le32 phy_idx; 4630 __le32 dbcc; 4631} __packed; 4632 4633struct rtw89_h2c_rf_iqk { 4634 u8 len; 4635 u8 ktype; 4636 u8 phy; 4637 u8 kpath; 4638 u8 band; 4639 u8 bw; 4640 u8 ch; 4641 u8 cv; 4642} __packed; 4643 4644struct rtw89_h2c_rf_dpk { 4645 u8 len; 4646 u8 phy; 4647 u8 dpk_enable; 4648 u8 kpath; 4649 u8 cur_band; 4650 u8 cur_bw; 4651 u8 cur_ch; 4652 u8 dpk_dbg_en; 4653} __packed; 4654 4655struct rtw89_h2c_rf_txgapk { 4656 u8 len; 4657 u8 ktype; 4658 u8 phy; 4659 u8 kpath; 4660 u8 band; 4661 u8 bw; 4662 u8 ch; 4663 u8 cv; 4664} __packed; 4665 4666struct rtw89_h2c_rf_dack { 4667 __le32 len; 4668 __le32 phy; 4669 __le32 type; 4670} __packed; 4671 4672struct rtw89_h2c_rf_rxdck_v0 { 4673 u8 len; 4674 u8 phy; 4675 u8 is_afe; 4676 u8 kpath; 4677 u8 cur_band; 4678 u8 cur_bw; 4679 u8 cur_ch; 4680 u8 rxdck_dbg_en; 4681} __packed; 4682 4683struct rtw89_h2c_rf_tas { 4684 __le32 enable; 4685} __packed; 4686 4687struct rtw89_h2c_rf_rxdck { 4688 struct rtw89_h2c_rf_rxdck_v0 v0; 4689 u8 is_chl_k; 4690} __packed; 4691 4692enum rtw89_rf_log_type { 4693 RTW89_RF_RUN_LOG = 0, 4694 RTW89_RF_RPT_LOG = 1, 4695}; 4696 4697struct rtw89_c2h_rf_log_hdr { 4698 u8 type; /* enum rtw89_rf_log_type */ 4699 __le16 len; 4700 u8 content[]; 4701} __packed; 4702 4703struct rtw89_c2h_rf_run_log { 4704 __le32 fmt_idx; 4705 __le32 arg[4]; 4706} __packed; 4707 4708struct rtw89_c2h_rf_iqk_rpt_log { 4709 bool iqk_tx_fail[2]; 4710 bool iqk_rx_fail[2]; 4711 bool is_iqk_init; 4712 bool is_reload; 4713 bool is_wb_txiqk[2]; 4714 bool is_wb_rxiqk[2]; 4715 bool is_nbiqk; 4716 bool txiqk_en; 4717 bool rxiqk_en; 4718 bool lok_en; 4719 bool iqk_xym_en; 4720 bool iqk_sram_en; 4721 bool iqk_fft_en; 4722 bool is_fw_iqk; 4723 bool is_iqk_enable; 4724 bool iqk_cfir_en; 4725 bool thermal_rek_en; 4726 u8 iqk_band[2]; 4727 u8 iqk_ch[2]; 4728 u8 iqk_bw[2]; 4729 u8 iqk_times; 4730 u8 version; 4731 u8 phy; 4732 u8 fwk_status; 4733 u8 rsvd; 4734 __le32 reload_cnt; 4735 __le32 iqk_fail_cnt; 4736 __le32 lok_idac[2]; 4737 __le32 lok_vbuf[2]; 4738 __le32 rftxgain[2][4]; 4739 __le32 rfrxgain[2][4]; 4740 __le32 tx_xym[2][4]; 4741 __le32 rx_xym[2][4]; 4742} __packed; 4743 4744struct rtw89_c2h_rf_dpk_rpt_log { 4745 u8 ver; 4746 u8 idx[2]; 4747 u8 band[2]; 4748 u8 bw[2]; 4749 u8 ch[2]; 4750 u8 path_ok[2]; 4751 u8 txagc[2]; 4752 u8 ther[2]; 4753 u8 gs[2]; 4754 u8 dc_i[4]; 4755 u8 dc_q[4]; 4756 u8 corr_val[2]; 4757 u8 corr_idx[2]; 4758 u8 is_timeout[2]; 4759 u8 rxbb_ov[2]; 4760 u8 rsvd; 4761} __packed; 4762 4763struct rtw89_c2h_rf_dack_rpt_log { 4764 u8 fwdack_ver; 4765 u8 fwdack_info_ver; 4766 u8 msbk_d[2][2][16]; 4767 u8 dadck_d[2][2]; 4768 u8 cdack_d[2][2][2]; 4769 u8 addck2_hd[2][2][2]; 4770 u8 addck2_ld[2][2][2]; 4771 u8 adgaink_d[2][2]; 4772 u8 biask_hd[2][2]; 4773 u8 biask_ld[2][2]; 4774 u8 addck_timeout; 4775 u8 cdack_timeout; 4776 u8 dadck_timeout; 4777 u8 msbk_timeout; 4778 u8 adgaink_timeout; 4779 u8 wbadcdck_timeout; 4780 u8 drck_timeout; 4781 u8 dack_fail; 4782 u8 wbdck_d[2]; 4783 u8 rck_d; 4784} __packed; 4785 4786struct rtw89_c2h_rf_rxdck_rpt_log { 4787 u8 ver; 4788 u8 band[2]; 4789 u8 bw[2]; 4790 u8 ch[2]; 4791 u8 timeout[2]; 4792} __packed; 4793 4794struct rtw89_c2h_rf_tssi_rpt_log { 4795 s8 alignment_power[2][2][4]; 4796 u8 alignment_power_cw_h[2][2][4]; 4797 u8 alignment_power_cw_l[2][2][4]; 4798 u8 tssi_alimk_state[2][2]; 4799 u8 default_txagc_offset[2][2]; 4800} __packed; 4801 4802struct rtw89_c2h_rf_txgapk_rpt_log { 4803 __le32 r0x8010[2]; 4804 __le32 chk_cnt; 4805 u8 track_d[2][17]; 4806 u8 power_d[2][17]; 4807 u8 is_txgapk_ok; 4808 u8 chk_id; 4809 u8 ver; 4810 u8 rsv1; 4811} __packed; 4812 4813struct rtw89_c2h_rfk_report { 4814 struct rtw89_c2h_hdr hdr; 4815 u8 state; /* enum rtw89_rfk_report_state */ 4816 u8 version; 4817} __packed; 4818 4819struct rtw89_c2h_rf_tas_rpt_log { 4820 __le32 cur_idx; 4821 __le16 txpwr_history[20]; 4822} __packed; 4823 4824struct rtw89_c2h_rf_tas_info { 4825 struct rtw89_c2h_hdr hdr; 4826 struct rtw89_c2h_rf_tas_rpt_log content; 4827} __packed; 4828 4829#define RTW89_FW_RSVD_PLE_SIZE 0x800 4830 4831#define RTW89_FW_BACKTRACE_INFO_SIZE 8 4832#define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \ 4833 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0) 4834 4835#define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */ 4836#define RTW89_FW_BACKTRACE_KEY 0xBACEBACE 4837 4838#define FWDL_WAIT_CNT 400000 4839#define FWDL_WAIT_CNT_USB 3200 4840 4841int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type); 4842int rtw89_fw_recognize(struct rtw89_dev *rtwdev); 4843int rtw89_fw_recognize_elements(struct rtw89_dev *rtwdev); 4844const struct firmware * 4845rtw89_early_fw_feature_recognize(struct device *device, 4846 const struct rtw89_chip_info *chip, 4847 struct rtw89_fw_info *early_fw, 4848 int *used_fw_format); 4849int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type, 4850 bool include_bb); 4851void rtw89_load_firmware_work(struct work_struct *work); 4852void rtw89_unload_firmware(struct rtw89_dev *rtwdev); 4853int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev); 4854int rtw89_fw_log_prepare(struct rtw89_dev *rtwdev); 4855void rtw89_fw_log_dump(struct rtw89_dev *rtwdev, u8 *buf, u32 len); 4856void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4857 u8 type, u8 cat, u8 class, u8 func, 4858 bool rack, bool dack, u32 len); 4859int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, 4860 struct rtw89_vif_link *rtwvif_link, 4861 struct rtw89_sta_link *rtwsta_link); 4862int rtw89_fw_h2c_default_cmac_tbl_g7(struct rtw89_dev *rtwdev, 4863 struct rtw89_vif_link *rtwvif_link, 4864 struct rtw89_sta_link *rtwsta_link); 4865int rtw89_fw_h2c_default_dmac_tbl_v2(struct rtw89_dev *rtwdev, 4866 struct rtw89_vif_link *rtwvif_link, 4867 struct rtw89_sta_link *rtwsta_link); 4868int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, 4869 struct rtw89_vif_link *rtwvif_link, 4870 struct rtw89_sta_link *rtwsta_link); 4871int rtw89_fw_h2c_assoc_cmac_tbl_g7(struct rtw89_dev *rtwdev, 4872 struct rtw89_vif_link *rtwvif_link, 4873 struct rtw89_sta_link *rtwsta_link); 4874int rtw89_fw_h2c_ampdu_cmac_tbl_g7(struct rtw89_dev *rtwdev, 4875 struct rtw89_vif_link *rtwvif_link, 4876 struct rtw89_sta_link *rtwsta_link); 4877int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev, 4878 struct rtw89_sta_link *rtwsta_link); 4879int rtw89_fw_h2c_txtime_cmac_tbl_g7(struct rtw89_dev *rtwdev, 4880 struct rtw89_sta_link *rtwsta_link); 4881int rtw89_fw_h2c_punctured_cmac_tbl_g7(struct rtw89_dev *rtwdev, 4882 struct rtw89_vif_link *rtwvif_link, 4883 u16 punctured); 4884int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev, 4885 struct rtw89_sta_link *rtwsta_link); 4886int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev, 4887 struct rtw89_vif_link *rtwvif_link); 4888int rtw89_fw_h2c_update_beacon_be(struct rtw89_dev *rtwdev, 4889 struct rtw89_vif_link *rtwvif_link); 4890int rtw89_fw_h2c_tbtt_tuning(struct rtw89_dev *rtwdev, 4891 struct rtw89_vif_link *rtwvif_link, u32 offset); 4892int rtw89_fw_h2c_pwr_lvl(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 4893int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif, 4894 struct rtw89_sta_link *rtwsta_link, const u8 *scan_mac_addr, 4895 enum rtw89_upd_mode upd_mode); 4896int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev, 4897 struct rtw89_vif_link *rtwvif_link, 4898 struct rtw89_sta_link *rtwsta_link); 4899int rtw89_fw_h2c_dctl_sec_cam_v2(struct rtw89_dev *rtwdev, 4900 struct rtw89_vif_link *rtwvif_link, 4901 struct rtw89_sta_link *rtwsta_link); 4902void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h); 4903void rtw89_fw_c2h_work(struct wiphy *wiphy, struct wiphy_work *work); 4904void rtw89_fw_c2h_purge_obsoleted_scan_events(struct rtw89_dev *rtwdev); 4905int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev, 4906 struct rtw89_vif_link *rtwvif_link, 4907 struct rtw89_sta_link *rtwsta_link, 4908 enum rtw89_upd_mode upd_mode); 4909int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 4910 struct rtw89_sta_link *rtwsta_link, bool dis_conn); 4911int rtw89_fw_h2c_notify_dbcc(struct rtw89_dev *rtwdev, bool en); 4912int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp, 4913 bool pause); 4914int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 4915 u8 ac, u32 val); 4916int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev); 4917int rtw89_fw_h2c_tx_duty(struct rtw89_dev *rtwdev, u8 lv); 4918int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev, 4919 struct rtw89_vif_link *rtwvif_link, 4920 bool connect); 4921int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev, 4922 struct rtw89_rx_phy_ppdu *phy_ppdu); 4923int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 4924int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi); 4925int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev, u8 type); 4926int rtw89_fw_h2c_cxdrv_init_v7(struct rtw89_dev *rtwdev, u8 type); 4927int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev, u8 type); 4928int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev, u8 type); 4929int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev, u8 type); 4930int rtw89_fw_h2c_cxdrv_role_v7(struct rtw89_dev *rtwdev, u8 type); 4931int rtw89_fw_h2c_cxdrv_role_v8(struct rtw89_dev *rtwdev, u8 type); 4932int rtw89_fw_h2c_cxdrv_osi_info(struct rtw89_dev *rtwdev, u8 type); 4933int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev, u8 type); 4934int rtw89_fw_h2c_cxdrv_ctrl_v7(struct rtw89_dev *rtwdev, u8 type); 4935int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev, u8 type); 4936int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev, u8 type); 4937int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id); 4938int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id, 4939 struct sk_buff *skb_ofld); 4940int rtw89_fw_h2c_scan_offload_ax(struct rtw89_dev *rtwdev, 4941 struct rtw89_scan_option *opt, 4942 struct rtw89_vif_link *vif, 4943 bool wowlan); 4944int rtw89_fw_h2c_scan_offload_be(struct rtw89_dev *rtwdev, 4945 struct rtw89_scan_option *opt, 4946 struct rtw89_vif_link *vif, 4947 bool wowlan); 4948int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev, 4949 struct rtw89_fw_h2c_rf_reg_info *info, 4950 u16 len, u8 page); 4951int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev); 4952int rtw89_fw_h2c_rf_ps_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 4953int rtw89_fw_h2c_rf_pre_ntfy(struct rtw89_dev *rtwdev, 4954 enum rtw89_phy_idx phy_idx); 4955int rtw89_fw_h2c_mcc_dig(struct rtw89_dev *rtwdev, 4956 enum rtw89_chanctx_idx chanctx_idx, 4957 u8 mcc_role_idx, u8 pd_val, bool en); 4958int rtw89_fw_h2c_rf_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, 4959 const struct rtw89_chan *chan, enum rtw89_tssi_mode tssi_mode); 4960int rtw89_fw_h2c_rf_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, 4961 const struct rtw89_chan *chan); 4962int rtw89_fw_h2c_rf_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, 4963 const struct rtw89_chan *chan); 4964int rtw89_fw_h2c_rf_txgapk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, 4965 const struct rtw89_chan *chan); 4966int rtw89_fw_h2c_rf_dack(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, 4967 const struct rtw89_chan *chan); 4968int rtw89_fw_h2c_rf_rxdck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, 4969 const struct rtw89_chan *chan, bool is_chl_k); 4970int rtw89_fw_h2c_rf_tas_trigger(struct rtw89_dev *rtwdev, bool enable); 4971int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, 4972 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, 4973 bool rack, bool dack); 4974int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len); 4975void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev); 4976void __rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev); 4977void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev); 4978int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 4979 u8 macid); 4980void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev, 4981 struct rtw89_vif_link *rtwvif_link, 4982 bool notify_fw); 4983void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw); 4984int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, 4985 struct rtw89_vif_link *rtwvif_link, 4986 struct rtw89_sta_link *rtwsta_link, 4987 bool valid, struct ieee80211_ampdu_params *params); 4988int rtw89_fw_h2c_ba_cam_v1(struct rtw89_dev *rtwdev, 4989 struct rtw89_vif_link *rtwvif_link, 4990 struct rtw89_sta_link *rtwsta_link, 4991 bool valid, struct ieee80211_ampdu_params *params); 4992void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev); 4993int rtw89_fw_h2c_init_ba_cam_users(struct rtw89_dev *rtwdev, u8 users, 4994 u8 offset, u8 mac_idx); 4995 4996int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev, 4997 struct rtw89_lps_parm *lps_param); 4998int rtw89_fw_h2c_lps_ch_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 4999int rtw89_fw_h2c_lps_ml_cmn_info(struct rtw89_dev *rtwdev, 5000 struct rtw89_vif *rtwvif); 5001int rtw89_fw_h2c_fwips(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 5002 bool enable); 5003struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len); 5004struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len); 5005int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev, 5006 struct rtw89_mac_h2c_info *h2c_info, 5007 struct rtw89_mac_c2h_info *c2h_info); 5008int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable); 5009void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev); 5010int rtw89_hw_scan_start(struct rtw89_dev *rtwdev, 5011 struct rtw89_vif_link *rtwvif_link, 5012 struct ieee80211_scan_request *scan_req); 5013void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, 5014 struct rtw89_vif_link *rtwvif_link, 5015 bool aborted); 5016int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, 5017 struct rtw89_vif_link *rtwvif_link, 5018 bool enable); 5019void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, 5020 struct rtw89_vif_link *rtwvif_link); 5021int rtw89_hw_scan_prep_chan_list_ax(struct rtw89_dev *rtwdev, 5022 struct rtw89_vif_link *rtwvif_link); 5023void rtw89_hw_scan_free_chan_list_ax(struct rtw89_dev *rtwdev); 5024int rtw89_hw_scan_add_chan_list_ax(struct rtw89_dev *rtwdev, 5025 struct rtw89_vif_link *rtwvif_link); 5026int rtw89_pno_scan_add_chan_list_ax(struct rtw89_dev *rtwdev, 5027 struct rtw89_vif_link *rtwvif_link); 5028int rtw89_hw_scan_prep_chan_list_be(struct rtw89_dev *rtwdev, 5029 struct rtw89_vif_link *rtwvif_link); 5030void rtw89_hw_scan_free_chan_list_be(struct rtw89_dev *rtwdev); 5031int rtw89_hw_scan_add_chan_list_be(struct rtw89_dev *rtwdev, 5032 struct rtw89_vif_link *rtwvif_link); 5033int rtw89_pno_scan_add_chan_list_be(struct rtw89_dev *rtwdev, 5034 struct rtw89_vif_link *rtwvif_link); 5035int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev); 5036int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev, 5037 const struct rtw89_pkt_drop_params *params); 5038int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev, 5039 struct rtw89_vif_link *rtwvif_link, 5040 struct ieee80211_p2p_noa_desc *desc, 5041 u8 act, u8 noa_id, u8 ctwindow_oppps); 5042int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, 5043 struct rtw89_vif_link *rtwvif_link, 5044 bool en); 5045int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 5046 bool enable); 5047int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev, 5048 struct rtw89_vif_link *rtwvif_link, bool enable); 5049int rtw89_fw_h2c_cfg_pno(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 5050 bool enable); 5051int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 5052 bool enable); 5053int rtw89_fw_h2c_arp_offload(struct rtw89_dev *rtwdev, 5054 struct rtw89_vif_link *rtwvif_link, bool enable); 5055int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev, 5056 struct rtw89_vif_link *rtwvif_link, bool enable); 5057int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 5058 bool enable); 5059int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev, 5060 struct rtw89_vif_link *rtwvif_link, bool enable); 5061int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev, 5062 struct rtw89_wow_cam_info *cam_info); 5063int rtw89_fw_h2c_wow_gtk_ofld(struct rtw89_dev *rtwdev, 5064 struct rtw89_vif_link *rtwvif_link, 5065 bool enable); 5066int rtw89_fw_h2c_wow_request_aoac(struct rtw89_dev *rtwdev); 5067int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev, 5068 const struct rtw89_fw_mcc_add_req *p); 5069int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev, 5070 const struct rtw89_fw_mcc_start_req *p); 5071int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid, 5072 bool prev_groups); 5073int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group, 5074 bool prev_groups); 5075int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group); 5076int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev, 5077 const struct rtw89_fw_mcc_tsf_req *req, 5078 struct rtw89_mac_mcc_tsf_rpt *rpt); 5079int rtw89_fw_h2c_mcc_macid_bitmap(struct rtw89_dev *rtwdev, u8 group, u8 macid, 5080 u8 *bitmap); 5081int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source, 5082 u8 target, u8 offset); 5083int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev, 5084 const struct rtw89_fw_mcc_duration *p); 5085int rtw89_fw_h2c_mrc_add(struct rtw89_dev *rtwdev, 5086 const struct rtw89_fw_mrc_add_arg *arg); 5087int rtw89_fw_h2c_mrc_start(struct rtw89_dev *rtwdev, 5088 const struct rtw89_fw_mrc_start_arg *arg); 5089int rtw89_fw_h2c_mrc_del(struct rtw89_dev *rtwdev, u8 sch_idx, u8 slot_idx); 5090int rtw89_fw_h2c_mrc_req_tsf(struct rtw89_dev *rtwdev, 5091 const struct rtw89_fw_mrc_req_tsf_arg *arg, 5092 struct rtw89_mac_mrc_tsf_rpt *rpt); 5093int rtw89_fw_h2c_mrc_upd_bitmap(struct rtw89_dev *rtwdev, 5094 const struct rtw89_fw_mrc_upd_bitmap_arg *arg); 5095int rtw89_fw_h2c_mrc_sync(struct rtw89_dev *rtwdev, 5096 const struct rtw89_fw_mrc_sync_arg *arg); 5097int rtw89_fw_h2c_mrc_upd_duration(struct rtw89_dev *rtwdev, 5098 const struct rtw89_fw_mrc_upd_duration_arg *arg); 5099int rtw89_fw_h2c_ap_info_refcount(struct rtw89_dev *rtwdev, bool en); 5100int rtw89_fw_h2c_mlo_link_cfg(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 5101 bool enable); 5102 5103static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev) 5104{ 5105 const struct rtw89_chip_info *chip = rtwdev->chip; 5106 5107 if (chip->bacam_ver == RTW89_BACAM_V0_EXT) 5108 rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev); 5109} 5110 5111static inline int rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, 5112 struct rtw89_vif_link *rtwvif_link, 5113 struct rtw89_sta_link *rtwsta_link) 5114{ 5115 const struct rtw89_chip_info *chip = rtwdev->chip; 5116 5117 return chip->ops->h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 5118} 5119 5120static inline int rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev *rtwdev, 5121 struct rtw89_vif_link *rtwvif_link, 5122 struct rtw89_sta_link *rtwsta_link) 5123{ 5124 const struct rtw89_chip_info *chip = rtwdev->chip; 5125 5126 if (chip->ops->h2c_default_dmac_tbl) 5127 return chip->ops->h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 5128 5129 return 0; 5130} 5131 5132static inline int rtw89_chip_h2c_update_beacon(struct rtw89_dev *rtwdev, 5133 struct rtw89_vif_link *rtwvif_link) 5134{ 5135 const struct rtw89_chip_info *chip = rtwdev->chip; 5136 5137 return chip->ops->h2c_update_beacon(rtwdev, rtwvif_link); 5138} 5139 5140static inline int rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, 5141 struct rtw89_vif_link *rtwvif_link, 5142 struct rtw89_sta_link *rtwsta_link) 5143{ 5144 const struct rtw89_chip_info *chip = rtwdev->chip; 5145 5146 return chip->ops->h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 5147} 5148 5149static inline 5150int rtw89_chip_h2c_ampdu_link_cmac_tbl(struct rtw89_dev *rtwdev, 5151 struct rtw89_vif_link *rtwvif_link, 5152 struct rtw89_sta_link *rtwsta_link) 5153{ 5154 const struct rtw89_chip_info *chip = rtwdev->chip; 5155 5156 if (chip->ops->h2c_ampdu_cmac_tbl) 5157 return chip->ops->h2c_ampdu_cmac_tbl(rtwdev, rtwvif_link, 5158 rtwsta_link); 5159 5160 return 0; 5161} 5162 5163static inline int rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev *rtwdev, 5164 struct rtw89_vif *rtwvif, 5165 struct rtw89_sta *rtwsta) 5166{ 5167 struct rtw89_vif_link *rtwvif_link; 5168 struct rtw89_sta_link *rtwsta_link; 5169 unsigned int link_id; 5170 int ret; 5171 5172 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 5173 rtwvif_link = rtwsta_link->rtwvif_link; 5174 ret = rtw89_chip_h2c_ampdu_link_cmac_tbl(rtwdev, rtwvif_link, 5175 rtwsta_link); 5176 if (ret) 5177 return ret; 5178 } 5179 5180 return 0; 5181} 5182 5183static inline 5184int rtw89_chip_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev, 5185 struct rtw89_sta_link *rtwsta_link) 5186{ 5187 const struct rtw89_chip_info *chip = rtwdev->chip; 5188 5189 return chip->ops->h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 5190} 5191 5192static inline 5193int rtw89_chip_h2c_punctured_cmac_tbl(struct rtw89_dev *rtwdev, 5194 struct rtw89_vif_link *rtwvif_link, 5195 u16 punctured) 5196{ 5197 const struct rtw89_chip_info *chip = rtwdev->chip; 5198 5199 if (!chip->ops->h2c_punctured_cmac_tbl) 5200 return 0; 5201 5202 return chip->ops->h2c_punctured_cmac_tbl(rtwdev, rtwvif_link, punctured); 5203} 5204 5205static inline 5206int rtw89_chip_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5207 bool valid, struct ieee80211_ampdu_params *params) 5208{ 5209 const struct rtw89_chip_info *chip = rtwdev->chip; 5210 struct rtw89_vif_link *rtwvif_link; 5211 struct rtw89_sta_link *rtwsta_link; 5212 unsigned int link_id; 5213 int ret; 5214 5215 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 5216 rtwvif_link = rtwsta_link->rtwvif_link; 5217 ret = chip->ops->h2c_ba_cam(rtwdev, rtwvif_link, rtwsta_link, 5218 valid, params); 5219 if (ret) 5220 return ret; 5221 } 5222 5223 return 0; 5224} 5225 5226/* Must consider compatibility; don't insert new in the mid. 5227 * Fill each field's default value in rtw89_regd_entcpy(). 5228 */ 5229struct rtw89_fw_regd_entry { 5230 u8 alpha2_0; 5231 u8 alpha2_1; 5232 u8 rule_2ghz; 5233 u8 rule_5ghz; 5234 u8 rule_6ghz; 5235 __le32 fmap; 5236} __packed; 5237 5238/* must consider compatibility; don't insert new in the mid */ 5239struct rtw89_fw_txpwr_byrate_entry { 5240 u8 band; 5241 u8 nss; 5242 u8 rs; 5243 u8 shf; 5244 u8 len; 5245 __le32 data; 5246 u8 bw; 5247 u8 ofdma; 5248} __packed; 5249 5250/* must consider compatibility; don't insert new in the mid */ 5251struct rtw89_fw_txpwr_lmt_2ghz_entry { 5252 u8 bw; 5253 u8 nt; 5254 u8 rs; 5255 u8 bf; 5256 u8 regd; 5257 u8 ch_idx; 5258 s8 v; 5259} __packed; 5260 5261/* must consider compatibility; don't insert new in the mid */ 5262struct rtw89_fw_txpwr_lmt_5ghz_entry { 5263 u8 bw; 5264 u8 nt; 5265 u8 rs; 5266 u8 bf; 5267 u8 regd; 5268 u8 ch_idx; 5269 s8 v; 5270} __packed; 5271 5272/* must consider compatibility; don't insert new in the mid */ 5273struct rtw89_fw_txpwr_lmt_6ghz_entry { 5274 u8 bw; 5275 u8 nt; 5276 u8 rs; 5277 u8 bf; 5278 u8 regd; 5279 u8 reg_6ghz_power; 5280 u8 ch_idx; 5281 s8 v; 5282} __packed; 5283 5284/* must consider compatibility; don't insert new in the mid */ 5285struct rtw89_fw_txpwr_lmt_ru_2ghz_entry { 5286 u8 ru; 5287 u8 nt; 5288 u8 regd; 5289 u8 ch_idx; 5290 s8 v; 5291} __packed; 5292 5293/* must consider compatibility; don't insert new in the mid */ 5294struct rtw89_fw_txpwr_lmt_ru_5ghz_entry { 5295 u8 ru; 5296 u8 nt; 5297 u8 regd; 5298 u8 ch_idx; 5299 s8 v; 5300} __packed; 5301 5302/* must consider compatibility; don't insert new in the mid */ 5303struct rtw89_fw_txpwr_lmt_ru_6ghz_entry { 5304 u8 ru; 5305 u8 nt; 5306 u8 regd; 5307 u8 reg_6ghz_power; 5308 u8 ch_idx; 5309 s8 v; 5310} __packed; 5311 5312/* must consider compatibility; don't insert new in the mid */ 5313struct rtw89_fw_tx_shape_lmt_entry { 5314 u8 band; 5315 u8 tx_shape_rs; 5316 u8 regd; 5317 u8 v; 5318} __packed; 5319 5320/* must consider compatibility; don't insert new in the mid */ 5321struct rtw89_fw_tx_shape_lmt_ru_entry { 5322 u8 band; 5323 u8 regd; 5324 u8 v; 5325} __packed; 5326 5327const struct rtw89_rfe_parms * 5328rtw89_load_rfe_data_from_fw(struct rtw89_dev *rtwdev, 5329 const struct rtw89_rfe_parms *init); 5330 5331enum rtw89_wow_wakeup_ver { 5332 RTW89_WOW_REASON_V0, 5333 RTW89_WOW_REASON_V1, 5334 RTW89_WOW_REASON_NUM, 5335}; 5336 5337#endif
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