core.h

   1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2/* Copyright(c) 2019-2020  Realtek Corporation
   3 */
   4
   5#ifndef __RTW89_CORE_H__
   6#define __RTW89_CORE_H__
   7
   8#include <linux/average.h>
   9#include <linux/bitfield.h>
  10#include <linux/dmi.h>
  11#include <linux/firmware.h>
  12#include <linux/iopoll.h>
  13#include <linux/workqueue.h>
  14#include <net/mac80211.h>
  15
  16struct rtw89_dev;
  17struct rtw89_pci_info;
  18struct rtw89_usb_info;
  19struct rtw89_mac_gen_def;
  20struct rtw89_phy_gen_def;
  21struct rtw89_fw_blacklist;
  22struct rtw89_efuse_block_cfg;
  23struct rtw89_h2c_rf_tssi;
  24struct rtw89_fw_txpwr_track_cfg;
  25struct rtw89_phy_rfk_log_fmt;
  26struct rtw89_debugfs;
  27struct rtw89_regd_data;
  28
  29extern const struct ieee80211_ops rtw89_ops;
  30
  31#define MASKBYTE0 0xff
  32#define MASKBYTE1 0xff00
  33#define MASKBYTE2 0xff0000
  34#define MASKBYTE3 0xff000000
  35#define MASKBYTE4 0xff00000000ULL
  36#define MASKHWORD 0xffff0000
  37#define MASKLWORD 0x0000ffff
  38#define MASKDWORD 0xffffffff
  39#define RFREG_MASK 0xfffff
  40#define INV_RF_DATA 0xffffffff
  41#define BYPASS_CR_DATA 0xbabecafe
  42#define RTW89_R32_EA 0xEAEAEAEA
  43#define RTW89_R32_DEAD 0xDEADBEEF
  44
  45#define RTW89_TRACK_WORK_PERIOD	round_jiffies_relative(HZ * 2)
  46#define RTW89_TRACK_PS_WORK_PERIOD msecs_to_jiffies(100)
  47#define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4)
  48#define RTW89_PS_HANG_MAX_CNT 3
  49#define CFO_TRACK_MAX_USER 64
  50#define MAX_RSSI 110
  51#define RSSI_FACTOR 1
  52#define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
  53#define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR)
  54#define DELTA_SWINGIDX_SIZE 30
  55
  56#define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he)
  57#define RTW89_RADIOTAP_ROOM_EHT \
  58	(sizeof(struct ieee80211_radiotap_tlv) + \
  59	 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \
  60	 sizeof(struct ieee80211_radiotap_tlv) + \
  61	 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4))
  62#define RTW89_RADIOTAP_ROOM \
  63	ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64)
  64
  65#define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
  66#define RTW89_HTC_VARIANT_HE 3
  67#define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2)
  68#define RTW89_HTC_VARIANT_HE_CID_OM 1
  69#define RTW89_HTC_VARIANT_HE_CID_CAS 6
  70#define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6)
  71
  72#define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6)
  73enum htc_om_channel_width {
  74	HTC_OM_CHANNEL_WIDTH_20 = 0,
  75	HTC_OM_CHANNEL_WIDTH_40 = 1,
  76	HTC_OM_CHANNEL_WIDTH_80 = 2,
  77	HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3,
  78};
  79#define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9)
  80#define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11)
  81#define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12)
  82#define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15)
  83#define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16)
  84#define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17)
  85
  86#define RTW89_TF_PAD GENMASK(11, 0)
  87#define RTW89_TF_BASIC_USER_INFO_SZ 6
  88
  89#define RTW89_GET_TF_USER_INFO_AID12(data)	\
  90	le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0))
  91#define RTW89_GET_TF_USER_INFO_RUA(data)	\
  92	le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12))
  93#define RTW89_GET_TF_USER_INFO_UL_MCS(data)	\
  94	le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21))
  95
  96enum rtw89_subband {
  97	RTW89_CH_2G = 0,
  98	RTW89_CH_5G_BAND_1 = 1,
  99	/* RTW89_CH_5G_BAND_2 = 2, unused */
 100	RTW89_CH_5G_BAND_3 = 3,
 101	RTW89_CH_5G_BAND_4 = 4,
 102
 103	RTW89_CH_6G_BAND_IDX0, /* Low */
 104	RTW89_CH_6G_BAND_IDX1, /* Low */
 105	RTW89_CH_6G_BAND_IDX2, /* Mid */
 106	RTW89_CH_6G_BAND_IDX3, /* Mid */
 107	RTW89_CH_6G_BAND_IDX4, /* High */
 108	RTW89_CH_6G_BAND_IDX5, /* High */
 109	RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
 110	RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
 111
 112	RTW89_SUBBAND_NR,
 113	RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1,
 114};
 115
 116enum rtw89_gain_offset {
 117	RTW89_GAIN_OFFSET_2G_CCK,
 118	RTW89_GAIN_OFFSET_2G_OFDM,
 119	RTW89_GAIN_OFFSET_5G_LOW,
 120	RTW89_GAIN_OFFSET_5G_MID,
 121	RTW89_GAIN_OFFSET_5G_HIGH,
 122	RTW89_GAIN_OFFSET_6G_L0,
 123	RTW89_GAIN_OFFSET_6G_L1,
 124	RTW89_GAIN_OFFSET_6G_M0,
 125	RTW89_GAIN_OFFSET_6G_M1,
 126	RTW89_GAIN_OFFSET_6G_H0,
 127	RTW89_GAIN_OFFSET_6G_H1,
 128	RTW89_GAIN_OFFSET_6G_UH0,
 129	RTW89_GAIN_OFFSET_6G_UH1,
 130
 131	RTW89_GAIN_OFFSET_NR,
 132};
 133
 134enum rtw89_hci_type {
 135	RTW89_HCI_TYPE_PCIE,
 136	RTW89_HCI_TYPE_USB,
 137	RTW89_HCI_TYPE_SDIO,
 138
 139	RTW89_HCI_TYPE_NUM,
 140};
 141
 142enum rtw89_hci_dle_type {
 143	RTW89_HCI_DLE_TYPE_PCIE,
 144	RTW89_HCI_DLE_TYPE_USB2,
 145	RTW89_HCI_DLE_TYPE_USB3,
 146	RTW89_HCI_DLE_TYPE_SDIO,
 147
 148	RTW89_HCI_DLE_TYPE_NUM,
 149};
 150
 151enum rtw89_core_chip_id {
 152	RTL8852A,
 153	RTL8852B,
 154	RTL8852BT,
 155	RTL8852C,
 156	RTL8851B,
 157	RTL8922A,
 158	RTL8922D,
 159};
 160
 161enum rtw89_chip_gen {
 162	RTW89_CHIP_AX,
 163	RTW89_CHIP_BE,
 164
 165	RTW89_CHIP_GEN_NUM,
 166};
 167
 168enum rtw89_cv {
 169	CHIP_CAV,
 170	CHIP_CBV,
 171	CHIP_CCV,
 172	CHIP_CDV,
 173	CHIP_CEV,
 174	CHIP_CFV,
 175	CHIP_CV_MAX,
 176	CHIP_CV_INVALID = CHIP_CV_MAX,
 177};
 178
 179enum rtw89_bacam_ver {
 180	RTW89_BACAM_V0,
 181	RTW89_BACAM_V1,
 182
 183	RTW89_BACAM_V0_EXT = 99,
 184};
 185
 186enum rtw89_core_tx_type {
 187	RTW89_CORE_TX_TYPE_DATA,
 188	RTW89_CORE_TX_TYPE_MGMT,
 189	RTW89_CORE_TX_TYPE_FWCMD,
 190};
 191
 192enum rtw89_core_rx_type {
 193	RTW89_CORE_RX_TYPE_WIFI		= 0,
 194	RTW89_CORE_RX_TYPE_PPDU_STAT	= 1,
 195	RTW89_CORE_RX_TYPE_CHAN_INFO	= 2,
 196	RTW89_CORE_RX_TYPE_BB_SCOPE	= 3,
 197	RTW89_CORE_RX_TYPE_F2P_TXCMD	= 4,
 198	RTW89_CORE_RX_TYPE_SS2FW	= 5,
 199	RTW89_CORE_RX_TYPE_TX_REPORT	= 6,
 200	RTW89_CORE_RX_TYPE_TX_REL_HOST	= 7,
 201	RTW89_CORE_RX_TYPE_DFS_REPORT	= 8,
 202	RTW89_CORE_RX_TYPE_TX_REL_CPU	= 9,
 203	RTW89_CORE_RX_TYPE_C2H		= 10,
 204	RTW89_CORE_RX_TYPE_CSI		= 11,
 205	RTW89_CORE_RX_TYPE_CQI		= 12,
 206	RTW89_CORE_RX_TYPE_H2C		= 13,
 207	RTW89_CORE_RX_TYPE_FWDL		= 14,
 208};
 209
 210enum rtw89_txq_flags {
 211	RTW89_TXQ_F_AMPDU		= 0,
 212	RTW89_TXQ_F_BLOCK_BA		= 1,
 213	RTW89_TXQ_F_FORBID_BA		= 2,
 214};
 215
 216enum rtw89_net_type {
 217	RTW89_NET_TYPE_NO_LINK		= 0,
 218	RTW89_NET_TYPE_AD_HOC		= 1,
 219	RTW89_NET_TYPE_INFRA		= 2,
 220	RTW89_NET_TYPE_AP_MODE		= 3,
 221};
 222
 223enum rtw89_wifi_role {
 224	RTW89_WIFI_ROLE_NONE,
 225	RTW89_WIFI_ROLE_STATION,
 226	RTW89_WIFI_ROLE_AP,
 227	RTW89_WIFI_ROLE_AP_VLAN,
 228	RTW89_WIFI_ROLE_ADHOC,
 229	RTW89_WIFI_ROLE_ADHOC_MASTER,
 230	RTW89_WIFI_ROLE_MESH_POINT,
 231	RTW89_WIFI_ROLE_MONITOR,
 232	RTW89_WIFI_ROLE_P2P_DEVICE,
 233	RTW89_WIFI_ROLE_P2P_CLIENT,
 234	RTW89_WIFI_ROLE_P2P_GO,
 235	RTW89_WIFI_ROLE_NAN,
 236	RTW89_WIFI_ROLE_MLME_MAX
 237};
 238
 239enum rtw89_upd_mode {
 240	RTW89_ROLE_CREATE,
 241	RTW89_ROLE_REMOVE,
 242	RTW89_ROLE_TYPE_CHANGE,
 243	RTW89_ROLE_INFO_CHANGE,
 244	RTW89_ROLE_CON_DISCONN,
 245	RTW89_ROLE_BAND_SW,
 246	RTW89_ROLE_FW_RESTORE,
 247};
 248
 249enum rtw89_self_role {
 250	RTW89_SELF_ROLE_CLIENT,
 251	RTW89_SELF_ROLE_AP,
 252	RTW89_SELF_ROLE_AP_CLIENT
 253};
 254
 255enum rtw89_msk_sO_el {
 256	RTW89_NO_MSK,
 257	RTW89_SMA,
 258	RTW89_TMA,
 259	RTW89_BSSID
 260};
 261
 262enum rtw89_sch_tx_sel {
 263	RTW89_SCH_TX_SEL_ALL,
 264	RTW89_SCH_TX_SEL_HIQ,
 265	RTW89_SCH_TX_SEL_MG0,
 266	RTW89_SCH_TX_SEL_MACID,
 267};
 268
 269/* RTW89_ADDR_CAM_SEC_NONE	: not enabled
 270 * RTW89_ADDR_CAM_SEC_ALL_UNI	: 0 - 6 unicast
 271 * RTW89_ADDR_CAM_SEC_NORMAL	: 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
 272 * RTW89_ADDR_CAM_SEC_4GROUP	: 0 - 1 unicast, 2 - 5 group, 6 BIP
 273 */
 274enum rtw89_add_cam_sec_mode {
 275	RTW89_ADDR_CAM_SEC_NONE		= 0,
 276	RTW89_ADDR_CAM_SEC_ALL_UNI	= 1,
 277	RTW89_ADDR_CAM_SEC_NORMAL	= 2,
 278	RTW89_ADDR_CAM_SEC_4GROUP	= 3,
 279};
 280
 281enum rtw89_sec_key_type {
 282	RTW89_SEC_KEY_TYPE_NONE		= 0,
 283	RTW89_SEC_KEY_TYPE_WEP40	= 1,
 284	RTW89_SEC_KEY_TYPE_WEP104	= 2,
 285	RTW89_SEC_KEY_TYPE_TKIP		= 3,
 286	RTW89_SEC_KEY_TYPE_WAPI		= 4,
 287	RTW89_SEC_KEY_TYPE_GCMSMS4	= 5,
 288	RTW89_SEC_KEY_TYPE_CCMP128	= 6,
 289	RTW89_SEC_KEY_TYPE_CCMP256	= 7,
 290	RTW89_SEC_KEY_TYPE_GCMP128	= 8,
 291	RTW89_SEC_KEY_TYPE_GCMP256	= 9,
 292	RTW89_SEC_KEY_TYPE_BIP_CCMP128	= 10,
 293};
 294
 295enum rtw89_port {
 296	RTW89_PORT_0 = 0,
 297	RTW89_PORT_1 = 1,
 298	RTW89_PORT_2 = 2,
 299	RTW89_PORT_3 = 3,
 300	RTW89_PORT_4 = 4,
 301	RTW89_PORT_NUM
 302};
 303
 304enum rtw89_band {
 305	RTW89_BAND_2G = 0,
 306	RTW89_BAND_5G = 1,
 307	RTW89_BAND_6G = 2,
 308	RTW89_BAND_NUM,
 309};
 310
 311enum rtw89_hw_rate {
 312	RTW89_HW_RATE_CCK1	= 0x0,
 313	RTW89_HW_RATE_CCK2	= 0x1,
 314	RTW89_HW_RATE_CCK5_5	= 0x2,
 315	RTW89_HW_RATE_CCK11	= 0x3,
 316	RTW89_HW_RATE_OFDM6	= 0x4,
 317	RTW89_HW_RATE_OFDM9	= 0x5,
 318	RTW89_HW_RATE_OFDM12	= 0x6,
 319	RTW89_HW_RATE_OFDM18	= 0x7,
 320	RTW89_HW_RATE_OFDM24	= 0x8,
 321	RTW89_HW_RATE_OFDM36	= 0x9,
 322	RTW89_HW_RATE_OFDM48	= 0xA,
 323	RTW89_HW_RATE_OFDM54	= 0xB,
 324	RTW89_HW_RATE_MCS0	= 0x80,
 325	RTW89_HW_RATE_MCS1	= 0x81,
 326	RTW89_HW_RATE_MCS2	= 0x82,
 327	RTW89_HW_RATE_MCS3	= 0x83,
 328	RTW89_HW_RATE_MCS4	= 0x84,
 329	RTW89_HW_RATE_MCS5	= 0x85,
 330	RTW89_HW_RATE_MCS6	= 0x86,
 331	RTW89_HW_RATE_MCS7	= 0x87,
 332	RTW89_HW_RATE_MCS8	= 0x88,
 333	RTW89_HW_RATE_MCS9	= 0x89,
 334	RTW89_HW_RATE_MCS10	= 0x8A,
 335	RTW89_HW_RATE_MCS11	= 0x8B,
 336	RTW89_HW_RATE_MCS12	= 0x8C,
 337	RTW89_HW_RATE_MCS13	= 0x8D,
 338	RTW89_HW_RATE_MCS14	= 0x8E,
 339	RTW89_HW_RATE_MCS15	= 0x8F,
 340	RTW89_HW_RATE_MCS16	= 0x90,
 341	RTW89_HW_RATE_MCS17	= 0x91,
 342	RTW89_HW_RATE_MCS18	= 0x92,
 343	RTW89_HW_RATE_MCS19	= 0x93,
 344	RTW89_HW_RATE_MCS20	= 0x94,
 345	RTW89_HW_RATE_MCS21	= 0x95,
 346	RTW89_HW_RATE_MCS22	= 0x96,
 347	RTW89_HW_RATE_MCS23	= 0x97,
 348	RTW89_HW_RATE_MCS24	= 0x98,
 349	RTW89_HW_RATE_MCS25	= 0x99,
 350	RTW89_HW_RATE_MCS26	= 0x9A,
 351	RTW89_HW_RATE_MCS27	= 0x9B,
 352	RTW89_HW_RATE_MCS28	= 0x9C,
 353	RTW89_HW_RATE_MCS29	= 0x9D,
 354	RTW89_HW_RATE_MCS30	= 0x9E,
 355	RTW89_HW_RATE_MCS31	= 0x9F,
 356	RTW89_HW_RATE_VHT_NSS1_MCS0	= 0x100,
 357	RTW89_HW_RATE_VHT_NSS1_MCS1	= 0x101,
 358	RTW89_HW_RATE_VHT_NSS1_MCS2	= 0x102,
 359	RTW89_HW_RATE_VHT_NSS1_MCS3	= 0x103,
 360	RTW89_HW_RATE_VHT_NSS1_MCS4	= 0x104,
 361	RTW89_HW_RATE_VHT_NSS1_MCS5	= 0x105,
 362	RTW89_HW_RATE_VHT_NSS1_MCS6	= 0x106,
 363	RTW89_HW_RATE_VHT_NSS1_MCS7	= 0x107,
 364	RTW89_HW_RATE_VHT_NSS1_MCS8	= 0x108,
 365	RTW89_HW_RATE_VHT_NSS1_MCS9	= 0x109,
 366	RTW89_HW_RATE_VHT_NSS2_MCS0	= 0x110,
 367	RTW89_HW_RATE_VHT_NSS2_MCS1	= 0x111,
 368	RTW89_HW_RATE_VHT_NSS2_MCS2	= 0x112,
 369	RTW89_HW_RATE_VHT_NSS2_MCS3	= 0x113,
 370	RTW89_HW_RATE_VHT_NSS2_MCS4	= 0x114,
 371	RTW89_HW_RATE_VHT_NSS2_MCS5	= 0x115,
 372	RTW89_HW_RATE_VHT_NSS2_MCS6	= 0x116,
 373	RTW89_HW_RATE_VHT_NSS2_MCS7	= 0x117,
 374	RTW89_HW_RATE_VHT_NSS2_MCS8	= 0x118,
 375	RTW89_HW_RATE_VHT_NSS2_MCS9	= 0x119,
 376	RTW89_HW_RATE_VHT_NSS3_MCS0	= 0x120,
 377	RTW89_HW_RATE_VHT_NSS3_MCS1	= 0x121,
 378	RTW89_HW_RATE_VHT_NSS3_MCS2	= 0x122,
 379	RTW89_HW_RATE_VHT_NSS3_MCS3	= 0x123,
 380	RTW89_HW_RATE_VHT_NSS3_MCS4	= 0x124,
 381	RTW89_HW_RATE_VHT_NSS3_MCS5	= 0x125,
 382	RTW89_HW_RATE_VHT_NSS3_MCS6	= 0x126,
 383	RTW89_HW_RATE_VHT_NSS3_MCS7	= 0x127,
 384	RTW89_HW_RATE_VHT_NSS3_MCS8	= 0x128,
 385	RTW89_HW_RATE_VHT_NSS3_MCS9	= 0x129,
 386	RTW89_HW_RATE_VHT_NSS4_MCS0	= 0x130,
 387	RTW89_HW_RATE_VHT_NSS4_MCS1	= 0x131,
 388	RTW89_HW_RATE_VHT_NSS4_MCS2	= 0x132,
 389	RTW89_HW_RATE_VHT_NSS4_MCS3	= 0x133,
 390	RTW89_HW_RATE_VHT_NSS4_MCS4	= 0x134,
 391	RTW89_HW_RATE_VHT_NSS4_MCS5	= 0x135,
 392	RTW89_HW_RATE_VHT_NSS4_MCS6	= 0x136,
 393	RTW89_HW_RATE_VHT_NSS4_MCS7	= 0x137,
 394	RTW89_HW_RATE_VHT_NSS4_MCS8	= 0x138,
 395	RTW89_HW_RATE_VHT_NSS4_MCS9	= 0x139,
 396	RTW89_HW_RATE_HE_NSS1_MCS0	= 0x180,
 397	RTW89_HW_RATE_HE_NSS1_MCS1	= 0x181,
 398	RTW89_HW_RATE_HE_NSS1_MCS2	= 0x182,
 399	RTW89_HW_RATE_HE_NSS1_MCS3	= 0x183,
 400	RTW89_HW_RATE_HE_NSS1_MCS4	= 0x184,
 401	RTW89_HW_RATE_HE_NSS1_MCS5	= 0x185,
 402	RTW89_HW_RATE_HE_NSS1_MCS6	= 0x186,
 403	RTW89_HW_RATE_HE_NSS1_MCS7	= 0x187,
 404	RTW89_HW_RATE_HE_NSS1_MCS8	= 0x188,
 405	RTW89_HW_RATE_HE_NSS1_MCS9	= 0x189,
 406	RTW89_HW_RATE_HE_NSS1_MCS10	= 0x18A,
 407	RTW89_HW_RATE_HE_NSS1_MCS11	= 0x18B,
 408	RTW89_HW_RATE_HE_NSS2_MCS0	= 0x190,
 409	RTW89_HW_RATE_HE_NSS2_MCS1	= 0x191,
 410	RTW89_HW_RATE_HE_NSS2_MCS2	= 0x192,
 411	RTW89_HW_RATE_HE_NSS2_MCS3	= 0x193,
 412	RTW89_HW_RATE_HE_NSS2_MCS4	= 0x194,
 413	RTW89_HW_RATE_HE_NSS2_MCS5	= 0x195,
 414	RTW89_HW_RATE_HE_NSS2_MCS6	= 0x196,
 415	RTW89_HW_RATE_HE_NSS2_MCS7	= 0x197,
 416	RTW89_HW_RATE_HE_NSS2_MCS8	= 0x198,
 417	RTW89_HW_RATE_HE_NSS2_MCS9	= 0x199,
 418	RTW89_HW_RATE_HE_NSS2_MCS10	= 0x19A,
 419	RTW89_HW_RATE_HE_NSS2_MCS11	= 0x19B,
 420	RTW89_HW_RATE_HE_NSS3_MCS0	= 0x1A0,
 421	RTW89_HW_RATE_HE_NSS3_MCS1	= 0x1A1,
 422	RTW89_HW_RATE_HE_NSS3_MCS2	= 0x1A2,
 423	RTW89_HW_RATE_HE_NSS3_MCS3	= 0x1A3,
 424	RTW89_HW_RATE_HE_NSS3_MCS4	= 0x1A4,
 425	RTW89_HW_RATE_HE_NSS3_MCS5	= 0x1A5,
 426	RTW89_HW_RATE_HE_NSS3_MCS6	= 0x1A6,
 427	RTW89_HW_RATE_HE_NSS3_MCS7	= 0x1A7,
 428	RTW89_HW_RATE_HE_NSS3_MCS8	= 0x1A8,
 429	RTW89_HW_RATE_HE_NSS3_MCS9	= 0x1A9,
 430	RTW89_HW_RATE_HE_NSS3_MCS10	= 0x1AA,
 431	RTW89_HW_RATE_HE_NSS3_MCS11	= 0x1AB,
 432	RTW89_HW_RATE_HE_NSS4_MCS0	= 0x1B0,
 433	RTW89_HW_RATE_HE_NSS4_MCS1	= 0x1B1,
 434	RTW89_HW_RATE_HE_NSS4_MCS2	= 0x1B2,
 435	RTW89_HW_RATE_HE_NSS4_MCS3	= 0x1B3,
 436	RTW89_HW_RATE_HE_NSS4_MCS4	= 0x1B4,
 437	RTW89_HW_RATE_HE_NSS4_MCS5	= 0x1B5,
 438	RTW89_HW_RATE_HE_NSS4_MCS6	= 0x1B6,
 439	RTW89_HW_RATE_HE_NSS4_MCS7	= 0x1B7,
 440	RTW89_HW_RATE_HE_NSS4_MCS8	= 0x1B8,
 441	RTW89_HW_RATE_HE_NSS4_MCS9	= 0x1B9,
 442	RTW89_HW_RATE_HE_NSS4_MCS10	= 0x1BA,
 443	RTW89_HW_RATE_HE_NSS4_MCS11	= 0x1BB,
 444
 445	RTW89_HW_RATE_V1_MCS0		= 0x100,
 446	RTW89_HW_RATE_V1_MCS1		= 0x101,
 447	RTW89_HW_RATE_V1_MCS2		= 0x102,
 448	RTW89_HW_RATE_V1_MCS3		= 0x103,
 449	RTW89_HW_RATE_V1_MCS4		= 0x104,
 450	RTW89_HW_RATE_V1_MCS5		= 0x105,
 451	RTW89_HW_RATE_V1_MCS6		= 0x106,
 452	RTW89_HW_RATE_V1_MCS7		= 0x107,
 453	RTW89_HW_RATE_V1_MCS8		= 0x108,
 454	RTW89_HW_RATE_V1_MCS9		= 0x109,
 455	RTW89_HW_RATE_V1_MCS10		= 0x10A,
 456	RTW89_HW_RATE_V1_MCS11		= 0x10B,
 457	RTW89_HW_RATE_V1_MCS12		= 0x10C,
 458	RTW89_HW_RATE_V1_MCS13		= 0x10D,
 459	RTW89_HW_RATE_V1_MCS14		= 0x10E,
 460	RTW89_HW_RATE_V1_MCS15		= 0x10F,
 461	RTW89_HW_RATE_V1_MCS16		= 0x110,
 462	RTW89_HW_RATE_V1_MCS17		= 0x111,
 463	RTW89_HW_RATE_V1_MCS18		= 0x112,
 464	RTW89_HW_RATE_V1_MCS19		= 0x113,
 465	RTW89_HW_RATE_V1_MCS20		= 0x114,
 466	RTW89_HW_RATE_V1_MCS21		= 0x115,
 467	RTW89_HW_RATE_V1_MCS22		= 0x116,
 468	RTW89_HW_RATE_V1_MCS23		= 0x117,
 469	RTW89_HW_RATE_V1_MCS24		= 0x118,
 470	RTW89_HW_RATE_V1_MCS25		= 0x119,
 471	RTW89_HW_RATE_V1_MCS26		= 0x11A,
 472	RTW89_HW_RATE_V1_MCS27		= 0x11B,
 473	RTW89_HW_RATE_V1_MCS28		= 0x11C,
 474	RTW89_HW_RATE_V1_MCS29		= 0x11D,
 475	RTW89_HW_RATE_V1_MCS30		= 0x11E,
 476	RTW89_HW_RATE_V1_MCS31		= 0x11F,
 477	RTW89_HW_RATE_V1_VHT_NSS1_MCS0	= 0x200,
 478	RTW89_HW_RATE_V1_VHT_NSS1_MCS1	= 0x201,
 479	RTW89_HW_RATE_V1_VHT_NSS1_MCS2	= 0x202,
 480	RTW89_HW_RATE_V1_VHT_NSS1_MCS3	= 0x203,
 481	RTW89_HW_RATE_V1_VHT_NSS1_MCS4	= 0x204,
 482	RTW89_HW_RATE_V1_VHT_NSS1_MCS5	= 0x205,
 483	RTW89_HW_RATE_V1_VHT_NSS1_MCS6	= 0x206,
 484	RTW89_HW_RATE_V1_VHT_NSS1_MCS7	= 0x207,
 485	RTW89_HW_RATE_V1_VHT_NSS1_MCS8	= 0x208,
 486	RTW89_HW_RATE_V1_VHT_NSS1_MCS9	= 0x209,
 487	RTW89_HW_RATE_V1_VHT_NSS1_MCS10	= 0x20A,
 488	RTW89_HW_RATE_V1_VHT_NSS1_MCS11	= 0x20B,
 489	RTW89_HW_RATE_V1_VHT_NSS2_MCS0	= 0x220,
 490	RTW89_HW_RATE_V1_VHT_NSS2_MCS1	= 0x221,
 491	RTW89_HW_RATE_V1_VHT_NSS2_MCS2	= 0x222,
 492	RTW89_HW_RATE_V1_VHT_NSS2_MCS3	= 0x223,
 493	RTW89_HW_RATE_V1_VHT_NSS2_MCS4	= 0x224,
 494	RTW89_HW_RATE_V1_VHT_NSS2_MCS5	= 0x225,
 495	RTW89_HW_RATE_V1_VHT_NSS2_MCS6	= 0x226,
 496	RTW89_HW_RATE_V1_VHT_NSS2_MCS7	= 0x227,
 497	RTW89_HW_RATE_V1_VHT_NSS2_MCS8	= 0x228,
 498	RTW89_HW_RATE_V1_VHT_NSS2_MCS9	= 0x229,
 499	RTW89_HW_RATE_V1_VHT_NSS2_MCS10	= 0x22A,
 500	RTW89_HW_RATE_V1_VHT_NSS2_MCS11	= 0x22B,
 501	RTW89_HW_RATE_V1_VHT_NSS3_MCS0	= 0x240,
 502	RTW89_HW_RATE_V1_VHT_NSS3_MCS1	= 0x241,
 503	RTW89_HW_RATE_V1_VHT_NSS3_MCS2	= 0x242,
 504	RTW89_HW_RATE_V1_VHT_NSS3_MCS3	= 0x243,
 505	RTW89_HW_RATE_V1_VHT_NSS3_MCS4	= 0x244,
 506	RTW89_HW_RATE_V1_VHT_NSS3_MCS5	= 0x245,
 507	RTW89_HW_RATE_V1_VHT_NSS3_MCS6	= 0x246,
 508	RTW89_HW_RATE_V1_VHT_NSS3_MCS7	= 0x247,
 509	RTW89_HW_RATE_V1_VHT_NSS3_MCS8	= 0x248,
 510	RTW89_HW_RATE_V1_VHT_NSS3_MCS9	= 0x249,
 511	RTW89_HW_RATE_V1_VHT_NSS3_MCS10	= 0x24A,
 512	RTW89_HW_RATE_V1_VHT_NSS3_MCS11	= 0x24B,
 513	RTW89_HW_RATE_V1_VHT_NSS4_MCS0	= 0x260,
 514	RTW89_HW_RATE_V1_VHT_NSS4_MCS1	= 0x261,
 515	RTW89_HW_RATE_V1_VHT_NSS4_MCS2	= 0x262,
 516	RTW89_HW_RATE_V1_VHT_NSS4_MCS3	= 0x263,
 517	RTW89_HW_RATE_V1_VHT_NSS4_MCS4	= 0x264,
 518	RTW89_HW_RATE_V1_VHT_NSS4_MCS5	= 0x265,
 519	RTW89_HW_RATE_V1_VHT_NSS4_MCS6	= 0x266,
 520	RTW89_HW_RATE_V1_VHT_NSS4_MCS7	= 0x267,
 521	RTW89_HW_RATE_V1_VHT_NSS4_MCS8	= 0x268,
 522	RTW89_HW_RATE_V1_VHT_NSS4_MCS9	= 0x269,
 523	RTW89_HW_RATE_V1_VHT_NSS4_MCS10	= 0x26A,
 524	RTW89_HW_RATE_V1_VHT_NSS4_MCS11	= 0x26B,
 525	RTW89_HW_RATE_V1_HE_NSS1_MCS0	= 0x300,
 526	RTW89_HW_RATE_V1_HE_NSS1_MCS1	= 0x301,
 527	RTW89_HW_RATE_V1_HE_NSS1_MCS2	= 0x302,
 528	RTW89_HW_RATE_V1_HE_NSS1_MCS3	= 0x303,
 529	RTW89_HW_RATE_V1_HE_NSS1_MCS4	= 0x304,
 530	RTW89_HW_RATE_V1_HE_NSS1_MCS5	= 0x305,
 531	RTW89_HW_RATE_V1_HE_NSS1_MCS6	= 0x306,
 532	RTW89_HW_RATE_V1_HE_NSS1_MCS7	= 0x307,
 533	RTW89_HW_RATE_V1_HE_NSS1_MCS8	= 0x308,
 534	RTW89_HW_RATE_V1_HE_NSS1_MCS9	= 0x309,
 535	RTW89_HW_RATE_V1_HE_NSS1_MCS10	= 0x30A,
 536	RTW89_HW_RATE_V1_HE_NSS1_MCS11	= 0x30B,
 537	RTW89_HW_RATE_V1_HE_NSS2_MCS0	= 0x320,
 538	RTW89_HW_RATE_V1_HE_NSS2_MCS1	= 0x321,
 539	RTW89_HW_RATE_V1_HE_NSS2_MCS2	= 0x322,
 540	RTW89_HW_RATE_V1_HE_NSS2_MCS3	= 0x323,
 541	RTW89_HW_RATE_V1_HE_NSS2_MCS4	= 0x324,
 542	RTW89_HW_RATE_V1_HE_NSS2_MCS5	= 0x325,
 543	RTW89_HW_RATE_V1_HE_NSS2_MCS6	= 0x326,
 544	RTW89_HW_RATE_V1_HE_NSS2_MCS7	= 0x327,
 545	RTW89_HW_RATE_V1_HE_NSS2_MCS8	= 0x328,
 546	RTW89_HW_RATE_V1_HE_NSS2_MCS9	= 0x329,
 547	RTW89_HW_RATE_V1_HE_NSS2_MCS10	= 0x32A,
 548	RTW89_HW_RATE_V1_HE_NSS2_MCS11	= 0x32B,
 549	RTW89_HW_RATE_V1_HE_NSS3_MCS0	= 0x340,
 550	RTW89_HW_RATE_V1_HE_NSS3_MCS1	= 0x341,
 551	RTW89_HW_RATE_V1_HE_NSS3_MCS2	= 0x342,
 552	RTW89_HW_RATE_V1_HE_NSS3_MCS3	= 0x343,
 553	RTW89_HW_RATE_V1_HE_NSS3_MCS4	= 0x344,
 554	RTW89_HW_RATE_V1_HE_NSS3_MCS5	= 0x345,
 555	RTW89_HW_RATE_V1_HE_NSS3_MCS6	= 0x346,
 556	RTW89_HW_RATE_V1_HE_NSS3_MCS7	= 0x347,
 557	RTW89_HW_RATE_V1_HE_NSS3_MCS8	= 0x348,
 558	RTW89_HW_RATE_V1_HE_NSS3_MCS9	= 0x349,
 559	RTW89_HW_RATE_V1_HE_NSS3_MCS10	= 0x34A,
 560	RTW89_HW_RATE_V1_HE_NSS3_MCS11	= 0x34B,
 561	RTW89_HW_RATE_V1_HE_NSS4_MCS0	= 0x360,
 562	RTW89_HW_RATE_V1_HE_NSS4_MCS1	= 0x361,
 563	RTW89_HW_RATE_V1_HE_NSS4_MCS2	= 0x362,
 564	RTW89_HW_RATE_V1_HE_NSS4_MCS3	= 0x363,
 565	RTW89_HW_RATE_V1_HE_NSS4_MCS4	= 0x364,
 566	RTW89_HW_RATE_V1_HE_NSS4_MCS5	= 0x365,
 567	RTW89_HW_RATE_V1_HE_NSS4_MCS6	= 0x366,
 568	RTW89_HW_RATE_V1_HE_NSS4_MCS7	= 0x367,
 569	RTW89_HW_RATE_V1_HE_NSS4_MCS8	= 0x368,
 570	RTW89_HW_RATE_V1_HE_NSS4_MCS9	= 0x369,
 571	RTW89_HW_RATE_V1_HE_NSS4_MCS10	= 0x36A,
 572	RTW89_HW_RATE_V1_HE_NSS4_MCS11	= 0x36B,
 573	RTW89_HW_RATE_V1_EHT_NSS1_MCS0	= 0x400,
 574	RTW89_HW_RATE_V1_EHT_NSS1_MCS1	= 0x401,
 575	RTW89_HW_RATE_V1_EHT_NSS1_MCS2	= 0x402,
 576	RTW89_HW_RATE_V1_EHT_NSS1_MCS3	= 0x403,
 577	RTW89_HW_RATE_V1_EHT_NSS1_MCS4	= 0x404,
 578	RTW89_HW_RATE_V1_EHT_NSS1_MCS5	= 0x405,
 579	RTW89_HW_RATE_V1_EHT_NSS1_MCS6	= 0x406,
 580	RTW89_HW_RATE_V1_EHT_NSS1_MCS7	= 0x407,
 581	RTW89_HW_RATE_V1_EHT_NSS1_MCS8	= 0x408,
 582	RTW89_HW_RATE_V1_EHT_NSS1_MCS9	= 0x409,
 583	RTW89_HW_RATE_V1_EHT_NSS1_MCS10	= 0x40A,
 584	RTW89_HW_RATE_V1_EHT_NSS1_MCS11	= 0x40B,
 585	RTW89_HW_RATE_V1_EHT_NSS1_MCS12	= 0x40C,
 586	RTW89_HW_RATE_V1_EHT_NSS1_MCS13	= 0x40D,
 587	RTW89_HW_RATE_V1_EHT_NSS1_MCS14	= 0x40E,
 588	RTW89_HW_RATE_V1_EHT_NSS1_MCS15	= 0x40F,
 589	RTW89_HW_RATE_V1_EHT_NSS2_MCS0	= 0x420,
 590	RTW89_HW_RATE_V1_EHT_NSS2_MCS1	= 0x421,
 591	RTW89_HW_RATE_V1_EHT_NSS2_MCS2	= 0x422,
 592	RTW89_HW_RATE_V1_EHT_NSS2_MCS3	= 0x423,
 593	RTW89_HW_RATE_V1_EHT_NSS2_MCS4	= 0x424,
 594	RTW89_HW_RATE_V1_EHT_NSS2_MCS5	= 0x425,
 595	RTW89_HW_RATE_V1_EHT_NSS2_MCS6	= 0x426,
 596	RTW89_HW_RATE_V1_EHT_NSS2_MCS7	= 0x427,
 597	RTW89_HW_RATE_V1_EHT_NSS2_MCS8	= 0x428,
 598	RTW89_HW_RATE_V1_EHT_NSS2_MCS9	= 0x429,
 599	RTW89_HW_RATE_V1_EHT_NSS2_MCS10	= 0x42A,
 600	RTW89_HW_RATE_V1_EHT_NSS2_MCS11	= 0x42B,
 601	RTW89_HW_RATE_V1_EHT_NSS2_MCS12	= 0x42C,
 602	RTW89_HW_RATE_V1_EHT_NSS2_MCS13	= 0x42D,
 603	RTW89_HW_RATE_V1_EHT_NSS3_MCS0	= 0x440,
 604	RTW89_HW_RATE_V1_EHT_NSS3_MCS1	= 0x441,
 605	RTW89_HW_RATE_V1_EHT_NSS3_MCS2	= 0x442,
 606	RTW89_HW_RATE_V1_EHT_NSS3_MCS3	= 0x443,
 607	RTW89_HW_RATE_V1_EHT_NSS3_MCS4	= 0x444,
 608	RTW89_HW_RATE_V1_EHT_NSS3_MCS5	= 0x445,
 609	RTW89_HW_RATE_V1_EHT_NSS3_MCS6	= 0x446,
 610	RTW89_HW_RATE_V1_EHT_NSS3_MCS7	= 0x447,
 611	RTW89_HW_RATE_V1_EHT_NSS3_MCS8	= 0x448,
 612	RTW89_HW_RATE_V1_EHT_NSS3_MCS9	= 0x449,
 613	RTW89_HW_RATE_V1_EHT_NSS3_MCS10	= 0x44A,
 614	RTW89_HW_RATE_V1_EHT_NSS3_MCS11	= 0x44B,
 615	RTW89_HW_RATE_V1_EHT_NSS3_MCS12	= 0x44C,
 616	RTW89_HW_RATE_V1_EHT_NSS3_MCS13	= 0x44D,
 617	RTW89_HW_RATE_V1_EHT_NSS4_MCS0	= 0x460,
 618	RTW89_HW_RATE_V1_EHT_NSS4_MCS1	= 0x461,
 619	RTW89_HW_RATE_V1_EHT_NSS4_MCS2	= 0x462,
 620	RTW89_HW_RATE_V1_EHT_NSS4_MCS3	= 0x463,
 621	RTW89_HW_RATE_V1_EHT_NSS4_MCS4	= 0x464,
 622	RTW89_HW_RATE_V1_EHT_NSS4_MCS5	= 0x465,
 623	RTW89_HW_RATE_V1_EHT_NSS4_MCS6	= 0x466,
 624	RTW89_HW_RATE_V1_EHT_NSS4_MCS7	= 0x467,
 625	RTW89_HW_RATE_V1_EHT_NSS4_MCS8	= 0x468,
 626	RTW89_HW_RATE_V1_EHT_NSS4_MCS9	= 0x469,
 627	RTW89_HW_RATE_V1_EHT_NSS4_MCS10	= 0x46A,
 628	RTW89_HW_RATE_V1_EHT_NSS4_MCS11	= 0x46B,
 629	RTW89_HW_RATE_V1_EHT_NSS4_MCS12	= 0x46C,
 630	RTW89_HW_RATE_V1_EHT_NSS4_MCS13	= 0x46D,
 631
 632	RTW89_HW_RATE_NR,
 633	RTW89_HW_RATE_INVAL,
 634
 635	RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),
 636	RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
 637	RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8),
 638	RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0),
 639};
 640
 641/* 2G channels,
 642 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
 643 */
 644#define RTW89_2G_CH_NUM 14
 645
 646/* 5G channels,
 647 * 36, 38, 40, 42, 44, 46, 48, 50,
 648 * 52, 54, 56, 58, 60, 62, 64,
 649 * 100, 102, 104, 106, 108, 110, 112, 114,
 650 * 116, 118, 120, 122, 124, 126, 128, 130,
 651 * 132, 134, 136, 138, 140, 142, 144,
 652 * 149, 151, 153, 155, 157, 159, 161, 163,
 653 * 165, 167, 169, 171, 173, 175, 177
 654 */
 655#define RTW89_5G_CH_NUM 53
 656
 657/* 6G channels,
 658 * 1, 3, 5, 7, 9, 11, 13, 15,
 659 * 17, 19, 21, 23, 25, 27, 29, 33,
 660 * 35, 37, 39, 41, 43, 45, 47, 49,
 661 * 51, 53, 55, 57, 59, 61, 65, 67,
 662 * 69, 71, 73, 75, 77, 79, 81, 83,
 663 * 85, 87, 89, 91, 93, 97, 99, 101,
 664 * 103, 105, 107, 109, 111, 113, 115, 117,
 665 * 119, 121, 123, 125, 129, 131, 133, 135,
 666 * 137, 139, 141, 143, 145, 147, 149, 151,
 667 * 153, 155, 157, 161, 163, 165, 167, 169,
 668 * 171, 173, 175, 177, 179, 181, 183, 185,
 669 * 187, 189, 193, 195, 197, 199, 201, 203,
 670 * 205, 207, 209, 211, 213, 215, 217, 219,
 671 * 221, 225, 227, 229, 231, 233, 235, 237,
 672 * 239, 241, 243, 245, 247, 249, 251, 253,
 673 */
 674#define RTW89_6G_CH_NUM 120
 675
 676enum rtw89_rate_section {
 677	RTW89_RS_CCK,
 678	RTW89_RS_OFDM,
 679	RTW89_RS_MCS, /* for HT/VHT/HE */
 680	RTW89_RS_HEDCM,
 681	RTW89_RS_OFFSET,
 682	RTW89_RS_NUM,
 683	RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
 684	RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1,
 685};
 686
 687enum rtw89_rate_offset_indexes {
 688	RTW89_RATE_OFFSET_HE,
 689	RTW89_RATE_OFFSET_VHT,
 690	RTW89_RATE_OFFSET_HT,
 691	RTW89_RATE_OFFSET_OFDM,
 692	RTW89_RATE_OFFSET_CCK,
 693	RTW89_RATE_OFFSET_DLRU_EHT,
 694	RTW89_RATE_OFFSET_DLRU_HE,
 695	RTW89_RATE_OFFSET_EHT,
 696	__RTW89_RATE_OFFSET_NUM,
 697
 698	RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1,
 699	RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1,
 700};
 701
 702enum rtw89_rate_num {
 703	RTW89_RATE_CCK_NUM	= 4,
 704	RTW89_RATE_OFDM_NUM	= 8,
 705	RTW89_RATE_HEDCM_NUM	= 4, /* for HEDCM MCS0/1/3/4 */
 706
 707	RTW89_RATE_MCS_NUM_AX	= 12,
 708	RTW89_RATE_MCS_NUM_BE	= 16,
 709	__RTW89_RATE_MCS_NUM	= 16,
 710};
 711
 712enum rtw89_nss {
 713	RTW89_NSS_1		= 0,
 714	RTW89_NSS_2		= 1,
 715	/* HE DCM only support 1ss and 2ss */
 716	RTW89_NSS_HEDCM_NUM	= RTW89_NSS_2 + 1,
 717	RTW89_NSS_3		= 2,
 718	RTW89_NSS_4		= 3,
 719	RTW89_NSS_NUM,
 720};
 721
 722enum rtw89_ntx {
 723	RTW89_1TX	= 0,
 724	RTW89_2TX	= 1,
 725	RTW89_NTX_NUM,
 726};
 727
 728enum rtw89_beamforming_type {
 729	RTW89_NONBF	= 0,
 730	RTW89_BF	= 1,
 731	RTW89_BF_NUM,
 732};
 733
 734enum rtw89_ofdma_type {
 735	RTW89_NON_OFDMA	= 0,
 736	RTW89_OFDMA	= 1,
 737	RTW89_OFDMA_NUM,
 738};
 739
 740/* neither insert new in the middle, nor change any given definition */
 741enum rtw89_regulation_type {
 742	RTW89_WW	= 0,
 743	RTW89_ETSI	= 1,
 744	RTW89_FCC	= 2,
 745	RTW89_MKK	= 3,
 746	RTW89_NA	= 4,
 747	RTW89_IC	= 5,
 748	RTW89_KCC	= 6,
 749	RTW89_ACMA	= 7,
 750	RTW89_NCC	= 8,
 751	RTW89_MEXICO	= 9,
 752	RTW89_CHILE	= 10,
 753	RTW89_UKRAINE	= 11,
 754	RTW89_CN	= 12,
 755	RTW89_QATAR	= 13,
 756	RTW89_UK	= 14,
 757	RTW89_THAILAND	= 15,
 758	RTW89_REGD_NUM,
 759};
 760
 761enum rtw89_reg_6ghz_power {
 762	RTW89_REG_6GHZ_POWER_VLP = 0,
 763	RTW89_REG_6GHZ_POWER_LPI = 1,
 764	RTW89_REG_6GHZ_POWER_STD = 2,
 765
 766	NUM_OF_RTW89_REG_6GHZ_POWER,
 767	RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP,
 768};
 769
 770#define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */
 771
 772/* calculate based on ieee80211 Transmit Power Envelope */
 773struct rtw89_reg_6ghz_tpe {
 774	bool valid;
 775	s8 constraint; /* unit: dBm */
 776};
 777
 778enum rtw89_fw_pkt_ofld_type {
 779	RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
 780	RTW89_PKT_OFLD_TYPE_PS_POLL = 1,
 781	RTW89_PKT_OFLD_TYPE_NULL_DATA = 2,
 782	RTW89_PKT_OFLD_TYPE_QOS_NULL = 3,
 783	RTW89_PKT_OFLD_TYPE_CTS2SELF = 4,
 784	RTW89_PKT_OFLD_TYPE_ARP_RSP = 5,
 785	RTW89_PKT_OFLD_TYPE_NDP = 6,
 786	RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7,
 787	RTW89_PKT_OFLD_TYPE_SA_QUERY = 8,
 788	RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12,
 789	RTW89_PKT_OFLD_TYPE_NUM,
 790};
 791
 792struct rtw89_txpwr_byrate {
 793	s8 cck[RTW89_RATE_CCK_NUM];
 794	s8 ofdm[RTW89_RATE_OFDM_NUM];
 795	s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM];
 796	s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM];
 797	s8 offset[__RTW89_RATE_OFFSET_NUM];
 798	s8 trap;
 799};
 800
 801struct rtw89_rate_desc {
 802	enum rtw89_nss nss;
 803	enum rtw89_rate_section rs;
 804	enum rtw89_ofdma_type ofdma;
 805	u8 idx;
 806};
 807
 808#define PHY_STS_HDR_LEN 8
 809#define RF_PATH_MAX 4
 810#define RTW89_MAX_PPDU_CNT 8
 811struct rtw89_rx_phy_ppdu {
 812	void *buf;
 813	u32 len;
 814	u8 rssi_avg;
 815	u8 rssi[RF_PATH_MAX];
 816	u8 mac_id;
 817	u8 chan_idx;
 818	u8 phy_idx;
 819	u8 ie;
 820	u16 rate;
 821	u8 rpl_avg;
 822	u8 rpl_path[RF_PATH_MAX];
 823	u8 rpl_fd[RF_PATH_MAX];
 824	u8 bw_idx;
 825	u8 rx_path_en;
 826	struct {
 827		bool has;
 828		u8 avg_snr;
 829		u8 evm_max;
 830		u8 evm_min;
 831	} ofdm;
 832	bool has_data;
 833	bool has_bcn;
 834	bool ldpc;
 835	bool stbc;
 836	bool to_self;
 837	bool valid;
 838	bool hdr_2_en;
 839};
 840
 841enum rtw89_mac_idx {
 842	RTW89_MAC_0 = 0,
 843	RTW89_MAC_1 = 1,
 844	RTW89_MAC_NUM,
 845};
 846
 847enum rtw89_phy_idx {
 848	RTW89_PHY_0 = 0,
 849	RTW89_PHY_1 = 1,
 850	RTW89_PHY_NUM,
 851};
 852
 853#define __RTW89_MLD_MAX_LINK_NUM 2
 854#define RTW89_MLD_NON_STA_LINK_NUM 1
 855
 856enum rtw89_chanctx_idx {
 857	RTW89_CHANCTX_0 = 0,
 858	RTW89_CHANCTX_1 = 1,
 859
 860	NUM_OF_RTW89_CHANCTX,
 861	RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX,
 862};
 863
 864enum rtw89_rf_path {
 865	RF_PATH_A = 0,
 866	RF_PATH_B = 1,
 867	RF_PATH_C = 2,
 868	RF_PATH_D = 3,
 869	RF_PATH_AB,
 870	RF_PATH_AC,
 871	RF_PATH_AD,
 872	RF_PATH_BC,
 873	RF_PATH_BD,
 874	RF_PATH_CD,
 875	RF_PATH_ABC,
 876	RF_PATH_ABD,
 877	RF_PATH_ACD,
 878	RF_PATH_BCD,
 879	RF_PATH_ABCD,
 880};
 881
 882enum rtw89_rf_path_bit {
 883	RF_A	= BIT(0),
 884	RF_B	= BIT(1),
 885	RF_C	= BIT(2),
 886	RF_D	= BIT(3),
 887
 888	RF_AB	= (RF_A | RF_B),
 889	RF_AC	= (RF_A | RF_C),
 890	RF_AD	= (RF_A | RF_D),
 891	RF_BC	= (RF_B | RF_C),
 892	RF_BD	= (RF_B | RF_D),
 893	RF_CD	= (RF_C | RF_D),
 894
 895	RF_ABC	= (RF_A | RF_B | RF_C),
 896	RF_ABD	= (RF_A | RF_B | RF_D),
 897	RF_ACD	= (RF_A | RF_C | RF_D),
 898	RF_BCD	= (RF_B | RF_C | RF_D),
 899
 900	RF_ABCD	= (RF_A | RF_B | RF_C | RF_D),
 901};
 902
 903enum rtw89_bandwidth {
 904	RTW89_CHANNEL_WIDTH_20	= 0,
 905	RTW89_CHANNEL_WIDTH_40	= 1,
 906	RTW89_CHANNEL_WIDTH_80	= 2,
 907	RTW89_CHANNEL_WIDTH_160	= 3,
 908	RTW89_CHANNEL_WIDTH_320	= 4,
 909
 910	/* keep index order above */
 911	RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5,
 912
 913	RTW89_CHANNEL_WIDTH_80_80 = 5,
 914	RTW89_CHANNEL_WIDTH_5 = 6,
 915	RTW89_CHANNEL_WIDTH_10 = 7,
 916};
 917
 918enum rtw89_ps_mode {
 919	RTW89_PS_MODE_NONE	= 0,
 920	RTW89_PS_MODE_RFOFF	= 1,
 921	RTW89_PS_MODE_CLK_GATED	= 2,
 922	RTW89_PS_MODE_PWR_GATED	= 3,
 923};
 924
 925#define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
 926#define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
 927#define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
 928#define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
 929#define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
 930
 931enum rtw89_pe_duration {
 932	RTW89_PE_DURATION_0 = 0,
 933	RTW89_PE_DURATION_8 = 1,
 934	RTW89_PE_DURATION_16 = 2,
 935	RTW89_PE_DURATION_16_20 = 3,
 936};
 937
 938enum rtw89_ru_bandwidth {
 939	RTW89_RU26 = 0,
 940	RTW89_RU52 = 1,
 941	RTW89_RU106 = 2,
 942	RTW89_RU52_26 = 3,
 943	RTW89_RU106_26 = 4,
 944	RTW89_RU_NUM,
 945};
 946
 947enum rtw89_sc_offset {
 948	RTW89_SC_DONT_CARE	= 0,
 949	RTW89_SC_20_UPPER	= 1,
 950	RTW89_SC_20_LOWER	= 2,
 951	RTW89_SC_20_UPMOST	= 3,
 952	RTW89_SC_20_LOWEST	= 4,
 953	RTW89_SC_20_UP2X	= 5,
 954	RTW89_SC_20_LOW2X	= 6,
 955	RTW89_SC_20_UP3X	= 7,
 956	RTW89_SC_20_LOW3X	= 8,
 957	RTW89_SC_40_UPPER	= 9,
 958	RTW89_SC_40_LOWER	= 10,
 959};
 960
 961/* only mgd features can be added to the enum */
 962enum rtw89_wow_flags {
 963	RTW89_WOW_FLAG_EN_MAGIC_PKT,
 964	RTW89_WOW_FLAG_EN_REKEY_PKT,
 965	RTW89_WOW_FLAG_EN_DISCONNECT,
 966	RTW89_WOW_FLAG_EN_PATTERN,
 967	RTW89_WOW_FLAG_NUM,
 968};
 969
 970struct rtw89_chan {
 971	u8 channel;
 972	u8 primary_channel;
 973	enum rtw89_band band_type;
 974	enum rtw89_bandwidth band_width;
 975
 976	/* The follow-up are derived from the above. We must ensure that it
 977	 * is assigned correctly in rtw89_chan_create() if new one is added.
 978	 */
 979	u32 freq;
 980	enum rtw89_subband subband_type;
 981	enum rtw89_sc_offset pri_ch_idx;
 982	u8 pri_sb_idx;
 983};
 984
 985struct rtw89_chan_rcd {
 986	u8 prev_primary_channel;
 987	enum rtw89_band prev_band_type;
 988	bool band_changed;
 989};
 990
 991struct rtw89_channel_help_params {
 992	u32 tx_en;
 993};
 994
 995struct rtw89_port_reg {
 996	u32 port_cfg;
 997	u32 tbtt_prohib;
 998	u32 bcn_area;
 999	u32 bcn_early;
1000	u32 tbtt_early;
1001	u32 tbtt_agg;
1002	u32 bcn_space;
1003	u32 bcn_forcetx;
1004	u32 bcn_err_cnt;
1005	u32 bcn_err_flag;
1006	u32 dtim_ctrl;
1007	u32 tbtt_shift;
1008	u32 bcn_cnt_tmr;
1009	u32 tsftr_l;
1010	u32 tsftr_h;
1011	u32 md_tsft;
1012	u32 bss_color;
1013	u32 mbssid;
1014	u32 mbssid_drop;
1015	u32 tsf_sync;
1016	u32 ptcl_dbg;
1017	u32 ptcl_dbg_info;
1018	u32 bcn_drop_all;
1019	u32 bcn_psr_rpt;
1020	u32 hiq_win[RTW89_PORT_NUM];
1021};
1022
1023struct rtw89_txwd_body {
1024	__le32 dword0;
1025	__le32 dword1;
1026	__le32 dword2;
1027	__le32 dword3;
1028	__le32 dword4;
1029	__le32 dword5;
1030} __packed;
1031
1032struct rtw89_txwd_body_v1 {
1033	__le32 dword0;
1034	__le32 dword1;
1035	__le32 dword2;
1036	__le32 dword3;
1037	__le32 dword4;
1038	__le32 dword5;
1039	__le32 dword6;
1040	__le32 dword7;
1041} __packed;
1042
1043struct rtw89_txwd_body_v2 {
1044	__le32 dword0;
1045	__le32 dword1;
1046	__le32 dword2;
1047	__le32 dword3;
1048	__le32 dword4;
1049	__le32 dword5;
1050	__le32 dword6;
1051	__le32 dword7;
1052} __packed;
1053
1054struct rtw89_txwd_info {
1055	__le32 dword0;
1056	__le32 dword1;
1057	__le32 dword2;
1058	__le32 dword3;
1059	__le32 dword4;
1060	__le32 dword5;
1061} __packed;
1062
1063struct rtw89_txwd_info_v2 {
1064	__le32 dword0;
1065	__le32 dword1;
1066	__le32 dword2;
1067	__le32 dword3;
1068	__le32 dword4;
1069	__le32 dword5;
1070	__le32 dword6;
1071	__le32 dword7;
1072} __packed;
1073
1074struct rtw89_rx_desc_info {
1075	u16 pkt_size;
1076	u8 pkt_type;
1077	u8 drv_info_size;
1078	u8 phy_rpt_size;
1079	u8 hdr_cnv_size;
1080	u8 shift;
1081	u8 wl_hd_iv_len;
1082	bool long_rxdesc;
1083	bool bb_sel;
1084	bool mac_info_valid;
1085	u16 data_rate;
1086	u8 gi_ltf;
1087	u8 bw;
1088	u32 free_run_cnt;
1089	u8 user_id;
1090	bool sr_en;
1091	u8 ppdu_cnt;
1092	u8 ppdu_type;
1093	bool icv_err;
1094	bool crc32_err;
1095	bool hw_dec;
1096	bool sw_dec;
1097	bool addr1_match;
1098	u8 frag;
1099	u16 seq;
1100	u8 frame_type;
1101	u8 rx_pl_id;
1102	bool addr_cam_valid;
1103	u8 addr_cam_id;
1104	u8 sec_cam_id;
1105	u8 mac_id;
1106	u16 offset;
1107	u16 rxd_len;
1108	bool ready;
1109	u16 rssi;
1110};
1111
1112struct rtw89_rxdesc_short {
1113	__le32 dword0;
1114	__le32 dword1;
1115	__le32 dword2;
1116	__le32 dword3;
1117} __packed;
1118
1119struct rtw89_rxdesc_short_v2 {
1120	__le32 dword0;
1121	__le32 dword1;
1122	__le32 dword2;
1123	__le32 dword3;
1124	__le32 dword4;
1125	__le32 dword5;
1126} __packed;
1127
1128struct rtw89_rxdesc_long {
1129	__le32 dword0;
1130	__le32 dword1;
1131	__le32 dword2;
1132	__le32 dword3;
1133	__le32 dword4;
1134	__le32 dword5;
1135	__le32 dword6;
1136	__le32 dword7;
1137} __packed;
1138
1139struct rtw89_rxdesc_long_v2 {
1140	__le32 dword0;
1141	__le32 dword1;
1142	__le32 dword2;
1143	__le32 dword3;
1144	__le32 dword4;
1145	__le32 dword5;
1146	__le32 dword6;
1147	__le32 dword7;
1148	__le32 dword8;
1149	__le32 dword9;
1150} __packed;
1151
1152struct rtw89_rxdesc_phy_rpt_v2 {
1153	__le32 dword0;
1154	__le32 dword1;
1155} __packed;
1156
1157struct rtw89_tx_desc_info {
1158	u16 pkt_size;
1159	u8 wp_offset;
1160	u8 mac_id;
1161	u8 qsel;
1162	u8 ch_dma;
1163	u8 hdr_llc_len;
1164	bool is_bmc;
1165	bool en_wd_info;
1166	bool wd_page;
1167	bool use_rate;
1168	bool dis_data_fb;
1169	bool tid_indicate;
1170	bool agg_en;
1171	bool bk;
1172	u8 ampdu_density;
1173	u8 ampdu_num;
1174	bool sec_en;
1175	bool report;
1176	bool tx_cnt_lmt_en;
1177	u8 sn: 4;
1178	u8 tx_cnt_lmt: 6;
1179	u8 addr_info_nr;
1180	u8 sec_keyid;
1181	u8 sec_type;
1182	u8 sec_cam_idx;
1183	u8 sec_seq[6];
1184	u16 data_rate;
1185	u16 data_retry_lowest_rate;
1186	u8 data_bw;
1187	u8 gi_ltf;
1188	bool fw_dl;
1189	u16 seq;
1190	bool a_ctrl_bsr;
1191	u8 hw_ssn_sel;
1192#define RTW89_MGMT_HW_SSN_SEL	1
1193	u8 hw_seq_mode;
1194#define RTW89_MGMT_HW_SEQ_MODE	1
1195	bool hiq;
1196	u8 port;
1197	bool er_cap;
1198	bool stbc;
1199	bool ldpc;
1200	bool upd_wlan_hdr;
1201	bool mlo;
1202	bool sw_mld;
1203};
1204
1205struct rtw89_core_tx_request {
1206	enum rtw89_core_tx_type tx_type;
1207
1208	struct sk_buff *skb;
1209	struct ieee80211_vif *vif;
1210	struct ieee80211_sta *sta;
1211	struct rtw89_vif_link *rtwvif_link;
1212	struct rtw89_sta_link *rtwsta_link;
1213	struct rtw89_tx_desc_info desc_info;
1214
1215	bool with_wait;
1216};
1217
1218struct rtw89_txq {
1219	struct list_head list;
1220	unsigned long flags;
1221	int wait_cnt;
1222};
1223
1224struct rtw89_mac_ax_gnt {
1225	u8 gnt_bt_sw_en;
1226	u8 gnt_bt;
1227	u8 gnt_wl_sw_en;
1228	u8 gnt_wl;
1229} __packed;
1230
1231struct rtw89_mac_ax_wl_act {
1232	u8 wlan_act_en;
1233	u8 wlan_act;
1234} __packed;
1235
1236#define RTW89_MAC_AX_COEX_GNT_NR 2
1237struct rtw89_mac_ax_coex_gnt {
1238	struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR];
1239	struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR];
1240};
1241
1242enum rtw89_btc_ncnt {
1243	BTC_NCNT_POWER_ON = 0x0,
1244	BTC_NCNT_POWER_OFF,
1245	BTC_NCNT_INIT_COEX,
1246	BTC_NCNT_SCAN_START,
1247	BTC_NCNT_SCAN_FINISH,
1248	BTC_NCNT_SPECIAL_PACKET,
1249	BTC_NCNT_SWITCH_BAND,
1250	BTC_NCNT_RFK_TIMEOUT,
1251	BTC_NCNT_SHOW_COEX_INFO,
1252	BTC_NCNT_ROLE_INFO,
1253	BTC_NCNT_CONTROL,
1254	BTC_NCNT_RADIO_STATE,
1255	BTC_NCNT_CUSTOMERIZE,
1256	BTC_NCNT_WL_RFK,
1257	BTC_NCNT_WL_STA,
1258	BTC_NCNT_WL_STA_LAST,
1259	BTC_NCNT_FWINFO,
1260	BTC_NCNT_TIMER,
1261	BTC_NCNT_SWITCH_CHBW,
1262	BTC_NCNT_RESUME_DL_FW,
1263	BTC_NCNT_COUNTRYCODE,
1264	BTC_NCNT_NUM,
1265};
1266
1267enum rtw89_btc_btinfo {
1268	BTC_BTINFO_L0 = 0,
1269	BTC_BTINFO_L1,
1270	BTC_BTINFO_L2,
1271	BTC_BTINFO_L3,
1272	BTC_BTINFO_H0,
1273	BTC_BTINFO_H1,
1274	BTC_BTINFO_H2,
1275	BTC_BTINFO_H3,
1276	BTC_BTINFO_MAX
1277};
1278
1279enum rtw89_btc_dcnt {
1280	BTC_DCNT_RUN = 0x0,
1281	BTC_DCNT_CX_RUNINFO,
1282	BTC_DCNT_RPT,
1283	BTC_DCNT_RPT_HANG,
1284	BTC_DCNT_CYCLE,
1285	BTC_DCNT_CYCLE_HANG,
1286	BTC_DCNT_W1,
1287	BTC_DCNT_W1_HANG,
1288	BTC_DCNT_B1,
1289	BTC_DCNT_B1_HANG,
1290	BTC_DCNT_TDMA_NONSYNC,
1291	BTC_DCNT_SLOT_NONSYNC,
1292	BTC_DCNT_BTCNT_HANG,
1293	BTC_DCNT_BTTX_HANG,
1294	BTC_DCNT_WL_SLOT_DRIFT,
1295	BTC_DCNT_WL_STA_LAST,
1296	BTC_DCNT_BT_SLOT_DRIFT,
1297	BTC_DCNT_BT_SLOT_FLOOD,
1298	BTC_DCNT_FDDT_TRIG,
1299	BTC_DCNT_E2G,
1300	BTC_DCNT_E2G_HANG,
1301	BTC_DCNT_WL_FW_VER_MATCH,
1302	BTC_DCNT_NULL_TX_FAIL,
1303	BTC_DCNT_WL_STA_NTFY,
1304	BTC_DCNT_NUM,
1305};
1306
1307enum rtw89_btc_wl_state_cnt {
1308	BTC_WCNT_SCANAP = 0x0,
1309	BTC_WCNT_DHCP,
1310	BTC_WCNT_EAPOL,
1311	BTC_WCNT_ARP,
1312	BTC_WCNT_SCBDUPDATE,
1313	BTC_WCNT_RFK_REQ,
1314	BTC_WCNT_RFK_GO,
1315	BTC_WCNT_RFK_REJECT,
1316	BTC_WCNT_RFK_TIMEOUT,
1317	BTC_WCNT_CH_UPDATE,
1318	BTC_WCNT_DBCC_ALL_2G,
1319	BTC_WCNT_DBCC_CHG,
1320	BTC_WCNT_RX_OK_LAST,
1321	BTC_WCNT_RX_OK_LAST2S,
1322	BTC_WCNT_RX_ERR_LAST,
1323	BTC_WCNT_RX_ERR_LAST2S,
1324	BTC_WCNT_RX_LAST,
1325	BTC_WCNT_NUM
1326};
1327
1328enum rtw89_btc_bt_state_cnt {
1329	BTC_BCNT_RETRY = 0x0,
1330	BTC_BCNT_REINIT,
1331	BTC_BCNT_REENABLE,
1332	BTC_BCNT_SCBDREAD,
1333	BTC_BCNT_RELINK,
1334	BTC_BCNT_IGNOWL,
1335	BTC_BCNT_INQPAG,
1336	BTC_BCNT_INQ,
1337	BTC_BCNT_PAGE,
1338	BTC_BCNT_ROLESW,
1339	BTC_BCNT_AFH,
1340	BTC_BCNT_INFOUPDATE,
1341	BTC_BCNT_INFOSAME,
1342	BTC_BCNT_SCBDUPDATE,
1343	BTC_BCNT_HIPRI_TX,
1344	BTC_BCNT_HIPRI_RX,
1345	BTC_BCNT_LOPRI_TX,
1346	BTC_BCNT_LOPRI_RX,
1347	BTC_BCNT_POLUT,
1348	BTC_BCNT_POLUT_NOW,
1349	BTC_BCNT_POLUT_DIFF,
1350	BTC_BCNT_RATECHG,
1351	BTC_BCNT_BTTXPWR_UPDATE,
1352	BTC_BCNT_NUM,
1353};
1354
1355enum rtw89_btc_bt_profile {
1356	BTC_BT_NOPROFILE = 0,
1357	BTC_BT_HFP = BIT(0),
1358	BTC_BT_HID = BIT(1),
1359	BTC_BT_A2DP = BIT(2),
1360	BTC_BT_PAN = BIT(3),
1361	BTC_PROFILE_MAX = 4,
1362};
1363
1364struct rtw89_btc_ant_info {
1365	u8 type;  /* shared, dedicated */
1366	u8 num;
1367	u8 isolation;
1368
1369	u8 single_pos: 1;/* Single antenna at S0 or S1 */
1370	u8 diversity: 1;
1371	u8 btg_pos: 2;
1372	u8 stream_cnt: 4;
1373};
1374
1375struct rtw89_btc_ant_info_v7 {
1376	u8 type;  /* shared, dedicated(non-shared) */
1377	u8 num;   /* antenna count  */
1378	u8 isolation;
1379	u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */
1380
1381	u8 diversity; /* only for wifi use 1-antenna */
1382	u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */
1383	u8 stream_cnt;  /* spatial_stream count */
1384	u8 rsvd;
1385} __packed;
1386
1387enum rtw89_tfc_dir {
1388	RTW89_TFC_UL,
1389	RTW89_TFC_DL,
1390};
1391
1392struct rtw89_btc_wl_smap {
1393	u32 busy: 1;
1394	u32 scan: 1;
1395	u32 connecting: 1;
1396	u32 roaming: 1;
1397	u32 dbccing: 1;
1398	u32 _4way: 1;
1399	u32 rf_off: 1;
1400	u32 lps: 2;
1401	u32 ips: 1;
1402	u32 init_ok: 1;
1403	u32 traffic_dir : 2;
1404	u32 rf_off_pre: 1;
1405	u32 lps_pre: 2;
1406	u32 lps_exiting: 1;
1407	u32 emlsr: 1;
1408};
1409
1410enum rtw89_tfc_interval {
1411	RTW89_TFC_INTERVAL_100MS,
1412	RTW89_TFC_INTERVAL_2SEC,
1413};
1414
1415enum rtw89_tfc_lv {
1416	RTW89_TFC_IDLE,
1417	RTW89_TFC_ULTRA_LOW,
1418	RTW89_TFC_LOW,
1419	RTW89_TFC_MID,
1420	RTW89_TFC_HIGH,
1421};
1422
1423DECLARE_EWMA(tp, 10, 2);
1424
1425struct rtw89_traffic_stats {
1426	/* units in bytes */
1427	u64 tx_unicast;
1428	u64 rx_unicast;
1429	u32 tx_avg_len;
1430	u32 rx_avg_len;
1431
1432	/* count for packets */
1433	u64 tx_cnt;
1434	u64 rx_cnt;
1435
1436	/* units in Mbps */
1437	u32 tx_throughput;
1438	u32 rx_throughput;
1439	u32 tx_throughput_raw;
1440	u32 rx_throughput_raw;
1441
1442	u32 rx_tf_acc;
1443	u32 rx_tf_periodic;
1444
1445	enum rtw89_tfc_lv tx_tfc_lv;
1446	enum rtw89_tfc_lv rx_tfc_lv;
1447	struct ewma_tp tx_ewma_tp;
1448	struct ewma_tp rx_ewma_tp;
1449
1450	u16 tx_rate;
1451	u16 rx_rate;
1452};
1453
1454struct rtw89_btc_chdef {
1455	u8 center_ch;
1456	u8 band;
1457	u8 chan;
1458	enum rtw89_sc_offset offset;
1459	enum rtw89_bandwidth bw;
1460};
1461
1462struct rtw89_btc_statistic {
1463	u8 rssi; /* 0%~110% (dBm = rssi -110) */
1464	struct rtw89_traffic_stats traffic;
1465};
1466
1467#define BTC_WL_RSSI_THMAX 4
1468
1469struct rtw89_btc_wl_link_info {
1470	struct rtw89_btc_chdef chdef;
1471	struct rtw89_btc_statistic stat;
1472	enum rtw89_tfc_dir dir;
1473	u8 rssi_state[BTC_WL_RSSI_THMAX];
1474	u8 mac_addr[ETH_ALEN];
1475	u8 busy;
1476	u8 ch;
1477	u8 bw;
1478	u8 band;
1479	u8 role;
1480	u8 pid;
1481	u8 phy;
1482	u8 dtim_period;
1483	u8 mode;
1484	u8 tx_1ss_limit;
1485
1486	u8 mac_id;
1487	u8 tx_retry;
1488
1489	u32 bcn_period;
1490	u32 busy_t;
1491	u32 tx_time;
1492	u32 client_cnt;
1493	u32 rx_rate_drop_cnt;
1494	u32 noa_duration;
1495
1496	u32 active: 1;
1497	u32 noa: 1;
1498	u32 client_ps: 1;
1499	u32 connected: 2;
1500};
1501
1502union rtw89_btc_wl_state_map {
1503	u32 val;
1504	struct rtw89_btc_wl_smap map;
1505};
1506
1507struct rtw89_btc_bt_hfp_desc {
1508	u32 exist: 1;
1509	u32 type: 2;
1510	u32 rsvd: 29;
1511};
1512
1513struct rtw89_btc_bt_hid_desc {
1514	u32 exist: 1;
1515	u32 slot_info: 2;
1516	u32 pair_cnt: 2;
1517	u32 type: 8;
1518	u32 rsvd: 19;
1519};
1520
1521struct rtw89_btc_bt_a2dp_desc {
1522	u8 exist: 1;
1523	u8 exist_last: 1;
1524	u8 play_latency: 1;
1525	u8 type: 3;
1526	u8 active: 1;
1527	u8 sink: 1;
1528	u32 handle_update: 1;
1529	u32 devinfo_query: 1;
1530	u32 no_empty_streak_2s: 8;
1531	u32 no_empty_streak_max: 8;
1532	u32 rsvd: 6;
1533
1534	u8 bitpool;
1535	u16 vendor_id;
1536	u32 device_name;
1537	u32 flush_time;
1538};
1539
1540struct rtw89_btc_bt_pan_desc {
1541	u32 exist: 1;
1542	u32 type: 1;
1543	u32 active: 1;
1544	u32 rsvd: 29;
1545};
1546
1547struct rtw89_btc_bt_rfk_info {
1548	u32 run: 1;
1549	u32 req: 1;
1550	u32 timeout: 1;
1551	u32 rsvd: 29;
1552};
1553
1554union rtw89_btc_bt_rfk_info_map {
1555	u32 val;
1556	struct rtw89_btc_bt_rfk_info map;
1557};
1558
1559struct rtw89_btc_bt_ver_info {
1560	u32 fw_coex; /* match with which coex_ver */
1561	u32 fw;
1562};
1563
1564struct rtw89_btc_bool_sta_chg {
1565	u32 now: 1;
1566	u32 last: 1;
1567	u32 remain: 1;
1568	u32 srvd: 29;
1569};
1570
1571struct rtw89_btc_u8_sta_chg {
1572	u8 now;
1573	u8 last;
1574	u8 remain;
1575	u8 rsvd;
1576};
1577
1578struct rtw89_btc_wl_scan_info {
1579	u8 band[RTW89_PHY_NUM];
1580	u8 phy_map;
1581	u8 rsvd;
1582};
1583
1584struct rtw89_btc_wl_dbcc_info {
1585	u8 op_band[RTW89_PHY_NUM]; /* op band in each phy */
1586	u8 scan_band[RTW89_PHY_NUM]; /* scan band in  each phy */
1587	u8 real_band[RTW89_PHY_NUM];
1588	u8 role[RTW89_PHY_NUM]; /* role in each phy */
1589};
1590
1591struct rtw89_btc_wl_mlo_info {
1592	u8 wmode[RTW89_PHY_NUM]; /* enum phl_mr_wmode */
1593	u8 ch_type[RTW89_PHY_NUM]; /* enum phl_mr_ch_type */
1594	u8 hwb_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for HW-band */
1595	u8 path_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for PHY0/1 */
1596
1597	u8 wtype; /* enum phl_mr_wtype */
1598	u8 mrcx_mode;
1599	u8 mrcx_act_hwb_map;
1600	u8 mrcx_bt_slot_rsp;
1601
1602	u8 rf_combination; /* enum btc_mlo_rf_combin 0:2+0, 1:0+2, 2:1+1,3:2+2 */
1603	u8 mlo_en; /* MLO enable */
1604	u8 mlo_adie; /* a-die count */
1605	u8 dual_hw_band_en; /* both 2 HW-band link exist */
1606
1607	u32 link_status; /* enum mlo_dbcc_mode_type */
1608};
1609
1610struct rtw89_btc_wl_active_role {
1611	u8 connected: 1;
1612	u8 pid: 3;
1613	u8 phy: 1;
1614	u8 noa: 1;
1615	u8 band: 2;
1616
1617	u8 client_ps: 1;
1618	u8 bw: 7;
1619
1620	u8 role;
1621	u8 ch;
1622
1623	u16 tx_lvl;
1624	u16 rx_lvl;
1625	u16 tx_rate;
1626	u16 rx_rate;
1627};
1628
1629struct rtw89_btc_wl_active_role_v1 {
1630	u8 connected: 1;
1631	u8 pid: 3;
1632	u8 phy: 1;
1633	u8 noa: 1;
1634	u8 band: 2;
1635
1636	u8 client_ps: 1;
1637	u8 bw: 7;
1638
1639	u8 role;
1640	u8 ch;
1641
1642	u16 tx_lvl;
1643	u16 rx_lvl;
1644	u16 tx_rate;
1645	u16 rx_rate;
1646
1647	u32 noa_duration; /* ms */
1648};
1649
1650struct rtw89_btc_wl_active_role_v2 {
1651	u8 connected: 1;
1652	u8 pid: 3;
1653	u8 phy: 1;
1654	u8 noa: 1;
1655	u8 band: 2;
1656
1657	u8 client_ps: 1;
1658	u8 bw: 7;
1659
1660	u8 role;
1661	u8 ch;
1662
1663	u32 noa_duration; /* ms */
1664};
1665
1666struct rtw89_btc_wl_active_role_v7 {
1667	u8 connected;
1668	u8 pid;
1669	u8 phy;
1670	u8 noa;
1671
1672	u8 band;
1673	u8 client_ps;
1674	u8 bw;
1675	u8 role;
1676
1677	u8 ch;
1678	u8 noa_dur;
1679	u8 client_cnt;
1680	u8 rsvd2;
1681} __packed;
1682
1683struct rtw89_btc_wl_role_info_bpos {
1684	u16 none: 1;
1685	u16 station: 1;
1686	u16 ap: 1;
1687	u16 vap: 1;
1688	u16 adhoc: 1;
1689	u16 adhoc_master: 1;
1690	u16 mesh: 1;
1691	u16 moniter: 1;
1692	u16 p2p_device: 1;
1693	u16 p2p_gc: 1;
1694	u16 p2p_go: 1;
1695	u16 nan: 1;
1696};
1697
1698struct rtw89_btc_wl_scc_ctrl {
1699	u8 null_role1;
1700	u8 null_role2;
1701	u8 ebt_null; /* if tx null at EBT slot */
1702};
1703
1704union rtw89_btc_wl_role_info_map {
1705	u16 val;
1706	struct rtw89_btc_wl_role_info_bpos role;
1707};
1708
1709struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */
1710	u8 connect_cnt;
1711	u8 link_mode;
1712	union rtw89_btc_wl_role_info_map role_map;
1713	struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM];
1714};
1715
1716struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */
1717	u8 connect_cnt;
1718	u8 link_mode;
1719	union rtw89_btc_wl_role_info_map role_map;
1720	struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM];
1721	u32 mrole_type; /* btc_wl_mrole_type */
1722	u32 mrole_noa_duration; /* ms */
1723
1724	u32 dbcc_en: 1;
1725	u32 dbcc_chg: 1;
1726	u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1727	u32 link_mode_chg: 1;
1728	u32 rsvd: 27;
1729};
1730
1731struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */
1732	u8 connect_cnt;
1733	u8 link_mode;
1734	union rtw89_btc_wl_role_info_map role_map;
1735	struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM];
1736	u32 mrole_type; /* btc_wl_mrole_type */
1737	u32 mrole_noa_duration; /* ms */
1738
1739	u32 dbcc_en: 1;
1740	u32 dbcc_chg: 1;
1741	u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1742	u32 link_mode_chg: 1;
1743	u32 rsvd: 27;
1744};
1745
1746struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */
1747	u8 connected;
1748	u8 pid;
1749	u8 phy;
1750	u8 noa;
1751
1752	u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */
1753	u8 active; /* 0:rlink is under doze */
1754	u8 bw; /* enum channel_width */
1755	u8 role; /*enum role_type */
1756
1757	u8 ch;
1758	u8 noa_dur; /* ms */
1759	u8 client_cnt; /* for Role = P2P-Go/AP */
1760	u8 mode; /* wifi protocol */
1761} __packed;
1762
1763#define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6
1764struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */
1765	u8 connect_cnt;
1766	u8 link_mode;
1767	u8 link_mode_chg;
1768	u8 p2p_2g;
1769
1770	struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER];
1771
1772	u32 role_map;
1773	u32 mrole_type; /* btc_wl_mrole_type */
1774	u32 mrole_noa_duration; /* ms */
1775	u32 dbcc_en;
1776	u32 dbcc_chg;
1777	u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1778} __packed;
1779
1780struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */
1781	u8 connect_cnt;
1782	u8 link_mode;
1783	u8 link_mode_chg;
1784	u8 p2p_2g;
1785
1786	u8 pta_req_band;
1787	u8 dbcc_en; /* 1+1 and 2.4G-included */
1788	u8 dbcc_chg;
1789	u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1790
1791	struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
1792
1793	u32 role_map;
1794	u32 mrole_type; /* btc_wl_mrole_type */
1795	u32 mrole_noa_duration; /* ms */
1796} __packed;
1797
1798struct rtw89_btc_wl_ver_info {
1799	u32 fw_coex; /* match with which coex_ver */
1800	u32 fw;
1801	u32 mac;
1802	u32 bb;
1803	u32 rf;
1804};
1805
1806struct rtw89_btc_wl_afh_info {
1807	u8 en;
1808	u8 ch;
1809	u8 bw;
1810	u8 rsvd;
1811} __packed;
1812
1813struct rtw89_btc_wl_rfk_info {
1814	u32 state: 2;
1815	u32 path_map: 4;
1816	u32 phy_map: 2;
1817	u32 band: 2;
1818	u32 type: 8;
1819	u32 con_rfk: 1;
1820	u32 rsvd: 13;
1821
1822	u32 start_time;
1823	u32 proc_time;
1824};
1825
1826struct rtw89_btc_bt_smap {
1827	u32 connect: 1;
1828	u32 ble_connect: 1;
1829	u32 acl_busy: 1;
1830	u32 sco_busy: 1;
1831	u32 mesh_busy: 1;
1832	u32 inq_pag: 1;
1833};
1834
1835union rtw89_btc_bt_state_map {
1836	u32 val;
1837	struct rtw89_btc_bt_smap map;
1838};
1839
1840#define BTC_BT_RSSI_THMAX 4
1841#define BTC_BT_AFH_GROUP 12
1842#define BTC_BT_AFH_LE_GROUP 5
1843
1844struct rtw89_btc_bt_txpwr_desc {
1845	s8 br_dbm;
1846	s8 le_dbm;
1847	u8 br_gain_index;
1848	u8 le_gain_index;
1849};
1850
1851struct rtw89_btc_bt_link_info {
1852	struct rtw89_btc_u8_sta_chg profile_cnt;
1853	struct rtw89_btc_bool_sta_chg multi_link;
1854	struct rtw89_btc_bool_sta_chg relink;
1855	struct rtw89_btc_bt_hfp_desc hfp_desc;
1856	struct rtw89_btc_bt_hid_desc hid_desc;
1857	struct rtw89_btc_bt_a2dp_desc a2dp_desc;
1858	struct rtw89_btc_bt_pan_desc pan_desc;
1859	union rtw89_btc_bt_state_map status;
1860	struct rtw89_btc_bt_txpwr_desc bt_txpwr_desc;
1861
1862	u8 sut_pwr_level[BTC_PROFILE_MAX];
1863	u8 golden_rx_shift[BTC_PROFILE_MAX];
1864	u8 rssi_state[BTC_BT_RSSI_THMAX];
1865	u8 afh_map[BTC_BT_AFH_GROUP];
1866	u8 afh_map_le[BTC_BT_AFH_LE_GROUP];
1867
1868	u32 role_sw: 1;
1869	u32 slave_role: 1;
1870	u32 afh_update: 1;
1871	u32 cqddr: 1;
1872	u32 rssi: 8;
1873	u32 tx_3m: 1;
1874	u32 rsvd: 19;
1875};
1876
1877struct rtw89_btc_3rdcx_info {
1878	u8 type;   /* 0: none, 1:zigbee, 2:LTE  */
1879	u8 hw_coex;
1880	u16 rsvd;
1881};
1882
1883struct rtw89_btc_dm_emap {
1884	u32 init: 1;
1885	u32 pta_owner: 1;
1886	u32 wl_rfk_timeout: 1;
1887	u32 bt_rfk_timeout: 1;
1888	u32 wl_fw_hang: 1;
1889	u32 cycle_hang: 1;
1890	u32 w1_hang: 1;
1891	u32 b1_hang: 1;
1892	u32 tdma_no_sync: 1;
1893	u32 slot_no_sync: 1;
1894	u32 wl_slot_drift: 1;
1895	u32 bt_slot_drift: 1;
1896	u32 role_num_mismatch: 1;
1897	u32 null1_tx_late: 1;
1898	u32 bt_afh_conflict: 1;
1899	u32 bt_leafh_conflict: 1;
1900	u32 bt_slot_flood: 1;
1901	u32 wl_e2g_hang: 1;
1902	u32 wl_ver_mismatch: 1;
1903	u32 bt_ver_mismatch: 1;
1904	u32 rfe_type0: 1;
1905	u32 h2c_buffer_over: 1;
1906	u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/
1907	u32 wl_no_sta_ntfy: 1;
1908
1909	u32 h2c_bmap_mismatch: 1;
1910	u32 c2h_bmap_mismatch: 1;
1911	u32 h2c_struct_invalid: 1;
1912	u32 c2h_struct_invalid: 1;
1913	u32 h2c_c2h_buffer_mismatch: 1;
1914};
1915
1916union rtw89_btc_dm_error_map {
1917	u32 val;
1918	struct rtw89_btc_dm_emap map;
1919};
1920
1921struct rtw89_btc_rf_para {
1922	u32 tx_pwr_freerun;
1923	u32 rx_gain_freerun;
1924	u32 tx_pwr_perpkt;
1925	u32 rx_gain_perpkt;
1926};
1927
1928struct rtw89_btc_wl_nhm {
1929	u8 instant_wl_nhm_dbm;
1930	u8 instant_wl_nhm_per_mhz;
1931	u16 valid_record_times;
1932	s8 record_pwr[16];
1933	u8 record_ratio[16];
1934	s8 pwr; /* dbm_per_MHz  */
1935	u8 ratio;
1936	u8 current_status;
1937	u8 refresh;
1938	bool start_flag;
1939	s8 pwr_max;
1940	s8 pwr_min;
1941};
1942
1943struct rtw89_btc_wl_info {
1944	struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM];
1945	struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
1946	struct rtw89_btc_wl_rfk_info rfk_info;
1947	struct rtw89_btc_wl_ver_info  ver_info;
1948	struct rtw89_btc_wl_afh_info afh_info;
1949	struct rtw89_btc_wl_role_info role_info;
1950	struct rtw89_btc_wl_role_info_v1 role_info_v1;
1951	struct rtw89_btc_wl_role_info_v2 role_info_v2;
1952	struct rtw89_btc_wl_role_info_v7 role_info_v7;
1953	struct rtw89_btc_wl_role_info_v8 role_info_v8;
1954	struct rtw89_btc_wl_scan_info scan_info;
1955	struct rtw89_btc_wl_dbcc_info dbcc_info;
1956	struct rtw89_btc_wl_mlo_info mlo_info;
1957	struct rtw89_btc_rf_para rf_para;
1958	struct rtw89_btc_wl_nhm nhm;
1959	union rtw89_btc_wl_state_map status;
1960
1961	u8 port_id[RTW89_WIFI_ROLE_MLME_MAX];
1962	u8 rssi_level;
1963	u8 cn_report;
1964	u8 coex_mode;
1965	u8 pta_req_mac;
1966	u8 bt_polut_type[RTW89_PHY_NUM]; /* BT polluted WL-Tx type for phy0/1  */
1967
1968	bool is_5g_hi_channel;
1969	bool go_client_exist;
1970	bool noa_exist;
1971	bool pta_reg_mac_chg;
1972	bool bg_mode;
1973	bool he_mode;
1974	bool scbd_change;
1975	bool fw_ver_mismatch;
1976	bool client_cnt_inc_2g;
1977	bool link_mode_chg;
1978	bool dbcc_chg;
1979	u32 scbd;
1980};
1981
1982struct rtw89_btc_module {
1983	struct rtw89_btc_ant_info ant;
1984	u8 rfe_type;
1985	u8 cv;
1986
1987	u8 bt_solo: 1;
1988	u8 bt_pos: 1;
1989	u8 switch_type: 1;
1990	u8 wa_type: 3;
1991
1992	u8 kt_ver_adie;
1993};
1994
1995struct rtw89_btc_module_v7 {
1996	u8 rfe_type;
1997	u8 kt_ver;
1998	u8 bt_solo;
1999	u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/
2000
2001	u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */
2002	u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */
2003	u8 kt_ver_adie;
2004	u8 rsvd;
2005
2006	struct rtw89_btc_ant_info_v7 ant;
2007} __packed;
2008
2009union rtw89_btc_module_info {
2010	struct rtw89_btc_module md;
2011	struct rtw89_btc_module_v7 md_v7;
2012};
2013
2014#define RTW89_BTC_DM_MAXSTEP 30
2015#define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8)
2016
2017struct rtw89_btc_dm_step {
2018	u16 step[RTW89_BTC_DM_MAXSTEP];
2019	u8 step_pos;
2020	bool step_ov;
2021};
2022
2023struct rtw89_btc_init_info {
2024	struct rtw89_btc_module module;
2025	u8 wl_guard_ch;
2026
2027	u8 wl_only: 1;
2028	u8 wl_init_ok: 1;
2029	u8 dbcc_en: 1;
2030	u8 cx_other: 1;
2031	u8 bt_only: 1;
2032
2033	u16 rsvd;
2034};
2035
2036struct rtw89_btc_init_info_v7 {
2037	u8 wl_guard_ch;
2038	u8 wl_only;
2039	u8 wl_init_ok;
2040	u8 rsvd3;
2041
2042	u8 cx_other;
2043	u8 bt_only;
2044	u8 pta_mode;
2045	u8 pta_direction;
2046
2047	struct rtw89_btc_module_v7 module;
2048} __packed;
2049
2050union rtw89_btc_init_info_u {
2051	struct rtw89_btc_init_info init;
2052	struct rtw89_btc_init_info_v7 init_v7;
2053};
2054
2055struct rtw89_btc_wl_tx_limit_para {
2056	u16 enable;
2057	u32 tx_time;	/* unit: us */
2058	u16 tx_retry;
2059};
2060
2061enum rtw89_btc_bt_scan_type {
2062	BTC_SCAN_INQ	= 0,
2063	BTC_SCAN_PAGE,
2064	BTC_SCAN_BLE,
2065	BTC_SCAN_INIT,
2066	BTC_SCAN_TV,
2067	BTC_SCAN_ADV,
2068	BTC_SCAN_MAX1,
2069};
2070
2071enum rtw89_btc_ble_scan_type {
2072	CXSCAN_BG = 0,
2073	CXSCAN_INIT,
2074	CXSCAN_LE,
2075	CXSCAN_MAX
2076};
2077
2078#define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0)
2079#define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1)
2080
2081struct rtw89_btc_bt_scan_info_v1 {
2082	__le16 win;
2083	__le16 intvl;
2084	__le32 flags;
2085} __packed;
2086
2087struct rtw89_btc_bt_scan_info_v2 {
2088	__le16 win;
2089	__le16 intvl;
2090} __packed;
2091
2092struct rtw89_btc_fbtc_btscan_v1 {
2093	u8 fver; /* btc_ver::fcxbtscan */
2094	u8 rsvd;
2095	__le16 rsvd2;
2096	struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1];
2097} __packed;
2098
2099struct rtw89_btc_fbtc_btscan_v2 {
2100	u8 fver; /* btc_ver::fcxbtscan */
2101	u8 type;
2102	__le16 rsvd2;
2103	struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
2104} __packed;
2105
2106struct rtw89_btc_fbtc_btscan_v7 {
2107	u8 fver; /* btc_ver::fcxbtscan */
2108	u8 type;
2109	u8 rsvd0;
2110	u8 rsvd1;
2111	struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
2112} __packed;
2113
2114union rtw89_btc_fbtc_btscan {
2115	struct rtw89_btc_fbtc_btscan_v1 v1;
2116	struct rtw89_btc_fbtc_btscan_v2 v2;
2117	struct rtw89_btc_fbtc_btscan_v7 v7;
2118};
2119
2120struct rtw89_btc_bt_info {
2121	struct rtw89_btc_bt_link_info link_info;
2122	struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1];
2123	struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX];
2124	struct rtw89_btc_bt_ver_info ver_info;
2125	struct rtw89_btc_bool_sta_chg enable;
2126	struct rtw89_btc_bool_sta_chg inq_pag;
2127	struct rtw89_btc_rf_para rf_para;
2128	union rtw89_btc_bt_rfk_info_map rfk_info;
2129
2130	u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */
2131	u8 txpwr_info[BTC_BTINFO_MAX];
2132	u8 rssi_level;
2133
2134	u32 scbd;
2135	u32 feature;
2136
2137	u32 mbx_avl: 1;
2138	u32 whql_test: 1;
2139	u32 igno_wl: 1;
2140	u32 reinit: 1;
2141	u32 ble_scan_en: 1;
2142	u32 btg_type: 1;
2143	u32 inq: 1;
2144	u32 pag: 1;
2145	u32 run_patch_code: 1;
2146	u32 hi_lna_rx: 1;
2147	u32 scan_rx_low_pri: 1;
2148	u32 scan_info_update: 1;
2149	u32 lna_constrain: 3;
2150	u32 rsvd: 17;
2151};
2152
2153struct rtw89_btc_cx {
2154	struct rtw89_btc_wl_info wl;
2155	struct rtw89_btc_bt_info bt;
2156	struct rtw89_btc_3rdcx_info other;
2157	u32 state_map;
2158	u32 cnt_bt[BTC_BCNT_NUM];
2159	u32 cnt_wl[BTC_WCNT_NUM];
2160};
2161
2162struct rtw89_btc_fbtc_tdma {
2163	u8 type; /* btc_ver::fcxtdma */
2164	u8 rxflctrl;
2165	u8 txpause;
2166	u8 wtgle_n;
2167	u8 leak_n;
2168	u8 ext_ctrl;
2169	u8 rxflctrl_role;
2170	u8 option_ctrl;
2171} __packed;
2172
2173struct rtw89_btc_fbtc_tdma_v3 {
2174	u8 fver; /* btc_ver::fcxtdma */
2175	u8 rsvd;
2176	__le16 rsvd1;
2177	struct rtw89_btc_fbtc_tdma tdma;
2178} __packed;
2179
2180union rtw89_btc_fbtc_tdma_le32 {
2181	struct rtw89_btc_fbtc_tdma v1;
2182	struct rtw89_btc_fbtc_tdma_v3 v3;
2183};
2184
2185#define CXMREG_MAX 30
2186#define CXMREG_MAX_V2 20
2187#define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/
2188#define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
2189
2190enum rtw89_btc_bt_sta_counter {
2191	BTC_BCNT_RFK_REQ = 0,
2192	BTC_BCNT_RFK_GO = 1,
2193	BTC_BCNT_RFK_REJECT = 2,
2194	BTC_BCNT_RFK_FAIL = 3,
2195	BTC_BCNT_RFK_TIMEOUT = 4,
2196	BTC_BCNT_HI_TX = 5,
2197	BTC_BCNT_HI_RX = 6,
2198	BTC_BCNT_LO_TX = 7,
2199	BTC_BCNT_LO_RX = 8,
2200	BTC_BCNT_POLLUTED = 9,
2201	BTC_BCNT_STA_MAX
2202};
2203
2204enum rtw89_btc_bt_sta_counter_v105 {
2205	BTC_BCNT_RFK_REQ_V105 = 0,
2206	BTC_BCNT_HI_TX_V105 = 1,
2207	BTC_BCNT_HI_RX_V105 = 2,
2208	BTC_BCNT_LO_TX_V105 = 3,
2209	BTC_BCNT_LO_RX_V105 = 4,
2210	BTC_BCNT_POLLUTED_V105 = 5,
2211	BTC_BCNT_STA_MAX_V105
2212};
2213
2214struct rtw89_btc_fbtc_rpt_ctrl_v1 {
2215	u16 fver; /* btc_ver::fcxbtcrpt */
2216	u16 rpt_cnt; /* tmr counters */
2217	u32 wl_fw_coex_ver; /* match which driver's coex version */
2218	u32 wl_fw_cx_offload;
2219	u32 wl_fw_ver;
2220	u32 rpt_enable;
2221	u32 rpt_para; /* ms */
2222	u32 mb_send_fail_cnt; /* fw send mailbox fail counter */
2223	u32 mb_send_ok_cnt; /* fw send mailbox ok counter */
2224	u32 mb_recv_cnt; /* fw recv mailbox counter */
2225	u32 mb_a2dp_empty_cnt; /* a2dp empty count */
2226	u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */
2227	u32 mb_a2dp_full_cnt; /* a2dp empty full counter */
2228	u32 bt_rfk_cnt[BTC_BCNT_HI_TX];
2229	u32 c2h_cnt; /* fw send c2h counter  */
2230	u32 h2c_cnt; /* fw recv h2c counter */
2231} __packed;
2232
2233struct rtw89_btc_fbtc_rpt_ctrl_info {
2234	__le32 cnt; /* fw report counter */
2235	__le32 en; /* report map */
2236	__le32 para; /* not used */
2237
2238	__le32 cnt_c2h; /* fw send c2h counter  */
2239	__le32 cnt_h2c; /* fw recv h2c counter */
2240	__le32 len_c2h; /* The total length of the last C2H  */
2241
2242	__le32 cnt_aoac_rf_on;  /* rf-on counter for aoac switch notify */
2243	__le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2244} __packed;
2245
2246struct rtw89_btc_fbtc_rpt_ctrl_info_v5 {
2247	__le32 cx_ver; /* match which driver's coex version */
2248	__le32 fw_ver;
2249	__le32 en; /* report map */
2250
2251	__le16 cnt; /* fw report counter */
2252	__le16 cnt_c2h; /* fw send c2h counter  */
2253	__le16 cnt_h2c; /* fw recv h2c counter */
2254	__le16 len_c2h; /* The total length of the last C2H  */
2255
2256	__le16 cnt_aoac_rf_on;  /* rf-on counter for aoac switch notify */
2257	__le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2258} __packed;
2259
2260struct rtw89_btc_fbtc_rpt_ctrl_info_v8 {
2261	__le16 cnt; /* fw report counter */
2262	__le16 cnt_c2h; /* fw send c2h counter  */
2263	__le16 cnt_h2c; /* fw recv h2c counter */
2264	__le16 len_c2h; /* The total length of the last C2H  */
2265
2266	__le16 cnt_aoac_rf_on;  /* rf-on counter for aoac switch notify */
2267	__le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2268
2269	__le32 cx_ver; /* match which driver's coex version */
2270	__le32 fw_ver;
2271	__le32 en; /* report map */
2272} __packed;
2273
2274struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info {
2275	__le32 cx_ver; /* match which driver's coex version */
2276	__le32 cx_offload;
2277	__le32 fw_ver;
2278} __packed;
2279
2280struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty {
2281	__le32 cnt_empty; /* a2dp empty count */
2282	__le32 cnt_flowctrl; /* a2dp empty flow control counter */
2283	__le32 cnt_tx;
2284	__le32 cnt_ack;
2285	__le32 cnt_nack;
2286} __packed;
2287
2288struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox {
2289	__le32 cnt_send_ok; /* fw send mailbox ok counter */
2290	__le32 cnt_send_fail; /* fw send mailbox fail counter */
2291	__le32 cnt_recv; /* fw recv mailbox counter */
2292	struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp;
2293} __packed;
2294
2295struct rtw89_btc_fbtc_rpt_ctrl_v4 {
2296	u8 fver;
2297	u8 rsvd;
2298	__le16 rsvd1;
2299	struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info;
2300	struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info;
2301	struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2302	__le32 bt_cnt[BTC_BCNT_STA_MAX];
2303	struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_NUM];
2304} __packed;
2305
2306struct rtw89_btc_fbtc_rpt_ctrl_v5 {
2307	u8 fver;
2308	u8 rsvd;
2309	__le16 rsvd1;
2310
2311	u8 gnt_val[RTW89_PHY_NUM][4];
2312	__le16 bt_cnt[BTC_BCNT_STA_MAX];
2313
2314	struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
2315	struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2316} __packed;
2317
2318struct rtw89_btc_fbtc_rpt_ctrl_v105 {
2319	u8 fver;
2320	u8 rsvd;
2321	__le16 rsvd1;
2322
2323	u8 gnt_val[RTW89_PHY_NUM][4];
2324	__le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2325
2326	struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
2327	struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2328} __packed;
2329
2330struct rtw89_btc_fbtc_rpt_ctrl_v7 {
2331	u8 fver;
2332	u8 rsvd0;
2333	u8 rsvd1;
2334	u8 rsvd2;
2335
2336	u8 gnt_val[RTW89_PHY_NUM][4];
2337	__le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2338
2339	struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info;
2340	struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2341} __packed;
2342
2343struct rtw89_btc_fbtc_rpt_ctrl_v8 {
2344	u8 fver;
2345	u8 rsvd0;
2346	u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */
2347	u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */
2348
2349	u8 gnt_val[RTW89_PHY_NUM][4];
2350	__le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2351
2352	struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info;
2353	struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2354} __packed;
2355
2356union rtw89_btc_fbtc_rpt_ctrl_ver_info {
2357	struct rtw89_btc_fbtc_rpt_ctrl_v1 v1;
2358	struct rtw89_btc_fbtc_rpt_ctrl_v4 v4;
2359	struct rtw89_btc_fbtc_rpt_ctrl_v5 v5;
2360	struct rtw89_btc_fbtc_rpt_ctrl_v105 v105;
2361	struct rtw89_btc_fbtc_rpt_ctrl_v7 v7;
2362	struct rtw89_btc_fbtc_rpt_ctrl_v8 v8;
2363};
2364
2365enum rtw89_fbtc_ext_ctrl_type {
2366	CXECTL_OFF = 0x0, /* tdma off */
2367	CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
2368	CXECTL_EXT = 0x2,
2369	CXECTL_MAX
2370};
2371
2372union rtw89_btc_fbtc_rxflct {
2373	u8 val;
2374	u8 type: 3;
2375	u8 tgln_n: 5;
2376};
2377
2378enum rtw89_btc_cxst_state {
2379	CXST_OFF = 0x0,
2380	CXST_B2W = 0x1,
2381	CXST_W1 = 0x2,
2382	CXST_W2 = 0x3,
2383	CXST_W2B = 0x4,
2384	CXST_B1 = 0x5,
2385	CXST_B2 = 0x6,
2386	CXST_B3 = 0x7,
2387	CXST_B4 = 0x8,
2388	CXST_LK = 0x9,
2389	CXST_BLK = 0xa,
2390	CXST_E2G = 0xb,
2391	CXST_E5G = 0xc,
2392	CXST_EBT = 0xd,
2393	CXST_ENULL = 0xe,
2394	CXST_WLK = 0xf,
2395	CXST_W1FDD = 0x10,
2396	CXST_B1FDD = 0x11,
2397	CXST_MAX = 0x12,
2398};
2399
2400enum rtw89_btc_cxevnt {
2401	CXEVNT_TDMA_ENTRY = 0x0,
2402	CXEVNT_WL_TMR,
2403	CXEVNT_B1_TMR,
2404	CXEVNT_B2_TMR,
2405	CXEVNT_B3_TMR,
2406	CXEVNT_B4_TMR,
2407	CXEVNT_W2B_TMR,
2408	CXEVNT_B2W_TMR,
2409	CXEVNT_BCN_EARLY,
2410	CXEVNT_A2DP_EMPTY,
2411	CXEVNT_LK_END,
2412	CXEVNT_RX_ISR,
2413	CXEVNT_RX_FC0,
2414	CXEVNT_RX_FC1,
2415	CXEVNT_BT_RELINK,
2416	CXEVNT_BT_RETRY,
2417	CXEVNT_E2G,
2418	CXEVNT_E5G,
2419	CXEVNT_EBT,
2420	CXEVNT_ENULL,
2421	CXEVNT_DRV_WLK,
2422	CXEVNT_BCN_OK,
2423	CXEVNT_BT_CHANGE,
2424	CXEVNT_EBT_EXTEND,
2425	CXEVNT_E2G_NULL1,
2426	CXEVNT_B1FDD_TMR,
2427	CXEVNT_MAX
2428};
2429
2430enum {
2431	CXBCN_ALL = 0x0,
2432	CXBCN_ALL_OK,
2433	CXBCN_BT_SLOT,
2434	CXBCN_BT_OK,
2435	CXBCN_MAX
2436};
2437
2438enum btc_slot_type {
2439	SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
2440	SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
2441	CXSTYPE_NUM,
2442};
2443
2444enum { /* TIME */
2445	CXT_BT = 0x0,
2446	CXT_WL = 0x1,
2447	CXT_MAX
2448};
2449
2450enum { /* TIME-A2DP */
2451	CXT_FLCTRL_OFF = 0x0,
2452	CXT_FLCTRL_ON = 0x1,
2453	CXT_FLCTRL_MAX
2454};
2455
2456enum { /* STEP TYPE */
2457	CXSTEP_NONE = 0x0,
2458	CXSTEP_EVNT = 0x1,
2459	CXSTEP_SLOT = 0x2,
2460	CXSTEP_MAX,
2461};
2462
2463enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */
2464	RPT_BT_AFH_SEQ_LEGACY = 0x10,
2465	RPT_BT_AFH_SEQ_LE = 0x20
2466};
2467
2468#define BTC_DBG_MAX1  32
2469struct rtw89_btc_fbtc_gpio_dbg_v1 {
2470	u8 fver; /* btc_ver::fcxgpiodbg */
2471	u8 rsvd;
2472	__le16 rsvd2;
2473	__le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
2474	__le32 pre_state; /* the debug signal is 1 or 0  */
2475	u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */
2476} __packed;
2477
2478struct rtw89_btc_fbtc_gpio_dbg_v7 {
2479	u8 fver;
2480	u8 rsvd0;
2481	u8 rsvd1;
2482	u8 rsvd2;
2483
2484	u8 gpio_map[BTC_DBG_MAX1];
2485
2486	__le32 en_map;
2487	__le32 pre_state;
2488} __packed;
2489
2490union rtw89_btc_fbtc_gpio_dbg {
2491	struct rtw89_btc_fbtc_gpio_dbg_v1 v1;
2492	struct rtw89_btc_fbtc_gpio_dbg_v7 v7;
2493};
2494
2495struct rtw89_btc_fbtc_mreg_val_v1 {
2496	u8 fver; /* btc_ver::fcxmreg */
2497	u8 reg_num;
2498	__le16 rsvd;
2499	__le32 mreg_val[CXMREG_MAX];
2500} __packed;
2501
2502struct rtw89_btc_fbtc_mreg_val_v2 {
2503	u8 fver; /* btc_ver::fcxmreg */
2504	u8 reg_num;
2505	__le16 rsvd;
2506	__le32 mreg_val[CXMREG_MAX_V2];
2507} __packed;
2508
2509struct rtw89_btc_fbtc_mreg_val_v7 {
2510	u8 fver;
2511	u8 reg_num;
2512	u8 rsvd0;
2513	u8 rsvd1;
2514	__le32 mreg_val[CXMREG_MAX_V2];
2515} __packed;
2516
2517union rtw89_btc_fbtc_mreg_val {
2518	struct rtw89_btc_fbtc_mreg_val_v1 v1;
2519	struct rtw89_btc_fbtc_mreg_val_v2 v2;
2520	struct rtw89_btc_fbtc_mreg_val_v7 v7;
2521};
2522
2523#define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \
2524	{ .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \
2525	  .offset = cpu_to_le32(__offset), }
2526
2527struct rtw89_btc_fbtc_mreg {
2528	__le16 type;
2529	__le16 bytes;
2530	__le32 offset;
2531} __packed;
2532
2533struct rtw89_btc_fbtc_slot {
2534	__le16 dur;
2535	__le32 cxtbl;
2536	__le16 cxtype;
2537} __packed;
2538
2539struct rtw89_btc_fbtc_slots {
2540	u8 fver; /* btc_ver::fcxslots */
2541	u8 tbl_num;
2542	__le16 rsvd;
2543	__le32 update_map;
2544	struct rtw89_btc_fbtc_slot slot[CXST_MAX];
2545} __packed;
2546
2547struct rtw89_btc_fbtc_slot_v7 {
2548	__le16 dur; /* slot duration */
2549	__le16 cxtype;
2550	__le32 cxtbl;
2551} __packed;
2552
2553struct rtw89_btc_fbtc_slot_u16 {
2554	__le16 dur; /* slot duration */
2555	__le16 cxtype;
2556	__le16 cxtbl_l16; /* coex table [15:0] */
2557	__le16 cxtbl_h16; /* coex table [31:16] */
2558} __packed;
2559
2560struct rtw89_btc_fbtc_1slot_v7 {
2561	u8 fver;
2562	u8 sid; /* slot id */
2563	__le16 rsvd;
2564	struct rtw89_btc_fbtc_slot_v7 slot;
2565} __packed;
2566
2567struct rtw89_btc_fbtc_slots_v7 {
2568	u8 fver;
2569	u8 slot_cnt;
2570	u8 rsvd0;
2571	u8 rsvd1;
2572	struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX];
2573	__le32 update_map;
2574} __packed;
2575
2576union rtw89_btc_fbtc_slots_info {
2577	struct rtw89_btc_fbtc_slots v1;
2578	struct rtw89_btc_fbtc_slots_v7 v7;
2579} __packed;
2580
2581struct rtw89_btc_fbtc_step {
2582	u8 type;
2583	u8 val;
2584	__le16 difft;
2585} __packed;
2586
2587struct rtw89_btc_fbtc_steps_v2 {
2588	u8 fver; /* btc_ver::fcxstep */
2589	u8 rsvd;
2590	__le16 cnt;
2591	__le16 pos_old;
2592	__le16 pos_new;
2593	struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2594} __packed;
2595
2596struct rtw89_btc_fbtc_steps_v3 {
2597	u8 fver;
2598	u8 en;
2599	__le16 rsvd;
2600	__le32 cnt;
2601	struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2602} __packed;
2603
2604union rtw89_btc_fbtc_steps_info {
2605	struct rtw89_btc_fbtc_steps_v2 v2;
2606	struct rtw89_btc_fbtc_steps_v3 v3;
2607};
2608
2609struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */
2610	u8 fver; /* btc_ver::fcxcysta */
2611	u8 rsvd;
2612	__le16 cycles; /* total cycle number */
2613	__le16 cycles_a2dp[CXT_FLCTRL_MAX];
2614	__le16 a2dpept; /* a2dp empty cnt */
2615	__le16 a2dpeptto; /* a2dp empty timeout cnt*/
2616	__le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
2617	__le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
2618	__le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2619	__le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */
2620	__le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */
2621	__le16 tavg_a2dpept; /* avg a2dp empty time */
2622	__le16 tmax_a2dpept; /* max a2dp empty time */
2623	__le16 tavg_lk; /* avg leak-slot time */
2624	__le16 tmax_lk; /* max leak-slot time */
2625	__le32 slot_cnt[CXST_MAX]; /* slot count */
2626	__le32 bcn_cnt[CXBCN_MAX];
2627	__le32 leakrx_cnt; /* the rximr occur at leak slot  */
2628	__le32 collision_cnt; /* counter for event/timer occur at same time */
2629	__le32 skip_cnt;
2630	__le32 exception;
2631	__le32 except_cnt;
2632	__le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];
2633} __packed;
2634
2635struct rtw89_btc_fbtc_fdd_try_info {
2636	__le16 cycles[CXT_FLCTRL_MAX];
2637	__le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */
2638	__le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */
2639} __packed;
2640
2641struct rtw89_btc_fbtc_cycle_time_info {
2642	__le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2643	__le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2644	__le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2645} __packed;
2646
2647struct rtw89_btc_fbtc_cycle_time_info_v5 {
2648	__le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2649	__le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2650} __packed;
2651
2652struct rtw89_btc_fbtc_a2dp_trx_stat {
2653	u8 empty_cnt;
2654	u8 retry_cnt;
2655	u8 tx_rate;
2656	u8 tx_cnt;
2657	u8 ack_cnt;
2658	u8 nack_cnt;
2659	u8 rsvd1;
2660	u8 rsvd2;
2661} __packed;
2662
2663struct rtw89_btc_fbtc_a2dp_trx_stat_v4 {
2664	u8 empty_cnt;
2665	u8 retry_cnt;
2666	u8 tx_rate;
2667	u8 tx_cnt;
2668	u8 ack_cnt;
2669	u8 nack_cnt;
2670	u8 no_empty_cnt;
2671	u8 rsvd;
2672} __packed;
2673
2674struct rtw89_btc_fbtc_cycle_a2dp_empty_info {
2675	__le16 cnt; /* a2dp empty cnt */
2676	__le16 cnt_timeout; /* a2dp empty timeout cnt*/
2677	__le16 tavg; /* avg a2dp empty time */
2678	__le16 tmax; /* max a2dp empty time */
2679} __packed;
2680
2681struct rtw89_btc_fbtc_cycle_leak_info {
2682	__le32 cnt_rximr; /* the rximr occur at leak slot  */
2683	__le16 tavg; /* avg leak-slot time */
2684	__le16 tmax; /* max leak-slot time */
2685} __packed;
2686
2687struct rtw89_btc_fbtc_cycle_leak_info_v7 {
2688	__le16 tavg;
2689	__le16 tamx;
2690	__le32 cnt_rximr;
2691} __packed;
2692
2693#define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0)
2694#define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10)
2695
2696struct rtw89_btc_fbtc_cycle_fddt_info {
2697	__le16 train_cycle;
2698	__le16 tp;
2699
2700	s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2701	s8 bt_tx_power; /* decrease Tx power (dB) */
2702	s8 bt_rx_gain;  /* LNA constrain level */
2703	u8 no_empty_cnt;
2704
2705	u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2706	u8 cn; /* condition_num */
2707	u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2708	u8 train_result; /* refer to enum btc_fddt_check_map */
2709} __packed;
2710
2711#define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0)
2712#define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4)
2713
2714struct rtw89_btc_fbtc_cycle_fddt_info_v5 {
2715	__le16 train_cycle;
2716	__le16 tp;
2717
2718	s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2719	s8 bt_tx_power; /* decrease Tx power (dB) */
2720	s8 bt_rx_gain;  /* LNA constrain level */
2721	u8 no_empty_cnt;
2722
2723	u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2724	u8 cn; /* condition_num */
2725	u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2726	u8 train_result; /* refer to enum btc_fddt_check_map */
2727} __packed;
2728
2729struct rtw89_btc_fbtc_fddt_cell_status {
2730	s8 wl_tx_pwr;
2731	s8 bt_tx_pwr;
2732	s8 bt_rx_gain;
2733	u8 state_phase; /* [0:3] train state, [4:7] train phase */
2734} __packed;
2735
2736struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */
2737	u8 fver;
2738	u8 rsvd;
2739	__le16 cycles; /* total cycle number */
2740	__le16 slot_step_time[BTC_CYCLE_SLOT_MAX];
2741	struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2742	struct rtw89_btc_fbtc_fdd_try_info fdd_try;
2743	struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2744	struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX];
2745	struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2746	__le32 slot_cnt[CXST_MAX]; /* slot count */
2747	__le32 bcn_cnt[CXBCN_MAX];
2748	__le32 collision_cnt; /* counter for event/timer occur at the same time */
2749	__le32 skip_cnt;
2750	__le32 except_cnt;
2751	__le32 except_map;
2752} __packed;
2753
2754#define FDD_TRAIN_WL_DIRECTION 2
2755#define FDD_TRAIN_WL_RSSI_LEVEL 5
2756#define FDD_TRAIN_BT_RSSI_LEVEL 5
2757
2758struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */
2759	u8 fver;
2760	u8 rsvd;
2761	u8 collision_cnt; /* counter for event/timer occur at the same time */
2762	u8 except_cnt;
2763
2764	__le16 skip_cnt;
2765	__le16 cycles; /* total cycle number */
2766
2767	__le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2768	__le16 slot_cnt[CXST_MAX]; /* slot count */
2769	__le16 bcn_cnt[CXBCN_MAX];
2770	struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2771	struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2772	struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2773	struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2774	struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX];
2775	struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2776							 [FDD_TRAIN_WL_RSSI_LEVEL]
2777							 [FDD_TRAIN_BT_RSSI_LEVEL];
2778	__le32 except_map;
2779} __packed;
2780
2781struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */
2782	u8 fver;
2783	u8 rsvd;
2784	u8 collision_cnt; /* counter for event/timer occur at the same time */
2785	u8 except_cnt;
2786	u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2787
2788	__le16 skip_cnt;
2789	__le16 cycles; /* total cycle number */
2790
2791	__le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2792	__le16 slot_cnt[CXST_MAX]; /* slot count */
2793	__le16 bcn_cnt[CXBCN_MAX];
2794	struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2795	struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2796	struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2797	struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2798	struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX];
2799	struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2800							 [FDD_TRAIN_WL_RSSI_LEVEL]
2801							 [FDD_TRAIN_BT_RSSI_LEVEL];
2802	__le32 except_map;
2803} __packed;
2804
2805struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */
2806	u8 fver;
2807	u8 rsvd;
2808	u8 collision_cnt; /* counter for event/timer occur at the same time */
2809	u8 except_cnt;
2810
2811	u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2812
2813	struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2814
2815	__le16 skip_cnt;
2816	__le16 cycles; /* total cycle number */
2817
2818	__le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2819	__le16 slot_cnt[CXST_MAX]; /* slot count */
2820	__le16 bcn_cnt[CXBCN_MAX];
2821
2822	struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2823	struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2824	struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot;
2825
2826	__le32 except_map;
2827} __packed;
2828
2829union rtw89_btc_fbtc_cysta_info {
2830	struct rtw89_btc_fbtc_cysta_v2 v2;
2831	struct rtw89_btc_fbtc_cysta_v3 v3;
2832	struct rtw89_btc_fbtc_cysta_v4 v4;
2833	struct rtw89_btc_fbtc_cysta_v5 v5;
2834	struct rtw89_btc_fbtc_cysta_v7 v7;
2835};
2836
2837struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */
2838	u8 fver; /* btc_ver::fcxnullsta */
2839	u8 rsvd;
2840	__le16 rsvd2;
2841	__le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2842	__le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2843	__le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
2844} __packed;
2845
2846struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */
2847	u8 fver; /* btc_ver::fcxnullsta */
2848	u8 rsvd;
2849	__le16 rsvd2;
2850	__le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2851	__le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2852	__le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */
2853} __packed;
2854
2855struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */
2856	u8 fver;
2857	u8 rsvd0;
2858	u8 rsvd1;
2859	u8 rsvd2;
2860
2861	__le32 tmax[2];
2862	__le32 tavg[2];
2863	__le32 result[2][5];
2864} __packed;
2865
2866union rtw89_btc_fbtc_cynullsta_info {
2867	struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */
2868	struct rtw89_btc_fbtc_cynullsta_v2 v2;
2869	struct rtw89_btc_fbtc_cynullsta_v7 v7;
2870};
2871
2872struct rtw89_btc_fbtc_btver_v1 {
2873	u8 fver; /* btc_ver::fcxbtver */
2874	u8 rsvd;
2875	__le16 rsvd2;
2876	__le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2877	__le32 fw_ver;
2878	__le32 feature;
2879} __packed;
2880
2881struct rtw89_btc_fbtc_btver_v7 {
2882	u8 fver;
2883	u8 rsvd0;
2884	u8 rsvd1;
2885	u8 rsvd2;
2886
2887	__le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2888	__le32 fw_ver;
2889	__le32 feature;
2890} __packed;
2891
2892union rtw89_btc_fbtc_btver {
2893	struct rtw89_btc_fbtc_btver_v1 v1;
2894	struct rtw89_btc_fbtc_btver_v7 v7;
2895} __packed;
2896
2897struct rtw89_btc_fbtc_btafh {
2898	u8 fver; /* btc_ver::fcxbtafh */
2899	u8 rsvd;
2900	__le16 rsvd2;
2901	u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
2902	u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
2903	u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
2904} __packed;
2905
2906struct rtw89_btc_fbtc_btafh_v2 {
2907	u8 fver; /* btc_ver::fcxbtafh */
2908	u8 rsvd;
2909	u8 rsvd2;
2910	u8 map_type;
2911	u8 afh_l[4];
2912	u8 afh_m[4];
2913	u8 afh_h[4];
2914	u8 afh_le_a[4];
2915	u8 afh_le_b[4];
2916} __packed;
2917
2918struct rtw89_btc_fbtc_btafh_v7 {
2919	u8 fver;
2920	u8 map_type;
2921	u8 rsvd0;
2922	u8 rsvd1;
2923	u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */
2924	u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */
2925	u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */
2926	u8 afh_le_a[4];
2927	u8 afh_le_b[4];
2928} __packed;
2929
2930struct rtw89_btc_fbtc_btdevinfo {
2931	u8 fver; /* btc_ver::fcxbtdevinfo */
2932	u8 rsvd;
2933	__le16 vendor_id;
2934	__le32 dev_name; /* only 24 bits valid */
2935	__le32 flush_time;
2936} __packed;
2937
2938#define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
2939struct rtw89_btc_rf_trx_para {
2940	u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2941	u32 wl_rx_gain;  /* rx gain table index (TBD.) */
2942	u8 bt_tx_power; /* decrease Tx power (dB) */
2943	u8 bt_rx_gain;  /* LNA constrain level */
2944};
2945
2946struct rtw89_btc_trx_info {
2947	u8 tx_lvl;
2948	u8 rx_lvl;
2949	u8 wl_rssi;
2950	u8 bt_rssi;
2951
2952	s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2953	s8 rx_gain;  /* rx gain table index (TBD.) */
2954	s8 bt_tx_power; /* decrease Tx power (dB) */
2955	s8 bt_rx_gain;  /* LNA constrain level */
2956
2957	u8 cn; /* condition_num */
2958	s8 nhm;
2959	u8 bt_profile;
2960	u8 rsvd2;
2961
2962	u16 tx_rate;
2963	u16 rx_rate;
2964
2965	u32 tx_tp;
2966	u32 rx_tp;
2967	u32 rx_err_ratio;
2968};
2969
2970enum btc_rf_path {
2971	BTC_RF_S0 = 0,
2972	BTC_RF_S1 = 1,
2973	BTC_RF_NUM,
2974};
2975
2976struct rtw89_btc_fbtc_outsrc_set_info {
2977	u8 rf_band[BTC_RF_NUM]; /* 0:2G, 1:non-2G */
2978	u8 btg_rx[BTC_RF_NUM];
2979	u8 nbtg_tx[BTC_RF_NUM];
2980
2981	struct rtw89_mac_ax_gnt gnt_set[BTC_RF_NUM]; /* refer to btc_gnt_ctrl */
2982	struct rtw89_mac_ax_wl_act wlact_set[BTC_RF_NUM]; /* BT0/BT1 */
2983
2984	u8 pta_req_hw_band;
2985	u8 rf_gbt_source;
2986} __packed;
2987
2988union rtw89_btc_fbtc_slot_u {
2989	struct rtw89_btc_fbtc_slot v1[CXST_MAX];
2990	struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX];
2991};
2992
2993struct rtw89_btc_dm {
2994	struct rtw89_btc_fbtc_outsrc_set_info ost_info_last; /* outsrc API setup info */
2995	struct rtw89_btc_fbtc_outsrc_set_info ost_info; /* outsrc API setup info */
2996	union rtw89_btc_fbtc_slot_u slot;
2997	union rtw89_btc_fbtc_slot_u slot_now;
2998	struct rtw89_btc_fbtc_tdma tdma;
2999	struct rtw89_btc_fbtc_tdma tdma_now;
3000	struct rtw89_mac_ax_coex_gnt gnt;
3001	union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */
3002	struct rtw89_btc_rf_trx_para rf_trx_para;
3003	struct rtw89_btc_wl_tx_limit_para wl_tx_limit;
3004	struct rtw89_btc_dm_step dm_step;
3005	struct rtw89_btc_wl_scc_ctrl wl_scc;
3006	struct rtw89_btc_trx_info trx_info;
3007	union rtw89_btc_dm_error_map error;
3008	u32 cnt_dm[BTC_DCNT_NUM];
3009	u32 cnt_notify[BTC_NCNT_NUM];
3010
3011	u32 update_slot_map;
3012	u32 set_ant_path;
3013	u32 e2g_slot_limit;
3014	u32 e2g_slot_nulltx_time;
3015
3016	u32 wl_only: 1;
3017	u32 wl_fw_cx_offload: 1;
3018	u32 freerun: 1;
3019	u32 fddt_train: 1;
3020	u32 wl_ps_ctrl: 2;
3021	u32 wl_mimo_ps: 1;
3022	u32 leak_ap: 1;
3023	u32 noisy_level: 3;
3024	u32 coex_info_map: 8;
3025	u32 bt_only: 1;
3026	u32 wl_btg_rx: 2;
3027	u32 trx_para_level: 8;
3028	u32 wl_stb_chg: 1;
3029	u32 pta_owner: 1;
3030
3031	u32 tdma_instant_excute: 1;
3032	u32 wl_btg_rx_rb: 2;
3033
3034	u16 slot_dur[CXST_MAX];
3035	u16 bt_slot_flood;
3036
3037	u8 run_reason;
3038	u8 run_action;
3039
3040	u8 wl_pre_agc: 2;
3041	u8 wl_lna2: 1;
3042	u8 freerun_chk: 1;
3043	u8 wl_pre_agc_rb: 2;
3044	u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */
3045	u8 slot_req_more: 1;
3046};
3047
3048struct rtw89_btc_ctrl {
3049	u32 manual: 1;
3050	u32 igno_bt: 1;
3051	u32 always_freerun: 1;
3052	u32 trace_step: 16;
3053	u32 rsvd: 12;
3054};
3055
3056struct rtw89_btc_ctrl_v7 {
3057	u8 manual;
3058	u8 igno_bt;
3059	u8 always_freerun;
3060	u8 rsvd;
3061} __packed;
3062
3063union rtw89_btc_ctrl_list {
3064	struct rtw89_btc_ctrl ctrl;
3065	struct rtw89_btc_ctrl_v7 ctrl_v7;
3066};
3067
3068struct rtw89_btc_dbg {
3069	/* cmd "rb" */
3070	bool rb_done;
3071	u32 rb_val;
3072};
3073
3074enum rtw89_btc_btf_fw_event {
3075	BTF_EVNT_RPT = 0,
3076	BTF_EVNT_BT_INFO = 1,
3077	BTF_EVNT_BT_SCBD = 2,
3078	BTF_EVNT_BT_REG = 3,
3079	BTF_EVNT_CX_RUNINFO = 4,
3080	BTF_EVNT_BT_PSD = 5,
3081	BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */
3082	BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */
3083	BTF_EVNT_BUF_OVERFLOW,
3084	BTF_EVNT_C2H_LOOPBACK,
3085	BTF_EVNT_BT_QUERY_TXPWR, /* fwc2hfunc > 3 */
3086	BTF_EVNT_MAX,
3087};
3088
3089enum btf_fw_event_report {
3090	BTC_RPT_TYPE_CTRL = 0x0,
3091	BTC_RPT_TYPE_TDMA,
3092	BTC_RPT_TYPE_SLOT,
3093	BTC_RPT_TYPE_CYSTA,
3094	BTC_RPT_TYPE_STEP,
3095	BTC_RPT_TYPE_NULLSTA,
3096	BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */
3097	BTC_RPT_TYPE_MREG,
3098	BTC_RPT_TYPE_GPIO_DBG,
3099	BTC_RPT_TYPE_BT_VER,
3100	BTC_RPT_TYPE_BT_SCAN,
3101	BTC_RPT_TYPE_BT_AFH,
3102	BTC_RPT_TYPE_BT_DEVICE,
3103	BTC_RPT_TYPE_TEST,
3104	BTC_RPT_TYPE_MAX = 31,
3105
3106	__BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA,
3107	__BTC_RPT_TYPE_V0_MAX = 12,
3108};
3109
3110enum rtw_btc_btf_reg_type {
3111	REG_MAC = 0x0,
3112	REG_BB = 0x1,
3113	REG_RF = 0x2,
3114	REG_BT_RF = 0x3,
3115	REG_BT_MODEM = 0x4,
3116	REG_BT_BLUEWIZE = 0x5,
3117	REG_BT_VENDOR = 0x6,
3118	REG_BT_LE = 0x7,
3119	REG_MAX_TYPE,
3120};
3121
3122struct rtw89_btc_rpt_cmn_info {
3123	u32 rx_cnt;
3124	u32 rx_len;
3125	u32 req_len; /* expected rsp len */
3126	u8 req_fver; /* expected rsp fver */
3127	u8 rsp_fver; /* fver from fw */
3128	u8 valid;
3129} __packed;
3130
3131union rtw89_btc_fbtc_btafh_info {
3132	struct rtw89_btc_fbtc_btafh v1;
3133	struct rtw89_btc_fbtc_btafh_v2 v2;
3134	struct rtw89_btc_fbtc_btafh_v7 v7;
3135};
3136
3137struct rtw89_btc_report_ctrl_state {
3138	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3139	union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo;
3140};
3141
3142struct rtw89_btc_rpt_fbtc_tdma {
3143	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3144	union rtw89_btc_fbtc_tdma_le32 finfo;
3145};
3146
3147struct rtw89_btc_rpt_fbtc_slots {
3148	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3149	union rtw89_btc_fbtc_slots_info finfo; /* info from fw */
3150};
3151
3152struct rtw89_btc_rpt_fbtc_cysta {
3153	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3154	union rtw89_btc_fbtc_cysta_info finfo;
3155};
3156
3157struct rtw89_btc_rpt_fbtc_step {
3158	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3159	union rtw89_btc_fbtc_steps_info finfo; /* info from fw */
3160};
3161
3162struct rtw89_btc_rpt_fbtc_nullsta {
3163	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3164	union rtw89_btc_fbtc_cynullsta_info finfo;
3165};
3166
3167struct rtw89_btc_rpt_fbtc_mreg {
3168	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3169	union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */
3170};
3171
3172struct rtw89_btc_rpt_fbtc_gpio_dbg {
3173	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3174	union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */
3175};
3176
3177struct rtw89_btc_rpt_fbtc_btver {
3178	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3179	union rtw89_btc_fbtc_btver finfo; /* info from fw */
3180};
3181
3182struct rtw89_btc_rpt_fbtc_btscan {
3183	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3184	union rtw89_btc_fbtc_btscan finfo; /* info from fw */
3185};
3186
3187struct rtw89_btc_rpt_fbtc_btafh {
3188	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3189	union rtw89_btc_fbtc_btafh_info finfo;
3190};
3191
3192struct rtw89_btc_rpt_fbtc_btdev {
3193	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3194	struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */
3195};
3196
3197enum rtw89_btc_btfre_type {
3198	BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
3199	BTFRE_UNDEF_TYPE,
3200	BTFRE_EXCEPTION,
3201	BTFRE_MAX,
3202};
3203
3204struct rtw89_btc_ver {
3205	enum rtw89_core_chip_id chip_id;
3206	u32 fw_ver_code;
3207
3208	u8 fcxbtcrpt;
3209	u8 fcxtdma;
3210	u8 fcxslots;
3211	u8 fcxcysta;
3212	u8 fcxstep;
3213	u8 fcxnullsta;
3214	u8 fcxmreg;
3215	u8 fcxgpiodbg;
3216	u8 fcxbtver;
3217	u8 fcxbtscan;
3218	u8 fcxbtafh;
3219	u8 fcxbtdevinfo;
3220	u8 fwlrole;
3221	u8 frptmap;
3222	u8 fcxctrl;
3223	u8 fcxinit;
3224
3225	u8 fwevntrptl;
3226	u8 fwc2hfunc;
3227	u8 drvinfo_type;
3228	u16 info_buf;
3229	u8 max_role_num;
3230	u8 fcxosi;
3231	u8 fcxmlo;
3232	u8 bt_desired;
3233};
3234
3235struct rtw89_btc_btf_fwinfo {
3236	u32 cnt_c2h;
3237	u32 cnt_h2c;
3238	u32 cnt_h2c_fail;
3239	u32 event[BTF_EVNT_MAX];
3240
3241	u32 err[BTFRE_MAX];
3242	u32 len_mismch;
3243	u32 fver_mismch;
3244	u32 rpt_en_map;
3245
3246	struct rtw89_btc_ver fw_subver;
3247	struct rtw89_btc_report_ctrl_state rpt_ctrl;
3248	struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma;
3249	struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots;
3250	struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta;
3251	struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step;
3252	struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta;
3253	struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval;
3254	struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;
3255	struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver;
3256	struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan;
3257	struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh;
3258	struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev;
3259};
3260
3261#define RTW89_BTC_POLICY_MAXLEN 512
3262
3263struct rtw89_btc {
3264	const struct rtw89_btc_ver *ver;
3265
3266	struct rtw89_btc_cx cx;
3267	struct rtw89_btc_dm dm;
3268	union rtw89_btc_ctrl_list ctrl;
3269	union rtw89_btc_module_info mdinfo;
3270	struct rtw89_btc_btf_fwinfo fwinfo;
3271	struct rtw89_btc_dbg dbg;
3272
3273	struct wiphy_work eapol_notify_work;
3274	struct wiphy_work arp_notify_work;
3275	struct wiphy_work dhcp_notify_work;
3276	struct wiphy_work icmp_notify_work;
3277
3278	u32 bt_req_len;
3279
3280	u8 policy[RTW89_BTC_POLICY_MAXLEN];
3281	u8 ant_type;
3282	u8 btg_pos;
3283	u16 policy_len;
3284	u16 policy_type;
3285	u32 hubmsg_cnt;
3286	bool bt_req_en;
3287	bool update_policy_force;
3288	bool lps;
3289	bool manual_ctrl;
3290};
3291
3292enum rtw89_btc_hmsg {
3293	RTW89_BTC_HMSG_TMR_EN = 0x0,
3294	RTW89_BTC_HMSG_BT_REG_READBACK = 0x1,
3295	RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2,
3296	RTW89_BTC_HMSG_FW_EV = 0x3,
3297	RTW89_BTC_HMSG_BT_LINK_CHG = 0x4,
3298	RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5,
3299
3300	NUM_OF_RTW89_BTC_HMSG,
3301};
3302
3303enum rtw89_ra_mode {
3304	RTW89_RA_MODE_CCK = BIT(0),
3305	RTW89_RA_MODE_OFDM = BIT(1),
3306	RTW89_RA_MODE_HT = BIT(2),
3307	RTW89_RA_MODE_VHT = BIT(3),
3308	RTW89_RA_MODE_HE = BIT(4),
3309	RTW89_RA_MODE_EHT = BIT(5),
3310};
3311
3312enum rtw89_ra_report_mode {
3313	RTW89_RA_RPT_MODE_LEGACY,
3314	RTW89_RA_RPT_MODE_HT,
3315	RTW89_RA_RPT_MODE_VHT,
3316	RTW89_RA_RPT_MODE_HE,
3317	RTW89_RA_RPT_MODE_EHT,
3318};
3319
3320enum rtw89_dig_noisy_level {
3321	RTW89_DIG_NOISY_LEVEL0 = -1,
3322	RTW89_DIG_NOISY_LEVEL1 = 0,
3323	RTW89_DIG_NOISY_LEVEL2 = 1,
3324	RTW89_DIG_NOISY_LEVEL3 = 2,
3325	RTW89_DIG_NOISY_LEVEL_MAX = 3,
3326};
3327
3328enum rtw89_gi_ltf {
3329	RTW89_GILTF_LGI_4XHE32 = 0,
3330	RTW89_GILTF_SGI_4XHE08 = 1,
3331	RTW89_GILTF_2XHE16 = 2,
3332	RTW89_GILTF_2XHE08 = 3,
3333	RTW89_GILTF_1XHE16 = 4,
3334	RTW89_GILTF_1XHE08 = 5,
3335	RTW89_GILTF_MAX
3336};
3337
3338enum rtw89_rx_frame_type {
3339	RTW89_RX_TYPE_MGNT = 0,
3340	RTW89_RX_TYPE_CTRL = 1,
3341	RTW89_RX_TYPE_DATA = 2,
3342	RTW89_RX_TYPE_RSVD = 3,
3343};
3344
3345enum rtw89_efuse_block {
3346	RTW89_EFUSE_BLOCK_SYS = 0,
3347	RTW89_EFUSE_BLOCK_RF = 1,
3348	RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2,
3349	RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3,
3350	RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4,
3351	RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5,
3352	RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6,
3353	RTW89_EFUSE_BLOCK_ADIE = 7,
3354
3355	RTW89_EFUSE_BLOCK_NUM,
3356	RTW89_EFUSE_BLOCK_IGNORE,
3357};
3358
3359struct rtw89_ra_info {
3360	u8 is_dis_ra:1;
3361	/* Bit0 : CCK
3362	 * Bit1 : OFDM
3363	 * Bit2 : HT
3364	 * Bit3 : VHT
3365	 * Bit4 : HE
3366	 * Bit5 : EHT
3367	 */
3368	u8 mode_ctrl:6;
3369	u8 bw_cap:3; /* enum rtw89_bandwidth */
3370	u8 macid;
3371	u8 dcm_cap:1;
3372	u8 er_cap:1;
3373	u8 init_rate_lv:2;
3374	u8 upd_all:1;
3375	u8 en_sgi:1;
3376	u8 ldpc_cap:1;
3377	u8 stbc_cap:1;
3378	u8 ss_num:3;
3379	u8 giltf:3;
3380	u8 upd_bw_nss_mask:1;
3381	u8 upd_mask:1;
3382	u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */
3383	/* BFee CSI */
3384	u8 band_num;
3385	u8 ra_csi_rate_en:1;
3386	u8 fixed_csi_rate_en:1;
3387	u8 cr_tbl_sel:1;
3388	u8 fix_giltf_en:1;
3389	u8 fix_giltf:3;
3390	u8 partial_bw_er:1;
3391	u8 csi_mcs_ss_idx;
3392	u8 csi_mode:2;
3393	u8 csi_gi_ltf:3;
3394	u8 csi_bw:3;
3395	/* after v1 */
3396	u8 is_noisy:1;
3397	u8 psra_en:1;
3398	u8 rsvd0:1;
3399	u8 macid_msb:2;
3400	u8 band:2; /* enum rtw89_band */
3401	u8 is_new_dbgreg:1;
3402};
3403
3404#define RTW89_PPDU_MAC_INFO_USR_SIZE 4
3405#define RTW89_PPDU_MAC_INFO_SIZE 8
3406#define RTW89_PPDU_MAC_RX_CNT_SIZE 96
3407#define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128
3408
3409#define RTW89_MAX_RX_AGG_NUM 64
3410#define RTW89_MAX_TX_AGG_NUM 128
3411
3412struct rtw89_ampdu_params {
3413	u16 agg_num;
3414	bool amsdu;
3415};
3416
3417struct rtw89_ra_report {
3418	struct rate_info txrate;
3419	u32 bit_rate;
3420	u16 hw_rate;
3421	bool might_fallback_legacy;
3422};
3423
3424DECLARE_EWMA(rssi, 10, 16);
3425DECLARE_EWMA(evm, 10, 16);
3426DECLARE_EWMA(snr, 10, 16);
3427
3428struct rtw89_ba_cam_entry {
3429	struct list_head list;
3430	u8 tid;
3431};
3432
3433#define RTW89_MAX_ADDR_CAM_NUM		128
3434#define RTW89_MAX_BSSID_CAM_NUM		20
3435#define RTW89_MAX_SEC_CAM_NUM		128
3436#define RTW89_MAX_BA_CAM_NUM		24
3437#define RTW89_SEC_CAM_IN_ADDR_CAM	7
3438
3439struct rtw89_addr_cam_entry {
3440	u8 addr_cam_idx;
3441	u8 offset;
3442	u8 len;
3443	u8 valid	: 1;
3444	u8 addr_mask	: 6;
3445	u8 wapi		: 1;
3446	u8 mask_sel	: 2;
3447	u8 bssid_cam_idx: 6;
3448
3449	u8 sec_ent_mode;
3450	DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM);
3451	u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM];
3452	u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM];
3453};
3454
3455struct rtw89_bssid_cam_entry {
3456	u8 bssid[ETH_ALEN];
3457	u8 phy_idx;
3458	u8 bssid_cam_idx;
3459	u8 offset;
3460	u8 len;
3461	u8 valid : 1;
3462	u8 num;
3463};
3464
3465struct rtw89_sec_cam_entry {
3466	u8 sec_cam_idx;
3467	u8 offset;
3468	u8 len;
3469	u8 type : 4;
3470	u8 ext_key : 1;
3471	u8 spp_mode : 1;
3472	/* 256 bits */
3473	u8 key[32];
3474
3475	struct ieee80211_key_conf *key_conf;
3476};
3477
3478struct rtw89_sta_link {
3479	struct rtw89_sta *rtwsta;
3480	struct list_head dlink_schd;
3481	unsigned int link_id;
3482
3483	u8 mac_id;
3484	u8 tx_retry;
3485	bool er_cap;
3486	struct rtw89_vif_link *rtwvif_link;
3487	struct rtw89_ra_info ra;
3488	struct rtw89_ra_report ra_report;
3489	int max_agg_wait;
3490	u8 prev_rssi;
3491	struct ewma_rssi avg_rssi;
3492	struct ewma_rssi rssi[RF_PATH_MAX];
3493	struct ewma_snr avg_snr;
3494	struct ewma_evm evm_1ss;
3495	struct ewma_evm evm_min[RF_PATH_MAX];
3496	struct ewma_evm evm_max[RF_PATH_MAX];
3497	struct ieee80211_rx_status rx_status;
3498	u16 rx_hw_rate;
3499	__le32 htc_template;
3500	struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */
3501	struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */
3502	struct list_head ba_cam_list;
3503
3504	bool use_cfg_mask;
3505	struct cfg80211_bitrate_mask mask;
3506
3507	bool cctl_tx_time;
3508	u32 ampdu_max_time:4;
3509	bool cctl_tx_retry_limit;
3510	u32 data_tx_cnt_lmt:6;
3511};
3512
3513struct rtw89_efuse {
3514	bool valid;
3515	bool power_k_valid;
3516	u8 xtal_cap;
3517	u8 addr[ETH_ALEN];
3518	u8 rfe_type;
3519	char country_code[2];
3520	u8 adc_td;
3521};
3522
3523struct rtw89_phy_rate_pattern {
3524	u64 ra_mask;
3525	u16 rate;
3526	u8 ra_mode;
3527	bool enable;
3528};
3529
3530#define RTW89_TX_DONE			0x0
3531#define RTW89_TX_RETRY_LIMIT		0x1
3532#define RTW89_TX_LIFE_TIME		0x2
3533#define RTW89_TX_MACID_DROP		0x3
3534
3535#define RTW89_MAX_TX_RPTS		16
3536#define RTW89_MAX_TX_RPTS_MASK		(RTW89_MAX_TX_RPTS - 1)
3537struct rtw89_tx_rpt {
3538	struct sk_buff *skbs[RTW89_MAX_TX_RPTS];
3539	/* protect skbs array access/modification */
3540	spinlock_t skb_lock;
3541	atomic_t sn;
3542};
3543
3544#define RTW89_TX_WAIT_WORK_TIMEOUT msecs_to_jiffies(500)
3545struct rtw89_tx_wait_info {
3546	struct rcu_head rcu_head;
3547	struct list_head list;
3548	struct completion completion;
3549	struct sk_buff *skb;
3550	bool tx_done;
3551};
3552
3553struct rtw89_tx_skb_data {
3554	struct rtw89_tx_wait_info __rcu *wait;
3555	u8 tx_rpt_sn;
3556	u8 tx_pkt_cnt_lmt;
3557	u8 hci_priv[];
3558};
3559
3560#define RTW89_SCAN_NULL_TIMEOUT 30
3561
3562#define RTW89_ROC_IDLE_TIMEOUT 500
3563#define RTW89_ROC_TX_TIMEOUT 30
3564enum rtw89_roc_state {
3565	RTW89_ROC_IDLE,
3566	RTW89_ROC_NORMAL,
3567	RTW89_ROC_MGMT,
3568};
3569
3570struct rtw89_roc {
3571	struct ieee80211_channel chan;
3572	struct wiphy_delayed_work roc_work;
3573	enum ieee80211_roc_type type;
3574	enum rtw89_roc_state state;
3575	int duration;
3576	unsigned int link_id;
3577};
3578
3579#define RTW89_P2P_MAX_NOA_NUM 2
3580
3581struct rtw89_p2p_ie_head {
3582	u8 eid;
3583	u8 ie_len;
3584	u8 oui[3];
3585	u8 oui_type;
3586} __packed;
3587
3588struct rtw89_noa_attr_head {
3589	u8 attr_type;
3590	__le16 attr_len;
3591	u8 index;
3592	u8 oppps_ctwindow;
3593} __packed;
3594
3595struct rtw89_p2p_noa_ie {
3596	struct rtw89_p2p_ie_head p2p_head;
3597	struct rtw89_noa_attr_head noa_head;
3598	struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM];
3599} __packed;
3600
3601struct rtw89_p2p_noa_setter {
3602	struct rtw89_p2p_noa_ie ie;
3603	u8 noa_count;
3604	u8 noa_index;
3605};
3606
3607struct rtw89_ps_noa_once_handler {
3608	bool in_duration;
3609	u64 tsf_begin;
3610	u64 tsf_end;
3611	struct wiphy_delayed_work set_work;
3612	struct wiphy_delayed_work clr_work;
3613};
3614
3615struct rtw89_vif_link {
3616	struct rtw89_vif *rtwvif;
3617	struct list_head dlink_schd;
3618	unsigned int link_id;
3619
3620	bool chanctx_assigned; /* only valid when running with chanctx_ops */
3621	enum rtw89_chanctx_idx chanctx_idx;
3622	enum rtw89_reg_6ghz_power reg_6ghz_power;
3623	struct rtw89_reg_6ghz_tpe reg_6ghz_tpe;
3624
3625	u8 mac_id;
3626	u8 port;
3627	u8 mac_addr[ETH_ALEN];
3628	u8 bssid[ETH_ALEN];
3629	u8 phy_idx;
3630	u8 mac_idx;
3631	u8 net_type;
3632	u8 wifi_role;
3633	u8 self_role;
3634	u8 wmm;
3635	u8 bcn_hit_cond;
3636	u8 bcn_bw_idx;
3637	u8 hit_rule;
3638	u8 last_noa_nr;
3639	u64 sync_bcn_tsf;
3640	u64 last_sync_bcn_tsf;
3641	bool rand_tsf_done;
3642	bool trigger;
3643	bool lsig_txop;
3644	u8 tgt_ind;
3645	u8 frm_tgt_ind;
3646	bool wowlan_pattern;
3647	bool wowlan_uc;
3648	bool wowlan_magic;
3649	bool is_hesta;
3650	bool last_a_ctrl;
3651	bool dyn_tb_bedge_en;
3652	bool pre_pwr_diff_en;
3653	bool pwr_diff_en;
3654	u8 def_tri_idx;
3655	struct wiphy_work update_beacon_work;
3656	struct wiphy_delayed_work csa_beacon_work;
3657	struct rtw89_addr_cam_entry addr_cam;
3658	struct rtw89_bssid_cam_entry bssid_cam;
3659	struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
3660	struct rtw89_phy_rate_pattern rate_pattern;
3661	struct list_head general_pkt_list;
3662	struct rtw89_p2p_noa_setter p2p_noa;
3663	struct rtw89_ps_noa_once_handler noa_once;
3664	struct wiphy_delayed_work mcc_gc_detect_beacon_work;
3665	u8 detect_bcn_count;
3666};
3667
3668enum rtw89_lv1_rcvy_step {
3669	RTW89_LV1_RCVY_STEP_1,
3670	RTW89_LV1_RCVY_STEP_2,
3671};
3672
3673struct rtw89_hci_ops {
3674	int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req);
3675	void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch);
3676	void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop);
3677	void (*reset)(struct rtw89_dev *rtwdev);
3678	int (*start)(struct rtw89_dev *rtwdev);
3679	void (*stop)(struct rtw89_dev *rtwdev);
3680	void (*pause)(struct rtw89_dev *rtwdev, bool pause);
3681	void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power);
3682	void (*recalc_int_mit)(struct rtw89_dev *rtwdev);
3683
3684	u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr);
3685	u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr);
3686	u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);
3687	void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
3688	void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
3689	void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
3690
3691	u32 (*read32_pci_cfg)(struct rtw89_dev *rtwdev, u32 addr);
3692
3693	int (*mac_pre_init)(struct rtw89_dev *rtwdev);
3694	int (*mac_pre_deinit)(struct rtw89_dev *rtwdev);
3695	int (*mac_post_init)(struct rtw89_dev *rtwdev);
3696	int (*deinit)(struct rtw89_dev *rtwdev);
3697
3698	u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch);
3699	int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step);
3700	void (*dump_err_status)(struct rtw89_dev *rtwdev);
3701	int (*napi_poll)(struct napi_struct *napi, int budget);
3702
3703	/* Deal with locks inside recovery_start and recovery_complete callbacks
3704	 * by hci instance, and handle things which need to consider under SER.
3705	 * e.g. turn on/off interrupts except for the one for halt notification.
3706	 */
3707	void (*recovery_start)(struct rtw89_dev *rtwdev);
3708	void (*recovery_complete)(struct rtw89_dev *rtwdev);
3709
3710	void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable);
3711	void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable);
3712	void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable);
3713	int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev);
3714	void (*clr_idx_all)(struct rtw89_dev *rtwdev);
3715	void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev);
3716	void (*disable_intr)(struct rtw89_dev *rtwdev);
3717	void (*enable_intr)(struct rtw89_dev *rtwdev);
3718	int (*rst_bdram)(struct rtw89_dev *rtwdev);
3719};
3720
3721struct rtw89_hci_info {
3722	const struct rtw89_hci_ops *ops;
3723	enum rtw89_hci_type type;
3724	enum rtw89_hci_dle_type dle_type;
3725	u32 rpwm_addr;
3726	u32 cpwm_addr;
3727	bool paused;
3728	bool tx_rpt_enabled;
3729};
3730
3731struct rtw89_chip_ops {
3732	int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
3733	int (*disable_bb_rf)(struct rtw89_dev *rtwdev);
3734	void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3735	void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3736	void (*bb_reset)(struct rtw89_dev *rtwdev,
3737			 enum rtw89_phy_idx phy_idx);
3738	void (*bb_sethw)(struct rtw89_dev *rtwdev);
3739	u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3740		       u32 addr, u32 mask);
3741	bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3742			 u32 addr, u32 mask, u32 data);
3743	void (*set_channel)(struct rtw89_dev *rtwdev,
3744			    const struct rtw89_chan *chan,
3745			    enum rtw89_mac_idx mac_idx,
3746			    enum rtw89_phy_idx phy_idx);
3747	void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter,
3748				 struct rtw89_channel_help_params *p,
3749				 const struct rtw89_chan *chan,
3750				 enum rtw89_mac_idx mac_idx,
3751				 enum rtw89_phy_idx phy_idx);
3752	int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map,
3753			  enum rtw89_efuse_block block);
3754	int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
3755	void (*fem_setup)(struct rtw89_dev *rtwdev);
3756	void (*rfe_gpio)(struct rtw89_dev *rtwdev);
3757	void (*rfk_hw_init)(struct rtw89_dev *rtwdev);
3758	void (*rfk_init)(struct rtw89_dev *rtwdev);
3759	void (*rfk_init_late)(struct rtw89_dev *rtwdev);
3760	void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
3761	void (*rfk_band_changed)(struct rtw89_dev *rtwdev,
3762				 enum rtw89_phy_idx phy_idx,
3763				 const struct rtw89_chan *chan);
3764	void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
3765			 bool start);
3766	void (*rfk_track)(struct rtw89_dev *rtwdev);
3767	void (*power_trim)(struct rtw89_dev *rtwdev);
3768	void (*set_txpwr)(struct rtw89_dev *rtwdev,
3769			  const struct rtw89_chan *chan,
3770			  enum rtw89_phy_idx phy_idx);
3771	void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev,
3772			       enum rtw89_phy_idx phy_idx);
3773	int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3774	u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
3775	u32 (*chan_to_rf18_val)(struct rtw89_dev *rtwdev,
3776				const struct rtw89_chan *chan);
3777	void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en,
3778			       enum rtw89_phy_idx phy_idx);
3779	void (*query_ppdu)(struct rtw89_dev *rtwdev,
3780			   struct rtw89_rx_phy_ppdu *phy_ppdu,
3781			   struct ieee80211_rx_status *status);
3782	void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev,
3783				    struct rtw89_rx_phy_ppdu *phy_ppdu);
3784	void (*phy_rpt_to_rssi)(struct rtw89_dev *rtwdev,
3785				struct rtw89_rx_desc_info *desc_info,
3786				struct ieee80211_rx_status *rx_status);
3787	void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en,
3788				enum rtw89_phy_idx phy_idx);
3789	void (*cfg_txrx_path)(struct rtw89_dev *rtwdev);
3790	void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,
3791				       s8 pw_ofst, enum rtw89_mac_idx mac_idx);
3792	void (*digital_pwr_comp)(struct rtw89_dev *rtwdev,
3793				 enum rtw89_phy_idx phy_idx);
3794	int (*pwr_on_func)(struct rtw89_dev *rtwdev);
3795	int (*pwr_off_func)(struct rtw89_dev *rtwdev);
3796	void (*query_rxdesc)(struct rtw89_dev *rtwdev,
3797			     struct rtw89_rx_desc_info *desc_info,
3798			     u8 *data, u32 data_offset);
3799	void (*fill_txdesc)(struct rtw89_dev *rtwdev,
3800			    struct rtw89_tx_desc_info *desc_info,
3801			    void *txdesc);
3802	void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev,
3803				  struct rtw89_tx_desc_info *desc_info,
3804				  void *txdesc);
3805	u8 (*get_ch_dma[RTW89_HCI_TYPE_NUM])(struct rtw89_dev *rtwdev, u8 qsel);
3806	int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl);
3807	int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev,
3808			   const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
3809	int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx,
3810			   u32 *tx_en, enum rtw89_sch_tx_sel sel);
3811	int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
3812	int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev,
3813				struct rtw89_vif_link *rtwvif_link,
3814				struct rtw89_sta_link *rtwsta_link);
3815	int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev,
3816				    struct rtw89_vif_link *rtwvif_link,
3817				    struct rtw89_sta_link *rtwsta_link);
3818	int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev,
3819				  struct rtw89_vif_link *rtwvif_link,
3820				  struct rtw89_sta_link *rtwsta_link);
3821	int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev,
3822				  struct rtw89_vif_link *rtwvif_link,
3823				  struct rtw89_sta_link *rtwsta_link);
3824	int (*h2c_txtime_cmac_tbl)(struct rtw89_dev *rtwdev,
3825				   struct rtw89_sta_link *rtwsta_link);
3826	int (*h2c_punctured_cmac_tbl)(struct rtw89_dev *rtwdev,
3827				      struct rtw89_vif_link *rtwvif_link,
3828				      u16 punctured);
3829	int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev,
3830				    struct rtw89_vif_link *rtwvif_link,
3831				    struct rtw89_sta_link *rtwsta_link);
3832	int (*h2c_update_beacon)(struct rtw89_dev *rtwdev,
3833				 struct rtw89_vif_link *rtwvif_link);
3834	int (*h2c_ba_cam)(struct rtw89_dev *rtwdev,
3835			  struct rtw89_vif_link *rtwvif_link,
3836			  struct rtw89_sta_link *rtwsta_link,
3837			  bool valid, struct ieee80211_ampdu_params *params);
3838
3839	void (*btc_set_rfe)(struct rtw89_dev *rtwdev);
3840	void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
3841	void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
3842	void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
3843	s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
3844	void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
3845	void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
3846	void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type);
3847	void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level);
3848};
3849
3850enum rtw89_dma_ch {
3851	RTW89_DMA_ACH0 = 0,
3852	RTW89_DMA_ACH1 = 1,
3853	RTW89_DMA_ACH2 = 2,
3854	RTW89_DMA_ACH3 = 3,
3855	RTW89_DMA_ACH4 = 4,
3856	RTW89_DMA_ACH5 = 5,
3857	RTW89_DMA_ACH6 = 6,
3858	RTW89_DMA_ACH7 = 7,
3859	RTW89_DMA_B0MG = 8,
3860	RTW89_DMA_B0HI = 9,
3861	RTW89_DMA_B1MG = 10,
3862	RTW89_DMA_B1HI = 11,
3863	RTW89_DMA_H2C = 12,
3864	RTW89_DMA_CH_NUM = 13
3865};
3866
3867#define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0))
3868
3869enum rtw89_mlo_dbcc_mode {
3870	MLO_DBCC_NOT_SUPPORT = 1,
3871	MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1),
3872	MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2),
3873	MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1),
3874	MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2),
3875	MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1),
3876	MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2),
3877	MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2),
3878	DBCC_LEGACY = 0xffffffff,
3879};
3880
3881enum rtw89_scan_be_operation {
3882	RTW89_SCAN_OP_STOP,
3883	RTW89_SCAN_OP_START,
3884	RTW89_SCAN_OP_SETPARM,
3885	RTW89_SCAN_OP_GETRPT,
3886	RTW89_SCAN_OP_NUM
3887};
3888
3889enum rtw89_scan_be_mode {
3890	RTW89_SCAN_MODE_SA,
3891	RTW89_SCAN_MODE_MACC,
3892	RTW89_SCAN_MODE_NUM
3893};
3894
3895enum rtw89_scan_be_opmode {
3896	RTW89_SCAN_OPMODE_NONE,
3897	RTW89_SCAN_OPMODE_TBTT,
3898	RTW89_SCAN_OPMODE_INTV,
3899	RTW89_SCAN_OPMODE_CNT,
3900	RTW89_SCAN_OPMODE_NUM,
3901};
3902
3903struct rtw89_scan_option {
3904	bool enable;
3905	bool target_ch_mode;
3906	u8 num_macc_role;
3907	u8 num_opch;
3908	u8 repeat;
3909	u16 norm_pd;
3910	u16 slow_pd;
3911	u16 norm_cy;
3912	u8 opch_end;
3913	u16 delay; /* in unit of ms */
3914	u64 prohib_chan;
3915	enum rtw89_phy_idx band;
3916	enum rtw89_scan_be_operation operation;
3917	enum rtw89_scan_be_mode scan_mode;
3918	enum rtw89_mlo_dbcc_mode mlo_mode;
3919};
3920
3921enum rtw89_qta_mode {
3922	RTW89_QTA_SCC,
3923	RTW89_QTA_DBCC,
3924	RTW89_QTA_DLFW,
3925	RTW89_QTA_WOW,
3926
3927	/* keep last */
3928	RTW89_QTA_INVALID,
3929};
3930
3931struct rtw89_hfc_ch_cfg {
3932	u16 min;
3933	u16 max;
3934#define grp_0 0
3935#define grp_1 1
3936#define grp_num 2
3937	u8 grp;
3938};
3939
3940struct rtw89_hfc_ch_info {
3941	u16 aval;
3942	u16 used;
3943};
3944
3945struct rtw89_hfc_pub_cfg {
3946	u16 grp0;
3947	u16 grp1;
3948	u16 pub_max;
3949	u16 wp_thrd;
3950};
3951
3952struct rtw89_hfc_pub_info {
3953	u16 g0_used;
3954	u16 g1_used;
3955	u16 g0_aval;
3956	u16 g1_aval;
3957	u16 pub_aval;
3958	u16 wp_aval;
3959};
3960
3961struct rtw89_hfc_prec_cfg {
3962	u16 ch011_prec;
3963	u16 h2c_prec;
3964	u16 wp_ch07_prec;
3965	u16 wp_ch811_prec;
3966	u8 ch011_full_cond;
3967	u8 h2c_full_cond;
3968	u8 wp_ch07_full_cond;
3969	u8 wp_ch811_full_cond;
3970};
3971
3972struct rtw89_hfc_param {
3973	bool en;
3974	bool h2c_en;
3975	u8 mode;
3976	const struct rtw89_hfc_ch_cfg *ch_cfg;
3977	struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM];
3978	struct rtw89_hfc_pub_cfg pub_cfg;
3979	struct rtw89_hfc_pub_info pub_info;
3980	struct rtw89_hfc_prec_cfg prec_cfg;
3981};
3982
3983struct rtw89_hfc_param_ini {
3984	const struct rtw89_hfc_ch_cfg *ch_cfg;
3985	const struct rtw89_hfc_pub_cfg *pub_cfg;
3986	const struct rtw89_hfc_prec_cfg *prec_cfg;
3987	u8 mode;
3988};
3989
3990struct rtw89_dle_size {
3991	u16 pge_size;
3992	u16 lnk_pge_num;
3993	u16 unlnk_pge_num;
3994	/* for WiFi 7 chips below */
3995	u32 srt_ofst;
3996};
3997
3998struct rtw89_wde_quota {
3999	u16 hif;
4000	u16 wcpu;
4001	u16 pkt_in;
4002	u16 cpu_io;
4003};
4004
4005struct rtw89_ple_quota {
4006	u16 cma0_tx;
4007	u16 cma1_tx;
4008	u16 c2h;
4009	u16 h2c;
4010	u16 wcpu;
4011	u16 mpdu_proc;
4012	u16 cma0_dma;
4013	u16 cma1_dma;
4014	u16 bb_rpt;
4015	u16 wd_rel;
4016	u16 cpu_io;
4017	u16 tx_rpt;
4018	/* for WiFi 7 chips below */
4019	u16 h2d;
4020};
4021
4022struct rtw89_rsvd_quota {
4023	u16 mpdu_info_tbl;
4024	u16 b0_csi;
4025	u16 b1_csi;
4026	u16 b0_lmr;
4027	u16 b1_lmr;
4028	u16 b0_ftm;
4029	u16 b1_ftm;
4030	u16 b0_smr;
4031	u16 b1_smr;
4032	u16 others;
4033};
4034
4035struct rtw89_dle_rsvd_size {
4036	u32 srt_ofst;
4037	u32 size;
4038};
4039
4040struct rtw89_dle_mem {
4041	enum rtw89_qta_mode mode;
4042	const struct rtw89_dle_size *wde_size;
4043	const struct rtw89_dle_size *ple_size;
4044	const struct rtw89_wde_quota *wde_min_qt;
4045	const struct rtw89_wde_quota *wde_max_qt;
4046	const struct rtw89_ple_quota *ple_min_qt;
4047	const struct rtw89_ple_quota *ple_max_qt;
4048	/* for WiFi 7 chips below */
4049	const struct rtw89_rsvd_quota *rsvd_qt;
4050	const struct rtw89_dle_rsvd_size *rsvd0_size;
4051	const struct rtw89_dle_rsvd_size *rsvd1_size;
4052};
4053
4054struct rtw89_reg_def {
4055	u32 addr;
4056	u32 mask;
4057};
4058
4059struct rtw89_reg2_def {
4060	u32 addr;
4061	u32 data;
4062};
4063
4064struct rtw89_reg3_def {
4065	u32 addr;
4066	u32 mask;
4067	u32 data;
4068};
4069
4070struct rtw89_reg5_def {
4071	u8 flag; /* recognized by parsers */
4072	u8 path;
4073	u32 addr;
4074	u32 mask;
4075	u32 data;
4076};
4077
4078struct rtw89_reg_imr {
4079	u32 addr;
4080	u32 clr;
4081	u32 set;
4082};
4083
4084struct rtw89_phy_table {
4085	const struct rtw89_reg2_def *regs;
4086	u32 n_regs;
4087	enum rtw89_rf_path rf_path;
4088	void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
4089		       enum rtw89_rf_path rf_path, void *data);
4090};
4091
4092struct rtw89_txpwr_table {
4093	const void *data;
4094	u32 size;
4095	void (*load)(struct rtw89_dev *rtwdev,
4096		     const struct rtw89_txpwr_table *tbl);
4097};
4098
4099struct rtw89_txpwr_rule_2ghz {
4100	const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
4101		       [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4102		       [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4103	const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
4104			  [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4105};
4106
4107struct rtw89_txpwr_rule_5ghz {
4108	const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
4109		       [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4110		       [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4111	const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
4112			  [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4113};
4114
4115struct rtw89_txpwr_rule_6ghz {
4116	const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
4117		       [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4118		       [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4119		       [RTW89_6G_CH_NUM];
4120	const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
4121			  [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4122			  [RTW89_6G_CH_NUM];
4123};
4124
4125struct rtw89_tx_shape {
4126	const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
4127	const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM];
4128};
4129
4130struct rtw89_rfe_parms {
4131	const struct rtw89_txpwr_table *byr_tbl;
4132	struct rtw89_txpwr_rule_2ghz rule_2ghz;
4133	struct rtw89_txpwr_rule_5ghz rule_5ghz;
4134	struct rtw89_txpwr_rule_6ghz rule_6ghz;
4135	struct rtw89_txpwr_rule_2ghz rule_da_2ghz;
4136	struct rtw89_txpwr_rule_5ghz rule_da_5ghz;
4137	struct rtw89_txpwr_rule_6ghz rule_da_6ghz;
4138	struct rtw89_tx_shape tx_shape;
4139	bool has_da;
4140};
4141
4142struct rtw89_rfe_parms_conf {
4143	const struct rtw89_rfe_parms *rfe_parms;
4144	u8 rfe_type;
4145};
4146
4147#define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0
4148
4149struct rtw89_txpwr_conf {
4150	u8 rfe_type;
4151	u8 ent_sz;
4152	u32 num_ents;
4153	const void *data;
4154};
4155
4156static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size,
4157				      const struct rtw89_txpwr_conf *conf)
4158{
4159	u8 valid_size = min(size, conf->ent_sz);
4160
4161	memcpy(entry, cursor, valid_size);
4162	return true;
4163}
4164
4165#define rtw89_txpwr_conf_valid(conf) (!!(conf)->data)
4166
4167#define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \
4168	for (typecheck(const void *, cursor), (cursor) = (conf)->data; \
4169	     (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \
4170	     (cursor) += (conf)->ent_sz) \
4171		if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf))
4172
4173struct rtw89_txpwr_byrate_data {
4174	struct rtw89_txpwr_conf conf;
4175	struct rtw89_txpwr_table tbl;
4176};
4177
4178struct rtw89_txpwr_lmt_2ghz_data {
4179	struct rtw89_txpwr_conf conf;
4180	s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
4181	    [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4182	    [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4183};
4184
4185struct rtw89_txpwr_lmt_5ghz_data {
4186	struct rtw89_txpwr_conf conf;
4187	s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
4188	    [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4189	    [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4190};
4191
4192struct rtw89_txpwr_lmt_6ghz_data {
4193	struct rtw89_txpwr_conf conf;
4194	s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
4195	    [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4196	    [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4197	    [RTW89_6G_CH_NUM];
4198};
4199
4200struct rtw89_txpwr_lmt_ru_2ghz_data {
4201	struct rtw89_txpwr_conf conf;
4202	s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4203	    [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4204};
4205
4206struct rtw89_txpwr_lmt_ru_5ghz_data {
4207	struct rtw89_txpwr_conf conf;
4208	s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4209	    [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4210};
4211
4212struct rtw89_txpwr_lmt_ru_6ghz_data {
4213	struct rtw89_txpwr_conf conf;
4214	s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4215	    [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4216	    [RTW89_6G_CH_NUM];
4217};
4218
4219struct rtw89_tx_shape_lmt_data {
4220	struct rtw89_txpwr_conf conf;
4221	u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
4222};
4223
4224struct rtw89_tx_shape_lmt_ru_data {
4225	struct rtw89_txpwr_conf conf;
4226	u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM];
4227};
4228
4229struct rtw89_rfe_data {
4230	struct rtw89_txpwr_byrate_data byrate;
4231	struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz;
4232	struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz;
4233	struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz;
4234	struct rtw89_txpwr_lmt_2ghz_data da_lmt_2ghz;
4235	struct rtw89_txpwr_lmt_5ghz_data da_lmt_5ghz;
4236	struct rtw89_txpwr_lmt_6ghz_data da_lmt_6ghz;
4237	struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz;
4238	struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz;
4239	struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz;
4240	struct rtw89_txpwr_lmt_ru_2ghz_data da_lmt_ru_2ghz;
4241	struct rtw89_txpwr_lmt_ru_5ghz_data da_lmt_ru_5ghz;
4242	struct rtw89_txpwr_lmt_ru_6ghz_data da_lmt_ru_6ghz;
4243	struct rtw89_tx_shape_lmt_data tx_shape_lmt;
4244	struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru;
4245	struct rtw89_rfe_parms rfe_parms;
4246};
4247
4248struct rtw89_page_regs {
4249	u32 hci_fc_ctrl;
4250	u32 ch_page_ctrl;
4251	u32 ach_page_ctrl;
4252	u32 ach_page_info;
4253	u32 pub_page_info3;
4254	u32 pub_page_ctrl1;
4255	u32 pub_page_ctrl2;
4256	u32 pub_page_info1;
4257	u32 pub_page_info2;
4258	u32 wp_page_ctrl1;
4259	u32 wp_page_ctrl2;
4260	u32 wp_page_info1;
4261};
4262
4263struct rtw89_imr_info {
4264	u32 wdrls_imr_set;
4265	u32 wsec_imr_reg;
4266	u32 wsec_imr_set;
4267	u32 mpdu_tx_imr_set;
4268	u32 mpdu_rx_imr_set;
4269	u32 sta_sch_imr_set;
4270	u32 txpktctl_imr_b0_reg;
4271	u32 txpktctl_imr_b0_clr;
4272	u32 txpktctl_imr_b0_set;
4273	u32 txpktctl_imr_b1_reg;
4274	u32 txpktctl_imr_b1_clr;
4275	u32 txpktctl_imr_b1_set;
4276	u32 wde_imr_clr;
4277	u32 wde_imr_set;
4278	u32 ple_imr_clr;
4279	u32 ple_imr_set;
4280	u32 host_disp_imr_clr;
4281	u32 host_disp_imr_set;
4282	u32 cpu_disp_imr_clr;
4283	u32 cpu_disp_imr_set;
4284	u32 other_disp_imr_clr;
4285	u32 other_disp_imr_set;
4286	u32 bbrpt_com_err_imr_reg;
4287	u32 bbrpt_chinfo_err_imr_reg;
4288	u32 bbrpt_err_imr_set;
4289	u32 bbrpt_dfs_err_imr_reg;
4290	u32 ptcl_imr_clr;
4291	u32 ptcl_imr_set;
4292	u32 cdma_imr_0_reg;
4293	u32 cdma_imr_0_clr;
4294	u32 cdma_imr_0_set;
4295	u32 cdma_imr_1_reg;
4296	u32 cdma_imr_1_clr;
4297	u32 cdma_imr_1_set;
4298	u32 phy_intf_imr_reg;
4299	u32 phy_intf_imr_clr;
4300	u32 phy_intf_imr_set;
4301	u32 rmac_imr_reg;
4302	u32 rmac_imr_clr;
4303	u32 rmac_imr_set;
4304	u32 tmac_imr_reg;
4305	u32 tmac_imr_clr;
4306	u32 tmac_imr_set;
4307};
4308
4309struct rtw89_imr_table {
4310	const struct rtw89_reg_imr *regs;
4311	u32 n_regs;
4312};
4313
4314struct rtw89_xtal_info {
4315	u32 xcap_reg;
4316	u32 sc_xo_mask;
4317	u32 sc_xi_mask;
4318};
4319
4320struct rtw89_rrsr_cfgs {
4321	struct rtw89_reg3_def ref_rate;
4322	struct rtw89_reg3_def rsc;
4323};
4324
4325struct rtw89_rfkill_regs {
4326	struct rtw89_reg3_def pinmux;
4327	struct rtw89_reg3_def mode;
4328};
4329
4330struct rtw89_dig_regs {
4331	u32 seg0_pd_reg;
4332	u32 pd_lower_bound_mask;
4333	u32 pd_spatial_reuse_en;
4334	u32 bmode_pd_reg;
4335	u32 bmode_cca_rssi_limit_en;
4336	u32 bmode_pd_lower_bound_reg;
4337	u32 bmode_rssi_nocca_low_th_mask;
4338	struct rtw89_reg_def p0_lna_init;
4339	struct rtw89_reg_def p1_lna_init;
4340	struct rtw89_reg_def p0_tia_init;
4341	struct rtw89_reg_def p1_tia_init;
4342	struct rtw89_reg_def p0_rxb_init;
4343	struct rtw89_reg_def p1_rxb_init;
4344	struct rtw89_reg_def p0_p20_pagcugc_en;
4345	struct rtw89_reg_def p0_s20_pagcugc_en;
4346	struct rtw89_reg_def p1_p20_pagcugc_en;
4347	struct rtw89_reg_def p1_s20_pagcugc_en;
4348};
4349
4350struct rtw89_edcca_regs {
4351	u32 edcca_level;
4352	u32 edcca_mask;
4353	u32 edcca_p_mask;
4354	u32 ppdu_level;
4355	u32 ppdu_mask;
4356	struct rtw89_edcca_p_regs {
4357		u32 rpt_a;
4358		u32 rpt_b;
4359		u32 rpt_sel;
4360		u32 rpt_sel_mask;
4361	} p[RTW89_PHY_NUM];
4362	u32 rpt_sel_be;
4363	u32 rpt_sel_be_mask;
4364	u32 tx_collision_t2r_st;
4365	u32 tx_collision_t2r_st_mask;
4366};
4367
4368struct rtw89_phy_ul_tb_info {
4369	bool dyn_tb_tri_en;
4370	u8 def_if_bandedge;
4371};
4372
4373struct rtw89_antdiv_stats {
4374	struct ewma_rssi cck_rssi_avg;
4375	struct ewma_rssi ofdm_rssi_avg;
4376	struct ewma_rssi non_legacy_rssi_avg;
4377	u16 pkt_cnt_cck;
4378	u16 pkt_cnt_ofdm;
4379	u16 pkt_cnt_non_legacy;
4380	u32 evm;
4381};
4382
4383struct rtw89_antdiv_info {
4384	struct rtw89_antdiv_stats target_stats;
4385	struct rtw89_antdiv_stats main_stats;
4386	struct rtw89_antdiv_stats aux_stats;
4387	u8 training_count;
4388	u8 rssi_pre;
4389	bool get_stats;
4390};
4391
4392enum rtw89_chanctx_state {
4393	RTW89_CHANCTX_STATE_MCC_START,
4394	RTW89_CHANCTX_STATE_MCC_STOP,
4395};
4396
4397enum rtw89_chanctx_callbacks {
4398	RTW89_CHANCTX_CALLBACK_PLACEHOLDER,
4399	RTW89_CHANCTX_CALLBACK_RFK,
4400	RTW89_CHANCTX_CALLBACK_TAS,
4401
4402	NUM_OF_RTW89_CHANCTX_CALLBACKS,
4403};
4404
4405struct rtw89_chanctx_listener {
4406	void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS])
4407		(struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state);
4408};
4409
4410#define RTW89_NHM_TH_NUM 11
4411#define RTW89_NHM_RPT_NUM 12
4412
4413struct rtw89_chip_info {
4414	enum rtw89_core_chip_id chip_id;
4415	enum rtw89_chip_gen chip_gen;
4416	const struct rtw89_chip_ops *ops;
4417	const struct rtw89_mac_gen_def *mac_def;
4418	const struct rtw89_phy_gen_def *phy_def;
4419	const char *fw_basename;
4420	u8 fw_format_max;
4421	bool try_ce_fw;
4422	u8 bbmcu_nr;
4423	u32 needed_fw_elms;
4424	const struct rtw89_fw_blacklist *fw_blacklist;
4425	u32 fifo_size;
4426	bool small_fifo_size;
4427	u32 dle_scc_rsvd_size;
4428	u16 max_amsdu_limit;
4429	bool dis_2g_40m_ul_ofdma;
4430	u32 rsvd_ple_ofst;
4431	const struct rtw89_hfc_param_ini *hfc_param_ini[RTW89_HCI_TYPE_NUM];
4432	const struct rtw89_dle_mem *dle_mem[RTW89_HCI_DLE_TYPE_NUM];
4433	u8 wde_qempty_acq_grpnum;
4434	u8 wde_qempty_mgq_grpsel;
4435	u32 rf_base_addr[2];
4436	u8 thermal_th[2];
4437	u8 support_macid_num;
4438	u8 support_link_num;
4439	u8 support_chanctx_num;
4440	u8 support_bands;
4441	u16 support_bandwidths;
4442	bool support_unii4;
4443	bool support_rnr;
4444	bool support_ant_gain;
4445	bool support_tas;
4446	bool support_sar_by_ant;
4447	bool support_noise;
4448	bool ul_tb_waveform_ctrl;
4449	bool ul_tb_pwr_diff;
4450	bool rx_freq_frome_ie;
4451	bool hw_sec_hdr;
4452	bool hw_mgmt_tx_encrypt;
4453	bool hw_tkip_crypto;
4454	bool hw_mlo_bmc_crypto;
4455	u8 rf_path_num;
4456	u8 tx_nss;
4457	u8 rx_nss;
4458	u8 acam_num;
4459	u8 bcam_num;
4460	u8 scam_num;
4461	u8 bacam_num;
4462	u8 bacam_dynamic_num;
4463	enum rtw89_bacam_ver bacam_ver;
4464	u8 addrcam_ver;
4465	u8 ppdu_max_usr;
4466
4467	u8 sec_ctrl_efuse_size;
4468	u32 physical_efuse_size;
4469	u32 logical_efuse_size;
4470	u32 limit_efuse_size;
4471	u32 dav_phy_efuse_size;
4472	u32 dav_log_efuse_size;
4473	u32 phycap_addr;
4474	u32 phycap_size;
4475	const struct rtw89_efuse_block_cfg *efuse_blocks;
4476
4477	const struct rtw89_pwr_cfg * const *pwr_on_seq;
4478	const struct rtw89_pwr_cfg * const *pwr_off_seq;
4479	const struct rtw89_phy_table *bb_table;
4480	const struct rtw89_phy_table *bb_gain_table;
4481	const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
4482	const struct rtw89_phy_table *nctl_table;
4483	const struct rtw89_rfk_tbl *nctl_post_table;
4484	const struct rtw89_phy_dig_gain_table *dig_table;
4485	const struct rtw89_dig_regs *dig_regs;
4486	const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table;
4487
4488	/* NULL if no rfe-specific, or a null-terminated array by rfe_parms */
4489	const struct rtw89_rfe_parms_conf *rfe_parms_conf;
4490	const struct rtw89_rfe_parms *dflt_parms;
4491	const struct rtw89_chanctx_listener *chanctx_listener;
4492
4493	u8 txpwr_factor_bb;
4494	u8 txpwr_factor_rf;
4495	u8 txpwr_factor_mac;
4496
4497	u32 para_ver;
4498	u32 wlcx_desired;
4499	u8 scbd;
4500	u8 mailbox;
4501
4502	u8 afh_guard_ch;
4503	const u8 *wl_rssi_thres;
4504	const u8 *bt_rssi_thres;
4505	u8 rssi_tol;
4506
4507	u8 mon_reg_num;
4508	const struct rtw89_btc_fbtc_mreg *mon_reg;
4509	u8 rf_para_ulink_num;
4510	const struct rtw89_btc_rf_trx_para *rf_para_ulink;
4511	u8 rf_para_dlink_num;
4512	const struct rtw89_btc_rf_trx_para *rf_para_dlink;
4513	u8 ps_mode_supported;
4514	u8 low_power_hci_modes;
4515
4516	u32 h2c_cctl_func_id;
4517	u32 hci_func_en_addr;
4518	u32 h2c_desc_size;
4519	u32 txwd_body_size;
4520	u32 txwd_info_size;
4521	u32 h2c_ctrl_reg;
4522	const u32 *h2c_regs;
4523	struct rtw89_reg_def h2c_counter_reg;
4524	u32 c2h_ctrl_reg;
4525	const u32 *c2h_regs;
4526	struct rtw89_reg_def c2h_counter_reg;
4527	const struct rtw89_page_regs *page_regs;
4528	const u32 *wow_reason_reg;
4529	bool cfo_src_fd;
4530	bool cfo_hw_comp;
4531	const struct rtw89_reg_def *dcfo_comp;
4532	u8 dcfo_comp_sft;
4533	const struct rtw89_reg_def (*nhm_report)[RTW89_NHM_RPT_NUM];
4534	const struct rtw89_reg_def (*nhm_th)[RTW89_NHM_TH_NUM];
4535	const struct rtw89_imr_info *imr_info;
4536	const struct rtw89_imr_table *imr_dmac_table;
4537	const struct rtw89_imr_table *imr_cmac_table;
4538	const struct rtw89_rrsr_cfgs *rrsr_cfgs;
4539	struct rtw89_reg_def bss_clr_vld;
4540	u32 bss_clr_map_reg;
4541	const struct rtw89_rfkill_regs *rfkill_init;
4542	struct rtw89_reg_def rfkill_get;
4543	u32 dma_ch_mask;
4544	const struct rtw89_edcca_regs *edcca_regs;
4545	const struct wiphy_wowlan_support *wowlan_stub;
4546	const struct rtw89_xtal_info *xtal_info;
4547};
4548
4549struct rtw89_chip_variant {
4550	bool no_mcs_12_13: 1;
4551	u32 fw_min_ver_code;
4552};
4553
4554union rtw89_bus_info {
4555	const struct rtw89_pci_info *pci;
4556	const struct rtw89_usb_info *usb;
4557};
4558
4559struct rtw89_driver_info {
4560	const struct rtw89_chip_info *chip;
4561	const struct rtw89_chip_variant *variant;
4562	const struct dmi_system_id *quirks;
4563	union rtw89_bus_info bus;
4564};
4565
4566enum rtw89_hcifc_mode {
4567	RTW89_HCIFC_POH = 0,
4568	RTW89_HCIFC_STF = 1,
4569	RTW89_HCIFC_SDIO = 2,
4570
4571	/* keep last */
4572	RTW89_HCIFC_MODE_INVALID,
4573};
4574
4575struct rtw89_dle_info {
4576	const struct rtw89_rsvd_quota *rsvd_qt;
4577	enum rtw89_qta_mode qta_mode;
4578	u16 ple_pg_size;
4579	u16 ple_free_pg;
4580	u16 c0_rx_qta;
4581	u16 c1_rx_qta;
4582};
4583
4584enum rtw89_host_rpr_mode {
4585	RTW89_RPR_MODE_POH = 0,
4586	RTW89_RPR_MODE_STF
4587};
4588
4589#define RTW89_COMPLETION_BUF_SIZE 40
4590#define RTW89_WAIT_COND_IDLE UINT_MAX
4591
4592struct rtw89_completion_data {
4593	bool err;
4594	u8 buf[RTW89_COMPLETION_BUF_SIZE];
4595};
4596
4597struct rtw89_wait_response {
4598	struct rcu_head rcu_head;
4599	struct completion completion;
4600	struct rtw89_completion_data data;
4601};
4602
4603struct rtw89_wait_info {
4604	atomic_t cond;
4605	struct rtw89_completion_data data;
4606	struct rtw89_wait_response __rcu *resp;
4607};
4608
4609#define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100)
4610
4611static inline void rtw89_init_wait(struct rtw89_wait_info *wait)
4612{
4613	rcu_assign_pointer(wait->resp, NULL);
4614	atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
4615}
4616
4617struct rtw89_mac_info {
4618	struct rtw89_dle_info dle_info;
4619	struct rtw89_hfc_param hfc_param;
4620	enum rtw89_qta_mode qta_mode;
4621	u8 rpwm_seq_num;
4622	u8 cpwm_seq_num;
4623
4624	/* see RTW89_FW_OFLD_WAIT_COND series for wait condition */
4625	struct rtw89_wait_info fw_ofld_wait;
4626	/* see RTW89_PS_WAIT_COND series for wait condition */
4627	struct rtw89_wait_info ps_wait;
4628};
4629
4630enum rtw89_fwdl_check_type {
4631	RTW89_FWDL_CHECK_FREERTOS_DONE,
4632	RTW89_FWDL_CHECK_WCPU_FWDL_DONE,
4633	RTW89_FWDL_CHECK_DCPU_FWDL_DONE,
4634	RTW89_FWDL_CHECK_BB0_FWDL_DONE,
4635	RTW89_FWDL_CHECK_BB1_FWDL_DONE,
4636};
4637
4638enum rtw89_fw_type {
4639	RTW89_FW_NORMAL = 1,
4640	RTW89_FW_WOWLAN = 3,
4641	RTW89_FW_NORMAL_CE = 5,
4642	RTW89_FW_BBMCU0 = 64,
4643	RTW89_FW_BBMCU1 = 65,
4644	RTW89_FW_LOGFMT = 255,
4645};
4646
4647#define RTW89_FW_FEATURE_GROUP(_grp, _features...) \
4648	RTW89_FW_FEATURE_##_grp##_MIN, \
4649	__RTW89_FW_FEATURE_##_grp##_S = RTW89_FW_FEATURE_##_grp##_MIN - 1, \
4650	_features \
4651	__RTW89_FW_FEATURE_##_grp##_E, \
4652	RTW89_FW_FEATURE_##_grp##_MAX = __RTW89_FW_FEATURE_##_grp##_E - 1
4653
4654enum rtw89_fw_feature {
4655	RTW89_FW_FEATURE_OLD_HT_RA_FORMAT,
4656	RTW89_FW_FEATURE_SCAN_OFFLOAD,
4657	RTW89_FW_FEATURE_TX_WAKE,
4658	RTW89_FW_FEATURE_GROUP(CRASH_TRIGGER,
4659			       RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_0,
4660			       RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_1,
4661	),
4662	RTW89_FW_FEATURE_NO_PACKET_DROP,
4663	RTW89_FW_FEATURE_NO_DEEP_PS,
4664	RTW89_FW_FEATURE_NO_LPS_PG,
4665	RTW89_FW_FEATURE_BEACON_FILTER,
4666	RTW89_FW_FEATURE_MACID_PAUSE_SLEEP,
4667	RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0,
4668	RTW89_FW_FEATURE_WOW_REASON_V1,
4669	RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0,
4670	RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V1,
4671	RTW89_FW_FEATURE_RFK_RXDCK_V0,
4672	RTW89_FW_FEATURE_RFK_IQK_V0,
4673	RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX,
4674	RTW89_FW_FEATURE_NOTIFY_AP_INFO,
4675	RTW89_FW_FEATURE_CH_INFO_BE_V0,
4676	RTW89_FW_FEATURE_LPS_CH_INFO,
4677	RTW89_FW_FEATURE_NO_PHYCAP_P1,
4678	RTW89_FW_FEATURE_NO_POWER_DIFFERENCE,
4679	RTW89_FW_FEATURE_BEACON_LOSS_COUNT_V1,
4680	RTW89_FW_FEATURE_SCAN_OFFLOAD_EXTRA_OP,
4681	RTW89_FW_FEATURE_RFK_NTFY_MCC_V0,
4682	RTW89_FW_FEATURE_LPS_DACK_BY_C2H_REG,
4683	RTW89_FW_FEATURE_BEACON_TRACKING,
4684	RTW89_FW_FEATURE_ADDR_CAM_V0,
4685};
4686
4687struct rtw89_fw_suit {
4688	enum rtw89_fw_type type;
4689	const u8 *data;
4690	u32 size;
4691	u8 major_ver;
4692	u8 minor_ver;
4693	u8 sub_ver;
4694	u8 sub_idex;
4695	u16 build_year;
4696	u16 build_mon;
4697	u16 build_date;
4698	u16 build_hour;
4699	u16 build_min;
4700	u8 cmd_ver;
4701	u8 hdr_ver;
4702	u32 commitid;
4703};
4704
4705#define RTW89_FW_VER_CODE(major, minor, sub, idx)	\
4706	(((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx))
4707#define RTW89_FW_SUIT_VER_CODE(s)	\
4708	RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex)
4709
4710#define RTW89_MFW_HDR_VER_CODE(mfw_hdr)		\
4711	RTW89_FW_VER_CODE((mfw_hdr)->ver.major,	\
4712			  (mfw_hdr)->ver.minor,	\
4713			  (mfw_hdr)->ver.sub,	\
4714			  (mfw_hdr)->ver.idx)
4715
4716#define RTW89_FW_HDR_VER_CODE(fw_hdr)				\
4717	RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION),	\
4718			  le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION),	\
4719			  le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION),	\
4720			  le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX))
4721
4722struct rtw89_fw_req_info {
4723	const struct firmware *firmware;
4724	struct completion completion;
4725};
4726
4727struct rtw89_fw_log {
4728	struct rtw89_fw_suit suit;
4729	bool enable;
4730	u32 last_fmt_id;
4731	u32 fmt_count;
4732	const __le32 *fmt_ids;
4733	const char *(*fmts)[];
4734};
4735
4736struct rtw89_fw_elm_info {
4737	struct rtw89_phy_table *bb_tbl;
4738	struct rtw89_phy_table *bb_gain;
4739	struct rtw89_phy_table *rf_radio[RF_PATH_MAX];
4740	struct rtw89_phy_table *rf_nctl;
4741	struct rtw89_fw_txpwr_track_cfg *txpwr_trk;
4742	struct rtw89_phy_rfk_log_fmt *rfk_log_fmt;
4743	const struct rtw89_regd_data *regd;
4744	const struct rtw89_fw_element_hdr *afe;
4745	const struct rtw89_fw_element_hdr *diag_mac;
4746};
4747
4748enum rtw89_fw_mss_dev_type {
4749	RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF,
4750	RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF,
4751};
4752
4753struct rtw89_fw_secure {
4754	bool secure_boot: 1;
4755	bool can_mss_v1: 1;
4756	bool can_mss_v0: 1;
4757	u32 sb_sel_mgn;
4758	u8 mss_dev_type;
4759	u8 mss_cust_idx;
4760	u8 mss_key_num;
4761	u8 mss_idx; /* v0 */
4762};
4763
4764struct rtw89_fw_info {
4765	struct rtw89_fw_req_info req;
4766	int fw_format;
4767	u8 h2c_seq;
4768	u8 rec_seq;
4769	u8 h2c_counter;
4770	u8 c2h_counter;
4771	struct rtw89_fw_suit normal;
4772	struct rtw89_fw_suit wowlan;
4773	struct rtw89_fw_suit bbmcu0;
4774	struct rtw89_fw_suit bbmcu1;
4775	struct rtw89_fw_log log;
4776	u32 feature_map;
4777	struct rtw89_fw_elm_info elm_info;
4778	struct rtw89_fw_secure sec;
4779};
4780
4781#define RTW89_CHK_FW_FEATURE(_feat, _fw) \
4782	(!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat)))
4783
4784#define RTW89_CHK_FW_FEATURE_GROUP(_grp, _fw) \
4785	(!!((_fw)->feature_map & GENMASK(RTW89_FW_FEATURE_ ## _grp ## _MAX, \
4786					 RTW89_FW_FEATURE_ ## _grp ## _MIN)))
4787
4788#define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \
4789	((_fw)->feature_map |= BIT(_fw_feature))
4790
4791struct rtw89_cam_info {
4792	DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM);
4793	DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM);
4794	DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
4795	DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM);
4796	struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM];
4797	const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM];
4798};
4799
4800enum rtw89_sar_sources {
4801	RTW89_SAR_SOURCE_NONE,
4802	RTW89_SAR_SOURCE_COMMON,
4803	RTW89_SAR_SOURCE_ACPI,
4804
4805	RTW89_SAR_SOURCE_NR,
4806};
4807
4808enum rtw89_sar_subband {
4809	RTW89_SAR_2GHZ_SUBBAND,
4810	RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */
4811	RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */
4812	RTW89_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */
4813	RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
4814	RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
4815	RTW89_SAR_6GHZ_SUBBAND_6,   /* U-NII-6 */
4816	RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
4817	RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
4818	RTW89_SAR_6GHZ_SUBBAND_8,   /* U-NII-8 */
4819
4820	RTW89_SAR_SUBBAND_NR,
4821};
4822
4823struct rtw89_sar_cfg_common {
4824	bool set[RTW89_SAR_SUBBAND_NR];
4825	s32 cfg[RTW89_SAR_SUBBAND_NR];
4826};
4827
4828enum rtw89_acpi_sar_subband {
4829	RTW89_ACPI_SAR_2GHZ_SUBBAND,
4830	RTW89_ACPI_SAR_5GHZ_SUBBAND_1,   /* U-NII-1 */
4831	RTW89_ACPI_SAR_5GHZ_SUBBAND_2,   /* U-NII-2 */
4832	RTW89_ACPI_SAR_5GHZ_SUBBAND_2E,  /* U-NII-2-Extended */
4833	RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */
4834	RTW89_ACPI_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
4835	RTW89_ACPI_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
4836	RTW89_ACPI_SAR_6GHZ_SUBBAND_6,   /* U-NII-6 */
4837	RTW89_ACPI_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
4838	RTW89_ACPI_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
4839	RTW89_ACPI_SAR_6GHZ_SUBBAND_8,   /* U-NII-8 */
4840
4841	NUM_OF_RTW89_ACPI_SAR_SUBBAND,
4842	RTW89_ACPI_SAR_SUBBAND_NR_LEGACY = RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4 + 1,
4843	RTW89_ACPI_SAR_SUBBAND_NR_HAS_6GHZ = RTW89_ACPI_SAR_6GHZ_SUBBAND_8 + 1,
4844};
4845
4846#define TXPWR_FACTOR_OF_RTW89_ACPI_SAR 3 /* unit: 0.125 dBm */
4847#define MAX_VAL_OF_RTW89_ACPI_SAR S16_MAX
4848#define MIN_VAL_OF_RTW89_ACPI_SAR S16_MIN
4849#define MAX_NUM_OF_RTW89_ACPI_SAR_TBL 6
4850#define NUM_OF_RTW89_ACPI_SAR_RF_PATH (RF_PATH_B + 1)
4851
4852struct rtw89_sar_entry_from_acpi {
4853	s16 v[NUM_OF_RTW89_ACPI_SAR_SUBBAND][NUM_OF_RTW89_ACPI_SAR_RF_PATH];
4854};
4855
4856struct rtw89_sar_table_from_acpi {
4857	/* If this table is active, must fill all fields according to either
4858	 * configuration in BIOS or some default values for SAR to work well.
4859	 */
4860	struct rtw89_sar_entry_from_acpi entries[RTW89_REGD_NUM];
4861};
4862
4863struct rtw89_sar_indicator_from_acpi {
4864	bool enable_sync;
4865	unsigned int fields;
4866	u8 (*rfpath_to_antidx)(enum rtw89_rf_path rfpath);
4867
4868	/* Select among @tables of container, rtw89_sar_cfg_acpi, by path.
4869	 * Not design with pointers since addresses will be invalid after
4870	 * sync content with local container instance.
4871	 */
4872	u8 tblsel[NUM_OF_RTW89_ACPI_SAR_RF_PATH];
4873};
4874
4875struct rtw89_sar_cfg_acpi {
4876	u8 downgrade_2tx;
4877	unsigned int valid_num;
4878	struct rtw89_sar_table_from_acpi tables[MAX_NUM_OF_RTW89_ACPI_SAR_TBL];
4879	struct rtw89_sar_indicator_from_acpi indicator;
4880};
4881
4882struct rtw89_sar_info {
4883	/* used to decide how to access SAR cfg union */
4884	enum rtw89_sar_sources src;
4885
4886	/* reserved for different knids of SAR cfg struct.
4887	 * supposed that a single cfg struct cannot handle various SAR sources.
4888	 */
4889	union {
4890		struct rtw89_sar_cfg_common cfg_common;
4891		struct rtw89_sar_cfg_acpi cfg_acpi;
4892	};
4893};
4894
4895enum rtw89_ant_gain_subband {
4896	RTW89_ANT_GAIN_2GHZ_SUBBAND,
4897	RTW89_ANT_GAIN_5GHZ_SUBBAND_1,   /* U-NII-1 */
4898	RTW89_ANT_GAIN_5GHZ_SUBBAND_2,   /* U-NII-2 */
4899	RTW89_ANT_GAIN_5GHZ_SUBBAND_2E,  /* U-NII-2-Extended */
4900	RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */
4901	RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
4902	RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
4903	RTW89_ANT_GAIN_6GHZ_SUBBAND_6,   /* U-NII-6 */
4904	RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
4905	RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
4906	RTW89_ANT_GAIN_6GHZ_SUBBAND_8,   /* U-NII-8 */
4907
4908	RTW89_ANT_GAIN_SUBBAND_NR,
4909};
4910
4911enum rtw89_ant_gain_domain_type {
4912	RTW89_ANT_GAIN_ETSI = 0,
4913
4914	RTW89_ANT_GAIN_DOMAIN_NUM,
4915};
4916
4917#define RTW89_ANT_GAIN_CHAIN_NUM 2
4918struct rtw89_ant_gain_info {
4919	s8 offset[RTW89_ANT_GAIN_CHAIN_NUM][RTW89_ANT_GAIN_SUBBAND_NR];
4920	u32 regd_enabled;
4921	bool block_country;
4922};
4923
4924struct rtw89_6ghz_span {
4925	enum rtw89_sar_subband sar_subband_low;
4926	enum rtw89_sar_subband sar_subband_high;
4927	enum rtw89_acpi_sar_subband acpi_sar_subband_low;
4928	enum rtw89_acpi_sar_subband acpi_sar_subband_high;
4929	enum rtw89_ant_gain_subband ant_gain_subband_low;
4930	enum rtw89_ant_gain_subband ant_gain_subband_high;
4931};
4932
4933#define RTW89_SAR_SPAN_VALID(span) ((span)->sar_subband_high)
4934#define RTW89_ACPI_SAR_SPAN_VALID(span) ((span)->acpi_sar_subband_high)
4935#define RTW89_ANT_GAIN_SPAN_VALID(span) ((span)->ant_gain_subband_high)
4936
4937enum rtw89_tas_state {
4938	RTW89_TAS_STATE_DPR_OFF,
4939	RTW89_TAS_STATE_DPR_ON,
4940	RTW89_TAS_STATE_STATIC_SAR,
4941};
4942
4943#define RTW89_TAS_TX_RATIO_WINDOW 6
4944#define RTW89_TAS_TXPWR_WINDOW 180
4945struct rtw89_tas_info {
4946	u16 tx_ratio_history[RTW89_TAS_TX_RATIO_WINDOW];
4947	u64 txpwr_history[RTW89_TAS_TXPWR_WINDOW];
4948	u8 enabled_countries;
4949	u8 txpwr_head_idx;
4950	u8 txpwr_tail_idx;
4951	u8 tx_ratio_idx;
4952	u16 total_tx_ratio;
4953	u64 total_txpwr;
4954	u64 instant_txpwr;
4955	u32 window_size;
4956	s8 dpr_on_threshold;
4957	s8 dpr_off_threshold;
4958	enum rtw89_tas_state backup_state;
4959	enum rtw89_tas_state state;
4960	bool keep_history;
4961	bool block_regd;
4962	bool enable;
4963	bool pause;
4964};
4965
4966struct rtw89_chanctx_cfg {
4967	enum rtw89_chanctx_idx idx;
4968	int ref_count;
4969};
4970
4971enum rtw89_chanctx_changes {
4972	RTW89_CHANCTX_REMOTE_STA_CHANGE,
4973	RTW89_CHANCTX_BCN_OFFSET_CHANGE,
4974	RTW89_CHANCTX_P2P_PS_CHANGE,
4975	RTW89_CHANCTX_BT_SLOT_CHANGE,
4976	RTW89_CHANCTX_TSF32_TOGGLE_CHANGE,
4977
4978	NUM_OF_RTW89_CHANCTX_CHANGES,
4979	RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES,
4980};
4981
4982enum rtw89_entity_mode {
4983	RTW89_ENTITY_MODE_SCC_OR_SMLD,
4984	RTW89_ENTITY_MODE_MCC_PREPARE,
4985	RTW89_ENTITY_MODE_MCC,
4986
4987	NUM_OF_RTW89_ENTITY_MODE,
4988	RTW89_ENTITY_MODE_INVALID = -EINVAL,
4989	RTW89_ENTITY_MODE_UNHANDLED = -ESRCH,
4990};
4991
4992#define RTW89_MAX_INTERFACE_NUM 2
4993
4994/* only valid when running with chanctx_ops */
4995struct rtw89_entity_mgnt {
4996	struct list_head active_list;
4997	struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM];
4998	enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM]
4999					  [__RTW89_MLD_MAX_LINK_NUM];
5000};
5001
5002struct rtw89_chanctx {
5003	struct cfg80211_chan_def chandef;
5004	struct rtw89_chan chan;
5005	struct rtw89_chan_rcd rcd;
5006
5007	/* only assigned when running with chanctx_ops */
5008	struct rtw89_chanctx_cfg *cfg;
5009};
5010
5011struct rtw89_edcca_bak {
5012	u8 a;
5013	u8 p;
5014	u8 ppdu;
5015	u8 th_old;
5016};
5017
5018enum rtw89_dm_type {
5019	RTW89_DM_DYNAMIC_EDCCA,
5020	RTW89_DM_THERMAL_PROTECT,
5021	RTW89_DM_TAS,
5022	RTW89_DM_MLO,
5023};
5024
5025#define RTW89_THERMAL_PROT_LV_MAX 5
5026#define RTW89_THERMAL_PROT_STEP 5 /* -5% for each level */
5027
5028struct rtw89_hal {
5029	u32 rx_fltr;
5030	u8 cv;
5031	u8 acv;
5032	u32 antenna_tx;
5033	u32 antenna_rx;
5034	u8 tx_nss;
5035	u8 rx_nss;
5036	bool tx_path_diversity;
5037	bool ant_diversity;
5038	bool ant_diversity_fixed;
5039	bool support_cckpd;
5040	bool support_igi;
5041	bool no_mcs_12_13;
5042	bool no_eht;
5043
5044	atomic_t roc_chanctx_idx;
5045	u8 roc_link_index;
5046
5047	DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES);
5048	DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX);
5049	struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX];
5050	struct cfg80211_chan_def roc_chandef;
5051
5052	bool entity_active[RTW89_PHY_NUM];
5053	bool entity_pause;
5054	enum rtw89_entity_mode entity_mode;
5055	struct rtw89_entity_mgnt entity_mgnt;
5056
5057	u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */
5058
5059	u8 thermal_prot_th;
5060	u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */
5061};
5062
5063#define RTW89_MAX_MAC_ID_NUM 128
5064#define RTW89_MAX_PKT_OFLD_NUM 255
5065
5066enum rtw89_flags {
5067	RTW89_FLAG_POWERON,
5068	RTW89_FLAG_DMAC_FUNC,
5069	RTW89_FLAG_CMAC0_FUNC,
5070	RTW89_FLAG_CMAC1_FUNC,
5071	RTW89_FLAG_FW_RDY,
5072	RTW89_FLAG_RUNNING,
5073	RTW89_FLAG_PROBE_DONE,
5074	RTW89_FLAG_BFEE_MON,
5075	RTW89_FLAG_BFEE_EN,
5076	RTW89_FLAG_BFEE_TIMER_KEEP,
5077	RTW89_FLAG_NAPI_RUNNING,
5078	RTW89_FLAG_LEISURE_PS,
5079	RTW89_FLAG_LOW_POWER_MODE,
5080	RTW89_FLAG_INACTIVE_PS,
5081	RTW89_FLAG_CRASH_SIMULATING,
5082	RTW89_FLAG_SER_HANDLING,
5083	RTW89_FLAG_WOWLAN,
5084	RTW89_FLAG_FORBIDDEN_TRACK_WORK,
5085	RTW89_FLAG_CHANGING_INTERFACE,
5086	RTW89_FLAG_HW_RFKILL_STATE,
5087	RTW89_FLAG_UNPLUGGED,
5088
5089	NUM_OF_RTW89_FLAGS,
5090};
5091
5092enum rtw89_quirks {
5093	RTW89_QUIRK_PCI_BER,
5094	RTW89_QUIRK_THERMAL_PROT_120C,
5095	RTW89_QUIRK_THERMAL_PROT_110C,
5096
5097	NUM_OF_RTW89_QUIRKS,
5098};
5099
5100enum rtw89_custid {
5101	RTW89_CUSTID_NONE,
5102	RTW89_CUSTID_ACER,
5103	RTW89_CUSTID_AMD,
5104	RTW89_CUSTID_ASUS,
5105	RTW89_CUSTID_DELL,
5106	RTW89_CUSTID_HP,
5107	RTW89_CUSTID_LENOVO,
5108};
5109
5110enum rtw89_pkt_drop_sel {
5111	RTW89_PKT_DROP_SEL_MACID_BE_ONCE,
5112	RTW89_PKT_DROP_SEL_MACID_BK_ONCE,
5113	RTW89_PKT_DROP_SEL_MACID_VI_ONCE,
5114	RTW89_PKT_DROP_SEL_MACID_VO_ONCE,
5115	RTW89_PKT_DROP_SEL_MACID_ALL,
5116	RTW89_PKT_DROP_SEL_MG0_ONCE,
5117	RTW89_PKT_DROP_SEL_HIQ_ONCE,
5118	RTW89_PKT_DROP_SEL_HIQ_PORT,
5119	RTW89_PKT_DROP_SEL_HIQ_MBSSID,
5120	RTW89_PKT_DROP_SEL_BAND,
5121	RTW89_PKT_DROP_SEL_BAND_ONCE,
5122	RTW89_PKT_DROP_SEL_REL_MACID,
5123	RTW89_PKT_DROP_SEL_REL_HIQ_PORT,
5124	RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID,
5125};
5126
5127struct rtw89_pkt_drop_params {
5128	enum rtw89_pkt_drop_sel sel;
5129	enum rtw89_mac_idx mac_band;
5130	u8 macid;
5131	u8 port;
5132	u8 mbssid;
5133	bool tf_trs;
5134	u32 macid_band_sel[4];
5135};
5136
5137struct rtw89_pkt_stat {
5138	u16 beacon_nr;
5139	u8 beacon_rate;
5140	u32 beacon_len;
5141	u32 rx_rate_cnt[RTW89_HW_RATE_NR];
5142};
5143
5144#define RTW89_BCN_TRACK_STAT_NR 32
5145#define RTW89_BCN_TRACK_SCALE_FACTOR 10
5146#define RTW89_BCN_TRACK_MAX_BIN_NUM 6
5147#define RTW89_BCN_TRACK_BIN_WIDTH 5
5148#define RTW89_BCN_TRACK_TARGET_BCN 80
5149
5150struct rtw89_beacon_dist {
5151	u16 min;
5152	u16 max;
5153	u16 outlier_count;
5154	u16 lower_bound;
5155	u16 upper_bound;
5156	u16 bins[RTW89_BCN_TRACK_MAX_BIN_NUM];
5157};
5158
5159struct rtw89_beacon_stat {
5160	u8 num;
5161	u8 wp;
5162	u16 tbtt_tu_min;
5163	u16 tbtt_tu_max;
5164	u16 drift[RTW89_BCN_TRACK_STAT_NR];
5165	u32 tbtt_us[RTW89_BCN_TRACK_STAT_NR];
5166	u16 tbtt_tu[RTW89_BCN_TRACK_STAT_NR];
5167	struct rtw89_beacon_dist bcn_dist;
5168};
5169
5170DECLARE_EWMA(thermal, 4, 4);
5171
5172struct rtw89_phy_stat {
5173	struct ewma_thermal avg_thermal[RF_PATH_MAX];
5174	u8 last_thermal_max;
5175	struct ewma_rssi bcn_rssi;
5176	struct rtw89_pkt_stat cur_pkt_stat;
5177	struct rtw89_pkt_stat last_pkt_stat;
5178	struct rtw89_beacon_stat bcn_stat;
5179};
5180
5181enum rtw89_rfk_report_state {
5182	RTW89_RFK_STATE_START = 0x0,
5183	RTW89_RFK_STATE_OK = 0x1,
5184	RTW89_RFK_STATE_FAIL = 0x2,
5185	RTW89_RFK_STATE_TIMEOUT = 0x3,
5186	RTW89_RFK_STATE_H2C_CMD_ERR = 0x4,
5187};
5188
5189struct rtw89_rfk_wait_info {
5190	struct completion completion;
5191	ktime_t start_time;
5192	enum rtw89_rfk_report_state state;
5193	u8 version;
5194};
5195
5196#define RTW89_DACK_PATH_NR 2
5197#define RTW89_DACK_IDX_NR 2
5198#define RTW89_DACK_MSBK_NR 16
5199struct rtw89_dack_info {
5200	bool dack_done;
5201	u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR];
5202	u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
5203	u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
5204	u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
5205	u32 dack_cnt;
5206	bool addck_timeout[RTW89_DACK_PATH_NR];
5207	bool dadck_timeout[RTW89_DACK_PATH_NR];
5208	bool msbk_timeout[RTW89_DACK_PATH_NR];
5209};
5210
5211enum rtw89_rfk_chs_nrs {
5212	__RTW89_RFK_CHS_NR_V0 = 2,
5213	__RTW89_RFK_CHS_NR_V1 = 3,
5214
5215	RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1,
5216};
5217
5218struct rtw89_rfk_mcc_info_data {
5219	u8 ch[RTW89_RFK_CHS_NR];
5220	u8 band[RTW89_RFK_CHS_NR];
5221	u8 bw[RTW89_RFK_CHS_NR];
5222	u8 table_idx;
5223};
5224
5225struct rtw89_rfk_mcc_info {
5226	struct rtw89_rfk_mcc_info_data data[2];
5227};
5228
5229#define RTW89_IQK_CHS_NR 2
5230#define RTW89_IQK_PATH_NR 4
5231
5232struct rtw89_lck_info {
5233	u8 thermal[RF_PATH_MAX];
5234};
5235
5236struct rtw89_rx_dck_info {
5237	u8 thermal[RF_PATH_MAX];
5238};
5239
5240struct rtw89_iqk_info {
5241	bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5242	bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5243	bool lok_fail[RTW89_IQK_PATH_NR];
5244	bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5245	bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5246	u32 iqk_fail_cnt;
5247	bool is_iqk_init;
5248	u32 iqk_channel[RTW89_IQK_CHS_NR];
5249	u8 iqk_band[RTW89_IQK_PATH_NR];
5250	u8 iqk_ch[RTW89_IQK_PATH_NR];
5251	u8 iqk_bw[RTW89_IQK_PATH_NR];
5252	u8 iqk_times;
5253	u8 version;
5254	u32 nb_txcfir[RTW89_IQK_PATH_NR];
5255	u32 nb_rxcfir[RTW89_IQK_PATH_NR];
5256	u32 bp_txkresult[RTW89_IQK_PATH_NR];
5257	u32 bp_rxkresult[RTW89_IQK_PATH_NR];
5258	u32 bp_iqkenable[RTW89_IQK_PATH_NR];
5259	bool is_wb_txiqk[RTW89_IQK_PATH_NR];
5260	bool is_wb_rxiqk[RTW89_IQK_PATH_NR];
5261	bool is_nbiqk;
5262	bool iqk_fft_en;
5263	bool iqk_xym_en;
5264	bool iqk_sram_en;
5265	bool iqk_cfir_en;
5266	u32 syn1to2;
5267	u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5268	u8 iqk_table_idx[RTW89_IQK_PATH_NR];
5269	u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5270	u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5271};
5272
5273#define RTW89_DPK_RF_PATH 2
5274#define RTW89_DPK_AVG_THERMAL_NUM 8
5275#define RTW89_DPK_BKUP_NUM 2
5276struct rtw89_dpk_bkup_para {
5277	enum rtw89_band band;
5278	enum rtw89_bandwidth bw;
5279	u8 ch;
5280	u8 path_ok;
5281	u8 mdpd_en;
5282	u8 txagc_dpk;
5283	u8 ther_dpk;
5284	u8 gs;
5285	u16 pwsf;
5286};
5287
5288struct rtw89_dpk_info {
5289	bool is_dpk_enable;
5290	bool is_dpk_reload_en;
5291	u8 dpk_gs[RTW89_PHY_NUM];
5292	u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
5293	u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
5294	u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
5295	u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
5296	u8 cur_idx[RTW89_DPK_RF_PATH];
5297	u8 cur_k_set;
5298	struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
5299	u8 max_dpk_txagc[RTW89_DPK_RF_PATH];
5300	u32 dpk_order[RTW89_DPK_RF_PATH];
5301};
5302
5303struct rtw89_fem_info {
5304	bool elna_2g;
5305	bool elna_5g;
5306	bool epa_2g;
5307	bool epa_5g;
5308	bool epa_6g;
5309};
5310
5311struct rtw89_phy_ch_info {
5312	u8 rssi_min;
5313	u16 rssi_min_macid;
5314	u8 pre_rssi_min;
5315	u8 rssi_max;
5316	u16 rssi_max_macid;
5317	u8 rxsc_160;
5318	u8 rxsc_80;
5319	u8 rxsc_40;
5320	u8 rxsc_20;
5321	u8 rxsc_l;
5322	u8 is_noisy;
5323};
5324
5325struct rtw89_agc_gaincode_set {
5326	u8 lna_idx;
5327	u8 tia_idx;
5328	u8 rxb_idx;
5329};
5330
5331#define IGI_RSSI_TH_NUM 5
5332#define FA_TH_NUM 4
5333#define TIA_LNA_OP1DB_NUM 8
5334#define LNA_GAIN_NUM 7
5335#define TIA_GAIN_NUM 2
5336struct rtw89_dig_info {
5337	struct rtw89_agc_gaincode_set cur_gaincode;
5338	bool force_gaincode_idx_en;
5339	struct rtw89_agc_gaincode_set force_gaincode;
5340	u8 igi_rssi_th[IGI_RSSI_TH_NUM];
5341	u16 fa_th[FA_TH_NUM];
5342	u8 igi_rssi;
5343	u8 igi_fa_rssi;
5344	u8 fa_rssi_ofst;
5345	u8 dyn_igi_max;
5346	u8 dyn_igi_min;
5347	bool dyn_pd_th_en;
5348	u8 dyn_pd_th_max;
5349	u8 pd_low_th_ofst;
5350	u8 ib_pbk;
5351	s8 ib_pkpwr;
5352	s8 lna_gain_a[LNA_GAIN_NUM];
5353	s8 lna_gain_g[LNA_GAIN_NUM];
5354	s8 *lna_gain;
5355	s8 tia_gain_a[TIA_GAIN_NUM];
5356	s8 tia_gain_g[TIA_GAIN_NUM];
5357	s8 *tia_gain;
5358	u32 bak_dig;
5359	bool is_linked_pre;
5360	bool bypass_dig;
5361	bool pause_dig;
5362};
5363
5364enum rtw89_multi_cfo_mode {
5365	RTW89_PKT_BASED_AVG_MODE = 0,
5366	RTW89_ENTRY_BASED_AVG_MODE = 1,
5367	RTW89_TP_BASED_AVG_MODE = 2,
5368};
5369
5370enum rtw89_phy_cfo_status {
5371	RTW89_PHY_DCFO_STATE_NORMAL = 0,
5372	RTW89_PHY_DCFO_STATE_ENHANCE = 1,
5373	RTW89_PHY_DCFO_STATE_HOLD = 2,
5374	RTW89_PHY_DCFO_STATE_MAX
5375};
5376
5377enum rtw89_phy_cfo_ul_ofdma_acc_mode {
5378	RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0,
5379	RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1
5380};
5381
5382struct rtw89_cfo_tracking_info {
5383	u16 cfo_timer_ms;
5384	bool cfo_trig_by_timer_en;
5385	enum rtw89_phy_cfo_status phy_cfo_status;
5386	enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode;
5387	u8 phy_cfo_trk_cnt;
5388	bool is_adjust;
5389	enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode;
5390	bool apply_compensation;
5391	u8 crystal_cap;
5392	u8 crystal_cap_default;
5393	u8 def_x_cap;
5394	s8 x_cap_ofst;
5395	u32 sta_cfo_tolerance;
5396	s32 cfo_tail[CFO_TRACK_MAX_USER];
5397	u16 cfo_cnt[CFO_TRACK_MAX_USER];
5398	s32 cfo_avg_pre;
5399	s32 cfo_avg[CFO_TRACK_MAX_USER];
5400	s32 pre_cfo_avg[CFO_TRACK_MAX_USER];
5401	s32 dcfo_avg;
5402	s32 dcfo_avg_pre;
5403	u32 packet_count;
5404	u32 packet_count_pre;
5405	s32 residual_cfo_acc;
5406	u8 phy_cfotrk_state;
5407	u8 phy_cfotrk_cnt;
5408	bool divergence_lock_en;
5409	u8 x_cap_lb;
5410	u8 x_cap_ub;
5411	u8 lock_cnt;
5412};
5413
5414enum rtw89_tssi_mode {
5415	RTW89_TSSI_NORMAL = 0,
5416	RTW89_TSSI_SCAN = 1,
5417};
5418
5419enum rtw89_tssi_alimk_band {
5420	TSSI_ALIMK_2G = 0,
5421	TSSI_ALIMK_5GL,
5422	TSSI_ALIMK_5GM,
5423	TSSI_ALIMK_5GH,
5424	TSSI_ALIMK_MAX
5425};
5426
5427/* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
5428#define TSSI_TRIM_CH_GROUP_NUM 8
5429#define TSSI_TRIM_CH_GROUP_NUM_6G 16
5430
5431#define TSSI_CCK_CH_GROUP_NUM 6
5432#define TSSI_MCS_2G_CH_GROUP_NUM 5
5433#define TSSI_MCS_5G_CH_GROUP_NUM 14
5434#define TSSI_MCS_6G_CH_GROUP_NUM 32
5435#define TSSI_MCS_CH_GROUP_NUM \
5436	(TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
5437#define TSSI_MAX_CH_NUM 67
5438#define TSSI_ALIMK_VALUE_NUM 8
5439
5440struct rtw89_tssi_info {
5441	u8 thermal[RF_PATH_MAX];
5442	s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];
5443	s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G];
5444	s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];
5445	s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];
5446	s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM];
5447	s8 extra_ofst[RF_PATH_MAX];
5448	bool tssi_tracking_check[RF_PATH_MAX];
5449	u8 default_txagc_offset[RF_PATH_MAX];
5450	u32 base_thermal[RF_PATH_MAX];
5451	bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM];
5452	u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM];
5453	u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM];
5454	bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX];
5455	u64 tssi_alimk_time;
5456};
5457
5458struct rtw89_power_trim_info {
5459	bool pg_thermal_trim;
5460	bool pg_pa_bias_trim;
5461	u8 thermal_trim[RF_PATH_MAX];
5462	u8 pa_bias_trim[RF_PATH_MAX];
5463	u8 pad_bias_trim[RF_PATH_MAX];
5464};
5465
5466enum rtw89_regd_func {
5467	RTW89_REGD_FUNC_TAS = 0, /* TAS (Time Average SAR) */
5468	RTW89_REGD_FUNC_DAG = 1, /* DAG (Dynamic Antenna Gain) */
5469
5470	NUM_OF_RTW89_REGD_FUNC,
5471};
5472
5473struct rtw89_regd {
5474	char alpha2[3];
5475	u8 txpwr_regd[RTW89_BAND_NUM];
5476	DECLARE_BITMAP(func_bitmap, NUM_OF_RTW89_REGD_FUNC);
5477};
5478
5479struct rtw89_regd_data {
5480	unsigned int nr;
5481	struct rtw89_regd map[] __counted_by(nr);
5482};
5483
5484struct rtw89_regd_ctrl {
5485	unsigned int nr;
5486	const struct rtw89_regd *map;
5487};
5488
5489#define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX
5490#define RTW89_5GHZ_UNII4_CHANNEL_NUM 3
5491#define RTW89_5GHZ_UNII4_START_INDEX 25
5492
5493struct rtw89_regulatory_info {
5494	struct rtw89_regd_ctrl ctrl;
5495	const struct rtw89_regd *regd;
5496	bool programmed;
5497
5498	enum rtw89_reg_6ghz_power reg_6ghz_power;
5499	struct rtw89_reg_6ghz_tpe reg_6ghz_tpe;
5500	bool txpwr_uk_follow_etsi;
5501
5502	DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM);
5503	DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM);
5504	DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM);
5505	DECLARE_BITMAP(block_6ghz_vlp, RTW89_REGD_MAX_COUNTRY_NUM);
5506};
5507
5508enum rtw89_ifs_clm_application {
5509	RTW89_IFS_CLM_INIT = 0,
5510	RTW89_IFS_CLM_BACKGROUND = 1,
5511	RTW89_IFS_CLM_ACS = 2,
5512	RTW89_IFS_CLM_DIG = 3,
5513	RTW89_IFS_CLM_TDMA_DIG = 4,
5514	RTW89_IFS_CLM_DBG = 5,
5515	RTW89_IFS_CLM_DBG_MANUAL = 6
5516};
5517
5518enum rtw89_env_racing_lv {
5519	RTW89_RAC_RELEASE = 0,
5520	RTW89_RAC_LV_1 = 1,
5521	RTW89_RAC_LV_2 = 2,
5522	RTW89_RAC_LV_3 = 3,
5523	RTW89_RAC_LV_4 = 4,
5524	RTW89_RAC_MAX_NUM = 5
5525};
5526
5527struct rtw89_ccx_para_info {
5528	enum rtw89_env_racing_lv rac_lv;
5529	u16 mntr_time;
5530	bool nhm_incld_cca;
5531	u8 nhm_manual_th_ofst;
5532	u8 nhm_manual_th0;
5533	enum rtw89_ifs_clm_application ifs_clm_app;
5534	u32 ifs_clm_manual_th_times;
5535	u32 ifs_clm_manual_th0;
5536	u8 fahm_manual_th_ofst;
5537	u8 fahm_manual_th0;
5538	u8 fahm_numer_opt;
5539	u8 fahm_denom_opt;
5540};
5541
5542enum rtw89_ccx_edcca_opt_sc_idx {
5543	RTW89_CCX_EDCCA_SEG0_P0 = 0,
5544	RTW89_CCX_EDCCA_SEG0_S1 = 1,
5545	RTW89_CCX_EDCCA_SEG0_S2 = 2,
5546	RTW89_CCX_EDCCA_SEG0_S3 = 3,
5547	RTW89_CCX_EDCCA_SEG1_P0 = 4,
5548	RTW89_CCX_EDCCA_SEG1_S1 = 5,
5549	RTW89_CCX_EDCCA_SEG1_S2 = 6,
5550	RTW89_CCX_EDCCA_SEG1_S3 = 7
5551};
5552
5553enum rtw89_ccx_edcca_opt_bw_idx {
5554	RTW89_CCX_EDCCA_BW20_0 = 0,
5555	RTW89_CCX_EDCCA_BW20_1 = 1,
5556	RTW89_CCX_EDCCA_BW20_2 = 2,
5557	RTW89_CCX_EDCCA_BW20_3 = 3,
5558	RTW89_CCX_EDCCA_BW20_4 = 4,
5559	RTW89_CCX_EDCCA_BW20_5 = 5,
5560	RTW89_CCX_EDCCA_BW20_6 = 6,
5561	RTW89_CCX_EDCCA_BW20_7 = 7
5562};
5563
5564struct rtw89_nhm_report {
5565	struct list_head list;
5566	struct ieee80211_channel *channel;
5567	u8 noise;
5568};
5569
5570#define RTW89_FAHM_TH_NUM 11
5571#define RTW89_FAHM_RPT_NUM 12
5572#define RTW89_IFS_CLM_NUM 4
5573struct rtw89_env_monitor_info {
5574	u8 ccx_watchdog_result;
5575	bool ccx_ongoing;
5576	u8 ccx_rac_lv;
5577	bool ccx_manual_ctrl;
5578	u16 ifs_clm_mntr_time;
5579	enum rtw89_ifs_clm_application ifs_clm_app;
5580	u16 ccx_period;
5581	u8 ccx_unit_idx;
5582	u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];
5583	u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];
5584	u16 ifs_clm_tx;
5585	u16 ifs_clm_edcca_excl_cca;
5586	u16 ifs_clm_ofdmfa;
5587	u16 ifs_clm_ofdmcca_excl_fa;
5588	u16 ifs_clm_cckfa;
5589	u16 ifs_clm_cckcca_excl_fa;
5590	u16 ifs_clm_total_ifs;
5591	u8 ifs_clm_his[RTW89_IFS_CLM_NUM];
5592	u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];
5593	u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];
5594	u8 ifs_clm_tx_ratio;
5595	u8 ifs_clm_edcca_excl_cca_ratio;
5596	u8 ifs_clm_cck_fa_ratio;
5597	u8 ifs_clm_ofdm_fa_ratio;
5598	u8 ifs_clm_cck_cca_excl_fa_ratio;
5599	u8 ifs_clm_ofdm_cca_excl_fa_ratio;
5600	u16 ifs_clm_cck_fa_permil;
5601	u16 ifs_clm_ofdm_fa_permil;
5602	u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];
5603	u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];
5604	bool nhm_include_cca;
5605	u32 nhm_sum;
5606	u32 nhm_mntr_time;
5607	u16 nhm_result[RTW89_NHM_RPT_NUM];
5608	u8 nhm_th[RTW89_NHM_RPT_NUM];
5609	struct rtw89_nhm_report *nhm_his[RTW89_BAND_NUM];
5610	struct list_head nhm_rpt_list;
5611};
5612
5613enum rtw89_ser_rcvy_step {
5614	RTW89_SER_DRV_STOP_TX,
5615	RTW89_SER_DRV_STOP_RX,
5616	RTW89_SER_DRV_STOP_RUN,
5617	RTW89_SER_HAL_STOP_DMA,
5618	RTW89_SER_SUPPRESS_LOG,
5619	RTW89_NUM_OF_SER_FLAGS
5620};
5621
5622struct rtw89_ser {
5623	u8 state;
5624	u8 alarm_event;
5625	bool prehandle_l1;
5626
5627	struct work_struct ser_hdl_work;
5628	struct delayed_work ser_alarm_work;
5629	const struct state_ent *st_tbl;
5630	const struct event_ent *ev_tbl;
5631	struct list_head msg_q;
5632	spinlock_t msg_q_lock; /* lock when read/write ser msg */
5633	DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS);
5634};
5635
5636enum rtw89_mac_ax_ps_mode {
5637	RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
5638	RTW89_MAC_AX_PS_MODE_LEGACY = 1,
5639	RTW89_MAC_AX_PS_MODE_WMMPS  = 2,
5640	RTW89_MAC_AX_PS_MODE_MAX    = 3,
5641};
5642
5643enum rtw89_last_rpwm_mode {
5644	RTW89_LAST_RPWM_PS        = 0x0,
5645	RTW89_LAST_RPWM_ACTIVE    = 0x6,
5646};
5647
5648struct rtw89_lps_parm {
5649	u8 macid;
5650	u8 psmode; /* enum rtw89_mac_ax_ps_mode */
5651	u8 lastrpwm; /* enum rtw89_last_rpwm_mode */
5652};
5653
5654struct rtw89_ppdu_sts_info {
5655	struct sk_buff_head rx_queue[RTW89_PHY_NUM];
5656	u8 curr_rx_ppdu_cnt[RTW89_PHY_NUM];
5657};
5658
5659struct rtw89_early_h2c {
5660	struct list_head list;
5661	u8 *h2c;
5662	u16 h2c_len;
5663};
5664
5665struct rtw89_hw_scan_extra_op {
5666	bool set;
5667	u8 macid;
5668	u8 port;
5669	struct rtw89_chan chan;
5670	struct rtw89_vif_link *rtwvif_link;
5671};
5672
5673struct rtw89_hw_scan_info {
5674	struct rtw89_vif_link *scanning_vif;
5675	struct list_head pkt_list[NUM_NL80211_BANDS];
5676	struct list_head chan_list;
5677	struct rtw89_chan op_chan;
5678	struct rtw89_hw_scan_extra_op extra_op;
5679	bool connected;
5680	bool abort;
5681	u16 delay; /* in unit of ms */
5682	u8 seq: 2;
5683};
5684
5685enum rtw89_phy_bb_gain_band {
5686	RTW89_BB_GAIN_BAND_2G = 0,
5687	RTW89_BB_GAIN_BAND_5G_L = 1,
5688	RTW89_BB_GAIN_BAND_5G_M = 2,
5689	RTW89_BB_GAIN_BAND_5G_H = 3,
5690	RTW89_BB_GAIN_BAND_6G_L = 4,
5691	RTW89_BB_GAIN_BAND_6G_M = 5,
5692	RTW89_BB_GAIN_BAND_6G_H = 6,
5693	RTW89_BB_GAIN_BAND_6G_UH = 7,
5694
5695	RTW89_BB_GAIN_BAND_NR,
5696};
5697
5698enum rtw89_phy_gain_band_be {
5699	RTW89_BB_GAIN_BAND_2G_BE = 0,
5700	RTW89_BB_GAIN_BAND_5G_L_BE = 1,
5701	RTW89_BB_GAIN_BAND_5G_M_BE = 2,
5702	RTW89_BB_GAIN_BAND_5G_H_BE = 3,
5703	RTW89_BB_GAIN_BAND_6G_L0_BE = 4,
5704	RTW89_BB_GAIN_BAND_6G_L1_BE = 5,
5705	RTW89_BB_GAIN_BAND_6G_M0_BE = 6,
5706	RTW89_BB_GAIN_BAND_6G_M1_BE = 7,
5707	RTW89_BB_GAIN_BAND_6G_H0_BE = 8,
5708	RTW89_BB_GAIN_BAND_6G_H1_BE = 9,
5709	RTW89_BB_GAIN_BAND_6G_UH0_BE = 10,
5710	RTW89_BB_GAIN_BAND_6G_UH1_BE = 11,
5711
5712	RTW89_BB_GAIN_BAND_NR_BE,
5713};
5714
5715enum rtw89_phy_bb_bw_be {
5716	RTW89_BB_BW_20_40 = 0,
5717	RTW89_BB_BW_80_160_320 = 1,
5718
5719	RTW89_BB_BW_NR_BE,
5720};
5721
5722enum rtw89_bw20_sc {
5723	RTW89_BW20_SC_20M = 1,
5724	RTW89_BW20_SC_40M = 2,
5725	RTW89_BW20_SC_80M = 4,
5726	RTW89_BW20_SC_160M = 8,
5727	RTW89_BW20_SC_320M = 16,
5728};
5729
5730enum rtw89_cmac_table_bw {
5731	RTW89_CMAC_BW_20M = 0,
5732	RTW89_CMAC_BW_40M = 1,
5733	RTW89_CMAC_BW_80M = 2,
5734	RTW89_CMAC_BW_160M = 3,
5735	RTW89_CMAC_BW_320M = 4,
5736
5737	RTW89_CMAC_BW_NR,
5738};
5739
5740enum rtw89_phy_bb_rxsc_num {
5741	RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */
5742	RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */
5743	RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */
5744};
5745
5746struct rtw89_phy_bb_gain_info {
5747	s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5748	s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM];
5749	s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5750	s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5751	s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5752			[LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */
5753	s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX];
5754	s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5755		      [RTW89_BB_RXSC_NUM_40];
5756	s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5757		      [RTW89_BB_RXSC_NUM_80];
5758	s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5759		       [RTW89_BB_RXSC_NUM_160];
5760};
5761
5762struct rtw89_phy_bb_gain_info_be {
5763	s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX]
5764		   [LNA_GAIN_NUM];
5765	s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX]
5766		   [TIA_GAIN_NUM];
5767	s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5768			  [RF_PATH_MAX][LNA_GAIN_NUM];
5769	s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5770		    [RF_PATH_MAX][LNA_GAIN_NUM];
5771	s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5772			[RF_PATH_MAX][LNA_GAIN_NUM + 1];
5773	s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5774		      [RTW89_BW20_SC_20M];
5775	s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5776		      [RTW89_BW20_SC_40M];
5777	s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5778		      [RTW89_BW20_SC_80M];
5779	s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5780		       [RTW89_BW20_SC_160M];
5781};
5782
5783struct rtw89_phy_efuse_gain {
5784	bool offset_valid;
5785	bool comp_valid;
5786	s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
5787	s8 offset_base[RTW89_PHY_NUM]; /* S(8, 4) */
5788	s8 rssi_base[RTW89_PHY_NUM]; /* S(8, 4) */
5789	s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
5790};
5791
5792#define RTW89_MAX_PATTERN_NUM             18
5793#define RTW89_MAX_PATTERN_MASK_SIZE       4
5794#define RTW89_MAX_PATTERN_SIZE            128
5795
5796struct rtw89_wow_cam_info {
5797	bool r_w;
5798	u8 idx;
5799	u32 mask[RTW89_MAX_PATTERN_MASK_SIZE];
5800	u16 crc;
5801	bool negative_pattern_match;
5802	bool skip_mac_hdr;
5803	bool uc;
5804	bool mc;
5805	bool bc;
5806	bool valid;
5807};
5808
5809struct rtw89_wow_key_info {
5810	u8 ptk_tx_iv[8];
5811	u8 valid_check;
5812	u8 symbol_check_en;
5813	u8 gtk_keyidx;
5814	u8 rsvd[5];
5815	u8 ptk_rx_iv[8];
5816	u8 gtk_rx_iv[4][8];
5817} __packed;
5818
5819struct rtw89_wow_gtk_info {
5820	u8 kck[32];
5821	u8 kek[32];
5822	u8 tk1[16];
5823	u8 rxmickey[8];
5824	u8 txmickey[8];
5825	__le32 igtk_keyid;
5826	__le64 ipn;
5827	u8 igtk[2][32];
5828	u8 psk[32];
5829} __packed;
5830
5831struct rtw89_wow_aoac_report {
5832	u8 rpt_ver;
5833	u8 sec_type;
5834	u8 key_idx;
5835	u8 pattern_idx;
5836	u8 rekey_ok;
5837	u8 ptk_tx_iv[8];
5838	u8 eapol_key_replay_count[8];
5839	u8 gtk[32];
5840	u8 ptk_rx_iv[8];
5841	u8 gtk_rx_iv[4][8];
5842	u64 igtk_key_id;
5843	u64 igtk_ipn;
5844	u8 igtk[32];
5845	u8 csa_pri_ch;
5846	u8 csa_bw;
5847	u8 csa_ch_offset;
5848	u8 csa_chsw_failed;
5849	u8 csa_ch_band;
5850};
5851
5852struct rtw89_wow_param {
5853	struct rtw89_vif_link *rtwvif_link;
5854	DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM);
5855	struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM];
5856	struct rtw89_wow_key_info key_info;
5857	struct rtw89_wow_gtk_info gtk_info;
5858	struct rtw89_wow_aoac_report aoac_rpt;
5859	u8 pattern_cnt;
5860	u8 ptk_alg;
5861	u8 gtk_alg;
5862	u8 ptk_keyidx;
5863	u8 akm;
5864
5865	/* see RTW89_WOW_WAIT_COND series for wait condition */
5866	struct rtw89_wait_info wait;
5867
5868	bool pno_inited;
5869	struct list_head pno_pkt_list;
5870	struct cfg80211_sched_scan_request *nd_config;
5871};
5872
5873struct rtw89_mcc_limit {
5874	bool enable;
5875	u16 max_tob; /* TU; max time offset behind */
5876	u16 max_toa; /* TU; max time offset ahead */
5877	u16 max_dur; /* TU */
5878};
5879
5880struct rtw89_mcc_policy {
5881	u8 c2h_rpt;
5882	u8 tx_null_early;
5883	u8 dis_tx_null;
5884	u8 in_curr_ch;
5885	u8 dis_sw_retry;
5886	u8 sw_retry_count;
5887};
5888
5889struct rtw89_mcc_role {
5890	struct rtw89_vif_link *rtwvif_link;
5891	struct rtw89_mcc_policy policy;
5892	struct rtw89_mcc_limit limit;
5893
5894	const struct rtw89_mcc_courtesy_cfg *crtz;
5895
5896	/* only valid when running with FW MRC mechanism */
5897	u8 slot_idx;
5898
5899	/* byte-array in LE order for FW */
5900	u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)];
5901	u8 probe_count;
5902
5903	u16 duration; /* TU */
5904	u16 beacon_interval; /* TU */
5905	bool is_2ghz;
5906	bool is_go;
5907	bool is_gc;
5908	bool ignore_bcn;
5909};
5910
5911struct rtw89_mcc_bt_role {
5912	u16 duration; /* TU */
5913};
5914
5915struct rtw89_mcc_courtesy_cfg {
5916	u8 slot_num;
5917	u8 macid_tgt;
5918};
5919
5920struct rtw89_mcc_courtesy {
5921	struct rtw89_mcc_courtesy_cfg ref;
5922	struct rtw89_mcc_courtesy_cfg aux;
5923};
5924
5925enum rtw89_mcc_plan {
5926	RTW89_MCC_PLAN_TAIL_BT,
5927	RTW89_MCC_PLAN_MID_BT,
5928	RTW89_MCC_PLAN_NO_BT,
5929
5930	NUM_OF_RTW89_MCC_PLAN,
5931};
5932
5933struct rtw89_mcc_pattern {
5934	s16 tob_ref; /* TU; time offset behind of reference role */
5935	s16 toa_ref; /* TU; time offset ahead of reference role */
5936	s16 tob_aux; /* TU; time offset behind of auxiliary role */
5937	s16 toa_aux; /* TU; time offset ahead of auxiliary role */
5938
5939	enum rtw89_mcc_plan plan;
5940	struct rtw89_mcc_courtesy courtesy;
5941};
5942
5943struct rtw89_mcc_sync {
5944	bool enable;
5945	u16 offset; /* TU */
5946	u8 macid_src;
5947	u8 band_src;
5948	u8 port_src;
5949	u8 macid_tgt;
5950	u8 band_tgt;
5951	u8 port_tgt;
5952};
5953
5954struct rtw89_mcc_config {
5955	struct rtw89_mcc_pattern pattern;
5956	struct rtw89_mcc_sync sync;
5957	u64 start_tsf;
5958	u64 start_tsf_in_aux_domain;
5959	u64 prepare_delay;
5960	u16 mcc_interval; /* TU */
5961	u16 beacon_offset; /* TU */
5962};
5963
5964enum rtw89_mcc_mode {
5965	RTW89_MCC_MODE_GO_STA,
5966	RTW89_MCC_MODE_GC_STA,
5967};
5968
5969struct rtw89_mcc_info {
5970	struct rtw89_wait_info wait;
5971
5972	u8 group;
5973	enum rtw89_mcc_mode mode;
5974	struct rtw89_mcc_role role_ref; /* reference role */
5975	struct rtw89_mcc_role role_aux; /* auxiliary role */
5976	struct rtw89_mcc_bt_role bt_role;
5977	struct rtw89_mcc_config config;
5978};
5979
5980enum rtw89_mlo_mode {
5981	RTW89_MLO_MODE_MLSR = 0,
5982	RTW89_MLO_MODE_EMLSR = 1,
5983
5984	NUM_OF_RTW89_MLO_MODE,
5985};
5986
5987struct rtw89_mlo_info {
5988	struct rtw89_wait_info wait;
5989};
5990
5991struct rtw89_beacon_track_info {
5992	bool is_data_ready;
5993	u32 tbtt_offset; /* in unit of microsecond */
5994	u16 bcn_timeout; /* in unit of millisecond */
5995
5996	/* The following are constant and set at association. */
5997	u8 dtim;
5998	u16 beacon_int;
5999	u16 low_bcn_th;
6000	u16 med_bcn_th;
6001	u16 high_bcn_th;
6002	u16 target_bcn_th;
6003	u16 outlier_low_bcn_th;
6004	u16 outlier_high_bcn_th;
6005	u32 close_bcn_intvl_th;
6006	u32 tbtt_diff_th;
6007};
6008
6009struct rtw89_dev {
6010	struct ieee80211_hw *hw;
6011	struct device *dev;
6012	const struct ieee80211_ops *ops;
6013
6014	bool dbcc_en;
6015	bool support_mlo;
6016	enum rtw89_mlo_dbcc_mode mlo_dbcc_mode;
6017	struct rtw89_hw_scan_info scan_info;
6018	const struct rtw89_chip_info *chip;
6019	const struct rtw89_chip_variant *variant;
6020	const struct rtw89_pci_info *pci_info;
6021	const struct rtw89_rfe_parms *rfe_parms;
6022	struct rtw89_hal hal;
6023	struct rtw89_beacon_track_info bcn_track;
6024	struct rtw89_mcc_info mcc;
6025	struct rtw89_mlo_info mlo;
6026	struct rtw89_mac_info mac;
6027	struct rtw89_fw_info fw;
6028	struct rtw89_hci_info hci;
6029	struct rtw89_efuse efuse;
6030	struct rtw89_traffic_stats stats;
6031	struct rtw89_rfe_data *rfe_data;
6032	enum rtw89_custid custid;
6033
6034	struct rtw89_sta_link __rcu *assoc_link_on_macid[RTW89_MAX_MAC_ID_NUM];
6035	refcount_t refcount_ap_info;
6036
6037	struct list_head rtwvifs_list;
6038	/* used to protect rf read write */
6039	struct mutex rf_mutex;
6040	struct workqueue_struct *txq_wq;
6041	struct work_struct txq_work;
6042	struct delayed_work txq_reinvoke_work;
6043	/* used to protect ba_list and forbid_ba_list */
6044	spinlock_t ba_lock;
6045	/* txqs to setup ba session */
6046	struct list_head ba_list;
6047	/* txqs to forbid ba session */
6048	struct list_head forbid_ba_list;
6049	struct work_struct ba_work;
6050	/* used to protect rpwm */
6051	spinlock_t rpwm_lock;
6052
6053	struct list_head tx_waits;
6054	struct wiphy_delayed_work tx_wait_work;
6055
6056	struct rtw89_tx_rpt tx_rpt;
6057
6058	struct rtw89_cam_info cam_info;
6059
6060	struct sk_buff_head c2h_queue;
6061	struct wiphy_work c2h_work;
6062	struct wiphy_work ips_work;
6063	struct wiphy_work cancel_6ghz_probe_work;
6064	struct work_struct load_firmware_work;
6065
6066	struct list_head early_h2c_list;
6067
6068	struct rtw89_ser ser;
6069
6070	DECLARE_BITMAP(hw_port, RTW89_PORT_NUM);
6071	DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM);
6072	DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS);
6073	DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM);
6074	DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS);
6075
6076	struct rtw89_phy_stat phystat;
6077	struct rtw89_rfk_wait_info rfk_wait;
6078	struct rtw89_dack_info dack;
6079	struct rtw89_iqk_info iqk;
6080	struct rtw89_dpk_info dpk;
6081	struct rtw89_rfk_mcc_info rfk_mcc;
6082	struct rtw89_lck_info lck;
6083	struct rtw89_rx_dck_info rx_dck;
6084	bool is_tssi_mode[RF_PATH_MAX];
6085	bool is_bt_iqk_timeout;
6086
6087	struct rtw89_fem_info fem;
6088	struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM];
6089	struct rtw89_tssi_info tssi;
6090	struct rtw89_power_trim_info pwr_trim;
6091
6092	struct rtw89_cfo_tracking_info cfo_tracking;
6093	union {
6094		struct rtw89_phy_bb_gain_info ax;
6095		struct rtw89_phy_bb_gain_info_be be;
6096	} bb_gain;
6097	struct rtw89_phy_efuse_gain efuse_gain;
6098	struct rtw89_phy_ul_tb_info ul_tb_info;
6099	struct rtw89_antdiv_info antdiv;
6100
6101	struct rtw89_bb_ctx {
6102		enum rtw89_phy_idx phy_idx;
6103		struct rtw89_env_monitor_info env_monitor;
6104		struct rtw89_dig_info dig;
6105		struct rtw89_phy_ch_info ch_info;
6106		struct rtw89_edcca_bak edcca_bak;
6107	} bbs[RTW89_PHY_NUM];
6108
6109	struct wiphy_delayed_work track_work;
6110	struct wiphy_delayed_work track_ps_work;
6111	struct wiphy_delayed_work chanctx_work;
6112	struct wiphy_delayed_work coex_act1_work;
6113	struct wiphy_delayed_work coex_bt_devinfo_work;
6114	struct wiphy_delayed_work coex_rfk_chk_work;
6115	struct wiphy_delayed_work cfo_track_work;
6116	struct wiphy_delayed_work mcc_prepare_done_work;
6117	struct delayed_work forbid_ba_work;
6118	struct wiphy_delayed_work antdiv_work;
6119	struct rtw89_ppdu_sts_info ppdu_sts;
6120	u8 total_sta_assoc;
6121	bool scanning;
6122
6123	struct rtw89_regulatory_info regulatory;
6124	struct rtw89_sar_info sar;
6125	struct rtw89_tas_info tas;
6126	struct rtw89_ant_gain_info ant_gain;
6127
6128	struct rtw89_btc btc;
6129	enum rtw89_ps_mode ps_mode;
6130	bool lps_enabled;
6131	u8 ps_hang_cnt;
6132
6133	struct rtw89_wow_param wow;
6134
6135	/* napi structure */
6136	struct net_device *netdev;
6137	struct napi_struct napi;
6138	int napi_budget_countdown;
6139
6140	struct rtw89_debugfs *debugfs;
6141	struct rtw89_vif *pure_monitor_mode_vif;
6142
6143	/* HCI related data, keep last */
6144	u8 priv[] __aligned(sizeof(void *));
6145};
6146
6147struct rtw89_link_conf_container {
6148	struct ieee80211_bss_conf *link_conf[IEEE80211_MLD_MAX_NUM_LINKS];
6149};
6150
6151struct rtw89_vif_ml_trans {
6152	u16 mediate_links;
6153	u16 links_to_del;
6154	u16 links_to_add;
6155};
6156
6157#define RTW89_VIF_IDLE_LINK_ID 0
6158
6159struct rtw89_vif {
6160	struct rtw89_dev *rtwdev;
6161	struct list_head list;
6162	struct list_head mgnt_entry;
6163	struct rtw89_link_conf_container __rcu *snap_link_confs;
6164
6165	u8 mac_addr[ETH_ALEN];
6166	__be32 ip_addr;
6167
6168	struct rtw89_traffic_stats stats;
6169	struct rtw89_traffic_stats stats_ps;
6170	u32 tdls_peer;
6171
6172	struct ieee80211_scan_ies *scan_ies;
6173	struct cfg80211_scan_request *scan_req;
6174
6175	struct rtw89_roc roc;
6176	bool offchan;
6177
6178	enum rtw89_mlo_mode mlo_mode;
6179	struct rtw89_vif_ml_trans ml_trans;
6180
6181	struct list_head dlink_pool;
6182	u8 links_inst_valid_num;
6183	DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
6184	struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS];
6185	struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num);
6186};
6187
6188static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link,
6189						  const struct rtw89_vif *rtwvif,
6190						  unsigned int link_id)
6191{
6192	*rtwvif_link = rtwvif->links[link_id];
6193	return !!*rtwvif_link;
6194}
6195
6196#define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \
6197	for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \
6198		if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id))
6199
6200enum rtw89_sta_flags {
6201	RTW89_REMOTE_STA_IN_PS,
6202
6203	NUM_OF_RTW89_STA_FLAGS,
6204};
6205
6206struct rtw89_sta {
6207	struct rtw89_dev *rtwdev;
6208	struct rtw89_vif *rtwvif;
6209
6210	DECLARE_BITMAP(flags, NUM_OF_RTW89_STA_FLAGS);
6211
6212	bool disassoc;
6213
6214	struct sk_buff_head roc_queue;
6215
6216	struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
6217	DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS);
6218
6219	DECLARE_BITMAP(pairwise_sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
6220
6221	struct list_head dlink_pool;
6222	u8 links_inst_valid_num;
6223	DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
6224	struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS];
6225	struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num);
6226};
6227
6228static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link,
6229						  const struct rtw89_sta *rtwsta,
6230						  unsigned int link_id)
6231{
6232	*rtwsta_link = rtwsta->links[link_id];
6233	return !!*rtwsta_link;
6234}
6235
6236#define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \
6237	for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \
6238		if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id))
6239
6240static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif)
6241{
6242	/* const after init, so no need to check if active first */
6243	return rtwvif->links_inst[0].mac_id;
6244}
6245
6246static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif)
6247{
6248	/* const after init, so no need to check if active first */
6249	return rtwvif->links_inst[0].port;
6250}
6251
6252static inline struct rtw89_vif_link *
6253rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index)
6254{
6255	if (index >= rtwvif->links_inst_valid_num ||
6256	    !test_bit(index, rtwvif->links_inst_map))
6257		return NULL;
6258	return &rtwvif->links_inst[index];
6259}
6260
6261static inline
6262u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link)
6263{
6264	struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
6265
6266	return rtwvif_link - rtwvif->links_inst;
6267}
6268
6269static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta)
6270{
6271	/* const after init, so no need to check if active first */
6272	return rtwsta->links_inst[0].mac_id;
6273}
6274
6275static inline struct rtw89_sta_link *
6276rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index)
6277{
6278	if (index >= rtwsta->links_inst_valid_num ||
6279	    !test_bit(index, rtwsta->links_inst_map))
6280		return NULL;
6281	return &rtwsta->links_inst[index];
6282}
6283
6284static inline
6285u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link)
6286{
6287	struct rtw89_sta *rtwsta = rtwsta_link->rtwsta;
6288
6289	return rtwsta_link - rtwsta->links_inst;
6290}
6291
6292static inline void rtw89_assoc_link_set(struct rtw89_sta_link *rtwsta_link)
6293{
6294	struct rtw89_sta *rtwsta = rtwsta_link->rtwsta;
6295	struct rtw89_dev *rtwdev = rtwsta->rtwdev;
6296
6297	rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id],
6298			   rtwsta_link);
6299}
6300
6301static inline void rtw89_assoc_link_clr(struct rtw89_sta_link *rtwsta_link)
6302{
6303	struct rtw89_sta *rtwsta = rtwsta_link->rtwsta;
6304	struct rtw89_dev *rtwdev = rtwsta->rtwdev;
6305
6306	rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id],
6307			   NULL);
6308	synchronize_rcu();
6309}
6310
6311static inline struct rtw89_sta_link *
6312rtw89_assoc_link_rcu_dereference(struct rtw89_dev *rtwdev, u8 macid)
6313{
6314	return rcu_dereference(rtwdev->assoc_link_on_macid[macid]);
6315}
6316
6317#define rtw89_get_designated_link(links_holder) \
6318({ \
6319	typeof(links_holder) p = links_holder; \
6320	list_first_entry_or_null(&p->dlink_pool, typeof(*p->links_inst), dlink_schd); \
6321})
6322
6323static inline void rtw89_tx_wait_release(struct rtw89_tx_wait_info *wait)
6324{
6325	dev_kfree_skb_any(wait->skb);
6326	kfree_rcu(wait, rcu_head);
6327}
6328
6329static inline void rtw89_tx_wait_list_clear(struct rtw89_dev *rtwdev)
6330{
6331	struct rtw89_tx_wait_info *wait, *tmp;
6332
6333	lockdep_assert_wiphy(rtwdev->hw->wiphy);
6334
6335	list_for_each_entry_safe(wait, tmp, &rtwdev->tx_waits, list) {
6336		if (!completion_done(&wait->completion))
6337			continue;
6338		list_del(&wait->list);
6339		rtw89_tx_wait_release(wait);
6340	}
6341}
6342
6343static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev,
6344				     struct rtw89_core_tx_request *tx_req)
6345{
6346	return rtwdev->hci.ops->tx_write(rtwdev, tx_req);
6347}
6348
6349static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)
6350{
6351	rtwdev->hci.ops->reset(rtwdev);
6352	/* hci.ops->reset must complete all pending TX wait SKBs */
6353	rtw89_tx_wait_list_clear(rtwdev);
6354}
6355
6356static inline int rtw89_hci_start(struct rtw89_dev *rtwdev)
6357{
6358	return rtwdev->hci.ops->start(rtwdev);
6359}
6360
6361static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev)
6362{
6363	rtwdev->hci.ops->stop(rtwdev);
6364}
6365
6366static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev)
6367{
6368	return rtwdev->hci.ops->deinit(rtwdev);
6369}
6370
6371static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause)
6372{
6373	rtwdev->hci.ops->pause(rtwdev, pause);
6374}
6375
6376static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power)
6377{
6378	rtwdev->hci.ops->switch_mode(rtwdev, low_power);
6379}
6380
6381static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev)
6382{
6383	rtwdev->hci.ops->recalc_int_mit(rtwdev);
6384}
6385
6386static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch)
6387{
6388	return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch);
6389}
6390
6391static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
6392{
6393	return rtwdev->hci.ops->tx_kick_off(rtwdev, txch);
6394}
6395
6396static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev)
6397{
6398	return rtwdev->hci.ops->mac_pre_deinit(rtwdev);
6399}
6400
6401static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues,
6402					  bool drop)
6403{
6404	if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
6405		return;
6406
6407	if (rtwdev->hci.ops->flush_queues)
6408		return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop);
6409}
6410
6411static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev)
6412{
6413	if (rtwdev->hci.ops->recovery_start)
6414		rtwdev->hci.ops->recovery_start(rtwdev);
6415}
6416
6417static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev)
6418{
6419	if (rtwdev->hci.ops->recovery_complete)
6420		rtwdev->hci.ops->recovery_complete(rtwdev);
6421}
6422
6423static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev)
6424{
6425	if (rtwdev->hci.ops->enable_intr)
6426		rtwdev->hci.ops->enable_intr(rtwdev);
6427}
6428
6429static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev)
6430{
6431	if (rtwdev->hci.ops->disable_intr)
6432		rtwdev->hci.ops->disable_intr(rtwdev);
6433}
6434
6435static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable)
6436{
6437	if (rtwdev->hci.ops->ctrl_txdma_ch)
6438		rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable);
6439}
6440
6441static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable)
6442{
6443	if (rtwdev->hci.ops->ctrl_txdma_fw_ch)
6444		rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable);
6445}
6446
6447static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable)
6448{
6449	if (rtwdev->hci.ops->ctrl_trxhci)
6450		rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable);
6451}
6452
6453static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev)
6454{
6455	int ret = 0;
6456
6457	if (rtwdev->hci.ops->poll_txdma_ch_idle)
6458		ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev);
6459	return ret;
6460}
6461
6462static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev)
6463{
6464	if (rtwdev->hci.ops->clr_idx_all)
6465		rtwdev->hci.ops->clr_idx_all(rtwdev);
6466}
6467
6468static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev)
6469{
6470	int ret = 0;
6471
6472	if (rtwdev->hci.ops->rst_bdram)
6473		ret = rtwdev->hci.ops->rst_bdram(rtwdev);
6474	return ret;
6475}
6476
6477static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev)
6478{
6479	if (rtwdev->hci.ops->clear)
6480		rtwdev->hci.ops->clear(rtwdev, pdev);
6481}
6482
6483static inline
6484struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb)
6485{
6486	/*
6487	 * This should be used by/after rtw89_hci_tx_write() and before doing
6488	 * ieee80211_tx_info_clear_status().
6489	 */
6490	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
6491
6492	return (struct rtw89_tx_skb_data *)info->driver_data;
6493}
6494
6495static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
6496{
6497	return rtwdev->hci.ops->read8(rtwdev, addr);
6498}
6499
6500static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr)
6501{
6502	return rtwdev->hci.ops->read16(rtwdev, addr);
6503}
6504
6505static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)
6506{
6507	return rtwdev->hci.ops->read32(rtwdev, addr);
6508}
6509
6510static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
6511{
6512	rtwdev->hci.ops->write8(rtwdev, addr, data);
6513}
6514
6515static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
6516{
6517	rtwdev->hci.ops->write16(rtwdev, addr, data);
6518}
6519
6520static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
6521{
6522	rtwdev->hci.ops->write32(rtwdev, addr, data);
6523}
6524
6525static inline void
6526rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
6527{
6528	u8 val;
6529
6530	val = rtw89_read8(rtwdev, addr);
6531	rtw89_write8(rtwdev, addr, val | bit);
6532}
6533
6534static inline void
6535rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
6536{
6537	u16 val;
6538
6539	val = rtw89_read16(rtwdev, addr);
6540	rtw89_write16(rtwdev, addr, val | bit);
6541}
6542
6543static inline void
6544rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
6545{
6546	u32 val;
6547
6548	val = rtw89_read32(rtwdev, addr);
6549	rtw89_write32(rtwdev, addr, val | bit);
6550}
6551
6552static inline void
6553rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
6554{
6555	u8 val;
6556
6557	val = rtw89_read8(rtwdev, addr);
6558	rtw89_write8(rtwdev, addr, val & ~bit);
6559}
6560
6561static inline void
6562rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
6563{
6564	u16 val;
6565
6566	val = rtw89_read16(rtwdev, addr);
6567	rtw89_write16(rtwdev, addr, val & ~bit);
6568}
6569
6570static inline void
6571rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
6572{
6573	u32 val;
6574
6575	val = rtw89_read32(rtwdev, addr);
6576	rtw89_write32(rtwdev, addr, val & ~bit);
6577}
6578
6579static inline u32
6580rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
6581{
6582	u32 shift = __ffs(mask);
6583	u32 orig;
6584	u32 ret;
6585
6586	orig = rtw89_read32(rtwdev, addr);
6587	ret = (orig & mask) >> shift;
6588
6589	return ret;
6590}
6591
6592static inline u16
6593rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
6594{
6595	u32 shift = __ffs(mask);
6596	u32 orig;
6597	u32 ret;
6598
6599	orig = rtw89_read16(rtwdev, addr);
6600	ret = (orig & mask) >> shift;
6601
6602	return ret;
6603}
6604
6605static inline u8
6606rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
6607{
6608	u32 shift = __ffs(mask);
6609	u32 orig;
6610	u32 ret;
6611
6612	orig = rtw89_read8(rtwdev, addr);
6613	ret = (orig & mask) >> shift;
6614
6615	return ret;
6616}
6617
6618static inline void
6619rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data)
6620{
6621	u32 shift = __ffs(mask);
6622	u32 orig;
6623	u32 set;
6624
6625	WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
6626
6627	orig = rtw89_read32(rtwdev, addr);
6628	set = (orig & ~mask) | ((data << shift) & mask);
6629	rtw89_write32(rtwdev, addr, set);
6630}
6631
6632static inline void
6633rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data)
6634{
6635	u32 shift;
6636	u16 orig, set;
6637
6638	mask &= 0xffff;
6639	shift = __ffs(mask);
6640
6641	orig = rtw89_read16(rtwdev, addr);
6642	set = (orig & ~mask) | ((data << shift) & mask);
6643	rtw89_write16(rtwdev, addr, set);
6644}
6645
6646static inline void
6647rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data)
6648{
6649	u32 shift;
6650	u8 orig, set;
6651
6652	mask &= 0xff;
6653	shift = __ffs(mask);
6654
6655	orig = rtw89_read8(rtwdev, addr);
6656	set = (orig & ~mask) | ((data << shift) & mask);
6657	rtw89_write8(rtwdev, addr, set);
6658}
6659
6660static inline u32
6661rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
6662	      u32 addr, u32 mask)
6663{
6664	u32 val;
6665
6666	mutex_lock(&rtwdev->rf_mutex);
6667	val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
6668	mutex_unlock(&rtwdev->rf_mutex);
6669
6670	return val;
6671}
6672
6673static inline void
6674rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
6675	       u32 addr, u32 mask, u32 data)
6676{
6677	mutex_lock(&rtwdev->rf_mutex);
6678	rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
6679	mutex_unlock(&rtwdev->rf_mutex);
6680}
6681
6682static inline u32 rtw89_read32_pci_cfg(struct rtw89_dev *rtwdev, u32 addr)
6683{
6684	if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE ||
6685	    !rtwdev->hci.ops->read32_pci_cfg)
6686		return RTW89_R32_EA;
6687
6688	return rtwdev->hci.ops->read32_pci_cfg(rtwdev, addr);
6689}
6690
6691static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)
6692{
6693	void *p = rtwtxq;
6694
6695	return container_of(p, struct ieee80211_txq, drv_priv);
6696}
6697
6698static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev,
6699				       struct ieee80211_txq *txq)
6700{
6701	struct rtw89_txq *rtwtxq;
6702
6703	if (!txq)
6704		return;
6705
6706	rtwtxq = (struct rtw89_txq *)txq->drv_priv;
6707	INIT_LIST_HEAD(&rtwtxq->list);
6708}
6709
6710static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif)
6711{
6712	void *p = rtwvif;
6713
6714	return container_of(p, struct ieee80211_vif, drv_priv);
6715}
6716
6717static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif)
6718{
6719	return rtwvif ? rtwvif_to_vif(rtwvif) : NULL;
6720}
6721
6722static inline
6723struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link)
6724{
6725	return rtwvif_to_vif(rtwvif_link->rtwvif);
6726}
6727
6728static inline
6729struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link)
6730{
6731	return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL;
6732}
6733
6734static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif)
6735{
6736	return (struct rtw89_vif *)vif->drv_priv;
6737}
6738
6739static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif)
6740{
6741	return vif ? vif_to_rtwvif(vif) : NULL;
6742}
6743
6744static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta)
6745{
6746	void *p = rtwsta;
6747
6748	return container_of(p, struct ieee80211_sta, drv_priv);
6749}
6750
6751static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta)
6752{
6753	return rtwsta ? rtwsta_to_sta(rtwsta) : NULL;
6754}
6755
6756static inline
6757struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link)
6758{
6759	return rtwsta_to_sta(rtwsta_link->rtwsta);
6760}
6761
6762static inline
6763struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link)
6764{
6765	return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL;
6766}
6767
6768static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta)
6769{
6770	return (struct rtw89_sta *)sta->drv_priv;
6771}
6772
6773static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta)
6774{
6775	return sta ? sta_to_rtwsta(sta) : NULL;
6776}
6777
6778static inline struct ieee80211_bss_conf *
6779__rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink)
6780{
6781	struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
6782	struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
6783	struct rtw89_link_conf_container *snap;
6784	struct ieee80211_bss_conf *bss_conf;
6785
6786	snap = rcu_dereference(rtwvif->snap_link_confs);
6787	if (snap) {
6788		bss_conf = snap->link_conf[rtwvif_link->link_id];
6789		goto out;
6790	}
6791
6792	bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]);
6793
6794out:
6795	if (unlikely(!bss_conf)) {
6796		*nolink = true;
6797		return &vif->bss_conf;
6798	}
6799
6800	*nolink = false;
6801	return bss_conf;
6802}
6803
6804#define rtw89_vif_rcu_dereference_link(rtwvif_link, assert)		\
6805({									\
6806	typeof(rtwvif_link) p = rtwvif_link;				\
6807	struct ieee80211_bss_conf *bss_conf;				\
6808	bool nolink;							\
6809									\
6810	bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink);	\
6811	if (unlikely(nolink) && (assert))				\
6812		rtw89_err(p->rtwvif->rtwdev,				\
6813			  "%s: cannot find exact bss_conf for link_id %u\n",\
6814			  __func__, p->link_id);			\
6815	bss_conf;							\
6816})
6817
6818static inline struct ieee80211_link_sta *
6819__rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink)
6820{
6821	struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
6822	struct ieee80211_link_sta *link_sta;
6823
6824	link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]);
6825	if (unlikely(!link_sta)) {
6826		*nolink = true;
6827		return &sta->deflink;
6828	}
6829
6830	*nolink = false;
6831	return link_sta;
6832}
6833
6834#define rtw89_sta_rcu_dereference_link(rtwsta_link, assert)		\
6835({									\
6836	typeof(rtwsta_link) p = rtwsta_link;				\
6837	struct ieee80211_link_sta *link_sta;				\
6838	bool nolink;							\
6839									\
6840	link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink);	\
6841	if (unlikely(nolink) && (assert))				\
6842		rtw89_err(p->rtwsta->rtwdev,				\
6843			  "%s: cannot find exact link_sta for link_id %u\n",\
6844			  __func__, p->link_id);			\
6845	link_sta;							\
6846})
6847
6848static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)
6849{
6850	if (hw_bw == RTW89_CHANNEL_WIDTH_160)
6851		return RATE_INFO_BW_160;
6852	else if (hw_bw == RTW89_CHANNEL_WIDTH_80)
6853		return RATE_INFO_BW_80;
6854	else if (hw_bw == RTW89_CHANNEL_WIDTH_40)
6855		return RATE_INFO_BW_40;
6856	else
6857		return RATE_INFO_BW_20;
6858}
6859
6860static inline
6861enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)
6862{
6863	switch (hw_band) {
6864	default:
6865	case RTW89_BAND_2G:
6866		return NL80211_BAND_2GHZ;
6867	case RTW89_BAND_5G:
6868		return NL80211_BAND_5GHZ;
6869	case RTW89_BAND_6G:
6870		return NL80211_BAND_6GHZ;
6871	}
6872}
6873
6874static inline
6875enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)
6876{
6877	switch (nl_band) {
6878	default:
6879	case NL80211_BAND_2GHZ:
6880		return RTW89_BAND_2G;
6881	case NL80211_BAND_5GHZ:
6882		return RTW89_BAND_5G;
6883	case NL80211_BAND_6GHZ:
6884		return RTW89_BAND_6G;
6885	}
6886}
6887
6888static inline
6889enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width)
6890{
6891	switch (width) {
6892	default:
6893		WARN(1, "Not support bandwidth %d\n", width);
6894		fallthrough;
6895	case NL80211_CHAN_WIDTH_20_NOHT:
6896	case NL80211_CHAN_WIDTH_20:
6897		return RTW89_CHANNEL_WIDTH_20;
6898	case NL80211_CHAN_WIDTH_40:
6899		return RTW89_CHANNEL_WIDTH_40;
6900	case NL80211_CHAN_WIDTH_80:
6901		return RTW89_CHANNEL_WIDTH_80;
6902	case NL80211_CHAN_WIDTH_160:
6903		return RTW89_CHANNEL_WIDTH_160;
6904	}
6905}
6906
6907static inline
6908enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua)
6909{
6910	switch (rua) {
6911	default:
6912		WARN(1, "Invalid RU allocation: %d\n", rua);
6913		fallthrough;
6914	case 0 ... 36:
6915		return NL80211_RATE_INFO_HE_RU_ALLOC_26;
6916	case 37 ... 52:
6917		return NL80211_RATE_INFO_HE_RU_ALLOC_52;
6918	case 53 ... 60:
6919		return NL80211_RATE_INFO_HE_RU_ALLOC_106;
6920	case 61 ... 64:
6921		return NL80211_RATE_INFO_HE_RU_ALLOC_242;
6922	case 65 ... 66:
6923		return NL80211_RATE_INFO_HE_RU_ALLOC_484;
6924	case 67:
6925		return NL80211_RATE_INFO_HE_RU_ALLOC_996;
6926	case 68:
6927		return NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
6928	}
6929}
6930
6931static inline
6932struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link,
6933						   struct rtw89_sta_link *rtwsta_link)
6934{
6935	if (rtwsta_link) {
6936		struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
6937
6938		if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls)
6939			return &rtwsta_link->addr_cam;
6940	}
6941	return &rtwvif_link->addr_cam;
6942}
6943
6944static inline
6945struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link,
6946						     struct rtw89_sta_link *rtwsta_link)
6947{
6948	if (rtwsta_link) {
6949		struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
6950
6951		if (sta->tdls)
6952			return &rtwsta_link->bssid_cam;
6953	}
6954	return &rtwvif_link->bssid_cam;
6955}
6956
6957static inline
6958void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev,
6959				    struct rtw89_channel_help_params *p,
6960				    const struct rtw89_chan *chan,
6961				    enum rtw89_mac_idx mac_idx,
6962				    enum rtw89_phy_idx phy_idx)
6963{
6964	rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan,
6965					    mac_idx, phy_idx);
6966}
6967
6968static inline
6969void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev,
6970				 struct rtw89_channel_help_params *p,
6971				 const struct rtw89_chan *chan,
6972				 enum rtw89_mac_idx mac_idx,
6973				 enum rtw89_phy_idx phy_idx)
6974{
6975	rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan,
6976					    mac_idx, phy_idx);
6977}
6978
6979static inline
6980const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev,
6981						  enum rtw89_chanctx_idx idx)
6982{
6983	struct rtw89_hal *hal = &rtwdev->hal;
6984	enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx);
6985
6986	if (roc_idx == idx)
6987		return &hal->roc_chandef;
6988
6989	return &hal->chanctx[idx].chandef;
6990}
6991
6992static inline
6993const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev,
6994					enum rtw89_chanctx_idx idx)
6995{
6996	struct rtw89_hal *hal = &rtwdev->hal;
6997
6998	return &hal->chanctx[idx].chan;
6999}
7000
7001static inline
7002const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev,
7003						enum rtw89_chanctx_idx idx)
7004{
7005	struct rtw89_hal *hal = &rtwdev->hal;
7006
7007	return &hal->chanctx[idx].rcd;
7008}
7009
7010static inline
7011const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan)
7012{
7013	const struct rtw89_chanctx *chanctx =
7014		container_of_const(chan, struct rtw89_chanctx, chan);
7015
7016	return &chanctx->rcd;
7017}
7018
7019static inline
7020const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev)
7021{
7022	struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif;
7023
7024	if (rtwvif_link)
7025		return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
7026	else
7027		return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
7028}
7029
7030static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
7031{
7032	const struct rtw89_chip_info *chip = rtwdev->chip;
7033
7034	if (chip->ops->fem_setup)
7035		chip->ops->fem_setup(rtwdev);
7036}
7037
7038static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev)
7039{
7040	const struct rtw89_chip_info *chip = rtwdev->chip;
7041
7042	if (chip->ops->rfe_gpio)
7043		chip->ops->rfe_gpio(rtwdev);
7044}
7045
7046static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev)
7047{
7048	const struct rtw89_chip_info *chip = rtwdev->chip;
7049
7050	if (chip->ops->rfk_hw_init)
7051		chip->ops->rfk_hw_init(rtwdev);
7052}
7053
7054static inline
7055void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev)
7056{
7057	const struct rtw89_chip_info *chip = rtwdev->chip;
7058
7059	if (!chip->ops->bb_preinit)
7060		return;
7061
7062	chip->ops->bb_preinit(rtwdev, RTW89_PHY_0);
7063
7064	if (rtwdev->dbcc_en)
7065		chip->ops->bb_preinit(rtwdev, RTW89_PHY_1);
7066}
7067
7068static inline
7069void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev)
7070{
7071	const struct rtw89_chip_info *chip = rtwdev->chip;
7072
7073	if (!chip->ops->bb_postinit)
7074		return;
7075
7076	chip->ops->bb_postinit(rtwdev, RTW89_PHY_0);
7077
7078	if (rtwdev->dbcc_en)
7079		chip->ops->bb_postinit(rtwdev, RTW89_PHY_1);
7080}
7081
7082static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
7083{
7084	const struct rtw89_chip_info *chip = rtwdev->chip;
7085
7086	if (chip->ops->bb_sethw)
7087		chip->ops->bb_sethw(rtwdev);
7088}
7089
7090static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev)
7091{
7092	const struct rtw89_chip_info *chip = rtwdev->chip;
7093
7094	if (chip->ops->rfk_init)
7095		chip->ops->rfk_init(rtwdev);
7096}
7097
7098static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev)
7099{
7100	const struct rtw89_chip_info *chip = rtwdev->chip;
7101
7102	if (chip->ops->rfk_init_late)
7103		chip->ops->rfk_init_late(rtwdev);
7104}
7105
7106static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev,
7107					  struct rtw89_vif_link *rtwvif_link)
7108{
7109	const struct rtw89_chip_info *chip = rtwdev->chip;
7110
7111	if (chip->ops->rfk_channel)
7112		chip->ops->rfk_channel(rtwdev, rtwvif_link);
7113}
7114
7115static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev,
7116					       enum rtw89_phy_idx phy_idx,
7117					       const struct rtw89_chan *chan)
7118{
7119	const struct rtw89_chip_info *chip = rtwdev->chip;
7120
7121	if (chip->ops->rfk_band_changed)
7122		chip->ops->rfk_band_changed(rtwdev, phy_idx, chan);
7123}
7124
7125static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev,
7126				       struct rtw89_vif_link *rtwvif_link, bool start)
7127{
7128	const struct rtw89_chip_info *chip = rtwdev->chip;
7129
7130	if (chip->ops->rfk_scan)
7131		chip->ops->rfk_scan(rtwdev, rtwvif_link, start);
7132}
7133
7134static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev)
7135{
7136	const struct rtw89_chip_info *chip = rtwdev->chip;
7137
7138	if (chip->ops->rfk_track)
7139		chip->ops->rfk_track(rtwdev);
7140}
7141
7142static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
7143{
7144	const struct rtw89_chip_info *chip = rtwdev->chip;
7145
7146	if (!chip->ops->set_txpwr_ctrl)
7147		return;
7148
7149	chip->ops->set_txpwr_ctrl(rtwdev,  RTW89_PHY_0);
7150	if (rtwdev->dbcc_en)
7151		chip->ops->set_txpwr_ctrl(rtwdev,  RTW89_PHY_1);
7152}
7153
7154static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev)
7155{
7156	const struct rtw89_chip_info *chip = rtwdev->chip;
7157
7158	if (chip->ops->power_trim)
7159		chip->ops->power_trim(rtwdev);
7160}
7161
7162static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev,
7163						enum rtw89_phy_idx phy_idx)
7164{
7165	const struct rtw89_chip_info *chip = rtwdev->chip;
7166
7167	if (chip->ops->init_txpwr_unit)
7168		chip->ops->init_txpwr_unit(rtwdev, phy_idx);
7169}
7170
7171static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev)
7172{
7173	__rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0);
7174	if (rtwdev->dbcc_en)
7175		__rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1);
7176}
7177
7178static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,
7179					enum rtw89_rf_path rf_path)
7180{
7181	const struct rtw89_chip_info *chip = rtwdev->chip;
7182
7183	if (!chip->ops->get_thermal)
7184		return 0x10;
7185
7186	return chip->ops->get_thermal(rtwdev, rf_path);
7187}
7188
7189static inline u32 rtw89_chip_chan_to_rf18_val(struct rtw89_dev *rtwdev,
7190					      const struct rtw89_chan *chan)
7191{
7192	const struct rtw89_chip_info *chip = rtwdev->chip;
7193
7194	if (!chip->ops->chan_to_rf18_val)
7195		return 0;
7196
7197	return chip->ops->chan_to_rf18_val(rtwdev, chan);
7198}
7199
7200static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
7201					 struct rtw89_rx_phy_ppdu *phy_ppdu,
7202					 struct ieee80211_rx_status *status)
7203{
7204	const struct rtw89_chip_info *chip = rtwdev->chip;
7205
7206	if (chip->ops->query_ppdu)
7207		chip->ops->query_ppdu(rtwdev, phy_ppdu, status);
7208}
7209
7210static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev,
7211						  struct rtw89_rx_phy_ppdu *phy_ppdu)
7212{
7213	const struct rtw89_chip_info *chip = rtwdev->chip;
7214
7215	if (chip->ops->convert_rpl_to_rssi)
7216		chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu);
7217}
7218
7219static inline void rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev *rtwdev,
7220					      struct rtw89_rx_desc_info *desc_info,
7221					      struct ieee80211_rx_status *rx_status)
7222{
7223	const struct rtw89_chip_info *chip = rtwdev->chip;
7224
7225	if (chip->ops->phy_rpt_to_rssi)
7226		chip->ops->phy_rpt_to_rssi(rtwdev, desc_info, rx_status);
7227}
7228
7229static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
7230					 enum rtw89_phy_idx phy_idx)
7231{
7232	const struct rtw89_chip_info *chip = rtwdev->chip;
7233
7234	if (chip->ops->ctrl_nbtg_bt_tx)
7235		chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx);
7236}
7237
7238static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev)
7239{
7240	const struct rtw89_chip_info *chip = rtwdev->chip;
7241
7242	if (chip->ops->cfg_txrx_path)
7243		chip->ops->cfg_txrx_path(rtwdev);
7244}
7245
7246static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev,
7247					       enum rtw89_phy_idx phy_idx)
7248{
7249	const struct rtw89_chip_info *chip = rtwdev->chip;
7250
7251	if (chip->ops->digital_pwr_comp)
7252		chip->ops->digital_pwr_comp(rtwdev, phy_idx);
7253}
7254
7255static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
7256					  const struct rtw89_txpwr_table *tbl)
7257{
7258	tbl->load(rtwdev, tbl);
7259}
7260
7261static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)
7262{
7263	const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
7264	const struct rtw89_regd *regd = regulatory->regd;
7265	u8 txpwr_regd = regd->txpwr_regd[band];
7266
7267	if (regulatory->txpwr_uk_follow_etsi && txpwr_regd == RTW89_UK)
7268		return RTW89_ETSI;
7269
7270	return txpwr_regd;
7271}
7272
7273static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
7274					enum rtw89_phy_idx phy_idx)
7275{
7276	const struct rtw89_chip_info *chip = rtwdev->chip;
7277
7278	if (chip->ops->ctrl_btg_bt_rx)
7279		chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx);
7280}
7281
7282static inline
7283void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev,
7284			     struct rtw89_rx_desc_info *desc_info,
7285			     u8 *data, u32 data_offset)
7286{
7287	const struct rtw89_chip_info *chip = rtwdev->chip;
7288
7289	chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset);
7290}
7291
7292static inline
7293void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev,
7294			    struct rtw89_tx_desc_info *desc_info,
7295			    void *txdesc)
7296{
7297	const struct rtw89_chip_info *chip = rtwdev->chip;
7298
7299	chip->ops->fill_txdesc(rtwdev, desc_info, txdesc);
7300}
7301
7302static inline
7303void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev,
7304				  struct rtw89_tx_desc_info *desc_info,
7305				  void *txdesc)
7306{
7307	const struct rtw89_chip_info *chip = rtwdev->chip;
7308
7309	chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc);
7310}
7311
7312static inline
7313u8 rtw89_chip_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel)
7314{
7315	const struct rtw89_chip_info *chip = rtwdev->chip;
7316
7317	return chip->ops->get_ch_dma[rtwdev->hci.type](rtwdev, qsel);
7318}
7319
7320static inline
7321void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev,
7322			    const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
7323{
7324	const struct rtw89_chip_info *chip = rtwdev->chip;
7325
7326	chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg);
7327}
7328
7329static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
7330{
7331	const struct rtw89_chip_info *chip = rtwdev->chip;
7332
7333	chip->ops->cfg_ctrl_path(rtwdev, wl);
7334}
7335
7336static inline
7337int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
7338			   u32 *tx_en, enum rtw89_sch_tx_sel sel)
7339{
7340	const struct rtw89_chip_info *chip = rtwdev->chip;
7341
7342	return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel);
7343}
7344
7345static inline
7346int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
7347{
7348	const struct rtw89_chip_info *chip = rtwdev->chip;
7349
7350	return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en);
7351}
7352
7353static inline
7354int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev,
7355				struct rtw89_vif_link *rtwvif_link,
7356				struct rtw89_sta_link *rtwsta_link)
7357{
7358	const struct rtw89_chip_info *chip = rtwdev->chip;
7359
7360	if (!chip->ops->h2c_dctl_sec_cam)
7361		return 0;
7362	return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link);
7363}
7364
7365static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)
7366{
7367	__le16 fc = hdr->frame_control;
7368
7369	if (ieee80211_has_tods(fc))
7370		return hdr->addr1;
7371	else if (ieee80211_has_fromds(fc))
7372		return hdr->addr2;
7373	else
7374		return hdr->addr3;
7375}
7376
7377static inline
7378bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta)
7379{
7380	if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
7381	    (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) ||
7382	    (link_sta->he_cap.he_cap_elem.phy_cap_info[3] &
7383			IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
7384	    (link_sta->he_cap.he_cap_elem.phy_cap_info[4] &
7385			IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER))
7386		return true;
7387	return false;
7388}
7389
7390static inline
7391bool rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta *link_sta)
7392{
7393	if (link_sta->he_cap.he_cap_elem.phy_cap_info[7] &
7394	    IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI)
7395		return true;
7396
7397	return false;
7398}
7399
7400static inline
7401bool rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta *link_sta)
7402{
7403	if (link_sta->he_cap.he_cap_elem.phy_cap_info[8] &
7404	    IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI)
7405		return true;
7406
7407	return false;
7408}
7409
7410static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,
7411						      enum rtw89_fw_type type)
7412{
7413	struct rtw89_fw_info *fw_info = &rtwdev->fw;
7414
7415	switch (type) {
7416	case RTW89_FW_WOWLAN:
7417		return &fw_info->wowlan;
7418	case RTW89_FW_LOGFMT:
7419		return &fw_info->log.suit;
7420	case RTW89_FW_BBMCU0:
7421		return &fw_info->bbmcu0;
7422	case RTW89_FW_BBMCU1:
7423		return &fw_info->bbmcu1;
7424	default:
7425		break;
7426	}
7427
7428	return &fw_info->normal;
7429}
7430
7431static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev,
7432						     unsigned int length)
7433{
7434	struct sk_buff *skb;
7435
7436	if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
7437		skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM);
7438		if (!skb)
7439			return NULL;
7440
7441		skb_reserve(skb, RTW89_RADIOTAP_ROOM);
7442		return skb;
7443	}
7444
7445	return dev_alloc_skb(length);
7446}
7447
7448static inline bool rtw89_core_is_tx_wait(struct rtw89_dev *rtwdev,
7449					 struct rtw89_tx_skb_data *skb_data)
7450{
7451	return rcu_access_pointer(skb_data->wait);
7452}
7453
7454static inline bool rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev,
7455					       struct rtw89_tx_skb_data *skb_data,
7456					       u8 tx_status)
7457{
7458	struct rtw89_tx_wait_info *wait;
7459
7460	guard(rcu)();
7461
7462	wait = rcu_dereference(skb_data->wait);
7463	if (!wait)
7464		return false;
7465
7466	wait->tx_done = tx_status == RTW89_TX_DONE;
7467	/* Don't access skb anymore after completion */
7468	complete_all(&wait->completion);
7469	return true;
7470}
7471
7472static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev)
7473{
7474	switch (rtwdev->mlo_dbcc_mode) {
7475	case MLO_1_PLUS_1_1RF:
7476	case MLO_1_PLUS_1_2RF:
7477	case DBCC_LEGACY:
7478		return true;
7479	default:
7480		return false;
7481	}
7482}
7483
7484static inline u8 rtw89_get_active_phy_bitmap(struct rtw89_dev *rtwdev)
7485{
7486	if (!rtwdev->dbcc_en)
7487		return BIT(RTW89_PHY_0);
7488
7489	switch (rtwdev->mlo_dbcc_mode) {
7490	case MLO_0_PLUS_2_1RF:
7491	case MLO_0_PLUS_2_2RF:
7492		return BIT(RTW89_PHY_1);
7493	case MLO_1_PLUS_1_1RF:
7494	case MLO_1_PLUS_1_2RF:
7495	case MLO_2_PLUS_2_2RF:
7496	case DBCC_LEGACY:
7497		return BIT(RTW89_PHY_0) | BIT(RTW89_PHY_1);
7498	case MLO_2_PLUS_0_1RF:
7499	case MLO_2_PLUS_0_2RF:
7500	default:
7501		return BIT(RTW89_PHY_0);
7502	}
7503}
7504
7505#define rtw89_for_each_active_bb(rtwdev, bb) \
7506	for (u8 __active_bb_bitmap = rtw89_get_active_phy_bitmap(rtwdev), \
7507	     __phy_idx = 0; __phy_idx < RTW89_PHY_NUM; __phy_idx++) \
7508		if (__active_bb_bitmap & BIT(__phy_idx) && \
7509		    (bb = &rtwdev->bbs[__phy_idx]))
7510
7511#define rtw89_for_each_capab_bb(rtwdev, bb) \
7512	for (u8 __phy_idx_max = rtwdev->dbcc_en ? RTW89_PHY_1 : RTW89_PHY_0, \
7513	     __phy_idx = 0; __phy_idx <= __phy_idx_max; __phy_idx++) \
7514		if ((bb = &rtwdev->bbs[__phy_idx]))
7515
7516static inline
7517struct rtw89_bb_ctx *rtw89_get_bb_ctx(struct rtw89_dev *rtwdev,
7518				      enum rtw89_phy_idx phy_idx)
7519{
7520	if (phy_idx >= RTW89_PHY_NUM)
7521		return &rtwdev->bbs[RTW89_PHY_0];
7522
7523	return &rtwdev->bbs[phy_idx];
7524}
7525
7526static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev)
7527{
7528	enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
7529
7530	if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT)
7531		return true;
7532
7533	return false;
7534}
7535
7536static inline u32 rtw89_bytes_to_mbps(u64 bytes, enum rtw89_tfc_interval interval)
7537{
7538	switch (interval) {
7539	default:
7540	case RTW89_TFC_INTERVAL_2SEC:
7541		return bytes >> 18; /* bytes/2s --> Mbps */;
7542	case RTW89_TFC_INTERVAL_100MS:
7543		return (bytes * 10) >> 17; /* bytes/100ms --> Mbps */
7544	}
7545}
7546
7547int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
7548			struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
7549int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
7550		 struct sk_buff *skb, bool fwdl);
7551void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel);
7552int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
7553				    struct rtw89_tx_wait_info *wait, int qsel,
7554				    unsigned int timeout);
7555void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
7556			    struct rtw89_tx_desc_info *desc_info,
7557			    void *txdesc);
7558void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
7559			       struct rtw89_tx_desc_info *desc_info,
7560			       void *txdesc);
7561void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev,
7562			       struct rtw89_tx_desc_info *desc_info,
7563			       void *txdesc);
7564void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
7565				     struct rtw89_tx_desc_info *desc_info,
7566				     void *txdesc);
7567void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev,
7568				     struct rtw89_tx_desc_info *desc_info,
7569				     void *txdesc);
7570u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel);
7571u8 rtw89_core_get_ch_dma_v1(struct rtw89_dev *rtwdev, u8 qsel);
7572u8 rtw89_core_get_ch_dma_v2(struct rtw89_dev *rtwdev, u8 qsel);
7573void rtw89_core_rx(struct rtw89_dev *rtwdev,
7574		   struct rtw89_rx_desc_info *desc_info,
7575		   struct sk_buff *skb);
7576void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
7577			     struct rtw89_rx_desc_info *desc_info,
7578			     u8 *data, u32 data_offset);
7579void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
7580				struct rtw89_rx_desc_info *desc_info,
7581				u8 *data, u32 data_offset);
7582void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
7583void rtw89_core_napi_stop(struct rtw89_dev *rtwdev);
7584int rtw89_core_napi_init(struct rtw89_dev *rtwdev);
7585void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev);
7586int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev,
7587			    struct rtw89_vif_link *rtwvif_link,
7588			    struct rtw89_sta_link *rtwsta_link);
7589int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev,
7590			      struct rtw89_vif_link *rtwvif_link,
7591			      struct rtw89_sta_link *rtwsta_link);
7592int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev,
7593				 struct rtw89_vif_link *rtwvif_link,
7594				 struct rtw89_sta_link *rtwsta_link);
7595int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev,
7596				   struct rtw89_vif_link *rtwvif_link,
7597				   struct rtw89_sta_link *rtwsta_link);
7598int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev,
7599			       struct rtw89_vif_link *rtwvif_link,
7600			       struct rtw89_sta_link *rtwsta_link);
7601void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
7602			       struct ieee80211_sta *sta,
7603			       struct cfg80211_tid_config *tid_config);
7604void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force);
7605void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks);
7606int rtw89_core_init(struct rtw89_dev *rtwdev);
7607void rtw89_core_deinit(struct rtw89_dev *rtwdev);
7608int rtw89_core_register(struct rtw89_dev *rtwdev);
7609void rtw89_core_unregister(struct rtw89_dev *rtwdev);
7610struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
7611					   u32 bus_data_size,
7612					   const struct rtw89_chip_info *chip,
7613					   const struct rtw89_chip_variant *variant);
7614void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev);
7615u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev);
7616void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id);
7617void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
7618		    u8 mac_id, u8 port);
7619void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
7620		    struct rtw89_sta *rtwsta, u8 mac_id);
7621struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif,
7622					  unsigned int link_id);
7623void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id);
7624struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta,
7625					  unsigned int link_id);
7626void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id);
7627void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev);
7628const struct rtw89_6ghz_span *
7629rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq);
7630void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef);
7631void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
7632			      struct rtw89_chan *chan);
7633int rtw89_set_channel(struct rtw89_dev *rtwdev);
7634u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size);
7635void rtw89_core_release_bit_map(unsigned long *addr, u8 bit);
7636void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits);
7637int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
7638				    struct rtw89_sta_link *rtwsta_link, u8 tid,
7639				    u8 *cam_idx);
7640int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
7641				    struct rtw89_sta_link *rtwsta_link, u8 tid,
7642				    u8 *cam_idx);
7643void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev,
7644				    struct ieee80211_sta *sta);
7645void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev,
7646					   struct ieee80211_sta *sta);
7647void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev,
7648					struct ieee80211_sta *sta);
7649void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc);
7650int rtw89_chip_info_setup(struct rtw89_dev *rtwdev);
7651void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
7652				       struct rtw89_vif_link *rtwvif_link);
7653bool rtw89_legacy_rate_to_bitrate(struct rtw89_dev *rtwdev, u8 legacy_rate, u16 *bitrate);
7654int rtw89_regd_setup(struct rtw89_dev *rtwdev);
7655int rtw89_regd_init_hint(struct rtw89_dev *rtwdev);
7656const char *rtw89_regd_get_string(enum rtw89_regulation_type regd);
7657void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
7658			      struct rtw89_traffic_stats *stats);
7659struct rtw89_wait_response *
7660rtw89_wait_for_cond_prep(struct rtw89_wait_info *wait, unsigned int cond)
7661__acquires(rtw89_wait);
7662int rtw89_wait_for_cond_eval(struct rtw89_wait_info *wait,
7663			     struct rtw89_wait_response *prep, int err)
7664__releases(rtw89_wait);
7665void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
7666			 const struct rtw89_completion_data *data);
7667int rtw89_core_start(struct rtw89_dev *rtwdev);
7668void rtw89_core_stop(struct rtw89_dev *rtwdev);
7669void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work);
7670void rtw89_core_csa_beacon_work(struct wiphy *wiphy, struct wiphy_work *work);
7671int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
7672			     bool qos, bool ps, int timeout);
7673void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work);
7674void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
7675void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
7676void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
7677			   const u8 *mac_addr, bool hw_scan);
7678void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
7679			      struct rtw89_vif_link *rtwvif_link, bool hw_scan);
7680int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
7681			  bool active);
7682void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev,
7683			      struct rtw89_vif_link *rtwvif_link,
7684			      struct ieee80211_bss_conf *bss_conf);
7685void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event);
7686int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
7687			   unsigned int link_id);
7688
7689#endif