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core.c
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linux-6.19.14/drivers/net/wireless/realtek/rtw89/core.c
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4#include <linux/ip.h> 5#include <linux/sort.h> 6#include <linux/udp.h> 7 8#include "cam.h" 9#include "chan.h" 10#include "coex.h" 11#include "core.h" 12#include "efuse.h" 13#include "fw.h" 14#include "mac.h" 15#include "phy.h" 16#include "ps.h" 17#include "reg.h" 18#include "sar.h" 19#include "ser.h" 20#include "txrx.h" 21#include "util.h" 22#include "wow.h" 23 24static bool rtw89_disable_ps_mode; 25module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 26MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 27 28#define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 29 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 30#define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 31 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 32#define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 33 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 34#define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 35 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 36#define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 37 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 38 39static struct ieee80211_channel rtw89_channels_2ghz[] = { 40 RTW89_DEF_CHAN_2G(2412, 1), 41 RTW89_DEF_CHAN_2G(2417, 2), 42 RTW89_DEF_CHAN_2G(2422, 3), 43 RTW89_DEF_CHAN_2G(2427, 4), 44 RTW89_DEF_CHAN_2G(2432, 5), 45 RTW89_DEF_CHAN_2G(2437, 6), 46 RTW89_DEF_CHAN_2G(2442, 7), 47 RTW89_DEF_CHAN_2G(2447, 8), 48 RTW89_DEF_CHAN_2G(2452, 9), 49 RTW89_DEF_CHAN_2G(2457, 10), 50 RTW89_DEF_CHAN_2G(2462, 11), 51 RTW89_DEF_CHAN_2G(2467, 12), 52 RTW89_DEF_CHAN_2G(2472, 13), 53 RTW89_DEF_CHAN_2G(2484, 14), 54}; 55 56static struct ieee80211_channel rtw89_channels_5ghz[] = { 57 RTW89_DEF_CHAN_5G(5180, 36), 58 RTW89_DEF_CHAN_5G(5200, 40), 59 RTW89_DEF_CHAN_5G(5220, 44), 60 RTW89_DEF_CHAN_5G(5240, 48), 61 RTW89_DEF_CHAN_5G(5260, 52), 62 RTW89_DEF_CHAN_5G(5280, 56), 63 RTW89_DEF_CHAN_5G(5300, 60), 64 RTW89_DEF_CHAN_5G(5320, 64), 65 RTW89_DEF_CHAN_5G(5500, 100), 66 RTW89_DEF_CHAN_5G(5520, 104), 67 RTW89_DEF_CHAN_5G(5540, 108), 68 RTW89_DEF_CHAN_5G(5560, 112), 69 RTW89_DEF_CHAN_5G(5580, 116), 70 RTW89_DEF_CHAN_5G(5600, 120), 71 RTW89_DEF_CHAN_5G(5620, 124), 72 RTW89_DEF_CHAN_5G(5640, 128), 73 RTW89_DEF_CHAN_5G(5660, 132), 74 RTW89_DEF_CHAN_5G(5680, 136), 75 RTW89_DEF_CHAN_5G(5700, 140), 76 RTW89_DEF_CHAN_5G(5720, 144), 77 RTW89_DEF_CHAN_5G(5745, 149), 78 RTW89_DEF_CHAN_5G(5765, 153), 79 RTW89_DEF_CHAN_5G(5785, 157), 80 RTW89_DEF_CHAN_5G(5805, 161), 81 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 82 RTW89_DEF_CHAN_5G(5845, 169), 83 RTW89_DEF_CHAN_5G(5865, 173), 84 RTW89_DEF_CHAN_5G(5885, 177), 85}; 86 87static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM == 88 ARRAY_SIZE(rtw89_channels_5ghz)); 89 90static struct ieee80211_channel rtw89_channels_6ghz[] = { 91 RTW89_DEF_CHAN_6G(5955, 1), 92 RTW89_DEF_CHAN_6G(5975, 5), 93 RTW89_DEF_CHAN_6G(5995, 9), 94 RTW89_DEF_CHAN_6G(6015, 13), 95 RTW89_DEF_CHAN_6G(6035, 17), 96 RTW89_DEF_CHAN_6G(6055, 21), 97 RTW89_DEF_CHAN_6G(6075, 25), 98 RTW89_DEF_CHAN_6G(6095, 29), 99 RTW89_DEF_CHAN_6G(6115, 33), 100 RTW89_DEF_CHAN_6G(6135, 37), 101 RTW89_DEF_CHAN_6G(6155, 41), 102 RTW89_DEF_CHAN_6G(6175, 45), 103 RTW89_DEF_CHAN_6G(6195, 49), 104 RTW89_DEF_CHAN_6G(6215, 53), 105 RTW89_DEF_CHAN_6G(6235, 57), 106 RTW89_DEF_CHAN_6G(6255, 61), 107 RTW89_DEF_CHAN_6G(6275, 65), 108 RTW89_DEF_CHAN_6G(6295, 69), 109 RTW89_DEF_CHAN_6G(6315, 73), 110 RTW89_DEF_CHAN_6G(6335, 77), 111 RTW89_DEF_CHAN_6G(6355, 81), 112 RTW89_DEF_CHAN_6G(6375, 85), 113 RTW89_DEF_CHAN_6G(6395, 89), 114 RTW89_DEF_CHAN_6G(6415, 93), 115 RTW89_DEF_CHAN_6G(6435, 97), 116 RTW89_DEF_CHAN_6G(6455, 101), 117 RTW89_DEF_CHAN_6G(6475, 105), 118 RTW89_DEF_CHAN_6G(6495, 109), 119 RTW89_DEF_CHAN_6G(6515, 113), 120 RTW89_DEF_CHAN_6G(6535, 117), 121 RTW89_DEF_CHAN_6G(6555, 121), 122 RTW89_DEF_CHAN_6G(6575, 125), 123 RTW89_DEF_CHAN_6G(6595, 129), 124 RTW89_DEF_CHAN_6G(6615, 133), 125 RTW89_DEF_CHAN_6G(6635, 137), 126 RTW89_DEF_CHAN_6G(6655, 141), 127 RTW89_DEF_CHAN_6G(6675, 145), 128 RTW89_DEF_CHAN_6G(6695, 149), 129 RTW89_DEF_CHAN_6G(6715, 153), 130 RTW89_DEF_CHAN_6G(6735, 157), 131 RTW89_DEF_CHAN_6G(6755, 161), 132 RTW89_DEF_CHAN_6G(6775, 165), 133 RTW89_DEF_CHAN_6G(6795, 169), 134 RTW89_DEF_CHAN_6G(6815, 173), 135 RTW89_DEF_CHAN_6G(6835, 177), 136 RTW89_DEF_CHAN_6G(6855, 181), 137 RTW89_DEF_CHAN_6G(6875, 185), 138 RTW89_DEF_CHAN_6G(6895, 189), 139 RTW89_DEF_CHAN_6G(6915, 193), 140 RTW89_DEF_CHAN_6G(6935, 197), 141 RTW89_DEF_CHAN_6G(6955, 201), 142 RTW89_DEF_CHAN_6G(6975, 205), 143 RTW89_DEF_CHAN_6G(6995, 209), 144 RTW89_DEF_CHAN_6G(7015, 213), 145 RTW89_DEF_CHAN_6G(7035, 217), 146 RTW89_DEF_CHAN_6G(7055, 221), 147 RTW89_DEF_CHAN_6G(7075, 225), 148 RTW89_DEF_CHAN_6G(7095, 229), 149 RTW89_DEF_CHAN_6G(7115, 233), 150}; 151 152static struct ieee80211_rate rtw89_bitrates[] = { 153 { .bitrate = 10, .hw_value = 0x00, }, 154 { .bitrate = 20, .hw_value = 0x01, }, 155 { .bitrate = 55, .hw_value = 0x02, }, 156 { .bitrate = 110, .hw_value = 0x03, }, 157 { .bitrate = 60, .hw_value = 0x04, }, 158 { .bitrate = 90, .hw_value = 0x05, }, 159 { .bitrate = 120, .hw_value = 0x06, }, 160 { .bitrate = 180, .hw_value = 0x07, }, 161 { .bitrate = 240, .hw_value = 0x08, }, 162 { .bitrate = 360, .hw_value = 0x09, }, 163 { .bitrate = 480, .hw_value = 0x0a, }, 164 { .bitrate = 540, .hw_value = 0x0b, }, 165}; 166 167static const struct ieee80211_iface_limit rtw89_iface_limits[] = { 168 { 169 .max = 1, 170 .types = BIT(NL80211_IFTYPE_STATION), 171 }, 172 { 173 .max = 1, 174 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 175 BIT(NL80211_IFTYPE_P2P_GO) | 176 BIT(NL80211_IFTYPE_AP), 177 }, 178}; 179 180static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = { 181 { 182 .max = 1, 183 .types = BIT(NL80211_IFTYPE_STATION), 184 }, 185 { 186 .max = 1, 187 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 188 BIT(NL80211_IFTYPE_P2P_GO), 189 }, 190}; 191 192static const struct ieee80211_iface_combination rtw89_iface_combs[] = { 193 { 194 .limits = rtw89_iface_limits, 195 .n_limits = ARRAY_SIZE(rtw89_iface_limits), 196 .max_interfaces = RTW89_MAX_INTERFACE_NUM, 197 .num_different_channels = 1, 198 }, 199 { 200 .limits = rtw89_iface_limits_mcc, 201 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc), 202 .max_interfaces = RTW89_MAX_INTERFACE_NUM, 203 .num_different_channels = 2, 204 }, 205}; 206 207static const u8 rtw89_ext_capa_sta[] = { 208 [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING, 209 [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, 210 [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, 211}; 212 213static const struct wiphy_iftype_ext_capab rtw89_iftypes_ext_capa[] = { 214 { 215 .iftype = NL80211_IFTYPE_STATION, 216 .extended_capabilities = rtw89_ext_capa_sta, 217 .extended_capabilities_mask = rtw89_ext_capa_sta, 218 .extended_capabilities_len = sizeof(rtw89_ext_capa_sta), 219 /* relevant only if EHT is supported */ 220 .eml_capabilities = 0, 221 .mld_capa_and_ops = 0, 222 }, 223}; 224 225#define RTW89_6GHZ_SPAN_HEAD 6145 226#define RTW89_6GHZ_SPAN_IDX(center_freq) \ 227 ((((int)(center_freq) - RTW89_6GHZ_SPAN_HEAD) / 5) / 2) 228 229#define RTW89_DECL_6GHZ_SPAN(center_freq, subband_l, subband_h) \ 230 [RTW89_6GHZ_SPAN_IDX(center_freq)] = { \ 231 .sar_subband_low = RTW89_SAR_6GHZ_ ## subband_l, \ 232 .sar_subband_high = RTW89_SAR_6GHZ_ ## subband_h, \ 233 .acpi_sar_subband_low = RTW89_ACPI_SAR_6GHZ_ ## subband_l, \ 234 .acpi_sar_subband_high = RTW89_ACPI_SAR_6GHZ_ ## subband_h, \ 235 .ant_gain_subband_low = RTW89_ANT_GAIN_6GHZ_ ## subband_l, \ 236 .ant_gain_subband_high = RTW89_ANT_GAIN_6GHZ_ ## subband_h, \ 237 } 238 239/* Since 6GHz subbands are not edge aligned, some cases span two subbands. 240 * In the following, we describe each of them with rtw89_6ghz_span. 241 */ 242static const struct rtw89_6ghz_span rtw89_overlapping_6ghz[] = { 243 RTW89_DECL_6GHZ_SPAN(6145, SUBBAND_5_L, SUBBAND_5_H), 244 RTW89_DECL_6GHZ_SPAN(6165, SUBBAND_5_L, SUBBAND_5_H), 245 RTW89_DECL_6GHZ_SPAN(6185, SUBBAND_5_L, SUBBAND_5_H), 246 RTW89_DECL_6GHZ_SPAN(6505, SUBBAND_6, SUBBAND_7_L), 247 RTW89_DECL_6GHZ_SPAN(6525, SUBBAND_6, SUBBAND_7_L), 248 RTW89_DECL_6GHZ_SPAN(6545, SUBBAND_6, SUBBAND_7_L), 249 RTW89_DECL_6GHZ_SPAN(6665, SUBBAND_7_L, SUBBAND_7_H), 250 RTW89_DECL_6GHZ_SPAN(6705, SUBBAND_7_L, SUBBAND_7_H), 251 RTW89_DECL_6GHZ_SPAN(6825, SUBBAND_7_H, SUBBAND_8), 252 RTW89_DECL_6GHZ_SPAN(6865, SUBBAND_7_H, SUBBAND_8), 253 RTW89_DECL_6GHZ_SPAN(6875, SUBBAND_7_H, SUBBAND_8), 254 RTW89_DECL_6GHZ_SPAN(6885, SUBBAND_7_H, SUBBAND_8), 255}; 256 257const struct rtw89_6ghz_span * 258rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq) 259{ 260 int idx; 261 262 if (center_freq >= RTW89_6GHZ_SPAN_HEAD) { 263 idx = RTW89_6GHZ_SPAN_IDX(center_freq); 264 /* To decrease size of rtw89_overlapping_6ghz[], 265 * RTW89_6GHZ_SPAN_IDX() truncates the leading NULLs 266 * to make first span as index 0 of the table. So, if center 267 * frequency is less than the first one, it will get netative. 268 */ 269 if (idx >= 0 && idx < ARRAY_SIZE(rtw89_overlapping_6ghz)) 270 return &rtw89_overlapping_6ghz[idx]; 271 } 272 273 return NULL; 274} 275 276bool rtw89_legacy_rate_to_bitrate(struct rtw89_dev *rtwdev, u8 legacy_rate, u16 *bitrate) 277{ 278 const struct ieee80211_rate *rate; 279 280 if (unlikely(legacy_rate >= ARRAY_SIZE(rtw89_bitrates))) { 281 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 282 "invalid legacy rate %d\n", legacy_rate); 283 return false; 284 } 285 286 rate = &rtw89_bitrates[legacy_rate]; 287 *bitrate = rate->bitrate; 288 289 return true; 290} 291 292static const struct ieee80211_supported_band rtw89_sband_2ghz = { 293 .band = NL80211_BAND_2GHZ, 294 .channels = rtw89_channels_2ghz, 295 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 296 .bitrates = rtw89_bitrates, 297 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 298 .ht_cap = {0}, 299 .vht_cap = {0}, 300}; 301 302static const struct ieee80211_supported_band rtw89_sband_5ghz = { 303 .band = NL80211_BAND_5GHZ, 304 .channels = rtw89_channels_5ghz, 305 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 306 307 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 308 .bitrates = rtw89_bitrates + 4, 309 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 310 .ht_cap = {0}, 311 .vht_cap = {0}, 312}; 313 314static const struct ieee80211_supported_band rtw89_sband_6ghz = { 315 .band = NL80211_BAND_6GHZ, 316 .channels = rtw89_channels_6ghz, 317 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 318 319 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 320 .bitrates = rtw89_bitrates + 4, 321 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 322}; 323 324static const struct rtw89_hw_rate_def { 325 enum rtw89_hw_rate ht; 326 enum rtw89_hw_rate vht[RTW89_NSS_NUM]; 327} rtw89_hw_rate[RTW89_CHIP_GEN_NUM] = { 328 [RTW89_CHIP_AX] = { 329 .ht = RTW89_HW_RATE_MCS0, 330 .vht = {RTW89_HW_RATE_VHT_NSS1_MCS0, 331 RTW89_HW_RATE_VHT_NSS2_MCS0, 332 RTW89_HW_RATE_VHT_NSS3_MCS0, 333 RTW89_HW_RATE_VHT_NSS4_MCS0}, 334 }, 335 [RTW89_CHIP_BE] = { 336 .ht = RTW89_HW_RATE_V1_MCS0, 337 .vht = {RTW89_HW_RATE_V1_VHT_NSS1_MCS0, 338 RTW89_HW_RATE_V1_VHT_NSS2_MCS0, 339 RTW89_HW_RATE_V1_VHT_NSS3_MCS0, 340 RTW89_HW_RATE_V1_VHT_NSS4_MCS0}, 341 }, 342}; 343 344static void __rtw89_traffic_stats_accu(struct rtw89_traffic_stats *stats, 345 struct sk_buff *skb, bool tx) 346{ 347 if (tx) { 348 stats->tx_cnt++; 349 stats->tx_unicast += skb->len; 350 } else { 351 stats->rx_cnt++; 352 stats->rx_unicast += skb->len; 353 } 354} 355 356static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 357 struct rtw89_vif *rtwvif, 358 struct sk_buff *skb, 359 bool accu_dev, bool tx) 360{ 361 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 362 363 if (!ieee80211_is_data(hdr->frame_control)) 364 return; 365 366 if (is_broadcast_ether_addr(hdr->addr1) || 367 is_multicast_ether_addr(hdr->addr1)) 368 return; 369 370 if (accu_dev) 371 __rtw89_traffic_stats_accu(&rtwdev->stats, skb, tx); 372 373 if (rtwvif) { 374 __rtw89_traffic_stats_accu(&rtwvif->stats, skb, tx); 375 __rtw89_traffic_stats_accu(&rtwvif->stats_ps, skb, tx); 376 } 377} 378 379void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 380{ 381 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 382 NL80211_CHAN_NO_HT); 383} 384 385void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 386 struct rtw89_chan *chan) 387{ 388 struct ieee80211_channel *channel = chandef->chan; 389 enum nl80211_chan_width width = chandef->width; 390 u32 primary_freq, center_freq; 391 u8 center_chan; 392 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 393 u32 offset; 394 u8 band; 395 396 center_chan = channel->hw_value; 397 primary_freq = channel->center_freq; 398 center_freq = chandef->center_freq1; 399 400 switch (width) { 401 case NL80211_CHAN_WIDTH_20_NOHT: 402 case NL80211_CHAN_WIDTH_20: 403 bandwidth = RTW89_CHANNEL_WIDTH_20; 404 break; 405 case NL80211_CHAN_WIDTH_40: 406 bandwidth = RTW89_CHANNEL_WIDTH_40; 407 if (primary_freq > center_freq) { 408 center_chan -= 2; 409 } else { 410 center_chan += 2; 411 } 412 break; 413 case NL80211_CHAN_WIDTH_80: 414 case NL80211_CHAN_WIDTH_160: 415 bandwidth = nl_to_rtw89_bandwidth(width); 416 if (primary_freq > center_freq) { 417 offset = (primary_freq - center_freq - 10) / 20; 418 center_chan -= 2 + offset * 4; 419 } else { 420 offset = (center_freq - primary_freq - 10) / 20; 421 center_chan += 2 + offset * 4; 422 } 423 break; 424 default: 425 center_chan = 0; 426 break; 427 } 428 429 switch (channel->band) { 430 default: 431 case NL80211_BAND_2GHZ: 432 band = RTW89_BAND_2G; 433 break; 434 case NL80211_BAND_5GHZ: 435 band = RTW89_BAND_5G; 436 break; 437 case NL80211_BAND_6GHZ: 438 band = RTW89_BAND_6G; 439 break; 440 } 441 442 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 443} 444 445static void __rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev, 446 const struct rtw89_chan *chan, 447 enum rtw89_phy_idx phy_idx) 448{ 449 const struct rtw89_chip_info *chip = rtwdev->chip; 450 bool entity_active; 451 452 entity_active = rtw89_get_entity_state(rtwdev, phy_idx); 453 if (!entity_active) 454 return; 455 456 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 457} 458 459void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 460{ 461 const struct rtw89_chan *chan; 462 463 chan = rtw89_mgnt_chan_get(rtwdev, 0); 464 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_0); 465 466 if (!rtwdev->support_mlo) 467 return; 468 469 chan = rtw89_mgnt_chan_get(rtwdev, 1); 470 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_1); 471} 472 473static void rtw89_chip_rfk_channel_for_pure_mon_vif(struct rtw89_dev *rtwdev, 474 enum rtw89_phy_idx phy_idx) 475{ 476 struct rtw89_vif *rtwvif = rtwdev->pure_monitor_mode_vif; 477 struct rtw89_vif_link *rtwvif_link; 478 479 if (!rtwvif) 480 return; 481 482 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, phy_idx); 483 if (!rtwvif_link) 484 return; 485 486 rtw89_chip_rfk_channel(rtwdev, rtwvif_link); 487} 488 489static void __rtw89_set_channel(struct rtw89_dev *rtwdev, 490 const struct rtw89_chan *chan, 491 enum rtw89_mac_idx mac_idx, 492 enum rtw89_phy_idx phy_idx) 493{ 494 const struct rtw89_chip_info *chip = rtwdev->chip; 495 const struct rtw89_chan_rcd *chan_rcd; 496 struct rtw89_channel_help_params bak; 497 bool entity_active; 498 499 entity_active = rtw89_get_entity_state(rtwdev, phy_idx); 500 501 chan_rcd = rtw89_chan_rcd_get_by_chan(chan); 502 503 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx); 504 505 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx); 506 507 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 508 509 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx); 510 511 if (!entity_active || chan_rcd->band_changed) { 512 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type); 513 rtw89_chip_rfk_band_changed(rtwdev, phy_idx, chan); 514 } 515 516 rtw89_set_entity_state(rtwdev, phy_idx, true); 517 518 rtw89_chip_rfk_channel_for_pure_mon_vif(rtwdev, phy_idx); 519} 520 521int rtw89_set_channel(struct rtw89_dev *rtwdev) 522{ 523 const struct rtw89_chan *chan; 524 enum rtw89_entity_mode mode; 525 526 mode = rtw89_entity_recalc(rtwdev); 527 if (mode < 0 || mode >= NUM_OF_RTW89_ENTITY_MODE) { 528 WARN(1, "Invalid ent mode: %d\n", mode); 529 return -EINVAL; 530 } 531 532 chan = rtw89_mgnt_chan_get(rtwdev, 0); 533 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_0, RTW89_PHY_0); 534 535 if (!rtwdev->support_mlo) 536 return 0; 537 538 chan = rtw89_mgnt_chan_get(rtwdev, 1); 539 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_1, RTW89_PHY_1); 540 541 return 0; 542} 543 544static enum rtw89_core_tx_type 545rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 546 struct sk_buff *skb) 547{ 548 struct ieee80211_hdr *hdr = (void *)skb->data; 549 __le16 fc = hdr->frame_control; 550 551 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) 552 return RTW89_CORE_TX_TYPE_MGMT; 553 554 return RTW89_CORE_TX_TYPE_DATA; 555} 556 557static void 558rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 559 struct rtw89_core_tx_request *tx_req, 560 enum btc_pkt_type pkt_type) 561{ 562 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 563 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 564 struct ieee80211_link_sta *link_sta; 565 struct sk_buff *skb = tx_req->skb; 566 struct rtw89_sta *rtwsta; 567 u8 ampdu_num; 568 u8 tid; 569 570 if (pkt_type == PACKET_EAPOL) { 571 desc_info->bk = true; 572 return; 573 } 574 575 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 576 return; 577 578 if (!rtwsta_link) { 579 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 580 return; 581 } 582 583 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 584 rtwsta = rtwsta_link->rtwsta; 585 586 rcu_read_lock(); 587 588 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 589 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 590 rtwsta->ampdu_params[tid].agg_num : 591 4 << link_sta->ht_cap.ampdu_factor) - 1); 592 593 desc_info->agg_en = true; 594 desc_info->ampdu_density = link_sta->ht_cap.ampdu_density; 595 desc_info->ampdu_num = ampdu_num; 596 597 rcu_read_unlock(); 598} 599 600static void 601rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 602 struct rtw89_core_tx_request *tx_req) 603{ 604 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 605 const struct rtw89_chip_info *chip = rtwdev->chip; 606 const struct rtw89_sec_cam_entry *sec_cam; 607 struct ieee80211_tx_info *info; 608 struct ieee80211_key_conf *key; 609 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 610 struct sk_buff *skb = tx_req->skb; 611 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 612 u8 sec_cam_idx; 613 u64 pn64; 614 615 info = IEEE80211_SKB_CB(skb); 616 key = info->control.hw_key; 617 sec_cam_idx = key->hw_key_idx; 618 sec_cam = cam_info->sec_entries[sec_cam_idx]; 619 if (!sec_cam) { 620 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 621 return; 622 } 623 624 switch (key->cipher) { 625 case WLAN_CIPHER_SUITE_WEP40: 626 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 627 break; 628 case WLAN_CIPHER_SUITE_WEP104: 629 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 630 break; 631 case WLAN_CIPHER_SUITE_TKIP: 632 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 633 break; 634 case WLAN_CIPHER_SUITE_CCMP: 635 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 636 break; 637 case WLAN_CIPHER_SUITE_CCMP_256: 638 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 639 break; 640 case WLAN_CIPHER_SUITE_GCMP: 641 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 642 break; 643 case WLAN_CIPHER_SUITE_GCMP_256: 644 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 645 break; 646 default: 647 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 648 return; 649 } 650 651 desc_info->sec_en = true; 652 desc_info->sec_keyid = key->keyidx; 653 desc_info->sec_type = sec_type; 654 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 655 656 if (!chip->hw_sec_hdr) 657 return; 658 659 pn64 = atomic64_inc_return(&key->tx_pn); 660 desc_info->sec_seq[0] = pn64; 661 desc_info->sec_seq[1] = pn64 >> 8; 662 desc_info->sec_seq[2] = pn64 >> 16; 663 desc_info->sec_seq[3] = pn64 >> 24; 664 desc_info->sec_seq[4] = pn64 >> 32; 665 desc_info->sec_seq[5] = pn64 >> 40; 666 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 667} 668 669static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 670 struct rtw89_core_tx_request *tx_req, 671 const struct rtw89_chan *chan) 672{ 673 struct sk_buff *skb = tx_req->skb; 674 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 675 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 676 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 677 struct ieee80211_vif *vif = tx_info->control.vif; 678 struct ieee80211_bss_conf *bss_conf; 679 u16 lowest_rate; 680 u16 rate; 681 682 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || 683 (vif && vif->p2p)) 684 lowest_rate = RTW89_HW_RATE_OFDM6; 685 else if (chan->band_type == RTW89_BAND_2G) 686 lowest_rate = RTW89_HW_RATE_CCK1; 687 else 688 lowest_rate = RTW89_HW_RATE_OFDM6; 689 690 if (!rtwvif_link) 691 return lowest_rate; 692 693 rcu_read_lock(); 694 695 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 696 if (!bss_conf->basic_rates || !rtwsta_link) { 697 rate = lowest_rate; 698 goto out; 699 } 700 701 rate = __ffs(bss_conf->basic_rates) + lowest_rate; 702 703out: 704 rcu_read_unlock(); 705 706 return rate; 707} 708 709static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 710 struct rtw89_core_tx_request *tx_req) 711{ 712 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 713 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 714 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 715 716 if (desc_info->mlo && !desc_info->sw_mld) { 717 if (rtwsta_link) 718 return rtw89_sta_get_main_macid(rtwsta_link->rtwsta); 719 else 720 return rtw89_vif_get_main_macid(rtwvif_link->rtwvif); 721 } 722 723 if (!rtwsta_link) 724 return rtwvif_link->mac_id; 725 726 return rtwsta_link->mac_id; 727} 728 729static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 730 struct rtw89_tx_desc_info *desc_info, 731 struct sk_buff *skb) 732{ 733 struct ieee80211_hdr *hdr = (void *)skb->data; 734 __le16 fc = hdr->frame_control; 735 736 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 737 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 738} 739 740u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) 741{ 742 switch (qsel) { 743 default: 744 rtw89_warn(rtwdev, "Cannot map qsel to dma: %d\n", qsel); 745 fallthrough; 746 case RTW89_TX_QSEL_BE_0: 747 case RTW89_TX_QSEL_BE_1: 748 case RTW89_TX_QSEL_BE_2: 749 case RTW89_TX_QSEL_BE_3: 750 return RTW89_TXCH_ACH0; 751 case RTW89_TX_QSEL_BK_0: 752 case RTW89_TX_QSEL_BK_1: 753 case RTW89_TX_QSEL_BK_2: 754 case RTW89_TX_QSEL_BK_3: 755 return RTW89_TXCH_ACH1; 756 case RTW89_TX_QSEL_VI_0: 757 case RTW89_TX_QSEL_VI_1: 758 case RTW89_TX_QSEL_VI_2: 759 case RTW89_TX_QSEL_VI_3: 760 return RTW89_TXCH_ACH2; 761 case RTW89_TX_QSEL_VO_0: 762 case RTW89_TX_QSEL_VO_1: 763 case RTW89_TX_QSEL_VO_2: 764 case RTW89_TX_QSEL_VO_3: 765 return RTW89_TXCH_ACH3; 766 case RTW89_TX_QSEL_B0_MGMT: 767 return RTW89_TXCH_CH8; 768 case RTW89_TX_QSEL_B0_HI: 769 return RTW89_TXCH_CH9; 770 case RTW89_TX_QSEL_B1_MGMT: 771 return RTW89_TXCH_CH10; 772 case RTW89_TX_QSEL_B1_HI: 773 return RTW89_TXCH_CH11; 774 } 775} 776EXPORT_SYMBOL(rtw89_core_get_ch_dma); 777 778u8 rtw89_core_get_ch_dma_v1(struct rtw89_dev *rtwdev, u8 qsel) 779{ 780 switch (qsel) { 781 default: 782 rtw89_warn(rtwdev, "Cannot map qsel to dma v1: %d\n", qsel); 783 fallthrough; 784 case RTW89_TX_QSEL_BE_0: 785 case RTW89_TX_QSEL_BK_0: 786 return RTW89_TXCH_ACH0; 787 case RTW89_TX_QSEL_VI_0: 788 case RTW89_TX_QSEL_VO_0: 789 return RTW89_TXCH_ACH2; 790 case RTW89_TX_QSEL_B0_MGMT: 791 case RTW89_TX_QSEL_B0_HI: 792 return RTW89_TXCH_CH8; 793 case RTW89_TX_QSEL_B1_MGMT: 794 case RTW89_TX_QSEL_B1_HI: 795 return RTW89_TXCH_CH10; 796 } 797} 798EXPORT_SYMBOL(rtw89_core_get_ch_dma_v1); 799 800u8 rtw89_core_get_ch_dma_v2(struct rtw89_dev *rtwdev, u8 qsel) 801{ 802 switch (qsel) { 803 default: 804 rtw89_warn(rtwdev, "Cannot map qsel to dma v2: %d\n", qsel); 805 fallthrough; 806 case RTW89_TX_QSEL_BE_0: 807 case RTW89_TX_QSEL_VO_0: 808 return RTW89_TXCH_ACH0; 809 case RTW89_TX_QSEL_BK_0: 810 case RTW89_TX_QSEL_VI_0: 811 return RTW89_TXCH_ACH2; 812 case RTW89_TX_QSEL_B0_MGMT: 813 case RTW89_TX_QSEL_B0_HI: 814 return RTW89_TXCH_CH8; 815 } 816} 817EXPORT_SYMBOL(rtw89_core_get_ch_dma_v2); 818 819static void 820rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 821 struct rtw89_core_tx_request *tx_req) 822{ 823 const struct rtw89_chip_info *chip = rtwdev->chip; 824 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 825 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 826 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 827 rtwvif_link->chanctx_idx); 828 struct sk_buff *skb = tx_req->skb; 829 u8 qsel, ch_dma; 830 831 qsel = rtw89_core_get_qsel_mgmt(rtwdev, tx_req); 832 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel); 833 834 desc_info->qsel = qsel; 835 desc_info->ch_dma = ch_dma; 836 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0; 837 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 838 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 839 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 840 841 /* fixed data rate for mgmt frames */ 842 desc_info->en_wd_info = true; 843 desc_info->use_rate = true; 844 desc_info->dis_data_fb = true; 845 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan); 846 847 if (chip->hw_mgmt_tx_encrypt && IEEE80211_SKB_CB(skb)->control.hw_key) { 848 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 849 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 850 } 851 852 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 853 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 854 desc_info->data_rate, chan->channel, chan->band_type, 855 chan->band_width); 856} 857 858static void 859rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 860 struct rtw89_core_tx_request *tx_req) 861{ 862 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 863 864 desc_info->is_bmc = false; 865 desc_info->wd_page = false; 866 desc_info->ch_dma = RTW89_DMA_H2C; 867} 868 869static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc, 870 const struct rtw89_chan *chan) 871{ 872 static const u8 rtw89_bandwidth_to_om[] = { 873 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 874 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 875 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 876 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 877 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 878 }; 879 const struct rtw89_chip_info *chip = rtwdev->chip; 880 struct rtw89_hal *hal = &rtwdev->hal; 881 u8 om_bandwidth; 882 883 if (!chip->dis_2g_40m_ul_ofdma || 884 chan->band_type != RTW89_BAND_2G || 885 chan->band_width != RTW89_CHANNEL_WIDTH_40) 886 return; 887 888 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 889 rtw89_bandwidth_to_om[chan->band_width] : 0; 890 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 891 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 892 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 893 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 894 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 895 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 896 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 897 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 898 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 899} 900 901static bool 902__rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 903 struct rtw89_core_tx_request *tx_req, 904 enum btc_pkt_type pkt_type) 905{ 906 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 907 struct sk_buff *skb = tx_req->skb; 908 struct ieee80211_hdr *hdr = (void *)skb->data; 909 struct ieee80211_link_sta *link_sta; 910 __le16 fc = hdr->frame_control; 911 912 /* AP IOT issue with EAPoL, ARP and DHCP */ 913 if (pkt_type < PACKET_MAX) 914 return false; 915 916 if (!rtwsta_link) 917 return false; 918 919 rcu_read_lock(); 920 921 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 922 if (!link_sta->he_cap.has_he) { 923 rcu_read_unlock(); 924 return false; 925 } 926 927 rcu_read_unlock(); 928 929 if (!ieee80211_is_data_qos(fc)) 930 return false; 931 932 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 933 return false; 934 935 if (rtwsta_link && rtwsta_link->ra_report.might_fallback_legacy) 936 return false; 937 938 return true; 939} 940 941static void 942__rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 943 struct rtw89_core_tx_request *tx_req) 944{ 945 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 946 struct sk_buff *skb = tx_req->skb; 947 struct ieee80211_hdr *hdr = (void *)skb->data; 948 __le16 fc = hdr->frame_control; 949 void *data; 950 __le32 *htc; 951 u8 *qc; 952 int hdr_len; 953 954 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 955 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 956 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 957 958 hdr = data; 959 htc = data + hdr_len; 960 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 961 *htc = rtwsta_link->htc_template ? rtwsta_link->htc_template : 962 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 963 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 964 965 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 966 qc[0] |= IEEE80211_QOS_CTL_EOSP; 967} 968 969static void 970rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 971 struct rtw89_core_tx_request *tx_req, 972 enum btc_pkt_type pkt_type) 973{ 974 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 975 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 976 977 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 978 goto desc_bk; 979 980 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 981 982 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 983 desc_info->a_ctrl_bsr = true; 984 985desc_bk: 986 if (!rtwvif_link || rtwvif_link->last_a_ctrl == desc_info->a_ctrl_bsr) 987 return; 988 989 rtwvif_link->last_a_ctrl = desc_info->a_ctrl_bsr; 990 desc_info->bk = true; 991} 992 993static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev, 994 struct rtw89_core_tx_request *tx_req) 995{ 996 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 997 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 998 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 999 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern; 1000 enum rtw89_chanctx_idx idx = rtwvif_link->chanctx_idx; 1001 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx); 1002 struct ieee80211_link_sta *link_sta; 1003 u16 lowest_rate; 1004 u16 rate; 1005 1006 if (rate_pattern->enable) 1007 return rate_pattern->rate; 1008 1009 if (vif->p2p) 1010 lowest_rate = RTW89_HW_RATE_OFDM6; 1011 else if (chan->band_type == RTW89_BAND_2G) 1012 lowest_rate = RTW89_HW_RATE_CCK1; 1013 else 1014 lowest_rate = RTW89_HW_RATE_OFDM6; 1015 1016 if (!rtwsta_link) 1017 return lowest_rate; 1018 1019 rcu_read_lock(); 1020 1021 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 1022 if (!link_sta->supp_rates[chan->band_type]) { 1023 rate = lowest_rate; 1024 goto out; 1025 } 1026 1027 rate = __ffs(link_sta->supp_rates[chan->band_type]) + lowest_rate; 1028 1029out: 1030 rcu_read_unlock(); 1031 1032 return rate; 1033} 1034 1035static void 1036rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 1037 struct rtw89_core_tx_request *tx_req) 1038{ 1039 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 1040 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 1041 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1042 struct sk_buff *skb = tx_req->skb; 1043 u8 tid, tid_indicate; 1044 u8 qsel, ch_dma; 1045 1046 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 1047 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 1048 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 1049 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel); 1050 1051 desc_info->ch_dma = ch_dma; 1052 desc_info->tid_indicate = tid_indicate; 1053 desc_info->qsel = qsel; 1054 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 1055 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0; 1056 desc_info->er_cap = rtwsta_link ? rtwsta_link->er_cap : false; 1057 desc_info->stbc = rtwsta_link ? rtwsta_link->ra.stbc_cap : false; 1058 desc_info->ldpc = rtwsta_link ? rtwsta_link->ra.ldpc_cap : false; 1059 1060 /* enable wd_info for AMPDU */ 1061 desc_info->en_wd_info = true; 1062 1063 if (IEEE80211_SKB_CB(skb)->control.hw_key) 1064 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 1065 1066 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req); 1067} 1068 1069static enum btc_pkt_type 1070rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 1071 struct rtw89_core_tx_request *tx_req) 1072{ 1073 struct wiphy *wiphy = rtwdev->hw->wiphy; 1074 struct sk_buff *skb = tx_req->skb; 1075 struct udphdr *udphdr; 1076 1077 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 1078 wiphy_work_queue(wiphy, &rtwdev->btc.eapol_notify_work); 1079 return PACKET_EAPOL; 1080 } 1081 1082 if (skb->protocol == htons(ETH_P_ARP)) { 1083 wiphy_work_queue(wiphy, &rtwdev->btc.arp_notify_work); 1084 return PACKET_ARP; 1085 } 1086 1087 if (skb->protocol == htons(ETH_P_IP) && 1088 ip_hdr(skb)->protocol == IPPROTO_UDP) { 1089 udphdr = udp_hdr(skb); 1090 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 1091 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 1092 skb->len > 282) { 1093 wiphy_work_queue(wiphy, &rtwdev->btc.dhcp_notify_work); 1094 return PACKET_DHCP; 1095 } 1096 } 1097 1098 if (skb->protocol == htons(ETH_P_IP) && 1099 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 1100 wiphy_work_queue(wiphy, &rtwdev->btc.icmp_notify_work); 1101 return PACKET_ICMP; 1102 } 1103 1104 return PACKET_MAX; 1105} 1106 1107static void 1108rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 1109 struct rtw89_core_tx_request *tx_req) 1110{ 1111 const struct rtw89_chip_info *chip = rtwdev->chip; 1112 1113 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 1114 return; 1115 1116 switch (chip->chip_id) { 1117 case RTL8852BT: 1118 if (test_bit(RTW89_FLAG_LEISURE_PS, rtwdev->flags)) 1119 goto notify; 1120 break; 1121 case RTL8852C: 1122 if (test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 1123 goto notify; 1124 break; 1125 default: 1126 if (test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags) && 1127 tx_req->tx_type == RTW89_CORE_TX_TYPE_MGMT) 1128 goto notify; 1129 break; 1130 } 1131 1132 return; 1133 1134notify: 1135 rtw89_mac_notify_wake(rtwdev); 1136} 1137 1138static void rtw89_core_tx_update_injection(struct rtw89_dev *rtwdev, 1139 struct rtw89_core_tx_request *tx_req, 1140 struct ieee80211_tx_info *info) 1141{ 1142 const struct rtw89_hw_rate_def *hw_rate = &rtw89_hw_rate[rtwdev->chip->chip_gen]; 1143 enum mac80211_rate_control_flags flags = info->control.rates[0].flags; 1144 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1145 const struct rtw89_chan *chan; 1146 u8 idx = info->control.rates[0].idx; 1147 u8 nss, mcs; 1148 1149 desc_info->use_rate = true; 1150 desc_info->dis_data_fb = true; 1151 1152 if (flags & IEEE80211_TX_RC_160_MHZ_WIDTH) 1153 desc_info->data_bw = 3; 1154 else if (flags & IEEE80211_TX_RC_80_MHZ_WIDTH) 1155 desc_info->data_bw = 2; 1156 else if (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 1157 desc_info->data_bw = 1; 1158 1159 if (flags & IEEE80211_TX_RC_SHORT_GI) 1160 desc_info->gi_ltf = 1; 1161 1162 if (flags & IEEE80211_TX_RC_VHT_MCS) { 1163 nss = umin(idx >> 4, ARRAY_SIZE(hw_rate->vht) - 1); 1164 mcs = idx & 0xf; 1165 desc_info->data_rate = hw_rate->vht[nss] + mcs; 1166 } else if (flags & IEEE80211_TX_RC_MCS) { 1167 desc_info->data_rate = hw_rate->ht + idx; 1168 } else { 1169 chan = rtw89_chan_get(rtwdev, tx_req->rtwvif_link->chanctx_idx); 1170 1171 desc_info->data_rate = idx + (chan->band_type == RTW89_BAND_2G ? 1172 RTW89_HW_RATE_CCK1 : RTW89_HW_RATE_OFDM6); 1173 } 1174} 1175 1176static void 1177rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 1178 struct rtw89_core_tx_request *tx_req) 1179{ 1180 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1181 struct sk_buff *skb = tx_req->skb; 1182 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1183 struct ieee80211_hdr *hdr = (void *)skb->data; 1184 struct rtw89_addr_cam_entry *addr_cam; 1185 enum btc_pkt_type pkt_type; 1186 bool upd_wlan_hdr = false; 1187 bool is_bmc; 1188 u16 seq; 1189 1190 desc_info->pkt_size = skb->len; 1191 1192 if (unlikely(tx_req->tx_type == RTW89_CORE_TX_TYPE_FWCMD)) { 1193 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 1194 return; 1195 } 1196 1197 tx_req->tx_type = rtw89_core_get_tx_type(rtwdev, skb); 1198 1199 if (tx_req->sta) 1200 desc_info->mlo = tx_req->sta->mlo; 1201 else if (tx_req->vif) 1202 desc_info->mlo = ieee80211_vif_is_mld(tx_req->vif); 1203 1204 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 1205 addr_cam = rtw89_get_addr_cam_of(tx_req->rtwvif_link, 1206 tx_req->rtwsta_link); 1207 if (addr_cam->valid && desc_info->mlo) 1208 upd_wlan_hdr = true; 1209 1210 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS || tx_req->with_wait) 1211 rtw89_tx_rpt_init(rtwdev, tx_req); 1212 1213 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 1214 is_multicast_ether_addr(hdr->addr1)); 1215 1216 desc_info->seq = seq; 1217 desc_info->is_bmc = is_bmc; 1218 desc_info->wd_page = true; 1219 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 1220 desc_info->upd_wlan_hdr = upd_wlan_hdr; 1221 1222 switch (tx_req->tx_type) { 1223 case RTW89_CORE_TX_TYPE_MGMT: 1224 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 1225 break; 1226 case RTW89_CORE_TX_TYPE_DATA: 1227 rtw89_core_tx_update_data_info(rtwdev, tx_req); 1228 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 1229 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 1230 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 1231 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 1232 break; 1233 default: 1234 break; 1235 } 1236 1237 if (unlikely(info->flags & IEEE80211_TX_CTL_INJECTED)) 1238 rtw89_core_tx_update_injection(rtwdev, tx_req, info); 1239} 1240 1241static void rtw89_tx_wait_work(struct wiphy *wiphy, struct wiphy_work *work) 1242{ 1243 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 1244 tx_wait_work.work); 1245 1246 rtw89_tx_wait_list_clear(rtwdev); 1247} 1248 1249void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 1250{ 1251 u8 ch_dma; 1252 1253 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel); 1254 1255 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 1256} 1257 1258int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1259 struct rtw89_tx_wait_info *wait, int qsel, 1260 unsigned int timeout) 1261{ 1262 unsigned long time_left; 1263 int ret = 0; 1264 1265 lockdep_assert_wiphy(rtwdev->hw->wiphy); 1266 1267 rtw89_core_tx_kick_off(rtwdev, qsel); 1268 time_left = wait_for_completion_timeout(&wait->completion, 1269 msecs_to_jiffies(timeout)); 1270 1271 if (time_left == 0) { 1272 ret = -ETIMEDOUT; 1273 list_add_tail(&wait->list, &rtwdev->tx_waits); 1274 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->tx_wait_work, 1275 RTW89_TX_WAIT_WORK_TIMEOUT); 1276 } else { 1277 if (!wait->tx_done) 1278 ret = -EAGAIN; 1279 rtw89_tx_wait_release(wait); 1280 } 1281 1282 return ret; 1283} 1284 1285int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 1286 struct sk_buff *skb, bool fwdl) 1287{ 1288 struct rtw89_core_tx_request tx_req = {0}; 1289 u32 cnt; 1290 int ret; 1291 1292 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 1293 rtw89_debug(rtwdev, RTW89_DBG_FW, 1294 "ignore h2c due to power is off with firmware state=%d\n", 1295 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 1296 dev_kfree_skb(skb); 1297 return 0; 1298 } 1299 1300 tx_req.skb = skb; 1301 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 1302 if (fwdl) 1303 tx_req.desc_info.fw_dl = true; 1304 1305 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1306 1307 if (!fwdl) 1308 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 1309 1310 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 1311 if (cnt == 0) { 1312 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 1313 return -ENOSPC; 1314 } 1315 1316 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1317 if (ret) { 1318 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1319 return ret; 1320 } 1321 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 1322 1323 return 0; 1324} 1325 1326static int rtw89_core_tx_write_link(struct rtw89_dev *rtwdev, 1327 struct rtw89_vif_link *rtwvif_link, 1328 struct rtw89_sta_link *rtwsta_link, 1329 struct sk_buff *skb, int *qsel, bool sw_mld, 1330 struct rtw89_tx_wait_info *wait) 1331{ 1332 struct ieee80211_sta *sta = rtwsta_link_to_sta_safe(rtwsta_link); 1333 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 1334 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 1335 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 1336 struct rtw89_core_tx_request tx_req = {}; 1337 int ret; 1338 1339 tx_req.skb = skb; 1340 tx_req.vif = vif; 1341 tx_req.sta = sta; 1342 tx_req.rtwvif_link = rtwvif_link; 1343 tx_req.rtwsta_link = rtwsta_link; 1344 tx_req.desc_info.sw_mld = sw_mld; 1345 tx_req.with_wait = !!wait; 1346 1347 rtw89_traffic_stats_accu(rtwdev, rtwvif, skb, true, true); 1348 rtw89_wow_parse_akm(rtwdev, skb); 1349 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1350 rtw89_core_tx_wake(rtwdev, &tx_req); 1351 1352 rcu_assign_pointer(skb_data->wait, wait); 1353 1354 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1355 if (ret) { 1356 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1357 return ret; 1358 } 1359 1360 if (qsel) 1361 *qsel = tx_req.desc_info.qsel; 1362 1363 return 0; 1364} 1365 1366int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1367 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 1368{ 1369 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 1370 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 1371 struct rtw89_sta_link *rtwsta_link = NULL; 1372 struct rtw89_vif_link *rtwvif_link; 1373 1374 if (rtwsta) { 1375 rtwsta_link = rtw89_get_designated_link(rtwsta); 1376 if (unlikely(!rtwsta_link)) { 1377 rtw89_err(rtwdev, "tx: find no sta designated link\n"); 1378 return -ENOLINK; 1379 } 1380 1381 rtwvif_link = rtwsta_link->rtwvif_link; 1382 } else { 1383 rtwvif_link = rtw89_get_designated_link(rtwvif); 1384 if (unlikely(!rtwvif_link)) { 1385 rtw89_err(rtwdev, "tx: find no vif designated link\n"); 1386 return -ENOLINK; 1387 } 1388 } 1389 1390 return rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, qsel, false, 1391 NULL); 1392} 1393 1394static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 1395{ 1396 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 1397 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1398 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1399 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1400 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1401 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 1402 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 1403 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 1404 1405 return cpu_to_le32(dword); 1406} 1407 1408static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 1409{ 1410 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1411 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1412 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1413 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1414 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1415 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 1416 1417 return cpu_to_le32(dword); 1418} 1419 1420static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 1421{ 1422 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1423 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1424 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 1425 1426 return cpu_to_le32(dword); 1427} 1428 1429static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 1430{ 1431 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 1432 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 1433 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 1434 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 1435 1436 return cpu_to_le32(dword); 1437} 1438 1439static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 1440{ 1441 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 1442 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 1443 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 1444 1445 return cpu_to_le32(dword); 1446} 1447 1448static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 1449{ 1450 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1451 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1452 1453 return cpu_to_le32(dword); 1454} 1455 1456static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 1457{ 1458 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1459 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1460 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1461 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1462 1463 return cpu_to_le32(dword); 1464} 1465 1466static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 1467{ 1468 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 1469 FIELD_PREP(RTW89_TXWD_BODY7_DATA_BW, desc_info->data_bw) | 1470 FIELD_PREP(RTW89_TXWD_BODY7_GI_LTF, desc_info->gi_ltf) | 1471 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 1472 1473 return cpu_to_le32(dword); 1474} 1475 1476static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 1477{ 1478 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 1479 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW, desc_info->data_bw) | 1480 FIELD_PREP(RTW89_TXWD_INFO0_GI_LTF, desc_info->gi_ltf) | 1481 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1482 FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1483 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1484 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1485 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1486 1487 return cpu_to_le32(dword); 1488} 1489 1490static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1491{ 1492 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1493 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1494 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1495 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) | 1496 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) | 1497 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0); 1498 1499 return cpu_to_le32(dword); 1500} 1501 1502static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1503{ 1504 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1505 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1506 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1507 desc_info->data_retry_lowest_rate) | 1508 FIELD_PREP(RTW89_TXWD_INFO1_DATA_TXCNT_LMT_SEL, 1509 desc_info->tx_cnt_lmt_en) | 1510 FIELD_PREP(RTW89_TXWD_INFO1_DATA_TXCNT_LMT, desc_info->tx_cnt_lmt); 1511 1512 return cpu_to_le32(dword); 1513} 1514 1515static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1516{ 1517 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1518 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1519 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1520 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1521 1522 return cpu_to_le32(dword); 1523} 1524 1525static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1526{ 1527 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1528 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1529 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1530 1531 return cpu_to_le32(dword); 1532} 1533 1534static __le32 rtw89_build_txwd_info3(struct rtw89_tx_desc_info *desc_info) 1535{ 1536 u32 dword = FIELD_PREP(RTW89_TXWD_INFO3_SPE_RPT, desc_info->report); 1537 1538 return cpu_to_le32(dword); 1539} 1540 1541static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1542{ 1543 bool rts_en = !desc_info->is_bmc; 1544 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) | 1545 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1) | 1546 FIELD_PREP(RTW89_TXWD_INFO4_SW_DEFINE, desc_info->sn); 1547 1548 return cpu_to_le32(dword); 1549} 1550 1551void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1552 struct rtw89_tx_desc_info *desc_info, 1553 void *txdesc) 1554{ 1555 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1556 struct rtw89_txwd_info *txwd_info; 1557 1558 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1559 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1560 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1561 1562 if (!desc_info->en_wd_info) 1563 return; 1564 1565 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1566 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1567 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1568 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1569 txwd_info->dword3 = rtw89_build_txwd_info3(desc_info); 1570 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1571 1572} 1573EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1574 1575void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1576 struct rtw89_tx_desc_info *desc_info, 1577 void *txdesc) 1578{ 1579 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1580 struct rtw89_txwd_info *txwd_info; 1581 1582 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1583 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1584 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1585 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1586 if (desc_info->sec_en) { 1587 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1588 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1589 } 1590 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1591 1592 if (!desc_info->en_wd_info) 1593 return; 1594 1595 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1596 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1597 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1598 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1599 txwd_info->dword3 = rtw89_build_txwd_info3(desc_info); 1600 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1601} 1602EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1603 1604static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info) 1605{ 1606 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1607 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) | 1608 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) | 1609 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1610 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page); 1611 1612 return cpu_to_le32(dword); 1613} 1614 1615static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info) 1616{ 1617 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1618 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1619 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type); 1620 1621 return cpu_to_le32(dword); 1622} 1623 1624static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info) 1625{ 1626 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) | 1627 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) | 1628 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) | 1629 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) | 1630 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) | 1631 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id); 1632 1633 return cpu_to_le32(dword); 1634} 1635 1636static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info) 1637{ 1638 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq) | 1639 FIELD_PREP(BE_TXD_BODY3_MLO_FLAG, desc_info->mlo) | 1640 FIELD_PREP(BE_TXD_BODY3_IS_MLD_SW_EN, desc_info->sw_mld); 1641 1642 return cpu_to_le32(dword); 1643} 1644 1645static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info) 1646{ 1647 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1648 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1649 1650 return cpu_to_le32(dword); 1651} 1652 1653static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info) 1654{ 1655 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1656 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1657 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1658 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1659 1660 return cpu_to_le32(dword); 1661} 1662 1663static __le32 rtw89_build_txwd_body6_v2(struct rtw89_tx_desc_info *desc_info) 1664{ 1665 u32 dword = FIELD_PREP(BE_TXD_BODY6_UPD_WLAN_HDR, desc_info->upd_wlan_hdr); 1666 1667 return cpu_to_le32(dword); 1668} 1669 1670static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info) 1671{ 1672 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) | 1673 FIELD_PREP(BE_TXD_BODY7_DATA_BW, desc_info->data_bw) | 1674 FIELD_PREP(BE_TXD_BODY7_GI_LTF, desc_info->gi_ltf) | 1675 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) | 1676 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) | 1677 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate); 1678 1679 return cpu_to_le32(dword); 1680} 1681 1682static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info) 1683{ 1684 u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) | 1685 FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) | 1686 FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1687 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port) | 1688 FIELD_PREP(BE_TXD_INFO0_DATA_TXCNT_LMT_SEL, 1689 desc_info->tx_cnt_lmt_en) | 1690 FIELD_PREP(BE_TXD_INFO0_DATA_TXCNT_LMT, desc_info->tx_cnt_lmt); 1691 1692 return cpu_to_le32(dword); 1693} 1694 1695static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info) 1696{ 1697 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) | 1698 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1699 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE, 1700 desc_info->data_retry_lowest_rate) | 1701 FIELD_PREP(BE_TXD_INFO1_SW_DEFINE, desc_info->sn); 1702 1703 return cpu_to_le32(dword); 1704} 1705 1706static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info) 1707{ 1708 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1709 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1710 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx) | 1711 FIELD_PREP(BE_TXD_INFO2_SPE_RPT_V1, desc_info->report); 1712 1713 return cpu_to_le32(dword); 1714} 1715 1716static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info) 1717{ 1718 bool rts_en = !desc_info->is_bmc; 1719 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) | 1720 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1); 1721 1722 return cpu_to_le32(dword); 1723} 1724 1725void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 1726 struct rtw89_tx_desc_info *desc_info, 1727 void *txdesc) 1728{ 1729 struct rtw89_txwd_body_v2 *txwd_body = txdesc; 1730 struct rtw89_txwd_info_v2 *txwd_info; 1731 1732 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info); 1733 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info); 1734 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info); 1735 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info); 1736 if (desc_info->sec_en) { 1737 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info); 1738 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info); 1739 } 1740 txwd_body->dword6 = rtw89_build_txwd_body6_v2(desc_info); 1741 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info); 1742 1743 if (!desc_info->en_wd_info) 1744 return; 1745 1746 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1); 1747 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info); 1748 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info); 1749 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info); 1750 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info); 1751} 1752EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2); 1753 1754static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1755{ 1756 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1757 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1758 RTW89_CORE_RX_TYPE_FWDL : 1759 RTW89_CORE_RX_TYPE_H2C); 1760 1761 return cpu_to_le32(dword); 1762} 1763 1764void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1765 struct rtw89_tx_desc_info *desc_info, 1766 void *txdesc) 1767{ 1768 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1769 1770 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1771} 1772EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1773 1774static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info) 1775{ 1776 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1777 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1778 RTW89_CORE_RX_TYPE_FWDL : 1779 RTW89_CORE_RX_TYPE_H2C); 1780 1781 return cpu_to_le32(dword); 1782} 1783 1784void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 1785 struct rtw89_tx_desc_info *desc_info, 1786 void *txdesc) 1787{ 1788 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc; 1789 1790 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info); 1791} 1792EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2); 1793 1794static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1795 struct sk_buff *skb, 1796 struct rtw89_rx_phy_ppdu *phy_ppdu) 1797{ 1798 const struct rtw89_chip_info *chip = rtwdev->chip; 1799 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data; 1800 const struct rtw89_rxinfo_user *user; 1801 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 1802 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE; 1803 bool rx_cnt_valid = false; 1804 bool invalid = false; 1805 u8 plcp_size = 0; 1806 u8 *phy_sts; 1807 u8 usr_num; 1808 int i; 1809 1810 if (chip_gen == RTW89_CHIP_BE) { 1811 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1); 1812 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1; 1813 } 1814 1815 if (invalid) 1816 return -EINVAL; 1817 1818 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD); 1819 if (chip_gen == RTW89_CHIP_BE) { 1820 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3; 1821 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1); 1822 } else { 1823 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3; 1824 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM); 1825 } 1826 if (usr_num > chip->ppdu_max_usr) { 1827 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n", 1828 usr_num); 1829 return -EINVAL; 1830 } 1831 1832 for (i = 0; i < usr_num; i++) { 1833 user = &rxinfo->user[i]; 1834 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID)) 1835 continue; 1836 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set 1837 * by hardware, so update mac_id by rxinfo_user[].mac_id. 1838 */ 1839 if (chip->chip_id == RTL8922A) 1840 phy_ppdu->mac_id = 1841 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID); 1842 else if (chip->chip_id == RTL8922D) 1843 phy_ppdu->mac_id = 1844 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID_V1); 1845 1846 phy_ppdu->has_data = 1847 le32_get_bits(user->w0, RTW89_RXINFO_USER_DATA); 1848 phy_ppdu->has_bcn = 1849 le32_get_bits(user->w0, RTW89_RXINFO_USER_BCN); 1850 break; 1851 } 1852 1853 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1854 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1855 /* 8-byte alignment */ 1856 if (usr_num & BIT(0)) 1857 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1858 if (rx_cnt_valid) 1859 phy_sts += rx_cnt_size; 1860 phy_sts += plcp_size; 1861 1862 if (phy_sts > skb->data + skb->len) 1863 return -EINVAL; 1864 1865 phy_ppdu->buf = phy_sts; 1866 phy_ppdu->len = skb->data + skb->len - phy_sts; 1867 1868 return 0; 1869} 1870 1871static u8 rtw89_get_data_rate_nss(struct rtw89_dev *rtwdev, u16 data_rate) 1872{ 1873 u8 data_rate_mode; 1874 1875 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 1876 switch (data_rate_mode) { 1877 case DATA_RATE_MODE_NON_HT: 1878 return 1; 1879 case DATA_RATE_MODE_HT: 1880 return rtw89_get_data_ht_nss(rtwdev, data_rate) + 1; 1881 case DATA_RATE_MODE_VHT: 1882 case DATA_RATE_MODE_HE: 1883 case DATA_RATE_MODE_EHT: 1884 return rtw89_get_data_nss(rtwdev, data_rate) + 1; 1885 default: 1886 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1887 return 0; 1888 } 1889} 1890 1891static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1892 struct ieee80211_sta *sta) 1893{ 1894 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1895 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 1896 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 1897 struct rtw89_hal *hal = &rtwdev->hal; 1898 struct rtw89_sta_link *rtwsta_link; 1899 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 1900 u8 ant_pos = U8_MAX; 1901 u8 evm_pos = 0; 1902 int i; 1903 1904 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, phy_ppdu->phy_idx); 1905 if (unlikely(!rtwsta_link)) 1906 return; 1907 1908 if (rtwsta_link->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self) 1909 return; 1910 1911 if (hal->ant_diversity && hal->antenna_rx) { 1912 ant_pos = __ffs(hal->antenna_rx); 1913 evm_pos = ant_pos; 1914 } 1915 1916 ewma_rssi_add(&rtwsta_link->avg_rssi, phy_ppdu->rssi_avg); 1917 1918 if (ant_pos < ant_num) { 1919 ewma_rssi_add(&rtwsta_link->rssi[ant_pos], phy_ppdu->rssi[0]); 1920 } else { 1921 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 1922 ewma_rssi_add(&rtwsta_link->rssi[i], phy_ppdu->rssi[i]); 1923 } 1924 1925 if (phy_ppdu->ofdm.has && (phy_ppdu->has_data || phy_ppdu->has_bcn)) { 1926 ewma_snr_add(&rtwsta_link->avg_snr, phy_ppdu->ofdm.avg_snr); 1927 if (rtw89_get_data_rate_nss(rtwdev, phy_ppdu->rate) == 1) { 1928 ewma_evm_add(&rtwsta_link->evm_1ss, phy_ppdu->ofdm.evm_min); 1929 } else { 1930 ewma_evm_add(&rtwsta_link->evm_min[evm_pos], 1931 phy_ppdu->ofdm.evm_min); 1932 ewma_evm_add(&rtwsta_link->evm_max[evm_pos], 1933 phy_ppdu->ofdm.evm_max); 1934 } 1935 } 1936} 1937 1938#define VAR_LEN 0xff 1939#define VAR_LEN_UNIT 8 1940static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, 1941 const struct rtw89_phy_sts_iehdr *iehdr) 1942{ 1943 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = { 1944 [RTW89_CHIP_AX] = { 1945 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1946 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1947 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1948 }, 1949 [RTW89_CHIP_BE] = { 1950 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1951 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 88, 56, VAR_LEN, 1952 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1953 }, 1954 }; 1955 const u8 *physts_ie_len_tab; 1956 u16 ie_len; 1957 u8 ie; 1958 1959 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen]; 1960 1961 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1962 if (physts_ie_len_tab[ie] != VAR_LEN) 1963 ie_len = physts_ie_len_tab[ie]; 1964 else 1965 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT; 1966 1967 return ie_len; 1968} 1969 1970static void rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev *rtwdev, 1971 const struct rtw89_phy_sts_iehdr *iehdr, 1972 struct rtw89_rx_phy_ppdu *phy_ppdu) 1973{ 1974 const struct rtw89_phy_sts_ie01_v2 *ie; 1975 u8 *rpl_fd = phy_ppdu->rpl_fd; 1976 1977 ie = (const struct rtw89_phy_sts_ie01_v2 *)iehdr; 1978 rpl_fd[RF_PATH_A] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_A); 1979 rpl_fd[RF_PATH_B] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_B); 1980 rpl_fd[RF_PATH_C] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C); 1981 rpl_fd[RF_PATH_D] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_D); 1982 1983 phy_ppdu->bw_idx = le32_get_bits(ie->w5, RTW89_PHY_STS_IE01_V2_W5_BW_IDX); 1984} 1985 1986static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, 1987 const struct rtw89_phy_sts_iehdr *iehdr, 1988 struct rtw89_rx_phy_ppdu *phy_ppdu) 1989{ 1990 const struct rtw89_phy_sts_ie01 *ie = (const struct rtw89_phy_sts_ie01 *)iehdr; 1991 s16 cfo; 1992 u32 t; 1993 1994 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX); 1995 1996 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 1997 phy_ppdu->ldpc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_LDPC); 1998 phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC); 1999 } 2000 2001 if (!phy_ppdu->hdr_2_en) 2002 phy_ppdu->rx_path_en = 2003 le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RX_PATH_EN); 2004 2005 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 2006 return; 2007 2008 if (!phy_ppdu->to_self) 2009 return; 2010 2011 phy_ppdu->rpl_avg = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RSSI_AVG_FD); 2012 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR); 2013 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX); 2014 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN); 2015 phy_ppdu->ofdm.has = true; 2016 2017 /* sign conversion for S(12,2) */ 2018 if (rtwdev->chip->cfo_src_fd) { 2019 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO); 2020 cfo = sign_extend32(t, 11); 2021 } else { 2022 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO); 2023 cfo = sign_extend32(t, 11); 2024 } 2025 2026 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 2027 2028 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 2029 rtw89_core_parse_phy_status_ie01_v2(rtwdev, iehdr, phy_ppdu); 2030} 2031 2032static void rtw89_core_parse_phy_status_ie00(struct rtw89_dev *rtwdev, 2033 const struct rtw89_phy_sts_iehdr *iehdr, 2034 struct rtw89_rx_phy_ppdu *phy_ppdu) 2035{ 2036 const struct rtw89_phy_sts_ie00 *ie = (const struct rtw89_phy_sts_ie00 *)iehdr; 2037 u16 tmp_rpl; 2038 2039 tmp_rpl = le32_get_bits(ie->w0, RTW89_PHY_STS_IE00_W0_RPL); 2040 phy_ppdu->rpl_avg = tmp_rpl >> 1; 2041 2042 if (!phy_ppdu->hdr_2_en) 2043 phy_ppdu->rx_path_en = 2044 le32_get_bits(ie->w3, RTW89_PHY_STS_IE00_W3_RX_PATH_EN); 2045} 2046 2047static void rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev *rtwdev, 2048 const struct rtw89_phy_sts_iehdr *iehdr, 2049 struct rtw89_rx_phy_ppdu *phy_ppdu) 2050{ 2051 const struct rtw89_phy_sts_ie00_v2 *ie; 2052 u8 *rpl_path = phy_ppdu->rpl_path; 2053 u16 tmp_rpl[RF_PATH_MAX]; 2054 u8 i; 2055 2056 ie = (const struct rtw89_phy_sts_ie00_v2 *)iehdr; 2057 tmp_rpl[RF_PATH_A] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_A); 2058 tmp_rpl[RF_PATH_B] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_B); 2059 tmp_rpl[RF_PATH_C] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_C); 2060 tmp_rpl[RF_PATH_D] = le32_get_bits(ie->w5, RTW89_PHY_STS_IE00_V2_W5_RPL_TD_D); 2061 2062 for (i = 0; i < RF_PATH_MAX; i++) 2063 rpl_path[i] = tmp_rpl[i] >> 1; 2064} 2065 2066static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, 2067 const struct rtw89_phy_sts_iehdr *iehdr, 2068 struct rtw89_rx_phy_ppdu *phy_ppdu) 2069{ 2070 u8 ie; 2071 2072 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 2073 2074 switch (ie) { 2075 case RTW89_PHYSTS_IE00_CMN_CCK: 2076 rtw89_core_parse_phy_status_ie00(rtwdev, iehdr, phy_ppdu); 2077 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 2078 rtw89_core_parse_phy_status_ie00_v2(rtwdev, iehdr, phy_ppdu); 2079 break; 2080 case RTW89_PHYSTS_IE01_CMN_OFDM: 2081 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu); 2082 break; 2083 default: 2084 break; 2085 } 2086 2087 return 0; 2088} 2089 2090static void rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu *phy_ppdu) 2091{ 2092 const struct rtw89_phy_sts_hdr_v2 *hdr = phy_ppdu->buf + PHY_STS_HDR_LEN; 2093 2094 phy_ppdu->rx_path_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_V2_W0_PATH_EN); 2095} 2096 2097static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 2098{ 2099 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 2100 u8 *rssi = phy_ppdu->rssi; 2101 2102 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP); 2103 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG); 2104 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A); 2105 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B); 2106 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C); 2107 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D); 2108 2109 phy_ppdu->hdr_2_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_HDR_2_EN); 2110 if (phy_ppdu->hdr_2_en) 2111 rtw89_core_update_phy_ppdu_hdr_v2(phy_ppdu); 2112} 2113 2114static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 2115 struct rtw89_rx_phy_ppdu *phy_ppdu) 2116{ 2117 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 2118 u32 len_from_header; 2119 bool physts_valid; 2120 2121 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID); 2122 if (!physts_valid) 2123 return -EINVAL; 2124 2125 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3; 2126 2127 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 2128 len_from_header += PHY_STS_HDR_LEN; 2129 2130 if (len_from_header != phy_ppdu->len) { 2131 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 2132 return -EINVAL; 2133 } 2134 rtw89_core_update_phy_ppdu(phy_ppdu); 2135 2136 return 0; 2137} 2138 2139static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 2140 struct rtw89_rx_phy_ppdu *phy_ppdu) 2141{ 2142 u16 ie_len; 2143 void *pos, *end; 2144 2145 /* mark invalid reports and bypass them */ 2146 if (phy_ppdu->ie < RTW89_CCK_PKT) 2147 return -EINVAL; 2148 2149 pos = phy_ppdu->buf + PHY_STS_HDR_LEN; 2150 if (phy_ppdu->hdr_2_en) 2151 pos += PHY_STS_HDR_LEN; 2152 end = phy_ppdu->buf + phy_ppdu->len; 2153 while (pos < end) { 2154 const struct rtw89_phy_sts_iehdr *iehdr = pos; 2155 2156 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr); 2157 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu); 2158 pos += ie_len; 2159 if (pos > end || ie_len == 0) { 2160 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2161 "phy status parse failed\n"); 2162 return -EINVAL; 2163 } 2164 } 2165 2166 rtw89_chip_convert_rpl_to_rssi(rtwdev, phy_ppdu); 2167 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu); 2168 2169 return 0; 2170} 2171 2172static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 2173 struct rtw89_rx_phy_ppdu *phy_ppdu) 2174{ 2175 int ret; 2176 2177 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 2178 if (ret) 2179 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 2180 else 2181 phy_ppdu->valid = true; 2182 2183 ieee80211_iterate_stations_atomic(rtwdev->hw, 2184 rtw89_core_rx_process_phy_ppdu_iter, 2185 phy_ppdu); 2186} 2187 2188static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev, 2189 u8 desc_info_gi, 2190 bool rx_status) 2191{ 2192 switch (desc_info_gi) { 2193 case RTW89_GILTF_SGI_4XHE08: 2194 case RTW89_GILTF_2XHE08: 2195 case RTW89_GILTF_1XHE08: 2196 return NL80211_RATE_INFO_HE_GI_0_8; 2197 case RTW89_GILTF_2XHE16: 2198 case RTW89_GILTF_1XHE16: 2199 return NL80211_RATE_INFO_HE_GI_1_6; 2200 case RTW89_GILTF_LGI_4XHE32: 2201 return NL80211_RATE_INFO_HE_GI_3_2; 2202 default: 2203 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 2204 if (rx_status) 2205 return NL80211_RATE_INFO_HE_GI_3_2; 2206 return U8_MAX; 2207 } 2208} 2209 2210static u8 rtw89_rxdesc_to_nl_eht_gi(struct rtw89_dev *rtwdev, 2211 u8 desc_info_gi, 2212 bool rx_status) 2213{ 2214 switch (desc_info_gi) { 2215 case RTW89_GILTF_SGI_4XHE08: 2216 case RTW89_GILTF_2XHE08: 2217 case RTW89_GILTF_1XHE08: 2218 return NL80211_RATE_INFO_EHT_GI_0_8; 2219 case RTW89_GILTF_2XHE16: 2220 case RTW89_GILTF_1XHE16: 2221 return NL80211_RATE_INFO_EHT_GI_1_6; 2222 case RTW89_GILTF_LGI_4XHE32: 2223 return NL80211_RATE_INFO_EHT_GI_3_2; 2224 default: 2225 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 2226 if (rx_status) 2227 return NL80211_RATE_INFO_EHT_GI_3_2; 2228 return U8_MAX; 2229 } 2230} 2231 2232static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev, 2233 u8 desc_info_gi, 2234 bool rx_status, bool eht) 2235{ 2236 return eht ? rtw89_rxdesc_to_nl_eht_gi(rtwdev, desc_info_gi, rx_status) : 2237 rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info_gi, rx_status); 2238} 2239 2240static 2241bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf, 2242 bool eht) 2243{ 2244 if (eht) 2245 return status->eht.gi == gi_ltf; 2246 2247 return status->he_gi == gi_ltf; 2248} 2249 2250static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 2251 struct rtw89_rx_desc_info *desc_info, 2252 struct ieee80211_rx_status *status) 2253{ 2254 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2255 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 2256 bool eht = false; 2257 u16 data_rate; 2258 bool ret; 2259 2260 data_rate = desc_info->data_rate; 2261 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 2262 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 2263 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 2264 /* rate_idx is still hardware value here */ 2265 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 2266 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 2267 } else if (data_rate_mode == DATA_RATE_MODE_VHT || 2268 data_rate_mode == DATA_RATE_MODE_HE || 2269 data_rate_mode == DATA_RATE_MODE_EHT) { 2270 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2271 } else { 2272 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 2273 } 2274 2275 eht = data_rate_mode == DATA_RATE_MODE_EHT; 2276 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 2277 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht); 2278 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 2279 status->rate_idx == rate_idx && 2280 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) && 2281 status->bw == bw; 2282 2283 return ret; 2284} 2285 2286struct rtw89_vif_rx_stats_iter_data { 2287 struct rtw89_dev *rtwdev; 2288 struct rtw89_rx_phy_ppdu *phy_ppdu; 2289 struct rtw89_rx_desc_info *desc_info; 2290 struct sk_buff *skb; 2291 const u8 *bssid; 2292}; 2293 2294static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 2295 struct rtw89_vif_link *rtwvif_link, 2296 struct ieee80211_bss_conf *bss_conf, 2297 struct sk_buff *skb) 2298{ 2299 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 2300 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 2301 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 2302 u8 *pos, *end, type, tf_bw; 2303 u16 aid, tf_rua; 2304 2305 if (!ether_addr_equal(bss_conf->bssid, tf->ta) || 2306 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION || 2307 rtwvif_link->net_type == RTW89_NET_TYPE_NO_LINK) 2308 return; 2309 2310 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 2311 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR) 2312 return; 2313 2314 end = (u8 *)tf + skb->len; 2315 pos = tf->variable; 2316 2317 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 2318 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 2319 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos); 2320 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK); 2321 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2322 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n", 2323 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 2324 tf_rua, tf_bw); 2325 2326 if (aid == RTW89_TF_PAD) 2327 break; 2328 2329 if (aid == vif->cfg.aid) { 2330 enum nl80211_he_ru_alloc rua; 2331 2332 rtwvif->stats.rx_tf_acc++; 2333 rtwdev->stats.rx_tf_acc++; 2334 2335 /* The following only required for HE trigger frame, but we 2336 * cannot use UL HE-SIG-A2 reserved subfield to identify it 2337 * since some 11ax APs will fill it with all 0s, which will 2338 * be misunderstood as EHT trigger frame. 2339 */ 2340 if (bss_conf->eht_support) 2341 break; 2342 2343 rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1); 2344 2345 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ && 2346 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106) 2347 rtwvif_link->pwr_diff_en = true; 2348 break; 2349 } 2350 2351 pos += RTW89_TF_BASIC_USER_INFO_SZ; 2352 } 2353} 2354 2355static void rtw89_cancel_6ghz_probe_work(struct wiphy *wiphy, struct wiphy_work *work) 2356{ 2357 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2358 cancel_6ghz_probe_work); 2359 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 2360 struct rtw89_pktofld_info *info; 2361 2362 lockdep_assert_wiphy(wiphy); 2363 2364 if (!rtwdev->scanning) 2365 return; 2366 2367 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 2368 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload)) 2369 continue; 2370 2371 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id); 2372 2373 /* Don't delete/free info from pkt_list at this moment. Let it 2374 * be deleted/freed in rtw89_release_pkt_list() after scanning, 2375 * since if during scanning, pkt_list is accessed in bottom half. 2376 */ 2377 } 2378} 2379 2380static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev, 2381 struct sk_buff *skb) 2382{ 2383 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 2384 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 2385 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 2386 struct rtw89_pktofld_info *info; 2387 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie; 2388 bool queue_work = false; 2389 2390 if (rx_status->band != NL80211_BAND_6GHZ) 2391 return; 2392 2393 if (unlikely(!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ)))) { 2394 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rx on unsupported 6 GHz\n"); 2395 return; 2396 } 2397 2398 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len); 2399 2400 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 2401 if (ether_addr_equal(info->bssid, mgmt->bssid)) { 2402 info->cancel = true; 2403 queue_work = true; 2404 continue; 2405 } 2406 2407 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0) 2408 continue; 2409 2410 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) { 2411 info->cancel = true; 2412 queue_work = true; 2413 } 2414 } 2415 2416 if (queue_work) 2417 wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->cancel_6ghz_probe_work); 2418} 2419 2420static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link *rtwvif_link, 2421 struct ieee80211_hdr *hdr, size_t len) 2422{ 2423 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr; 2424 2425 if (len < offsetof(typeof(*mgmt), u.beacon.variable)) 2426 return; 2427 2428 WRITE_ONCE(rtwvif_link->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp)); 2429} 2430 2431static u32 rtw89_bcn_calc_min_tbtt(struct rtw89_dev *rtwdev, u32 tbtt1, u32 tbtt2) 2432{ 2433 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2434 u32 close_bcn_intvl_th = bcn_track->close_bcn_intvl_th; 2435 u32 tbtt_diff_th = bcn_track->tbtt_diff_th; 2436 2437 if (tbtt2 > tbtt1) 2438 swap(tbtt1, tbtt2); 2439 2440 if (tbtt1 - tbtt2 > tbtt_diff_th) 2441 return tbtt1; 2442 else if (tbtt2 > close_bcn_intvl_th) 2443 return tbtt2; 2444 else if (tbtt1 > close_bcn_intvl_th) 2445 return tbtt1; 2446 else 2447 return tbtt2; 2448} 2449 2450static void rtw89_bcn_cfg_tbtt_offset(struct rtw89_dev *rtwdev, 2451 struct rtw89_vif_link *rtwvif_link) 2452{ 2453 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2454 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2455 u32 offset = bcn_track->tbtt_offset; 2456 2457 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2458 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2459 const struct rtw89_port_reg *p = mac->port_base; 2460 u32 bcnspc, val; 2461 2462 bcnspc = rtw89_read32_port_mask(rtwdev, rtwvif_link, 2463 p->bcn_space, B_AX_BCN_SPACE_MASK); 2464 val = bcnspc - (offset / 1024); 2465 val = u32_encode_bits(val, B_AX_TBTT_SHIFT_OFST_MAG) | 2466 B_AX_TBTT_SHIFT_OFST_SIGN; 2467 2468 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_shift, 2469 B_AX_TBTT_SHIFT_OFST_MASK, val); 2470 2471 return; 2472 } 2473 2474 rtw89_fw_h2c_tbtt_tuning(rtwdev, rtwvif_link, offset); 2475} 2476 2477static void rtw89_bcn_update_tbtt_offset(struct rtw89_dev *rtwdev, 2478 struct rtw89_vif_link *rtwvif_link) 2479{ 2480 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2481 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2482 u32 *tbtt_us = bcn_stat->tbtt_us; 2483 u32 offset = tbtt_us[0]; 2484 u8 i; 2485 2486 for (i = 1; i < RTW89_BCN_TRACK_STAT_NR; i++) 2487 offset = rtw89_bcn_calc_min_tbtt(rtwdev, tbtt_us[i], offset); 2488 2489 if (bcn_track->tbtt_offset == offset) 2490 return; 2491 2492 bcn_track->tbtt_offset = offset; 2493 rtw89_bcn_cfg_tbtt_offset(rtwdev, rtwvif_link); 2494} 2495 2496static int cmp_u16(const void *a, const void *b) 2497{ 2498 return *(const u16 *)a - *(const u16 *)b; 2499} 2500 2501static u16 _rtw89_bcn_calc_drift(u16 tbtt, u16 offset, u16 beacon_int) 2502{ 2503 if (tbtt < offset) 2504 return beacon_int - offset + tbtt; 2505 2506 return tbtt - offset; 2507} 2508 2509static void rtw89_bcn_calc_drift(struct rtw89_dev *rtwdev) 2510{ 2511 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2512 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2513 u16 offset_tu = bcn_track->tbtt_offset / 1024; 2514 u16 *tbtt_tu = bcn_stat->tbtt_tu; 2515 u16 *drift = bcn_stat->drift; 2516 u8 i; 2517 2518 bcn_stat->tbtt_tu_min = U16_MAX; 2519 bcn_stat->tbtt_tu_max = 0; 2520 for (i = 0; i < RTW89_BCN_TRACK_STAT_NR; i++) { 2521 drift[i] = _rtw89_bcn_calc_drift(tbtt_tu[i], offset_tu, 2522 bcn_track->beacon_int); 2523 2524 bcn_stat->tbtt_tu_min = min(bcn_stat->tbtt_tu_min, tbtt_tu[i]); 2525 bcn_stat->tbtt_tu_max = max(bcn_stat->tbtt_tu_max, tbtt_tu[i]); 2526 } 2527 2528 sort(drift, RTW89_BCN_TRACK_STAT_NR, sizeof(*drift), cmp_u16, NULL); 2529} 2530 2531static void rtw89_bcn_calc_distribution(struct rtw89_dev *rtwdev) 2532{ 2533 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2534 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist; 2535 u16 lower_bound, upper_bound, outlier_count = 0; 2536 u16 *drift = bcn_stat->drift; 2537 u16 *bins = bcn_dist->bins; 2538 u16 q1, q3, iqr, tmp; 2539 u8 i; 2540 2541 BUILD_BUG_ON(RTW89_BCN_TRACK_STAT_NR % 4 != 0); 2542 2543 memset(bcn_dist, 0, sizeof(*bcn_dist)); 2544 2545 bcn_dist->min = drift[0]; 2546 bcn_dist->max = drift[RTW89_BCN_TRACK_STAT_NR - 1]; 2547 2548 tmp = RTW89_BCN_TRACK_STAT_NR / 4; 2549 q1 = ((drift[tmp] + drift[tmp - 1]) * RTW89_BCN_TRACK_SCALE_FACTOR) / 2; 2550 2551 tmp = (RTW89_BCN_TRACK_STAT_NR * 3) / 4; 2552 q3 = ((drift[tmp] + drift[tmp - 1]) * RTW89_BCN_TRACK_SCALE_FACTOR) / 2; 2553 2554 iqr = q3 - q1; 2555 tmp = (3 * iqr) / 2; 2556 2557 if (bcn_dist->min <= 5) 2558 lower_bound = bcn_dist->min; 2559 else if (q1 > tmp) 2560 lower_bound = (q1 - tmp) / RTW89_BCN_TRACK_SCALE_FACTOR; 2561 else 2562 lower_bound = 0; 2563 2564 upper_bound = (q3 + tmp) / RTW89_BCN_TRACK_SCALE_FACTOR; 2565 2566 for (i = 0; i < RTW89_BCN_TRACK_STAT_NR; i++) { 2567 u16 tbtt = bcn_stat->tbtt_tu[i]; 2568 u16 min = bcn_stat->tbtt_tu_min; 2569 u8 bin_idx; 2570 2571 /* histogram */ 2572 bin_idx = min((tbtt - min) / RTW89_BCN_TRACK_BIN_WIDTH, 2573 RTW89_BCN_TRACK_MAX_BIN_NUM - 1); 2574 bins[bin_idx]++; 2575 2576 /* boxplot outlier */ 2577 if (drift[i] < lower_bound || drift[i] > upper_bound) 2578 outlier_count++; 2579 } 2580 2581 bcn_dist->outlier_count = outlier_count; 2582 bcn_dist->lower_bound = lower_bound; 2583 bcn_dist->upper_bound = upper_bound; 2584} 2585 2586static u8 rtw89_bcn_get_coverage(struct rtw89_dev *rtwdev, u16 threshold) 2587{ 2588 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2589 int l = 0, r = RTW89_BCN_TRACK_STAT_NR - 1, m; 2590 u16 *drift = bcn_stat->drift; 2591 int index = -1; 2592 u8 count = 0; 2593 2594 while (l <= r) { 2595 m = l + (r - l) / 2; 2596 2597 if (drift[m] <= threshold) { 2598 index = m; 2599 l = m + 1; 2600 } else { 2601 r = m - 1; 2602 } 2603 } 2604 2605 count = (index == -1) ? 0 : (index + 1); 2606 2607 return (count * PERCENT) / RTW89_BCN_TRACK_STAT_NR; 2608} 2609 2610static u16 rtw89_bcn_get_histogram_bound(struct rtw89_dev *rtwdev, u8 target) 2611{ 2612 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2613 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist; 2614 u16 tbtt_tu_max = bcn_stat->tbtt_tu_max; 2615 u16 upper, lower = bcn_stat->tbtt_tu_min; 2616 u8 i, count = 0; 2617 2618 for (i = 0; i < RTW89_BCN_TRACK_MAX_BIN_NUM; i++) { 2619 upper = lower + RTW89_BCN_TRACK_BIN_WIDTH - 1; 2620 if (i == RTW89_BCN_TRACK_MAX_BIN_NUM - 1) 2621 upper = max(upper, tbtt_tu_max); 2622 2623 count += bcn_dist->bins[i]; 2624 if (count > target) 2625 break; 2626 2627 lower = upper + 1; 2628 } 2629 2630 return upper; 2631} 2632 2633static u16 rtw89_bcn_get_rx_time(struct rtw89_dev *rtwdev, 2634 const struct rtw89_chan *chan) 2635{ 2636#define RTW89_SYMBOL_TIME_2GHZ 192 2637#define RTW89_SYMBOL_TIME_5GHZ 20 2638#define RTW89_SYMBOL_TIME_6GHZ 20 2639 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 2640 u16 bitrate, val; 2641 2642 if (!rtw89_legacy_rate_to_bitrate(rtwdev, pkt_stat->beacon_rate, &bitrate)) 2643 return 0; 2644 2645 val = (pkt_stat->beacon_len * 8 * RTW89_BCN_TRACK_SCALE_FACTOR) / bitrate; 2646 2647 switch (chan->band_type) { 2648 default: 2649 case RTW89_BAND_2G: 2650 val += RTW89_SYMBOL_TIME_2GHZ; 2651 break; 2652 case RTW89_BAND_5G: 2653 val += RTW89_SYMBOL_TIME_5GHZ; 2654 break; 2655 case RTW89_BAND_6G: 2656 val += RTW89_SYMBOL_TIME_6GHZ; 2657 break; 2658 } 2659 2660 /* convert to millisecond */ 2661 return DIV_ROUND_UP(val, 1000); 2662} 2663 2664static void rtw89_bcn_calc_timeout(struct rtw89_dev *rtwdev, 2665 struct rtw89_vif_link *rtwvif_link) 2666{ 2667#define RTW89_BCN_TRACK_EXTEND_TIMEOUT 5 2668#define RTW89_BCN_TRACK_COVERAGE_TH 0 /* unit: TU */ 2669#define RTW89_BCN_TRACK_STRONG_RSSI 80 2670 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 2671 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 2672 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2673 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2674 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist; 2675 u16 outlier_high_bcn_th = bcn_track->outlier_high_bcn_th; 2676 u16 outlier_low_bcn_th = bcn_track->outlier_low_bcn_th; 2677 u8 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi); 2678 u16 target_bcn_th = bcn_track->target_bcn_th; 2679 u16 low_bcn_th = bcn_track->low_bcn_th; 2680 u16 med_bcn_th = bcn_track->med_bcn_th; 2681 u16 beacon_int = bcn_track->beacon_int; 2682 u16 bcn_timeout; 2683 2684 if (pkt_stat->beacon_nr < low_bcn_th) { 2685 bcn_timeout = (RTW89_BCN_TRACK_TARGET_BCN * beacon_int) / PERCENT; 2686 goto out; 2687 } 2688 2689 if (bcn_dist->outlier_count >= outlier_high_bcn_th) { 2690 bcn_timeout = bcn_dist->max; 2691 goto out; 2692 } 2693 2694 if (pkt_stat->beacon_nr < med_bcn_th) { 2695 if (bcn_dist->outlier_count > outlier_low_bcn_th) 2696 bcn_timeout = (bcn_dist->max + bcn_dist->upper_bound) / 2; 2697 else 2698 bcn_timeout = bcn_dist->upper_bound + 2699 RTW89_BCN_TRACK_EXTEND_TIMEOUT; 2700 2701 goto out; 2702 } 2703 2704 if (rssi >= RTW89_BCN_TRACK_STRONG_RSSI) { 2705 if (rtw89_bcn_get_coverage(rtwdev, RTW89_BCN_TRACK_COVERAGE_TH) >= 90) { 2706 /* ideal case */ 2707 bcn_timeout = 0; 2708 } else { 2709 u16 offset_tu = bcn_track->tbtt_offset / 1024; 2710 u16 upper_bound; 2711 2712 upper_bound = 2713 rtw89_bcn_get_histogram_bound(rtwdev, target_bcn_th); 2714 bcn_timeout = 2715 _rtw89_bcn_calc_drift(upper_bound, offset_tu, beacon_int); 2716 } 2717 2718 goto out; 2719 } 2720 2721 bcn_timeout = bcn_stat->drift[target_bcn_th]; 2722 2723out: 2724 bcn_track->bcn_timeout = bcn_timeout + rtw89_bcn_get_rx_time(rtwdev, chan); 2725} 2726 2727static void rtw89_bcn_update_timeout(struct rtw89_dev *rtwdev, 2728 struct rtw89_vif_link *rtwvif_link) 2729{ 2730 rtw89_bcn_calc_drift(rtwdev); 2731 rtw89_bcn_calc_distribution(rtwdev); 2732 rtw89_bcn_calc_timeout(rtwdev, rtwvif_link); 2733} 2734 2735static void rtw89_core_bcn_track(struct rtw89_dev *rtwdev) 2736{ 2737 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2738 struct rtw89_vif_link *rtwvif_link; 2739 struct rtw89_vif *rtwvif; 2740 unsigned int link_id; 2741 2742 if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw)) 2743 return; 2744 2745 if (!rtwdev->lps_enabled) 2746 return; 2747 2748 if (!bcn_track->is_data_ready) 2749 return; 2750 2751 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 2752 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) { 2753 if (!(rtwvif_link->wifi_role == RTW89_WIFI_ROLE_STATION || 2754 rtwvif_link->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT)) 2755 continue; 2756 2757 rtw89_bcn_update_tbtt_offset(rtwdev, rtwvif_link); 2758 rtw89_bcn_update_timeout(rtwdev, rtwvif_link); 2759 } 2760 } 2761} 2762 2763static bool rtw89_core_bcn_track_can_lps(struct rtw89_dev *rtwdev) 2764{ 2765 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2766 2767 if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw)) 2768 return true; 2769 2770 return bcn_track->is_data_ready; 2771} 2772 2773static void rtw89_core_bcn_track_assoc(struct rtw89_dev *rtwdev, 2774 struct rtw89_vif_link *rtwvif_link) 2775{ 2776#define RTW89_BCN_TRACK_MED_BCN 70 2777#define RTW89_BCN_TRACK_LOW_BCN 30 2778#define RTW89_BCN_TRACK_OUTLIER_HIGH_BCN 30 2779#define RTW89_BCN_TRACK_OUTLIER_LOW_BCN 20 2780 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2781 u32 period = jiffies_to_msecs(RTW89_TRACK_WORK_PERIOD); 2782 struct ieee80211_bss_conf *bss_conf; 2783 u32 beacons_in_period; 2784 u32 bcn_intvl_us; 2785 u16 beacon_int; 2786 u8 dtim; 2787 2788 rcu_read_lock(); 2789 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 2790 beacon_int = bss_conf->beacon_int ?: 100; 2791 dtim = bss_conf->dtim_period; 2792 rcu_read_unlock(); 2793 2794 beacons_in_period = period / beacon_int / dtim; 2795 bcn_intvl_us = ieee80211_tu_to_usec(beacon_int); 2796 2797 bcn_track->low_bcn_th = 2798 (beacons_in_period * RTW89_BCN_TRACK_LOW_BCN) / PERCENT; 2799 bcn_track->med_bcn_th = 2800 (beacons_in_period * RTW89_BCN_TRACK_MED_BCN) / PERCENT; 2801 bcn_track->outlier_low_bcn_th = 2802 (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_OUTLIER_LOW_BCN) / PERCENT; 2803 bcn_track->outlier_high_bcn_th = 2804 (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_OUTLIER_HIGH_BCN) / PERCENT; 2805 bcn_track->target_bcn_th = 2806 (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_TARGET_BCN) / PERCENT; 2807 2808 bcn_track->close_bcn_intvl_th = ieee80211_tu_to_usec(beacon_int - 3); 2809 bcn_track->tbtt_diff_th = (bcn_intvl_us * 85) / PERCENT; 2810 bcn_track->beacon_int = beacon_int; 2811 bcn_track->dtim = dtim; 2812} 2813 2814static void rtw89_core_bcn_track_reset(struct rtw89_dev *rtwdev) 2815{ 2816 memset(&rtwdev->phystat.bcn_stat, 0, sizeof(rtwdev->phystat.bcn_stat)); 2817 memset(&rtwdev->bcn_track, 0, sizeof(rtwdev->bcn_track)); 2818} 2819 2820static void rtw89_vif_rx_bcn_stat(struct rtw89_dev *rtwdev, struct sk_buff *skb) 2821{ 2822#define RTW89_APPEND_TSF_2GHZ 384 2823#define RTW89_APPEND_TSF_5GHZ 52 2824#define RTW89_APPEND_TSF_6GHZ 52 2825 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 2826 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 2827 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2828 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2829 u32 bcn_intvl_us = ieee80211_tu_to_usec(bcn_track->beacon_int); 2830 u64 tsf = le64_to_cpu(mgmt->u.beacon.timestamp); 2831 u8 wp, num = bcn_stat->num; 2832 u16 append; 2833 2834 if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw)) 2835 return; 2836 2837 /* Skip if not yet associated */ 2838 if (!bcn_intvl_us) 2839 return; 2840 2841 switch (rx_status->band) { 2842 default: 2843 case NL80211_BAND_2GHZ: 2844 append = RTW89_APPEND_TSF_2GHZ; 2845 break; 2846 case NL80211_BAND_5GHZ: 2847 append = RTW89_APPEND_TSF_5GHZ; 2848 break; 2849 case NL80211_BAND_6GHZ: 2850 append = RTW89_APPEND_TSF_6GHZ; 2851 break; 2852 } 2853 2854 wp = bcn_stat->wp; 2855 div_u64_rem(tsf - append, bcn_intvl_us, &bcn_stat->tbtt_us[wp]); 2856 bcn_stat->tbtt_tu[wp] = bcn_stat->tbtt_us[wp] / 1024; 2857 bcn_stat->wp = (wp + 1) % RTW89_BCN_TRACK_STAT_NR; 2858 bcn_stat->num = umin(num + 1, RTW89_BCN_TRACK_STAT_NR); 2859 bcn_track->is_data_ready = bcn_stat->num == RTW89_BCN_TRACK_STAT_NR; 2860} 2861 2862static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 2863 struct ieee80211_vif *vif) 2864{ 2865 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 2866 struct rtw89_dev *rtwdev = iter_data->rtwdev; 2867 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 2868 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 2869 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 2870 struct sk_buff *skb = iter_data->skb; 2871 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 2872 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2873 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu; 2874 bool is_mld = ieee80211_vif_is_mld(vif); 2875 struct ieee80211_bss_conf *bss_conf; 2876 struct rtw89_vif_link *rtwvif_link; 2877 const u8 *bssid = iter_data->bssid; 2878 const u8 *target_bssid; 2879 2880 if (rtwdev->scanning && 2881 (ieee80211_is_beacon(hdr->frame_control) || 2882 ieee80211_is_probe_resp(hdr->frame_control))) 2883 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb); 2884 2885 rcu_read_lock(); 2886 2887 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, desc_info->bb_sel); 2888 if (unlikely(!rtwvif_link)) 2889 goto out; 2890 2891 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 2892 if (!bss_conf->bssid) 2893 goto out; 2894 2895 if (ieee80211_is_trigger(hdr->frame_control)) { 2896 rtw89_stats_trigger_frame(rtwdev, rtwvif_link, bss_conf, skb); 2897 goto out; 2898 } 2899 2900 target_bssid = ieee80211_is_beacon(hdr->frame_control) && 2901 bss_conf->nontransmitted ? 2902 bss_conf->transmitter_bssid : bss_conf->bssid; 2903 if (!ether_addr_equal(target_bssid, bssid)) 2904 goto out; 2905 2906 if (is_mld) { 2907 rx_status->link_valid = true; 2908 rx_status->link_id = rtwvif_link->link_id; 2909 } 2910 2911 if (ieee80211_is_beacon(hdr->frame_control)) { 2912 if (vif->type == NL80211_IFTYPE_STATION && 2913 !test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) { 2914 rtw89_vif_sync_bcn_tsf(rtwvif_link, hdr, skb->len); 2915 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu); 2916 } 2917 2918 if (phy_ppdu) { 2919 ewma_rssi_add(&rtwdev->phystat.bcn_rssi, phy_ppdu->rssi_avg); 2920 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 2921 rtwvif_link->bcn_bw_idx = phy_ppdu->bw_idx; 2922 } 2923 2924 pkt_stat->beacon_nr++; 2925 pkt_stat->beacon_rate = desc_info->data_rate; 2926 pkt_stat->beacon_len = skb->len; 2927 2928 rtw89_vif_rx_bcn_stat(rtwdev, skb); 2929 } 2930 2931 if (!ether_addr_equal(bss_conf->addr, hdr->addr1)) 2932 goto out; 2933 2934 if (desc_info->data_rate < RTW89_HW_RATE_NR) 2935 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 2936 2937 rtw89_traffic_stats_accu(rtwdev, rtwvif, skb, false, false); 2938 2939out: 2940 rcu_read_unlock(); 2941} 2942 2943static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 2944 struct rtw89_rx_phy_ppdu *phy_ppdu, 2945 struct rtw89_rx_desc_info *desc_info, 2946 struct sk_buff *skb) 2947{ 2948 struct rtw89_vif_rx_stats_iter_data iter_data; 2949 2950 rtw89_traffic_stats_accu(rtwdev, NULL, skb, true, false); 2951 2952 iter_data.rtwdev = rtwdev; 2953 iter_data.phy_ppdu = phy_ppdu; 2954 iter_data.desc_info = desc_info; 2955 iter_data.skb = skb; 2956 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 2957 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 2958} 2959 2960static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 2961 struct ieee80211_rx_status *status) 2962{ 2963 const struct rtw89_chan_rcd *rcd = 2964 rtw89_chan_rcd_get(rtwdev, RTW89_CHANCTX_0); 2965 u16 chan = rcd->prev_primary_channel; 2966 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type); 2967 2968 if (status->band != NL80211_BAND_2GHZ && 2969 status->encoding == RX_ENC_LEGACY && 2970 status->rate_idx < RTW89_HW_RATE_OFDM6) { 2971 status->freq = ieee80211_channel_to_frequency(chan, band); 2972 status->band = band; 2973 } 2974} 2975 2976static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 2977{ 2978 if (rx_status->band == NL80211_BAND_2GHZ || 2979 rx_status->encoding != RX_ENC_LEGACY) 2980 return; 2981 2982 /* Some control frames' freq(ACKs in this case) are reported wrong due 2983 * to FW notify timing, set to lowest rate to prevent overflow. 2984 */ 2985 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 2986 rx_status->rate_idx = 0; 2987 return; 2988 } 2989 2990 /* No 4 CCK rates for non-2G */ 2991 rx_status->rate_idx -= 4; 2992} 2993 2994static 2995void rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev *rtwdev, 2996 struct ieee80211_rx_status *rx_status, 2997 struct rtw89_rx_phy_ppdu *phy_ppdu) 2998{ 2999 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 3000 return; 3001 3002 if (!phy_ppdu) 3003 return; 3004 3005 if (phy_ppdu->ldpc) 3006 rx_status->enc_flags |= RX_ENC_FLAG_LDPC; 3007 if (phy_ppdu->stbc) 3008 rx_status->enc_flags |= u8_encode_bits(1, RX_ENC_FLAG_STBC_MASK); 3009} 3010 3011static const u8 rx_status_bw_to_radiotap_eht_usig[] = { 3012 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ, 3013 [RATE_INFO_BW_5] = U8_MAX, 3014 [RATE_INFO_BW_10] = U8_MAX, 3015 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ, 3016 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ, 3017 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ, 3018 [RATE_INFO_BW_HE_RU] = U8_MAX, 3019 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1, 3020 [RATE_INFO_BW_EHT_RU] = U8_MAX, 3021}; 3022 3023static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev, 3024 struct sk_buff *skb, 3025 struct ieee80211_rx_status *rx_status) 3026{ 3027 struct ieee80211_radiotap_eht_usig *usig; 3028 struct ieee80211_radiotap_eht *eht; 3029 struct ieee80211_radiotap_tlv *tlv; 3030 int eht_len = struct_size(eht, user_info, 1); 3031 int usig_len = sizeof(*usig); 3032 int len; 3033 u8 bw; 3034 3035 len = sizeof(*tlv) + ALIGN(eht_len, 4) + 3036 sizeof(*tlv) + ALIGN(usig_len, 4); 3037 3038 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END; 3039 skb_reset_mac_header(skb); 3040 3041 /* EHT */ 3042 tlv = skb_push(skb, len); 3043 memset(tlv, 0, len); 3044 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT); 3045 tlv->len = cpu_to_le16(eht_len); 3046 3047 eht = (struct ieee80211_radiotap_eht *)tlv->data; 3048 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI); 3049 eht->data[0] = 3050 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI); 3051 3052 eht->user_info[0] = 3053 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN | 3054 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O | 3055 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN); 3056 eht->user_info[0] |= 3057 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) | 3058 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O); 3059 if (rx_status->enc_flags & RX_ENC_FLAG_LDPC) 3060 eht->user_info[0] |= 3061 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_CODING); 3062 3063 /* U-SIG */ 3064 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4); 3065 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG); 3066 tlv->len = cpu_to_le16(usig_len); 3067 3068 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig)) 3069 return; 3070 3071 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw]; 3072 if (bw == U8_MAX) 3073 return; 3074 3075 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data; 3076 usig->common = 3077 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) | 3078 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW); 3079} 3080 3081static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev, 3082 struct sk_buff *skb, 3083 struct ieee80211_rx_status *rx_status) 3084{ 3085 static const struct ieee80211_radiotap_he known_he = { 3086 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 3087 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN | 3088 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN | 3089 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 3090 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 3091 }; 3092 struct ieee80211_radiotap_he *he; 3093 3094 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 3095 return; 3096 3097 if (rx_status->encoding == RX_ENC_HE) { 3098 rx_status->flag |= RX_FLAG_RADIOTAP_HE; 3099 he = skb_push(skb, sizeof(*he)); 3100 *he = known_he; 3101 } else if (rx_status->encoding == RX_ENC_EHT) { 3102 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status); 3103 } 3104} 3105 3106static void rtw89_core_validate_rx_signal(struct ieee80211_rx_status *rx_status) 3107{ 3108 if (!rx_status->signal) 3109 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 3110} 3111 3112static void rtw89_core_update_rx_freq_from_ie(struct rtw89_dev *rtwdev, 3113 struct sk_buff *skb, 3114 struct ieee80211_rx_status *rx_status) 3115{ 3116 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 3117 size_t hdr_len, ielen; 3118 u8 *variable; 3119 int chan; 3120 3121 if (!rtwdev->chip->rx_freq_frome_ie) 3122 return; 3123 3124 if (!rtwdev->scanning) 3125 return; 3126 3127 if (ieee80211_is_beacon(mgmt->frame_control)) { 3128 variable = mgmt->u.beacon.variable; 3129 hdr_len = offsetof(struct ieee80211_mgmt, 3130 u.beacon.variable); 3131 } else if (ieee80211_is_probe_resp(mgmt->frame_control)) { 3132 variable = mgmt->u.probe_resp.variable; 3133 hdr_len = offsetof(struct ieee80211_mgmt, 3134 u.probe_resp.variable); 3135 } else { 3136 return; 3137 } 3138 3139 if (skb->len > hdr_len) 3140 ielen = skb->len - hdr_len; 3141 else 3142 return; 3143 3144 /* The parsing code for both 2GHz and 5GHz bands is the same in this 3145 * function. 3146 */ 3147 chan = cfg80211_get_ies_channel_number(variable, ielen, NL80211_BAND_2GHZ); 3148 if (chan == -1) 3149 return; 3150 3151 rx_status->band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 3152 rx_status->freq = ieee80211_channel_to_frequency(chan, rx_status->band); 3153} 3154 3155static void rtw89_core_correct_mcc_chan(struct rtw89_dev *rtwdev, 3156 struct rtw89_rx_desc_info *desc_info, 3157 struct ieee80211_rx_status *rx_status, 3158 struct rtw89_rx_phy_ppdu *phy_ppdu) 3159{ 3160 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 3161 struct rtw89_vif_link *rtwvif_link; 3162 struct rtw89_sta_link *rtwsta_link; 3163 const struct rtw89_chan *chan; 3164 u8 mac_id = desc_info->mac_id; 3165 enum rtw89_entity_mode mode; 3166 enum nl80211_band band; 3167 3168 mode = rtw89_get_entity_mode(rtwdev); 3169 if (likely(mode != RTW89_ENTITY_MODE_MCC)) 3170 return; 3171 3172 if (chip_gen == RTW89_CHIP_BE && phy_ppdu) 3173 mac_id = phy_ppdu->mac_id; 3174 3175 rcu_read_lock(); 3176 3177 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, mac_id); 3178 if (!rtwsta_link) 3179 goto out; 3180 3181 rtwvif_link = rtwsta_link->rtwvif_link; 3182 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 3183 band = rtw89_hw_to_nl80211_band(chan->band_type); 3184 rx_status->freq = ieee80211_channel_to_frequency(chan->primary_channel, band); 3185 3186out: 3187 rcu_read_unlock(); 3188} 3189 3190static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 3191 struct rtw89_rx_phy_ppdu *phy_ppdu, 3192 struct rtw89_rx_desc_info *desc_info, 3193 struct sk_buff *skb_ppdu, 3194 struct ieee80211_rx_status *rx_status) 3195{ 3196 struct napi_struct *napi = &rtwdev->napi; 3197 3198 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 3199 if (unlikely(!napi_is_scheduled(napi))) 3200 napi = NULL; 3201 3202 rtw89_core_hw_to_sband_rate(rx_status); 3203 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 3204 rtw89_core_update_rx_status_by_ppdu(rtwdev, rx_status, phy_ppdu); 3205 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status); 3206 rtw89_core_validate_rx_signal(rx_status); 3207 rtw89_core_update_rx_freq_from_ie(rtwdev, skb_ppdu, rx_status); 3208 rtw89_core_correct_mcc_chan(rtwdev, desc_info, rx_status, phy_ppdu); 3209 3210 /* In low power mode, it does RX in thread context. */ 3211 local_bh_disable(); 3212 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 3213 local_bh_enable(); 3214 rtwdev->napi_budget_countdown--; 3215} 3216 3217static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 3218 struct rtw89_rx_phy_ppdu *phy_ppdu, 3219 struct rtw89_rx_desc_info *desc_info, 3220 struct sk_buff *skb) 3221{ 3222 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 3223 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 3224 struct sk_buff *skb_ppdu = NULL, *tmp; 3225 struct ieee80211_rx_status *rx_status; 3226 3227 if (curr > RTW89_MAX_PPDU_CNT) 3228 return; 3229 3230 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 3231 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 3232 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 3233 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 3234 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 3235 rtw89_correct_cck_chan(rtwdev, rx_status); 3236 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 3237 } 3238} 3239 3240static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 3241 struct rtw89_rx_desc_info *desc_info, 3242 struct sk_buff *skb) 3243{ 3244 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 3245 .len = skb->len, 3246 .to_self = desc_info->addr1_match, 3247 .rate = desc_info->data_rate, 3248 .mac_id = desc_info->mac_id, 3249 .phy_idx = desc_info->bb_sel}; 3250 int ret; 3251 3252 if (desc_info->mac_info_valid) { 3253 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 3254 if (ret) 3255 goto out; 3256 } 3257 3258 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 3259 if (ret) 3260 goto out; 3261 3262 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 3263 3264out: 3265 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 3266 dev_kfree_skb_any(skb); 3267} 3268 3269static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 3270 struct rtw89_rx_desc_info *desc_info, 3271 struct sk_buff *skb) 3272{ 3273 switch (desc_info->pkt_type) { 3274 case RTW89_CORE_RX_TYPE_C2H: 3275 rtw89_fw_c2h_irqsafe(rtwdev, skb); 3276 break; 3277 case RTW89_CORE_RX_TYPE_PPDU_STAT: 3278 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 3279 break; 3280 default: 3281 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 3282 desc_info->pkt_type); 3283 dev_kfree_skb_any(skb); 3284 break; 3285 } 3286} 3287 3288void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 3289 struct rtw89_rx_desc_info *desc_info, 3290 u8 *data, u32 data_offset) 3291{ 3292 const struct rtw89_chip_info *chip = rtwdev->chip; 3293 struct rtw89_rxdesc_short *rxd_s; 3294 struct rtw89_rxdesc_long *rxd_l; 3295 u8 shift_len, drv_info_len; 3296 3297 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 3298 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK); 3299 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK); 3300 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD); 3301 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK); 3302 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD); 3303 if (chip->chip_id == RTL8852C) 3304 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK); 3305 else 3306 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK); 3307 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK); 3308 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK); 3309 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK); 3310 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN); 3311 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK); 3312 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK); 3313 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK); 3314 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR); 3315 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR); 3316 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC); 3317 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC); 3318 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH); 3319 3320 shift_len = desc_info->shift << 1; /* 2-byte unit */ 3321 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 3322 desc_info->offset = data_offset + shift_len + drv_info_len; 3323 if (desc_info->long_rxdesc) 3324 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long); 3325 else 3326 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short); 3327 desc_info->ready = true; 3328 3329 if (!desc_info->long_rxdesc) 3330 return; 3331 3332 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 3333 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK); 3334 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD); 3335 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK); 3336 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK); 3337 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK); 3338 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK); 3339} 3340EXPORT_SYMBOL(rtw89_core_query_rxdesc); 3341 3342void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 3343 struct rtw89_rx_desc_info *desc_info, 3344 u8 *data, u32 data_offset) 3345{ 3346 struct rtw89_rxdesc_phy_rpt_v2 *rxd_rpt; 3347 struct rtw89_rxdesc_short_v2 *rxd_s; 3348 struct rtw89_rxdesc_long_v2 *rxd_l; 3349 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len; 3350 3351 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset); 3352 3353 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK); 3354 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK); 3355 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK); 3356 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK); 3357 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK); 3358 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD); 3359 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK); 3360 desc_info->bb_sel = le32_get_bits(rxd_s->dword0, BE_RXD_BB_SEL); 3361 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT) 3362 desc_info->mac_info_valid = true; 3363 3364 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK); 3365 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK); 3366 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD); 3367 3368 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR); 3369 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR); 3370 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC); 3371 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC); 3372 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH); 3373 3374 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK); 3375 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK); 3376 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK); 3377 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK); 3378 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK); 3379 3380 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5); 3381 3382 shift_len = desc_info->shift << 1; /* 2-byte unit */ 3383 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 3384 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */ 3385 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */ 3386 desc_info->offset = data_offset + shift_len + drv_info_len + 3387 phy_rtp_len + hdr_cnv_len; 3388 3389 if (desc_info->long_rxdesc) 3390 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2); 3391 else 3392 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2); 3393 desc_info->ready = true; 3394 3395 if (phy_rtp_len == sizeof(*rxd_rpt)) { 3396 rxd_rpt = (struct rtw89_rxdesc_phy_rpt_v2 *)(data + data_offset + 3397 desc_info->rxd_len); 3398 desc_info->rssi = le32_get_bits(rxd_rpt->dword0, BE_RXD_PHY_RSSI); 3399 } 3400 3401 if (!desc_info->long_rxdesc) 3402 return; 3403 3404 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset); 3405 3406 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN); 3407 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK); 3408 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK); 3409 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK); 3410 3411 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK); 3412} 3413EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2); 3414 3415struct rtw89_core_iter_rx_status { 3416 struct rtw89_dev *rtwdev; 3417 struct ieee80211_rx_status *rx_status; 3418 struct rtw89_rx_desc_info *desc_info; 3419 u8 mac_id; 3420}; 3421 3422static 3423void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 3424{ 3425 struct rtw89_core_iter_rx_status *iter_data = 3426 (struct rtw89_core_iter_rx_status *)data; 3427 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 3428 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 3429 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3430 struct rtw89_sta_link *rtwsta_link; 3431 u8 mac_id = iter_data->mac_id; 3432 3433 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, desc_info->bb_sel); 3434 if (unlikely(!rtwsta_link)) 3435 return; 3436 3437 if (mac_id != rtwsta_link->mac_id) 3438 return; 3439 3440 rtwsta_link->rx_status = *rx_status; 3441 rtwsta_link->rx_hw_rate = desc_info->data_rate; 3442} 3443 3444static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 3445 struct rtw89_rx_desc_info *desc_info, 3446 struct ieee80211_rx_status *rx_status) 3447{ 3448 struct rtw89_core_iter_rx_status iter_data; 3449 3450 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 3451 return; 3452 3453 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 3454 return; 3455 3456 iter_data.rtwdev = rtwdev; 3457 iter_data.rx_status = rx_status; 3458 iter_data.desc_info = desc_info; 3459 iter_data.mac_id = desc_info->mac_id; 3460 ieee80211_iterate_stations_atomic(rtwdev->hw, 3461 rtw89_core_stats_sta_rx_status_iter, 3462 &iter_data); 3463} 3464 3465static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 3466 struct sk_buff *skb, 3467 struct rtw89_rx_desc_info *desc_info, 3468 struct ieee80211_rx_status *rx_status) 3469{ 3470 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 3471 const struct cfg80211_chan_def *chandef = 3472 rtw89_chandef_get(rtwdev, RTW89_CHANCTX_0); 3473 u16 data_rate; 3474 u8 data_rate_mode; 3475 bool eht = false; 3476 u8 gi; 3477 3478 /* currently using single PHY */ 3479 rx_status->freq = chandef->chan->center_freq; 3480 rx_status->band = chandef->chan->band; 3481 3482 if (ieee80211_is_beacon(hdr->frame_control) || 3483 ieee80211_is_probe_resp(hdr->frame_control)) 3484 rx_status->boottime_ns = ktime_get_boottime_ns(); 3485 3486 if (rtwdev->scanning && 3487 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 3488 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev); 3489 u8 chan = cur->primary_channel; 3490 u8 band = cur->band_type; 3491 enum nl80211_band nl_band; 3492 3493 nl_band = rtw89_hw_to_nl80211_band(band); 3494 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 3495 rx_status->band = nl_band; 3496 } 3497 3498 if (desc_info->icv_err || desc_info->crc32_err) 3499 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 3500 3501 if (desc_info->hw_dec && 3502 !(desc_info->sw_dec || desc_info->icv_err)) 3503 rx_status->flag |= RX_FLAG_DECRYPTED; 3504 3505 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 3506 3507 data_rate = desc_info->data_rate; 3508 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 3509 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 3510 rx_status->encoding = RX_ENC_LEGACY; 3511 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 3512 /* convert rate_idx after we get the correct band */ 3513 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 3514 rx_status->encoding = RX_ENC_HT; 3515 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 3516 if (desc_info->gi_ltf) 3517 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 3518 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 3519 rx_status->encoding = RX_ENC_VHT; 3520 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 3521 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 3522 if (desc_info->gi_ltf) 3523 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 3524 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 3525 rx_status->encoding = RX_ENC_HE; 3526 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 3527 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 3528 } else if (data_rate_mode == DATA_RATE_MODE_EHT) { 3529 rx_status->encoding = RX_ENC_EHT; 3530 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 3531 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 3532 eht = true; 3533 } else { 3534 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 3535 } 3536 3537 /* he_gi is used to match ppdu, so we always fill it. */ 3538 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht); 3539 if (eht) 3540 rx_status->eht.gi = gi; 3541 else 3542 rx_status->he_gi = gi; 3543 rx_status->flag |= RX_FLAG_MACTIME_START; 3544 rx_status->mactime = desc_info->free_run_cnt; 3545 3546 rtw89_chip_phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 3547 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 3548} 3549 3550static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 3551{ 3552 const struct rtw89_chip_info *chip = rtwdev->chip; 3553 3554 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE) 3555 return RTW89_PS_MODE_NONE; 3556 3557 if (rtw89_disable_ps_mode || !chip->ps_mode_supported || 3558 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw)) 3559 return RTW89_PS_MODE_NONE; 3560 3561 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) && 3562 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw)) 3563 return RTW89_PS_MODE_PWR_GATED; 3564 3565 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 3566 return RTW89_PS_MODE_CLK_GATED; 3567 3568 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 3569 return RTW89_PS_MODE_RFOFF; 3570 3571 return RTW89_PS_MODE_NONE; 3572} 3573 3574static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 3575 struct rtw89_rx_desc_info *desc_info) 3576{ 3577 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 3578 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 3579 struct ieee80211_rx_status *rx_status; 3580 struct sk_buff *skb_ppdu, *tmp; 3581 3582 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 3583 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 3584 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 3585 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 3586 } 3587} 3588 3589static 3590void rtw89_core_rx_pkt_hdl(struct rtw89_dev *rtwdev, const struct sk_buff *skb, 3591 const struct rtw89_rx_desc_info *desc) 3592{ 3593 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 3594 struct rtw89_sta_link *rtwsta_link; 3595 struct ieee80211_sta *sta; 3596 struct rtw89_sta *rtwsta; 3597 u8 macid = desc->mac_id; 3598 3599 if (!refcount_read(&rtwdev->refcount_ap_info)) 3600 return; 3601 3602 rcu_read_lock(); 3603 3604 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid); 3605 if (!rtwsta_link) 3606 goto out; 3607 3608 rtwsta = rtwsta_link->rtwsta; 3609 if (!test_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags)) 3610 goto out; 3611 3612 sta = rtwsta_to_sta(rtwsta); 3613 if (ieee80211_is_pspoll(hdr->frame_control)) 3614 ieee80211_sta_pspoll(sta); 3615 else if (ieee80211_has_pm(hdr->frame_control) && 3616 (ieee80211_is_data_qos(hdr->frame_control) || 3617 ieee80211_is_qos_nullfunc(hdr->frame_control))) 3618 ieee80211_sta_uapsd_trigger(sta, ieee80211_get_tid(hdr)); 3619 3620out: 3621 rcu_read_unlock(); 3622} 3623 3624void rtw89_core_rx(struct rtw89_dev *rtwdev, 3625 struct rtw89_rx_desc_info *desc_info, 3626 struct sk_buff *skb) 3627{ 3628 struct ieee80211_rx_status *rx_status; 3629 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 3630 u8 ppdu_cnt = desc_info->ppdu_cnt; 3631 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 3632 3633 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 3634 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 3635 return; 3636 } 3637 3638 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 3639 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 3640 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 3641 } 3642 3643 rx_status = IEEE80211_SKB_RXCB(skb); 3644 memset(rx_status, 0, sizeof(*rx_status)); 3645 rtw89_core_update_rx_status(rtwdev, skb, desc_info, rx_status); 3646 rtw89_core_rx_pkt_hdl(rtwdev, skb, desc_info); 3647 if (desc_info->long_rxdesc && 3648 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 3649 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 3650 else 3651 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 3652} 3653EXPORT_SYMBOL(rtw89_core_rx); 3654 3655void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 3656{ 3657 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 3658 return; 3659 3660 napi_enable(&rtwdev->napi); 3661} 3662EXPORT_SYMBOL(rtw89_core_napi_start); 3663 3664void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 3665{ 3666 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 3667 return; 3668 3669 napi_synchronize(&rtwdev->napi); 3670 napi_disable(&rtwdev->napi); 3671} 3672EXPORT_SYMBOL(rtw89_core_napi_stop); 3673 3674int rtw89_core_napi_init(struct rtw89_dev *rtwdev) 3675{ 3676 rtwdev->netdev = alloc_netdev_dummy(0); 3677 if (!rtwdev->netdev) 3678 return -ENOMEM; 3679 3680 netif_napi_add(rtwdev->netdev, &rtwdev->napi, 3681 rtwdev->hci.ops->napi_poll); 3682 return 0; 3683} 3684EXPORT_SYMBOL(rtw89_core_napi_init); 3685 3686void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 3687{ 3688 rtw89_core_napi_stop(rtwdev); 3689 netif_napi_del(&rtwdev->napi); 3690 free_netdev(rtwdev->netdev); 3691} 3692EXPORT_SYMBOL(rtw89_core_napi_deinit); 3693 3694static void rtw89_core_ba_work(struct work_struct *work) 3695{ 3696 struct rtw89_dev *rtwdev = 3697 container_of(work, struct rtw89_dev, ba_work); 3698 struct rtw89_txq *rtwtxq, *tmp; 3699 int ret; 3700 3701 spin_lock_bh(&rtwdev->ba_lock); 3702 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 3703 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3704 struct ieee80211_sta *sta = txq->sta; 3705 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 3706 u8 tid = txq->tid; 3707 3708 if (!sta) { 3709 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 3710 goto skip_ba_work; 3711 } 3712 3713 if (rtwsta->disassoc) { 3714 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3715 "cannot start BA with disassoc sta\n"); 3716 goto skip_ba_work; 3717 } 3718 3719 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 3720 if (ret) { 3721 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3722 "failed to setup BA session for %pM:%2d: %d\n", 3723 sta->addr, tid, ret); 3724 if (ret == -EINVAL) 3725 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 3726 } 3727skip_ba_work: 3728 list_del_init(&rtwtxq->list); 3729 } 3730 spin_unlock_bh(&rtwdev->ba_lock); 3731} 3732 3733void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 3734 struct ieee80211_sta *sta) 3735{ 3736 struct rtw89_txq *rtwtxq, *tmp; 3737 3738 spin_lock_bh(&rtwdev->ba_lock); 3739 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 3740 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3741 3742 if (sta == txq->sta) 3743 list_del_init(&rtwtxq->list); 3744 } 3745 spin_unlock_bh(&rtwdev->ba_lock); 3746} 3747 3748void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 3749 struct ieee80211_sta *sta) 3750{ 3751 struct rtw89_txq *rtwtxq, *tmp; 3752 3753 spin_lock_bh(&rtwdev->ba_lock); 3754 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 3755 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3756 3757 if (sta == txq->sta) { 3758 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3759 list_del_init(&rtwtxq->list); 3760 } 3761 } 3762 spin_unlock_bh(&rtwdev->ba_lock); 3763} 3764 3765void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 3766 struct ieee80211_sta *sta) 3767{ 3768 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3769 struct sk_buff *skb; 3770 3771 while ((skb = skb_dequeue(&rtwsta->roc_queue))) 3772 dev_kfree_skb_any(skb); 3773} 3774 3775static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 3776 struct rtw89_txq *rtwtxq) 3777{ 3778 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3779 struct ieee80211_sta *sta = txq->sta; 3780 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 3781 3782 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 3783 return; 3784 3785 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 3786 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 3787 return; 3788 3789 spin_lock_bh(&rtwdev->ba_lock); 3790 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 3791 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 3792 spin_unlock_bh(&rtwdev->ba_lock); 3793 3794 ieee80211_stop_tx_ba_session(sta, txq->tid); 3795 cancel_delayed_work(&rtwdev->forbid_ba_work); 3796 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 3797 RTW89_FORBID_BA_TIMER); 3798} 3799 3800static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 3801 struct rtw89_txq *rtwtxq, 3802 struct sk_buff *skb) 3803{ 3804 struct ieee80211_hw *hw = rtwdev->hw; 3805 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3806 struct ieee80211_sta *sta = txq->sta; 3807 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 3808 3809 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 3810 return; 3811 3812 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 3813 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 3814 return; 3815 } 3816 3817 if (unlikely(!sta)) 3818 return; 3819 3820 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 3821 return; 3822 3823 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 3824 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 3825 return; 3826 } 3827 3828 spin_lock_bh(&rtwdev->ba_lock); 3829 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 3830 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 3831 ieee80211_queue_work(hw, &rtwdev->ba_work); 3832 } 3833 spin_unlock_bh(&rtwdev->ba_lock); 3834} 3835 3836static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 3837 struct rtw89_txq *rtwtxq, 3838 unsigned long frame_cnt, 3839 unsigned long byte_cnt) 3840{ 3841 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3842 struct ieee80211_vif *vif = txq->vif; 3843 struct ieee80211_sta *sta = txq->sta; 3844 struct sk_buff *skb; 3845 unsigned long i; 3846 int ret; 3847 3848 rcu_read_lock(); 3849 for (i = 0; i < frame_cnt; i++) { 3850 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 3851 if (!skb) { 3852 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 3853 goto out; 3854 } 3855 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 3856 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 3857 if (ret) { 3858 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 3859 ieee80211_free_txskb(rtwdev->hw, skb); 3860 break; 3861 } 3862 } 3863out: 3864 rcu_read_unlock(); 3865} 3866 3867static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 3868{ 3869 u8 qsel, ch_dma; 3870 3871 qsel = rtw89_core_get_qsel(rtwdev, tid); 3872 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel); 3873 3874 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 3875} 3876 3877static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 3878 struct ieee80211_txq *txq, 3879 unsigned long *frame_cnt, 3880 bool *sched_txq, bool *reinvoke) 3881{ 3882 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3883 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(txq->sta); 3884 struct rtw89_sta_link *rtwsta_link; 3885 3886 if (!rtwsta) 3887 return false; 3888 3889 rtwsta_link = rtw89_get_designated_link(rtwsta); 3890 if (unlikely(!rtwsta_link)) { 3891 rtw89_err(rtwdev, "agg wait: find no designated link\n"); 3892 return false; 3893 } 3894 3895 if (rtwsta_link->max_agg_wait <= 0) 3896 return false; 3897 3898 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 3899 return false; 3900 3901 if (*frame_cnt > 1) { 3902 *frame_cnt -= 1; 3903 *sched_txq = true; 3904 *reinvoke = true; 3905 rtwtxq->wait_cnt = 1; 3906 return false; 3907 } 3908 3909 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta_link->max_agg_wait) { 3910 *reinvoke = true; 3911 rtwtxq->wait_cnt++; 3912 return true; 3913 } 3914 3915 rtwtxq->wait_cnt = 0; 3916 return false; 3917} 3918 3919static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 3920{ 3921 struct ieee80211_hw *hw = rtwdev->hw; 3922 struct ieee80211_txq *txq; 3923 struct rtw89_vif *rtwvif; 3924 struct rtw89_txq *rtwtxq; 3925 unsigned long frame_cnt; 3926 unsigned long byte_cnt; 3927 u32 tx_resource; 3928 bool sched_txq; 3929 3930 ieee80211_txq_schedule_start(hw, ac); 3931 while ((txq = ieee80211_next_txq(hw, ac))) { 3932 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3933 rtwvif = vif_to_rtwvif(txq->vif); 3934 3935 if (rtwvif->offchan) { 3936 ieee80211_return_txq(hw, txq, true); 3937 continue; 3938 } 3939 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 3940 sched_txq = false; 3941 3942 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 3943 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 3944 ieee80211_return_txq(hw, txq, true); 3945 continue; 3946 } 3947 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 3948 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 3949 ieee80211_return_txq(hw, txq, sched_txq); 3950 if (frame_cnt != 0) 3951 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 3952 3953 /* bound of tx_resource could get stuck due to burst traffic */ 3954 if (frame_cnt == tx_resource) 3955 *reinvoke = true; 3956 } 3957 ieee80211_txq_schedule_end(hw, ac); 3958} 3959 3960static void rtw89_ips_work(struct wiphy *wiphy, struct wiphy_work *work) 3961{ 3962 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 3963 ips_work); 3964 3965 lockdep_assert_wiphy(wiphy); 3966 3967 rtw89_enter_ips_by_hwflags(rtwdev); 3968} 3969 3970static void rtw89_core_txq_work(struct work_struct *w) 3971{ 3972 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 3973 bool reinvoke = false; 3974 u8 ac; 3975 3976 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 3977 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 3978 3979 if (reinvoke) { 3980 /* reinvoke to process the last frame */ 3981 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 3982 } 3983} 3984 3985static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 3986{ 3987 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 3988 txq_reinvoke_work.work); 3989 3990 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 3991} 3992 3993static void rtw89_forbid_ba_work(struct work_struct *w) 3994{ 3995 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 3996 forbid_ba_work.work); 3997 struct rtw89_txq *rtwtxq, *tmp; 3998 3999 spin_lock_bh(&rtwdev->ba_lock); 4000 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 4001 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 4002 list_del_init(&rtwtxq->list); 4003 } 4004 spin_unlock_bh(&rtwdev->ba_lock); 4005} 4006 4007static void rtw89_core_sta_pending_tx_iter(void *data, 4008 struct ieee80211_sta *sta) 4009{ 4010 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 4011 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 4012 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 4013 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4014 struct rtw89_vif_link *target = data; 4015 struct rtw89_vif_link *rtwvif_link; 4016 unsigned int link_id; 4017 struct sk_buff *skb; 4018 int qsel, ret; 4019 4020 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4021 if (rtwvif_link->chanctx_idx == target->chanctx_idx) 4022 goto bottom; 4023 4024 return; 4025 4026bottom: 4027 if (skb_queue_len(&rtwsta->roc_queue) == 0) 4028 return; 4029 4030 while ((skb = skb_dequeue(&rtwsta->roc_queue))) { 4031 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 4032 if (ret) { 4033 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret); 4034 dev_kfree_skb_any(skb); 4035 } else { 4036 rtw89_core_tx_kick_off(rtwdev, qsel); 4037 } 4038 } 4039} 4040 4041static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev, 4042 struct rtw89_vif_link *rtwvif_link) 4043{ 4044 ieee80211_iterate_stations_atomic(rtwdev->hw, 4045 rtw89_core_sta_pending_tx_iter, 4046 rtwvif_link); 4047} 4048 4049int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 4050 bool qos, bool ps, int timeout) 4051{ 4052 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4053 int link_id = ieee80211_vif_is_mld(vif) ? rtwvif_link->link_id : -1; 4054 struct rtw89_sta_link *rtwsta_link; 4055 struct rtw89_tx_wait_info *wait; 4056 struct ieee80211_sta *sta; 4057 struct ieee80211_hdr *hdr; 4058 struct rtw89_sta *rtwsta; 4059 struct sk_buff *skb; 4060 int ret, qsel; 4061 4062 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 4063 return 0; 4064 4065 wait = kzalloc(sizeof(*wait), GFP_KERNEL); 4066 if (!wait) 4067 return -ENOMEM; 4068 4069 init_completion(&wait->completion); 4070 4071 rcu_read_lock(); 4072 sta = ieee80211_find_sta(vif, vif->cfg.ap_addr); 4073 if (!sta) { 4074 ret = -EINVAL; 4075 goto out; 4076 } 4077 rtwsta = sta_to_rtwsta(sta); 4078 4079 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, link_id, qos); 4080 if (!skb) { 4081 ret = -ENOMEM; 4082 goto out; 4083 } 4084 4085 wait->skb = skb; 4086 4087 hdr = (struct ieee80211_hdr *)skb->data; 4088 if (ps) 4089 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 4090 4091 rtwsta_link = rtwsta->links[rtwvif_link->link_id]; 4092 if (unlikely(!rtwsta_link)) { 4093 ret = -ENOLINK; 4094 dev_kfree_skb_any(skb); 4095 goto out; 4096 } 4097 4098 ret = rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, &qsel, true, 4099 wait); 4100 if (ret) { 4101 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret); 4102 dev_kfree_skb_any(skb); 4103 goto out; 4104 } 4105 4106 rcu_read_unlock(); 4107 4108 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, wait, qsel, 4109 timeout); 4110out: 4111 rcu_read_unlock(); 4112 kfree(wait); 4113 4114 return ret; 4115} 4116 4117void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4118{ 4119 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4120 struct rtw89_chanctx_pause_parm pause_parm = { 4121 .rsn = RTW89_CHANCTX_PAUSE_REASON_ROC, 4122 }; 4123 struct ieee80211_hw *hw = rtwdev->hw; 4124 struct rtw89_roc *roc = &rtwvif->roc; 4125 struct rtw89_vif_link *rtwvif_link; 4126 struct cfg80211_chan_def roc_chan; 4127 struct rtw89_vif *tmp_vif; 4128 u32 reg; 4129 int ret; 4130 4131 lockdep_assert_wiphy(hw->wiphy); 4132 4133 rtw89_leave_ips_by_hwflags(rtwdev); 4134 rtw89_leave_lps(rtwdev); 4135 4136 rtwvif_link = rtw89_get_designated_link(rtwvif); 4137 if (unlikely(!rtwvif_link)) { 4138 rtw89_err(rtwdev, "roc start: find no designated link\n"); 4139 return; 4140 } 4141 4142 roc->link_id = rtwvif_link->link_id; 4143 4144 pause_parm.trigger = rtwvif_link; 4145 rtw89_chanctx_pause(rtwdev, &pause_parm); 4146 4147 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, true, 4148 RTW89_ROC_TX_TIMEOUT); 4149 if (ret) 4150 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 4151 "roc send null-1 failed: %d\n", ret); 4152 4153 rtw89_for_each_rtwvif(rtwdev, tmp_vif) { 4154 struct rtw89_vif_link *tmp_link; 4155 unsigned int link_id; 4156 4157 rtw89_vif_for_each_link(tmp_vif, tmp_link, link_id) { 4158 if (tmp_link->chanctx_idx == rtwvif_link->chanctx_idx) { 4159 tmp_vif->offchan = true; 4160 break; 4161 } 4162 } 4163 } 4164 4165 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT); 4166 rtw89_config_roc_chandef(rtwdev, rtwvif_link, &roc_chan); 4167 rtw89_set_channel(rtwdev); 4168 4169 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx); 4170 rtw89_write32_clr(rtwdev, reg, B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH); 4171 4172 ieee80211_ready_on_channel(hw); 4173 wiphy_delayed_work_cancel(hw->wiphy, &rtwvif->roc.roc_work); 4174 wiphy_delayed_work_queue(hw->wiphy, &rtwvif->roc.roc_work, 4175 msecs_to_jiffies(rtwvif->roc.duration)); 4176} 4177 4178void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4179{ 4180 struct ieee80211_hw *hw = rtwdev->hw; 4181 struct rtw89_roc *roc = &rtwvif->roc; 4182 struct rtw89_vif_link *rtwvif_link; 4183 struct rtw89_vif *tmp_vif; 4184 int ret; 4185 4186 lockdep_assert_wiphy(hw->wiphy); 4187 4188 ieee80211_remain_on_channel_expired(hw); 4189 4190 rtw89_leave_ips_by_hwflags(rtwdev); 4191 rtw89_leave_lps(rtwdev); 4192 4193 rtwvif_link = rtwvif->links[roc->link_id]; 4194 if (unlikely(!rtwvif_link)) { 4195 rtw89_err(rtwdev, "roc end: find no link (link id %u)\n", 4196 roc->link_id); 4197 return; 4198 } 4199 4200 rtw89_mac_set_rx_fltr(rtwdev, rtwvif_link->mac_idx, rtwdev->hal.rx_fltr); 4201 4202 roc->state = RTW89_ROC_IDLE; 4203 rtw89_config_roc_chandef(rtwdev, rtwvif_link, NULL); 4204 rtw89_chanctx_proceed(rtwdev, NULL); 4205 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, false, 4206 RTW89_ROC_TX_TIMEOUT); 4207 if (ret) 4208 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 4209 "roc send null-0 failed: %d\n", ret); 4210 4211 rtw89_for_each_rtwvif(rtwdev, tmp_vif) 4212 tmp_vif->offchan = false; 4213 4214 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif_link); 4215 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 4216 4217 if (hw->conf.flags & IEEE80211_CONF_IDLE) 4218 wiphy_delayed_work_queue(hw->wiphy, &roc->roc_work, 4219 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT)); 4220} 4221 4222void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work) 4223{ 4224 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 4225 roc.roc_work.work); 4226 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 4227 struct rtw89_roc *roc = &rtwvif->roc; 4228 4229 lockdep_assert_wiphy(wiphy); 4230 4231 switch (roc->state) { 4232 case RTW89_ROC_IDLE: 4233 rtw89_enter_ips_by_hwflags(rtwdev); 4234 break; 4235 case RTW89_ROC_MGMT: 4236 case RTW89_ROC_NORMAL: 4237 rtw89_roc_end(rtwdev, rtwvif); 4238 break; 4239 default: 4240 break; 4241 } 4242} 4243 4244static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 4245 u32 throughput, u64 cnt, 4246 enum rtw89_tfc_interval interval) 4247{ 4248 u64 cnt_level; 4249 4250 switch (interval) { 4251 default: 4252 case RTW89_TFC_INTERVAL_100MS: 4253 cnt_level = 5; 4254 break; 4255 case RTW89_TFC_INTERVAL_2SEC: 4256 cnt_level = 100; 4257 break; 4258 } 4259 4260 if (cnt < cnt_level) 4261 return RTW89_TFC_IDLE; 4262 if (throughput > 50) 4263 return RTW89_TFC_HIGH; 4264 if (throughput > 10) 4265 return RTW89_TFC_MID; 4266 if (throughput > 2) 4267 return RTW89_TFC_LOW; 4268 return RTW89_TFC_ULTRA_LOW; 4269} 4270 4271static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 4272 struct rtw89_traffic_stats *stats, 4273 enum rtw89_tfc_interval interval) 4274{ 4275 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 4276 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 4277 4278 stats->tx_throughput_raw = rtw89_bytes_to_mbps(stats->tx_unicast, interval); 4279 stats->rx_throughput_raw = rtw89_bytes_to_mbps(stats->rx_unicast, interval); 4280 4281 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 4282 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 4283 4284 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 4285 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 4286 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 4287 stats->tx_cnt, interval); 4288 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 4289 stats->rx_cnt, interval); 4290 stats->tx_avg_len = stats->tx_cnt ? 4291 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 4292 stats->rx_avg_len = stats->rx_cnt ? 4293 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 4294 4295 stats->tx_unicast = 0; 4296 stats->rx_unicast = 0; 4297 stats->tx_cnt = 0; 4298 stats->rx_cnt = 0; 4299 stats->rx_tf_periodic = stats->rx_tf_acc; 4300 stats->rx_tf_acc = 0; 4301 4302 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 4303 return true; 4304 4305 return false; 4306} 4307 4308static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 4309{ 4310 struct rtw89_vif_link *rtwvif_link; 4311 struct rtw89_vif *rtwvif; 4312 unsigned int link_id; 4313 bool tfc_changed; 4314 4315 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats, 4316 RTW89_TFC_INTERVAL_2SEC); 4317 4318 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4319 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats, 4320 RTW89_TFC_INTERVAL_2SEC); 4321 4322 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4323 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif_link); 4324 } 4325 4326 return tfc_changed; 4327} 4328 4329static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 4330{ 4331 struct ieee80211_vif *vif; 4332 struct rtw89_vif *rtwvif; 4333 4334 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4335 if (rtwvif->tdls_peer) 4336 continue; 4337 if (rtwvif->offchan) 4338 continue; 4339 4340 if (rtwvif->stats_ps.tx_tfc_lv >= RTW89_TFC_MID || 4341 rtwvif->stats_ps.rx_tfc_lv >= RTW89_TFC_MID) 4342 continue; 4343 4344 vif = rtwvif_to_vif(rtwvif); 4345 4346 if (!(vif->type == NL80211_IFTYPE_STATION || 4347 vif->type == NL80211_IFTYPE_P2P_CLIENT)) 4348 continue; 4349 4350 if (!rtw89_core_bcn_track_can_lps(rtwdev)) 4351 continue; 4352 4353 rtw89_enter_lps(rtwdev, rtwvif, true); 4354 } 4355} 4356 4357static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev) 4358{ 4359 enum rtw89_entity_mode mode; 4360 4361 mode = rtw89_get_entity_mode(rtwdev); 4362 if (mode == RTW89_ENTITY_MODE_MCC) 4363 return; 4364 4365 rtw89_chip_rfk_track(rtwdev); 4366} 4367 4368void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 4369 struct rtw89_vif_link *rtwvif_link, 4370 struct ieee80211_bss_conf *bss_conf) 4371{ 4372 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev); 4373 4374 if (mode == RTW89_ENTITY_MODE_MCC) 4375 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE); 4376 else 4377 rtw89_process_p2p_ps(rtwdev, rtwvif_link, bss_conf); 4378} 4379 4380void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 4381 struct rtw89_traffic_stats *stats) 4382{ 4383 stats->tx_unicast = 0; 4384 stats->rx_unicast = 0; 4385 stats->tx_cnt = 0; 4386 stats->rx_cnt = 0; 4387 ewma_tp_init(&stats->tx_ewma_tp); 4388 ewma_tp_init(&stats->rx_ewma_tp); 4389} 4390 4391#define RTW89_MLSR_GOTO_2GHZ_THRESHOLD -53 4392#define RTW89_MLSR_EXIT_2GHZ_THRESHOLD -38 4393static void rtw89_core_mlsr_link_decision(struct rtw89_dev *rtwdev, 4394 struct rtw89_vif *rtwvif) 4395{ 4396 unsigned int sel_link_id = IEEE80211_MLD_MAX_NUM_LINKS; 4397 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4398 struct rtw89_vif_link *rtwvif_link; 4399 const struct rtw89_chan *chan; 4400 unsigned long usable_links; 4401 unsigned int link_id; 4402 u8 decided_bands; 4403 u8 rssi; 4404 4405 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi); 4406 if (unlikely(!rssi)) 4407 return; 4408 4409 if (RTW89_RSSI_RAW_TO_DBM(rssi) >= RTW89_MLSR_EXIT_2GHZ_THRESHOLD) 4410 decided_bands = BIT(RTW89_BAND_5G) | BIT(RTW89_BAND_6G); 4411 else if (RTW89_RSSI_RAW_TO_DBM(rssi) <= RTW89_MLSR_GOTO_2GHZ_THRESHOLD) 4412 decided_bands = BIT(RTW89_BAND_2G); 4413 else 4414 return; 4415 4416 usable_links = ieee80211_vif_usable_links(vif); 4417 4418 rtwvif_link = rtw89_get_designated_link(rtwvif); 4419 if (unlikely(!rtwvif_link)) 4420 goto select; 4421 4422 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 4423 if (decided_bands & BIT(chan->band_type)) 4424 return; 4425 4426 usable_links &= ~BIT(rtwvif_link->link_id); 4427 4428select: 4429 rcu_read_lock(); 4430 4431 for_each_set_bit(link_id, &usable_links, IEEE80211_MLD_MAX_NUM_LINKS) { 4432 struct ieee80211_bss_conf *link_conf; 4433 struct ieee80211_channel *channel; 4434 enum rtw89_band band; 4435 4436 link_conf = rcu_dereference(vif->link_conf[link_id]); 4437 if (unlikely(!link_conf)) 4438 continue; 4439 4440 channel = link_conf->chanreq.oper.chan; 4441 if (unlikely(!channel)) 4442 continue; 4443 4444 band = rtw89_nl80211_to_hw_band(channel->band); 4445 if (decided_bands & BIT(band)) { 4446 sel_link_id = link_id; 4447 break; 4448 } 4449 } 4450 4451 rcu_read_unlock(); 4452 4453 if (sel_link_id == IEEE80211_MLD_MAX_NUM_LINKS) 4454 return; 4455 4456 rtw89_core_mlsr_switch(rtwdev, rtwvif, sel_link_id); 4457} 4458 4459static void rtw89_core_mlo_track(struct rtw89_dev *rtwdev) 4460{ 4461 struct rtw89_hal *hal = &rtwdev->hal; 4462 struct ieee80211_vif *vif; 4463 struct rtw89_vif *rtwvif; 4464 4465 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_MLO)) 4466 return; 4467 4468 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4469 vif = rtwvif_to_vif(rtwvif); 4470 if (!vif->cfg.assoc || !ieee80211_vif_is_mld(vif)) 4471 continue; 4472 4473 switch (rtwvif->mlo_mode) { 4474 case RTW89_MLO_MODE_MLSR: 4475 rtw89_core_mlsr_link_decision(rtwdev, rtwvif); 4476 break; 4477 default: 4478 break; 4479 } 4480 } 4481} 4482 4483static void rtw89_track_ps_work(struct wiphy *wiphy, struct wiphy_work *work) 4484{ 4485 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 4486 track_ps_work.work); 4487 struct rtw89_vif *rtwvif; 4488 4489 lockdep_assert_wiphy(wiphy); 4490 4491 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WORK, rtwdev->flags)) 4492 return; 4493 4494 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 4495 return; 4496 4497 wiphy_delayed_work_queue(wiphy, &rtwdev->track_ps_work, 4498 RTW89_TRACK_PS_WORK_PERIOD); 4499 4500 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4501 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats_ps, 4502 RTW89_TFC_INTERVAL_100MS); 4503 4504 if (rtwdev->scanning) 4505 return; 4506 4507 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 4508 rtw89_enter_lps_track(rtwdev); 4509} 4510 4511static void rtw89_track_work(struct wiphy *wiphy, struct wiphy_work *work) 4512{ 4513 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 4514 track_work.work); 4515 bool tfc_changed; 4516 4517 lockdep_assert_wiphy(wiphy); 4518 4519 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WORK, rtwdev->flags)) 4520 return; 4521 4522 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 4523 return; 4524 4525 wiphy_delayed_work_queue(wiphy, &rtwdev->track_work, 4526 RTW89_TRACK_WORK_PERIOD); 4527 4528 tfc_changed = rtw89_traffic_stats_track(rtwdev); 4529 if (rtwdev->scanning) 4530 return; 4531 4532 rtw89_leave_lps(rtwdev); 4533 4534 if (tfc_changed) { 4535 rtw89_hci_recalc_int_mit(rtwdev); 4536 rtw89_btc_ntfy_wl_sta(rtwdev); 4537 } 4538 rtw89_mac_bf_monitor_track(rtwdev); 4539 rtw89_core_bcn_track(rtwdev); 4540 rtw89_phy_stat_track(rtwdev); 4541 rtw89_phy_env_monitor_track(rtwdev); 4542 rtw89_phy_dig(rtwdev); 4543 rtw89_core_rfk_track(rtwdev); 4544 rtw89_phy_ra_update(rtwdev); 4545 rtw89_phy_cfo_track(rtwdev); 4546 rtw89_phy_tx_path_div_track(rtwdev); 4547 rtw89_phy_antdiv_track(rtwdev); 4548 rtw89_phy_ul_tb_ctrl_track(rtwdev); 4549 rtw89_phy_edcca_track(rtwdev); 4550 rtw89_sar_track(rtwdev); 4551 rtw89_chanctx_track(rtwdev); 4552 rtw89_core_rfkill_poll(rtwdev, false); 4553 rtw89_core_mlo_track(rtwdev); 4554 4555 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 4556 rtw89_enter_lps_track(rtwdev); 4557} 4558 4559u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 4560{ 4561 unsigned long bit; 4562 4563 bit = find_first_zero_bit(addr, size); 4564 if (bit < size) 4565 set_bit(bit, addr); 4566 4567 return bit; 4568} 4569 4570void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 4571{ 4572 clear_bit(bit, addr); 4573} 4574 4575void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 4576{ 4577 bitmap_zero(addr, nbits); 4578} 4579 4580int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 4581 struct rtw89_sta_link *rtwsta_link, u8 tid, 4582 u8 *cam_idx) 4583{ 4584 const struct rtw89_chip_info *chip = rtwdev->chip; 4585 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 4586 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 4587 u8 idx; 4588 int i; 4589 4590 lockdep_assert_wiphy(rtwdev->hw->wiphy); 4591 4592 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 4593 if (idx == chip->bacam_num) { 4594 /* allocate a static BA CAM to tid=0/5, so replace the existing 4595 * one if BA CAM is full. Hardware will process the original tid 4596 * automatically. 4597 */ 4598 if (tid != 0 && tid != 5) 4599 return -ENOSPC; 4600 4601 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 4602 tmp = &cam_info->ba_cam_entry[i]; 4603 if (tmp->tid == 0 || tmp->tid == 5) 4604 continue; 4605 4606 idx = i; 4607 entry = tmp; 4608 list_del(&entry->list); 4609 break; 4610 } 4611 4612 if (!entry) 4613 return -ENOSPC; 4614 } else { 4615 entry = &cam_info->ba_cam_entry[idx]; 4616 } 4617 4618 entry->tid = tid; 4619 list_add_tail(&entry->list, &rtwsta_link->ba_cam_list); 4620 4621 *cam_idx = idx; 4622 4623 return 0; 4624} 4625 4626int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 4627 struct rtw89_sta_link *rtwsta_link, u8 tid, 4628 u8 *cam_idx) 4629{ 4630 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 4631 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 4632 u8 idx; 4633 4634 lockdep_assert_wiphy(rtwdev->hw->wiphy); 4635 4636 list_for_each_entry_safe(entry, tmp, &rtwsta_link->ba_cam_list, list) { 4637 if (entry->tid != tid) 4638 continue; 4639 4640 idx = entry - cam_info->ba_cam_entry; 4641 list_del(&entry->list); 4642 4643 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 4644 *cam_idx = idx; 4645 return 0; 4646 } 4647 4648 return -ENOENT; 4649} 4650 4651#define RTW89_TYPE_MAPPING(_type) \ 4652 case NL80211_IFTYPE_ ## _type: \ 4653 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 4654 break 4655void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc) 4656{ 4657 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4658 const struct ieee80211_bss_conf *bss_conf; 4659 4660 switch (vif->type) { 4661 case NL80211_IFTYPE_STATION: 4662 if (vif->p2p) 4663 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT; 4664 else 4665 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_STATION; 4666 break; 4667 case NL80211_IFTYPE_AP: 4668 if (vif->p2p) 4669 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_GO; 4670 else 4671 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_AP; 4672 break; 4673 RTW89_TYPE_MAPPING(ADHOC); 4674 RTW89_TYPE_MAPPING(MONITOR); 4675 RTW89_TYPE_MAPPING(MESH_POINT); 4676 default: 4677 WARN_ON(1); 4678 break; 4679 } 4680 4681 switch (vif->type) { 4682 case NL80211_IFTYPE_AP: 4683 case NL80211_IFTYPE_MESH_POINT: 4684 rtwvif_link->net_type = RTW89_NET_TYPE_AP_MODE; 4685 rtwvif_link->self_role = RTW89_SELF_ROLE_AP; 4686 break; 4687 case NL80211_IFTYPE_ADHOC: 4688 rtwvif_link->net_type = RTW89_NET_TYPE_AD_HOC; 4689 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT; 4690 break; 4691 case NL80211_IFTYPE_STATION: 4692 if (assoc) { 4693 rtwvif_link->net_type = RTW89_NET_TYPE_INFRA; 4694 4695 rcu_read_lock(); 4696 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 4697 rtwvif_link->trigger = bss_conf->he_support; 4698 rcu_read_unlock(); 4699 } else { 4700 rtwvif_link->net_type = RTW89_NET_TYPE_NO_LINK; 4701 rtwvif_link->trigger = false; 4702 } 4703 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT; 4704 rtwvif_link->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 4705 break; 4706 case NL80211_IFTYPE_MONITOR: 4707 break; 4708 default: 4709 WARN_ON(1); 4710 break; 4711 } 4712} 4713 4714int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 4715 struct rtw89_vif_link *rtwvif_link, 4716 struct rtw89_sta_link *rtwsta_link) 4717{ 4718 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4719 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 4720 struct rtw89_hal *hal = &rtwdev->hal; 4721 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 4722 int i; 4723 int ret; 4724 4725 rtwsta_link->prev_rssi = 0; 4726 INIT_LIST_HEAD(&rtwsta_link->ba_cam_list); 4727 ewma_rssi_init(&rtwsta_link->avg_rssi); 4728 ewma_snr_init(&rtwsta_link->avg_snr); 4729 ewma_evm_init(&rtwsta_link->evm_1ss); 4730 for (i = 0; i < ant_num; i++) { 4731 ewma_rssi_init(&rtwsta_link->rssi[i]); 4732 ewma_evm_init(&rtwsta_link->evm_min[i]); 4733 ewma_evm_init(&rtwsta_link->evm_max[i]); 4734 } 4735 4736 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 4737 /* must do rtw89_reg_6ghz_recalc() before rfk channel */ 4738 ret = rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, true); 4739 if (ret) 4740 return ret; 4741 4742 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 4743 BTC_ROLE_MSTS_STA_CONN_START); 4744 rtw89_chip_rfk_channel(rtwdev, rtwvif_link); 4745 4746 if (vif->p2p) { 4747 rtw89_mac_get_tx_retry_limit(rtwdev, rtwsta_link, 4748 &rtwsta_link->tx_retry); 4749 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false, 60); 4750 } 4751 rtw89_phy_dig_suspend(rtwdev); 4752 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 4753 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta_link->mac_id, false); 4754 if (ret) { 4755 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 4756 return ret; 4757 } 4758 4759 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link, 4760 RTW89_ROLE_CREATE); 4761 if (ret) { 4762 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 4763 return ret; 4764 } 4765 4766 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 4767 if (ret) 4768 return ret; 4769 4770 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 4771 if (ret) 4772 return ret; 4773 } 4774 4775 return 0; 4776} 4777 4778int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 4779 struct rtw89_vif_link *rtwvif_link, 4780 struct rtw89_sta_link *rtwsta_link) 4781{ 4782 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4783 4784 rtw89_assoc_link_clr(rtwsta_link); 4785 4786 if (vif->type == NL80211_IFTYPE_STATION) { 4787 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, false); 4788 rtw89_core_bcn_track_reset(rtwdev); 4789 } 4790 4791 if (rtwvif_link->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT) 4792 rtw89_p2p_noa_once_deinit(rtwvif_link); 4793 4794 return 0; 4795} 4796 4797int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 4798 struct rtw89_vif_link *rtwvif_link, 4799 struct rtw89_sta_link *rtwsta_link) 4800{ 4801 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4802 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 4803 int ret; 4804 4805 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, true); 4806 rtw89_mac_bf_disassoc(rtwdev, rtwvif_link, rtwsta_link); 4807 4808 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 4809 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta_link->addr_cam); 4810 if (sta->tdls) 4811 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta_link->bssid_cam); 4812 4813 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 4814 rtw89_vif_type_mapping(rtwvif_link, false); 4815 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif_link, true); 4816 } 4817 4818 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 4819 if (ret) { 4820 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 4821 return ret; 4822 } 4823 4824 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, true); 4825 if (ret) { 4826 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 4827 return ret; 4828 } 4829 4830 /* update cam aid mac_id net_type */ 4831 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL, 4832 RTW89_ROLE_CON_DISCONN); 4833 if (ret) { 4834 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 4835 return ret; 4836 } 4837 4838 return ret; 4839} 4840 4841static bool rtw89_sta_link_can_er(struct rtw89_dev *rtwdev, 4842 struct ieee80211_bss_conf *bss_conf, 4843 struct ieee80211_link_sta *link_sta) 4844{ 4845 if (!bss_conf->he_support || 4846 bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE) 4847 return false; 4848 4849 if (rtwdev->chip->chip_id == RTL8852C && 4850 rtw89_sta_link_has_su_mu_4xhe08(link_sta) && 4851 !rtw89_sta_link_has_er_su_4xhe08(link_sta)) 4852 return false; 4853 4854 return true; 4855} 4856 4857int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 4858 struct rtw89_vif_link *rtwvif_link, 4859 struct rtw89_sta_link *rtwsta_link) 4860{ 4861 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4862 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 4863 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif_link, 4864 rtwsta_link); 4865 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 4866 rtwvif_link->chanctx_idx); 4867 struct ieee80211_link_sta *link_sta; 4868 int ret; 4869 4870 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 4871 if (sta->tdls) { 4872 rcu_read_lock(); 4873 4874 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 4875 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif_link, bssid_cam, 4876 link_sta->addr); 4877 if (ret) { 4878 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 4879 rcu_read_unlock(); 4880 return ret; 4881 } 4882 4883 rcu_read_unlock(); 4884 } 4885 4886 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta_link->addr_cam, bssid_cam); 4887 if (ret) { 4888 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 4889 return ret; 4890 } 4891 } 4892 4893 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 4894 if (ret) { 4895 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 4896 return ret; 4897 } 4898 4899 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, false); 4900 if (ret) { 4901 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 4902 return ret; 4903 } 4904 4905 /* update cam aid mac_id net_type */ 4906 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL, 4907 RTW89_ROLE_CON_DISCONN); 4908 if (ret) { 4909 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 4910 return ret; 4911 } 4912 4913 rtw89_phy_ra_assoc(rtwdev, rtwsta_link); 4914 rtw89_mac_bf_assoc(rtwdev, rtwvif_link, rtwsta_link); 4915 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, false); 4916 4917 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 4918 struct ieee80211_bss_conf *bss_conf; 4919 4920 rcu_read_lock(); 4921 4922 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4923 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 4924 rtwsta_link->er_cap = rtw89_sta_link_can_er(rtwdev, bss_conf, link_sta); 4925 4926 rcu_read_unlock(); 4927 4928 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 4929 BTC_ROLE_MSTS_STA_CONN_END); 4930 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta_link->htc_template, chan); 4931 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif_link); 4932 rtw89_core_bcn_track_assoc(rtwdev, rtwvif_link); 4933 4934 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif_link, rtwsta_link->mac_id); 4935 if (ret) { 4936 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 4937 return ret; 4938 } 4939 4940 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true); 4941 4942 if (vif->p2p) 4943 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false, 4944 rtwsta_link->tx_retry); 4945 rtw89_phy_dig_resume(rtwdev, false); 4946 } 4947 4948 rtw89_assoc_link_set(rtwsta_link); 4949 return ret; 4950} 4951 4952int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 4953 struct rtw89_vif_link *rtwvif_link, 4954 struct rtw89_sta_link *rtwsta_link) 4955{ 4956 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4957 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 4958 int ret; 4959 4960 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 4961 rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, false); 4962 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 4963 BTC_ROLE_MSTS_STA_DIS_CONN); 4964 4965 if (vif->p2p) 4966 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false, 4967 rtwsta_link->tx_retry); 4968 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 4969 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link, 4970 RTW89_ROLE_REMOVE); 4971 if (ret) { 4972 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 4973 return ret; 4974 } 4975 } 4976 4977 return 0; 4978} 4979 4980static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 4981 struct ieee80211_sta *sta, 4982 struct cfg80211_tid_cfg *tid_conf) 4983{ 4984 struct ieee80211_txq *txq; 4985 struct rtw89_txq *rtwtxq; 4986 u32 mask = tid_conf->mask; 4987 u8 tids = tid_conf->tids; 4988 int tids_nbit = BITS_PER_BYTE; 4989 int i; 4990 4991 for (i = 0; i < tids_nbit; i++, tids >>= 1) { 4992 if (!tids) 4993 break; 4994 4995 if (!(tids & BIT(0))) 4996 continue; 4997 4998 txq = sta->txq[i]; 4999 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 5000 5001 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) { 5002 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) { 5003 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 5004 } else { 5005 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) 5006 ieee80211_stop_tx_ba_session(sta, txq->tid); 5007 spin_lock_bh(&rtwdev->ba_lock); 5008 list_del_init(&rtwtxq->list); 5009 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 5010 spin_unlock_bh(&rtwdev->ba_lock); 5011 } 5012 } 5013 5014 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) { 5015 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE) 5016 sta->max_amsdu_subframes = 0; 5017 else 5018 sta->max_amsdu_subframes = 1; 5019 } 5020 } 5021} 5022 5023void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 5024 struct ieee80211_sta *sta, 5025 struct cfg80211_tid_config *tid_config) 5026{ 5027 int i; 5028 5029 for (i = 0; i < tid_config->n_tid_conf; i++) 5030 _rtw89_core_set_tid_config(rtwdev, sta, 5031 &tid_config->tid_conf[i]); 5032} 5033 5034static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 5035 struct ieee80211_sta_ht_cap *ht_cap) 5036{ 5037 static const __le16 highest[RF_PATH_MAX] = { 5038 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 5039 }; 5040 struct rtw89_hal *hal = &rtwdev->hal; 5041 u8 nss = hal->rx_nss; 5042 int i; 5043 5044 ht_cap->ht_supported = true; 5045 ht_cap->cap = 0; 5046 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 5047 IEEE80211_HT_CAP_MAX_AMSDU | 5048 IEEE80211_HT_CAP_TX_STBC | 5049 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 5050 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 5051 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 5052 IEEE80211_HT_CAP_DSSSCCK40 | 5053 IEEE80211_HT_CAP_SGI_40; 5054 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 5055 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 5056 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 5057 for (i = 0; i < nss; i++) 5058 ht_cap->mcs.rx_mask[i] = 0xFF; 5059 ht_cap->mcs.rx_mask[4] = 0x01; 5060 ht_cap->mcs.rx_highest = highest[nss - 1]; 5061} 5062 5063static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 5064 struct ieee80211_sta_vht_cap *vht_cap) 5065{ 5066 static const __le16 highest_bw80[RF_PATH_MAX] = { 5067 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 5068 }; 5069 static const __le16 highest_bw160[RF_PATH_MAX] = { 5070 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 5071 }; 5072 const struct rtw89_chip_info *chip = rtwdev->chip; 5073 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ? 5074 highest_bw160 : highest_bw80; 5075 struct rtw89_hal *hal = &rtwdev->hal; 5076 u16 tx_mcs_map = 0, rx_mcs_map = 0; 5077 u8 sts_cap = 3; 5078 int i; 5079 5080 for (i = 0; i < 8; i++) { 5081 if (i < hal->tx_nss) 5082 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 5083 else 5084 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 5085 if (i < hal->rx_nss) 5086 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 5087 else 5088 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 5089 } 5090 5091 vht_cap->vht_supported = true; 5092 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 5093 IEEE80211_VHT_CAP_SHORT_GI_80 | 5094 IEEE80211_VHT_CAP_RXSTBC_1 | 5095 IEEE80211_VHT_CAP_HTC_VHT | 5096 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 5097 0; 5098 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 5099 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 5100 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 5101 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 5102 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 5103 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 5104 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 5105 IEEE80211_VHT_CAP_SHORT_GI_160; 5106 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 5107 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 5108 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 5109 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 5110 5111 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW)) 5112 vht_cap->vht_mcs.tx_highest |= 5113 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 5114} 5115 5116static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 5117 enum nl80211_band band, 5118 enum nl80211_iftype iftype, 5119 struct ieee80211_sband_iftype_data *iftype_data) 5120{ 5121 const struct rtw89_chip_info *chip = rtwdev->chip; 5122 struct rtw89_hal *hal = &rtwdev->hal; 5123 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 5124 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 5125 struct ieee80211_sta_he_cap *he_cap; 5126 int nss = hal->rx_nss; 5127 u8 *mac_cap_info; 5128 u8 *phy_cap_info; 5129 u16 mcs_map = 0; 5130 int i; 5131 5132 for (i = 0; i < 8; i++) { 5133 if (i < nss) 5134 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 5135 else 5136 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 5137 } 5138 5139 he_cap = &iftype_data->he_cap; 5140 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 5141 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 5142 5143 he_cap->has_he = true; 5144 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 5145 if (iftype == NL80211_IFTYPE_STATION) 5146 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 5147 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 5148 IEEE80211_HE_MAC_CAP2_BSR; 5149 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 5150 if (iftype == NL80211_IFTYPE_AP) 5151 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 5152 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 5153 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 5154 if (iftype == NL80211_IFTYPE_STATION) 5155 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 5156 if (band == NL80211_BAND_2GHZ) { 5157 phy_cap_info[0] = 5158 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 5159 } else { 5160 phy_cap_info[0] = 5161 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 5162 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 5163 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 5164 } 5165 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 5166 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 5167 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 5168 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 5169 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 5170 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 5171 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 5172 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 5173 if (iftype == NL80211_IFTYPE_STATION) 5174 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 5175 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 5176 if (iftype == NL80211_IFTYPE_AP) 5177 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 5178 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 5179 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 5180 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 5181 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 5182 phy_cap_info[5] = no_ng16 ? 0 : 5183 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 5184 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 5185 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 5186 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 5187 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 5188 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 5189 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 5190 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 5191 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 5192 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 5193 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 5194 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 5195 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 5196 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 5197 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 5198 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 5199 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 5200 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 5201 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 5202 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 5203 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 5204 if (iftype == NL80211_IFTYPE_STATION) 5205 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 5206 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 5207 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 5208 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) { 5209 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 5210 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 5211 } 5212 5213 if (band == NL80211_BAND_6GHZ) { 5214 __le16 capa; 5215 5216 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 5217 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 5218 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 5219 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 5220 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 5221 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 5222 iftype_data->he_6ghz_capa.capa = capa; 5223 } 5224} 5225 5226static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev, 5227 enum nl80211_band band, 5228 enum nl80211_iftype iftype, 5229 struct ieee80211_sband_iftype_data *iftype_data) 5230{ 5231 const struct rtw89_chip_info *chip = rtwdev->chip; 5232 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem; 5233 struct ieee80211_eht_mcs_nss_supp *eht_nss; 5234 struct ieee80211_sta_eht_cap *eht_cap; 5235 struct rtw89_hal *hal = &rtwdev->hal; 5236 bool support_mcs_12_13 = true; 5237 bool support_320mhz = false; 5238 u8 val, val_mcs13; 5239 int sts = 8; 5240 5241 if (chip->chip_gen == RTW89_CHIP_AX || hal->no_eht) 5242 return; 5243 5244 if (hal->no_mcs_12_13) 5245 support_mcs_12_13 = false; 5246 5247 if (band == NL80211_BAND_6GHZ && 5248 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320)) 5249 support_320mhz = true; 5250 5251 eht_cap = &iftype_data->eht_cap; 5252 eht_cap_elem = &eht_cap->eht_cap_elem; 5253 eht_nss = &eht_cap->eht_mcs_nss_supp; 5254 5255 eht_cap->has_eht = true; 5256 5257 eht_cap_elem->mac_cap_info[0] = 5258 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991, 5259 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 5260 eht_cap_elem->mac_cap_info[1] = 0; 5261 5262 eht_cap_elem->phy_cap_info[0] = 5263 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 5264 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 5265 if (support_320mhz) 5266 eht_cap_elem->phy_cap_info[0] |= 5267 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 5268 5269 eht_cap_elem->phy_cap_info[0] |= 5270 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)), 5271 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 5272 eht_cap_elem->phy_cap_info[1] = 5273 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)), 5274 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) | 5275 u8_encode_bits(sts - 1, 5276 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 5277 if (support_320mhz) 5278 eht_cap_elem->phy_cap_info[1] |= 5279 u8_encode_bits(sts - 1, 5280 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 5281 5282 eht_cap_elem->phy_cap_info[2] = 0; 5283 5284 eht_cap_elem->phy_cap_info[3] = 5285 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 5286 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 5287 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 5288 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; 5289 5290 eht_cap_elem->phy_cap_info[4] = 5291 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP | 5292 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 5293 5294 eht_cap_elem->phy_cap_info[5] = 5295 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US, 5296 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK); 5297 5298 eht_cap_elem->phy_cap_info[6] = 0; 5299 eht_cap_elem->phy_cap_info[7] = 0; 5300 eht_cap_elem->phy_cap_info[8] = 0; 5301 5302 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) | 5303 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX); 5304 val_mcs13 = support_mcs_12_13 ? val : 0; 5305 5306 eht_nss->bw._80.rx_tx_mcs9_max_nss = val; 5307 eht_nss->bw._80.rx_tx_mcs11_max_nss = val; 5308 eht_nss->bw._80.rx_tx_mcs13_max_nss = val_mcs13; 5309 eht_nss->bw._160.rx_tx_mcs9_max_nss = val; 5310 eht_nss->bw._160.rx_tx_mcs11_max_nss = val; 5311 eht_nss->bw._160.rx_tx_mcs13_max_nss = val_mcs13; 5312 if (support_320mhz) { 5313 eht_nss->bw._320.rx_tx_mcs9_max_nss = val; 5314 eht_nss->bw._320.rx_tx_mcs11_max_nss = val; 5315 eht_nss->bw._320.rx_tx_mcs13_max_nss = val_mcs13; 5316 } 5317} 5318 5319#define RTW89_SBAND_IFTYPES_NR 2 5320 5321static int rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev, 5322 enum nl80211_band band, 5323 struct ieee80211_supported_band *sband) 5324{ 5325 struct ieee80211_sband_iftype_data *iftype_data; 5326 enum nl80211_iftype iftype; 5327 int idx = 0; 5328 5329 iftype_data = devm_kcalloc(rtwdev->dev, RTW89_SBAND_IFTYPES_NR, 5330 sizeof(*iftype_data), GFP_KERNEL); 5331 if (!iftype_data) 5332 return -ENOMEM; 5333 5334 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) { 5335 switch (iftype) { 5336 case NL80211_IFTYPE_STATION: 5337 case NL80211_IFTYPE_AP: 5338 break; 5339 default: 5340 continue; 5341 } 5342 5343 if (idx >= RTW89_SBAND_IFTYPES_NR) { 5344 rtw89_warn(rtwdev, "run out of iftype_data\n"); 5345 break; 5346 } 5347 5348 iftype_data[idx].types_mask = BIT(iftype); 5349 5350 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]); 5351 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]); 5352 5353 idx++; 5354 } 5355 5356 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx); 5357 return 0; 5358} 5359 5360static struct ieee80211_supported_band * 5361rtw89_core_sband_dup(struct rtw89_dev *rtwdev, 5362 const struct ieee80211_supported_band *sband) 5363{ 5364 struct ieee80211_supported_band *dup; 5365 5366 dup = devm_kmemdup(rtwdev->dev, sband, sizeof(*sband), GFP_KERNEL); 5367 if (!dup) 5368 return NULL; 5369 5370 dup->channels = devm_kmemdup(rtwdev->dev, sband->channels, 5371 sizeof(*sband->channels) * sband->n_channels, 5372 GFP_KERNEL); 5373 if (!dup->channels) 5374 return NULL; 5375 5376 dup->bitrates = devm_kmemdup(rtwdev->dev, sband->bitrates, 5377 sizeof(*sband->bitrates) * sband->n_bitrates, 5378 GFP_KERNEL); 5379 if (!dup->bitrates) 5380 return NULL; 5381 5382 return dup; 5383} 5384 5385static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 5386{ 5387 struct ieee80211_hw *hw = rtwdev->hw; 5388 struct ieee80211_supported_band *sband; 5389 u8 support_bands = rtwdev->chip->support_bands; 5390 int ret; 5391 5392 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 5393 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_2ghz); 5394 if (!sband) 5395 return -ENOMEM; 5396 rtw89_init_ht_cap(rtwdev, &sband->ht_cap); 5397 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband); 5398 if (ret) 5399 return ret; 5400 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 5401 } 5402 5403 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 5404 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_5ghz); 5405 if (!sband) 5406 return -ENOMEM; 5407 rtw89_init_ht_cap(rtwdev, &sband->ht_cap); 5408 rtw89_init_vht_cap(rtwdev, &sband->vht_cap); 5409 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband); 5410 if (ret) 5411 return ret; 5412 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 5413 } 5414 5415 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 5416 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_6ghz); 5417 if (!sband) 5418 return -ENOMEM; 5419 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband); 5420 if (ret) 5421 return ret; 5422 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband; 5423 } 5424 5425 return 0; 5426} 5427 5428static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 5429{ 5430 int i; 5431 5432 for (i = 0; i < RTW89_PHY_NUM; i++) 5433 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 5434 for (i = 0; i < RTW89_PHY_NUM; i++) 5435 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 5436} 5437 5438void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work) 5439{ 5440 struct rtw89_dev *rtwdev; 5441 struct rtw89_vif_link *rtwvif_link = container_of(work, struct rtw89_vif_link, 5442 update_beacon_work); 5443 5444 lockdep_assert_wiphy(wiphy); 5445 5446 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE) 5447 return; 5448 5449 rtwdev = rtwvif_link->rtwvif->rtwdev; 5450 5451 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link); 5452} 5453 5454void rtw89_core_csa_beacon_work(struct wiphy *wiphy, struct wiphy_work *work) 5455{ 5456 struct rtw89_vif_link *rtwvif_link = 5457 container_of(work, struct rtw89_vif_link, csa_beacon_work.work); 5458 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 5459 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 5460 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 5461 struct ieee80211_bss_conf *bss_conf; 5462 unsigned int delay; 5463 5464 lockdep_assert_wiphy(wiphy); 5465 5466 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE) 5467 return; 5468 5469 rcu_read_lock(); 5470 5471 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 5472 if (!bss_conf->csa_active) { 5473 rcu_read_unlock(); 5474 return; 5475 } 5476 5477 delay = ieee80211_tu_to_usec(bss_conf->beacon_int); 5478 5479 rcu_read_unlock(); 5480 5481 if (!ieee80211_beacon_cntdwn_is_complete(vif, rtwvif_link->link_id)) { 5482 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link); 5483 5484 wiphy_delayed_work_queue(wiphy, &rtwvif_link->csa_beacon_work, 5485 usecs_to_jiffies(delay)); 5486 } else { 5487 ieee80211_csa_finish(vif, rtwvif_link->link_id); 5488 } 5489} 5490 5491struct rtw89_wait_response * 5492rtw89_wait_for_cond_prep(struct rtw89_wait_info *wait, unsigned int cond) 5493{ 5494 struct rtw89_wait_response *prep; 5495 unsigned int cur; 5496 5497 /* use -EPERM _iff_ telling eval side not to make any changes */ 5498 5499 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond); 5500 if (cur != RTW89_WAIT_COND_IDLE) 5501 return ERR_PTR(-EPERM); 5502 5503 prep = kzalloc(sizeof(*prep), GFP_KERNEL); 5504 if (!prep) 5505 return ERR_PTR(-ENOMEM); 5506 5507 init_completion(&prep->completion); 5508 5509 rcu_assign_pointer(wait->resp, prep); 5510 5511 return prep; 5512} 5513 5514int rtw89_wait_for_cond_eval(struct rtw89_wait_info *wait, 5515 struct rtw89_wait_response *prep, int err) 5516{ 5517 unsigned long time_left; 5518 5519 if (IS_ERR(prep)) { 5520 err = err ?: PTR_ERR(prep); 5521 5522 /* special error case: no permission to reset anything */ 5523 if (PTR_ERR(prep) == -EPERM) 5524 return err; 5525 5526 goto reset; 5527 } 5528 5529 if (err) 5530 goto cleanup; 5531 5532 time_left = wait_for_completion_timeout(&prep->completion, 5533 RTW89_WAIT_FOR_COND_TIMEOUT); 5534 if (time_left == 0) { 5535 err = -ETIMEDOUT; 5536 goto cleanup; 5537 } 5538 5539 wait->data = prep->data; 5540 5541cleanup: 5542 rcu_assign_pointer(wait->resp, NULL); 5543 kfree_rcu(prep, rcu_head); 5544 5545reset: 5546 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 5547 5548 if (err) 5549 return err; 5550 5551 if (wait->data.err) 5552 return -EFAULT; 5553 5554 return 0; 5555} 5556 5557static void rtw89_complete_cond_resp(struct rtw89_wait_response *resp, 5558 const struct rtw89_completion_data *data) 5559{ 5560 resp->data = *data; 5561 complete(&resp->completion); 5562} 5563 5564void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 5565 const struct rtw89_completion_data *data) 5566{ 5567 struct rtw89_wait_response *resp; 5568 unsigned int cur; 5569 5570 guard(rcu)(); 5571 5572 resp = rcu_dereference(wait->resp); 5573 if (!resp) 5574 return; 5575 5576 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE); 5577 if (cur != cond) 5578 return; 5579 5580 rtw89_complete_cond_resp(resp, data); 5581} 5582 5583void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event) 5584{ 5585 u16 bt_req_len; 5586 5587 switch (event) { 5588 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT: 5589 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0); 5590 rtw89_debug(rtwdev, RTW89_DBG_BTC, 5591 "coex updates BT req len to %d TU\n", bt_req_len); 5592 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE); 5593 break; 5594 default: 5595 if (event < NUM_OF_RTW89_BTC_HMSG) 5596 rtw89_debug(rtwdev, RTW89_DBG_BTC, 5597 "unhandled BTC HMSG event: %d\n", event); 5598 else 5599 rtw89_warn(rtwdev, 5600 "unrecognized BTC HMSG event: %d\n", event); 5601 break; 5602 } 5603} 5604 5605void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks) 5606{ 5607 const struct dmi_system_id *match; 5608 enum rtw89_quirks quirk; 5609 5610 if (!quirks) 5611 return; 5612 5613 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) { 5614 quirk = (uintptr_t)match->driver_data; 5615 if (quirk >= NUM_OF_RTW89_QUIRKS) 5616 continue; 5617 5618 set_bit(quirk, rtwdev->quirks); 5619 } 5620} 5621EXPORT_SYMBOL(rtw89_check_quirks); 5622 5623int rtw89_core_start(struct rtw89_dev *rtwdev) 5624{ 5625 bool no_bbmcu = !rtwdev->chip->bbmcu_nr; 5626 int ret; 5627 5628 ret = rtw89_mac_preinit(rtwdev); 5629 if (ret) { 5630 rtw89_err(rtwdev, "mac preinit fail, ret: %d\n", ret); 5631 return ret; 5632 } 5633 5634 if (no_bbmcu) 5635 rtw89_chip_bb_preinit(rtwdev); 5636 5637 rtw89_phy_init_bb_afe(rtwdev); 5638 5639 /* above do preinit before downloading firmware */ 5640 5641 ret = rtw89_mac_init(rtwdev); 5642 if (ret) { 5643 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 5644 return ret; 5645 } 5646 5647 rtw89_btc_ntfy_poweron(rtwdev); 5648 5649 /* efuse process */ 5650 5651 /* pre-config BB/RF, BB reset/RFC reset */ 5652 ret = rtw89_chip_reset_bb_rf(rtwdev); 5653 if (ret) 5654 return ret; 5655 5656 rtw89_phy_init_bb_reg(rtwdev); 5657 rtw89_chip_bb_postinit(rtwdev); 5658 rtw89_phy_init_rf_reg(rtwdev, false); 5659 5660 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 5661 5662 rtw89_phy_dm_init(rtwdev); 5663 5664 rtw89_mac_cfg_ppdu_status_bands(rtwdev, true); 5665 rtw89_mac_cfg_phy_rpt_bands(rtwdev, true); 5666 rtw89_mac_update_rts_threshold(rtwdev); 5667 5668 ret = rtw89_hci_start(rtwdev); 5669 if (ret) { 5670 rtw89_err(rtwdev, "failed to start hci\n"); 5671 return ret; 5672 } 5673 5674 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->track_work, 5675 RTW89_TRACK_WORK_PERIOD); 5676 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->track_ps_work, 5677 RTW89_TRACK_PS_WORK_PERIOD); 5678 5679 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 5680 5681 rtw89_chip_rfk_init_late(rtwdev); 5682 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 5683 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable); 5684 rtw89_fw_h2c_init_ba_cam(rtwdev); 5685 rtw89_tas_fw_timer_enable(rtwdev, true); 5686 rtwdev->ps_hang_cnt = 0; 5687 5688 return 0; 5689} 5690 5691void rtw89_core_stop(struct rtw89_dev *rtwdev) 5692{ 5693 struct wiphy *wiphy = rtwdev->hw->wiphy; 5694 struct rtw89_btc *btc = &rtwdev->btc; 5695 5696 lockdep_assert_wiphy(wiphy); 5697 5698 /* Prvent to stop twice; enter_ips and ops_stop */ 5699 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 5700 return; 5701 5702 rtw89_tas_fw_timer_enable(rtwdev, false); 5703 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 5704 5705 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 5706 5707 wiphy_work_cancel(wiphy, &rtwdev->c2h_work); 5708 wiphy_work_cancel(wiphy, &rtwdev->cancel_6ghz_probe_work); 5709 wiphy_work_cancel(wiphy, &btc->eapol_notify_work); 5710 wiphy_work_cancel(wiphy, &btc->arp_notify_work); 5711 wiphy_work_cancel(wiphy, &btc->dhcp_notify_work); 5712 wiphy_work_cancel(wiphy, &btc->icmp_notify_work); 5713 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 5714 wiphy_delayed_work_cancel(wiphy, &rtwdev->tx_wait_work); 5715 wiphy_delayed_work_cancel(wiphy, &rtwdev->track_work); 5716 wiphy_delayed_work_cancel(wiphy, &rtwdev->track_ps_work); 5717 wiphy_delayed_work_cancel(wiphy, &rtwdev->chanctx_work); 5718 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_act1_work); 5719 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_bt_devinfo_work); 5720 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_rfk_chk_work); 5721 wiphy_delayed_work_cancel(wiphy, &rtwdev->cfo_track_work); 5722 wiphy_delayed_work_cancel(wiphy, &rtwdev->mcc_prepare_done_work); 5723 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 5724 wiphy_delayed_work_cancel(wiphy, &rtwdev->antdiv_work); 5725 5726 rtw89_btc_ntfy_poweroff(rtwdev); 5727 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 5728 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 5729 rtw89_hci_stop(rtwdev); 5730 rtw89_hci_deinit(rtwdev); 5731 rtw89_mac_pwr_off(rtwdev); 5732 rtw89_hci_reset(rtwdev); 5733} 5734 5735u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev) 5736{ 5737 const struct rtw89_chip_info *chip = rtwdev->chip; 5738 u8 mac_id_num; 5739 u8 mac_id; 5740 5741 if (rtwdev->support_mlo) 5742 mac_id_num = chip->support_macid_num / chip->support_link_num; 5743 else 5744 mac_id_num = chip->support_macid_num; 5745 5746 mac_id = find_first_zero_bit(rtwdev->mac_id_map, mac_id_num); 5747 if (mac_id == mac_id_num) 5748 return RTW89_MAX_MAC_ID_NUM; 5749 5750 set_bit(mac_id, rtwdev->mac_id_map); 5751 return mac_id; 5752} 5753 5754void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id) 5755{ 5756 clear_bit(mac_id, rtwdev->mac_id_map); 5757} 5758 5759void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5760 u8 mac_id, u8 port) 5761{ 5762 const struct rtw89_chip_info *chip = rtwdev->chip; 5763 u8 support_link_num = chip->support_link_num; 5764 u8 support_mld_num = 0; 5765 unsigned int link_id; 5766 u8 index; 5767 5768 bitmap_zero(rtwvif->links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5769 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) 5770 rtwvif->links[link_id] = NULL; 5771 5772 rtwvif->rtwdev = rtwdev; 5773 5774 if (rtwdev->support_mlo) { 5775 rtwvif->links_inst_valid_num = support_link_num; 5776 support_mld_num = chip->support_macid_num / support_link_num; 5777 } else { 5778 rtwvif->links_inst_valid_num = 1; 5779 } 5780 5781 for (index = 0; index < rtwvif->links_inst_valid_num; index++) { 5782 struct rtw89_vif_link *inst = &rtwvif->links_inst[index]; 5783 5784 inst->rtwvif = rtwvif; 5785 inst->mac_id = mac_id + index * support_mld_num; 5786 inst->mac_idx = RTW89_MAC_0 + index; 5787 inst->phy_idx = RTW89_PHY_0 + index; 5788 5789 /* multi-link use the same port id on different HW bands */ 5790 inst->port = port; 5791 } 5792} 5793 5794void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5795 struct rtw89_sta *rtwsta, u8 mac_id) 5796{ 5797 const struct rtw89_chip_info *chip = rtwdev->chip; 5798 u8 support_link_num = chip->support_link_num; 5799 u8 support_mld_num = 0; 5800 unsigned int link_id; 5801 u8 index; 5802 5803 bitmap_zero(rtwsta->links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5804 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) 5805 rtwsta->links[link_id] = NULL; 5806 5807 rtwsta->rtwdev = rtwdev; 5808 rtwsta->rtwvif = rtwvif; 5809 5810 if (rtwdev->support_mlo) { 5811 rtwsta->links_inst_valid_num = support_link_num; 5812 support_mld_num = chip->support_macid_num / support_link_num; 5813 } else { 5814 rtwsta->links_inst_valid_num = 1; 5815 } 5816 5817 for (index = 0; index < rtwsta->links_inst_valid_num; index++) { 5818 struct rtw89_sta_link *inst = &rtwsta->links_inst[index]; 5819 5820 inst->rtwvif_link = &rtwvif->links_inst[index]; 5821 5822 inst->rtwsta = rtwsta; 5823 inst->mac_id = mac_id + index * support_mld_num; 5824 } 5825} 5826 5827struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 5828 unsigned int link_id) 5829{ 5830 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id]; 5831 u8 index; 5832 int ret; 5833 5834 if (rtwvif_link) 5835 return rtwvif_link; 5836 5837 index = find_first_zero_bit(rtwvif->links_inst_map, 5838 rtwvif->links_inst_valid_num); 5839 if (index == rtwvif->links_inst_valid_num) { 5840 ret = -EBUSY; 5841 goto err; 5842 } 5843 5844 rtwvif_link = &rtwvif->links_inst[index]; 5845 rtwvif_link->link_id = link_id; 5846 5847 set_bit(index, rtwvif->links_inst_map); 5848 rtwvif->links[link_id] = rtwvif_link; 5849 list_add_tail(&rtwvif_link->dlink_schd, &rtwvif->dlink_pool); 5850 return rtwvif_link; 5851 5852err: 5853 rtw89_err(rtwvif->rtwdev, "vif (link_id %u) failed to set link: %d\n", 5854 link_id, ret); 5855 return NULL; 5856} 5857 5858void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id) 5859{ 5860 struct rtw89_vif_link **container = &rtwvif->links[link_id]; 5861 struct rtw89_vif_link *link = *container; 5862 u8 index; 5863 5864 if (!link) 5865 return; 5866 5867 index = rtw89_vif_link_inst_get_index(link); 5868 clear_bit(index, rtwvif->links_inst_map); 5869 *container = NULL; 5870 list_del(&link->dlink_schd); 5871} 5872 5873struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 5874 unsigned int link_id) 5875{ 5876 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5877 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id]; 5878 struct rtw89_sta_link *rtwsta_link = rtwsta->links[link_id]; 5879 u8 index; 5880 int ret; 5881 5882 if (rtwsta_link) 5883 return rtwsta_link; 5884 5885 if (!rtwvif_link) { 5886 ret = -ENOLINK; 5887 goto err; 5888 } 5889 5890 index = rtw89_vif_link_inst_get_index(rtwvif_link); 5891 if (test_bit(index, rtwsta->links_inst_map)) { 5892 ret = -EBUSY; 5893 goto err; 5894 } 5895 5896 rtwsta_link = &rtwsta->links_inst[index]; 5897 rtwsta_link->link_id = link_id; 5898 5899 set_bit(index, rtwsta->links_inst_map); 5900 rtwsta->links[link_id] = rtwsta_link; 5901 list_add_tail(&rtwsta_link->dlink_schd, &rtwsta->dlink_pool); 5902 return rtwsta_link; 5903 5904err: 5905 rtw89_err(rtwsta->rtwdev, "sta (link_id %u) failed to set link: %d\n", 5906 link_id, ret); 5907 return NULL; 5908} 5909 5910void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id) 5911{ 5912 struct rtw89_sta_link **container = &rtwsta->links[link_id]; 5913 struct rtw89_sta_link *link = *container; 5914 u8 index; 5915 5916 if (!link) 5917 return; 5918 5919 index = rtw89_sta_link_inst_get_index(link); 5920 clear_bit(index, rtwsta->links_inst_map); 5921 *container = NULL; 5922 list_del(&link->dlink_schd); 5923} 5924 5925int rtw89_core_init(struct rtw89_dev *rtwdev) 5926{ 5927 struct rtw89_btc *btc = &rtwdev->btc; 5928 u8 band; 5929 5930 INIT_LIST_HEAD(&rtwdev->ba_list); 5931 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 5932 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 5933 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 5934 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 5935 if (!(rtwdev->chip->support_bands & BIT(band))) 5936 continue; 5937 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 5938 } 5939 INIT_LIST_HEAD(&rtwdev->scan_info.chan_list); 5940 INIT_LIST_HEAD(&rtwdev->tx_waits); 5941 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 5942 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 5943 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 5944 wiphy_delayed_work_init(&rtwdev->track_work, rtw89_track_work); 5945 wiphy_delayed_work_init(&rtwdev->track_ps_work, rtw89_track_ps_work); 5946 wiphy_delayed_work_init(&rtwdev->chanctx_work, rtw89_chanctx_work); 5947 wiphy_delayed_work_init(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 5948 wiphy_delayed_work_init(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 5949 wiphy_delayed_work_init(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 5950 wiphy_delayed_work_init(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 5951 wiphy_delayed_work_init(&rtwdev->mcc_prepare_done_work, rtw89_mcc_prepare_done_work); 5952 wiphy_delayed_work_init(&rtwdev->tx_wait_work, rtw89_tx_wait_work); 5953 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 5954 wiphy_delayed_work_init(&rtwdev->antdiv_work, rtw89_phy_antdiv_work); 5955 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 5956 if (!rtwdev->txq_wq) 5957 return -ENOMEM; 5958 spin_lock_init(&rtwdev->ba_lock); 5959 spin_lock_init(&rtwdev->rpwm_lock); 5960 mutex_init(&rtwdev->rf_mutex); 5961 rtwdev->total_sta_assoc = 0; 5962 5963 rtw89_init_wait(&rtwdev->mcc.wait); 5964 rtw89_init_wait(&rtwdev->mlo.wait); 5965 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait); 5966 rtw89_init_wait(&rtwdev->wow.wait); 5967 rtw89_init_wait(&rtwdev->mac.ps_wait); 5968 5969 wiphy_work_init(&rtwdev->c2h_work, rtw89_fw_c2h_work); 5970 wiphy_work_init(&rtwdev->ips_work, rtw89_ips_work); 5971 wiphy_work_init(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work); 5972 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work); 5973 5974 spin_lock_init(&rtwdev->tx_rpt.skb_lock); 5975 skb_queue_head_init(&rtwdev->c2h_queue); 5976 rtw89_core_ppdu_sts_init(rtwdev); 5977 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 5978 5979 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 5980 rtwdev->dbcc_en = false; 5981 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT; 5982 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 5983 5984 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 5985 rtwdev->dbcc_en = true; 5986 rtwdev->mac.qta_mode = RTW89_QTA_DBCC; 5987 rtwdev->mlo_dbcc_mode = MLO_1_PLUS_1_1RF; 5988 } 5989 5990 rtwdev->bbs[RTW89_PHY_0].phy_idx = RTW89_PHY_0; 5991 rtwdev->bbs[RTW89_PHY_1].phy_idx = RTW89_PHY_1; 5992 5993 wiphy_work_init(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 5994 wiphy_work_init(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 5995 wiphy_work_init(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 5996 wiphy_work_init(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 5997 5998 init_completion(&rtwdev->fw.req.completion); 5999 init_completion(&rtwdev->rfk_wait.completion); 6000 6001 schedule_work(&rtwdev->load_firmware_work); 6002 6003 rtw89_ser_init(rtwdev); 6004 rtw89_entity_init(rtwdev); 6005 rtw89_sar_init(rtwdev); 6006 rtw89_phy_ant_gain_init(rtwdev); 6007 6008 return 0; 6009} 6010EXPORT_SYMBOL(rtw89_core_init); 6011 6012void rtw89_core_deinit(struct rtw89_dev *rtwdev) 6013{ 6014 rtw89_ser_deinit(rtwdev); 6015 rtw89_unload_firmware(rtwdev); 6016 __rtw89_fw_free_all_early_h2c(rtwdev); 6017 6018 destroy_workqueue(rtwdev->txq_wq); 6019 mutex_destroy(&rtwdev->rf_mutex); 6020} 6021EXPORT_SYMBOL(rtw89_core_deinit); 6022 6023void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 6024 const u8 *mac_addr, bool hw_scan) 6025{ 6026 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 6027 rtwvif_link->chanctx_idx); 6028 struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 6029 6030 rtwdev->scanning = true; 6031 6032 ether_addr_copy(rtwvif_link->mac_addr, mac_addr); 6033 rtw89_btc_ntfy_scan_start(rtwdev, rtwvif_link->phy_idx, chan->band_type); 6034 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, true); 6035 rtw89_hci_recalc_int_mit(rtwdev); 6036 rtw89_phy_config_edcca(rtwdev, bb, true); 6037 rtw89_tas_scan(rtwdev, true); 6038 6039 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, mac_addr, 6040 RTW89_ROLE_INFO_CHANGE); 6041} 6042 6043void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 6044 struct rtw89_vif_link *rtwvif_link, bool hw_scan) 6045{ 6046 struct ieee80211_bss_conf *bss_conf; 6047 struct rtw89_bb_ctx *bb; 6048 int ret; 6049 6050 if (!rtwvif_link) 6051 return; 6052 6053 rcu_read_lock(); 6054 6055 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 6056 ether_addr_copy(rtwvif_link->mac_addr, bss_conf->addr); 6057 6058 rcu_read_unlock(); 6059 6060 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL, 6061 RTW89_ROLE_INFO_CHANGE); 6062 6063 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, false); 6064 rtw89_btc_ntfy_scan_finish(rtwdev, rtwvif_link->phy_idx); 6065 bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 6066 rtw89_phy_config_edcca(rtwdev, bb, false); 6067 rtw89_tas_scan(rtwdev, false); 6068 6069 if (hw_scan) { 6070 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, false, false, 6071 RTW89_SCAN_NULL_TIMEOUT); 6072 if (ret) 6073 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 6074 "scan send null-0 failed: %d\n", ret); 6075 } 6076 6077 rtwdev->scanning = false; 6078 rtw89_for_each_active_bb(rtwdev, bb) 6079 bb->dig.bypass_dig = true; 6080 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 6081 wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->ips_work); 6082} 6083 6084static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 6085{ 6086 const struct rtw89_chip_info *chip = rtwdev->chip; 6087 int ret; 6088 u8 val; 6089 u8 cv; 6090 6091 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 6092 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 6093 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 6094 cv = CHIP_CAV; 6095 else 6096 cv = CHIP_CBV; 6097 } 6098 6099 rtwdev->hal.cv = cv; 6100 6101 if (rtw89_is_rtl885xb(rtwdev)) { 6102 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val); 6103 if (ret) 6104 return; 6105 6106 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK); 6107 } 6108} 6109 6110static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 6111{ 6112 const struct rtw89_chip_info *chip = rtwdev->chip; 6113 6114 rtwdev->hal.support_cckpd = 6115 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 6116 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 6117 rtwdev->hal.support_igi = 6118 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 6119 6120 if (test_bit(RTW89_QUIRK_THERMAL_PROT_120C, rtwdev->quirks)) 6121 rtwdev->hal.thermal_prot_th = chip->thermal_th[1]; 6122 else if (test_bit(RTW89_QUIRK_THERMAL_PROT_110C, rtwdev->quirks)) 6123 rtwdev->hal.thermal_prot_th = chip->thermal_th[0]; 6124 else 6125 rtwdev->hal.thermal_prot_th = 0; 6126} 6127 6128static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev) 6129{ 6130 const struct rtw89_chip_info *chip = rtwdev->chip; 6131 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf; 6132 struct rtw89_efuse *efuse = &rtwdev->efuse; 6133 const struct rtw89_rfe_parms *sel; 6134 u8 rfe_type = efuse->rfe_type; 6135 6136 if (!conf) { 6137 sel = chip->dflt_parms; 6138 goto out; 6139 } 6140 6141 while (conf->rfe_parms) { 6142 if (rfe_type == conf->rfe_type) { 6143 sel = conf->rfe_parms; 6144 goto out; 6145 } 6146 conf++; 6147 } 6148 6149 sel = chip->dflt_parms; 6150 6151out: 6152 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel); 6153 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl); 6154} 6155 6156int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6157 unsigned int link_id) 6158{ 6159 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 6160 u16 usable_links = ieee80211_vif_usable_links(vif); 6161 u16 active_links = vif->active_links; 6162 struct rtw89_vif_link *target; 6163 int ret; 6164 6165 lockdep_assert_wiphy(rtwdev->hw->wiphy); 6166 6167 if (unlikely(!ieee80211_vif_is_mld(vif))) 6168 return -EOPNOTSUPP; 6169 6170 if (unlikely(link_id >= IEEE80211_MLD_MAX_NUM_LINKS || 6171 !(usable_links & BIT(link_id)))) { 6172 rtw89_warn(rtwdev, "%s: link id %u is not usable\n", __func__, 6173 link_id); 6174 return -ENOLINK; 6175 } 6176 6177 if (active_links == BIT(link_id)) 6178 return 0; 6179 6180 rtw89_debug(rtwdev, RTW89_DBG_STATE, "%s: switch to link id %u MLSR\n", 6181 __func__, link_id); 6182 6183 rtw89_leave_lps(rtwdev); 6184 6185 ieee80211_stop_queues(rtwdev->hw); 6186 flush_work(&rtwdev->txq_work); 6187 6188 ret = ieee80211_set_active_links(vif, BIT(link_id)); 6189 if (ret) { 6190 rtw89_err(rtwdev, "%s: failed to work on link id %u\n", 6191 __func__, link_id); 6192 goto wake_queue; 6193 } 6194 6195 target = rtwvif->links[link_id]; 6196 if (unlikely(!target)) { 6197 rtw89_err(rtwdev, "%s: failed to confirm link id %u\n", 6198 __func__, link_id); 6199 6200 ieee80211_set_active_links(vif, active_links); 6201 ret = -EFAULT; 6202 goto wake_queue; 6203 } 6204 6205 rtw89_chip_rfk_channel(rtwdev, target); 6206 6207 rtwvif->mlo_mode = RTW89_MLO_MODE_MLSR; 6208 6209wake_queue: 6210 ieee80211_wake_queues(rtwdev->hw); 6211 6212 return ret; 6213} 6214 6215static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 6216{ 6217 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6218 int ret; 6219 6220 ret = rtw89_mac_partial_init(rtwdev, false); 6221 if (ret) 6222 return ret; 6223 6224 ret = mac->parse_efuse_map(rtwdev); 6225 if (ret) 6226 return ret; 6227 6228 ret = mac->parse_phycap_map(rtwdev); 6229 if (ret) 6230 return ret; 6231 6232 ret = rtw89_mac_setup_phycap(rtwdev); 6233 if (ret) 6234 return ret; 6235 6236 rtw89_core_setup_phycap(rtwdev); 6237 6238 rtw89_hci_mac_pre_deinit(rtwdev); 6239 6240 return 0; 6241} 6242 6243static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 6244{ 6245 rtw89_chip_fem_setup(rtwdev); 6246 6247 return 0; 6248} 6249 6250static bool rtw89_chip_has_rfkill(struct rtw89_dev *rtwdev) 6251{ 6252 return !!rtwdev->chip->rfkill_init; 6253} 6254 6255static void rtw89_core_rfkill_init(struct rtw89_dev *rtwdev) 6256{ 6257 const struct rtw89_rfkill_regs *regs = rtwdev->chip->rfkill_init; 6258 6259 rtw89_write16_mask(rtwdev, regs->pinmux.addr, 6260 regs->pinmux.mask, regs->pinmux.data); 6261 rtw89_write16_mask(rtwdev, regs->mode.addr, 6262 regs->mode.mask, regs->mode.data); 6263} 6264 6265static bool rtw89_core_rfkill_get(struct rtw89_dev *rtwdev) 6266{ 6267 const struct rtw89_reg_def *reg = &rtwdev->chip->rfkill_get; 6268 6269 return !rtw89_read8_mask(rtwdev, reg->addr, reg->mask); 6270} 6271 6272static void rtw89_rfkill_polling_init(struct rtw89_dev *rtwdev) 6273{ 6274 if (!rtw89_chip_has_rfkill(rtwdev)) 6275 return; 6276 6277 rtw89_core_rfkill_init(rtwdev); 6278 rtw89_core_rfkill_poll(rtwdev, true); 6279 wiphy_rfkill_start_polling(rtwdev->hw->wiphy); 6280} 6281 6282static void rtw89_rfkill_polling_deinit(struct rtw89_dev *rtwdev) 6283{ 6284 if (!rtw89_chip_has_rfkill(rtwdev)) 6285 return; 6286 6287 wiphy_rfkill_stop_polling(rtwdev->hw->wiphy); 6288} 6289 6290void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force) 6291{ 6292 bool prev, blocked; 6293 6294 if (!rtw89_chip_has_rfkill(rtwdev)) 6295 return; 6296 6297 prev = test_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 6298 blocked = rtw89_core_rfkill_get(rtwdev); 6299 6300 if (!force && prev == blocked) 6301 return; 6302 6303 rtw89_info(rtwdev, "rfkill hardware state changed to %s\n", 6304 blocked ? "disable" : "enable"); 6305 6306 if (blocked) 6307 set_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 6308 else 6309 clear_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 6310 6311 wiphy_rfkill_set_hw_state(rtwdev->hw->wiphy, blocked); 6312} 6313 6314int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 6315{ 6316 int ret; 6317 6318 rtw89_read_chip_ver(rtwdev); 6319 6320 ret = rtw89_mac_pwr_on(rtwdev); 6321 if (ret) { 6322 rtw89_err(rtwdev, "failed to power on\n"); 6323 return ret; 6324 } 6325 6326 ret = rtw89_wait_firmware_completion(rtwdev); 6327 if (ret) { 6328 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 6329 goto out; 6330 } 6331 6332 ret = rtw89_fw_recognize(rtwdev); 6333 if (ret) { 6334 rtw89_err(rtwdev, "failed to recognize firmware\n"); 6335 goto out; 6336 } 6337 6338 ret = rtw89_chip_efuse_info_setup(rtwdev); 6339 if (ret) 6340 goto out; 6341 6342 ret = rtw89_fw_recognize_elements(rtwdev); 6343 if (ret) { 6344 rtw89_err(rtwdev, "failed to recognize firmware elements\n"); 6345 goto out; 6346 } 6347 6348 ret = rtw89_chip_board_info_setup(rtwdev); 6349 if (ret) 6350 goto out; 6351 6352 rtw89_core_setup_rfe_parms(rtwdev); 6353 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 6354 6355out: 6356 rtw89_mac_pwr_off(rtwdev); 6357 6358 return ret; 6359} 6360EXPORT_SYMBOL(rtw89_chip_info_setup); 6361 6362void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 6363 struct rtw89_vif_link *rtwvif_link) 6364{ 6365 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 6366 const struct rtw89_chip_info *chip = rtwdev->chip; 6367 struct ieee80211_bss_conf *bss_conf; 6368 6369 rcu_read_lock(); 6370 6371 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 6372 if (!bss_conf->he_support || !vif->cfg.assoc) { 6373 rcu_read_unlock(); 6374 return; 6375 } 6376 6377 rcu_read_unlock(); 6378 6379 if (chip->ops->set_txpwr_ul_tb_offset) 6380 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif_link->mac_idx); 6381} 6382 6383static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 6384{ 6385 const struct rtw89_chip_info *chip = rtwdev->chip; 6386 u8 n = rtwdev->support_mlo ? chip->support_link_num : 1; 6387 struct ieee80211_hw *hw = rtwdev->hw; 6388 struct rtw89_efuse *efuse = &rtwdev->efuse; 6389 struct rtw89_hal *hal = &rtwdev->hal; 6390 int ret; 6391 int tx_headroom = IEEE80211_HT_CTL_LEN; 6392 6393 if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) 6394 tx_headroom += chip->txwd_body_size + chip->txwd_info_size; 6395 6396 hw->vif_data_size = struct_size_t(struct rtw89_vif, links_inst, n); 6397 hw->sta_data_size = struct_size_t(struct rtw89_sta, links_inst, n); 6398 hw->txq_data_size = sizeof(struct rtw89_txq); 6399 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 6400 6401 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 6402 6403 hw->extra_tx_headroom = tx_headroom; 6404 hw->queues = IEEE80211_NUM_ACS; 6405 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; 6406 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; 6407 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL; 6408 6409 hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC | 6410 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 6411 hw->radiotap_vht_details |= IEEE80211_RADIOTAP_VHT_KNOWN_STBC; 6412 6413 ieee80211_hw_set(hw, SIGNAL_DBM); 6414 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 6415 ieee80211_hw_set(hw, MFP_CAPABLE); 6416 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 6417 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 6418 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 6419 ieee80211_hw_set(hw, TX_AMSDU); 6420 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 6421 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 6422 ieee80211_hw_set(hw, SUPPORTS_PS); 6423 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 6424 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 6425 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 6426 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 6427 ieee80211_hw_set(hw, CHANCTX_STA_CSA); 6428 6429 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 6430 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 6431 6432 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw)) 6433 ieee80211_hw_set(hw, CONNECTION_MONITOR); 6434 6435 if (RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &rtwdev->fw)) 6436 ieee80211_hw_set(hw, AP_LINK_PS); 6437 6438 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 6439 BIT(NL80211_IFTYPE_AP) | 6440 BIT(NL80211_IFTYPE_P2P_CLIENT) | 6441 BIT(NL80211_IFTYPE_P2P_GO); 6442 6443 if (hal->ant_diversity) { 6444 hw->wiphy->available_antennas_tx = 0x3; 6445 hw->wiphy->available_antennas_rx = 0x3; 6446 } else { 6447 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 6448 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 6449 } 6450 6451 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 6452 WIPHY_FLAG_TDLS_EXTERNAL_SETUP | 6453 WIPHY_FLAG_AP_UAPSD | 6454 WIPHY_FLAG_HAS_CHANNEL_SWITCH | 6455 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK; 6456 6457 if (!chip->support_rnr) 6458 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ; 6459 6460 if (chip->chip_gen == RTW89_CHIP_BE) 6461 hw->wiphy->flags |= WIPHY_FLAG_DISABLE_WEXT; 6462 6463 if (rtwdev->support_mlo) { 6464 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_MLO; 6465 hw->wiphy->iftype_ext_capab = rtw89_iftypes_ext_capa; 6466 hw->wiphy->num_iftype_ext_capab = ARRAY_SIZE(rtw89_iftypes_ext_capa); 6467 } 6468 6469 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 6470 6471 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 6472 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 6473 6474#ifdef CONFIG_PM 6475 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 6476 hw->wiphy->max_sched_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 6477#endif 6478 6479 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 6480 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 6481 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 6482 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 6483 hw->wiphy->max_remain_on_channel_duration = 1000; 6484 6485 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 6486 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 6487 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 6488 6489 ret = rtw89_core_set_supported_band(rtwdev); 6490 if (ret) { 6491 rtw89_err(rtwdev, "failed to set supported band\n"); 6492 return ret; 6493 } 6494 6495 ret = rtw89_regd_setup(rtwdev); 6496 if (ret) { 6497 rtw89_err(rtwdev, "failed to set up regd\n"); 6498 return ret; 6499 } 6500 6501 hw->wiphy->sar_capa = &rtw89_sar_capa; 6502 6503 ret = ieee80211_register_hw(hw); 6504 if (ret) { 6505 rtw89_err(rtwdev, "failed to register hw\n"); 6506 return ret; 6507 } 6508 6509 ret = rtw89_regd_init_hint(rtwdev); 6510 if (ret) { 6511 rtw89_err(rtwdev, "failed to init regd\n"); 6512 goto err_unregister_hw; 6513 } 6514 6515 rtw89_rfkill_polling_init(rtwdev); 6516 6517 return 0; 6518 6519err_unregister_hw: 6520 ieee80211_unregister_hw(hw); 6521 6522 return ret; 6523} 6524 6525static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 6526{ 6527 struct ieee80211_hw *hw = rtwdev->hw; 6528 6529 rtw89_rfkill_polling_deinit(rtwdev); 6530 ieee80211_unregister_hw(hw); 6531} 6532 6533int rtw89_core_register(struct rtw89_dev *rtwdev) 6534{ 6535 int ret; 6536 6537 ret = rtw89_core_register_hw(rtwdev); 6538 if (ret) { 6539 rtw89_err(rtwdev, "failed to register core hw\n"); 6540 return ret; 6541 } 6542 6543 rtw89_phy_dm_init_data(rtwdev); 6544 rtw89_debugfs_init(rtwdev); 6545 6546 return 0; 6547} 6548EXPORT_SYMBOL(rtw89_core_register); 6549 6550void rtw89_core_unregister(struct rtw89_dev *rtwdev) 6551{ 6552 rtw89_core_unregister_hw(rtwdev); 6553 6554 rtw89_debugfs_deinit(rtwdev); 6555} 6556EXPORT_SYMBOL(rtw89_core_unregister); 6557 6558struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 6559 u32 bus_data_size, 6560 const struct rtw89_chip_info *chip, 6561 const struct rtw89_chip_variant *variant) 6562{ 6563 struct rtw89_fw_info early_fw = {}; 6564 const struct firmware *firmware; 6565 struct ieee80211_hw *hw; 6566 struct rtw89_dev *rtwdev; 6567 struct ieee80211_ops *ops; 6568 u32 driver_data_size; 6569 int fw_format = -1; 6570 bool support_mlo; 6571 bool no_chanctx; 6572 6573 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format); 6574 6575 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 6576 if (!ops) 6577 goto err; 6578 6579 no_chanctx = chip->support_chanctx_num == 0 || 6580 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) || 6581 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw); 6582 6583 if (no_chanctx) { 6584 ops->add_chanctx = ieee80211_emulate_add_chanctx; 6585 ops->remove_chanctx = ieee80211_emulate_remove_chanctx; 6586 ops->change_chanctx = ieee80211_emulate_change_chanctx; 6587 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx; 6588 ops->assign_vif_chanctx = NULL; 6589 ops->unassign_vif_chanctx = NULL; 6590 ops->remain_on_channel = NULL; 6591 ops->cancel_remain_on_channel = NULL; 6592 } 6593 6594 if (!chip->support_noise) 6595 ops->get_survey = NULL; 6596 6597 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 6598 hw = ieee80211_alloc_hw(driver_data_size, ops); 6599 if (!hw) 6600 goto err; 6601 6602 /* Currently, our AP_LINK_PS handling only works for non-MLD softap 6603 * or MLD-single-link softap. If RTW89_MLD_NON_STA_LINK_NUM enlarges, 6604 * please tweak entire AP_LINKS_PS handling before supporting MLO. 6605 */ 6606 support_mlo = !no_chanctx && chip->support_link_num && 6607 RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &early_fw) && 6608 RTW89_MLD_NON_STA_LINK_NUM == 1; 6609 6610 hw->wiphy->iface_combinations = rtw89_iface_combs; 6611 6612 if (no_chanctx || chip->support_chanctx_num == 1) 6613 hw->wiphy->n_iface_combinations = 1; 6614 else 6615 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs); 6616 6617 rtwdev = hw->priv; 6618 rtwdev->hw = hw; 6619 rtwdev->dev = device; 6620 rtwdev->ops = ops; 6621 rtwdev->chip = chip; 6622 rtwdev->variant = variant; 6623 rtwdev->fw.req.firmware = firmware; 6624 rtwdev->fw.fw_format = fw_format; 6625 rtwdev->support_mlo = support_mlo; 6626 6627 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s chanctx\n", 6628 no_chanctx ? "without" : "with"); 6629 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s MLO cap\n", 6630 support_mlo ? "with" : "without"); 6631 6632 return rtwdev; 6633 6634err: 6635 kfree(ops); 6636 release_firmware(firmware); 6637 return NULL; 6638} 6639EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 6640 6641void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 6642{ 6643 kfree(rtwdev->ops); 6644 kfree(rtwdev->rfe_data); 6645 release_firmware(rtwdev->fw.req.firmware); 6646 ieee80211_free_hw(rtwdev->hw); 6647} 6648EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 6649 6650MODULE_AUTHOR("Realtek Corporation"); 6651MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 6652MODULE_LICENSE("Dual BSD/GPL");
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