rtw88xxa.h

  1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
  2/* Copyright(c) 2024  Realtek Corporation
  3 */
  4
  5#ifndef __RTW88XXA_H__
  6#define __RTW88XXA_H__
  7
  8#include <asm/byteorder.h>
  9#include "reg.h"
 10
 11struct rtw8821au_efuse {
 12	u8 res4[48];			/* 0xd0 */
 13	u8 vid[2];			/* 0x100 */
 14	u8 pid[2];
 15	u8 res8[3];
 16	u8 mac_addr[ETH_ALEN];		/* 0x107 */
 17	u8 res9[243];
 18} __packed;
 19
 20struct rtw8812au_efuse {
 21	u8 vid[2];			/* 0xd0 */
 22	u8 pid[2];			/* 0xd2 */
 23	u8 res0[3];
 24	u8 mac_addr[ETH_ALEN];		/* 0xd7 */
 25	u8 res1[291];
 26} __packed;
 27
 28struct rtw88xxa_efuse {
 29	__le16 rtl_id;
 30	u8 res0[6];			/* 0x02 */
 31	u8 usb_mode;			/* 0x08 */
 32	u8 res1[7];			/* 0x09 */
 33
 34	/* power index for four RF paths */
 35	struct rtw_txpwr_idx txpwr_idx_table[4];
 36
 37	u8 channel_plan;		/* 0xb8 */
 38	u8 xtal_k;
 39	u8 thermal_meter;
 40	u8 iqk_lck;
 41	u8 pa_type;			/* 0xbc */
 42	u8 lna_type_2g;			/* 0xbd */
 43	u8 res2;
 44	u8 lna_type_5g;			/* 0xbf */
 45	u8 res3;
 46	u8 rf_board_option;		/* 0xc1 */
 47	u8 rf_feature_option;
 48	u8 rf_bt_setting;
 49	u8 eeprom_version;
 50	u8 eeprom_customer_id;		/* 0xc5 */
 51	u8 tx_bb_swing_setting_2g;
 52	u8 tx_bb_swing_setting_5g;
 53	u8 tx_pwr_calibrate_rate;
 54	u8 rf_antenna_option;		/* 0xc9 */
 55	u8 rfe_option;
 56	u8 country_code[2];
 57	u8 res4[3];
 58	union {
 59		struct rtw8821au_efuse rtw8821au;
 60		struct rtw8812au_efuse rtw8812au;
 61	};
 62} __packed;
 63
 64static_assert(sizeof(struct rtw88xxa_efuse) == 512);
 65
 66#define WLAN_BCN_DMA_TIME			0x02
 67#define WLAN_TBTT_PROHIBIT			0x04
 68#define WLAN_TBTT_HOLD_TIME			0x064
 69#define WLAN_TBTT_TIME	(WLAN_TBTT_PROHIBIT |\
 70			(WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
 71
 72struct rtw_jaguar_phy_status_rpt {
 73	__le32 w0;
 74	__le32 w1;
 75	__le32 w2;
 76	__le32 w3;
 77	__le32 w4;
 78	__le32 w5;
 79	__le32 w6;
 80} __packed;
 81
 82#define RTW_JGRPHY_W0_GAIN_A		GENMASK(6, 0)
 83#define RTW_JGRPHY_W0_TRSW_A		BIT(7)
 84#define RTW_JGRPHY_W0_GAIN_B		GENMASK(14, 8)
 85#define RTW_JGRPHY_W0_TRSW_B		BIT(15)
 86#define RTW_JGRPHY_W0_CHL_NUM		GENMASK(25, 16)
 87#define RTW_JGRPHY_W0_SUB_CHNL		GENMASK(29, 26)
 88#define RTW_JGRPHY_W0_R_RFMOD		GENMASK(31, 30)
 89
 90/* CCK: */
 91#define RTW_JGRPHY_W1_SIG_QUAL		GENMASK(7, 0)
 92#define RTW_JGRPHY_W1_AGC_RPT_VGA_IDX	GENMASK(12, 8)
 93#define RTW_JGRPHY_W1_AGC_RPT_LNA_IDX	GENMASK(15, 13)
 94#define RTW_JGRPHY_W1_BB_POWER		GENMASK(23, 16)
 95/* OFDM: */
 96#define RTW_JGRPHY_W1_PWDB_ALL		GENMASK(7, 0)
 97#define RTW_JGRPHY_W1_CFO_SHORT_A	GENMASK(15, 8)	/* s8 */
 98#define RTW_JGRPHY_W1_CFO_SHORT_B	GENMASK(23, 16)	/* s8 */
 99#define RTW_JGRPHY_W1_BT_RF_CH_MSB	GENMASK(31, 30)
100
101#define RTW_JGRPHY_W2_ANT_DIV_SW_A	BIT(0)
102#define RTW_JGRPHY_W2_ANT_DIV_SW_B	BIT(1)
103#define RTW_JGRPHY_W2_BT_RF_CH_LSB	GENMASK(7, 2)
104#define RTW_JGRPHY_W2_CFO_TAIL_A	GENMASK(15, 8)	/* s8 */
105#define RTW_JGRPHY_W2_CFO_TAIL_B	GENMASK(23, 16)	/* s8 */
106#define RTW_JGRPHY_W2_PCTS_MSK_RPT_0	GENMASK(31, 24)
107
108#define RTW_JGRPHY_W3_PCTS_MSK_RPT_1	GENMASK(7, 0)
109/* Stream 1 and 2 RX EVM: */
110#define RTW_JGRPHY_W3_RXEVM_1		GENMASK(15, 8)	/* s8 */
111#define RTW_JGRPHY_W3_RXEVM_2		GENMASK(23, 16)	/* s8 */
112#define RTW_JGRPHY_W3_RXSNR_A		GENMASK(31, 24)	/* s8 */
113
114#define RTW_JGRPHY_W4_RXSNR_B		GENMASK(7, 0)	/* s8 */
115#define RTW_JGRPHY_W4_PCTS_MSK_RPT_2	GENMASK(21, 8)
116#define RTW_JGRPHY_W4_PCTS_RPT_VALID	BIT(22)
117#define RTW_JGRPHY_W4_RXEVM_3		GENMASK(31, 24)	/* s8 */
118
119#define RTW_JGRPHY_W5_RXEVM_4		GENMASK(7, 0)	/* s8 */
120/* 8812a, stream 1 and 2 CSI: */
121#define RTW_JGRPHY_W5_CSI_CURRENT_1	GENMASK(15, 8)
122#define RTW_JGRPHY_W5_CSI_CURRENT_2	GENMASK(23, 16)
123/* 8814a: */
124#define RTW_JGRPHY_W5_RXSNR_C		GENMASK(15, 8)	/* s8 */
125#define RTW_JGRPHY_W5_RXSNR_D		GENMASK(23, 16)	/* s8 */
126#define RTW_JGRPHY_W5_GAIN_C		GENMASK(30, 24)
127#define RTW_JGRPHY_W5_TRSW_C		BIT(31)
128
129#define RTW_JGRPHY_W6_GAIN_D		GENMASK(6, 0)
130#define RTW_JGRPHY_W6_TRSW_D		BIT(7)
131#define RTW_JGRPHY_W6_SIGEVM		GENMASK(15, 8)	/* s8 */
132#define RTW_JGRPHY_W6_ANTIDX_ANTC	GENMASK(18, 16)
133#define RTW_JGRPHY_W6_ANTIDX_ANTD	GENMASK(21, 19)
134#define RTW_JGRPHY_W6_DPDT_CTRL_KEEP	BIT(22)
135#define RTW_JGRPHY_W6_GNT_BT_KEEP	BIT(23)
136#define RTW_JGRPHY_W6_ANTIDX_ANTA	GENMASK(26, 24)
137#define RTW_JGRPHY_W6_ANTIDX_ANTB	GENMASK(29, 27)
138#define RTW_JGRPHY_W6_HW_ANTSW_OCCUR	GENMASK(31, 30)
139
140#define RF18_BW_MASK		(BIT(11) | BIT(10))
141
142void rtw88xxa_efuse_grant(struct rtw_dev *rtwdev, bool on);
143int rtw88xxa_read_efuse(struct rtw_dev *rtwdev, u8 *log_map);
144void rtw88xxa_power_off(struct rtw_dev *rtwdev,
145			const struct rtw_pwr_seq_cmd *const *enter_lps_flow);
146int rtw88xxa_power_on(struct rtw_dev *rtwdev);
147u32 rtw88xxa_phy_read_rf(struct rtw_dev *rtwdev,
148			 enum rtw_rf_path rf_path, u32 addr, u32 mask);
149void rtw88xxa_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
150			  u8 primary_chan_idx);
151void rtw88xxa_query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
152			       struct rtw_rx_pkt_stat *pkt_stat,
153			       s8 (*cck_rx_pwr)(u8 lna_idx, u8 vga_idx));
154void rtw88xxa_set_tx_power_index(struct rtw_dev *rtwdev);
155void rtw88xxa_false_alarm_statistics(struct rtw_dev *rtwdev);
156void rtw88xxa_iqk_backup_mac_bb(struct rtw_dev *rtwdev,
157				u32 *macbb_backup,
158				const u32 *backup_macbb_reg,
159				u32 macbb_num);
160void rtw88xxa_iqk_backup_afe(struct rtw_dev *rtwdev, u32 *afe_backup,
161			     const u32 *backup_afe_reg, u32 afe_num);
162void rtw88xxa_iqk_restore_mac_bb(struct rtw_dev *rtwdev,
163				 u32 *macbb_backup,
164				 const u32 *backup_macbb_reg,
165				 u32 macbb_num);
166void rtw88xxa_iqk_configure_mac(struct rtw_dev *rtwdev);
167bool rtw88xxa_iqk_finish(int average, int threshold,
168			 int *x_temp, int *y_temp, int *x, int *y,
169			 bool break_inner, bool break_outer);
170void rtw88xxa_phy_pwrtrack(struct rtw_dev *rtwdev,
171			   void (*do_lck)(struct rtw_dev *rtwdev),
172			   void (*do_iqk)(struct rtw_dev *rtwdev));
173void rtw88xxa_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl);
174
175#endif