rtw88xxa.c

   1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2/* Copyright(c) 2024  Realtek Corporation
   3 */
   4
   5#include <linux/usb.h>
   6#include "main.h"
   7#include "coex.h"
   8#include "phy.h"
   9#include "rtw88xxa.h"
  10#include "mac.h"
  11#include "reg.h"
  12#include "sec.h"
  13#include "debug.h"
  14#include "bf.h"
  15#include "efuse.h"
  16#include "usb.h"
  17
  18void rtw88xxa_efuse_grant(struct rtw_dev *rtwdev, bool on)
  19{
  20	if (on) {
  21		rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON);
  22
  23		rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_ELDR);
  24		rtw_write16_set(rtwdev, REG_SYS_CLKR,
  25				BIT_LOADER_CLK_EN | BIT_ANA8M);
  26	} else {
  27		rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
  28	}
  29}
  30EXPORT_SYMBOL(rtw88xxa_efuse_grant);
  31
  32static void rtw8812a_read_amplifier_type(struct rtw_dev *rtwdev)
  33{
  34	struct rtw_efuse *efuse = &rtwdev->efuse;
  35
  36	efuse->ext_pa_2g = (efuse->pa_type_2g & BIT(5)) &&
  37			   (efuse->pa_type_2g & BIT(4));
  38	efuse->ext_lna_2g = (efuse->lna_type_2g & BIT(7)) &&
  39			    (efuse->lna_type_2g & BIT(3));
  40
  41	efuse->ext_pa_5g = (efuse->pa_type_5g & BIT(1)) &&
  42			   (efuse->pa_type_5g & BIT(0));
  43	efuse->ext_lna_5g = (efuse->lna_type_5g & BIT(7)) &&
  44			    (efuse->lna_type_5g & BIT(3));
  45
  46	/* For rtw_phy_cond2: */
  47	if (efuse->ext_pa_2g) {
  48		u8 ext_type_pa_2g_a = u8_get_bits(efuse->lna_type_2g, BIT(2));
  49		u8 ext_type_pa_2g_b = u8_get_bits(efuse->lna_type_2g, BIT(6));
  50
  51		efuse->gpa_type = (ext_type_pa_2g_b << 2) | ext_type_pa_2g_a;
  52	}
  53
  54	if (efuse->ext_pa_5g) {
  55		u8 ext_type_pa_5g_a = u8_get_bits(efuse->lna_type_5g, BIT(2));
  56		u8 ext_type_pa_5g_b = u8_get_bits(efuse->lna_type_5g, BIT(6));
  57
  58		efuse->apa_type = (ext_type_pa_5g_b << 2) | ext_type_pa_5g_a;
  59	}
  60
  61	if (efuse->ext_lna_2g) {
  62		u8 ext_type_lna_2g_a = u8_get_bits(efuse->lna_type_2g,
  63						   BIT(1) | BIT(0));
  64		u8 ext_type_lna_2g_b = u8_get_bits(efuse->lna_type_2g,
  65						   BIT(5) | BIT(4));
  66
  67		efuse->glna_type = (ext_type_lna_2g_b << 2) | ext_type_lna_2g_a;
  68	}
  69
  70	if (efuse->ext_lna_5g) {
  71		u8 ext_type_lna_5g_a = u8_get_bits(efuse->lna_type_5g,
  72						   BIT(1) | BIT(0));
  73		u8 ext_type_lna_5g_b = u8_get_bits(efuse->lna_type_5g,
  74						   BIT(5) | BIT(4));
  75
  76		efuse->alna_type = (ext_type_lna_5g_b << 2) | ext_type_lna_5g_a;
  77	}
  78}
  79
  80static void rtw8812a_read_rfe_type(struct rtw_dev *rtwdev,
  81				   struct rtw88xxa_efuse *map)
  82{
  83	struct rtw_efuse *efuse = &rtwdev->efuse;
  84
  85	if (map->rfe_option == 0xff) {
  86		if (rtwdev->hci.type == RTW_HCI_TYPE_USB)
  87			efuse->rfe_option = 0;
  88		else if (rtwdev->hci.type == RTW_HCI_TYPE_PCIE)
  89			efuse->rfe_option = 2;
  90		else
  91			efuse->rfe_option = 4;
  92	} else if (map->rfe_option & BIT(7)) {
  93		if (efuse->ext_lna_5g) {
  94			if (efuse->ext_pa_5g) {
  95				if (efuse->ext_lna_2g && efuse->ext_pa_2g)
  96					efuse->rfe_option = 3;
  97				else
  98					efuse->rfe_option = 0;
  99			} else {
 100				efuse->rfe_option = 2;
 101			}
 102		} else {
 103			efuse->rfe_option = 4;
 104		}
 105	} else {
 106		efuse->rfe_option = map->rfe_option & 0x3f;
 107
 108		/* Due to other customer already use incorrect EFUSE map for
 109		 * their product. We need to add workaround to prevent to
 110		 * modify spec and notify all customer to revise the IC 0xca
 111		 * content.
 112		 */
 113		if (efuse->rfe_option == 4 &&
 114		    (efuse->ext_pa_5g || efuse->ext_pa_2g ||
 115		     efuse->ext_lna_5g || efuse->ext_lna_2g)) {
 116			if (rtwdev->hci.type == RTW_HCI_TYPE_USB)
 117				efuse->rfe_option = 0;
 118			else if (rtwdev->hci.type == RTW_HCI_TYPE_PCIE)
 119				efuse->rfe_option = 2;
 120		}
 121	}
 122}
 123
 124static void rtw88xxa_read_usb_type(struct rtw_dev *rtwdev)
 125{
 126	struct rtw_efuse *efuse = &rtwdev->efuse;
 127	struct rtw_hal *hal = &rtwdev->hal;
 128	u8 antenna = 0;
 129	u8 wmode = 0;
 130	u8 val8, i;
 131
 132	efuse->hw_cap.bw = BIT(RTW_CHANNEL_WIDTH_20) |
 133			   BIT(RTW_CHANNEL_WIDTH_40) |
 134			   BIT(RTW_CHANNEL_WIDTH_80);
 135	efuse->hw_cap.ptcl = EFUSE_HW_CAP_PTCL_VHT;
 136
 137	if (rtwdev->chip->id == RTW_CHIP_TYPE_8821A)
 138		efuse->hw_cap.nss = 1;
 139	else
 140		efuse->hw_cap.nss = 2;
 141
 142	if (rtwdev->chip->id == RTW_CHIP_TYPE_8821A)
 143		goto print_hw_cap;
 144
 145	for (i = 0; i < 2; i++) {
 146		rtw_read8_physical_efuse(rtwdev, 1019 - i, &val8);
 147
 148		antenna = u8_get_bits(val8, GENMASK(7, 5));
 149		if (antenna)
 150			break;
 151		antenna = u8_get_bits(val8, GENMASK(3, 1));
 152		if (antenna)
 153			break;
 154	}
 155
 156	for (i = 0; i < 2; i++) {
 157		rtw_read8_physical_efuse(rtwdev, 1021 - i, &val8);
 158
 159		wmode = u8_get_bits(val8, GENMASK(3, 2));
 160		if (wmode)
 161			break;
 162	}
 163
 164	if (antenna == 1) {
 165		rtw_info(rtwdev, "This RTL8812AU says it is 1T1R.\n");
 166
 167		efuse->hw_cap.nss = 1;
 168		hal->rf_type = RF_1T1R;
 169		hal->rf_path_num = 1;
 170		hal->rf_phy_num = 1;
 171		hal->antenna_tx = BB_PATH_A;
 172		hal->antenna_rx = BB_PATH_A;
 173	} else {
 174		/* Override rtw_chip_parameter_setup(). It detects 8812au as 1T1R. */
 175		efuse->hw_cap.nss = 2;
 176		hal->rf_type = RF_2T2R;
 177		hal->rf_path_num = 2;
 178		hal->rf_phy_num = 2;
 179		hal->antenna_tx = BB_PATH_AB;
 180		hal->antenna_rx = BB_PATH_AB;
 181
 182		if (antenna == 2 && wmode == 2) {
 183			rtw_info(rtwdev, "This RTL8812AU says it can't do VHT.\n");
 184
 185			/* Can't be EFUSE_HW_CAP_IGNORE and can't be
 186			 * EFUSE_HW_CAP_PTCL_VHT, so make it 1.
 187			 */
 188			efuse->hw_cap.ptcl = 1;
 189			efuse->hw_cap.bw &= ~BIT(RTW_CHANNEL_WIDTH_80);
 190		}
 191	}
 192
 193print_hw_cap:
 194	rtw_dbg(rtwdev, RTW_DBG_EFUSE,
 195		"hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n",
 196		efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl,
 197		efuse->hw_cap.ant_num, efuse->hw_cap.nss);
 198}
 199
 200int rtw88xxa_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
 201{
 202	const struct rtw_chip_info *chip = rtwdev->chip;
 203	struct rtw_efuse *efuse = &rtwdev->efuse;
 204	struct rtw88xxa_efuse *map;
 205	int i;
 206
 207	if (chip->id == RTW_CHIP_TYPE_8812A)
 208		rtwdev->hal.cut_version += 1;
 209
 210	if (rtw_dbg_is_enabled(rtwdev, RTW_DBG_EFUSE))
 211		print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
 212			       log_map, chip->log_efuse_size, true);
 213
 214	map = (struct rtw88xxa_efuse *)log_map;
 215
 216	efuse->rf_board_option = map->rf_board_option;
 217	efuse->crystal_cap = map->xtal_k;
 218	if (efuse->crystal_cap == 0xff)
 219		efuse->crystal_cap = 0x20;
 220	efuse->pa_type_2g = map->pa_type;
 221	efuse->pa_type_5g = map->pa_type;
 222	efuse->lna_type_2g = map->lna_type_2g;
 223	efuse->lna_type_5g = map->lna_type_5g;
 224	if (chip->id == RTW_CHIP_TYPE_8812A) {
 225		rtw8812a_read_amplifier_type(rtwdev);
 226		rtw8812a_read_rfe_type(rtwdev, map);
 227
 228		efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(1));
 229	}
 230	efuse->channel_plan = map->channel_plan;
 231	efuse->country_code[0] = map->country_code[0];
 232	efuse->country_code[1] = map->country_code[1];
 233	efuse->bt_setting = map->rf_bt_setting;
 234	efuse->regd = map->rf_board_option & 0x7;
 235	efuse->thermal_meter[0] = map->thermal_meter;
 236	efuse->thermal_meter[1] = map->thermal_meter;
 237	efuse->thermal_meter_k = map->thermal_meter;
 238	efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g;
 239	efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g;
 240
 241	rtw88xxa_read_usb_type(rtwdev);
 242
 243	if (chip->id == RTW_CHIP_TYPE_8821A)
 244		efuse->btcoex = rtw_read32_mask(rtwdev, REG_WL_BT_PWR_CTRL,
 245						BIT_BT_FUNC_EN);
 246	else
 247		efuse->btcoex = (map->rf_board_option & 0xe0) == 0x20;
 248	efuse->share_ant = !!(efuse->bt_setting & BIT(0));
 249
 250	/* No antenna diversity because it's disabled in the vendor driver */
 251	efuse->ant_div_cfg = 0;
 252
 253	efuse->ant_div_type = map->rf_antenna_option;
 254	if (efuse->ant_div_type == 0xff)
 255		efuse->ant_div_type = 0x3;
 256
 257	for (i = 0; i < 4; i++)
 258		efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
 259
 260	switch (rtw_hci_type(rtwdev)) {
 261	case RTW_HCI_TYPE_USB:
 262		if (chip->id == RTW_CHIP_TYPE_8821A)
 263			ether_addr_copy(efuse->addr, map->rtw8821au.mac_addr);
 264		else
 265			ether_addr_copy(efuse->addr, map->rtw8812au.mac_addr);
 266		break;
 267	case RTW_HCI_TYPE_PCIE:
 268	case RTW_HCI_TYPE_SDIO:
 269	default:
 270		/* unsupported now */
 271		return -EOPNOTSUPP;
 272	}
 273
 274	return 0;
 275}
 276EXPORT_SYMBOL(rtw88xxa_read_efuse);
 277
 278static void rtw88xxa_reset_8051(struct rtw_dev *rtwdev)
 279{
 280	const struct rtw_chip_info *chip = rtwdev->chip;
 281	u8 val8;
 282
 283	/* Reset MCU IO Wrapper */
 284	rtw_write8_clr(rtwdev, REG_RSV_CTRL, BIT(1));
 285	if (chip->id == RTW_CHIP_TYPE_8812A)
 286		rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT(3));
 287	else
 288		rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT(0));
 289
 290	val8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN + 1);
 291	rtw_write8(rtwdev, REG_SYS_FUNC_EN + 1, val8 & ~BIT(2));
 292
 293	/* Enable MCU IO Wrapper */
 294	rtw_write8_clr(rtwdev, REG_RSV_CTRL, BIT(1));
 295	if (chip->id == RTW_CHIP_TYPE_8812A)
 296		rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT(3));
 297	else
 298		rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT(0));
 299
 300	rtw_write8(rtwdev, REG_SYS_FUNC_EN + 1, val8 | BIT(2));
 301}
 302
 303/* A lightweight deinit function */
 304static void rtw88xxau_hw_reset(struct rtw_dev *rtwdev)
 305{
 306	u8 val8;
 307
 308	if (!(rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_RAM_DL_SEL))
 309		return;
 310
 311	rtw88xxa_reset_8051(rtwdev);
 312	rtw_write8(rtwdev, REG_MCUFW_CTRL, 0x00);
 313
 314	/* before BB reset should do clock gated */
 315	rtw_write32_set(rtwdev, REG_FPGA0_XCD_RF_PARA, BIT(6));
 316
 317	/* reset BB */
 318	rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN, BIT(0) | BIT(1));
 319
 320	/* reset RF */
 321	rtw_write8(rtwdev, REG_RF_CTRL, 0);
 322
 323	/* reset TRX path */
 324	rtw_write16(rtwdev, REG_CR, 0);
 325
 326	/* reset MAC, reg0x5[1], auto FSM off */
 327	rtw_write8_set(rtwdev, REG_APS_FSMCO + 1, APS_FSMCO_MAC_OFF >> 8);
 328
 329	/* check if reg0x5[1] auto cleared */
 330	if (read_poll_timeout_atomic(rtw_read8, val8,
 331				     !(val8 & (APS_FSMCO_MAC_OFF >> 8)),
 332				     1, 5000, false,
 333				     rtwdev, REG_APS_FSMCO + 1))
 334		rtw_err(rtwdev, "%s: timed out waiting for 0x5[1]\n", __func__);
 335
 336	/* reg0x5[0], auto FSM on */
 337	val8 |= APS_FSMCO_MAC_ENABLE >> 8;
 338	rtw_write8(rtwdev, REG_APS_FSMCO + 1, val8);
 339
 340	rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN + 1, BIT(4) | BIT(7));
 341	rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT(4) | BIT(7));
 342}
 343
 344static int rtw88xxau_init_power_on(struct rtw_dev *rtwdev)
 345{
 346	const struct rtw_chip_info *chip = rtwdev->chip;
 347	u16 val16;
 348	int ret;
 349
 350	ret = rtw_pwr_seq_parser(rtwdev, chip->pwr_on_seq);
 351	if (ret) {
 352		rtw_err(rtwdev, "power on flow failed\n");
 353		return ret;
 354	}
 355
 356	rtw_write16(rtwdev, REG_CR, 0);
 357	val16 = BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN |
 358		BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN |
 359		BIT_MAC_SEC_EN | BIT_32K_CAL_TMR_EN;
 360	rtw_write16_set(rtwdev, REG_CR, val16);
 361
 362	if (chip->id == RTW_CHIP_TYPE_8821A) {
 363		if (rtw_read8(rtwdev, REG_SYS_CFG1 + 3) & BIT(0))
 364			rtw_write8_set(rtwdev, REG_LDO_SWR_CTRL, BIT(6));
 365	}
 366
 367	return ret;
 368}
 369
 370static int rtw88xxa_llt_write(struct rtw_dev *rtwdev, u32 address, u32 data)
 371{
 372	u32 value = BIT_LLT_WRITE_ACCESS | (address << 8) | data;
 373	int count = 0;
 374
 375	rtw_write32(rtwdev, REG_LLT_INIT, value);
 376
 377	do {
 378		if (!rtw_read32_mask(rtwdev, REG_LLT_INIT, BIT(31) | BIT(30)))
 379			break;
 380
 381		if (count > 20) {
 382			rtw_err(rtwdev, "Failed to poll write LLT done at %d!\n",
 383				address);
 384			return -EBUSY;
 385		}
 386	} while (++count);
 387
 388	return 0;
 389}
 390
 391static int rtw88xxa_llt_init(struct rtw_dev *rtwdev, u32 boundary)
 392{
 393	u32 last_entry = 255;
 394	int status = 0;
 395	u32 i;
 396
 397	for (i = 0; i < boundary - 1; i++) {
 398		status = rtw88xxa_llt_write(rtwdev, i, i + 1);
 399		if (status)
 400			return status;
 401	}
 402
 403	status = rtw88xxa_llt_write(rtwdev, boundary - 1, 0xFF);
 404	if (status)
 405		return status;
 406
 407	for (i = boundary; i < last_entry; i++) {
 408		status = rtw88xxa_llt_write(rtwdev, i, i + 1);
 409		if (status)
 410			return status;
 411	}
 412
 413	status = rtw88xxa_llt_write(rtwdev, last_entry, boundary);
 414
 415	return status;
 416}
 417
 418static void rtw88xxau_init_queue_reserved_page(struct rtw_dev *rtwdev)
 419{
 420	const struct rtw_chip_info *chip = rtwdev->chip;
 421	struct rtw_fifo_conf *fifo = &rtwdev->fifo;
 422	const struct rtw_page_table *pg_tbl = NULL;
 423	u16 pubq_num;
 424	u32 val32;
 425
 426	switch (rtw_hci_type(rtwdev)) {
 427	case RTW_HCI_TYPE_PCIE:
 428		pg_tbl = &chip->page_table[1];
 429		break;
 430	case RTW_HCI_TYPE_USB:
 431		if (rtwdev->hci.bulkout_num == 2)
 432			pg_tbl = &chip->page_table[2];
 433		else if (rtwdev->hci.bulkout_num == 3)
 434			pg_tbl = &chip->page_table[3];
 435		else if (rtwdev->hci.bulkout_num == 4)
 436			pg_tbl = &chip->page_table[4];
 437		break;
 438	case RTW_HCI_TYPE_SDIO:
 439		pg_tbl = &chip->page_table[0];
 440		break;
 441	default:
 442		break;
 443	}
 444
 445	pubq_num = fifo->acq_pg_num - pg_tbl->hq_num - pg_tbl->lq_num -
 446		   pg_tbl->nq_num - pg_tbl->exq_num - pg_tbl->gapq_num;
 447
 448	val32 = BIT_RQPN_NE(pg_tbl->nq_num, pg_tbl->exq_num);
 449	rtw_write32(rtwdev, REG_RQPN_NPQ, val32);
 450
 451	val32 = BIT_RQPN_HLP(pg_tbl->hq_num, pg_tbl->lq_num, pubq_num);
 452	rtw_write32(rtwdev, REG_RQPN, val32);
 453}
 454
 455static void rtw88xxau_init_tx_buffer_boundary(struct rtw_dev *rtwdev)
 456{
 457	struct rtw_fifo_conf *fifo = &rtwdev->fifo;
 458
 459	rtw_write8(rtwdev, REG_BCNQ_BDNY, fifo->rsvd_boundary);
 460	rtw_write8(rtwdev, REG_MGQ_BDNY, fifo->rsvd_boundary);
 461	rtw_write8(rtwdev, REG_WMAC_LBK_BF_HD, fifo->rsvd_boundary);
 462	rtw_write8(rtwdev, REG_TRXFF_BNDY, fifo->rsvd_boundary);
 463	rtw_write8(rtwdev, REG_DWBCN0_CTRL + 1, fifo->rsvd_boundary);
 464}
 465
 466static int rtw88xxau_init_queue_priority(struct rtw_dev *rtwdev)
 467{
 468	const struct rtw_chip_info *chip = rtwdev->chip;
 469	u8 bulkout_num = rtwdev->hci.bulkout_num;
 470	const struct rtw_rqpn *rqpn = NULL;
 471	u16 txdma_pq_map;
 472
 473	switch (rtw_hci_type(rtwdev)) {
 474	case RTW_HCI_TYPE_PCIE:
 475		rqpn = &chip->rqpn_table[1];
 476		break;
 477	case RTW_HCI_TYPE_USB:
 478		if (bulkout_num == 2)
 479			rqpn = &chip->rqpn_table[2];
 480		else if (bulkout_num == 3)
 481			rqpn = &chip->rqpn_table[3];
 482		else if (bulkout_num == 4)
 483			rqpn = &chip->rqpn_table[4];
 484		else
 485			return -EINVAL;
 486		break;
 487	case RTW_HCI_TYPE_SDIO:
 488		rqpn = &chip->rqpn_table[0];
 489		break;
 490	default:
 491		return -EINVAL;
 492	}
 493
 494	rtwdev->fifo.rqpn = rqpn;
 495
 496	txdma_pq_map = rtw_read16(rtwdev, REG_TXDMA_PQ_MAP) & 0x7;
 497	txdma_pq_map |= BIT_TXDMA_HIQ_MAP(rqpn->dma_map_hi);
 498	txdma_pq_map |= BIT_TXDMA_MGQ_MAP(rqpn->dma_map_mg);
 499	txdma_pq_map |= BIT_TXDMA_BKQ_MAP(rqpn->dma_map_bk);
 500	txdma_pq_map |= BIT_TXDMA_BEQ_MAP(rqpn->dma_map_be);
 501	txdma_pq_map |= BIT_TXDMA_VIQ_MAP(rqpn->dma_map_vi);
 502	txdma_pq_map |= BIT_TXDMA_VOQ_MAP(rqpn->dma_map_vo);
 503	rtw_write16(rtwdev, REG_TXDMA_PQ_MAP, txdma_pq_map);
 504
 505	/* Packet in Hi Queue Tx immediately (No constraint for ATIM Period). */
 506	if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && bulkout_num == 4)
 507		rtw_write8(rtwdev, REG_HIQ_NO_LMT_EN, 0xff);
 508
 509	return 0;
 510}
 511
 512static void rtw88xxa_init_wmac_setting(struct rtw_dev *rtwdev)
 513{
 514	rtw_write16(rtwdev, REG_RXFLTMAP0, 0xffff);
 515	rtw_write16(rtwdev, REG_RXFLTMAP1, 0x0400);
 516	rtw_write16(rtwdev, REG_RXFLTMAP2, 0xffff);
 517
 518	rtw_write32(rtwdev, REG_MAR, 0xffffffff);
 519	rtw_write32(rtwdev, REG_MAR + 4, 0xffffffff);
 520}
 521
 522static void rtw88xxa_init_adaptive_ctrl(struct rtw_dev *rtwdev)
 523{
 524	rtw_write32_mask(rtwdev, REG_RRSR, 0xfffff, 0xffff1);
 525	rtw_write16(rtwdev, REG_RETRY_LIMIT, 0x3030);
 526}
 527
 528static void rtw88xxa_init_edca(struct rtw_dev *rtwdev)
 529{
 530	rtw_write16(rtwdev, REG_SPEC_SIFS, 0x100a);
 531	rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, 0x100a);
 532
 533	rtw_write16(rtwdev, REG_SIFS, 0x100a);
 534	rtw_write16(rtwdev, REG_SIFS + 2, 0x100a);
 535
 536	rtw_write32(rtwdev, REG_EDCA_BE_PARAM, 0x005EA42B);
 537	rtw_write32(rtwdev, REG_EDCA_BK_PARAM, 0x0000A44F);
 538	rtw_write32(rtwdev, REG_EDCA_VI_PARAM, 0x005EA324);
 539	rtw_write32(rtwdev, REG_EDCA_VO_PARAM, 0x002FA226);
 540
 541	rtw_write8(rtwdev, REG_USTIME_TSF, 0x50);
 542	rtw_write8(rtwdev, REG_USTIME_EDCA, 0x50);
 543}
 544
 545static void rtw88xxau_tx_aggregation(struct rtw_dev *rtwdev)
 546{
 547	const struct rtw_chip_info *chip = rtwdev->chip;
 548
 549	rtw_write32_mask(rtwdev, REG_DWBCN0_CTRL, 0xf0,
 550			 chip->usb_tx_agg_desc_num);
 551
 552	if (chip->id == RTW_CHIP_TYPE_8821A)
 553		rtw_write8(rtwdev, REG_DWBCN1_CTRL,
 554			   chip->usb_tx_agg_desc_num << 1);
 555}
 556
 557static void rtw88xxa_init_beacon_parameters(struct rtw_dev *rtwdev)
 558{
 559	u16 val16;
 560
 561	val16 = (BIT_DIS_TSF_UDT << 8) | BIT_DIS_TSF_UDT;
 562	if (rtwdev->efuse.btcoex)
 563		val16 |= BIT_EN_BCN_FUNCTION;
 564	rtw_write16(rtwdev, REG_BCN_CTRL, val16);
 565
 566	rtw_write32_mask(rtwdev, REG_TBTT_PROHIBIT, 0xfffff, WLAN_TBTT_TIME);
 567	rtw_write8(rtwdev, REG_DRVERLYINT, 0x05);
 568	rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
 569	rtw_write16(rtwdev, REG_BCNTCFG, 0x4413);
 570}
 571
 572static void rtw88xxa_phy_bb_config(struct rtw_dev *rtwdev)
 573{
 574	u8 val8, crystal_cap;
 575
 576	/* power on BB/RF domain */
 577	val8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
 578	val8 |= BIT_FEN_USBA;
 579	rtw_write8(rtwdev, REG_SYS_FUNC_EN, val8);
 580
 581	/* toggle BB reset */
 582	val8 |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
 583	rtw_write8(rtwdev, REG_SYS_FUNC_EN, val8);
 584
 585	rtw_write8(rtwdev, REG_RF_CTRL,
 586		   BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
 587	rtw_write8(rtwdev, REG_RF_B_CTRL,
 588		   BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
 589
 590	rtw_load_table(rtwdev, rtwdev->chip->bb_tbl);
 591	rtw_load_table(rtwdev, rtwdev->chip->agc_tbl);
 592
 593	crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
 594	if (rtwdev->chip->id == RTW_CHIP_TYPE_8812A)
 595		rtw_write32_mask(rtwdev, REG_AFE_CTRL3, 0x7FF80000,
 596				 crystal_cap | (crystal_cap << 6));
 597	else
 598		rtw_write32_mask(rtwdev, REG_AFE_CTRL3, 0x00FFF000,
 599				 crystal_cap | (crystal_cap << 6));
 600}
 601
 602static void rtw88xxa_phy_rf_config(struct rtw_dev *rtwdev)
 603{
 604	u8 rf_path;
 605
 606	for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++)
 607		rtw_load_table(rtwdev, rtwdev->chip->rf_tbl[rf_path]);
 608}
 609
 610static void rtw8812a_config_1t(struct rtw_dev *rtwdev)
 611{
 612	/* BB OFDM RX Path_A */
 613	rtw_write32_mask(rtwdev, REG_RXPSEL, 0xff, 0x11);
 614
 615	/* BB OFDM TX Path_A */
 616	rtw_write32_mask(rtwdev, REG_TXPSEL, MASKLWORD, 0x1111);
 617
 618	/* BB CCK R/Rx Path_A */
 619	rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0c000000, 0x0);
 620
 621	/* MCS support */
 622	rtw_write32_mask(rtwdev, REG_RX_MCS_LIMIT, 0xc0000060, 0x4);
 623
 624	/* RF Path_B HSSI OFF */
 625	rtw_write32_mask(rtwdev, REG_3WIRE_SWB, 0xf, 0x4);
 626
 627	/* RF Path_B Power Down */
 628	rtw_write32_mask(rtwdev, REG_LSSI_WRITE_B, MASKDWORD, 0);
 629
 630	/* ADDA Path_B OFF */
 631	rtw_write32_mask(rtwdev, REG_AFE_PWR1_B, MASKDWORD, 0);
 632	rtw_write32_mask(rtwdev, REG_AFE_PWR2_B, MASKDWORD, 0);
 633}
 634
 635static const u32 rtw88xxa_txscale_tbl[] = {
 636	0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
 637	0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
 638	0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
 639	0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
 640};
 641
 642static u32 rtw88xxa_get_bb_swing(struct rtw_dev *rtwdev, u8 band, u8 path)
 643{
 644	static const u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6};
 645	struct rtw_efuse *efuse = &rtwdev->efuse;
 646	u8 tx_bb_swing;
 647
 648	if (band == RTW_BAND_2G)
 649		tx_bb_swing = efuse->tx_bb_swing_setting_2g;
 650	else
 651		tx_bb_swing = efuse->tx_bb_swing_setting_5g;
 652
 653	if (path == RF_PATH_B)
 654		tx_bb_swing >>= 2;
 655	tx_bb_swing &= 0x3;
 656
 657	return swing2setting[tx_bb_swing];
 658}
 659
 660static u8 rtw88xxa_get_swing_index(struct rtw_dev *rtwdev)
 661{
 662	u32 swing, table_value;
 663	u8 i;
 664
 665	swing = rtw88xxa_get_bb_swing(rtwdev, rtwdev->hal.current_band_type,
 666				      RF_PATH_A);
 667
 668	for (i = 0; i < ARRAY_SIZE(rtw88xxa_txscale_tbl); i++) {
 669		table_value = rtw88xxa_txscale_tbl[i];
 670		if (swing == table_value)
 671			return i;
 672	}
 673
 674	return 24;
 675}
 676
 677static void rtw88xxa_pwrtrack_init(struct rtw_dev *rtwdev)
 678{
 679	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
 680	u8 path;
 681
 682	dm_info->default_ofdm_index = rtw88xxa_get_swing_index(rtwdev);
 683
 684	if (rtwdev->chip->id == RTW_CHIP_TYPE_8821A)
 685		dm_info->default_cck_index = 0;
 686	else
 687		dm_info->default_cck_index = 24;
 688
 689	for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
 690		ewma_thermal_init(&dm_info->avg_thermal[path]);
 691		dm_info->delta_power_index[path] = 0;
 692		dm_info->delta_power_index_last[path] = 0;
 693	}
 694
 695	dm_info->pwr_trk_triggered = false;
 696	dm_info->pwr_trk_init_trigger = true;
 697	dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
 698}
 699
 700void rtw88xxa_power_off(struct rtw_dev *rtwdev,
 701			const struct rtw_pwr_seq_cmd *const *enter_lps_flow)
 702{
 703	struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev);
 704	enum usb_device_speed speed = rtwusb->udev->speed;
 705	u16 ori_fsmc0;
 706	u8 reg_cr;
 707
 708	reg_cr = rtw_read8(rtwdev, REG_CR);
 709
 710	/* Already powered off */
 711	if (reg_cr == 0 || reg_cr == 0xEA)
 712		return;
 713
 714	rtw_hci_stop(rtwdev);
 715
 716	if (!rtwdev->efuse.btcoex)
 717		rtw_write16_clr(rtwdev, REG_GPIO_MUXCFG, BIT_EN_SIC);
 718
 719	/* set Reg 0xf008[3:4] to 2'11 to enable U1/U2 Mode in USB3.0. */
 720	if (speed == USB_SPEED_SUPER)
 721		rtw_write8_set(rtwdev, REG_USB_MOD, 0x18);
 722
 723	rtw_write32(rtwdev, REG_HISR0, 0xffffffff);
 724	rtw_write32(rtwdev, REG_HISR1, 0xffffffff);
 725	rtw_write32(rtwdev, REG_HIMR0, 0);
 726	rtw_write32(rtwdev, REG_HIMR1, 0);
 727
 728	if (rtwdev->efuse.btcoex)
 729		rtw_coex_power_off_setting(rtwdev);
 730
 731	ori_fsmc0 = rtw_read16(rtwdev, REG_APS_FSMCO);
 732	rtw_write16(rtwdev, REG_APS_FSMCO, ori_fsmc0 & ~APS_FSMCO_HW_POWERDOWN);
 733
 734	/* Stop Tx Report Timer. */
 735	rtw_write8_clr(rtwdev, REG_TX_RPT_CTRL, BIT(1));
 736
 737	/* Stop Rx */
 738	rtw_write8(rtwdev, REG_CR, 0);
 739
 740	rtw_pwr_seq_parser(rtwdev, enter_lps_flow);
 741
 742	if (rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_RAM_DL_SEL)
 743		rtw88xxa_reset_8051(rtwdev);
 744
 745	rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN + 1, BIT(2));
 746	rtw_write8(rtwdev, REG_MCUFW_CTRL, 0);
 747
 748	rtw_pwr_seq_parser(rtwdev, rtwdev->chip->pwr_off_seq);
 749
 750	if (ori_fsmc0 & APS_FSMCO_HW_POWERDOWN)
 751		rtw_write16_set(rtwdev, REG_APS_FSMCO, APS_FSMCO_HW_POWERDOWN);
 752
 753	clear_bit(RTW_FLAG_POWERON, rtwdev->flags);
 754}
 755EXPORT_SYMBOL(rtw88xxa_power_off);
 756
 757static void rtw88xxa_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 band)
 758{
 759	rtw_write32_mask(rtwdev, REG_TXSCALE_A, BB_SWING_MASK,
 760			 rtw88xxa_get_bb_swing(rtwdev, band, RF_PATH_A));
 761	rtw_write32_mask(rtwdev, REG_TXSCALE_B, BB_SWING_MASK,
 762			 rtw88xxa_get_bb_swing(rtwdev, band, RF_PATH_B));
 763	rtw88xxa_pwrtrack_init(rtwdev);
 764}
 765
 766static void rtw8821a_set_ext_band_switch(struct rtw_dev *rtwdev, u8 band)
 767{
 768	rtw_write32_mask(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN, 0);
 769	rtw_write32_mask(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL, 1);
 770	rtw_write32_mask(rtwdev, REG_RFE_INV_A, 0xf, 7);
 771	rtw_write32_mask(rtwdev, REG_RFE_INV_A, 0xf0, 7);
 772
 773	if (band == RTW_BAND_2G)
 774		rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(29) | BIT(28), 1);
 775	else
 776		rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(29) | BIT(28), 2);
 777}
 778
 779static void rtw8821a_phy_set_rfe_reg_24g(struct rtw_dev *rtwdev)
 780{
 781	struct rtw_efuse *efuse = &rtwdev->efuse;
 782
 783	/* Turn off RF PA and LNA */
 784
 785	/* 0xCB0[15:12] = 0x7 (LNA_On)*/
 786	rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xF000, 0x7);
 787	/* 0xCB0[7:4] = 0x7 (PAPE_A)*/
 788	rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xF0, 0x7);
 789
 790	if (efuse->ext_lna_2g) {
 791		/* Turn on 2.4G External LNA */
 792		rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(20), 1);
 793		rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(22), 0);
 794		rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(2, 0), 0x2);
 795		rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(10, 8), 0x2);
 796	} else {
 797		/* Bypass 2.4G External LNA */
 798		rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(20), 0);
 799		rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(22), 0);
 800		rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(2, 0), 0x7);
 801		rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(10, 8), 0x7);
 802	}
 803}
 804
 805static void rtw8821a_phy_set_rfe_reg_5g(struct rtw_dev *rtwdev)
 806{
 807	/* Turn ON RF PA and LNA */
 808
 809	/* 0xCB0[15:12] = 0x7 (LNA_On)*/
 810	rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xF000, 0x5);
 811	/* 0xCB0[7:4] = 0x7 (PAPE_A)*/
 812	rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xF0, 0x4);
 813
 814	/* Bypass 2.4G External LNA */
 815	rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(20), 0);
 816	rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(22), 0);
 817	rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(2, 0), 0x7);
 818	rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(10, 8), 0x7);
 819}
 820
 821static void rtw8812a_phy_set_rfe_reg_24g(struct rtw_dev *rtwdev)
 822{
 823	switch (rtwdev->efuse.rfe_option) {
 824	case 0:
 825	case 2:
 826		rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777);
 827		rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
 828		rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x000);
 829		rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000);
 830		break;
 831	case 1:
 832		if (rtwdev->efuse.btcoex) {
 833			rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xffffff, 0x777777);
 834			rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
 835			rtw_write32_mask(rtwdev, REG_RFE_INV_A, 0x33f00000, 0x000);
 836			rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000);
 837		} else {
 838			rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777);
 839			rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
 840			rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x000);
 841			rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000);
 842		}
 843		break;
 844	case 3:
 845		rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x54337770);
 846		rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x54337770);
 847		rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x010);
 848		rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x010);
 849		rtw_write32_mask(rtwdev, REG_ANTSEL_SW, 0x00000303, 0x1);
 850		break;
 851	case 4:
 852		rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777);
 853		rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
 854		rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x001);
 855		rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x001);
 856		break;
 857	case 5:
 858		rtw_write8(rtwdev, REG_RFE_PINMUX_A + 2, 0x77);
 859		rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
 860		rtw_write8_clr(rtwdev, REG_RFE_INV_A + 3, BIT(0));
 861		rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000);
 862		break;
 863	case 6:
 864		rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x07772770);
 865		rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x07772770);
 866		rtw_write32(rtwdev, REG_RFE_INV_A, 0x00000077);
 867		rtw_write32(rtwdev, REG_RFE_INV_B, 0x00000077);
 868		break;
 869	default:
 870		break;
 871	}
 872}
 873
 874static void rtw8812a_phy_set_rfe_reg_5g(struct rtw_dev *rtwdev)
 875{
 876	switch (rtwdev->efuse.rfe_option) {
 877	case 0:
 878		rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77337717);
 879		rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77337717);
 880		rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x010);
 881		rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x010);
 882		break;
 883	case 1:
 884		if (rtwdev->efuse.btcoex) {
 885			rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xffffff, 0x337717);
 886			rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77337717);
 887			rtw_write32_mask(rtwdev, REG_RFE_INV_A, 0x33f00000, 0x000);
 888			rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000);
 889		} else {
 890			rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77337717);
 891			rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77337717);
 892			rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x000);
 893			rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000);
 894		}
 895		break;
 896	case 2:
 897	case 4:
 898		rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77337777);
 899		rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77337777);
 900		rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x010);
 901		rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x010);
 902		break;
 903	case 3:
 904		rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x54337717);
 905		rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x54337717);
 906		rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x010);
 907		rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x010);
 908		rtw_write32_mask(rtwdev, REG_ANTSEL_SW, 0x00000303, 0x1);
 909		break;
 910	case 5:
 911		rtw_write8(rtwdev, REG_RFE_PINMUX_A + 2, 0x33);
 912		rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77337777);
 913		rtw_write8_set(rtwdev, REG_RFE_INV_A + 3, BIT(0));
 914		rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x010);
 915		break;
 916	case 6:
 917		rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x07737717);
 918		rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x07737717);
 919		rtw_write32(rtwdev, REG_RFE_INV_A, 0x00000077);
 920		rtw_write32(rtwdev, REG_RFE_INV_B, 0x00000077);
 921		break;
 922	default:
 923		break;
 924	}
 925}
 926
 927static void rtw88xxa_switch_band(struct rtw_dev *rtwdev, u8 new_band, u8 bw)
 928{
 929	const struct rtw_chip_info *chip = rtwdev->chip;
 930	u16 basic_rates, reg_41a;
 931
 932	/* 8811au one antenna module doesn't support antenna div, so driver must
 933	 * control antenna band, otherwise one of the band will have issue
 934	 */
 935	if (chip->id == RTW_CHIP_TYPE_8821A && !rtwdev->efuse.btcoex &&
 936	    rtwdev->efuse.ant_div_cfg == 0)
 937		rtw8821a_set_ext_band_switch(rtwdev, new_band);
 938
 939	if (new_band == RTW_BAND_2G) {
 940		rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
 941
 942		if (chip->id == RTW_CHIP_TYPE_8821A) {
 943			rtw8821a_phy_set_rfe_reg_24g(rtwdev);
 944
 945			rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0);
 946		} else {
 947			rtw_write32_mask(rtwdev, REG_BWINDICATION, 0x3, 0x1);
 948			rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(17, 13), 0x17);
 949
 950			if (bw == RTW_CHANNEL_WIDTH_20 &&
 951			    rtwdev->hal.rf_type == RF_1T1R &&
 952			    !rtwdev->efuse.ext_lna_2g)
 953				rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(3, 1), 0x02);
 954			else
 955				rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(3, 1), 0x04);
 956
 957			rtw_write32_mask(rtwdev, REG_CCASEL, 0x3, 0);
 958
 959			rtw8812a_phy_set_rfe_reg_24g(rtwdev);
 960		}
 961
 962		rtw_write32_mask(rtwdev, REG_TXPSEL, 0xf0, 0x1);
 963		rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0x1);
 964
 965		basic_rates = BIT(DESC_RATE1M) | BIT(DESC_RATE2M) |
 966			      BIT(DESC_RATE5_5M) | BIT(DESC_RATE11M) |
 967			      BIT(DESC_RATE6M) | BIT(DESC_RATE12M) |
 968			      BIT(DESC_RATE24M);
 969		rtw_write32_mask(rtwdev, REG_RRSR, 0xfffff, basic_rates);
 970
 971		rtw_write8_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
 972	} else { /* RTW_BAND_5G */
 973		if (chip->id == RTW_CHIP_TYPE_8821A)
 974			rtw8821a_phy_set_rfe_reg_5g(rtwdev);
 975
 976		rtw_write8_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
 977
 978		read_poll_timeout_atomic(rtw_read16, reg_41a, (reg_41a & 0x30) == 0x30,
 979					 50, 2500, false, rtwdev, REG_TXPKT_EMPTY);
 980
 981		rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
 982
 983		if (chip->id == RTW_CHIP_TYPE_8821A) {
 984			rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 1);
 985		} else {
 986			rtw_write32_mask(rtwdev, REG_BWINDICATION, 0x3, 0x2);
 987			rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(17, 13), 0x15);
 988			rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(3, 1), 0x04);
 989
 990			rtw_write32_mask(rtwdev, REG_CCASEL, 0x3, 1);
 991
 992			rtw8812a_phy_set_rfe_reg_5g(rtwdev);
 993		}
 994
 995		rtw_write32_mask(rtwdev, REG_TXPSEL, 0xf0, 0);
 996		rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0xf);
 997
 998		basic_rates = BIT(DESC_RATE6M) | BIT(DESC_RATE12M) |
 999			      BIT(DESC_RATE24M);
1000		rtw_write32_mask(rtwdev, REG_RRSR, 0xfffff, basic_rates);
1001	}
1002
1003	rtw88xxa_set_channel_bb_swing(rtwdev, new_band);
1004}
1005
1006int rtw88xxa_power_on(struct rtw_dev *rtwdev)
1007{
1008	struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev);
1009	const struct rtw_chip_info *chip = rtwdev->chip;
1010	struct rtw_efuse *efuse = &rtwdev->efuse;
1011	struct rtw_hal *hal = &rtwdev->hal;
1012	int ret;
1013
1014	if (test_bit(RTW_FLAG_POWERON, rtwdev->flags))
1015		return 0;
1016
1017	/* Override rtw_chip_efuse_info_setup() */
1018	if (chip->id == RTW_CHIP_TYPE_8821A)
1019		efuse->btcoex = rtw_read32_mask(rtwdev, REG_WL_BT_PWR_CTRL,
1020						BIT_BT_FUNC_EN);
1021
1022	/* Override rtw_chip_efuse_info_setup() */
1023	if (chip->id == RTW_CHIP_TYPE_8812A)
1024		rtw8812a_read_amplifier_type(rtwdev);
1025
1026	ret = rtw_hci_setup(rtwdev);
1027	if (ret) {
1028		rtw_err(rtwdev, "failed to setup hci\n");
1029		goto err;
1030	}
1031
1032	/* Revise for U2/U3 switch we can not update RF-A/B reset.
1033	 * Reset after MAC power on to prevent RF R/W error.
1034	 * Is it a right method?
1035	 */
1036	if (chip->id == RTW_CHIP_TYPE_8812A) {
1037		rtw_write8(rtwdev, REG_RF_CTRL, 5);
1038		rtw_write8(rtwdev, REG_RF_CTRL, 7);
1039		rtw_write8(rtwdev, REG_RF_B_CTRL, 5);
1040		rtw_write8(rtwdev, REG_RF_B_CTRL, 7);
1041	}
1042
1043	/* If HW didn't go through a complete de-initial procedure,
1044	 * it probably occurs some problem for double initial
1045	 * procedure.
1046	 */
1047	rtw88xxau_hw_reset(rtwdev);
1048
1049	ret = rtw88xxau_init_power_on(rtwdev);
1050	if (ret) {
1051		rtw_err(rtwdev, "failed to power on\n");
1052		goto err;
1053	}
1054
1055	ret = rtw_set_trx_fifo_info(rtwdev);
1056	if (ret) {
1057		rtw_err(rtwdev, "failed to set trx fifo info\n");
1058		goto err;
1059	}
1060
1061	ret = rtw88xxa_llt_init(rtwdev, rtwdev->fifo.rsvd_boundary);
1062	if (ret) {
1063		rtw_err(rtwdev, "failed to init llt\n");
1064		goto err;
1065	}
1066
1067	rtw_write32_set(rtwdev, REG_TXDMA_OFFSET_CHK, BIT_DROP_DATA_EN);
1068
1069	ret = rtw_wait_firmware_completion(rtwdev);
1070	if (ret) {
1071		rtw_err(rtwdev, "failed to wait firmware completion\n");
1072		goto err_off;
1073	}
1074
1075	ret = rtw_download_firmware(rtwdev, &rtwdev->fw);
1076	if (ret) {
1077		rtw_err(rtwdev, "failed to download firmware\n");
1078		goto err_off;
1079	}
1080
1081	rtw_write8(rtwdev, REG_HMETFR, 0xf);
1082
1083	rtw_load_table(rtwdev, chip->mac_tbl);
1084
1085	rtw88xxau_init_queue_reserved_page(rtwdev);
1086	rtw88xxau_init_tx_buffer_boundary(rtwdev);
1087	rtw88xxau_init_queue_priority(rtwdev);
1088
1089	rtw_write16(rtwdev, REG_TRXFF_BNDY + 2,
1090		    chip->rxff_size - REPORT_BUF - 1);
1091
1092	if (chip->id == RTW_CHIP_TYPE_8812A)
1093		rtw_write8(rtwdev, REG_PBP,
1094			   u8_encode_bits(PBP_512, PBP_TX_MASK) |
1095			   u8_encode_bits(PBP_64, PBP_RX_MASK));
1096
1097	rtw_write8(rtwdev, REG_RX_DRVINFO_SZ, PHY_STATUS_SIZE);
1098
1099	rtw_write32(rtwdev, REG_HIMR0, 0);
1100	rtw_write32(rtwdev, REG_HIMR1, 0);
1101
1102	rtw_write32_mask(rtwdev, REG_CR, 0x30000, 0x2);
1103
1104	rtw88xxa_init_wmac_setting(rtwdev);
1105	rtw88xxa_init_adaptive_ctrl(rtwdev);
1106	rtw88xxa_init_edca(rtwdev);
1107
1108	rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL, BIT(7));
1109	rtw_write8(rtwdev, REG_ACKTO, 0x80);
1110
1111	rtw88xxau_tx_aggregation(rtwdev);
1112
1113	rtw88xxa_init_beacon_parameters(rtwdev);
1114	rtw_write8(rtwdev, REG_BCN_MAX_ERR, 0xff);
1115
1116	rtw_hci_interface_cfg(rtwdev);
1117
1118	/* usb3 rx interval */
1119	rtw_write8(rtwdev, REG_USB3_RXITV, 0x01);
1120
1121	/* burst length=4, set 0x3400 for burst length=2 */
1122	rtw_write16(rtwdev, REG_RXDMA_STATUS, 0x7400);
1123	rtw_write8(rtwdev, REG_RXDMA_STATUS + 1, 0xf5);
1124
1125	/* 0x456 = 0x70, sugguested by Zhilin */
1126	if (chip->id == RTW_CHIP_TYPE_8821A)
1127		rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, 0x5e);
1128	else
1129		rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, 0x70);
1130
1131	rtw_write32(rtwdev, REG_AMPDU_MAX_LENGTH, 0xffffffff);
1132	rtw_write8(rtwdev, REG_USTIME_TSF, 0x50);
1133	rtw_write8(rtwdev, REG_USTIME_EDCA, 0x50);
1134
1135	if (rtwusb->udev->speed == USB_SPEED_SUPER)
1136		/* Disable U1/U2 Mode to avoid 2.5G spur in USB3.0. */
1137		rtw_write8_clr(rtwdev, REG_USB_MOD, BIT(4) | BIT(3));
1138
1139	rtw_write8_set(rtwdev, REG_SINGLE_AMPDU_CTRL, BIT_EN_SINGLE_APMDU);
1140
1141	/* for VHT packet length 11K */
1142	rtw_write8(rtwdev, REG_RX_PKT_LIMIT, 0x18);
1143
1144	rtw_write8(rtwdev, REG_PIFS, 0x00);
1145
1146	if (chip->id == RTW_CHIP_TYPE_8821A) {
1147		/* 0x0a0a too small, it can't pass AC logo. change to 0x1f1f */
1148		rtw_write16(rtwdev, REG_MAX_AGGR_NUM, 0x1f1f);
1149		rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, 0x80);
1150		rtw_write32(rtwdev, REG_FAST_EDCA_CTRL, 0x03087777);
1151	} else {
1152		rtw_write16(rtwdev, REG_MAX_AGGR_NUM, 0x1f1f);
1153		rtw_write8_clr(rtwdev, REG_FWHW_TXQ_CTRL, BIT(7));
1154	}
1155
1156	 /* to prevent mac is reseted by bus. */
1157	rtw_write8_set(rtwdev, REG_RSV_CTRL, BIT(5) | BIT(6));
1158
1159	/* ARFB table 9 for 11ac 5G 2SS */
1160	rtw_write32(rtwdev, REG_ARFR0, 0x00000010);
1161	rtw_write32(rtwdev, REG_ARFRH0, 0xfffff000);
1162
1163	/* ARFB table 10 for 11ac 5G 1SS */
1164	rtw_write32(rtwdev, REG_ARFR1_V1, 0x00000010);
1165	rtw_write32(rtwdev, REG_ARFRH1_V1, 0x003ff000);
1166
1167	/* ARFB table 11 for 11ac 24G 1SS */
1168	rtw_write32(rtwdev, REG_ARFR2_V1, 0x00000015);
1169	rtw_write32(rtwdev, REG_ARFRH2_V1, 0x003ff000);
1170
1171	/* ARFB table 12 for 11ac 24G 2SS */
1172	rtw_write32(rtwdev, REG_ARFR3_V1, 0x00000015);
1173	rtw_write32(rtwdev, REG_ARFRH3_V1, 0xffcff000);
1174
1175	rtw_write8_set(rtwdev, REG_CR, BIT_MACTXEN | BIT_MACRXEN);
1176
1177	rtw88xxa_phy_bb_config(rtwdev);
1178	rtw88xxa_phy_rf_config(rtwdev);
1179
1180	if (chip->id == RTW_CHIP_TYPE_8812A && hal->rf_path_num == 1)
1181		rtw8812a_config_1t(rtwdev);
1182
1183	rtw88xxa_switch_band(rtwdev, RTW_BAND_2G, RTW_CHANNEL_WIDTH_20);
1184
1185	rtw_write32(rtwdev, RTW_SEC_CMD_REG, BIT(31) | BIT(30));
1186
1187	rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0xff);
1188	rtw_write32(rtwdev, REG_BAR_MODE_CTRL, 0x0201ffff);
1189	rtw_write8(rtwdev, REG_NAV_CTRL + 2, 0);
1190
1191	rtw_write8_clr(rtwdev, REG_GPIO_MUXCFG, BIT(5));
1192
1193	rtw_phy_init(rtwdev);
1194
1195	rtw88xxa_pwrtrack_init(rtwdev);
1196
1197	/* 0x4c6[3] 1: RTS BW = Data BW
1198	 * 0: RTS BW depends on CCA / secondary CCA result.
1199	 */
1200	rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT(3));
1201
1202	/* enable Tx report. */
1203	rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, 0x0f);
1204
1205	/* Pretx_en, for WEP/TKIP SEC */
1206	rtw_write8(rtwdev, REG_EARLY_MODE_CONTROL + 3, 0x01);
1207
1208	rtw_write16(rtwdev, REG_TX_RPT_TIME, 0x3df0);
1209
1210	/* Reset USB mode switch setting */
1211	rtw_write8(rtwdev, REG_SYS_SDIO_CTRL, 0x0);
1212	rtw_write8(rtwdev, REG_ACLK_MON, 0x0);
1213
1214	rtw_write8(rtwdev, REG_USB_HRPWM, 0);
1215
1216	/* ack for xmit mgmt frames. */
1217	rtw_write32_set(rtwdev, REG_FWHW_TXQ_CTRL, BIT(12));
1218
1219	hal->cck_high_power = rtw_read32_mask(rtwdev, REG_CCK_RPT_FORMAT,
1220					      BIT_CCK_RPT_FORMAT);
1221
1222	ret = rtw_hci_start(rtwdev);
1223	if (ret) {
1224		rtw_err(rtwdev, "failed to start hci\n");
1225		goto err_off;
1226	}
1227
1228	if (efuse->btcoex) {
1229		rtw_coex_power_on_setting(rtwdev);
1230		rtw_coex_init_hw_config(rtwdev, false);
1231	}
1232
1233	set_bit(RTW_FLAG_POWERON, rtwdev->flags);
1234
1235	return 0;
1236
1237err_off:
1238	chip->ops->power_off(rtwdev);
1239
1240err:
1241	return ret;
1242}
1243EXPORT_SYMBOL(rtw88xxa_power_on);
1244
1245u32 rtw88xxa_phy_read_rf(struct rtw_dev *rtwdev,
1246			 enum rtw_rf_path rf_path, u32 addr, u32 mask)
1247{
1248	static const u32 pi_addr[2] = { REG_3WIRE_SWA, REG_3WIRE_SWB };
1249	static const u32 read_addr[2][2] = {
1250		{ REG_SI_READ_A, REG_SI_READ_B },
1251		{ REG_PI_READ_A, REG_PI_READ_B }
1252	};
1253	const struct rtw_chip_info *chip = rtwdev->chip;
1254	const struct rtw_hal *hal = &rtwdev->hal;
1255	bool set_cca, pi_mode;
1256	u32 val;
1257
1258	if (rf_path >= hal->rf_phy_num) {
1259		rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1260		return INV_RF_DATA;
1261	}
1262
1263	/* CCA off to avoid reading the wrong value.
1264	 * Toggling CCA would affect RF 0x0, skip it.
1265	 */
1266	set_cca = addr != 0x0 && chip->id == RTW_CHIP_TYPE_8812A &&
1267		  hal->cut_version != RTW_CHIP_VER_CUT_C;
1268
1269	if (set_cca)
1270		rtw_write32_set(rtwdev, REG_CCA2ND, BIT(3));
1271
1272	addr &= 0xff;
1273
1274	pi_mode = rtw_read32_mask(rtwdev, pi_addr[rf_path], 0x4);
1275
1276	rtw_write32_mask(rtwdev, REG_HSSI_READ, MASKBYTE0, addr);
1277
1278	if (chip->id == RTW_CHIP_TYPE_8821A ||
1279	    hal->cut_version == RTW_CHIP_VER_CUT_C)
1280		udelay(20);
1281
1282	val = rtw_read32_mask(rtwdev, read_addr[pi_mode][rf_path], mask);
1283
1284	/* CCA on */
1285	if (set_cca)
1286		rtw_write32_clr(rtwdev, REG_CCA2ND, BIT(3));
1287
1288	return val;
1289}
1290EXPORT_SYMBOL(rtw88xxa_phy_read_rf);
1291
1292static void rtw8812a_phy_fix_spur(struct rtw_dev *rtwdev, u8 channel, u8 bw)
1293{
1294	/* C cut Item12 ADC FIFO CLOCK */
1295	if (rtwdev->hal.cut_version == RTW_CHIP_VER_CUT_C) {
1296		if (bw == RTW_CHANNEL_WIDTH_40 && channel == 11)
1297			rtw_write32_mask(rtwdev, REG_ADCCLK, 0xC00, 0x3);
1298		else
1299			rtw_write32_mask(rtwdev, REG_ADCCLK, 0xC00, 0x2);
1300
1301		/* A workaround to resolve 2480Mhz spur by setting ADC clock
1302		 * as 160M.
1303		 */
1304		if (bw == RTW_CHANNEL_WIDTH_20 && (channel == 13 || channel == 14)) {
1305			rtw_write32_mask(rtwdev, REG_ADCCLK, 0x300, 0x3);
1306			rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 1);
1307		} else if (bw == RTW_CHANNEL_WIDTH_40 && channel == 11) {
1308			rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 1);
1309		} else if (bw != RTW_CHANNEL_WIDTH_80) {
1310			rtw_write32_mask(rtwdev, REG_ADCCLK, 0x300, 0x2);
1311			rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0);
1312		}
1313	} else {
1314		/* A workaround to resolve 2480Mhz spur by setting ADC clock
1315		 * as 160M.
1316		 */
1317		if (bw == RTW_CHANNEL_WIDTH_20 && (channel == 13 || channel == 14))
1318			rtw_write32_mask(rtwdev, REG_ADCCLK, 0x300, 0x3);
1319		else if (channel <= 14) /* 2.4G only */
1320			rtw_write32_mask(rtwdev, REG_ADCCLK, 0x300, 0x2);
1321	}
1322}
1323
1324static void rtw88xxa_switch_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw)
1325{
1326	struct rtw_hal *hal = &rtwdev->hal;
1327	u32 fc_area, rf_mod_ag;
1328	u8 path;
1329
1330	switch (channel) {
1331	case 36 ... 48:
1332		fc_area = 0x494;
1333		break;
1334	case 50 ... 64:
1335		fc_area = 0x453;
1336		break;
1337	case 100 ... 116:
1338		fc_area = 0x452;
1339		break;
1340	default:
1341		if (channel >= 118)
1342			fc_area = 0x412;
1343		else
1344			fc_area = 0x96a;
1345		break;
1346	}
1347
1348	rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, fc_area);
1349
1350	for (path = 0; path < hal->rf_path_num; path++) {
1351		switch (channel) {
1352		case 36 ... 64:
1353			rf_mod_ag = 0x101;
1354			break;
1355		case 100 ... 140:
1356			rf_mod_ag = 0x301;
1357			break;
1358		default:
1359			if (channel > 140)
1360				rf_mod_ag = 0x501;
1361			else
1362				rf_mod_ag = 0x000;
1363			break;
1364		}
1365
1366		rtw_write_rf(rtwdev, path, RF_CFGCH,
1367			     RF18_RFSI_MASK | RF18_BAND_MASK, rf_mod_ag);
1368
1369		if (rtwdev->chip->id == RTW_CHIP_TYPE_8812A)
1370			rtw8812a_phy_fix_spur(rtwdev, channel, bw);
1371
1372		rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_CHANNEL_MASK, channel);
1373	}
1374}
1375
1376static void rtw88xxa_set_reg_bw(struct rtw_dev *rtwdev, u8 bw)
1377{
1378	u16 val16 = rtw_read16(rtwdev, REG_WMAC_TRXPTCL_CTL);
1379
1380	val16 &= ~BIT_RFMOD;
1381	if (bw == RTW_CHANNEL_WIDTH_80)
1382		val16 |= BIT_RFMOD_80M;
1383	else if (bw == RTW_CHANNEL_WIDTH_40)
1384		val16 |= BIT_RFMOD_40M;
1385
1386	rtw_write16(rtwdev, REG_WMAC_TRXPTCL_CTL, val16);
1387}
1388
1389static void rtw88xxa_post_set_bw_mode(struct rtw_dev *rtwdev, u8 channel,
1390				      u8 bw, u8 primary_chan_idx)
1391{
1392	struct rtw_hal *hal = &rtwdev->hal;
1393	u8 txsc40 = 0, txsc20, txsc;
1394	u8 reg_837, l1pkval;
1395
1396	rtw88xxa_set_reg_bw(rtwdev, bw);
1397
1398	txsc20 = primary_chan_idx;
1399	if (bw == RTW_CHANNEL_WIDTH_80) {
1400		if (txsc20 == RTW_SC_20_UPPER || txsc20 == RTW_SC_20_UPMOST)
1401			txsc40 = RTW_SC_40_UPPER;
1402		else
1403			txsc40 = RTW_SC_40_LOWER;
1404	}
1405
1406	txsc = BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40);
1407	rtw_write8(rtwdev, REG_DATA_SC, txsc);
1408
1409	reg_837 = rtw_read8(rtwdev, REG_BWINDICATION + 3);
1410
1411	switch (bw) {
1412	default:
1413	case RTW_CHANNEL_WIDTH_20:
1414		rtw_write32_mask(rtwdev, REG_ADCCLK, 0x003003C3, 0x00300200);
1415		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0);
1416
1417		if (hal->rf_type == RF_2T2R)
1418			rtw_write32_mask(rtwdev, REG_L1PKTH, 0x03C00000, 7);
1419		else
1420			rtw_write32_mask(rtwdev, REG_L1PKTH, 0x03C00000, 8);
1421
1422		break;
1423	case RTW_CHANNEL_WIDTH_40:
1424		rtw_write32_mask(rtwdev, REG_ADCCLK, 0x003003C3, 0x00300201);
1425		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0);
1426		rtw_write32_mask(rtwdev, REG_ADCCLK, 0x3C, txsc);
1427		rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0000000, txsc);
1428
1429		if (reg_837 & BIT(2)) {
1430			l1pkval = 6;
1431		} else {
1432			if (hal->rf_type == RF_2T2R)
1433				l1pkval = 7;
1434			else
1435				l1pkval = 8;
1436		}
1437
1438		rtw_write32_mask(rtwdev, REG_L1PKTH, 0x03C00000, l1pkval);
1439
1440		if (txsc == RTW_SC_20_UPPER)
1441			rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
1442		else
1443			rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
1444
1445		break;
1446	case RTW_CHANNEL_WIDTH_80:
1447		rtw_write32_mask(rtwdev, REG_ADCCLK, 0x003003C3, 0x00300202);
1448		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 1);
1449		rtw_write32_mask(rtwdev, REG_ADCCLK, 0x3C, txsc);
1450		rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0000000, txsc);
1451
1452		if (reg_837 & BIT(2)) {
1453			l1pkval = 5;
1454		} else {
1455			if (hal->rf_type == RF_2T2R)
1456				l1pkval = 6;
1457			else
1458				l1pkval = 7;
1459		}
1460
1461		rtw_write32_mask(rtwdev, REG_L1PKTH, 0x03C00000, l1pkval);
1462
1463		break;
1464	}
1465}
1466
1467static void rtw88xxa_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
1468{
1469	u8 path;
1470
1471	for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
1472		switch (bw) {
1473		case RTW_CHANNEL_WIDTH_5:
1474		case RTW_CHANNEL_WIDTH_10:
1475		case RTW_CHANNEL_WIDTH_20:
1476		default:
1477			rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 3);
1478			break;
1479		case RTW_CHANNEL_WIDTH_40:
1480			rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 1);
1481			break;
1482		case RTW_CHANNEL_WIDTH_80:
1483			rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 0);
1484			break;
1485		}
1486	}
1487}
1488
1489void rtw88xxa_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
1490			  u8 primary_chan_idx)
1491{
1492	u8 old_band, new_band;
1493
1494	if (rtw_read8(rtwdev, REG_CCK_CHECK) & BIT_CHECK_CCK_EN)
1495		old_band = RTW_BAND_5G;
1496	else
1497		old_band = RTW_BAND_2G;
1498
1499	if (channel > 14)
1500		new_band = RTW_BAND_5G;
1501	else
1502		new_band = RTW_BAND_2G;
1503
1504	if (new_band != old_band)
1505		rtw88xxa_switch_band(rtwdev, new_band, bw);
1506
1507	rtw88xxa_switch_channel(rtwdev, channel, bw);
1508
1509	rtw88xxa_post_set_bw_mode(rtwdev, channel, bw, primary_chan_idx);
1510
1511	if (rtwdev->chip->id == RTW_CHIP_TYPE_8812A)
1512		rtw8812a_phy_fix_spur(rtwdev, channel, bw);
1513
1514	rtw88xxa_set_channel_rf(rtwdev, channel, bw);
1515}
1516EXPORT_SYMBOL(rtw88xxa_set_channel);
1517
1518void rtw88xxa_query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
1519			       struct rtw_rx_pkt_stat *pkt_stat,
1520			       s8 (*cck_rx_pwr)(u8 lna_idx, u8 vga_idx))
1521{
1522	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1523	struct rtw_jaguar_phy_status_rpt *rpt;
1524	u8 gain[RTW_RF_PATH_MAX], rssi, i;
1525	s8 rx_pwr_db, power_a, power_b;
1526	const s8 min_rx_power = -120;
1527	u8 lna_idx, vga_idx;
1528
1529	rpt = (struct rtw_jaguar_phy_status_rpt *)phy_status;
1530
1531	if (pkt_stat->rate <= DESC_RATE11M) {
1532		lna_idx = le32_get_bits(rpt->w1, RTW_JGRPHY_W1_AGC_RPT_LNA_IDX);
1533		vga_idx = le32_get_bits(rpt->w1, RTW_JGRPHY_W1_AGC_RPT_VGA_IDX);
1534
1535		rx_pwr_db = cck_rx_pwr(lna_idx, vga_idx);
1536
1537		pkt_stat->rx_power[RF_PATH_A] = rx_pwr_db;
1538		pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
1539		dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
1540		pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
1541		pkt_stat->signal_power = rx_pwr_db;
1542	} else { /* OFDM rate */
1543		gain[RF_PATH_A] = le32_get_bits(rpt->w0, RTW_JGRPHY_W0_GAIN_A);
1544		gain[RF_PATH_B] = le32_get_bits(rpt->w0, RTW_JGRPHY_W0_GAIN_B);
1545
1546		for (i = RF_PATH_A; i < rtwdev->hal.rf_path_num; i++) {
1547			pkt_stat->rx_power[i] = gain[i] - 110;
1548			rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[i], 1);
1549			dm_info->rssi[i] = rssi;
1550		}
1551
1552		pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power,
1553							 rtwdev->hal.rf_path_num);
1554
1555		power_a = pkt_stat->rx_power[RF_PATH_A];
1556		power_b = pkt_stat->rx_power[RF_PATH_B];
1557		if (rtwdev->hal.rf_path_num == 1)
1558			power_b = power_a;
1559
1560		pkt_stat->signal_power = max3(power_a, power_b, min_rx_power);
1561	}
1562}
1563EXPORT_SYMBOL(rtw88xxa_query_phy_status);
1564
1565static void
1566rtw88xxa_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path,
1567				    u8 rs, u32 *phy_pwr_idx)
1568{
1569	static const u32 offset_txagc[2] = {
1570		REG_TX_AGC_A_CCK_11_CCK_1, REG_TX_AGC_B_CCK_11_CCK_1
1571	};
1572	u8 rate, rate_idx, pwr_index, shift;
1573	struct rtw_hal *hal = &rtwdev->hal;
1574	bool write_1ss_mcs9;
1575	u32 mask;
1576	int j;
1577
1578	for (j = 0; j < rtw_rate_size[rs]; j++) {
1579		rate = rtw_rate_section[rs][j];
1580
1581		pwr_index = hal->tx_pwr_tbl[path][rate];
1582
1583		shift = rate & 0x3;
1584		*phy_pwr_idx |= ((u32)pwr_index << (shift * 8));
1585
1586		write_1ss_mcs9 = rate == DESC_RATEVHT1SS_MCS9 &&
1587				 hal->rf_path_num == 1;
1588
1589		if (write_1ss_mcs9)
1590			mask = MASKLWORD;
1591		else
1592			mask = MASKDWORD;
1593
1594		if (shift == 0x3 || write_1ss_mcs9) {
1595			rate_idx = rate & 0xfc;
1596			if (rate >= DESC_RATEVHT1SS_MCS0)
1597				rate_idx -= 0x10;
1598
1599			rtw_write32_mask(rtwdev, offset_txagc[path] + rate_idx,
1600					 mask, *phy_pwr_idx);
1601
1602			*phy_pwr_idx = 0;
1603		}
1604	}
1605}
1606
1607static void rtw88xxa_tx_power_training(struct rtw_dev *rtwdev, u8 bw,
1608				       u8 channel, u8 path)
1609{
1610	static const u32 write_offset[] = {
1611		REG_TX_PWR_TRAINING_A, REG_TX_PWR_TRAINING_B,
1612	};
1613	u32 power_level, write_data;
1614	u8 i;
1615
1616	power_level = rtwdev->hal.tx_pwr_tbl[path][DESC_RATEMCS7];
1617	write_data = 0;
1618
1619	for (i = 0; i < 3; i++) {
1620		if (i == 0)
1621			power_level -= 10;
1622		else if (i == 1)
1623			power_level -= 8;
1624		else
1625			power_level -= 6;
1626
1627		write_data |= max_t(u32, power_level, 2) << (i * 8);
1628	}
1629
1630	rtw_write32_mask(rtwdev, write_offset[path], 0xffffff, write_data);
1631}
1632
1633void rtw88xxa_set_tx_power_index(struct rtw_dev *rtwdev)
1634{
1635	struct rtw_hal *hal = &rtwdev->hal;
1636	u32 phy_pwr_idx = 0;
1637	int rs, path;
1638
1639	for (path = 0; path < hal->rf_path_num; path++) {
1640		for (rs = 0; rs <= __RTW_RATE_SECTION_2SS_MAX; rs++) {
1641			if (hal->rf_path_num == 1 &&
1642			    (rs == RTW_RATE_SECTION_HT_2S ||
1643			     rs == RTW_RATE_SECTION_VHT_2S))
1644				continue;
1645
1646			if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags) &&
1647			    rs > RTW_RATE_SECTION_OFDM)
1648				continue;
1649
1650			if (hal->current_band_type == RTW_BAND_5G &&
1651			    rs == RTW_RATE_SECTION_CCK)
1652				continue;
1653
1654			rtw88xxa_set_tx_power_index_by_rate(rtwdev, path, rs,
1655							    &phy_pwr_idx);
1656		}
1657
1658		rtw88xxa_tx_power_training(rtwdev, hal->current_band_width,
1659					   hal->current_channel, path);
1660	}
1661}
1662EXPORT_SYMBOL(rtw88xxa_set_tx_power_index);
1663
1664void rtw88xxa_false_alarm_statistics(struct rtw_dev *rtwdev)
1665{
1666	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1667	u32 cck_fa_cnt, ofdm_fa_cnt;
1668	u32 crc32_cnt, cca32_cnt;
1669	u32 cck_enable;
1670
1671	cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28);
1672	cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK);
1673	ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM);
1674
1675	dm_info->cck_fa_cnt = cck_fa_cnt;
1676	dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
1677	dm_info->total_fa_cnt = ofdm_fa_cnt;
1678	if (cck_enable)
1679		dm_info->total_fa_cnt += cck_fa_cnt;
1680
1681	crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK);
1682	dm_info->cck_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
1683	dm_info->cck_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD);
1684
1685	crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM);
1686	dm_info->ofdm_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
1687	dm_info->ofdm_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD);
1688
1689	crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT);
1690	dm_info->ht_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
1691	dm_info->ht_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD);
1692
1693	crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT);
1694	dm_info->vht_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
1695	dm_info->vht_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD);
1696
1697	cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM);
1698	dm_info->ofdm_cca_cnt = u32_get_bits(cca32_cnt, MASKHWORD);
1699	dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
1700	if (cck_enable) {
1701		cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK);
1702		dm_info->cck_cca_cnt = u32_get_bits(cca32_cnt, MASKLWORD);
1703		dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
1704	}
1705
1706	rtw_write32_set(rtwdev, REG_FAS, BIT(17));
1707	rtw_write32_clr(rtwdev, REG_FAS, BIT(17));
1708	rtw_write32_clr(rtwdev, REG_CCK0_FAREPORT, BIT(15));
1709	rtw_write32_set(rtwdev, REG_CCK0_FAREPORT, BIT(15));
1710	rtw_write32_set(rtwdev, REG_CNTRST, BIT(0));
1711	rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0));
1712}
1713EXPORT_SYMBOL(rtw88xxa_false_alarm_statistics);
1714
1715void rtw88xxa_iqk_backup_mac_bb(struct rtw_dev *rtwdev,
1716				u32 *macbb_backup,
1717				const u32 *backup_macbb_reg,
1718				u32 macbb_num)
1719{
1720	u32 i;
1721
1722	/* [31] = 0 --> Page C */
1723	rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
1724
1725	/* save MACBB default value */
1726	for (i = 0; i < macbb_num; i++)
1727		macbb_backup[i] = rtw_read32(rtwdev, backup_macbb_reg[i]);
1728}
1729EXPORT_SYMBOL(rtw88xxa_iqk_backup_mac_bb);
1730
1731void rtw88xxa_iqk_backup_afe(struct rtw_dev *rtwdev, u32 *afe_backup,
1732			     const u32 *backup_afe_reg, u32 afe_num)
1733{
1734	u32 i;
1735
1736	/* [31] = 0 --> Page C */
1737	rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
1738
1739	/* Save AFE Parameters */
1740	for (i = 0; i < afe_num; i++)
1741		afe_backup[i] = rtw_read32(rtwdev, backup_afe_reg[i]);
1742}
1743EXPORT_SYMBOL(rtw88xxa_iqk_backup_afe);
1744
1745void rtw88xxa_iqk_restore_mac_bb(struct rtw_dev *rtwdev,
1746				 u32 *macbb_backup,
1747				 const u32 *backup_macbb_reg,
1748				 u32 macbb_num)
1749{
1750	u32 i;
1751
1752	/* [31] = 0 --> Page C */
1753	rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
1754
1755	/* Reload MacBB Parameters */
1756	for (i = 0; i < macbb_num; i++)
1757		rtw_write32(rtwdev, backup_macbb_reg[i], macbb_backup[i]);
1758}
1759EXPORT_SYMBOL(rtw88xxa_iqk_restore_mac_bb);
1760
1761void rtw88xxa_iqk_configure_mac(struct rtw_dev *rtwdev)
1762{
1763	/* [31] = 0 --> Page C */
1764	rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
1765
1766	rtw_write8(rtwdev, REG_TXPAUSE, 0x3f);
1767	rtw_write32_mask(rtwdev, REG_BCN_CTRL,
1768			 (BIT_EN_BCN_FUNCTION << 8) | BIT_EN_BCN_FUNCTION, 0x0);
1769
1770	/* RX ante off */
1771	rtw_write8(rtwdev, REG_RXPSEL, 0x00);
1772
1773	/* CCA off */
1774	rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf, 0xc);
1775
1776	/* CCK RX path off */
1777	rtw_write8(rtwdev, REG_CCK_RX + 3, 0xf);
1778}
1779EXPORT_SYMBOL(rtw88xxa_iqk_configure_mac);
1780
1781bool rtw88xxa_iqk_finish(int average, int threshold,
1782			 int *x_temp, int *y_temp, int *x, int *y,
1783			 bool break_inner, bool break_outer)
1784{
1785	bool finish = false;
1786	int i, ii, dx, dy;
1787
1788	for (i = 0; i < average; i++) {
1789		for (ii = i + 1; ii < average; ii++) {
1790			dx = abs_diff(x_temp[i] >> 21, x_temp[ii] >> 21);
1791			dy = abs_diff(y_temp[i] >> 21, y_temp[ii] >> 21);
1792
1793			if (dx < threshold && dy < threshold) {
1794				*x = ((x_temp[i] >> 21) + (x_temp[ii] >> 21));
1795				*y = ((y_temp[i] >> 21) + (y_temp[ii] >> 21));
1796
1797				*x /= 2;
1798				*y /= 2;
1799
1800				finish = true;
1801
1802				if (break_inner)
1803					break;
1804			}
1805		}
1806
1807		if (finish && break_outer)
1808			break;
1809	}
1810
1811	return finish;
1812}
1813EXPORT_SYMBOL(rtw88xxa_iqk_finish);
1814
1815static void rtw88xxa_pwrtrack_set(struct rtw_dev *rtwdev, u8 tx_rate, u8 path)
1816{
1817	static const u32 reg_txscale[2] = { REG_TXSCALE_A, REG_TXSCALE_B };
1818	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1819	u8 cck_swing_idx, ofdm_swing_idx;
1820	u8 pwr_tracking_limit;
1821
1822	switch (tx_rate) {
1823	case DESC_RATE1M ... DESC_RATE11M:
1824		pwr_tracking_limit = 32;
1825		break;
1826	case DESC_RATE6M ... DESC_RATE48M:
1827	case DESC_RATEMCS3 ... DESC_RATEMCS4:
1828	case DESC_RATEMCS11 ... DESC_RATEMCS12:
1829	case DESC_RATEVHT1SS_MCS3 ... DESC_RATEVHT1SS_MCS4:
1830	case DESC_RATEVHT2SS_MCS3 ... DESC_RATEVHT2SS_MCS4:
1831		pwr_tracking_limit = 30;
1832		break;
1833	case DESC_RATE54M:
1834	case DESC_RATEMCS5 ... DESC_RATEMCS7:
1835	case DESC_RATEMCS13 ... DESC_RATEMCS15:
1836	case DESC_RATEVHT1SS_MCS5 ... DESC_RATEVHT1SS_MCS6:
1837	case DESC_RATEVHT2SS_MCS5 ... DESC_RATEVHT2SS_MCS6:
1838		pwr_tracking_limit = 28;
1839		break;
1840	case DESC_RATEMCS0 ... DESC_RATEMCS2:
1841	case DESC_RATEMCS8 ... DESC_RATEMCS10:
1842	case DESC_RATEVHT1SS_MCS0 ... DESC_RATEVHT1SS_MCS2:
1843	case DESC_RATEVHT2SS_MCS0 ... DESC_RATEVHT2SS_MCS2:
1844		pwr_tracking_limit = 34;
1845		break;
1846	case DESC_RATEVHT1SS_MCS7:
1847	case DESC_RATEVHT2SS_MCS7:
1848		pwr_tracking_limit = 26;
1849		break;
1850	default:
1851	case DESC_RATEVHT1SS_MCS8:
1852	case DESC_RATEVHT2SS_MCS8:
1853		pwr_tracking_limit = 24;
1854		break;
1855	case DESC_RATEVHT1SS_MCS9:
1856	case DESC_RATEVHT2SS_MCS9:
1857		pwr_tracking_limit = 22;
1858		break;
1859	}
1860
1861	cck_swing_idx = dm_info->delta_power_index[path] + dm_info->default_cck_index;
1862	ofdm_swing_idx = dm_info->delta_power_index[path] + dm_info->default_ofdm_index;
1863
1864	if (ofdm_swing_idx > pwr_tracking_limit) {
1865		if (path == RF_PATH_A)
1866			dm_info->txagc_remnant_cck = cck_swing_idx - pwr_tracking_limit;
1867		dm_info->txagc_remnant_ofdm[path] = ofdm_swing_idx - pwr_tracking_limit;
1868
1869		ofdm_swing_idx = pwr_tracking_limit;
1870	} else if (ofdm_swing_idx == 0) {
1871		if (path == RF_PATH_A)
1872			dm_info->txagc_remnant_cck = cck_swing_idx;
1873		dm_info->txagc_remnant_ofdm[path] = ofdm_swing_idx;
1874	} else {
1875		if (path == RF_PATH_A)
1876			dm_info->txagc_remnant_cck = 0;
1877		dm_info->txagc_remnant_ofdm[path] = 0;
1878	}
1879
1880	rtw_write32_mask(rtwdev, reg_txscale[path], GENMASK(31, 21),
1881			 rtw88xxa_txscale_tbl[ofdm_swing_idx]);
1882}
1883
1884void rtw88xxa_phy_pwrtrack(struct rtw_dev *rtwdev,
1885			   void (*do_lck)(struct rtw_dev *rtwdev),
1886			   void (*do_iqk)(struct rtw_dev *rtwdev))
1887{
1888	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1889	struct rtw_hal *hal = &rtwdev->hal;
1890	struct rtw_swing_table swing_table;
1891	s8 remnant_pre[RTW_RF_PATH_MAX];
1892	u8 thermal_value, delta, path;
1893	bool need_iqk;
1894
1895	rtw_phy_config_swing_table(rtwdev, &swing_table);
1896
1897	if (rtwdev->efuse.thermal_meter[0] == 0xff) {
1898		pr_err_once("efuse thermal meter is 0xff\n");
1899		return;
1900	}
1901
1902	thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1903
1904	rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A);
1905
1906	need_iqk = rtw_phy_pwrtrack_need_iqk(rtwdev);
1907
1908	if (need_iqk && do_lck)
1909		do_lck(rtwdev);
1910
1911	if (dm_info->pwr_trk_init_trigger)
1912		dm_info->pwr_trk_init_trigger = false;
1913	else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value,
1914						   RF_PATH_A))
1915		goto iqk;
1916
1917	delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A);
1918
1919	for (path = RF_PATH_A; path < hal->rf_path_num; path++) {
1920		remnant_pre[path] = dm_info->txagc_remnant_ofdm[path];
1921
1922		dm_info->delta_power_index[path] =
1923			rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, path,
1924						    RF_PATH_A, delta);
1925
1926		if (dm_info->delta_power_index[path] !=
1927		    dm_info->delta_power_index_last[path]) {
1928			dm_info->delta_power_index_last[path] =
1929				dm_info->delta_power_index[path];
1930
1931			rtw88xxa_pwrtrack_set(rtwdev, dm_info->tx_rate, path);
1932		}
1933	}
1934
1935	for (path = RF_PATH_A; path < hal->rf_path_num; path++) {
1936		if (remnant_pre[path] != dm_info->txagc_remnant_ofdm[path]) {
1937			rtw_phy_set_tx_power_level(rtwdev,
1938						   hal->current_channel);
1939			break;
1940		}
1941	}
1942
1943iqk:
1944	if (need_iqk)
1945		do_iqk(rtwdev);
1946}
1947EXPORT_SYMBOL(rtw88xxa_phy_pwrtrack);
1948
1949void rtw88xxa_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
1950{
1951	static const u8 pd[CCK_PD_LV_MAX] = {0x40, 0x83, 0xcd, 0xdd, 0xed};
1952	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1953
1954	/* Override rtw_phy_cck_pd_lv_link(). It implements something
1955	 * like type 2/3/4. We need type 1 here.
1956	 */
1957	if (rtw_is_assoc(rtwdev)) {
1958		if (dm_info->min_rssi > 60) {
1959			new_lvl = CCK_PD_LV3;
1960		} else if (dm_info->min_rssi > 35) {
1961			new_lvl = CCK_PD_LV2;
1962		} else if (dm_info->min_rssi > 20) {
1963			if (dm_info->cck_fa_avg > 500)
1964				new_lvl = CCK_PD_LV2;
1965			else if (dm_info->cck_fa_avg < 250)
1966				new_lvl = CCK_PD_LV1;
1967			else
1968				return;
1969		} else {
1970			new_lvl = CCK_PD_LV1;
1971		}
1972	}
1973
1974	rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n",
1975		dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl);
1976
1977	if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl)
1978		return;
1979
1980	dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
1981	dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl;
1982
1983	rtw_write8(rtwdev, REG_CCK_PD_TH, pd[new_lvl]);
1984}
1985EXPORT_SYMBOL(rtw88xxa_phy_cck_pd_set);
1986
1987MODULE_AUTHOR("Realtek Corporation");
1988MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821a/8811a/8812a common code");
1989MODULE_LICENSE("Dual BSD/GPL");