rtw8814a.c

   1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2/* Copyright(c) 2025  Realtek Corporation
   3 */
   4
   5#include <linux/usb.h>
   6#include "main.h"
   7#include "coex.h"
   8#include "tx.h"
   9#include "phy.h"
  10#include "rtw8814a.h"
  11#include "rtw8814a_table.h"
  12#include "rtw88xxa.h"
  13#include "reg.h"
  14#include "debug.h"
  15#include "efuse.h"
  16#include "regd.h"
  17#include "usb.h"
  18
  19static void rtw8814a_efuse_grant(struct rtw_dev *rtwdev, bool on)
  20{
  21	if (on) {
  22		rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON);
  23
  24		rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_ELDR);
  25		rtw_write16_set(rtwdev, REG_SYS_CLKR,
  26				BIT_LOADER_CLK_EN | BIT_ANA8M);
  27	} else {
  28		rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
  29	}
  30}
  31
  32static void rtw8814a_read_rfe_type(struct rtw_dev *rtwdev)
  33{
  34	struct rtw_efuse *efuse = &rtwdev->efuse;
  35
  36	if (!(efuse->rfe_option & BIT(7)))
  37		return;
  38
  39	if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE)
  40		efuse->rfe_option = 0;
  41	else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB)
  42		efuse->rfe_option = 1;
  43}
  44
  45static void rtw8814a_read_amplifier_type(struct rtw_dev *rtwdev)
  46{
  47	struct rtw_efuse *efuse = &rtwdev->efuse;
  48
  49	switch (efuse->rfe_option) {
  50	case 1:
  51		/* Internal 2G */
  52		efuse->pa_type_2g = 0;
  53		efuse->lna_type_2g = 0;
  54		/* External 5G */
  55		efuse->pa_type_5g = BIT(0);
  56		efuse->lna_type_5g = BIT(3);
  57		break;
  58	case 2 ... 5:
  59		/* External everything */
  60		efuse->pa_type_2g = BIT(4);
  61		efuse->lna_type_2g = BIT(3);
  62		efuse->pa_type_5g = BIT(0);
  63		efuse->lna_type_5g = BIT(3);
  64		break;
  65	case 6:
  66		efuse->lna_type_5g = BIT(3);
  67		break;
  68	default:
  69		break;
  70	}
  71}
  72
  73static void rtw8814a_read_rf_type(struct rtw_dev *rtwdev,
  74				  struct rtw8814a_efuse *map)
  75{
  76	struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev);
  77	struct rtw_hal *hal = &rtwdev->hal;
  78
  79	switch (map->trx_antenna_option) {
  80	case 0xff: /* 4T4R */
  81	case 0xee: /* 3T3R */
  82		if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB &&
  83		    rtwusb->udev->speed != USB_SPEED_SUPER)
  84			hal->rf_type = RF_2T2R;
  85		else
  86			hal->rf_type = RF_3T3R;
  87
  88		break;
  89	case 0x66: /* 2T2R */
  90	case 0x6f: /* 2T4R */
  91	default:
  92		hal->rf_type = RF_2T2R;
  93		break;
  94	}
  95
  96	hal->rf_path_num = 4;
  97	hal->rf_phy_num = 4;
  98
  99	if (hal->rf_type == RF_3T3R) {
 100		hal->antenna_rx = BB_PATH_ABC;
 101		hal->antenna_tx = BB_PATH_ABC;
 102	} else {
 103		hal->antenna_rx = BB_PATH_AB;
 104		hal->antenna_tx = BB_PATH_AB;
 105	}
 106}
 107
 108static void rtw8814a_init_hwcap(struct rtw_dev *rtwdev)
 109{
 110	struct rtw_efuse *efuse = &rtwdev->efuse;
 111	struct rtw_hal *hal = &rtwdev->hal;
 112
 113	efuse->hw_cap.bw = BIT(RTW_CHANNEL_WIDTH_20) |
 114			   BIT(RTW_CHANNEL_WIDTH_40) |
 115			   BIT(RTW_CHANNEL_WIDTH_80);
 116	efuse->hw_cap.ptcl = EFUSE_HW_CAP_PTCL_VHT;
 117
 118	if (hal->rf_type == RF_3T3R)
 119		efuse->hw_cap.nss = 3;
 120	else
 121		efuse->hw_cap.nss = 2;
 122
 123	rtw_dbg(rtwdev, RTW_DBG_EFUSE,
 124		"hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n",
 125		efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl,
 126		efuse->hw_cap.ant_num, efuse->hw_cap.nss);
 127}
 128
 129static int rtw8814a_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
 130{
 131	struct rtw_efuse *efuse = &rtwdev->efuse;
 132	struct rtw8814a_efuse *map;
 133	int i;
 134
 135	if (rtw_dbg_is_enabled(rtwdev, RTW_DBG_EFUSE))
 136		print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
 137			       log_map, rtwdev->chip->log_efuse_size, true);
 138
 139	map = (struct rtw8814a_efuse *)log_map;
 140
 141	efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(4));
 142	efuse->rfe_option = map->rfe_option;
 143	efuse->rf_board_option = map->rf_board_option;
 144	efuse->crystal_cap = map->xtal_k;
 145	efuse->channel_plan = map->channel_plan;
 146	efuse->country_code[0] = map->country_code[0];
 147	efuse->country_code[1] = map->country_code[1];
 148	efuse->bt_setting = map->rf_bt_setting;
 149	efuse->regd = map->rf_board_option & 0x7;
 150	efuse->thermal_meter[RF_PATH_A] = map->thermal_meter;
 151	efuse->thermal_meter_k = map->thermal_meter;
 152	efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g;
 153	efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g;
 154
 155	rtw8814a_read_rfe_type(rtwdev);
 156	rtw8814a_read_amplifier_type(rtwdev);
 157
 158	/* Override rtw_chip_parameter_setup() */
 159	rtw8814a_read_rf_type(rtwdev, map);
 160
 161	rtw8814a_init_hwcap(rtwdev);
 162
 163	for (i = 0; i < 4; i++)
 164		efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
 165
 166	switch (rtw_hci_type(rtwdev)) {
 167	case RTW_HCI_TYPE_USB:
 168		ether_addr_copy(efuse->addr, map->u.mac_addr);
 169		break;
 170	case RTW_HCI_TYPE_PCIE:
 171		ether_addr_copy(efuse->addr, map->e.mac_addr);
 172		break;
 173	case RTW_HCI_TYPE_SDIO:
 174	default:
 175		/* unsupported now */
 176		return -EOPNOTSUPP;
 177	}
 178
 179	return 0;
 180}
 181
 182static void rtw8814a_init_rfe_reg(struct rtw_dev *rtwdev)
 183{
 184	u8 rfe_option = rtwdev->efuse.rfe_option;
 185
 186	if (rfe_option == 2 || rfe_option == 1) {
 187		rtw_write32_mask(rtwdev, 0x1994, 0xf, 0xf);
 188		rtw_write8_set(rtwdev, REG_GPIO_MUXCFG + 2, 0xf0);
 189	} else if (rfe_option == 0) {
 190		rtw_write32_mask(rtwdev, 0x1994, 0xf, 0xf);
 191		rtw_write8_set(rtwdev, REG_GPIO_MUXCFG + 2, 0xc0);
 192	}
 193}
 194
 195#define RTW_TXSCALE_SIZE 37
 196static const u32 rtw8814a_txscale_tbl[RTW_TXSCALE_SIZE] = {
 197	0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
 198	0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
 199	0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
 200	0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
 201};
 202
 203static u32 rtw8814a_get_bb_swing(struct rtw_dev *rtwdev, u8 band, u8 rf_path)
 204{
 205	static const u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6};
 206	struct rtw_efuse *efuse = &rtwdev->efuse;
 207	u8 tx_bb_swing;
 208
 209	if (band == RTW_BAND_2G)
 210		tx_bb_swing = efuse->tx_bb_swing_setting_2g;
 211	else
 212		tx_bb_swing = efuse->tx_bb_swing_setting_5g;
 213
 214	tx_bb_swing >>= 2 * rf_path;
 215	tx_bb_swing &= 0x3;
 216
 217	return swing2setting[tx_bb_swing];
 218}
 219
 220static u8 rtw8814a_get_swing_index(struct rtw_dev *rtwdev)
 221{
 222	u32 swing, table_value;
 223	u8 i;
 224
 225	swing = rtw8814a_get_bb_swing(rtwdev, rtwdev->hal.current_band_type,
 226				      RF_PATH_A);
 227
 228	for (i = 0; i < ARRAY_SIZE(rtw8814a_txscale_tbl); i++) {
 229		table_value = rtw8814a_txscale_tbl[i];
 230		if (swing == table_value)
 231			return i;
 232	}
 233
 234	return 24;
 235}
 236
 237static void rtw8814a_pwrtrack_init(struct rtw_dev *rtwdev)
 238{
 239	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
 240	u8 path;
 241
 242	dm_info->default_ofdm_index = rtw8814a_get_swing_index(rtwdev);
 243
 244	for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
 245		ewma_thermal_init(&dm_info->avg_thermal[path]);
 246		dm_info->delta_power_index[path] = 0;
 247		dm_info->delta_power_index_last[path] = 0;
 248	}
 249	dm_info->pwr_trk_triggered = false;
 250	dm_info->pwr_trk_init_trigger = true;
 251	dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
 252}
 253
 254static void rtw8814a_config_trx_path(struct rtw_dev *rtwdev)
 255{
 256	/* RX CCK disable 2R CCA */
 257	rtw_write32_clr(rtwdev, REG_CCK0_FAREPORT,
 258			BIT_CCK0_2RX | BIT_CCK0_MRC);
 259	/* pathB tx on, path A/C/D tx off */
 260	rtw_write32_mask(rtwdev, REG_CCK_RX, 0xf0000000, 0x4);
 261	/* pathB rx */
 262	rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0x5);
 263}
 264
 265static void rtw8814a_config_cck_rx_antenna_init(struct rtw_dev *rtwdev)
 266{
 267	/* CCK 2R CCA parameters */
 268
 269	/* Disable Ant diversity */
 270	rtw_write32_mask(rtwdev, REG_RXSB, BIT_RXSB_ANA_DIV, 0x0);
 271	/* Concurrent CCA at LSB & USB */
 272	rtw_write32_mask(rtwdev, REG_CCA, BIT_CCA_CO, 0);
 273	/* RX path diversity enable */
 274	rtw_write32_mask(rtwdev, REG_ANTSEL, BIT_ANT_BYCO, 0);
 275	/* r_en_mrc_antsel */
 276	rtw_write32_mask(rtwdev, REG_PRECTRL, BIT_DIS_CO_PATHSEL, 0);
 277	/* MBC weighting */
 278	rtw_write32_mask(rtwdev, REG_CCA_MF, BIT_MBC_WIN, 1);
 279	/* 2R CCA only */
 280	rtw_write32_mask(rtwdev, REG_CCKTX, BIT_CMB_CCA_2R, 1);
 281}
 282
 283static void rtw8814a_phy_set_param(struct rtw_dev *rtwdev)
 284{
 285	u32 crystal_cap, val32;
 286	u8 val8, rf_path;
 287
 288	/* power on BB/RF domain */
 289	if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB)
 290		rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_USBA);
 291	else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE)
 292		rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_PCIEA);
 293
 294	rtw_write8_set(rtwdev, REG_SYS_CFG3_8814A + 2,
 295		       BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB);
 296
 297	/* Power on RF paths A..D */
 298	val8 = BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB;
 299	rtw_write8(rtwdev, REG_RF_CTRL, val8);
 300	rtw_write8(rtwdev, REG_RF_CTRL1, val8);
 301	rtw_write8(rtwdev, REG_RF_CTRL2, val8);
 302	rtw_write8(rtwdev, REG_RF_CTRL3, val8);
 303
 304	rtw_load_table(rtwdev, rtwdev->chip->bb_tbl);
 305	rtw_load_table(rtwdev, rtwdev->chip->agc_tbl);
 306
 307	crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
 308	crystal_cap |= crystal_cap << 6;
 309	rtw_write32_mask(rtwdev, REG_AFE_CTRL3, 0x07ff8000, crystal_cap);
 310
 311	rtw8814a_config_trx_path(rtwdev);
 312
 313	for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++)
 314		rtw_load_table(rtwdev, rtwdev->chip->rf_tbl[rf_path]);
 315
 316	val32 = rtw_read_rf(rtwdev, RF_PATH_A, RF_RCK1_V1, RFREG_MASK);
 317	rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK1_V1, RFREG_MASK, val32);
 318	rtw_write_rf(rtwdev, RF_PATH_C, RF_RCK1_V1, RFREG_MASK, val32);
 319	rtw_write_rf(rtwdev, RF_PATH_D, RF_RCK1_V1, RFREG_MASK, val32);
 320
 321	rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
 322
 323	rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0xFF);
 324
 325	rtw_write32(rtwdev, REG_BAR_MODE_CTRL, 0x0201ffff);
 326
 327	rtw_write8(rtwdev, REG_MISC_CTRL, BIT_DIS_SECOND_CCA);
 328
 329	rtw_write8(rtwdev, REG_NAV_CTRL + 2, 0);
 330
 331	rtw_write8_clr(rtwdev, REG_GPIO_MUXCFG, BIT(5));
 332
 333	rtw8814a_config_cck_rx_antenna_init(rtwdev);
 334
 335	rtw_phy_init(rtwdev);
 336	rtw8814a_pwrtrack_init(rtwdev);
 337
 338	rtw8814a_init_rfe_reg(rtwdev);
 339
 340	rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT(3));
 341
 342	rtw_write8(rtwdev, REG_NAV_CTRL + 2, 235);
 343
 344	/* enable Tx report. */
 345	rtw_write8(rtwdev,  REG_FWHW_TXQ_CTRL + 1, 0x1F);
 346
 347	if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) {
 348		/* Reset USB mode switch setting */
 349		rtw_write8(rtwdev, REG_SYS_SDIO_CTRL, 0x0);
 350		rtw_write8(rtwdev, REG_ACLK_MON, 0x0);
 351	}
 352}
 353
 354static void rtw8814ae_enable_rf_1_2v(struct rtw_dev *rtwdev)
 355{
 356	/* This is for fullsize card, because GPIO7 there is floating.
 357	 * We should pull GPIO7 high to enable RF 1.2V Switch Power Supply
 358	 */
 359
 360	/* 1. set 0x40[1:0] to 0, BIT_GPIOSEL=0, select pin as GPIO */
 361	rtw_write8_clr(rtwdev, REG_GPIO_MUXCFG, BIT(1) | BIT(0));
 362
 363	/* 2. set 0x44[31] to 0
 364	 * mode=0: data port;
 365	 * mode=1 and BIT_GPIO_IO_SEL=0: interrupt mode;
 366	 */
 367	rtw_write8_clr(rtwdev, REG_GPIO_PIN_CTRL + 3, BIT(7));
 368
 369	/* 3. data mode
 370	 * 3.1 set 0x44[23] to 1
 371	 * sel=0: input;
 372	 * sel=1: output;
 373	 */
 374	rtw_write8_set(rtwdev, REG_GPIO_PIN_CTRL + 2, BIT(7));
 375
 376	/* 3.2 set 0x44[15] to 1
 377	 * output high value;
 378	 */
 379	rtw_write8_set(rtwdev, REG_GPIO_PIN_CTRL + 1, BIT(7));
 380}
 381
 382static int rtw8814a_mac_init(struct rtw_dev *rtwdev)
 383{
 384	struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev);
 385
 386	rtw_write16(rtwdev, REG_CR,
 387		    MAC_TRX_ENABLE | BIT_MAC_SEC_EN | BIT_32K_CAL_TMR_EN);
 388
 389	rtw_load_table(rtwdev, rtwdev->chip->mac_tbl);
 390
 391	if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB)
 392		rtw_write8(rtwdev, REG_AUTO_LLT_V1 + 3,
 393			   rtwdev->chip->usb_tx_agg_desc_num << 1);
 394
 395	rtw_write32(rtwdev, REG_HIMR0, 0);
 396	rtw_write32(rtwdev, REG_HIMR1, 0);
 397
 398	rtw_write32_mask(rtwdev, REG_RRSR, 0xfffff, 0xfffff);
 399
 400	rtw_write16(rtwdev, REG_RETRY_LIMIT, 0x3030);
 401
 402	rtw_write16(rtwdev, REG_RXFLTMAP0, 0xffff);
 403	rtw_write16(rtwdev, REG_RXFLTMAP1, 0x0400);
 404	rtw_write16(rtwdev, REG_RXFLTMAP2, 0xffff);
 405
 406	rtw_write8(rtwdev, REG_MAX_AGGR_NUM, 0x36);
 407	rtw_write8(rtwdev, REG_MAX_AGGR_NUM + 1, 0x36);
 408
 409	/* Set Spec SIFS (used in NAV) */
 410	rtw_write16(rtwdev, REG_SPEC_SIFS, 0x100a);
 411	rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, 0x100a);
 412
 413	/* Set SIFS for CCK */
 414	rtw_write16(rtwdev, REG_SIFS, 0x100a);
 415
 416	/* Set SIFS for OFDM */
 417	rtw_write16(rtwdev, REG_SIFS + 2, 0x100a);
 418
 419	/* TXOP */
 420	rtw_write32(rtwdev, REG_EDCA_BE_PARAM, 0x005EA42B);
 421	rtw_write32(rtwdev, REG_EDCA_BK_PARAM, 0x0000A44F);
 422	rtw_write32(rtwdev, REG_EDCA_VI_PARAM, 0x005EA324);
 423	rtw_write32(rtwdev, REG_EDCA_VO_PARAM, 0x002FA226);
 424
 425	rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL, BIT(7));
 426
 427	rtw_write8(rtwdev, REG_ACKTO, 0x80);
 428
 429	rtw_write16(rtwdev, REG_BCN_CTRL,
 430		    BIT_DIS_TSF_UDT | (BIT_DIS_TSF_UDT << 8));
 431	rtw_write32_mask(rtwdev, REG_TBTT_PROHIBIT, 0xfffff, WLAN_TBTT_TIME);
 432	rtw_write8(rtwdev, REG_DRVERLYINT, 0x05);
 433	rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
 434	rtw_write16(rtwdev, REG_BCNTCFG, 0x4413);
 435	rtw_write8(rtwdev, REG_BCN_MAX_ERR, 0xFF);
 436
 437	rtw_write32(rtwdev, REG_FAST_EDCA_VOVI_SETTING, 0x08070807);
 438	rtw_write32(rtwdev, REG_FAST_EDCA_BEBK_SETTING, 0x08070807);
 439
 440	if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB &&
 441	    rtwusb->udev->speed == USB_SPEED_SUPER) {
 442		/* Disable U1/U2 Mode to avoid 2.5G spur in USB3.0. */
 443		rtw_write8_clr(rtwdev, REG_USB_MOD, BIT(4) | BIT(3));
 444		/* To avoid usb 3.0 H2C fail. */
 445		rtw_write16(rtwdev, 0xf002, 0);
 446
 447		rtw_write8_clr(rtwdev, REG_SW_AMPDU_BURST_MODE_CTRL,
 448			       BIT_PRE_TX_CMD);
 449	} else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE) {
 450		rtw8814ae_enable_rf_1_2v(rtwdev);
 451
 452		/* Force the antenna b to wifi. */
 453		rtw_write8_set(rtwdev, REG_PAD_CTRL1, BIT(2));
 454		rtw_write8_set(rtwdev, REG_PAD_CTRL1 + 1, BIT(0));
 455		rtw_write8_set(rtwdev, REG_LED_CFG + 3,
 456			       (BIT(27) | BIT_DPDT_WL_SEL) >> 24);
 457	}
 458
 459	return 0;
 460}
 461
 462static void rtw8814a_set_rfe_reg_24g(struct rtw_dev *rtwdev)
 463{
 464	switch (rtwdev->efuse.rfe_option) {
 465	case 2:
 466		rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x72707270);
 467		rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x72707270);
 468		rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x72707270);
 469		rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77707770);
 470
 471		rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D,
 472				 BIT_RFE_SELSW0_D, 0x72);
 473
 474		break;
 475	case 1:
 476		rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777);
 477		rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
 478		rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x77777777);
 479		rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77777777);
 480
 481		rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D,
 482				 BIT_RFE_SELSW0_D, 0x77);
 483
 484		break;
 485	case 0:
 486	default:
 487		rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777);
 488		rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
 489		rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x77777777);
 490		/* Is it not necessary to set REG_RFE_PINMUX_D ? */
 491
 492		rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D,
 493				 BIT_RFE_SELSW0_D, 0x77);
 494
 495		break;
 496	}
 497}
 498
 499static void rtw8814a_set_rfe_reg_5g(struct rtw_dev *rtwdev)
 500{
 501	switch (rtwdev->efuse.rfe_option) {
 502	case 2:
 503		rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x37173717);
 504		rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x37173717);
 505		rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x37173717);
 506		rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77177717);
 507
 508		rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D,
 509				 BIT_RFE_SELSW0_D, 0x37);
 510
 511		break;
 512	case 1:
 513		rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x33173317);
 514		rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x33173317);
 515		rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x33173317);
 516		rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77177717);
 517
 518		rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D,
 519				 BIT_RFE_SELSW0_D, 0x33);
 520
 521		break;
 522	case 0:
 523	default:
 524		rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x54775477);
 525		rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x54775477);
 526		rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x54775477);
 527		rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x54775477);
 528
 529		rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D,
 530				 BIT_RFE_SELSW0_D, 0x54);
 531
 532		break;
 533	}
 534}
 535
 536static void rtw8814a_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 band)
 537{
 538	rtw_write32_mask(rtwdev, REG_TXSCALE_A, BB_SWING_MASK,
 539			 rtw8814a_get_bb_swing(rtwdev, band, RF_PATH_A));
 540	rtw_write32_mask(rtwdev, REG_TXSCALE_B, BB_SWING_MASK,
 541			 rtw8814a_get_bb_swing(rtwdev, band, RF_PATH_B));
 542	rtw_write32_mask(rtwdev, REG_TXSCALE_C, BB_SWING_MASK,
 543			 rtw8814a_get_bb_swing(rtwdev, band, RF_PATH_C));
 544	rtw_write32_mask(rtwdev, REG_TXSCALE_D, BB_SWING_MASK,
 545			 rtw8814a_get_bb_swing(rtwdev, band, RF_PATH_D));
 546	rtw8814a_pwrtrack_init(rtwdev);
 547}
 548
 549static void rtw8814a_set_bw_reg_adc(struct rtw_dev *rtwdev, u8 bw)
 550{
 551	u32 adc = 0;
 552
 553	if (bw == RTW_CHANNEL_WIDTH_20)
 554		adc = 0;
 555	else if (bw == RTW_CHANNEL_WIDTH_40)
 556		adc = 1;
 557	else if (bw == RTW_CHANNEL_WIDTH_80)
 558		adc = 2;
 559
 560	rtw_write32_mask(rtwdev, REG_ADCCLK, BIT(1) | BIT(0), adc);
 561}
 562
 563static void rtw8814a_set_bw_reg_agc(struct rtw_dev *rtwdev, u8 new_band, u8 bw)
 564{
 565	u32 agc = 7;
 566
 567	if (bw == RTW_CHANNEL_WIDTH_20) {
 568		agc = 6;
 569	} else if (bw == RTW_CHANNEL_WIDTH_40) {
 570		if (new_band == RTW_BAND_5G)
 571			agc = 8;
 572		else
 573			agc = 7;
 574	} else if (bw == RTW_CHANNEL_WIDTH_80) {
 575		agc = 3;
 576	}
 577
 578	rtw_write32_mask(rtwdev, REG_CCASEL, 0xf000, agc);
 579}
 580
 581static void rtw8814a_switch_band(struct rtw_dev *rtwdev, u8 new_band, u8 bw)
 582{
 583	/* Clear 0x1000[16], When this bit is set to 0, CCK and OFDM
 584	 * are disabled, and clock are gated. Otherwise, CCK and OFDM
 585	 * are enabled.
 586	 */
 587	rtw_write8_clr(rtwdev, REG_SYS_CFG3_8814A + 2, BIT_FEN_BB_RSTB);
 588
 589	if (new_band == RTW_BAND_2G) {
 590		rtw_write32_mask(rtwdev, REG_AGC_TABLE, 0x1f, 0);
 591
 592		rtw8814a_set_rfe_reg_24g(rtwdev);
 593
 594		rtw_write32_mask(rtwdev, REG_TXPSEL, 0xf0, 0x2);
 595		rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0x5);
 596
 597		rtw_write32_mask(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST, 0x3);
 598
 599		rtw_write8(rtwdev, REG_CCK_CHECK, 0);
 600
 601		rtw_write32_mask(rtwdev, 0xa80, BIT(18), 0);
 602	} else {
 603		rtw_write8(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
 604
 605		/* Enable CCK Tx function, even when CCK is off */
 606		rtw_write32_mask(rtwdev, 0xa80, BIT(18), 1);
 607
 608		rtw8814a_set_rfe_reg_5g(rtwdev);
 609
 610		rtw_write32_mask(rtwdev, REG_TXPSEL, 0xf0, 0x0);
 611		rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0xf);
 612
 613		rtw_write32_mask(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST, 0x2);
 614	}
 615
 616	rtw8814a_set_channel_bb_swing(rtwdev, new_band);
 617
 618	rtw8814a_set_bw_reg_adc(rtwdev, bw);
 619	rtw8814a_set_bw_reg_agc(rtwdev, new_band, bw);
 620
 621	rtw_write8_set(rtwdev, REG_SYS_CFG3_8814A + 2, BIT_FEN_BB_RSTB);
 622}
 623
 624static void rtw8814a_switch_channel(struct rtw_dev *rtwdev, u8 channel)
 625{
 626	struct rtw_hal *hal = &rtwdev->hal;
 627	u32 fc_area, rf_mod_ag, cfgch;
 628	u8 path;
 629
 630	switch (channel) {
 631	case 36 ... 48:
 632		fc_area = 0x494;
 633		break;
 634	case 50 ... 64:
 635		fc_area = 0x453;
 636		break;
 637	case 100 ... 116:
 638		fc_area = 0x452;
 639		break;
 640	default:
 641		if (channel >= 118)
 642			fc_area = 0x412;
 643		else
 644			fc_area = 0x96a;
 645		break;
 646	}
 647
 648	rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, fc_area);
 649
 650	for (path = 0; path < hal->rf_path_num; path++) {
 651		switch (channel) {
 652		case 36 ... 64:
 653			rf_mod_ag = 0x101;
 654			break;
 655		case 100 ... 140:
 656			rf_mod_ag = 0x301;
 657			break;
 658		default:
 659			if (channel > 140)
 660				rf_mod_ag = 0x501;
 661			else
 662				rf_mod_ag = 0x000;
 663			break;
 664		}
 665
 666		cfgch = (rf_mod_ag << 8) | channel;
 667
 668		rtw_write_rf(rtwdev, path, RF_CFGCH,
 669			     RF18_RFSI_MASK | RF18_BAND_MASK | RF18_CHANNEL_MASK, cfgch);
 670	}
 671
 672	switch (channel) {
 673	case 36 ... 64:
 674		rtw_write32_mask(rtwdev, REG_AGC_TABLE, 0x1f, 1);
 675		break;
 676	case 100 ... 144:
 677		rtw_write32_mask(rtwdev, REG_AGC_TABLE, 0x1f, 2);
 678		break;
 679	default:
 680		if (channel >= 149)
 681			rtw_write32_mask(rtwdev, REG_AGC_TABLE, 0x1f, 3);
 682
 683		break;
 684	}
 685}
 686
 687static void rtw8814a_24g_cck_tx_dfir(struct rtw_dev *rtwdev, u8 channel)
 688{
 689	if (channel >= 1 && channel <= 11) {
 690		rtw_write32(rtwdev, REG_CCK0_TX_FILTER1, 0x1a1b0030);
 691		rtw_write32(rtwdev, REG_CCK0_TX_FILTER2, 0x090e1317);
 692		rtw_write32(rtwdev, REG_CCK0_DEBUG_PORT, 0x00000204);
 693	} else if (channel >= 12 && channel <= 13) {
 694		rtw_write32(rtwdev, REG_CCK0_TX_FILTER1, 0x1a1b0030);
 695		rtw_write32(rtwdev, REG_CCK0_TX_FILTER2, 0x090e1217);
 696		rtw_write32(rtwdev, REG_CCK0_DEBUG_PORT, 0x00000305);
 697	} else if (channel == 14) {
 698		rtw_write32(rtwdev, REG_CCK0_TX_FILTER1, 0x1a1b0030);
 699		rtw_write32(rtwdev, REG_CCK0_TX_FILTER2, 0x00000E17);
 700		rtw_write32(rtwdev, REG_CCK0_DEBUG_PORT, 0x00000000);
 701	}
 702}
 703
 704static void rtw8814a_set_bw_reg_mac(struct rtw_dev *rtwdev, u8 bw)
 705{
 706	u16 val16 = rtw_read16(rtwdev, REG_WMAC_TRXPTCL_CTL);
 707
 708	val16 &= ~BIT_RFMOD;
 709	if (bw == RTW_CHANNEL_WIDTH_80)
 710		val16 |= BIT_RFMOD_80M;
 711	else if (bw == RTW_CHANNEL_WIDTH_40)
 712		val16 |= BIT_RFMOD_40M;
 713
 714	rtw_write16(rtwdev, REG_WMAC_TRXPTCL_CTL, val16);
 715}
 716
 717static void rtw8814a_set_bw_rf(struct rtw_dev *rtwdev, u8 bw)
 718{
 719	u8 path;
 720
 721	for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
 722		switch (bw) {
 723		case RTW_CHANNEL_WIDTH_5:
 724		case RTW_CHANNEL_WIDTH_10:
 725		case RTW_CHANNEL_WIDTH_20:
 726		default:
 727			rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 3);
 728			break;
 729		case RTW_CHANNEL_WIDTH_40:
 730			rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 1);
 731			break;
 732		case RTW_CHANNEL_WIDTH_80:
 733			rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 0);
 734			break;
 735		}
 736	}
 737}
 738
 739static void rtw8814a_adc_clk(struct rtw_dev *rtwdev)
 740{
 741	static const u32 rxiqc_reg[2][4] = {
 742		{ REG_RX_IQC_AB_A, REG_RX_IQC_AB_B,
 743		  REG_RX_IQC_AB_C, REG_RX_IQC_AB_D },
 744		{ REG_RX_IQC_CD_A, REG_RX_IQC_CD_B,
 745		  REG_RX_IQC_CD_C, REG_RX_IQC_CD_D }
 746	};
 747	u32 bb_reg_8fc, bb_reg_808, rxiqc[4];
 748	u32 i = 0, mac_active = 1;
 749	u8 mac_reg_522;
 750
 751	if (rtwdev->hal.cut_version != RTW_CHIP_VER_CUT_A)
 752		return;
 753
 754	/* 1 Step1. MAC TX pause */
 755	mac_reg_522 = rtw_read8(rtwdev, REG_TXPAUSE);
 756	bb_reg_8fc = rtw_read32(rtwdev, REG_DBGSEL);
 757	bb_reg_808 = rtw_read32(rtwdev, REG_RXPSEL);
 758	rtw_write8(rtwdev, REG_TXPAUSE, 0x3f);
 759
 760	/* 1 Step 2. Backup rxiqc & rxiqc = 0 */
 761	for (i = 0; i < 4; i++) {
 762		rxiqc[i] = rtw_read32(rtwdev, rxiqc_reg[0][i]);
 763		rtw_write32(rtwdev, rxiqc_reg[0][i], 0x0);
 764		rtw_write32(rtwdev, rxiqc_reg[1][i], 0x0);
 765	}
 766	rtw_write32_mask(rtwdev, REG_PRECTRL, BIT_IQ_WGT, 0x3);
 767	i = 0;
 768
 769	/* 1 Step 3. Monitor MAC IDLE */
 770	rtw_write32(rtwdev, REG_DBGSEL, 0x0);
 771	while (mac_active) {
 772		mac_active = rtw_read32(rtwdev, REG_DBGRPT) & 0x803e0008;
 773		i++;
 774		if (i > 1000)
 775			break;
 776	}
 777
 778	/* 1 Step 4. ADC clk flow */
 779	rtw_write8(rtwdev, REG_RXPSEL, 0x11);
 780	rtw_write32_mask(rtwdev, REG_DAC_RSTB, BIT(13), 0x1);
 781	rtw_write8_mask(rtwdev, REG_GNT_BT, BIT(2) | BIT(1), 0x3);
 782	rtw_write32_mask(rtwdev, REG_CCK_RPT_FORMAT, BIT(2), 0x1);
 783
 784	/* 0xc1c/0xe1c/0x181c/0x1a1c[4] must=1 to ensure table can be
 785	 * written when bbrstb=0
 786	 * 0xc60/0xe60/0x1860/0x1a60[15] always = 1 after this line
 787	 * 0xc60/0xe60/0x1860/0x1a60[14] always = 0 bcz its error in A-cut
 788	 */
 789
 790	/* power_off/clk_off @ anapar_state=idle mode */
 791	rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x15800002);
 792	rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x01808003);
 793	rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x15800002);
 794	rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x01808003);
 795	rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x15800002);
 796	rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x01808003);
 797	rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x15800002);
 798	rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x01808003);
 799
 800	rtw_write8_mask(rtwdev, REG_GNT_BT, BIT(2), 0x0);
 801	rtw_write32_mask(rtwdev, REG_CCK_RPT_FORMAT, BIT(2), 0x0);
 802	/* [19] = 1 to turn off ADC */
 803	rtw_write32(rtwdev, REG_CK_MONHA, 0x0D080058);
 804	rtw_write32(rtwdev, REG_CK_MONHB, 0x0D080058);
 805	rtw_write32(rtwdev, REG_CK_MONHC, 0x0D080058);
 806	rtw_write32(rtwdev, REG_CK_MONHD, 0x0D080058);
 807
 808	/* power_on/clk_off */
 809	/* [19] = 0 to turn on ADC */
 810	rtw_write32(rtwdev, REG_CK_MONHA, 0x0D000058);
 811	rtw_write32(rtwdev, REG_CK_MONHB, 0x0D000058);
 812	rtw_write32(rtwdev, REG_CK_MONHC, 0x0D000058);
 813	rtw_write32(rtwdev, REG_CK_MONHD, 0x0D000058);
 814
 815	/* power_on/clk_on @ anapar_state=BT mode */
 816	rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x05808032);
 817	rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x05808032);
 818	rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x05808032);
 819	rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x05808032);
 820	rtw_write8_mask(rtwdev, REG_GNT_BT, BIT(2), 0x1);
 821	rtw_write32_mask(rtwdev, REG_CCK_RPT_FORMAT, BIT(2), 0x1);
 822
 823	/* recover original setting @ anapar_state=BT mode */
 824	rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x05808032);
 825	rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x05808032);
 826	rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x05808032);
 827	rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x05808032);
 828
 829	rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x05800002);
 830	rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x07808003);
 831	rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x05800002);
 832	rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x07808003);
 833	rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x05800002);
 834	rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x07808003);
 835	rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x05800002);
 836	rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x07808003);
 837
 838	rtw_write8_mask(rtwdev, REG_GNT_BT, BIT(2) | BIT(1), 0x0);
 839	rtw_write32_mask(rtwdev, REG_CCK_RPT_FORMAT, BIT(2), 0x0);
 840	rtw_write32_mask(rtwdev, REG_DAC_RSTB, BIT(13), 0x0);
 841
 842	/* 1 Step 5. Recover MAC TX & IQC */
 843	rtw_write8(rtwdev, REG_TXPAUSE, mac_reg_522);
 844	rtw_write32(rtwdev, REG_DBGSEL, bb_reg_8fc);
 845	rtw_write32(rtwdev, REG_RXPSEL, bb_reg_808);
 846	for (i = 0; i < 4; i++) {
 847		rtw_write32(rtwdev, rxiqc_reg[0][i], rxiqc[i]);
 848		rtw_write32(rtwdev, rxiqc_reg[1][i], 0x01000000);
 849	}
 850	rtw_write32_mask(rtwdev, REG_PRECTRL, BIT_IQ_WGT, 0x0);
 851}
 852
 853static void rtw8814a_spur_calibration_ch140(struct rtw_dev *rtwdev, u8 channel)
 854{
 855	struct rtw_hal *hal = &rtwdev->hal;
 856
 857	/* Add for 8814AE module ch140 MP Rx */
 858	if (channel == 140) {
 859		if (hal->ch_param[0] == 0)
 860			hal->ch_param[0] = rtw_read32(rtwdev, REG_CCASEL);
 861		if (hal->ch_param[1] == 0)
 862			hal->ch_param[1] = rtw_read32(rtwdev, REG_PDMFTH);
 863
 864		rtw_write32(rtwdev, REG_CCASEL, 0x75438170);
 865		rtw_write32(rtwdev, REG_PDMFTH, 0x79a18a0a);
 866	} else {
 867		if (rtw_read32(rtwdev, REG_CCASEL) == 0x75438170 &&
 868		    hal->ch_param[0] != 0)
 869			rtw_write32(rtwdev, REG_CCASEL, hal->ch_param[0]);
 870
 871		if (rtw_read32(rtwdev, REG_PDMFTH) == 0x79a18a0a &&
 872		    hal->ch_param[1] != 0)
 873			rtw_write32(rtwdev, REG_PDMFTH, hal->ch_param[1]);
 874
 875		hal->ch_param[0] = rtw_read32(rtwdev, REG_CCASEL);
 876		hal->ch_param[1] = rtw_read32(rtwdev, REG_PDMFTH);
 877	}
 878}
 879
 880static void rtw8814a_set_nbi_reg(struct rtw_dev *rtwdev, u32 tone_idx)
 881{
 882	/* tone_idx X 10 */
 883	static const u32 nbi_128[] = {
 884		25, 55, 85, 115, 135,
 885		155, 185, 205, 225, 245,
 886		265, 285, 305, 335, 355,
 887		375, 395, 415, 435, 455,
 888		485, 505, 525, 555, 585, 615, 635
 889	};
 890	u32 reg_idx = 0;
 891	u32 i;
 892
 893	for (i = 0; i < ARRAY_SIZE(nbi_128); i++) {
 894		if (tone_idx < nbi_128[i]) {
 895			reg_idx = i + 1;
 896			break;
 897		}
 898	}
 899
 900	rtw_write32_mask(rtwdev, REG_NBI_SETTING, 0xfc000, reg_idx);
 901}
 902
 903static void rtw8814a_nbi_setting(struct rtw_dev *rtwdev, u32 ch, u32 f_intf)
 904{
 905	u32 fc, int_distance, tone_idx;
 906
 907	fc = 2412 + (ch - 1) * 5;
 908	int_distance = abs_diff(fc, f_intf);
 909
 910	/* 10 * (int_distance / 0.3125) */
 911	tone_idx = int_distance << 5;
 912
 913	rtw8814a_set_nbi_reg(rtwdev, tone_idx);
 914
 915	rtw_write32_mask(rtwdev, REG_NBI_SETTING, BIT_NBI_ENABLE, 1);
 916}
 917
 918static void rtw8814a_spur_nbi_setting(struct rtw_dev *rtwdev)
 919{
 920	u8 primary_channel = rtwdev->hal.primary_channel;
 921	u8 rfe_type = rtwdev->efuse.rfe_option;
 922
 923	if (rfe_type != 0 && rfe_type != 1 && rfe_type != 6 && rfe_type != 7)
 924		return;
 925
 926	if (primary_channel == 14)
 927		rtw8814a_nbi_setting(rtwdev, primary_channel, 2480);
 928	else if (primary_channel >= 4 && primary_channel <= 8)
 929		rtw8814a_nbi_setting(rtwdev, primary_channel, 2440);
 930	else
 931		rtw_write32_mask(rtwdev, REG_NBI_SETTING, BIT_NBI_ENABLE, 0);
 932}
 933
 934/* A workaround to eliminate the 5280 MHz & 5600 MHz & 5760 MHz spur of 8814A */
 935static void rtw8814a_spur_calibration(struct rtw_dev *rtwdev, u8 channel, u8 bw)
 936{
 937	u8 rfe_type = rtwdev->efuse.rfe_option;
 938	bool reset_nbi_csi = true;
 939
 940	if (rfe_type == 0) {
 941		switch (bw) {
 942		case RTW_CHANNEL_WIDTH_40:
 943			if (channel == 54 || channel == 118) {
 944				rtw_write32_mask(rtwdev, REG_NBI_SETTING,
 945						 0x000fe000, 0x3e >> 1);
 946				rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
 947						 BIT(0), 1);
 948				rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0);
 949				rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK1,
 950						 BIT(0), 1);
 951				rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0);
 952				rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0);
 953
 954				reset_nbi_csi = false;
 955			} else if (channel == 151) {
 956				rtw_write32_mask(rtwdev, REG_NBI_SETTING,
 957						 0x000fe000, 0x1e >> 1);
 958				rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
 959						 BIT(0), 1);
 960				rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK0,
 961						 BIT(16), 1);
 962				rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
 963				rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0);
 964				rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0);
 965
 966				reset_nbi_csi = false;
 967			}
 968			break;
 969		case RTW_CHANNEL_WIDTH_80:
 970			if (channel == 58 || channel == 122) {
 971				rtw_write32_mask(rtwdev, REG_NBI_SETTING,
 972						 0x000fe000, 0x3a >> 1);
 973				rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
 974						 BIT(0), 1);
 975				rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0);
 976				rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
 977				rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0);
 978				rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK7,
 979						 BIT(0), 1);
 980
 981				reset_nbi_csi = false;
 982			} else if (channel == 155) {
 983				rtw_write32_mask(rtwdev, REG_NBI_SETTING,
 984						 0x000fe000, 0x5a >> 1);
 985				rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
 986						 BIT(0), 1);
 987				rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0);
 988				rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
 989				rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK6,
 990						 BIT(16), 1);
 991				rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0);
 992
 993				reset_nbi_csi = false;
 994			}
 995			break;
 996		case RTW_CHANNEL_WIDTH_20:
 997			if (channel == 153) {
 998				rtw_write32_mask(rtwdev, REG_NBI_SETTING,
 999						 0x000fe000, 0x1e >> 1);
1000				rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
1001						 BIT(0), 1);
1002				rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0);
1003				rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
1004				rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0);
1005				rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK7,
1006						 BIT(16), 1);
1007
1008				reset_nbi_csi = false;
1009			}
1010
1011			rtw8814a_spur_calibration_ch140(rtwdev, channel);
1012			break;
1013		default:
1014			break;
1015		}
1016	} else if (rfe_type == 1 || rfe_type == 2) {
1017		switch (bw) {
1018		case RTW_CHANNEL_WIDTH_20:
1019			if (channel == 153) {
1020				rtw_write32_mask(rtwdev, REG_NBI_SETTING,
1021						 0x000fe000, 0x1E >> 1);
1022				rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
1023						 BIT(0), 1);
1024				rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0);
1025				rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
1026				rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0);
1027				rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK7,
1028						 BIT(16), 1);
1029
1030				reset_nbi_csi = false;
1031			}
1032			break;
1033		case RTW_CHANNEL_WIDTH_40:
1034			if (channel == 151) {
1035				rtw_write32_mask(rtwdev, REG_NBI_SETTING,
1036						 0x000fe000, 0x1e >> 1);
1037				rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
1038						 BIT(0), 1);
1039				rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK0,
1040						 BIT(16), 1);
1041				rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
1042				rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0);
1043				rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0);
1044
1045				reset_nbi_csi = false;
1046			}
1047			break;
1048		case RTW_CHANNEL_WIDTH_80:
1049			if (channel == 155) {
1050				rtw_write32_mask(rtwdev, REG_NBI_SETTING,
1051						 0x000fe000, 0x5a >> 1);
1052				rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
1053						 BIT(0), 1);
1054				rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0);
1055				rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
1056				rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK6,
1057						 BIT(16), 1);
1058				rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0);
1059
1060				reset_nbi_csi = false;
1061			}
1062			break;
1063		default:
1064			break;
1065		}
1066	}
1067
1068	if (reset_nbi_csi) {
1069		rtw_write32_mask(rtwdev, REG_NBI_SETTING,
1070				 0x000fe000, 0xfc >> 1);
1071		rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1, BIT(0), 0);
1072		rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0);
1073		rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
1074		rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0);
1075		rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0);
1076	}
1077
1078	rtw8814a_spur_nbi_setting(rtwdev);
1079}
1080
1081static void rtw8814a_set_bw_mode(struct rtw_dev *rtwdev, u8 new_band,
1082				 u8 channel, u8 bw, u8 primary_chan_idx)
1083{
1084	u8 txsc40 = 0, txsc20, txsc;
1085
1086	rtw8814a_set_bw_reg_mac(rtwdev, bw);
1087
1088	txsc20 = primary_chan_idx;
1089	if (bw == RTW_CHANNEL_WIDTH_80) {
1090		if (txsc20 == RTW_SC_20_UPPER || txsc20 == RTW_SC_20_UPMOST)
1091			txsc40 = RTW_SC_40_UPPER;
1092		else
1093			txsc40 = RTW_SC_40_LOWER;
1094	}
1095
1096	txsc = BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40);
1097	rtw_write8(rtwdev, REG_DATA_SC, txsc);
1098
1099	rtw8814a_set_bw_reg_adc(rtwdev, bw);
1100	rtw8814a_set_bw_reg_agc(rtwdev, new_band, bw);
1101
1102	if (bw == RTW_CHANNEL_WIDTH_80) {
1103		rtw_write32_mask(rtwdev, REG_ADCCLK, 0x3c, txsc);
1104	} else if (bw == RTW_CHANNEL_WIDTH_40) {
1105		rtw_write32_mask(rtwdev, REG_ADCCLK, 0x3c, txsc);
1106
1107		if (txsc == RTW_SC_20_UPPER)
1108			rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
1109		else
1110			rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
1111	}
1112
1113	rtw8814a_set_bw_rf(rtwdev, bw);
1114
1115	rtw8814a_adc_clk(rtwdev);
1116
1117	rtw8814a_spur_calibration(rtwdev, channel, bw);
1118}
1119
1120static void rtw8814a_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
1121				 u8 primary_chan_idx)
1122{
1123	u8 old_band, new_band;
1124
1125	if (rtw_read8(rtwdev, REG_CCK_CHECK) & BIT_CHECK_CCK_EN)
1126		old_band = RTW_BAND_5G;
1127	else
1128		old_band = RTW_BAND_2G;
1129
1130	if (channel > 14)
1131		new_band = RTW_BAND_5G;
1132	else
1133		new_band = RTW_BAND_2G;
1134
1135	if (new_band != old_band)
1136		rtw8814a_switch_band(rtwdev, new_band, bw);
1137
1138	rtw8814a_switch_channel(rtwdev, channel);
1139
1140	rtw8814a_24g_cck_tx_dfir(rtwdev, channel);
1141
1142	rtw8814a_set_bw_mode(rtwdev, new_band, channel, bw, primary_chan_idx);
1143}
1144
1145static s8 rtw8814a_cck_rx_pwr(u8 lna_idx, u8 vga_idx)
1146{
1147	s8 rx_pwr_all = 0;
1148
1149	switch (lna_idx) {
1150	case 7:
1151		rx_pwr_all = -38 - 2 * vga_idx;
1152		break;
1153	case 5:
1154		rx_pwr_all = -28 - 2 * vga_idx;
1155		break;
1156	case 3:
1157		rx_pwr_all = -8 - 2 * vga_idx;
1158		break;
1159	case 2:
1160		rx_pwr_all = -1 - 2 * vga_idx;
1161		break;
1162	default:
1163		break;
1164	}
1165
1166	return rx_pwr_all;
1167}
1168
1169static void rtw8814a_query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
1170				      struct rtw_rx_pkt_stat *pkt_stat)
1171{
1172	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1173	struct rtw_jaguar_phy_status_rpt *rpt;
1174	u8 gain[RTW_RF_PATH_MAX], rssi, i;
1175	s8 rx_pwr_db, middle1, middle2;
1176	s8 snr[RTW_RF_PATH_MAX];
1177	s8 evm[RTW_RF_PATH_MAX];
1178	u8 rfmode, subchannel;
1179	u8 lna, vga;
1180	s8 cfo[2];
1181
1182	rpt = (struct rtw_jaguar_phy_status_rpt *)phy_status;
1183
1184	pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
1185
1186	if (pkt_stat->rate <= DESC_RATE11M) {
1187		lna = le32_get_bits(rpt->w1, RTW_JGRPHY_W1_AGC_RPT_LNA_IDX);
1188		vga = le32_get_bits(rpt->w1, RTW_JGRPHY_W1_AGC_RPT_VGA_IDX);
1189
1190		rx_pwr_db = rtw8814a_cck_rx_pwr(lna, vga);
1191
1192		pkt_stat->rx_power[RF_PATH_A] = rx_pwr_db;
1193		pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
1194		dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
1195		pkt_stat->signal_power = rx_pwr_db;
1196	} else { /* OFDM rate */
1197		gain[RF_PATH_A] = le32_get_bits(rpt->w0, RTW_JGRPHY_W0_GAIN_A);
1198		gain[RF_PATH_B] = le32_get_bits(rpt->w0, RTW_JGRPHY_W0_GAIN_B);
1199		gain[RF_PATH_C] = le32_get_bits(rpt->w5, RTW_JGRPHY_W5_GAIN_C);
1200		gain[RF_PATH_D] = le32_get_bits(rpt->w6, RTW_JGRPHY_W6_GAIN_D);
1201
1202		snr[RF_PATH_A] = le32_get_bits(rpt->w3, RTW_JGRPHY_W3_RXSNR_A);
1203		snr[RF_PATH_B] = le32_get_bits(rpt->w4, RTW_JGRPHY_W4_RXSNR_B);
1204		snr[RF_PATH_C] = le32_get_bits(rpt->w5, RTW_JGRPHY_W5_RXSNR_C);
1205		snr[RF_PATH_D] = le32_get_bits(rpt->w5, RTW_JGRPHY_W5_RXSNR_D);
1206
1207		evm[RF_PATH_A] = le32_get_bits(rpt->w3, RTW_JGRPHY_W3_RXEVM_1);
1208		evm[RF_PATH_B] = le32_get_bits(rpt->w3, RTW_JGRPHY_W3_RXEVM_2);
1209		evm[RF_PATH_C] = le32_get_bits(rpt->w4, RTW_JGRPHY_W4_RXEVM_3);
1210		evm[RF_PATH_D] = le32_get_bits(rpt->w5, RTW_JGRPHY_W5_RXEVM_4);
1211
1212		if (pkt_stat->rate <= DESC_RATE54M)
1213			evm[RF_PATH_A] = le32_get_bits(rpt->w6,
1214						       RTW_JGRPHY_W6_SIGEVM);
1215
1216		for (i = RF_PATH_A; i < RTW_RF_PATH_MAX; i++) {
1217			pkt_stat->rx_power[i] = gain[i] - 110;
1218
1219			rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[i], 1);
1220			dm_info->rssi[i] = rssi;
1221
1222			pkt_stat->rx_snr[i] = snr[i];
1223			dm_info->rx_snr[i] = snr[i] >> 1;
1224
1225			pkt_stat->rx_evm[i] = evm[i];
1226			evm[i] = max_t(s8, -127, evm[i]);
1227			dm_info->rx_evm_dbm[i] = abs(evm[i]) >> 1;
1228		}
1229
1230		rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power,
1231					       RTW_RF_PATH_MAX);
1232		pkt_stat->rssi = rssi;
1233
1234		/* When power saving is enabled the hardware sometimes
1235		 * reports unbelievably high gain for paths A and C
1236		 * (e.g. one frame 64 68 68 72, the next frame 106 66 88 72,
1237		 * the next 66 66 68 72), so use the second lowest gain
1238		 * instead of the highest.
1239		 */
1240		middle1 = max(min(gain[RF_PATH_A], gain[RF_PATH_B]),
1241			      min(gain[RF_PATH_C], gain[RF_PATH_D]));
1242		middle2 = min(max(gain[RF_PATH_A], gain[RF_PATH_B]),
1243			      max(gain[RF_PATH_C], gain[RF_PATH_D]));
1244		rx_pwr_db = min(middle1, middle2);
1245		rx_pwr_db -= 110;
1246		pkt_stat->signal_power = rx_pwr_db;
1247
1248		rfmode = le32_get_bits(rpt->w0, RTW_JGRPHY_W0_R_RFMOD);
1249		subchannel = le32_get_bits(rpt->w0, RTW_JGRPHY_W0_SUB_CHNL);
1250
1251		if (rfmode == 1 && subchannel == 0) {
1252			pkt_stat->bw = RTW_CHANNEL_WIDTH_40;
1253		} else if (rfmode == 2) {
1254			if (subchannel == 0)
1255				pkt_stat->bw = RTW_CHANNEL_WIDTH_80;
1256			else if (subchannel == 9 || subchannel == 10)
1257				pkt_stat->bw = RTW_CHANNEL_WIDTH_40;
1258		}
1259
1260		cfo[RF_PATH_A] = le32_get_bits(rpt->w2, RTW_JGRPHY_W2_CFO_TAIL_A);
1261		cfo[RF_PATH_B] = le32_get_bits(rpt->w2, RTW_JGRPHY_W2_CFO_TAIL_B);
1262
1263		for (i = RF_PATH_A; i < 2; i++) {
1264			pkt_stat->cfo_tail[i] = cfo[i];
1265			dm_info->cfo_tail[i] = (cfo[i] * 5) >> 1;
1266		}
1267	}
1268}
1269
1270static void
1271rtw8814a_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs)
1272{
1273	struct rtw_hal *hal = &rtwdev->hal;
1274	u32 txagc_table_wd;
1275	u8 rate, pwr_index;
1276	int j;
1277
1278	for (j = 0; j < rtw_rate_size[rs]; j++) {
1279		rate = rtw_rate_section[rs][j];
1280
1281		pwr_index = hal->tx_pwr_tbl[path][rate] + 2;
1282		if (pwr_index > rtwdev->chip->max_power_index)
1283			pwr_index = rtwdev->chip->max_power_index;
1284
1285		txagc_table_wd = 0x00801000;
1286		txagc_table_wd |= (pwr_index << 24) | (path << 8) | rate;
1287
1288		rtw_write32(rtwdev, REG_AGC_TBL, txagc_table_wd);
1289
1290		/* first time to turn on the txagc table
1291		 * second to write the addr0
1292		 */
1293		if (rate == DESC_RATE1M)
1294			rtw_write32(rtwdev, REG_AGC_TBL, txagc_table_wd);
1295	}
1296}
1297
1298static void rtw8814a_set_tx_power_index(struct rtw_dev *rtwdev)
1299{
1300	struct rtw_hal *hal = &rtwdev->hal;
1301	int path;
1302
1303	for (path = 0; path < hal->rf_path_num; path++) {
1304		if (hal->current_band_type == RTW_BAND_2G)
1305			rtw8814a_set_tx_power_index_by_rate(rtwdev, path,
1306							    RTW_RATE_SECTION_CCK);
1307
1308		rtw8814a_set_tx_power_index_by_rate(rtwdev, path,
1309						    RTW_RATE_SECTION_OFDM);
1310
1311		if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
1312			continue;
1313
1314		rtw8814a_set_tx_power_index_by_rate(rtwdev, path,
1315						    RTW_RATE_SECTION_HT_1S);
1316		rtw8814a_set_tx_power_index_by_rate(rtwdev, path,
1317						    RTW_RATE_SECTION_VHT_1S);
1318
1319		rtw8814a_set_tx_power_index_by_rate(rtwdev, path,
1320						    RTW_RATE_SECTION_HT_2S);
1321		rtw8814a_set_tx_power_index_by_rate(rtwdev, path,
1322						    RTW_RATE_SECTION_VHT_2S);
1323
1324		rtw8814a_set_tx_power_index_by_rate(rtwdev, path,
1325						    RTW_RATE_SECTION_HT_3S);
1326		rtw8814a_set_tx_power_index_by_rate(rtwdev, path,
1327						    RTW_RATE_SECTION_VHT_3S);
1328	}
1329}
1330
1331static void rtw8814a_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
1332{
1333}
1334
1335/* Without this RTL8814A sends too many frames and (some?) 11n AP
1336 * can't handle it, resulting in low TX speed. Other chips seem fine.
1337 */
1338static void rtw8814a_set_ampdu_factor(struct rtw_dev *rtwdev, u8 factor)
1339{
1340	factor = min_t(u8, factor, IEEE80211_VHT_MAX_AMPDU_256K);
1341
1342	rtw_write32(rtwdev, REG_AMPDU_MAX_LENGTH, (8192 << factor) - 1);
1343}
1344
1345static void rtw8814a_false_alarm_statistics(struct rtw_dev *rtwdev)
1346{
1347	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1348	u32 cck_fa_cnt, ofdm_fa_cnt;
1349	u32 crc32_cnt, cca32_cnt;
1350	u32 cck_enable;
1351
1352	cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28);
1353	cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK);
1354	ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM);
1355
1356	dm_info->cck_fa_cnt = cck_fa_cnt;
1357	dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
1358	dm_info->total_fa_cnt = ofdm_fa_cnt;
1359	if (cck_enable)
1360		dm_info->total_fa_cnt += cck_fa_cnt;
1361
1362	crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK);
1363	dm_info->cck_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
1364	dm_info->cck_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD);
1365
1366	crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM);
1367	dm_info->ofdm_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
1368	dm_info->ofdm_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD);
1369
1370	crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT);
1371	dm_info->ht_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
1372	dm_info->ht_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD);
1373
1374	crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT);
1375	dm_info->vht_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
1376	dm_info->vht_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD);
1377
1378	cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM);
1379	dm_info->ofdm_cca_cnt = u32_get_bits(cca32_cnt, MASKHWORD);
1380	dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
1381	if (cck_enable) {
1382		cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK);
1383		dm_info->cck_cca_cnt = u32_get_bits(cca32_cnt, MASKLWORD);
1384		dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
1385	}
1386
1387	rtw_write32_set(rtwdev, REG_FAS, BIT(17));
1388	rtw_write32_clr(rtwdev, REG_FAS, BIT(17));
1389	rtw_write32_clr(rtwdev, REG_CCK0_FAREPORT, BIT(15));
1390	rtw_write32_set(rtwdev, REG_CCK0_FAREPORT, BIT(15));
1391	rtw_write32_set(rtwdev, REG_CNTRST, BIT(0));
1392	rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0));
1393}
1394
1395#define MAC_REG_NUM_8814 2
1396#define BB_REG_NUM_8814 14
1397#define RF_REG_NUM_8814 1
1398
1399static void rtw8814a_iqk_backup_mac_bb(struct rtw_dev *rtwdev,
1400				       u32 *mac_backup, u32 *bb_backup,
1401				       const u32 *mac_regs,
1402				       const u32 *bb_regs)
1403{
1404	u32 i;
1405
1406	/* save MACBB default value */
1407	for (i = 0; i < MAC_REG_NUM_8814; i++)
1408		mac_backup[i] = rtw_read32(rtwdev, mac_regs[i]);
1409
1410	for (i = 0; i < BB_REG_NUM_8814; i++)
1411		bb_backup[i] = rtw_read32(rtwdev, bb_regs[i]);
1412}
1413
1414static void rtw8814a_iqk_backup_rf(struct rtw_dev *rtwdev,
1415				   u32 rf_backup[][4], const u32 *rf_regs)
1416{
1417	u32 i;
1418
1419	/* Save RF Parameters */
1420	for (i = 0; i < RF_REG_NUM_8814; i++) {
1421		rf_backup[i][RF_PATH_A] = rtw_read_rf(rtwdev, RF_PATH_A,
1422						      rf_regs[i], RFREG_MASK);
1423		rf_backup[i][RF_PATH_B] = rtw_read_rf(rtwdev, RF_PATH_B,
1424						      rf_regs[i], RFREG_MASK);
1425		rf_backup[i][RF_PATH_C] = rtw_read_rf(rtwdev, RF_PATH_C,
1426						      rf_regs[i], RFREG_MASK);
1427		rf_backup[i][RF_PATH_D] = rtw_read_rf(rtwdev, RF_PATH_D,
1428						      rf_regs[i], RFREG_MASK);
1429	}
1430}
1431
1432static void rtw8814a_iqk_afe_setting(struct rtw_dev *rtwdev, bool do_iqk)
1433{
1434	if (do_iqk) {
1435		/* IQK AFE setting RX_WAIT_CCA mode */
1436		rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x0e808003);
1437		rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x0e808003);
1438		rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x0e808003);
1439		rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x0e808003);
1440	} else {
1441		rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x07808003);
1442		rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x07808003);
1443		rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x07808003);
1444		rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x07808003);
1445	}
1446
1447	rtw_write32_mask(rtwdev, REG_DAC_RSTB, BIT(13), 0x1);
1448
1449	rtw_write8_set(rtwdev, REG_GNT_BT, BIT(2) | BIT(1));
1450	rtw_write8_clr(rtwdev, REG_GNT_BT, BIT(2) | BIT(1));
1451
1452	rtw_write32_set(rtwdev, REG_CCK_RPT_FORMAT, BIT(2));
1453	rtw_write32_clr(rtwdev, REG_CCK_RPT_FORMAT, BIT(2));
1454}
1455
1456static void rtw8814a_iqk_restore_mac_bb(struct rtw_dev *rtwdev,
1457					u32 *mac_backup, u32 *bb_backup,
1458					const u32 *mac_regs,
1459					const u32 *bb_regs)
1460{
1461	u32 i;
1462
1463	/* Reload MacBB Parameters */
1464	for (i = 0; i < MAC_REG_NUM_8814; i++)
1465		rtw_write32(rtwdev, mac_regs[i], mac_backup[i]);
1466
1467	for (i = 0; i < BB_REG_NUM_8814; i++)
1468		rtw_write32(rtwdev, bb_regs[i], bb_backup[i]);
1469}
1470
1471static void rtw8814a_iqk_restore_rf(struct rtw_dev *rtwdev,
1472				    const u32 rf_backup[][4],
1473				    const u32 *rf_regs)
1474{
1475	u32 i;
1476
1477	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x0);
1478	rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE, RFREG_MASK, 0x0);
1479	rtw_write_rf(rtwdev, RF_PATH_C, RF_LUTWE, RFREG_MASK, 0x0);
1480	rtw_write_rf(rtwdev, RF_PATH_D, RF_LUTWE, RFREG_MASK, 0x0);
1481
1482	rtw_write_rf(rtwdev, RF_PATH_A, RF_RXBB2, RFREG_MASK, 0x88001);
1483	rtw_write_rf(rtwdev, RF_PATH_B, RF_RXBB2, RFREG_MASK, 0x88001);
1484	rtw_write_rf(rtwdev, RF_PATH_C, RF_RXBB2, RFREG_MASK, 0x88001);
1485	rtw_write_rf(rtwdev, RF_PATH_D, RF_RXBB2, RFREG_MASK, 0x88001);
1486
1487	for (i = 0; i < RF_REG_NUM_8814; i++) {
1488		rtw_write_rf(rtwdev, RF_PATH_A, rf_regs[i],
1489			     RFREG_MASK, rf_backup[i][RF_PATH_A]);
1490		rtw_write_rf(rtwdev, RF_PATH_B, rf_regs[i],
1491			     RFREG_MASK, rf_backup[i][RF_PATH_B]);
1492		rtw_write_rf(rtwdev, RF_PATH_C, rf_regs[i],
1493			     RFREG_MASK, rf_backup[i][RF_PATH_C]);
1494		rtw_write_rf(rtwdev, RF_PATH_D, rf_regs[i],
1495			     RFREG_MASK, rf_backup[i][RF_PATH_D]);
1496	}
1497}
1498
1499static void rtw8814a_iqk_reset_nctl(struct rtw_dev *rtwdev)
1500{
1501	rtw_write32(rtwdev, 0x1b00, 0xf8000000);
1502	rtw_write32(rtwdev, 0x1b80, 0x00000006);
1503
1504	rtw_write32(rtwdev, 0x1b00, 0xf8000000);
1505	rtw_write32(rtwdev, 0x1b80, 0x00000002);
1506}
1507
1508static void rtw8814a_iqk_configure_mac(struct rtw_dev *rtwdev)
1509{
1510	rtw_write8(rtwdev, REG_TXPAUSE, 0x3f);
1511	rtw_write32_clr(rtwdev, REG_BCN_CTRL,
1512			(BIT_EN_BCN_FUNCTION << 8) | BIT_EN_BCN_FUNCTION);
1513
1514	/* RX ante off */
1515	rtw_write8(rtwdev, REG_RXPSEL, 0x00);
1516	/* CCA off */
1517	rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf, 0xe);
1518	/* CCK RX path off */
1519	rtw_write32_set(rtwdev, REG_PRECTRL, BIT_IQ_WGT);
1520	rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777);
1521	rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
1522	rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x77777777);
1523	rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77777777);
1524	rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D, BIT_RFE_SELSW0_D, 0x77);
1525	rtw_write32_mask(rtwdev, REG_PSD, BIT_PSD_INI, 0x0);
1526
1527	rtw_write32_mask(rtwdev, REG_RFE_INV0, 0xf, 0x0);
1528}
1529
1530static void rtw8814a_lok_one_shot(struct rtw_dev *rtwdev, u8 path)
1531{
1532	u32 lok_temp1, lok_temp2;
1533	bool lok_ready;
1534	u8 ii;
1535
1536	/* ADC Clock source */
1537	rtw_write32_mask(rtwdev, REG_FAS, BIT(21) | BIT(20), path);
1538	/* LOK: CMD ID = 0
1539	 * {0xf8000011, 0xf8000021, 0xf8000041, 0xf8000081}
1540	 */
1541	rtw_write32(rtwdev, 0x1b00, 0xf8000001 | (BIT(path) << 4));
1542
1543	usleep_range(1000, 1100);
1544
1545	if (read_poll_timeout(!rtw_read32_mask, lok_ready, lok_ready,
1546			      1000, 10000, false,
1547			      rtwdev, 0x1b00, BIT(0))) {
1548		rtw_dbg(rtwdev, RTW_DBG_RFK, "==>S%d LOK timed out\n", path);
1549
1550		rtw8814a_iqk_reset_nctl(rtwdev);
1551
1552		rtw_write_rf(rtwdev, path, RF_DTXLOK, RFREG_MASK, 0x08400);
1553
1554		return;
1555	}
1556
1557	rtw_write32(rtwdev, 0x1b00, 0xf8000000 | (path << 1));
1558	rtw_write32(rtwdev, 0x1bd4, 0x003f0001);
1559
1560	lok_temp2 = rtw_read32_mask(rtwdev, 0x1bfc, 0x003e0000);
1561	lok_temp2 = (lok_temp2 + 0x10) & 0x1f;
1562
1563	lok_temp1 = rtw_read32_mask(rtwdev, 0x1bfc, 0x0000003e);
1564	lok_temp1 = (lok_temp1 + 0x10) & 0x1f;
1565
1566	for (ii = 1; ii < 5; ii++) {
1567		lok_temp1 += (lok_temp1 & BIT(4 - ii)) << (ii * 2);
1568		lok_temp2 += (lok_temp2 & BIT(4 - ii)) << (ii * 2);
1569	}
1570
1571	rtw_dbg(rtwdev, RTW_DBG_RFK,
1572		"path %d lok_temp1 = %#x, lok_temp2 = %#x\n",
1573		path, lok_temp1 >> 4, lok_temp2 >> 4);
1574
1575	rtw_write_rf(rtwdev, path, RF_DTXLOK, 0x07c00, lok_temp1 >> 4);
1576	rtw_write_rf(rtwdev, path, RF_DTXLOK, 0xf8000, lok_temp2 >> 4);
1577}
1578
1579static void rtw8814a_iqk_tx_one_shot(struct rtw_dev *rtwdev, u8 path,
1580				     u32 *tx_matrix, bool *tx_ok)
1581{
1582	u8 bw = rtwdev->hal.current_band_width;
1583	u8 cal_retry;
1584	u32 iqk_cmd;
1585
1586	for (cal_retry = 0; cal_retry < 4; cal_retry++) {
1587		rtw_write32_mask(rtwdev, REG_FAS, BIT(21) | BIT(20), path);
1588
1589		iqk_cmd = 0xf8000001 | ((bw + 3) << 8) | (BIT(path) << 4);
1590
1591		rtw_dbg(rtwdev, RTW_DBG_RFK, "TXK_Trigger = %#x\n", iqk_cmd);
1592
1593		rtw_write32(rtwdev, 0x1b00, iqk_cmd);
1594
1595		usleep_range(10000, 11000);
1596
1597		if (read_poll_timeout(!rtw_read32_mask, *tx_ok, *tx_ok,
1598				      1000, 20000, false,
1599				      rtwdev, 0x1b00, BIT(0))) {
1600			rtw_dbg(rtwdev, RTW_DBG_RFK,
1601				"tx iqk S%d timed out\n", path);
1602
1603			rtw8814a_iqk_reset_nctl(rtwdev);
1604		} else {
1605			*tx_ok = !rtw_read32_mask(rtwdev, 0x1b08, BIT(26));
1606
1607			if (*tx_ok)
1608				break;
1609		}
1610	}
1611
1612	rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d tx ==> 0x1b00 = 0x%x\n",
1613		path, rtw_read32(rtwdev, 0x1b00));
1614	rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d tx ==> 0x1b08 = 0x%x\n",
1615		path, rtw_read32(rtwdev, 0x1b08));
1616	rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d tx ==> cal_retry = %x\n",
1617		path, cal_retry);
1618
1619	rtw_write32(rtwdev, 0x1b00, 0xf8000000 | (path << 1));
1620
1621	if (*tx_ok) {
1622		*tx_matrix = rtw_read32(rtwdev, 0x1b38);
1623
1624		rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d_IQC = 0x%x\n",
1625			path, *tx_matrix);
1626	}
1627}
1628
1629static void rtw8814a_iqk_rx_one_shot(struct rtw_dev *rtwdev, u8 path,
1630				     u32 *tx_matrix, bool *tx_ok)
1631{
1632	static const u16 iqk_apply[RTW_RF_PATH_MAX] = {
1633		REG_TXAGCIDX, REG_TX_AGC_B, REG_TX_AGC_C, REG_TX_AGC_D
1634	};
1635	u8 band = rtwdev->hal.current_band_type;
1636	u8 bw = rtwdev->hal.current_band_width;
1637	u32 rx_matrix;
1638	u8 cal_retry;
1639	u32 iqk_cmd;
1640	bool rx_ok;
1641
1642	for (cal_retry = 0; cal_retry < 4; cal_retry++) {
1643		rtw_write32_mask(rtwdev, REG_FAS, BIT(21) | BIT(20), path);
1644
1645		if (band == RTW_BAND_2G) {
1646			rtw_write_rf(rtwdev, path, RF_LUTDBG, BIT(11), 0x1);
1647			rtw_write_rf(rtwdev, path, RF_GAINTX, 0xfffff, 0x51ce1);
1648
1649			switch (path) {
1650			case 0:
1651			case 1:
1652				rtw_write32(rtwdev, REG_RFE_PINMUX_B,
1653					    0x54775477);
1654				break;
1655			case 2:
1656				rtw_write32(rtwdev, REG_RFE_PINMUX_C,
1657					    0x54775477);
1658				break;
1659			case 3:
1660				rtw_write32(rtwdev, REG_RFE_INVSEL_D, 0x75400000);
1661				rtw_write32(rtwdev, REG_RFE_PINMUX_D,
1662					    0x77777777);
1663				break;
1664			}
1665		}
1666
1667		iqk_cmd = 0xf8000001 | ((9 - bw) << 8) | (BIT(path) << 4);
1668
1669		rtw_dbg(rtwdev, RTW_DBG_RFK, "RXK_Trigger = 0x%x\n", iqk_cmd);
1670
1671		rtw_write32(rtwdev, 0x1b00, iqk_cmd);
1672
1673		usleep_range(10000, 11000);
1674
1675		if (read_poll_timeout(!rtw_read32_mask, rx_ok, rx_ok,
1676				      1000, 20000, false,
1677				      rtwdev, 0x1b00, BIT(0))) {
1678			rtw_dbg(rtwdev, RTW_DBG_RFK,
1679				"rx iqk S%d timed out\n", path);
1680
1681			rtw8814a_iqk_reset_nctl(rtwdev);
1682		} else {
1683			rx_ok = !rtw_read32_mask(rtwdev, 0x1b08, BIT(26));
1684
1685			if (rx_ok)
1686				break;
1687		}
1688	}
1689
1690	rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d rx ==> 0x1b00 = 0x%x\n",
1691		path, rtw_read32(rtwdev, 0x1b00));
1692	rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d rx ==> 0x1b08 = 0x%x\n",
1693		path, rtw_read32(rtwdev, 0x1b08));
1694	rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d rx ==> cal_retry = %x\n",
1695		path, cal_retry);
1696
1697	rtw_write32(rtwdev, 0x1b00, 0xf8000000 | (path << 1));
1698
1699	if (rx_ok) {
1700		rtw_write32(rtwdev, 0x1b3c, 0x20000000);
1701		rx_matrix = rtw_read32(rtwdev, 0x1b3c);
1702
1703		rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d_IQC = 0x%x\n",
1704			path, rx_matrix);
1705	}
1706
1707	if (*tx_ok)
1708		rtw_write32(rtwdev, 0x1b38, *tx_matrix);
1709	else
1710		rtw_write32_mask(rtwdev, iqk_apply[path], BIT(0), 0x0);
1711
1712	if (!rx_ok)
1713		rtw_write32_mask(rtwdev, iqk_apply[path],
1714				 BIT(11) | BIT(10), 0x0);
1715
1716	if (band == RTW_BAND_2G)
1717		rtw_write_rf(rtwdev, path, RF_LUTDBG, BIT(11), 0x0);
1718}
1719
1720static void rtw8814a_iqk(struct rtw_dev *rtwdev)
1721{
1722	u8 band = rtwdev->hal.current_band_type;
1723	u8 bw = rtwdev->hal.current_band_width;
1724	u32 tx_matrix[RTW_RF_PATH_MAX];
1725	bool tx_ok[RTW_RF_PATH_MAX];
1726	u8 path;
1727
1728	rtw_dbg(rtwdev, RTW_DBG_RFK, "IQK band = %d GHz bw = %d MHz\n",
1729		band == RTW_BAND_2G ? 2 : 5, (1 << (bw + 1)) * 10);
1730
1731	rtw_write_rf(rtwdev, RF_PATH_A, RF_TXMOD, BIT(19), 0x1);
1732	rtw_write_rf(rtwdev, RF_PATH_B, RF_TXMOD, BIT(19), 0x1);
1733	rtw_write_rf(rtwdev, RF_PATH_C, RF_TXMOD, BIT(19), 0x1);
1734	rtw_write_rf(rtwdev, RF_PATH_D, RF_TXMOD, BIT(19), 0x1);
1735
1736	rtw_write32_mask(rtwdev, REG_TXAGCIDX,
1737			 (BIT(11) | BIT(10) | BIT(0)), 0x401);
1738	rtw_write32_mask(rtwdev, REG_TX_AGC_B,
1739			 (BIT(11) | BIT(10) | BIT(0)), 0x401);
1740	rtw_write32_mask(rtwdev, REG_TX_AGC_C,
1741			 (BIT(11) | BIT(10) | BIT(0)), 0x401);
1742	rtw_write32_mask(rtwdev, REG_TX_AGC_D,
1743			 (BIT(11) | BIT(10) | BIT(0)), 0x401);
1744
1745	if (band == RTW_BAND_5G)
1746		rtw_write32(rtwdev, 0x1b00, 0xf8000ff1);
1747	else
1748		rtw_write32(rtwdev, 0x1b00, 0xf8000ef1);
1749
1750	usleep_range(1000, 1100);
1751
1752	rtw_write32(rtwdev, 0x810, 0x20101063);
1753	rtw_write32(rtwdev, REG_DAC_RSTB, 0x0B00C000);
1754
1755	for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++)
1756		rtw8814a_lok_one_shot(rtwdev, path);
1757
1758	for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++)
1759		rtw8814a_iqk_tx_one_shot(rtwdev, path,
1760					 &tx_matrix[path], &tx_ok[path]);
1761
1762	for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++)
1763		rtw8814a_iqk_rx_one_shot(rtwdev, path,
1764					 &tx_matrix[path], &tx_ok[path]);
1765}
1766
1767static void rtw8814a_do_iqk(struct rtw_dev *rtwdev)
1768{
1769	static const u32 backup_mac_reg[MAC_REG_NUM_8814] = {0x520, 0x550};
1770	static const u32 backup_bb_reg[BB_REG_NUM_8814] = {
1771		0xa14, 0x808, 0x838, 0x90c, 0x810, 0xcb0, 0xeb0,
1772		0x18b4, 0x1ab4, 0x1abc, 0x9a4, 0x764, 0xcbc, 0x910
1773	};
1774	static const u32 backup_rf_reg[RF_REG_NUM_8814] = {0x0};
1775	u32 rf_backup[RF_REG_NUM_8814][RTW_RF_PATH_MAX];
1776	u32 mac_backup[MAC_REG_NUM_8814];
1777	u32 bb_backup[BB_REG_NUM_8814];
1778
1779	rtw8814a_iqk_backup_mac_bb(rtwdev, mac_backup, bb_backup,
1780				   backup_mac_reg, backup_bb_reg);
1781	rtw8814a_iqk_afe_setting(rtwdev, true);
1782	rtw8814a_iqk_backup_rf(rtwdev, rf_backup, backup_rf_reg);
1783	rtw8814a_iqk_configure_mac(rtwdev);
1784	rtw8814a_iqk(rtwdev);
1785	rtw8814a_iqk_reset_nctl(rtwdev); /* for 3-wire to BB use */
1786	rtw8814a_iqk_afe_setting(rtwdev, false);
1787	rtw8814a_iqk_restore_mac_bb(rtwdev, mac_backup, bb_backup,
1788				    backup_mac_reg, backup_bb_reg);
1789	rtw8814a_iqk_restore_rf(rtwdev, rf_backup, backup_rf_reg);
1790}
1791
1792static void rtw8814a_phy_calibration(struct rtw_dev *rtwdev)
1793{
1794	rtw8814a_do_iqk(rtwdev);
1795}
1796
1797static void rtw8814a_coex_cfg_init(struct rtw_dev *rtwdev)
1798{
1799}
1800
1801static void rtw8814a_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type,
1802					 u8 pos_type)
1803{
1804	/* Override rtw_coex_coex_ctrl_owner(). RF path C does not
1805	 * function when BIT_LTE_MUX_CTRL_PATH is set.
1806	 */
1807	rtw_write8_clr(rtwdev, REG_SYS_SDIO_CTRL + 3,
1808		       BIT_LTE_MUX_CTRL_PATH >> 24);
1809}
1810
1811static void rtw8814a_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
1812{
1813}
1814
1815static void rtw8814a_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
1816{
1817}
1818
1819static void rtw8814a_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
1820{
1821	struct rtw_coex *coex = &rtwdev->coex;
1822	struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1823
1824	/* Only needed to make rtw8814a_coex_cfg_ant_switch() run. */
1825	coex_rfe->ant_switch_exist = true;
1826}
1827
1828static void rtw8814a_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
1829{
1830}
1831
1832static void rtw8814a_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
1833{
1834}
1835
1836static void rtw8814a_txagc_swing_offset(struct rtw_dev *rtwdev, u8 path,
1837					u8 tx_pwr_idx_offset,
1838					s8 *txagc_idx, u8 *swing_idx)
1839{
1840	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1841	u8 swing_upper_bound = dm_info->default_ofdm_index + 10;
1842	s8 delta_pwr_idx = dm_info->delta_power_index[path];
1843	u8 swing_index = dm_info->default_ofdm_index;
1844	u8 max_tx_pwr_idx_offset = 0xf;
1845	u8 swing_lower_bound = 0;
1846	s8 agc_index = 0;
1847
1848	tx_pwr_idx_offset = min_t(u8, tx_pwr_idx_offset, max_tx_pwr_idx_offset);
1849
1850	if (delta_pwr_idx >= 0) {
1851		if (delta_pwr_idx <= tx_pwr_idx_offset) {
1852			agc_index = delta_pwr_idx;
1853			swing_index = dm_info->default_ofdm_index;
1854		} else if (delta_pwr_idx > tx_pwr_idx_offset) {
1855			agc_index = tx_pwr_idx_offset;
1856			swing_index = dm_info->default_ofdm_index +
1857					delta_pwr_idx - tx_pwr_idx_offset;
1858			swing_index = min_t(u8, swing_index, swing_upper_bound);
1859		}
1860	} else {
1861		if (dm_info->default_ofdm_index > abs(delta_pwr_idx))
1862			swing_index =
1863				dm_info->default_ofdm_index + delta_pwr_idx;
1864		else
1865			swing_index = swing_lower_bound;
1866		swing_index = max_t(u8, swing_index, swing_lower_bound);
1867
1868		agc_index = 0;
1869	}
1870
1871	if (swing_index >= RTW_TXSCALE_SIZE) {
1872		rtw_warn(rtwdev, "swing index overflow\n");
1873		swing_index = RTW_TXSCALE_SIZE - 1;
1874	}
1875	*txagc_idx = agc_index;
1876	*swing_idx = swing_index;
1877}
1878
1879static void rtw8814a_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 path,
1880				      u8 pwr_idx_offset)
1881{
1882	static const u32 txagc_reg[RTW_RF_PATH_MAX] = {
1883		REG_TX_AGC_A, REG_TX_AGC_B, REG_TX_AGC_C, REG_TX_AGC_D
1884	};
1885	static const u32 txscale_reg[RTW_RF_PATH_MAX] = {
1886		REG_TXSCALE_A, REG_TXSCALE_B, REG_TXSCALE_C, REG_TXSCALE_D
1887	};
1888	s8 txagc_idx;
1889	u8 swing_idx;
1890
1891	rtw8814a_txagc_swing_offset(rtwdev, path, pwr_idx_offset,
1892				    &txagc_idx, &swing_idx);
1893	rtw_write32_mask(rtwdev, txagc_reg[path], GENMASK(29, 25),
1894			 txagc_idx);
1895	rtw_write32_mask(rtwdev, txscale_reg[path], BB_SWING_MASK,
1896			 rtw8814a_txscale_tbl[swing_idx]);
1897}
1898
1899static void rtw8814a_pwrtrack_set(struct rtw_dev *rtwdev, u8 path)
1900{
1901	u8 max_pwr_idx = rtwdev->chip->max_power_index;
1902	u8 band_width = rtwdev->hal.current_band_width;
1903	u8 channel = rtwdev->hal.current_channel;
1904	u8 tx_rate = rtwdev->dm_info.tx_rate;
1905	u8 regd = rtw_regd_get(rtwdev);
1906	u8 pwr_idx_offset, tx_pwr_idx;
1907
1908	tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, path, tx_rate,
1909						band_width, channel, regd);
1910
1911	tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx);
1912
1913	pwr_idx_offset = max_pwr_idx - tx_pwr_idx;
1914
1915	rtw8814a_pwrtrack_set_pwr(rtwdev, path, pwr_idx_offset);
1916}
1917
1918static void rtw8814a_phy_pwrtrack_path(struct rtw_dev *rtwdev,
1919				       struct rtw_swing_table *swing_table,
1920				       u8 path)
1921{
1922	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1923	u8 power_idx_cur, power_idx_last;
1924	u8 delta;
1925
1926	/* 8814A only has one thermal meter at PATH A */
1927	delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A);
1928
1929	power_idx_last = dm_info->delta_power_index[path];
1930	power_idx_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table,
1931						    path, RF_PATH_A, delta);
1932
1933	/* if delta of power indexes are the same, just skip */
1934	if (power_idx_cur == power_idx_last)
1935		return;
1936
1937	dm_info->delta_power_index[path] = power_idx_cur;
1938	rtw8814a_pwrtrack_set(rtwdev, path);
1939}
1940
1941static void rtw8814a_phy_pwrtrack(struct rtw_dev *rtwdev)
1942{
1943	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1944	struct rtw_swing_table swing_table;
1945	u8 thermal_value, path;
1946
1947	rtw_phy_config_swing_table(rtwdev, &swing_table);
1948
1949	if (rtwdev->efuse.thermal_meter[RF_PATH_A] == 0xff)
1950		return;
1951
1952	thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1953
1954	rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A);
1955
1956	if (dm_info->pwr_trk_init_trigger)
1957		dm_info->pwr_trk_init_trigger = false;
1958	else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value,
1959						   RF_PATH_A))
1960		goto iqk;
1961
1962	for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++)
1963		rtw8814a_phy_pwrtrack_path(rtwdev, &swing_table, path);
1964
1965iqk:
1966	if (rtw_phy_pwrtrack_need_iqk(rtwdev))
1967		rtw8814a_do_iqk(rtwdev);
1968}
1969
1970static void rtw8814a_pwr_track(struct rtw_dev *rtwdev)
1971{
1972	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1973
1974	if (!dm_info->pwr_trk_triggered) {
1975		rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER,
1976			     GENMASK(17, 16), 0x03);
1977		dm_info->pwr_trk_triggered = true;
1978		return;
1979	}
1980
1981	rtw8814a_phy_pwrtrack(rtwdev);
1982	dm_info->pwr_trk_triggered = false;
1983}
1984
1985static void rtw8814a_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
1986{
1987	static const u8 pd[CCK_PD_LV_MAX] = {0x40, 0x83, 0xcd, 0xdd, 0xed};
1988	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1989
1990	/* Override rtw_phy_cck_pd_lv_link(). It implements something
1991	 * like type 2/3/4. We need type 1 here.
1992	 */
1993	if (rtw_is_assoc(rtwdev)) {
1994		if (dm_info->min_rssi > 60) {
1995			new_lvl = CCK_PD_LV3;
1996		} else if (dm_info->min_rssi > 35) {
1997			new_lvl = CCK_PD_LV2;
1998		} else if (dm_info->min_rssi > 20) {
1999			if (dm_info->cck_fa_avg > 500)
2000				new_lvl = CCK_PD_LV2;
2001			else if (dm_info->cck_fa_avg < 250)
2002				new_lvl = CCK_PD_LV1;
2003			else
2004				return;
2005		} else {
2006			new_lvl = CCK_PD_LV1;
2007		}
2008	}
2009
2010	rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n",
2011		dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl);
2012
2013	if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl)
2014		return;
2015
2016	dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
2017	dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl;
2018
2019	rtw_write8(rtwdev, REG_CCK_PD_TH, pd[new_lvl]);
2020}
2021
2022static void rtw8814a_led_set(struct led_classdev *led,
2023			     enum led_brightness brightness)
2024{
2025	struct rtw_dev *rtwdev = container_of(led, struct rtw_dev, led_cdev);
2026	u32 led_gpio_cfg;
2027
2028	led_gpio_cfg = rtw_read32(rtwdev, REG_GPIO_PIN_CTRL_2);
2029	led_gpio_cfg |= BIT(16) | BIT(17) | BIT(21) | BIT(22);
2030
2031	if (brightness == LED_OFF) {
2032		led_gpio_cfg |= BIT(8) | BIT(9) | BIT(13) | BIT(14);
2033	} else {
2034		led_gpio_cfg &= ~(BIT(8) | BIT(9) | BIT(13) | BIT(14));
2035		led_gpio_cfg &= ~(BIT(0) | BIT(1) | BIT(5) | BIT(6));
2036	}
2037
2038	rtw_write32(rtwdev, REG_GPIO_PIN_CTRL_2, led_gpio_cfg);
2039}
2040
2041static void rtw8814a_fill_txdesc_checksum(struct rtw_dev *rtwdev,
2042					  struct rtw_tx_pkt_info *pkt_info,
2043					  u8 *txdesc)
2044{
2045	size_t words = 32 / 2; /* calculate the first 32 bytes (16 words) */
2046
2047	fill_txdesc_checksum_common(txdesc, words);
2048}
2049
2050static const struct rtw_chip_ops rtw8814a_ops = {
2051	.power_on		= rtw_power_on,
2052	.power_off		= rtw_power_off,
2053	.phy_set_param		= rtw8814a_phy_set_param,
2054	.read_efuse		= rtw8814a_read_efuse,
2055	.query_phy_status	= rtw8814a_query_phy_status,
2056	.set_channel		= rtw8814a_set_channel,
2057	.mac_init		= rtw8814a_mac_init,
2058	.mac_postinit		= NULL,
2059	.read_rf		= rtw_phy_read_rf,
2060	.write_rf		= rtw_phy_write_rf_reg_sipi,
2061	.set_tx_power_index	= rtw8814a_set_tx_power_index,
2062	.set_antenna		= NULL,
2063	.cfg_ldo25		= rtw8814a_cfg_ldo25,
2064	.efuse_grant		= rtw8814a_efuse_grant,
2065	.set_ampdu_factor	= rtw8814a_set_ampdu_factor,
2066	.false_alarm_statistics	= rtw8814a_false_alarm_statistics,
2067	.phy_calibration	= rtw8814a_phy_calibration,
2068	.cck_pd_set		= rtw8814a_phy_cck_pd_set,
2069	.pwr_track		= rtw8814a_pwr_track,
2070	.config_bfee		= NULL,
2071	.set_gid_table		= NULL,
2072	.cfg_csi_rate		= NULL,
2073	.led_set		= rtw8814a_led_set,
2074	.fill_txdesc_checksum	= rtw8814a_fill_txdesc_checksum,
2075
2076	.coex_set_init		= rtw8814a_coex_cfg_init,
2077	.coex_set_ant_switch	= rtw8814a_coex_cfg_ant_switch,
2078	.coex_set_gnt_fix	= rtw8814a_coex_cfg_gnt_fix,
2079	.coex_set_gnt_debug	= rtw8814a_coex_cfg_gnt_debug,
2080	.coex_set_rfe_type	= rtw8814a_coex_cfg_rfe_type,
2081	.coex_set_wl_tx_power	= rtw8814a_coex_cfg_wl_tx_power,
2082	.coex_set_wl_rx_gain	= rtw8814a_coex_cfg_wl_rx_gain,
2083};
2084
2085static const struct rtw_rqpn rqpn_table_8814a[] = {
2086	/* SDIO */
2087	{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, /* vo vi */
2088	 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,	 /* be bk */
2089	 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},	 /* mg hi */
2090	/* PCIE */
2091	{RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_NORMAL,
2092	 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2093	 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
2094	/* USB, 2 bulk out */
2095	{RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH,
2096	 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2097	 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
2098	/* USB, 3 bulk out */
2099	{RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_NORMAL,
2100	 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2101	 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
2102	/* USB, 4 bulk out */
2103	{RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_NORMAL,
2104	 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2105	 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
2106};
2107
2108static const struct rtw_prioq_addrs prioq_addrs_8814a = {
2109	.prio[RTW_DMA_MAPPING_EXTRA] = {
2110		.rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2,
2111	},
2112	.prio[RTW_DMA_MAPPING_LOW] = {
2113		.rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2,
2114	},
2115	.prio[RTW_DMA_MAPPING_NORMAL] = {
2116		.rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2,
2117	},
2118	.prio[RTW_DMA_MAPPING_HIGH] = {
2119		.rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2,
2120	},
2121	.wsize = true,
2122};
2123
2124static const struct rtw_page_table page_table_8814a[] = {
2125	/* SDIO */
2126	{0, 0, 0, 0, 0},	/* hq nq lq exq gapq */
2127	/* PCIE */
2128	{32, 32, 32, 32, 0},
2129	/* USB, 2 bulk out */
2130	{32, 32, 32, 32, 0},
2131	/* USB, 3 bulk out */
2132	{32, 32, 32, 32, 0},
2133	/* USB, 4 bulk out */
2134	{32, 32, 32, 32, 0},
2135};
2136
2137static const struct rtw_intf_phy_para_table phy_para_table_8814a = {};
2138
2139static const struct rtw_hw_reg rtw8814a_dig[] = {
2140	[0] = { .addr = 0xc50, .mask = 0x7f },
2141	[1] = { .addr = 0xe50, .mask = 0x7f },
2142	[2] = { .addr = 0x1850, .mask = 0x7f },
2143	[3] = { .addr = 0x1a50, .mask = 0x7f },
2144};
2145
2146static const struct rtw_rfe_def rtw8814a_rfe_defs[] = {
2147	[0] = { .phy_pg_tbl	= &rtw8814a_bb_pg_type0_tbl,
2148		.txpwr_lmt_tbl	= &rtw8814a_txpwr_lmt_type0_tbl,
2149		.pwr_track_tbl	= &rtw8814a_rtw_pwrtrk_type0_tbl },
2150	[1] = { .phy_pg_tbl	= &rtw8814a_bb_pg_tbl,
2151		.txpwr_lmt_tbl	= &rtw8814a_txpwr_lmt_type1_tbl,
2152		.pwr_track_tbl	= &rtw8814a_rtw_pwrtrk_tbl },
2153};
2154
2155/* rssi in percentage % (dbm = % - 100) */
2156static const u8 wl_rssi_step_8814a[] = {60, 50, 44, 30};
2157static const u8 bt_rssi_step_8814a[] = {30, 30, 30, 30};
2158
2159/* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
2160static const struct coex_rf_para rf_para_tx_8814a[] = {
2161	{0, 0, false, 7},  /* for normal */
2162	{0, 16, false, 7}, /* for WL-CPT */
2163	{4, 0, true, 1},
2164	{3, 6, true, 1},
2165	{2, 9, true, 1},
2166	{1, 13, true, 1}
2167};
2168
2169static const struct coex_rf_para rf_para_rx_8814a[] = {
2170	{0, 0, false, 7},  /* for normal */
2171	{0, 16, false, 7}, /* for WL-CPT */
2172	{4, 0, true, 1},
2173	{3, 6, true, 1},
2174	{2, 9, true, 1},
2175	{1, 13, true, 1}
2176};
2177
2178static_assert(ARRAY_SIZE(rf_para_tx_8814a) == ARRAY_SIZE(rf_para_rx_8814a));
2179
2180const struct rtw_chip_info rtw8814a_hw_spec = {
2181	.ops = &rtw8814a_ops,
2182	.id = RTW_CHIP_TYPE_8814A,
2183	.fw_name = "rtw88/rtw8814a_fw.bin",
2184	.wlan_cpu = RTW_WCPU_3081,
2185	.tx_pkt_desc_sz = 40,
2186	.tx_buf_desc_sz = 16,
2187	.rx_pkt_desc_sz = 24,
2188	.rx_buf_desc_sz = 8,
2189	.phy_efuse_size = 1024,
2190	.log_efuse_size = 512,
2191	.ptct_efuse_size = 0,
2192	.txff_size = (2048 - 10) * TX_PAGE_SIZE,
2193	.rxff_size = 23552,
2194	.rsvd_drv_pg_num = 8,
2195	.band = RTW_BAND_2G | RTW_BAND_5G,
2196	.page_size = TX_PAGE_SIZE,
2197	.csi_buf_pg_num = 0,
2198	.dig_min = 0x1c,
2199	.txgi_factor = 1,
2200	.is_pwr_by_rate_dec = true,
2201	.rx_ldpc = true,
2202	.max_power_index = 0x3f,
2203	.ampdu_density = IEEE80211_HT_MPDU_DENSITY_2,
2204	.amsdu_in_ampdu = false, /* RX speed is better without AMSDU */
2205	.usb_tx_agg_desc_num = 3,
2206	.hw_feature_report = false,
2207	.c2h_ra_report_size = 6,
2208	.old_datarate_fb_limit = false,
2209	.ht_supported = true,
2210	.vht_supported = true,
2211	.lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),
2212	.sys_func_en = 0xDC,
2213	.pwr_on_seq = card_enable_flow_8814a,
2214	.pwr_off_seq = card_disable_flow_8814a,
2215	.rqpn_table = rqpn_table_8814a,
2216	.prioq_addrs = &prioq_addrs_8814a,
2217	.page_table = page_table_8814a,
2218	.intf_table = &phy_para_table_8814a,
2219	.dig = rtw8814a_dig,
2220	.dig_cck = NULL,
2221	.rf_base_addr = {0x2800, 0x2c00, 0x3800, 0x3c00},
2222	.rf_sipi_addr = {0xc90, 0xe90, 0x1890, 0x1a90},
2223	.ltecoex_addr = NULL,
2224	.mac_tbl = &rtw8814a_mac_tbl,
2225	.agc_tbl = &rtw8814a_agc_tbl,
2226	.bb_tbl = &rtw8814a_bb_tbl,
2227	.rf_tbl = {&rtw8814a_rf_a_tbl, &rtw8814a_rf_b_tbl,
2228		   &rtw8814a_rf_c_tbl, &rtw8814a_rf_d_tbl},
2229	.rfe_defs = rtw8814a_rfe_defs,
2230	.rfe_defs_size = ARRAY_SIZE(rtw8814a_rfe_defs),
2231	.iqk_threshold = 8,
2232	.max_scan_ie_len = IEEE80211_MAX_DATA_LEN,
2233
2234	.coex_para_ver = 0,
2235	.bt_desired_ver = 0,
2236	.scbd_support = false,
2237	.new_scbd10_def = false,
2238	.ble_hid_profile_support = false,
2239	.wl_mimo_ps_support = false,
2240	.pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
2241	.bt_rssi_type = COEX_BTRSSI_RATIO,
2242	.ant_isolation = 15,
2243	.rssi_tolerance = 2,
2244	.wl_rssi_step = wl_rssi_step_8814a,
2245	.bt_rssi_step = bt_rssi_step_8814a,
2246	.table_sant_num = 0,
2247	.table_sant = NULL,
2248	.table_nsant_num = 0,
2249	.table_nsant = NULL,
2250	.tdma_sant_num = 0,
2251	.tdma_sant = NULL,
2252	.tdma_nsant_num = 0,
2253	.tdma_nsant = NULL,
2254	.wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8814a),
2255	.wl_rf_para_tx = rf_para_tx_8814a,
2256	.wl_rf_para_rx = rf_para_rx_8814a,
2257	.bt_afh_span_bw20 = 0x24,
2258	.bt_afh_span_bw40 = 0x36,
2259	.afh_5g_num = 0,
2260	.afh_5g = NULL,
2261	.coex_info_hw_regs_num = 0,
2262	.coex_info_hw_regs = NULL,
2263};
2264EXPORT_SYMBOL(rtw8814a_hw_spec);
2265
2266MODULE_FIRMWARE("rtw88/rtw8814a_fw.bin");
2267
2268MODULE_AUTHOR("Bitterblue Smith <rtl8821cerfe2@gmail.com>");
2269MODULE_DESCRIPTION("Realtek 802.11ac wireless 8814a driver");
2270MODULE_LICENSE("Dual BSD/GPL");