rtw8812a.c

   1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2/* Copyright(c) 2024  Realtek Corporation
   3 */
   4
   5#include "main.h"
   6#include "coex.h"
   7#include "phy.h"
   8#include "reg.h"
   9#include "rtw88xxa.h"
  10#include "rtw8812a.h"
  11#include "rtw8812a_table.h"
  12#include "tx.h"
  13
  14static void rtw8812a_power_off(struct rtw_dev *rtwdev)
  15{
  16	rtw88xxa_power_off(rtwdev, enter_lps_flow_8812a);
  17}
  18
  19static s8 rtw8812a_cck_rx_pwr(u8 lna_idx, u8 vga_idx)
  20{
  21	s8 rx_pwr_all = 0;
  22
  23	switch (lna_idx) {
  24	case 7:
  25		if (vga_idx <= 27)
  26			rx_pwr_all = -94 + 2 * (27 - vga_idx);
  27		else
  28			rx_pwr_all = -94;
  29		break;
  30	case 6:
  31		rx_pwr_all = -42 + 2 * (2 - vga_idx);
  32		break;
  33	case 5:
  34		rx_pwr_all = -36 + 2 * (7 - vga_idx);
  35		break;
  36	case 4:
  37		rx_pwr_all = -30 + 2 * (7 - vga_idx);
  38		break;
  39	case 3:
  40		rx_pwr_all = -18 + 2 * (7 - vga_idx);
  41		break;
  42	case 2:
  43		rx_pwr_all = 2 * (5 - vga_idx);
  44		break;
  45	case 1:
  46		rx_pwr_all = 14 - 2 * vga_idx;
  47		break;
  48	case 0:
  49		rx_pwr_all = 20 - 2 * vga_idx;
  50		break;
  51	default:
  52		break;
  53	}
  54
  55	return rx_pwr_all;
  56}
  57
  58static void rtw8812a_query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
  59				      struct rtw_rx_pkt_stat *pkt_stat)
  60{
  61	rtw88xxa_query_phy_status(rtwdev, phy_status, pkt_stat,
  62				  rtw8812a_cck_rx_pwr);
  63
  64	if (pkt_stat->rate >= DESC_RATE6M)
  65		return;
  66
  67	if (rtwdev->hal.cck_high_power)
  68		return;
  69
  70	if (pkt_stat->rssi >= 80)
  71		pkt_stat->rssi = ((pkt_stat->rssi - 80) << 1) +
  72				 ((pkt_stat->rssi - 80) >> 1) + 80;
  73	else if (pkt_stat->rssi <= 78 && pkt_stat->rssi >= 20)
  74		pkt_stat->rssi += 3;
  75}
  76
  77static void rtw8812a_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
  78{
  79}
  80
  81static void rtw8812a_do_lck(struct rtw_dev *rtwdev)
  82{
  83	u32 cont_tx, lc_cal, i;
  84
  85	cont_tx = rtw_read32_mask(rtwdev, REG_SINGLE_TONE_CONT_TX, 0x70000);
  86
  87	lc_cal = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK);
  88
  89	if (!cont_tx)
  90		rtw_write8(rtwdev, REG_TXPAUSE, 0xff);
  91
  92	rtw_write_rf(rtwdev, RF_PATH_A, RF_LCK, BIT(14), 1);
  93
  94	rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, 0x08000, 1);
  95
  96	mdelay(150);
  97
  98	for (i = 0; i < 5; i++) {
  99		if (rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, 0x08000) != 1)
 100			break;
 101
 102		mdelay(10);
 103	}
 104
 105	if (i == 5)
 106		rtw_dbg(rtwdev, RTW_DBG_RFK, "LCK timed out\n");
 107
 108	rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal);
 109
 110	rtw_write_rf(rtwdev, RF_PATH_A, RF_LCK, BIT(14), 0);
 111
 112	if (!cont_tx)
 113		rtw_write8(rtwdev, REG_TXPAUSE, 0);
 114
 115	rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal);
 116}
 117
 118static void rtw8812a_iqk_backup_rf(struct rtw_dev *rtwdev, u32 *rfa_backup,
 119				   u32 *rfb_backup, const u32 *backup_rf_reg,
 120				   u32 rf_num)
 121{
 122	u32 i;
 123
 124	/* [31] = 0 --> Page C */
 125	rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
 126
 127	/* Save RF Parameters */
 128	for (i = 0; i < rf_num; i++) {
 129		rfa_backup[i] = rtw_read_rf(rtwdev, RF_PATH_A,
 130					    backup_rf_reg[i], MASKDWORD);
 131		rfb_backup[i] = rtw_read_rf(rtwdev, RF_PATH_B,
 132					    backup_rf_reg[i], MASKDWORD);
 133	}
 134}
 135
 136static void rtw8812a_iqk_restore_rf(struct rtw_dev *rtwdev,
 137				    enum rtw_rf_path path,
 138				    const u32 *backup_rf_reg,
 139				    u32 *RF_backup, u32 rf_reg_num)
 140{
 141	u32 i;
 142
 143	/* [31] = 0 --> Page C */
 144	rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
 145
 146	for (i = 0; i < rf_reg_num; i++)
 147		rtw_write_rf(rtwdev, path, backup_rf_reg[i],
 148			     RFREG_MASK, RF_backup[i]);
 149
 150	rtw_write_rf(rtwdev, path, RF_LUTWE, RFREG_MASK, 0);
 151}
 152
 153static void rtw8812a_iqk_restore_afe(struct rtw_dev *rtwdev, u32 *afe_backup,
 154				     const u32 *backup_afe_reg, u32 afe_num)
 155{
 156	u32 i;
 157
 158	/* [31] = 0 --> Page C */
 159	rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
 160
 161	/* Reload AFE Parameters */
 162	for (i = 0; i < afe_num; i++)
 163		rtw_write32(rtwdev, backup_afe_reg[i], afe_backup[i]);
 164
 165	/* [31] = 1 --> Page C1 */
 166	rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x1);
 167
 168	rtw_write32(rtwdev, REG_OFDM0_XA_TX_IQ_IMBALANCE, 0x0);
 169	rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x0);
 170	rtw_write32(rtwdev, REG_OFDM0_XB_TX_IQ_IMBALANCE, 0x0);
 171	rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x3c000000);
 172	rtw_write32_mask(rtwdev, REG_LSSI_WRITE_A, BIT(7), 1);
 173	rtw_write32_mask(rtwdev, REG_IQK_DPD_CFG, BIT(18), 1);
 174	rtw_write32_mask(rtwdev, REG_IQK_DPD_CFG, BIT(29), 1);
 175	rtw_write32_mask(rtwdev, REG_CFG_PMPD, BIT(29), 1);
 176
 177	rtw_write32(rtwdev, REG_TXTONEB, 0x0);
 178	rtw_write32(rtwdev, REG_RXTONEB, 0x0);
 179	rtw_write32(rtwdev, REG_TXPITMB, 0x0);
 180	rtw_write32(rtwdev, REG_RXPITMB, 0x3c000000);
 181	rtw_write32_mask(rtwdev, REG_LSSI_WRITE_B, BIT(7), 1);
 182	rtw_write32_mask(rtwdev, REG_BPBDB, BIT(18), 1);
 183	rtw_write32_mask(rtwdev, REG_BPBDB, BIT(29), 1);
 184	rtw_write32_mask(rtwdev, REG_PHYTXONB, BIT(29), 1);
 185}
 186
 187static void rtw8812a_iqk_rx_fill(struct rtw_dev *rtwdev, enum rtw_rf_path path,
 188				 unsigned int rx_x, unsigned int rx_y)
 189{
 190	switch (path) {
 191	case RF_PATH_A:
 192		/* [31] = 0 --> Page C */
 193		rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
 194		if (rx_x >> 1 >= 0x112 ||
 195		    (rx_y >> 1 >= 0x12 && rx_y >> 1 <= 0x3ee)) {
 196			rtw_write32_mask(rtwdev, REG_RX_IQC_AB_A,
 197					 0x000003ff, 0x100);
 198			rtw_write32_mask(rtwdev, REG_RX_IQC_AB_A,
 199					 0x03ff0000, 0);
 200		} else {
 201			rtw_write32_mask(rtwdev, REG_RX_IQC_AB_A,
 202					 0x000003ff, rx_x >> 1);
 203			rtw_write32_mask(rtwdev, REG_RX_IQC_AB_A,
 204					 0x03ff0000, rx_y >> 1);
 205		}
 206		rtw_dbg(rtwdev, RTW_DBG_RFK,
 207			"rx_x = %x;;rx_y = %x ====>fill to IQC\n",
 208			rx_x >> 1 & 0x000003ff, rx_y >> 1 & 0x000003ff);
 209		rtw_dbg(rtwdev, RTW_DBG_RFK, "0xc10 = %x ====>fill to IQC\n",
 210			rtw_read32(rtwdev, REG_RX_IQC_AB_A));
 211		break;
 212	case RF_PATH_B:
 213		/* [31] = 0 --> Page C */
 214		rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
 215		if (rx_x >> 1 >= 0x112 ||
 216		    (rx_y >> 1 >= 0x12 && rx_y >> 1 <= 0x3ee)) {
 217			rtw_write32_mask(rtwdev, REG_RX_IQC_AB_B,
 218					 0x000003ff, 0x100);
 219			rtw_write32_mask(rtwdev, REG_RX_IQC_AB_B,
 220					 0x03ff0000, 0);
 221		} else {
 222			rtw_write32_mask(rtwdev, REG_RX_IQC_AB_B,
 223					 0x000003ff, rx_x >> 1);
 224			rtw_write32_mask(rtwdev, REG_RX_IQC_AB_B,
 225					 0x03ff0000, rx_y >> 1);
 226		}
 227		rtw_dbg(rtwdev, RTW_DBG_RFK,
 228			"rx_x = %x;;rx_y = %x ====>fill to IQC\n",
 229			rx_x >> 1 & 0x000003ff, rx_y >> 1 & 0x000003ff);
 230		rtw_dbg(rtwdev, RTW_DBG_RFK, "0xe10 = %x====>fill to IQC\n",
 231			rtw_read32(rtwdev, REG_RX_IQC_AB_B));
 232		break;
 233	default:
 234		break;
 235	}
 236}
 237
 238static void rtw8812a_iqk_tx_fill(struct rtw_dev *rtwdev, enum rtw_rf_path path,
 239				 unsigned int tx_x, unsigned int tx_y)
 240{
 241	switch (path) {
 242	case RF_PATH_A:
 243		/* [31] = 1 --> Page C1 */
 244		rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x1);
 245		rtw_write32_mask(rtwdev, REG_PREDISTA, BIT(7), 0x1);
 246		rtw_write32_mask(rtwdev, REG_IQK_DPD_CFG, BIT(18), 0x1);
 247		rtw_write32_mask(rtwdev, REG_IQK_DPD_CFG, BIT(29), 0x1);
 248		rtw_write32_mask(rtwdev, REG_CFG_PMPD, BIT(29), 0x1);
 249		rtw_write32_mask(rtwdev, REG_IQC_Y, 0x000007ff, tx_y);
 250		rtw_write32_mask(rtwdev, REG_IQC_X, 0x000007ff, tx_x);
 251		rtw_dbg(rtwdev, RTW_DBG_RFK,
 252			"tx_x = %x;;tx_y = %x =====> fill to IQC\n",
 253			tx_x & 0x000007ff, tx_y & 0x000007ff);
 254		rtw_dbg(rtwdev, RTW_DBG_RFK,
 255			"0xcd4 = %x;;0xccc = %x ====>fill to IQC\n",
 256			rtw_read32_mask(rtwdev, REG_IQC_X, 0x000007ff),
 257			rtw_read32_mask(rtwdev, REG_IQC_Y, 0x000007ff));
 258		break;
 259	case RF_PATH_B:
 260		/* [31] = 1 --> Page C1 */
 261		rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x1);
 262		rtw_write32_mask(rtwdev, REG_PREDISTB, BIT(7), 0x1);
 263		rtw_write32_mask(rtwdev, REG_BPBDB, BIT(18), 0x1);
 264		rtw_write32_mask(rtwdev, REG_BPBDB, BIT(29), 0x1);
 265		rtw_write32_mask(rtwdev, REG_PHYTXONB, BIT(29), 0x1);
 266		rtw_write32_mask(rtwdev, REG_IQKYB, 0x000007ff, tx_y);
 267		rtw_write32_mask(rtwdev, REG_IQKXB, 0x000007ff, tx_x);
 268		rtw_dbg(rtwdev, RTW_DBG_RFK,
 269			"tx_x = %x;;tx_y = %x =====> fill to IQC\n",
 270			tx_x & 0x000007ff, tx_y & 0x000007ff);
 271		rtw_dbg(rtwdev, RTW_DBG_RFK,
 272			"0xed4 = %x;;0xecc = %x ====>fill to IQC\n",
 273			rtw_read32_mask(rtwdev, REG_IQKXB, 0x000007ff),
 274			rtw_read32_mask(rtwdev, REG_IQKYB, 0x000007ff));
 275		break;
 276	default:
 277		break;
 278	}
 279}
 280
 281static void rtw8812a_iqk(struct rtw_dev *rtwdev)
 282{
 283	int tx_x0_temp[10], tx_y0_temp[10], tx_x1_temp[10], tx_y1_temp[10];
 284	int rx_x0_temp[10], rx_y0_temp[10], rx_x1_temp[10], rx_y1_temp[10];
 285	bool iqk0_ready = false, tx0_finish = false, rx0_finish = false;
 286	bool iqk1_ready = false, tx1_finish = false, rx1_finish = false;
 287	u8 tx0_avg = 0, tx1_avg = 0, rx0_avg = 0, rx1_avg = 0;
 288	int tx_x0 = 0, tx_y0 = 0, tx_x1 = 0, tx_y1 = 0;
 289	int rx_x0 = 0, rx_y0 = 0, rx_x1 = 0, rx_y1 = 0;
 290	struct rtw_efuse *efuse = &rtwdev->efuse;
 291	bool tx0_fail = true, rx0_fail = true;
 292	bool tx1_fail = true, rx1_fail = true;
 293	u8 cal0_retry, cal1_retry;
 294	u8 delay_count;
 295
 296	/* [31] = 0 --> Page C */
 297	rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
 298
 299	/* ========path-A AFE all on======== */
 300	/* Port 0 DAC/ADC on */
 301	rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x77777777);
 302	rtw_write32(rtwdev, REG_AFE_PWR2_A, 0x77777777);
 303
 304	/* Port 1 DAC/ADC on */
 305	rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x77777777);
 306	rtw_write32(rtwdev, REG_AFE_PWR2_B, 0x77777777);
 307
 308	rtw_write32(rtwdev, REG_RX_WAIT_CCA_TX_CCK_RFON_A, 0x19791979);
 309	rtw_write32(rtwdev, REG_RX_WAIT_CCA_TX_CCK_RFON_B, 0x19791979);
 310
 311	/* hardware 3-wire off */
 312	rtw_write32_mask(rtwdev, REG_3WIRE_SWA, 0xf, 0x4);
 313	rtw_write32_mask(rtwdev, REG_3WIRE_SWB, 0xf, 0x4);
 314
 315	/* DAC/ADC sampling rate (160 MHz) */
 316	rtw_write32_mask(rtwdev, REG_CK_MONHA, GENMASK(26, 24), 0x7);
 317	rtw_write32_mask(rtwdev, REG_CK_MONHB, GENMASK(26, 24), 0x7);
 318
 319	/* [31] = 0 --> Page C */
 320	rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
 321	/* ====== path A TX IQK RF setting ====== */
 322	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80002);
 323	rtw_write_rf(rtwdev, RF_PATH_A, RF_MODE_TABLE_ADDR, RFREG_MASK, 0x20000);
 324	rtw_write_rf(rtwdev, RF_PATH_A, RF_MODE_TABLE_DATA0, RFREG_MASK, 0x3fffd);
 325	rtw_write_rf(rtwdev, RF_PATH_A, RF_MODE_TABLE_DATA1, RFREG_MASK, 0xfe83f);
 326	rtw_write_rf(rtwdev, RF_PATH_A, RF_TXA_PREPAD, RFREG_MASK, 0x931d5);
 327	rtw_write_rf(rtwdev, RF_PATH_A, RF_RXBB2, RFREG_MASK, 0x8a001);
 328
 329	/* ====== path B TX IQK RF setting ====== */
 330	rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE, RFREG_MASK, 0x80002);
 331	rtw_write_rf(rtwdev, RF_PATH_B, RF_MODE_TABLE_ADDR, RFREG_MASK, 0x20000);
 332	rtw_write_rf(rtwdev, RF_PATH_B, RF_MODE_TABLE_DATA0, RFREG_MASK, 0x3fffd);
 333	rtw_write_rf(rtwdev, RF_PATH_B, RF_MODE_TABLE_DATA1, RFREG_MASK, 0xfe83f);
 334	rtw_write_rf(rtwdev, RF_PATH_B, RF_TXA_PREPAD, RFREG_MASK, 0x931d5);
 335	rtw_write_rf(rtwdev, RF_PATH_B, RF_RXBB2, RFREG_MASK, 0x8a001);
 336
 337	rtw_write32(rtwdev, REG_DAC_RSTB, 0x00008000);
 338	rtw_write32_mask(rtwdev, REG_TXAGCIDX, BIT(0), 0x1);
 339	rtw_write32_mask(rtwdev, REG_INIDLYB, BIT(0), 0x1);
 340	rtw_write32(rtwdev, REG_IQK_COM00, 0x29002000); /* TX (X,Y) */
 341	rtw_write32(rtwdev, REG_IQK_COM32, 0xa9002000); /* RX (X,Y) */
 342	rtw_write32(rtwdev, REG_IQK_COM96, 0x00462910); /* [0]:AGC_en, [15]:idac_K_Mask */
 343	/* [31] = 1 --> Page C1 */
 344	rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x1);
 345
 346	if (efuse->ext_pa_5g) {
 347		if (efuse->rfe_option == 1) {
 348			rtw_write32(rtwdev, REG_OFDM0_XB_TX_IQ_IMBALANCE, 0x821403e3);
 349			rtw_write32(rtwdev, REG_TXPITMB, 0x821403e3);
 350		} else {
 351			rtw_write32(rtwdev, REG_OFDM0_XB_TX_IQ_IMBALANCE, 0x821403f7);
 352			rtw_write32(rtwdev, REG_TXPITMB, 0x821403f7);
 353		}
 354	} else {
 355		rtw_write32(rtwdev, REG_OFDM0_XB_TX_IQ_IMBALANCE, 0x821403f1);
 356		rtw_write32(rtwdev, REG_TXPITMB, 0x821403f1);
 357	}
 358
 359	if (rtwdev->hal.current_band_type == RTW_BAND_5G) {
 360		rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x68163e96);
 361		rtw_write32(rtwdev, REG_RXPITMB, 0x68163e96);
 362	} else {
 363		rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x28163e96);
 364		rtw_write32(rtwdev, REG_RXPITMB, 0x28163e96);
 365
 366		if (efuse->rfe_option == 3) {
 367			if (efuse->ext_pa_2g)
 368				rtw_write32(rtwdev, REG_OFDM0_XB_TX_IQ_IMBALANCE,
 369					    0x821403e3);
 370			else
 371				rtw_write32(rtwdev, REG_OFDM0_XB_TX_IQ_IMBALANCE,
 372					    0x821403f7);
 373		}
 374	}
 375
 376	/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
 377	rtw_write32(rtwdev, REG_OFDM0_XA_TX_IQ_IMBALANCE, 0x18008c10);
 378	/* RX_Tone_idx[9:0], RxK_Mask[29] */
 379	rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x38008c10);
 380	rtw_write32(rtwdev, REG_INTPO_SETA, 0x00000000);
 381	/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
 382	rtw_write32(rtwdev, REG_TXTONEB, 0x18008c10);
 383	/* RX_Tone_idx[9:0], RxK_Mask[29] */
 384	rtw_write32(rtwdev, REG_RXTONEB, 0x38008c10);
 385	rtw_write32(rtwdev, REG_INTPO_SETB, 0x00000000);
 386
 387	cal0_retry = 0;
 388	cal1_retry = 0;
 389	while (1) {
 390		/* one shot */
 391		rtw_write32(rtwdev, REG_RFECTL_A, 0x00100000);
 392		rtw_write32(rtwdev, REG_RFECTL_B, 0x00100000);
 393		rtw_write32(rtwdev, REG_IQK_COM64, 0xfa000000);
 394		rtw_write32(rtwdev, REG_IQK_COM64, 0xf8000000);
 395
 396		mdelay(10);
 397
 398		rtw_write32(rtwdev, REG_RFECTL_A, 0x00000000);
 399		rtw_write32(rtwdev, REG_RFECTL_B, 0x00000000);
 400
 401		for (delay_count = 0; delay_count < 20; delay_count++) {
 402			if (!tx0_finish)
 403				iqk0_ready = rtw_read32_mask(rtwdev,
 404							     REG_IQKA_END,
 405							     BIT(10));
 406			if (!tx1_finish)
 407				iqk1_ready = rtw_read32_mask(rtwdev,
 408							     REG_IQKB_END,
 409							     BIT(10));
 410			if (iqk0_ready && iqk1_ready)
 411				break;
 412
 413			mdelay(1);
 414		}
 415
 416		rtw_dbg(rtwdev, RTW_DBG_RFK, "TX delay_count = %d\n",
 417			delay_count);
 418
 419		if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
 420			/* ============TXIQK Check============== */
 421			tx0_fail = rtw_read32_mask(rtwdev, REG_IQKA_END, BIT(12));
 422			tx1_fail = rtw_read32_mask(rtwdev, REG_IQKB_END, BIT(12));
 423
 424			if (!(tx0_fail || tx0_finish)) {
 425				rtw_write32(rtwdev, REG_RFECTL_A, 0x02000000);
 426				tx_x0_temp[tx0_avg] = rtw_read32_mask(rtwdev,
 427								      REG_IQKA_END,
 428								      0x07ff0000);
 429				rtw_write32(rtwdev, REG_RFECTL_A, 0x04000000);
 430				tx_y0_temp[tx0_avg] = rtw_read32_mask(rtwdev,
 431								      REG_IQKA_END,
 432								      0x07ff0000);
 433
 434				rtw_dbg(rtwdev, RTW_DBG_RFK,
 435					"tx_x0[%d] = %x ;; tx_y0[%d] = %x\n",
 436					tx0_avg, tx_x0_temp[tx0_avg],
 437					tx0_avg, tx_y0_temp[tx0_avg]);
 438
 439				tx_x0_temp[tx0_avg] <<= 21;
 440				tx_y0_temp[tx0_avg] <<= 21;
 441
 442				tx0_avg++;
 443			} else {
 444				cal0_retry++;
 445				if (cal0_retry == 10)
 446					break;
 447			}
 448
 449			if (!(tx1_fail || tx1_finish)) {
 450				rtw_write32(rtwdev, REG_RFECTL_B, 0x02000000);
 451				tx_x1_temp[tx1_avg] = rtw_read32_mask(rtwdev,
 452								      REG_IQKB_END,
 453								      0x07ff0000);
 454				rtw_write32(rtwdev, REG_RFECTL_B, 0x04000000);
 455				tx_y1_temp[tx1_avg] = rtw_read32_mask(rtwdev,
 456								      REG_IQKB_END,
 457								      0x07ff0000);
 458
 459				rtw_dbg(rtwdev, RTW_DBG_RFK,
 460					"tx_x1[%d] = %x ;; tx_y1[%d] = %x\n",
 461					tx1_avg, tx_x1_temp[tx1_avg],
 462					tx1_avg, tx_y1_temp[tx1_avg]);
 463
 464				tx_x1_temp[tx1_avg] <<= 21;
 465				tx_y1_temp[tx1_avg] <<= 21;
 466
 467				tx1_avg++;
 468			} else {
 469				cal1_retry++;
 470				if (cal1_retry == 10)
 471					break;
 472			}
 473		} else {
 474			cal0_retry++;
 475			cal1_retry++;
 476
 477			rtw_dbg(rtwdev, RTW_DBG_RFK,
 478				"delay 20ms TX IQK Not Ready!!!!!\n");
 479
 480			if (cal0_retry == 10)
 481				break;
 482		}
 483
 484		if (tx0_avg >= 2)
 485			tx0_finish = rtw88xxa_iqk_finish(tx0_avg, 4,
 486							 tx_x0_temp, tx_y0_temp, &tx_x0, &tx_y0,
 487							 false, false);
 488
 489		if (tx1_avg >= 2)
 490			tx1_finish = rtw88xxa_iqk_finish(tx1_avg, 4,
 491							 tx_x1_temp, tx_y1_temp, &tx_x1, &tx_y1,
 492							 false, false);
 493
 494		rtw_dbg(rtwdev, RTW_DBG_RFK,
 495			"tx0_average = %d, tx1_average = %d\n",
 496			tx0_avg, tx1_avg);
 497		rtw_dbg(rtwdev, RTW_DBG_RFK,
 498			"tx0_finish = %d, tx1_finish = %d\n",
 499			tx0_finish, tx1_finish);
 500
 501		if (tx0_finish && tx1_finish)
 502			break;
 503
 504		if ((cal0_retry + tx0_avg) >= 10 ||
 505		    (cal1_retry + tx1_avg) >= 10)
 506			break;
 507	}
 508
 509	rtw_dbg(rtwdev, RTW_DBG_RFK, "TXA_cal_retry = %d\n", cal0_retry);
 510	rtw_dbg(rtwdev, RTW_DBG_RFK, "TXB_cal_retry = %d\n", cal1_retry);
 511
 512	/* [31] = 0 --> Page C */
 513	rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
 514	/* Load LOK */
 515	rtw_write_rf(rtwdev, RF_PATH_A, RF_TXMOD, 0x7fe00,
 516		     rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, 0xffc00));
 517	rtw_write_rf(rtwdev, RF_PATH_B, RF_TXMOD, 0x7fe00,
 518		     rtw_read_rf(rtwdev, RF_PATH_B, RF_DTXLOK, 0xffc00));
 519	/* [31] = 1 --> Page C1 */
 520	rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x1);
 521
 522	/* [31] = 0 --> Page C */
 523	rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
 524	if (tx0_finish) {
 525		/* ====== path A RX IQK RF setting====== */
 526		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000);
 527		rtw_write_rf(rtwdev, RF_PATH_A, RF_MODE_TABLE_ADDR, RFREG_MASK,
 528			     0x30000);
 529		rtw_write_rf(rtwdev, RF_PATH_A, RF_MODE_TABLE_DATA0, RFREG_MASK,
 530			     0x3f7ff);
 531		rtw_write_rf(rtwdev, RF_PATH_A, RF_MODE_TABLE_DATA1, RFREG_MASK,
 532			     0xfe7bf);
 533		rtw_write_rf(rtwdev, RF_PATH_A, RF_RXBB2, RFREG_MASK, 0x88001);
 534		rtw_write_rf(rtwdev, RF_PATH_A, RF_TXA_PREPAD, RFREG_MASK, 0x931d1);
 535		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000);
 536	}
 537	if (tx1_finish) {
 538		/* ====== path B RX IQK RF setting====== */
 539		rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE, RFREG_MASK, 0x80000);
 540		rtw_write_rf(rtwdev, RF_PATH_B, RF_MODE_TABLE_ADDR, RFREG_MASK,
 541			     0x30000);
 542		rtw_write_rf(rtwdev, RF_PATH_B, RF_MODE_TABLE_DATA0, RFREG_MASK,
 543			     0x3f7ff);
 544		rtw_write_rf(rtwdev, RF_PATH_B, RF_MODE_TABLE_DATA1, RFREG_MASK,
 545			     0xfe7bf);
 546		rtw_write_rf(rtwdev, RF_PATH_B, RF_RXBB2, RFREG_MASK, 0x88001);
 547		rtw_write_rf(rtwdev, RF_PATH_B, RF_TXA_PREPAD, RFREG_MASK, 0x931d1);
 548		rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE, RFREG_MASK, 0x00000);
 549	}
 550
 551	rtw_write32_mask(rtwdev, REG_IQK_COM00, BIT(31), 0x1);
 552	rtw_write32_mask(rtwdev, REG_IQK_COM00, BIT(31), 0x0);
 553	rtw_write32(rtwdev, REG_DAC_RSTB, 0x00008000);
 554
 555	if (rtwdev->hci.type == RTW_HCI_TYPE_PCIE)
 556		rtw_write32(rtwdev, REG_IQK_COM96, 0x0046a911);
 557	else
 558		rtw_write32(rtwdev, REG_IQK_COM96, 0x0046a890);
 559
 560	if (efuse->rfe_option == 1) {
 561		rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777717);
 562		rtw_write32(rtwdev, REG_RFE_INV_A, 0x00000077);
 563		rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777717);
 564		rtw_write32(rtwdev, REG_RFE_INV_B, 0x00000077);
 565	} else {
 566		rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777717);
 567		rtw_write32(rtwdev, REG_RFE_INV_A, 0x02000077);
 568		rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777717);
 569		rtw_write32(rtwdev, REG_RFE_INV_B, 0x02000077);
 570	}
 571
 572	/* [31] = 1 --> Page C1 */
 573	rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x1);
 574
 575	if (tx0_finish) {
 576		/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
 577		rtw_write32(rtwdev, REG_OFDM0_XA_TX_IQ_IMBALANCE, 0x38008c10);
 578		/* RX_Tone_idx[9:0], RxK_Mask[29] */
 579		rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x18008c10);
 580		rtw_write32(rtwdev, REG_OFDM0_XB_TX_IQ_IMBALANCE, 0x82140119);
 581	}
 582	if (tx1_finish) {
 583		/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
 584		rtw_write32(rtwdev, REG_TXTONEB, 0x38008c10);
 585		/* RX_Tone_idx[9:0], RxK_Mask[29] */
 586		rtw_write32(rtwdev, REG_RXTONEB, 0x18008c10);
 587		rtw_write32(rtwdev, REG_TXPITMB, 0x82140119);
 588	}
 589
 590	cal0_retry = 0;
 591	cal1_retry = 0;
 592	while (1) {
 593		/* one shot */
 594		/* [31] = 0 --> Page C */
 595		rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
 596
 597		if (tx0_finish) {
 598			rtw_write32_mask(rtwdev, REG_IQK_COM00, 0x03FF8000,
 599					 tx_x0 & 0x000007ff);
 600			rtw_write32_mask(rtwdev, REG_IQK_COM00, 0x000007FF,
 601					 tx_y0 & 0x000007ff);
 602			/* [31] = 1 --> Page C1 */
 603			rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x1);
 604			if (efuse->rfe_option == 1)
 605				rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x28161500);
 606			else
 607				rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x28160cc0);
 608			rtw_write32(rtwdev, REG_RFECTL_A, 0x00300000);
 609			rtw_write32(rtwdev, REG_RFECTL_A, 0x00100000);
 610			mdelay(5);
 611			rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x3c000000);
 612			rtw_write32(rtwdev, REG_RFECTL_A, 0x00000000);
 613		}
 614
 615		if (tx1_finish) {
 616			/* [31] = 0 --> Page C */
 617			rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
 618			rtw_write32_mask(rtwdev, REG_IQK_COM00, 0x03FF8000,
 619					 tx_x1 & 0x000007ff);
 620			rtw_write32_mask(rtwdev, REG_IQK_COM00, 0x000007FF,
 621					 tx_y1 & 0x000007ff);
 622			/* [31] = 1 --> Page C1 */
 623			rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x1);
 624			if (efuse->rfe_option == 1)
 625				rtw_write32(rtwdev, REG_RXPITMB, 0x28161500);
 626			else
 627				rtw_write32(rtwdev, REG_RXPITMB, 0x28160ca0);
 628			rtw_write32(rtwdev, REG_RFECTL_B, 0x00300000);
 629			rtw_write32(rtwdev, REG_RFECTL_B, 0x00100000);
 630			mdelay(5);
 631			rtw_write32(rtwdev, REG_RXPITMB, 0x3c000000);
 632			rtw_write32(rtwdev, REG_RFECTL_B, 0x00000000);
 633		}
 634
 635		for (delay_count = 0; delay_count < 20; delay_count++) {
 636			if (!rx0_finish && tx0_finish)
 637				iqk0_ready = rtw_read32_mask(rtwdev,
 638							     REG_IQKA_END,
 639							     BIT(10));
 640			if (!rx1_finish && tx1_finish)
 641				iqk1_ready = rtw_read32_mask(rtwdev,
 642							     REG_IQKB_END,
 643							     BIT(10));
 644			if (iqk0_ready && iqk1_ready)
 645				break;
 646
 647			mdelay(1);
 648		}
 649
 650		rtw_dbg(rtwdev, RTW_DBG_RFK, "RX delay_count = %d\n",
 651			delay_count);
 652
 653		if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
 654			/* ============RXIQK Check============== */
 655			rx0_fail = rtw_read32_mask(rtwdev, REG_IQKA_END, BIT(11));
 656			rx1_fail = rtw_read32_mask(rtwdev, REG_IQKB_END, BIT(11));
 657
 658			if (!(rx0_fail || rx0_finish) && tx0_finish) {
 659				rtw_write32(rtwdev, REG_RFECTL_A, 0x06000000);
 660				rx_x0_temp[rx0_avg] = rtw_read32_mask(rtwdev,
 661								      REG_IQKA_END,
 662								      0x07ff0000);
 663				rtw_write32(rtwdev, REG_RFECTL_A, 0x08000000);
 664				rx_y0_temp[rx0_avg] = rtw_read32_mask(rtwdev,
 665								      REG_IQKA_END,
 666								      0x07ff0000);
 667
 668				rtw_dbg(rtwdev, RTW_DBG_RFK,
 669					"rx_x0[%d] = %x ;; rx_y0[%d] = %x\n",
 670					rx0_avg, rx_x0_temp[rx0_avg],
 671					rx0_avg, rx_y0_temp[rx0_avg]);
 672
 673				rx_x0_temp[rx0_avg] <<= 21;
 674				rx_y0_temp[rx0_avg] <<= 21;
 675
 676				rx0_avg++;
 677			} else {
 678				rtw_dbg(rtwdev, RTW_DBG_RFK,
 679					"1. RXA_cal_retry = %d\n", cal0_retry);
 680
 681				cal0_retry++;
 682				if (cal0_retry == 10)
 683					break;
 684			}
 685
 686			if (!(rx1_fail || rx1_finish) && tx1_finish) {
 687				rtw_write32(rtwdev, REG_RFECTL_B, 0x06000000);
 688				rx_x1_temp[rx1_avg] = rtw_read32_mask(rtwdev,
 689								      REG_IQKB_END,
 690								      0x07ff0000);
 691				rtw_write32(rtwdev, REG_RFECTL_B, 0x08000000);
 692				rx_y1_temp[rx1_avg] = rtw_read32_mask(rtwdev,
 693								      REG_IQKB_END,
 694								      0x07ff0000);
 695
 696				rtw_dbg(rtwdev, RTW_DBG_RFK,
 697					"rx_x1[%d] = %x ;; rx_y1[%d] = %x\n",
 698					rx1_avg, rx_x1_temp[rx1_avg],
 699					rx1_avg, rx_y1_temp[rx1_avg]);
 700
 701				rx_x1_temp[rx1_avg] <<= 21;
 702				rx_y1_temp[rx1_avg] <<= 21;
 703
 704				rx1_avg++;
 705			} else {
 706				cal1_retry++;
 707				if (cal1_retry == 10)
 708					break;
 709			}
 710		} else {
 711			rtw_dbg(rtwdev, RTW_DBG_RFK,
 712				"2. RXA_cal_retry = %d\n", cal0_retry);
 713
 714			cal0_retry++;
 715			cal1_retry++;
 716
 717			rtw_dbg(rtwdev, RTW_DBG_RFK,
 718				"delay 20ms RX IQK Not Ready!!!!!\n");
 719
 720			if (cal0_retry == 10)
 721				break;
 722		}
 723
 724		rtw_dbg(rtwdev, RTW_DBG_RFK, "3. RXA_cal_retry = %d\n",
 725			cal0_retry);
 726
 727		if (rx0_avg >= 2)
 728			rx0_finish = rtw88xxa_iqk_finish(rx0_avg, 4,
 729							 rx_x0_temp, rx_y0_temp,
 730							 &rx_x0, &rx_y0,
 731							 true, false);
 732
 733		if (rx1_avg >= 2)
 734			rx1_finish = rtw88xxa_iqk_finish(rx1_avg, 4,
 735							 rx_x1_temp, rx_y1_temp,
 736							 &rx_x1, &rx_y1,
 737							 true, false);
 738
 739		rtw_dbg(rtwdev, RTW_DBG_RFK,
 740			"rx0_average = %d, rx1_average = %d\n",
 741			rx0_avg, rx1_avg);
 742		rtw_dbg(rtwdev, RTW_DBG_RFK,
 743			"rx0_finish = %d, rx1_finish = %d\n",
 744			rx0_finish, rx1_finish);
 745
 746		if ((rx0_finish || !tx0_finish) && (rx1_finish || !tx1_finish))
 747			break;
 748
 749		if ((cal0_retry + rx0_avg) >= 10 ||
 750		    (cal1_retry + rx1_avg) >= 10 ||
 751		    rx0_avg == 3 || rx1_avg == 3)
 752			break;
 753	}
 754
 755	rtw_dbg(rtwdev, RTW_DBG_RFK, "RXA_cal_retry = %d\n", cal0_retry);
 756	rtw_dbg(rtwdev, RTW_DBG_RFK, "RXB_cal_retry = %d\n", cal1_retry);
 757
 758	/* FillIQK Result */
 759	rtw_dbg(rtwdev, RTW_DBG_RFK, "========Path_A =======\n");
 760
 761	if (tx0_finish)
 762		rtw8812a_iqk_tx_fill(rtwdev, RF_PATH_A, tx_x0, tx_y0);
 763	else
 764		rtw8812a_iqk_tx_fill(rtwdev, RF_PATH_A, 0x200, 0x0);
 765
 766	if (rx0_finish)
 767		rtw8812a_iqk_rx_fill(rtwdev, RF_PATH_A, rx_x0, rx_y0);
 768	else
 769		rtw8812a_iqk_rx_fill(rtwdev, RF_PATH_A, 0x200, 0x0);
 770
 771	rtw_dbg(rtwdev, RTW_DBG_RFK, "========Path_B =======\n");
 772
 773	if (tx1_finish)
 774		rtw8812a_iqk_tx_fill(rtwdev, RF_PATH_B, tx_x1, tx_y1);
 775	else
 776		rtw8812a_iqk_tx_fill(rtwdev, RF_PATH_B, 0x200, 0x0);
 777
 778	if (rx1_finish)
 779		rtw8812a_iqk_rx_fill(rtwdev, RF_PATH_B, rx_x1, rx_y1);
 780	else
 781		rtw8812a_iqk_rx_fill(rtwdev, RF_PATH_B, 0x200, 0x0);
 782}
 783
 784#define MACBB_REG_NUM_8812A 9
 785#define AFE_REG_NUM_8812A 12
 786#define RF_REG_NUM_8812A 3
 787
 788static void rtw8812a_do_iqk(struct rtw_dev *rtwdev)
 789{
 790	static const u32 backup_macbb_reg[MACBB_REG_NUM_8812A] = {
 791		0x520, 0x550, 0x808, 0xa04, 0x90c, 0xc00, 0xe00, 0x838, 0x82c
 792	};
 793	static const u32 backup_afe_reg[AFE_REG_NUM_8812A] = {
 794		0xc5c, 0xc60, 0xc64, 0xc68, 0xcb0, 0xcb4,
 795		0xe5c, 0xe60, 0xe64, 0xe68, 0xeb0, 0xeb4
 796	};
 797	static const u32 backup_rf_reg[RF_REG_NUM_8812A] = {
 798		0x65, 0x8f, 0x0
 799	};
 800	u32 macbb_backup[MACBB_REG_NUM_8812A] = {};
 801	u32 afe_backup[AFE_REG_NUM_8812A] = {};
 802	u32 rfa_backup[RF_REG_NUM_8812A] = {};
 803	u32 rfb_backup[RF_REG_NUM_8812A] = {};
 804	u32 reg_cb8, reg_eb8;
 805
 806	rtw88xxa_iqk_backup_mac_bb(rtwdev, macbb_backup,
 807				   backup_macbb_reg, MACBB_REG_NUM_8812A);
 808
 809	rtw_write32_set(rtwdev, REG_CCASEL, BIT(31));
 810	reg_cb8 = rtw_read32(rtwdev, REG_RFECTL_A);
 811	reg_eb8 = rtw_read32(rtwdev, REG_RFECTL_B);
 812	rtw_write32_clr(rtwdev, REG_CCASEL, BIT(31));
 813
 814	rtw88xxa_iqk_backup_afe(rtwdev, afe_backup,
 815				backup_afe_reg, AFE_REG_NUM_8812A);
 816	rtw8812a_iqk_backup_rf(rtwdev, rfa_backup, rfb_backup,
 817			       backup_rf_reg, RF_REG_NUM_8812A);
 818
 819	rtw88xxa_iqk_configure_mac(rtwdev);
 820
 821	rtw8812a_iqk(rtwdev);
 822
 823	rtw8812a_iqk_restore_rf(rtwdev, RF_PATH_A, backup_rf_reg,
 824				rfa_backup, RF_REG_NUM_8812A);
 825	rtw8812a_iqk_restore_rf(rtwdev, RF_PATH_B, backup_rf_reg,
 826				rfb_backup, RF_REG_NUM_8812A);
 827
 828	rtw8812a_iqk_restore_afe(rtwdev, afe_backup,
 829				 backup_afe_reg, AFE_REG_NUM_8812A);
 830
 831	rtw_write32_set(rtwdev, REG_CCASEL, BIT(31));
 832	rtw_write32(rtwdev, REG_RFECTL_A, reg_cb8);
 833	rtw_write32(rtwdev, REG_RFECTL_B, reg_eb8);
 834	rtw_write32_clr(rtwdev, REG_CCASEL, BIT(31));
 835
 836	rtw88xxa_iqk_restore_mac_bb(rtwdev, macbb_backup,
 837				    backup_macbb_reg, MACBB_REG_NUM_8812A);
 838}
 839
 840static void rtw8812a_phy_calibration(struct rtw_dev *rtwdev)
 841{
 842	u8 channel = rtwdev->hal.current_channel;
 843
 844	rtw8812a_do_iqk(rtwdev);
 845
 846	/* The official driver wants to do this after connecting
 847	 * but before first writing a new igi (phydm_get_new_igi).
 848	 * Here seems close enough.
 849	 */
 850	if (channel >= 36 && channel <= 64)
 851		rtw_load_table(rtwdev, &rtw8812a_agc_diff_lb_tbl);
 852	else if (channel >= 100)
 853		rtw_load_table(rtwdev, &rtw8812a_agc_diff_hb_tbl);
 854}
 855
 856static void rtw8812a_pwr_track(struct rtw_dev *rtwdev)
 857{
 858	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
 859
 860	if (!dm_info->pwr_trk_triggered) {
 861		rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER,
 862			     GENMASK(17, 16), 0x03);
 863		dm_info->pwr_trk_triggered = true;
 864		return;
 865	}
 866
 867	rtw88xxa_phy_pwrtrack(rtwdev, rtw8812a_do_lck, rtw8812a_do_iqk);
 868	dm_info->pwr_trk_triggered = false;
 869}
 870
 871static void rtw8812a_led_set(struct led_classdev *led,
 872			     enum led_brightness brightness)
 873{
 874	struct rtw_dev *rtwdev = container_of(led, struct rtw_dev, led_cdev);
 875	u8 ledcfg;
 876
 877	ledcfg = rtw_read8(rtwdev, REG_LED_CFG);
 878	ledcfg &= BIT(6) | BIT(4);
 879	ledcfg |= BIT(5);
 880
 881	if (brightness == LED_OFF)
 882		ledcfg |= BIT(3);
 883
 884	rtw_write8(rtwdev, REG_LED_CFG, ledcfg);
 885}
 886
 887static void rtw8812a_fill_txdesc_checksum(struct rtw_dev *rtwdev,
 888					  struct rtw_tx_pkt_info *pkt_info,
 889					  u8 *txdesc)
 890{
 891	fill_txdesc_checksum_common(txdesc, 16);
 892}
 893
 894static void rtw8812a_coex_cfg_init(struct rtw_dev *rtwdev)
 895{
 896}
 897
 898static void rtw8812a_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
 899{
 900}
 901
 902static void rtw8821a_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
 903{
 904}
 905
 906static void rtw8821a_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
 907{
 908}
 909
 910static void rtw8821a_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
 911{
 912}
 913
 914static const struct rtw_chip_ops rtw8812a_ops = {
 915	.power_on		= rtw88xxa_power_on,
 916	.power_off		= rtw8812a_power_off,
 917	.phy_set_param		= NULL,
 918	.read_efuse		= rtw88xxa_read_efuse,
 919	.query_phy_status	= rtw8812a_query_phy_status,
 920	.set_channel		= rtw88xxa_set_channel,
 921	.mac_init		= NULL,
 922	.mac_postinit		= NULL,
 923	.read_rf		= rtw88xxa_phy_read_rf,
 924	.write_rf		= rtw_phy_write_rf_reg_sipi,
 925	.set_antenna		= NULL,
 926	.set_tx_power_index	= rtw88xxa_set_tx_power_index,
 927	.cfg_ldo25		= rtw8812a_cfg_ldo25,
 928	.efuse_grant		= rtw88xxa_efuse_grant,
 929	.set_ampdu_factor	= NULL,
 930	.false_alarm_statistics	= rtw88xxa_false_alarm_statistics,
 931	.phy_calibration	= rtw8812a_phy_calibration,
 932	.cck_pd_set		= rtw88xxa_phy_cck_pd_set,
 933	.pwr_track		= rtw8812a_pwr_track,
 934	.config_bfee		= NULL,
 935	.set_gid_table		= NULL,
 936	.cfg_csi_rate		= NULL,
 937	.led_set		= rtw8812a_led_set,
 938	.fill_txdesc_checksum	= rtw8812a_fill_txdesc_checksum,
 939	.coex_set_init		= rtw8812a_coex_cfg_init,
 940	.coex_set_ant_switch	= NULL,
 941	.coex_set_gnt_fix	= rtw8812a_coex_cfg_gnt_fix,
 942	.coex_set_gnt_debug	= NULL,
 943	.coex_set_rfe_type	= rtw8821a_coex_cfg_rfe_type,
 944	.coex_set_wl_tx_power	= rtw8821a_coex_cfg_wl_tx_power,
 945	.coex_set_wl_rx_gain	= rtw8821a_coex_cfg_wl_rx_gain,
 946};
 947
 948static const struct rtw_page_table page_table_8812a[] = {
 949	/* hq_num, nq_num, lq_num, exq_num, gapq_num */
 950	{0, 0, 0, 0, 0},	/* SDIO */
 951	{0, 0, 0, 0, 0},	/* PCI */
 952	{16, 0, 0, 0, 1},	/* 2 bulk out endpoints */
 953	{16, 0, 16, 0, 1},	/* 3 bulk out endpoints */
 954	{16, 0, 16, 0, 1},	/* 4 bulk out endpoints */
 955};
 956
 957static const struct rtw_rqpn rqpn_table_8812a[] = {
 958	{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
 959	 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
 960	 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
 961
 962	{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
 963	 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
 964	 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
 965
 966	{RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH,
 967	 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
 968	 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
 969
 970	{RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_NORMAL,
 971	 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
 972	 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
 973
 974	{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
 975	 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
 976	 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
 977};
 978
 979static const struct rtw_prioq_addrs prioq_addrs_8812a = {
 980	.prio[RTW_DMA_MAPPING_EXTRA] = {
 981		.rsvd = REG_RQPN_NPQ + 2, .avail = REG_RQPN_NPQ + 3,
 982	},
 983	.prio[RTW_DMA_MAPPING_LOW] = {
 984		.rsvd = REG_RQPN + 1, .avail = REG_FIFOPAGE_CTRL_2 + 1,
 985	},
 986	.prio[RTW_DMA_MAPPING_NORMAL] = {
 987		.rsvd = REG_RQPN_NPQ, .avail = REG_RQPN_NPQ + 1,
 988	},
 989	.prio[RTW_DMA_MAPPING_HIGH] = {
 990		.rsvd = REG_RQPN, .avail = REG_FIFOPAGE_CTRL_2,
 991	},
 992	.wsize = false,
 993};
 994
 995static const struct rtw_hw_reg rtw8812a_dig[] = {
 996	[0] = { .addr = REG_RXIGI_A, .mask = 0x7f },
 997	[1] = { .addr = REG_RXIGI_B, .mask = 0x7f },
 998};
 999
1000static const struct rtw_rfe_def rtw8812a_rfe_defs[] = {
1001	[0] = { .phy_pg_tbl	= &rtw8812a_bb_pg_tbl,
1002		.txpwr_lmt_tbl	= &rtw8812a_txpwr_lmt_tbl,
1003		.pwr_track_tbl	= &rtw8812a_rtw_pwr_track_tbl, },
1004	[1] = { .phy_pg_tbl	= &rtw8812a_bb_pg_tbl,
1005		.txpwr_lmt_tbl	= &rtw8812a_txpwr_lmt_tbl,
1006		.pwr_track_tbl	= &rtw8812a_rtw_pwr_track_tbl, },
1007	[2] = { .phy_pg_tbl	= &rtw8812a_bb_pg_tbl,
1008		.txpwr_lmt_tbl	= &rtw8812a_txpwr_lmt_tbl,
1009		.pwr_track_tbl	= &rtw8812a_rtw_pwr_track_tbl, },
1010	[3] = { .phy_pg_tbl	= &rtw8812a_bb_pg_rfe3_tbl,
1011		.txpwr_lmt_tbl	= &rtw8812a_txpwr_lmt_tbl,
1012		.pwr_track_tbl	= &rtw8812a_rtw_pwr_track_rfe3_tbl, },
1013};
1014
1015static const u8 wl_rssi_step_8812a[] = {101, 45, 101, 40};
1016static const u8 bt_rssi_step_8812a[] = {101, 101, 101, 101};
1017
1018static const struct coex_rf_para rf_para_tx_8812a[] = {
1019	{0, 0, false, 7},  /* for normal */
1020	{0, 20, false, 7}, /* for WL-CPT */
1021	{8, 17, true, 4},
1022	{7, 18, true, 4},
1023	{6, 19, true, 4},
1024	{5, 20, true, 4}
1025};
1026
1027static const struct coex_rf_para rf_para_rx_8812a[] = {
1028	{0, 0, false, 7},  /* for normal */
1029	{0, 20, false, 7}, /* for WL-CPT */
1030	{3, 24, true, 5},
1031	{2, 26, true, 5},
1032	{1, 27, true, 5},
1033	{0, 28, true, 5}
1034};
1035
1036static_assert(ARRAY_SIZE(rf_para_tx_8812a) == ARRAY_SIZE(rf_para_rx_8812a));
1037
1038const struct rtw_chip_info rtw8812a_hw_spec = {
1039	.ops = &rtw8812a_ops,
1040	.id = RTW_CHIP_TYPE_8812A,
1041	.fw_name = "rtw88/rtw8812a_fw.bin",
1042	.wlan_cpu = RTW_WCPU_8051,
1043	.tx_pkt_desc_sz = 40,
1044	.tx_buf_desc_sz = 16,
1045	.rx_pkt_desc_sz = 24,
1046	.rx_buf_desc_sz = 8,
1047	.phy_efuse_size = 512,
1048	.log_efuse_size = 512,
1049	.ptct_efuse_size = 0,
1050	.txff_size = 131072,
1051	.rxff_size = 16128,
1052	.rsvd_drv_pg_num = 9,
1053	.txgi_factor = 1,
1054	.is_pwr_by_rate_dec = true,
1055	.max_power_index = 0x3f,
1056	.csi_buf_pg_num = 0,
1057	.band = RTW_BAND_2G | RTW_BAND_5G,
1058	.page_size = 512,
1059	.dig_min = 0x20,
1060	.ht_supported = true,
1061	.vht_supported = true,
1062	.lps_deep_mode_supported = 0,
1063	.sys_func_en = 0xFD,
1064	.pwr_on_seq = card_enable_flow_8812a,
1065	.pwr_off_seq = card_disable_flow_8812a,
1066	.page_table = page_table_8812a,
1067	.rqpn_table = rqpn_table_8812a,
1068	.prioq_addrs = &prioq_addrs_8812a,
1069	.intf_table = NULL,
1070	.dig = rtw8812a_dig,
1071	.rf_sipi_addr = {REG_LSSI_WRITE_A, REG_LSSI_WRITE_B},
1072	.ltecoex_addr = NULL,
1073	.mac_tbl = &rtw8812a_mac_tbl,
1074	.agc_tbl = &rtw8812a_agc_tbl,
1075	.bb_tbl = &rtw8812a_bb_tbl,
1076	.rf_tbl = {&rtw8812a_rf_a_tbl, &rtw8812a_rf_b_tbl},
1077	.rfe_defs = rtw8812a_rfe_defs,
1078	.rfe_defs_size = ARRAY_SIZE(rtw8812a_rfe_defs),
1079	.rx_ldpc = false,
1080	.amsdu_in_ampdu = true,
1081	.hw_feature_report = false,
1082	.c2h_ra_report_size = 4,
1083	.old_datarate_fb_limit = true,
1084	.usb_tx_agg_desc_num = 1,
1085	.iqk_threshold = 8,
1086	.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1087	.max_scan_ie_len = IEEE80211_MAX_DATA_LEN,
1088
1089	.coex_para_ver = 0, /* no coex code in 8812au driver */
1090	.bt_desired_ver = 0,
1091	.scbd_support = false,
1092	.new_scbd10_def = false,
1093	.ble_hid_profile_support = false,
1094	.wl_mimo_ps_support = false,
1095	.pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
1096	.bt_rssi_type = COEX_BTRSSI_RATIO,
1097	.ant_isolation = 15,
1098	.rssi_tolerance = 2,
1099	.wl_rssi_step = wl_rssi_step_8812a,
1100	.bt_rssi_step = bt_rssi_step_8812a,
1101	.table_sant_num = 0,
1102	.table_sant = NULL,
1103	.table_nsant_num = 0,
1104	.table_nsant = NULL,
1105	.tdma_sant_num = 0,
1106	.tdma_sant = NULL,
1107	.tdma_nsant_num = 0,
1108	.tdma_nsant = NULL,
1109	.wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8812a),
1110	.wl_rf_para_tx = rf_para_tx_8812a,
1111	.wl_rf_para_rx = rf_para_rx_8812a,
1112	.bt_afh_span_bw20 = 0x20,
1113	.bt_afh_span_bw40 = 0x30,
1114	.afh_5g_num = 0,
1115	.afh_5g = NULL,
1116	.coex_info_hw_regs_num = 0,
1117	.coex_info_hw_regs = NULL,
1118};
1119EXPORT_SYMBOL(rtw8812a_hw_spec);
1120
1121MODULE_FIRMWARE("rtw88/rtw8812a_fw.bin");
1122
1123MODULE_AUTHOR("Realtek Corporation");
1124MODULE_DESCRIPTION("Realtek 802.11ac wireless 8812a driver");
1125MODULE_LICENSE("Dual BSD/GPL");