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rtw8723d.c
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linux-6.19.14/drivers/net/wireless/realtek/rtw88/rtw8723d.c
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5#include <linux/module.h> 6#include "main.h" 7#include "coex.h" 8#include "fw.h" 9#include "tx.h" 10#include "rx.h" 11#include "phy.h" 12#include "rtw8723x.h" 13#include "rtw8723d.h" 14#include "rtw8723d_table.h" 15#include "mac.h" 16#include "reg.h" 17#include "debug.h" 18 19#define WLAN_SLOT_TIME 0x09 20#define WLAN_RL_VAL 0x3030 21#define WLAN_BAR_VAL 0x0201ffff 22#define BIT_MASK_TBTT_HOLD 0x00000fff 23#define BIT_SHIFT_TBTT_HOLD 8 24#define BIT_MASK_TBTT_SETUP 0x000000ff 25#define BIT_SHIFT_TBTT_SETUP 0 26#define BIT_MASK_TBTT_MASK ((BIT_MASK_TBTT_HOLD << BIT_SHIFT_TBTT_HOLD) | \ 27 (BIT_MASK_TBTT_SETUP << BIT_SHIFT_TBTT_SETUP)) 28#define TBTT_TIME(s, h)((((s) & BIT_MASK_TBTT_SETUP) << BIT_SHIFT_TBTT_SETUP) |\ 29 (((h) & BIT_MASK_TBTT_HOLD) << BIT_SHIFT_TBTT_HOLD)) 30#define WLAN_TBTT_TIME_NORMAL TBTT_TIME(0x04, 0x80) 31#define WLAN_TBTT_TIME_STOP_BCN TBTT_TIME(0x04, 0x64) 32#define WLAN_PIFS_VAL 0 33#define WLAN_AGG_BRK_TIME 0x16 34#define WLAN_NAV_PROT_LEN 0x0040 35#define WLAN_SPEC_SIFS 0x100a 36#define WLAN_RX_PKT_LIMIT 0x17 37#define WLAN_MAX_AGG_NR 0x0A 38#define WLAN_AMPDU_MAX_TIME 0x1C 39#define WLAN_ANT_SEL 0x82 40#define WLAN_LTR_IDLE_LAT 0x90039003 41#define WLAN_LTR_ACT_LAT 0x883c883c 42#define WLAN_LTR_CTRL1 0xCB004010 43#define WLAN_LTR_CTRL2 0x01233425 44 45static const u32 rtw8723d_ofdm_swing_table[] = { 46 0x0b40002d, 0x0c000030, 0x0cc00033, 0x0d800036, 0x0e400039, 0x0f00003c, 47 0x10000040, 0x11000044, 0x12000048, 0x1300004c, 0x14400051, 0x15800056, 48 0x16c0005b, 0x18000060, 0x19800066, 0x1b00006c, 0x1c800072, 0x1e400079, 49 0x20000080, 0x22000088, 0x24000090, 0x26000098, 0x288000a2, 0x2ac000ab, 50 0x2d4000b5, 0x300000c0, 0x32c000cb, 0x35c000d7, 0x390000e4, 0x3c8000f2, 51 0x40000100, 0x43c0010f, 0x47c0011f, 0x4c000130, 0x50800142, 0x55400155, 52 0x5a400169, 0x5fc0017f, 0x65400195, 0x6b8001ae, 0x71c001c7, 0x788001e2, 53 0x7f8001fe, 54}; 55 56static const u32 rtw8723d_cck_swing_table[] = { 57 0x0CD, 0x0D9, 0x0E6, 0x0F3, 0x102, 0x111, 0x121, 0x132, 0x144, 0x158, 58 0x16C, 0x182, 0x198, 0x1B1, 0x1CA, 0x1E5, 0x202, 0x221, 0x241, 0x263, 59 0x287, 0x2AE, 0x2D6, 0x301, 0x32F, 0x35F, 0x392, 0x3C9, 0x402, 0x43F, 60 0x47F, 0x4C3, 0x50C, 0x558, 0x5A9, 0x5FF, 0x65A, 0x6BA, 0x720, 0x78C, 61 0x7FF, 62}; 63 64#define RTW_OFDM_SWING_TABLE_SIZE ARRAY_SIZE(rtw8723d_ofdm_swing_table) 65#define RTW_CCK_SWING_TABLE_SIZE ARRAY_SIZE(rtw8723d_cck_swing_table) 66 67static void rtw8723d_pwrtrack_init(struct rtw_dev *rtwdev) 68{ 69 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 70 u8 path; 71 72 dm_info->default_ofdm_index = RTW_DEF_OFDM_SWING_INDEX; 73 74 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { 75 ewma_thermal_init(&dm_info->avg_thermal[path]); 76 dm_info->delta_power_index[path] = 0; 77 } 78 dm_info->pwr_trk_triggered = false; 79 dm_info->pwr_trk_init_trigger = true; 80 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 81 dm_info->txagc_remnant_cck = 0; 82 dm_info->txagc_remnant_ofdm[RF_PATH_A] = 0; 83} 84 85static void rtw8723d_phy_set_param(struct rtw_dev *rtwdev) 86{ 87 u8 xtal_cap; 88 u32 val32; 89 90 /* power on BB/RF domain */ 91 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, 92 BIT_FEN_EN_25_1 | BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 93 rtw_write8_set(rtwdev, REG_RF_CTRL, 94 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 95 rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80); 96 97 rtw_phy_load_tables(rtwdev); 98 99 /* post init after header files config */ 100 rtw_write32_clr(rtwdev, REG_RCR, BIT_RCR_ADF); 101 rtw_write8_set(rtwdev, REG_HIQ_NO_LMT_EN, BIT_HIQ_NO_LMT_EN_ROOT); 102 rtw_write16_set(rtwdev, REG_AFE_CTRL_4, BIT_CK320M_AFE_EN | BIT_EN_SYN); 103 104 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; 105 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, 106 xtal_cap | (xtal_cap << 6)); 107 rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN); 108 if ((rtwdev->efuse.afe >> 4) == 14) { 109 rtw_write32_set(rtwdev, REG_AFE_CTRL3, BIT_XTAL_GMP_BIT4); 110 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BITS_PLL); 111 rtw_write32_set(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA1); 112 rtw_write32_clr(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA0); 113 } 114 115 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 116 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 117 rtw_write16(rtwdev, REG_RETRY_LIMIT, WLAN_RL_VAL); 118 rtw_write32(rtwdev, REG_BAR_MODE_CTRL, WLAN_BAR_VAL); 119 rtw_write8(rtwdev, REG_ATIMWND, 0x2); 120 rtw_write8(rtwdev, REG_BCN_CTRL, 121 BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION | BIT_EN_TXBCN_RPT); 122 val32 = rtw_read32(rtwdev, REG_TBTT_PROHIBIT); 123 val32 &= ~BIT_MASK_TBTT_MASK; 124 val32 |= WLAN_TBTT_TIME_STOP_BCN; 125 rtw_write8(rtwdev, REG_TBTT_PROHIBIT, val32); 126 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_VAL); 127 rtw_write8(rtwdev, REG_AGGR_BREAK_TIME, WLAN_AGG_BRK_TIME); 128 rtw_write16(rtwdev, REG_NAV_PROT_LEN, WLAN_NAV_PROT_LEN); 129 rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, WLAN_SPEC_SIFS); 130 rtw_write16(rtwdev, REG_SIFS, WLAN_SPEC_SIFS); 131 rtw_write16(rtwdev, REG_SIFS + 2, WLAN_SPEC_SIFS); 132 rtw_write8(rtwdev, REG_SINGLE_AMPDU_CTRL, BIT_EN_SINGLE_APMDU); 133 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RX_PKT_LIMIT); 134 rtw_write8(rtwdev, REG_MAX_AGGR_NUM, WLAN_MAX_AGG_NR); 135 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, WLAN_AMPDU_MAX_TIME); 136 rtw_write8(rtwdev, REG_LEDCFG2, WLAN_ANT_SEL); 137 138 rtw_write32(rtwdev, REG_LTR_IDLE_LATENCY, WLAN_LTR_IDLE_LAT); 139 rtw_write32(rtwdev, REG_LTR_ACTIVE_LATENCY, WLAN_LTR_ACT_LAT); 140 rtw_write32(rtwdev, REG_LTR_CTRL_BASIC, WLAN_LTR_CTRL1); 141 rtw_write32(rtwdev, REG_LTR_CTRL_BASIC + 4, WLAN_LTR_CTRL2); 142 143 rtw_phy_init(rtwdev); 144 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; 145 146 rtw_write16_set(rtwdev, REG_TXDMA_OFFSET_CHK, BIT_DROP_DATA_EN); 147 148 rtw8723x_lck(rtwdev); 149 150 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); 151 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20); 152 153 rtw8723d_pwrtrack_init(rtwdev); 154} 155 156static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 157 struct rtw_rx_pkt_stat *pkt_stat) 158{ 159 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 160 s8 min_rx_power = -120; 161 u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status); 162 163 pkt_stat->rx_power[RF_PATH_A] = pwdb - 97; 164 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 165 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 166 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 167 min_rx_power); 168 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 169} 170 171static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 172 struct rtw_rx_pkt_stat *pkt_stat) 173{ 174 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 175 u8 rxsc, bw; 176 s8 min_rx_power = -120; 177 s8 rx_evm; 178 179 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 180 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 181 else 182 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 183 184 if (GET_PHY_STAT_P1_RF_MODE(phy_status) == 0) 185 bw = RTW_CHANNEL_WIDTH_20; 186 else if ((rxsc == 1) || (rxsc == 2)) 187 bw = RTW_CHANNEL_WIDTH_20; 188 else 189 bw = RTW_CHANNEL_WIDTH_40; 190 191 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 192 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 193 pkt_stat->bw = bw; 194 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 195 min_rx_power); 196 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status); 197 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status); 198 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status); 199 200 dm_info->curr_rx_rate = pkt_stat->rate; 201 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 202 dm_info->rx_snr[RF_PATH_A] = pkt_stat->rx_snr[RF_PATH_A] >> 1; 203 dm_info->cfo_tail[RF_PATH_A] = (pkt_stat->cfo_tail[RF_PATH_A] * 5) >> 1; 204 205 rx_evm = clamp_t(s8, -pkt_stat->rx_evm[RF_PATH_A] >> 1, 0, 64); 206 rx_evm &= 0x3F; /* 64->0: second path of 1SS rate is 64 */ 207 dm_info->rx_evm_dbm[RF_PATH_A] = rx_evm; 208} 209 210static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 211 struct rtw_rx_pkt_stat *pkt_stat) 212{ 213 u8 page; 214 215 page = *phy_status & 0xf; 216 217 switch (page) { 218 case 0: 219 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 220 break; 221 case 1: 222 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 223 break; 224 default: 225 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 226 return; 227 } 228} 229 230static bool rtw8723d_check_spur_ov_thres(struct rtw_dev *rtwdev, 231 u8 channel, u32 thres) 232{ 233 u32 freq; 234 bool ret = false; 235 236 if (channel == 13) 237 freq = FREQ_CH13; 238 else if (channel == 14) 239 freq = FREQ_CH14; 240 else 241 return false; 242 243 rtw_write32(rtwdev, REG_ANALOG_P4, DIS_3WIRE); 244 rtw_write32(rtwdev, REG_PSDFN, freq); 245 rtw_write32(rtwdev, REG_PSDFN, START_PSD | freq); 246 247 msleep(30); 248 if (rtw_read32(rtwdev, REG_PSDRPT) >= thres) 249 ret = true; 250 251 rtw_write32(rtwdev, REG_PSDFN, freq); 252 rtw_write32(rtwdev, REG_ANALOG_P4, EN_3WIRE); 253 254 return ret; 255} 256 257static void rtw8723d_cfg_notch(struct rtw_dev *rtwdev, u8 channel, bool notch) 258{ 259 if (!notch) { 260 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f); 261 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); 262 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 263 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 264 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 265 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 266 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); 267 return; 268 } 269 270 switch (channel) { 271 case 13: 272 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb); 273 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 274 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x04000000); 275 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 276 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 277 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 278 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 279 break; 280 case 14: 281 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5); 282 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 283 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 284 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 285 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 286 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00080000); 287 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 288 break; 289 default: 290 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); 291 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); 292 break; 293 } 294} 295 296static void rtw8723d_spur_cal(struct rtw_dev *rtwdev, u8 channel) 297{ 298 bool notch; 299 300 if (channel < 13) { 301 rtw8723d_cfg_notch(rtwdev, channel, false); 302 return; 303 } 304 305 notch = rtw8723d_check_spur_ov_thres(rtwdev, channel, SPUR_THRES); 306 rtw8723d_cfg_notch(rtwdev, channel, notch); 307} 308 309static void rtw8723d_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 310{ 311 u32 rf_cfgch_a, rf_cfgch_b; 312 313 rf_cfgch_a = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); 314 rf_cfgch_b = rtw_read_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK); 315 316 rf_cfgch_a &= ~RFCFGCH_CHANNEL_MASK; 317 rf_cfgch_b &= ~RFCFGCH_CHANNEL_MASK; 318 rf_cfgch_a |= (channel & RFCFGCH_CHANNEL_MASK); 319 rf_cfgch_b |= (channel & RFCFGCH_CHANNEL_MASK); 320 321 rf_cfgch_a &= ~RFCFGCH_BW_MASK; 322 switch (bw) { 323 case RTW_CHANNEL_WIDTH_20: 324 rf_cfgch_a |= RFCFGCH_BW_20M; 325 break; 326 case RTW_CHANNEL_WIDTH_40: 327 rf_cfgch_a |= RFCFGCH_BW_40M; 328 break; 329 default: 330 break; 331 } 332 333 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_cfgch_a); 334 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_cfgch_b); 335 336 rtw8723d_spur_cal(rtwdev, channel); 337} 338 339static const struct rtw_backup_info cck_dfir_cfg[][CCK_DFIR_NR] = { 340 [0] = { 341 { .len = 4, .reg = 0xA24, .val = 0x64B80C1C }, 342 { .len = 4, .reg = 0xA28, .val = 0x00008810 }, 343 { .len = 4, .reg = 0xAAC, .val = 0x01235667 }, 344 }, 345 [1] = { 346 { .len = 4, .reg = 0xA24, .val = 0x0000B81C }, 347 { .len = 4, .reg = 0xA28, .val = 0x00000000 }, 348 { .len = 4, .reg = 0xAAC, .val = 0x00003667 }, 349 }, 350}; 351 352static void rtw8723d_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 353 u8 primary_ch_idx) 354{ 355 const struct rtw_backup_info *cck_dfir; 356 int i; 357 358 cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1]; 359 360 for (i = 0; i < CCK_DFIR_NR; i++, cck_dfir++) 361 rtw_write32(rtwdev, cck_dfir->reg, cck_dfir->val); 362 363 switch (bw) { 364 case RTW_CHANNEL_WIDTH_20: 365 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0); 366 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0); 367 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 1); 368 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_MASK_RXBB_DFIR, 0xa); 369 break; 370 case RTW_CHANNEL_WIDTH_40: 371 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1); 372 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1); 373 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 0); 374 rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND, 375 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0)); 376 break; 377 default: 378 break; 379 } 380} 381 382static void rtw8723d_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 383 u8 primary_chan_idx) 384{ 385 rtw8723d_set_channel_rf(rtwdev, channel, bw); 386 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 387 rtw8723d_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 388} 389 390static void rtw8723d_shutdown(struct rtw_dev *rtwdev) 391{ 392 rtw_write16_set(rtwdev, REG_HCI_OPT_CTRL, BIT_USB_SUS_DIS); 393} 394 395struct rtw_8723d_iqk_cfg { 396 const char *name; 397 u32 val_bb_sel_btg; 398 u32 reg_lutwe; 399 u32 val_txiqk_pi; 400 u32 reg_padlut; 401 u32 reg_gaintx; 402 u32 reg_bspad; 403 u32 val_wlint; 404 u32 val_wlsel; 405 u32 val_iqkpts; 406}; 407 408static const struct rtw_8723d_iqk_cfg iqk_tx_cfg[PATH_NR] = { 409 [PATH_S1] = { 410 .name = "S1", 411 .val_bb_sel_btg = 0x99000000, 412 .reg_lutwe = RF_LUTWE, 413 .val_txiqk_pi = 0x8214019f, 414 .reg_padlut = RF_LUTDBG, 415 .reg_gaintx = RF_GAINTX, 416 .reg_bspad = RF_BSPAD, 417 .val_wlint = 0xe0d, 418 .val_wlsel = 0x60d, 419 .val_iqkpts = 0xfa000000, 420 }, 421 [PATH_S0] = { 422 .name = "S0", 423 .val_bb_sel_btg = 0x99000280, 424 .reg_lutwe = RF_LUTWE2, 425 .val_txiqk_pi = 0x8214018a, 426 .reg_padlut = RF_TXADBG, 427 .reg_gaintx = RF_TRXIQ, 428 .reg_bspad = RF_TXATANK, 429 .val_wlint = 0xe6d, 430 .val_wlsel = 0x66d, 431 .val_iqkpts = 0xf9000000, 432 }, 433}; 434 435static u8 rtw8723d_iqk_check_tx_failed(struct rtw_dev *rtwdev, 436 const struct rtw_8723d_iqk_cfg *iqk_cfg) 437{ 438 s32 tx_x, tx_y; 439 u32 tx_fail; 440 441 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n", 442 rtw_read32(rtwdev, REG_IQK_RES_RY)); 443 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n", 444 rtw_read32(rtwdev, REG_IQK_RES_TX), 445 rtw_read32(rtwdev, REG_IQK_RES_TY)); 446 rtw_dbg(rtwdev, RTW_DBG_RFK, 447 "[IQK] 0xe90(before IQK)= 0x%x, 0xe98(after IQK) = 0x%x\n", 448 rtw_read32(rtwdev, 0xe90), 449 rtw_read32(rtwdev, 0xe98)); 450 451 tx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_TX_FAIL); 452 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 453 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 454 455 if (!tx_fail && tx_x != IQK_TX_X_ERR && tx_y != IQK_TX_Y_ERR) 456 return IQK_TX_OK; 457 458 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] %s TXIQK is failed\n", 459 iqk_cfg->name); 460 461 return 0; 462} 463 464static u8 rtw8723d_iqk_check_rx_failed(struct rtw_dev *rtwdev, 465 const struct rtw_8723d_iqk_cfg *iqk_cfg) 466{ 467 s32 rx_x, rx_y; 468 u32 rx_fail; 469 470 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n", 471 rtw_read32(rtwdev, REG_IQK_RES_RX), 472 rtw_read32(rtwdev, REG_IQK_RES_RY)); 473 474 rtw_dbg(rtwdev, RTW_DBG_RFK, 475 "[IQK] 0xea0(before IQK)= 0x%x, 0xea8(after IQK) = 0x%x\n", 476 rtw_read32(rtwdev, 0xea0), 477 rtw_read32(rtwdev, 0xea8)); 478 479 rx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_RX_FAIL); 480 rx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX); 481 rx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY); 482 rx_y = abs(iqkxy_to_s32(rx_y)); 483 484 if (!rx_fail && rx_x < IQK_RX_X_UPPER && rx_x > IQK_RX_X_LOWER && 485 rx_y < IQK_RX_Y_LMT) 486 return IQK_RX_OK; 487 488 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] %s RXIQK STEP2 is failed\n", 489 iqk_cfg->name); 490 491 return 0; 492} 493 494#define IQK_LTE_WRITE_VAL_8723D 0x0000ff00 495 496static void rtw8723d_iqk_one_shot(struct rtw_dev *rtwdev, bool tx, 497 const struct rtw_8723d_iqk_cfg *iqk_cfg) 498{ 499 u32 pts = (tx ? iqk_cfg->val_iqkpts : 0xf9000000); 500 501 /* enter IQK mode */ 502 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); 503 rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8723D); 504 505 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0054); 506 mdelay(1); 507 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] GNT_BT @%s %sIQK1 = 0x%x\n", 508 iqk_cfg->name, tx ? "TX" : "RX", 509 rtw_read32(rtwdev, REG_LTECOEX_READ_DATA)); 510 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x948 @%s %sIQK1 = 0x%x\n", 511 iqk_cfg->name, tx ? "TX" : "RX", 512 rtw_read32(rtwdev, REG_BB_SEL_BTG)); 513 514 /* One shot, LOK & IQK */ 515 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, pts); 516 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000); 517 518 if (!check_hw_ready(rtwdev, REG_IQK_RES_RY, BIT_IQK_DONE, 1)) 519 rtw_warn(rtwdev, "%s %s IQK isn't done\n", iqk_cfg->name, 520 tx ? "TX" : "RX"); 521} 522 523static void rtw8723d_iqk_txrx_path_post(struct rtw_dev *rtwdev, 524 const struct rtw_8723d_iqk_cfg *iqk_cfg, 525 const struct rtw8723x_iqk_backup_regs *backup) 526{ 527 rtw8723x_iqk_restore_lte_path_gnt(rtwdev, backup); 528 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup->bb_sel_btg); 529 530 /* leave IQK mode */ 531 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 532 mdelay(1); 533 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x0); 534 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, BIT(0), 0x0); 535 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, BIT(0), 0x0); 536} 537 538static u8 rtw8723d_iqk_tx_path(struct rtw_dev *rtwdev, 539 const struct rtw_8723d_iqk_cfg *iqk_cfg, 540 const struct rtw8723x_iqk_backup_regs *backup) 541{ 542 u8 status; 543 544 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s TXIQK!!\n", iqk_cfg->name); 545 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s TXIQK = 0x%x\n", 546 iqk_cfg->name, 547 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 548 549 rtw_write32(rtwdev, REG_BB_SEL_BTG, iqk_cfg->val_bb_sel_btg); 550 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 551 mdelay(1); 552 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000); 553 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00004); 554 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005d); 555 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xBFFE0); 556 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); 557 558 /* IQK setting */ 559 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x08008c0c); 560 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); 561 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, iqk_cfg->val_txiqk_pi); 562 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160200); 563 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); 564 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 565 566 /* LOK setting */ 567 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911); 568 569 /* PA, PAD setting */ 570 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1); 571 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0); 572 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x1E0, 0x3); 573 rtw_write_rf(rtwdev, RF_PATH_A, RF_RXIQGEN, 0x1F, 0xf); 574 575 /* LOK setting for 8723D */ 576 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x10, 0x1); 577 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_bspad, 0x1, 0x1); 578 579 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, iqk_cfg->val_wlint); 580 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK, iqk_cfg->val_wlsel); 581 582 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s TXIQK = 0x%x\n", 583 iqk_cfg->name, 584 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK)); 585 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s TXIQK = 0x%x\n", 586 iqk_cfg->name, 587 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK)); 588 589 rtw8723d_iqk_one_shot(rtwdev, true, iqk_cfg); 590 status = rtw8723d_iqk_check_tx_failed(rtwdev, iqk_cfg); 591 592 rtw8723d_iqk_txrx_path_post(rtwdev, iqk_cfg, backup); 593 594 return status; 595} 596 597static u8 rtw8723d_iqk_rx_path(struct rtw_dev *rtwdev, 598 const struct rtw_8723d_iqk_cfg *iqk_cfg, 599 const struct rtw8723x_iqk_backup_regs *backup) 600{ 601 u32 tx_x, tx_y; 602 u8 status; 603 604 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s RXIQK Step1!!\n", 605 iqk_cfg->name); 606 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK1 = 0x%x\n", 607 iqk_cfg->name, 608 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 609 rtw_write32(rtwdev, REG_BB_SEL_BTG, iqk_cfg->val_bb_sel_btg); 610 611 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 612 613 /* IQK setting */ 614 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); 615 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 616 617 /* path IQK setting */ 618 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c); 619 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); 620 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); 621 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); 622 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82160000); 623 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160000); 624 625 /* LOK setting */ 626 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911); 627 628 /* RXIQK mode */ 629 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000); 630 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00006); 631 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f); 632 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xa7ffb); 633 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); 634 635 /* PA/PAD=0 */ 636 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1); 637 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0); 638 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, iqk_cfg->val_wlint); 639 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK, iqk_cfg->val_wlsel); 640 641 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1@ path %s RXIQK1 = 0x%x\n", 642 iqk_cfg->name, 643 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK)); 644 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2@ path %s RXIQK1 = 0x%x\n", 645 iqk_cfg->name, 646 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK)); 647 648 rtw8723d_iqk_one_shot(rtwdev, false, iqk_cfg); 649 status = rtw8723d_iqk_check_tx_failed(rtwdev, iqk_cfg); 650 651 if (!status) 652 goto restore; 653 654 /* second round */ 655 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 656 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 657 658 rtw_write32(rtwdev, REG_TXIQK_11N, BIT_SET_TXIQK_11N(tx_x, tx_y)); 659 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n", 660 rtw_read32(rtwdev, REG_TXIQK_11N), 661 BIT_SET_TXIQK_11N(tx_x, tx_y)); 662 663 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s RXIQK STEP2!!\n", 664 iqk_cfg->name); 665 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK2 = 0x%x\n", 666 iqk_cfg->name, 667 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 668 669 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 670 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c); 671 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c); 672 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); 673 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); 674 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82170000); 675 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28171400); 676 677 /* LOK setting */ 678 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1); 679 680 /* RXIQK mode */ 681 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 682 mdelay(1); 683 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x80000, 0x1); 684 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00007); 685 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f); 686 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xb3fdb); 687 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); 688 689 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s RXIQK2 = 0x%x\n", 690 iqk_cfg->name, 691 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK)); 692 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s RXIQK2 = 0x%x\n", 693 iqk_cfg->name, 694 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK)); 695 696 rtw8723d_iqk_one_shot(rtwdev, false, iqk_cfg); 697 status |= rtw8723d_iqk_check_rx_failed(rtwdev, iqk_cfg); 698 699restore: 700 rtw8723d_iqk_txrx_path_post(rtwdev, iqk_cfg, backup); 701 702 return status; 703} 704 705static 706void rtw8723d_iqk_fill_s1_matrix(struct rtw_dev *rtwdev, const s32 result[]) 707{ 708 s32 oldval_1; 709 s32 x, y; 710 s32 tx1_a, tx1_a_ext; 711 s32 tx1_c, tx1_c_ext; 712 713 if (result[IQK_S1_TX_X] == 0) 714 return; 715 716 oldval_1 = rtw_read32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 717 BIT_MASK_TXIQ_ELM_D); 718 719 x = iqkxy_to_s32(result[IQK_S1_TX_X]); 720 tx1_a = iqk_mult(x, oldval_1, &tx1_a_ext); 721 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 722 BIT_MASK_TXIQ_ELM_A, tx1_a); 723 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, 724 BIT_MASK_OFDM0_EXT_A, tx1_a_ext); 725 726 y = iqkxy_to_s32(result[IQK_S1_TX_Y]); 727 tx1_c = iqk_mult(y, oldval_1, &tx1_c_ext); 728 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 729 BIT_SET_TXIQ_ELM_C1(tx1_c)); 730 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 731 BIT_MASK_TXIQ_ELM_C, BIT_SET_TXIQ_ELM_C2(tx1_c)); 732 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, 733 BIT_MASK_OFDM0_EXT_C, tx1_c_ext); 734 735 rtw_dbg(rtwdev, RTW_DBG_RFK, 736 "[IQK] X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n", 737 x, tx1_a, oldval_1); 738 rtw_dbg(rtwdev, RTW_DBG_RFK, 739 "[IQK] Y = 0x%x, TX1_C = 0x%x\n", y, tx1_c); 740 741 if (result[IQK_S1_RX_X] == 0) 742 return; 743 744 rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_X, 745 result[IQK_S1_RX_X]); 746 rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_Y1, 747 BIT_SET_RXIQ_S1_Y1(result[IQK_S1_RX_Y])); 748 rtw_write32_mask(rtwdev, REG_RXIQK_MATRIX_LSB_11N, BIT_MASK_RXIQ_S1_Y2, 749 BIT_SET_RXIQ_S1_Y2(result[IQK_S1_RX_Y])); 750} 751 752static 753void rtw8723d_iqk_fill_s0_matrix(struct rtw_dev *rtwdev, const s32 result[]) 754{ 755 s32 oldval_0; 756 s32 x, y; 757 s32 tx0_a, tx0_a_ext; 758 s32 tx0_c, tx0_c_ext; 759 760 if (result[IQK_S0_TX_X] == 0) 761 return; 762 763 oldval_0 = rtw_read32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0); 764 765 x = iqkxy_to_s32(result[IQK_S0_TX_X]); 766 tx0_a = iqk_mult(x, oldval_0, &tx0_a_ext); 767 768 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, tx0_a); 769 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, tx0_a_ext); 770 771 y = iqkxy_to_s32(result[IQK_S0_TX_Y]); 772 tx0_c = iqk_mult(y, oldval_0, &tx0_c_ext); 773 774 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, tx0_c); 775 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, tx0_c_ext); 776 777 if (result[IQK_S0_RX_X] == 0) 778 return; 779 780 rtw_write32_mask(rtwdev, REG_RXIQ_AB_S0, BIT_MASK_RXIQ_X_S0, 781 result[IQK_S0_RX_X]); 782 rtw_write32_mask(rtwdev, REG_RXIQ_AB_S0, BIT_MASK_RXIQ_Y_S0, 783 result[IQK_S0_RX_Y]); 784} 785 786static void rtw8723d_iqk_config_mac(struct rtw_dev *rtwdev) 787{ 788 rtw_write8(rtwdev, REG_TXPAUSE, 0xff); 789} 790 791static 792void rtw8723d_iqk_rf_standby(struct rtw_dev *rtwdev, enum rtw_rf_path path) 793{ 794 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path-%s standby mode!\n", 795 path == RF_PATH_A ? "S1" : "S0"); 796 797 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 798 mdelay(1); 799 rtw_write_rf(rtwdev, path, RF_MODE, RFREG_MASK, 0x10000); 800 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); 801} 802 803#define ADDA_ON_VAL_8723D 0x03c00016 804 805static 806void rtw8723d_iqk_precfg_path(struct rtw_dev *rtwdev, enum rtw8723x_path path) 807{ 808 if (path == PATH_S0) { 809 rtw8723d_iqk_rf_standby(rtwdev, RF_PATH_A); 810 rtw8723x_iqk_path_adda_on(rtwdev, ADDA_ON_VAL_8723D); 811 } 812 813 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); 814 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); 815 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 816 817 if (path == PATH_S1) { 818 rtw8723d_iqk_rf_standby(rtwdev, RF_PATH_B); 819 rtw8723x_iqk_path_adda_on(rtwdev, ADDA_ON_VAL_8723D); 820 } 821} 822 823static 824void rtw8723d_iqk_one_round(struct rtw_dev *rtwdev, s32 result[][IQK_NR], u8 t, 825 const struct rtw8723x_iqk_backup_regs *backup) 826{ 827 u32 i; 828 u8 s1_ok, s0_ok; 829 830 rtw_dbg(rtwdev, RTW_DBG_RFK, 831 "[IQK] IQ Calibration for 1T1R_S0/S1 for %d times\n", t); 832 833 rtw8723x_iqk_path_adda_on(rtwdev, ADDA_ON_VAL_8723D); 834 rtw8723d_iqk_config_mac(rtwdev); 835 rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf); 836 rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05611); 837 rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4); 838 rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204200); 839 rtw8723d_iqk_precfg_path(rtwdev, PATH_S1); 840 841 for (i = 0; i < PATH_IQK_RETRY; i++) { 842 s1_ok = rtw8723d_iqk_tx_path(rtwdev, &iqk_tx_cfg[PATH_S1], backup); 843 if (s1_ok == IQK_TX_OK) { 844 rtw_dbg(rtwdev, RTW_DBG_RFK, 845 "[IQK] path S1 Tx IQK Success!!\n"); 846 result[t][IQK_S1_TX_X] = 847 rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 848 result[t][IQK_S1_TX_Y] = 849 rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 850 break; 851 } 852 853 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 Tx IQK Fail!!\n"); 854 result[t][IQK_S1_TX_X] = 0x100; 855 result[t][IQK_S1_TX_Y] = 0x0; 856 } 857 858 for (i = 0; i < PATH_IQK_RETRY; i++) { 859 s1_ok = rtw8723d_iqk_rx_path(rtwdev, &iqk_tx_cfg[PATH_S1], backup); 860 if (s1_ok == (IQK_TX_OK | IQK_RX_OK)) { 861 rtw_dbg(rtwdev, RTW_DBG_RFK, 862 "[IQK] path S1 Rx IQK Success!!\n"); 863 result[t][IQK_S1_RX_X] = 864 rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX); 865 result[t][IQK_S1_RX_Y] = 866 rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY); 867 break; 868 } 869 870 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 Rx IQK Fail!!\n"); 871 result[t][IQK_S1_RX_X] = 0x100; 872 result[t][IQK_S1_RX_Y] = 0x0; 873 } 874 875 if (s1_ok == 0x0) 876 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 IQK is failed!!\n"); 877 878 rtw8723d_iqk_precfg_path(rtwdev, PATH_S0); 879 880 for (i = 0; i < PATH_IQK_RETRY; i++) { 881 s0_ok = rtw8723d_iqk_tx_path(rtwdev, &iqk_tx_cfg[PATH_S0], backup); 882 if (s0_ok == IQK_TX_OK) { 883 rtw_dbg(rtwdev, RTW_DBG_RFK, 884 "[IQK] path S0 Tx IQK Success!!\n"); 885 result[t][IQK_S0_TX_X] = 886 rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 887 result[t][IQK_S0_TX_Y] = 888 rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 889 break; 890 } 891 892 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 Tx IQK Fail!!\n"); 893 result[t][IQK_S0_TX_X] = 0x100; 894 result[t][IQK_S0_TX_Y] = 0x0; 895 } 896 897 for (i = 0; i < PATH_IQK_RETRY; i++) { 898 s0_ok = rtw8723d_iqk_rx_path(rtwdev, &iqk_tx_cfg[PATH_S0], backup); 899 if (s0_ok == (IQK_TX_OK | IQK_RX_OK)) { 900 rtw_dbg(rtwdev, RTW_DBG_RFK, 901 "[IQK] path S0 Rx IQK Success!!\n"); 902 903 result[t][IQK_S0_RX_X] = 904 rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX); 905 result[t][IQK_S0_RX_Y] = 906 rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY); 907 break; 908 } 909 910 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 Rx IQK Fail!!\n"); 911 result[t][IQK_S0_RX_X] = 0x100; 912 result[t][IQK_S0_RX_Y] = 0x0; 913 } 914 915 if (s0_ok == 0x0) 916 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 IQK is failed!!\n"); 917 918 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 919 mdelay(1); 920 921 rtw_dbg(rtwdev, RTW_DBG_RFK, 922 "[IQK] back to BB mode, load original value!\n"); 923} 924 925static void rtw8723d_phy_calibration(struct rtw_dev *rtwdev) 926{ 927 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 928 s32 result[IQK_ROUND_SIZE][IQK_NR]; 929 struct rtw8723x_iqk_backup_regs backup; 930 u8 i, j; 931 u8 final_candidate = IQK_ROUND_INVALID; 932 bool good; 933 934 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Start!!!\n"); 935 936 memset(result, 0, sizeof(result)); 937 938 rtw8723x_iqk_backup_path_ctrl(rtwdev, &backup); 939 rtw8723x_iqk_backup_lte_path_gnt(rtwdev, &backup); 940 rtw8723x_iqk_backup_regs(rtwdev, &backup); 941 942 for (i = IQK_ROUND_0; i <= IQK_ROUND_2; i++) { 943 rtw8723x_iqk_config_path_ctrl(rtwdev); 944 rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8723D); 945 946 rtw8723d_iqk_one_round(rtwdev, result, i, &backup); 947 948 if (i > IQK_ROUND_0) 949 rtw8723x_iqk_restore_regs(rtwdev, &backup); 950 rtw8723x_iqk_restore_lte_path_gnt(rtwdev, &backup); 951 rtw8723x_iqk_restore_path_ctrl(rtwdev, &backup); 952 953 for (j = IQK_ROUND_0; j < i; j++) { 954 good = rtw8723x_iqk_similarity_cmp(rtwdev, result, j, i); 955 956 if (good) { 957 final_candidate = j; 958 rtw_dbg(rtwdev, RTW_DBG_RFK, 959 "[IQK] cmp %d:%d final_candidate is %x\n", 960 j, i, final_candidate); 961 goto iqk_done; 962 } 963 } 964 } 965 966 if (final_candidate == IQK_ROUND_INVALID) { 967 s32 reg_tmp = 0; 968 969 for (i = 0; i < IQK_NR; i++) 970 reg_tmp += result[IQK_ROUND_HYBRID][i]; 971 972 if (reg_tmp != 0) { 973 final_candidate = IQK_ROUND_HYBRID; 974 } else { 975 WARN(1, "IQK is failed\n"); 976 goto out; 977 } 978 } 979 980iqk_done: 981 rtw8723d_iqk_fill_s1_matrix(rtwdev, result[final_candidate]); 982 rtw8723d_iqk_fill_s0_matrix(rtwdev, result[final_candidate]); 983 984 dm_info->iqk.result.s1_x = result[final_candidate][IQK_S1_TX_X]; 985 dm_info->iqk.result.s1_y = result[final_candidate][IQK_S1_TX_Y]; 986 dm_info->iqk.result.s0_x = result[final_candidate][IQK_S0_TX_X]; 987 dm_info->iqk.result.s0_y = result[final_candidate][IQK_S0_TX_Y]; 988 dm_info->iqk.done = true; 989 990out: 991 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup.bb_sel_btg); 992 993 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] final_candidate is %x\n", 994 final_candidate); 995 996 for (i = IQK_ROUND_0; i < IQK_ROUND_SIZE; i++) 997 rtw_dbg(rtwdev, RTW_DBG_RFK, 998 "[IQK] Result %u: rege94_s1=%x rege9c_s1=%x regea4_s1=%x regeac_s1=%x rege94_s0=%x rege9c_s0=%x regea4_s0=%x regeac_s0=%x %s\n", 999 i, 1000 result[i][0], result[i][1], result[i][2], result[i][3], 1001 result[i][4], result[i][5], result[i][6], result[i][7], 1002 final_candidate == i ? "(final candidate)" : ""); 1003 1004 rtw_dbg(rtwdev, RTW_DBG_RFK, 1005 "[IQK]0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n", 1006 rtw_read32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE), 1007 rtw_read32(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N), 1008 rtw_read32(rtwdev, REG_A_RXIQI), 1009 rtw_read32(rtwdev, REG_RXIQK_MATRIX_LSB_11N)); 1010 rtw_dbg(rtwdev, RTW_DBG_RFK, 1011 "[IQK]0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n", 1012 rtw_read32(rtwdev, REG_TXIQ_AB_S0), 1013 rtw_read32(rtwdev, REG_TXIQ_CD_S0), 1014 rtw_read32(rtwdev, REG_RXIQ_AB_S0)); 1015 1016 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] finished\n"); 1017} 1018 1019static void rtw8723d_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 1020{ 1021 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1022 u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13}; 1023 u8 cck_n_rx; 1024 1025 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n", 1026 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl); 1027 1028 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl) 1029 return; 1030 1031 cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) && 1032 rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1; 1033 rtw_dbg(rtwdev, RTW_DBG_PHY, 1034 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n", 1035 rtw_is_assoc(rtwdev), new_lvl, cck_n_rx, 1036 dm_info->cck_pd_default + new_lvl * 2, 1037 pd[new_lvl], dm_info->cck_fa_avg); 1038 1039 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 1040 1041 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl; 1042 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]); 1043 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000, 1044 dm_info->cck_pd_default + new_lvl * 2); 1045} 1046 1047/* for coex */ 1048static void rtw8723d_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 1049{ 1050} 1051 1052static void rtw8723d_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 1053{ 1054 rtw_write8_mask(rtwdev, REG_LEDCFG2, BIT(6), 0); 1055 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(0), 0); 1056 rtw_write8_mask(rtwdev, REG_GPIO_INTM + 2, BIT(4), 0); 1057 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT(1), 0); 1058 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(1), 0); 1059 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT(7), 0); 1060 rtw_write8_mask(rtwdev, REG_SYS_CLKR + 1, BIT(1), 0); 1061 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT(3), 0); 1062} 1063 1064static void rtw8723d_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 1065{ 1066 struct rtw_efuse *efuse = &rtwdev->efuse; 1067 struct rtw_coex *coex = &rtwdev->coex; 1068 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1069 bool aux = efuse->bt_setting & BIT(6); 1070 1071 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 1072 coex_rfe->ant_switch_polarity = 0; 1073 coex_rfe->ant_switch_exist = false; 1074 coex_rfe->ant_switch_with_bt = false; 1075 coex_rfe->ant_switch_diversity = false; 1076 coex_rfe->wlg_at_btg = true; 1077 1078 /* decide antenna at main or aux */ 1079 if (efuse->share_ant) { 1080 if (aux) 1081 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x80); 1082 else 1083 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x200); 1084 } else { 1085 if (aux) 1086 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x280); 1087 else 1088 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x0); 1089 } 1090 1091 /* disable LTE coex in wifi side */ 1092 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0); 1093 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); 1094 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); 1095} 1096 1097static void rtw8723d_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 1098{ 1099 struct rtw_coex *coex = &rtwdev->coex; 1100 struct rtw_coex_dm *coex_dm = &coex->dm; 1101 static const u8 wl_tx_power[] = {0xb2, 0x90}; 1102 u8 pwr; 1103 1104 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 1105 return; 1106 1107 coex_dm->cur_wl_pwr_lvl = wl_pwr; 1108 1109 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power)) 1110 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1; 1111 1112 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl]; 1113 1114 rtw_write8(rtwdev, REG_ANA_PARAM1 + 3, pwr); 1115} 1116 1117static void rtw8723d_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 1118{ 1119 struct rtw_coex *coex = &rtwdev->coex; 1120 struct rtw_coex_dm *coex_dm = &coex->dm; 1121 /* WL Rx Low gain on */ 1122 static const u32 wl_rx_low_gain_on[] = { 1123 0xec120101, 0xeb130101, 0xce140101, 0xcd150101, 0xcc160101, 1124 0xcb170101, 0xca180101, 0x8d190101, 0x8c1a0101, 0x8b1b0101, 1125 0x4f1c0101, 0x4e1d0101, 0x4d1e0101, 0x4c1f0101, 0x0e200101, 1126 0x0d210101, 0x0c220101, 0x0b230101, 0xcf240001, 0xce250001, 1127 0xcd260001, 0xcc270001, 0x8f280001 1128 }; 1129 /* WL Rx Low gain off */ 1130 static const u32 wl_rx_low_gain_off[] = { 1131 0xec120101, 0xeb130101, 0xea140101, 0xe9150101, 0xe8160101, 1132 0xe7170101, 0xe6180101, 0xe5190101, 0xe41a0101, 0xe31b0101, 1133 0xe21c0101, 0xe11d0101, 0xe01e0101, 0x861f0101, 0x85200101, 1134 0x84210101, 0x83220101, 0x82230101, 0x81240101, 0x80250101, 1135 0x44260101, 0x43270101, 0x42280101 1136 }; 1137 u8 i; 1138 1139 if (low_gain == coex_dm->cur_wl_rx_low_gain_en) 1140 return; 1141 1142 coex_dm->cur_wl_rx_low_gain_en = low_gain; 1143 1144 if (coex_dm->cur_wl_rx_low_gain_en) { 1145 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++) 1146 rtw_write32(rtwdev, REG_AGCRSSI, wl_rx_low_gain_on[i]); 1147 } else { 1148 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++) 1149 rtw_write32(rtwdev, REG_AGCRSSI, wl_rx_low_gain_off[i]); 1150 } 1151} 1152 1153static void rtw8723d_set_iqk_matrix_by_result(struct rtw_dev *rtwdev, 1154 u32 ofdm_swing, u8 rf_path) 1155{ 1156 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1157 s32 ele_A, ele_D, ele_C; 1158 s32 ele_A_ext, ele_C_ext, ele_D_ext; 1159 s32 iqk_result_x; 1160 s32 iqk_result_y; 1161 s32 value32; 1162 1163 switch (rf_path) { 1164 default: 1165 case RF_PATH_A: 1166 iqk_result_x = dm_info->iqk.result.s1_x; 1167 iqk_result_y = dm_info->iqk.result.s1_y; 1168 break; 1169 case RF_PATH_B: 1170 iqk_result_x = dm_info->iqk.result.s0_x; 1171 iqk_result_y = dm_info->iqk.result.s0_y; 1172 break; 1173 } 1174 1175 /* new element D */ 1176 ele_D = OFDM_SWING_D(ofdm_swing); 1177 iqk_mult(iqk_result_x, ele_D, &ele_D_ext); 1178 /* new element A */ 1179 iqk_result_x = iqkxy_to_s32(iqk_result_x); 1180 ele_A = iqk_mult(iqk_result_x, ele_D, &ele_A_ext); 1181 /* new element C */ 1182 iqk_result_y = iqkxy_to_s32(iqk_result_y); 1183 ele_C = iqk_mult(iqk_result_y, ele_D, &ele_C_ext); 1184 1185 switch (rf_path) { 1186 case RF_PATH_A: 1187 default: 1188 /* write new elements A, C, D, and element B is always 0 */ 1189 value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D); 1190 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, value32); 1191 value32 = BIT_SET_TXIQ_ELM_C1(ele_C); 1192 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1193 value32); 1194 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1195 value32 &= ~BIT_MASK_OFDM0_EXTS; 1196 value32 |= BIT_SET_OFDM0_EXTS(ele_A_ext, ele_C_ext, ele_D_ext); 1197 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1198 break; 1199 1200 case RF_PATH_B: 1201 /* write new elements A, C, D, and element B is always 0 */ 1202 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0, ele_D); 1203 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, ele_C); 1204 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, ele_A); 1205 1206 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0, 1207 ele_D_ext); 1208 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, 1209 ele_A_ext); 1210 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, 1211 ele_C_ext); 1212 break; 1213 } 1214} 1215 1216static void rtw8723d_set_iqk_matrix(struct rtw_dev *rtwdev, s8 ofdm_index, 1217 u8 rf_path) 1218{ 1219 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1220 s32 value32; 1221 u32 ofdm_swing; 1222 1223 if (ofdm_index >= RTW_OFDM_SWING_TABLE_SIZE) 1224 ofdm_index = RTW_OFDM_SWING_TABLE_SIZE - 1; 1225 else if (ofdm_index < 0) 1226 ofdm_index = 0; 1227 1228 ofdm_swing = rtw8723d_ofdm_swing_table[ofdm_index]; 1229 1230 if (dm_info->iqk.done) { 1231 rtw8723d_set_iqk_matrix_by_result(rtwdev, ofdm_swing, rf_path); 1232 return; 1233 } 1234 1235 switch (rf_path) { 1236 case RF_PATH_A: 1237 default: 1238 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, ofdm_swing); 1239 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1240 0x00); 1241 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1242 value32 &= ~BIT_MASK_OFDM0_EXTS; 1243 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1244 break; 1245 1246 case RF_PATH_B: 1247 /* image S1:c80 to S0:Cd0 and Cd4 */ 1248 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, 1249 OFDM_SWING_A(ofdm_swing)); 1250 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_B_S0, 1251 OFDM_SWING_B(ofdm_swing)); 1252 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, 1253 OFDM_SWING_C(ofdm_swing)); 1254 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0, 1255 OFDM_SWING_D(ofdm_swing)); 1256 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0, 0x0); 1257 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, 0x0); 1258 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, 0x0); 1259 break; 1260 } 1261} 1262 1263static void rtw8723d_pwrtrack_set_ofdm_pwr(struct rtw_dev *rtwdev, s8 swing_idx, 1264 s8 txagc_idx) 1265{ 1266 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1267 1268 dm_info->txagc_remnant_ofdm[RF_PATH_A] = txagc_idx; 1269 1270 rtw8723d_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_A); 1271 rtw8723d_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_B); 1272} 1273 1274static void rtw8723d_pwrtrack_set_cck_pwr(struct rtw_dev *rtwdev, s8 swing_idx, 1275 s8 txagc_idx) 1276{ 1277 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1278 1279 dm_info->txagc_remnant_cck = txagc_idx; 1280 1281 rtw_write32_mask(rtwdev, 0xab4, 0x000007FF, 1282 rtw8723d_cck_swing_table[swing_idx]); 1283} 1284 1285static void rtw8723d_pwrtrack_set(struct rtw_dev *rtwdev, u8 path) 1286{ 1287 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1288 struct rtw_hal *hal = &rtwdev->hal; 1289 u8 limit_ofdm; 1290 u8 limit_cck = 40; 1291 s8 final_ofdm_swing_index; 1292 s8 final_cck_swing_index; 1293 1294 limit_ofdm = rtw8723x_pwrtrack_get_limit_ofdm(rtwdev); 1295 1296 final_ofdm_swing_index = RTW_DEF_OFDM_SWING_INDEX + 1297 dm_info->delta_power_index[path]; 1298 final_cck_swing_index = RTW_DEF_CCK_SWING_INDEX + 1299 dm_info->delta_power_index[path]; 1300 1301 if (final_ofdm_swing_index > limit_ofdm) 1302 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, limit_ofdm, 1303 final_ofdm_swing_index - limit_ofdm); 1304 else if (final_ofdm_swing_index < 0) 1305 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, 0, 1306 final_ofdm_swing_index); 1307 else 1308 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0); 1309 1310 if (final_cck_swing_index > limit_cck) 1311 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, limit_cck, 1312 final_cck_swing_index - limit_cck); 1313 else if (final_cck_swing_index < 0) 1314 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, 0, 1315 final_cck_swing_index); 1316 else 1317 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0); 1318 1319 rtw_phy_set_tx_power_level(rtwdev, hal->current_channel); 1320} 1321 1322static void rtw8723d_phy_pwrtrack(struct rtw_dev *rtwdev) 1323{ 1324 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1325 struct rtw_swing_table swing_table; 1326 u8 thermal_value, delta, path; 1327 bool do_iqk = false; 1328 1329 rtw_phy_config_swing_table(rtwdev, &swing_table); 1330 1331 if (rtwdev->efuse.thermal_meter[0] == 0xff) 1332 return; 1333 1334 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1335 1336 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1337 1338 do_iqk = rtw_phy_pwrtrack_need_iqk(rtwdev); 1339 1340 if (do_iqk) 1341 rtw8723x_lck(rtwdev); 1342 1343 if (dm_info->pwr_trk_init_trigger) 1344 dm_info->pwr_trk_init_trigger = false; 1345 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1346 RF_PATH_A)) 1347 goto iqk; 1348 1349 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1350 1351 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); 1352 1353 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1354 s8 delta_cur, delta_last; 1355 1356 delta_last = dm_info->delta_power_index[path]; 1357 delta_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, 1358 path, RF_PATH_A, delta); 1359 if (delta_last == delta_cur) 1360 continue; 1361 1362 dm_info->delta_power_index[path] = delta_cur; 1363 rtw8723d_pwrtrack_set(rtwdev, path); 1364 } 1365 1366 rtw8723x_pwrtrack_set_xtal(rtwdev, RF_PATH_A, delta); 1367 1368iqk: 1369 if (do_iqk) 1370 rtw8723d_phy_calibration(rtwdev); 1371} 1372 1373static void rtw8723d_pwr_track(struct rtw_dev *rtwdev) 1374{ 1375 struct rtw_efuse *efuse = &rtwdev->efuse; 1376 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1377 1378 if (efuse->power_track_type != 0) 1379 return; 1380 1381 if (!dm_info->pwr_trk_triggered) { 1382 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1383 GENMASK(17, 16), 0x03); 1384 dm_info->pwr_trk_triggered = true; 1385 return; 1386 } 1387 1388 rtw8723d_phy_pwrtrack(rtwdev); 1389 dm_info->pwr_trk_triggered = false; 1390} 1391 1392static const struct rtw_chip_ops rtw8723d_ops = { 1393 .power_on = rtw_power_on, 1394 .power_off = rtw_power_off, 1395 .phy_set_param = rtw8723d_phy_set_param, 1396 .read_efuse = rtw8723x_read_efuse, 1397 .query_phy_status = query_phy_status, 1398 .set_channel = rtw8723d_set_channel, 1399 .mac_init = rtw8723x_mac_init, 1400 .mac_postinit = rtw8723x_mac_postinit, 1401 .shutdown = rtw8723d_shutdown, 1402 .read_rf = rtw_phy_read_rf_sipi, 1403 .write_rf = rtw_phy_write_rf_reg_sipi, 1404 .set_tx_power_index = rtw8723x_set_tx_power_index, 1405 .set_antenna = NULL, 1406 .cfg_ldo25 = rtw8723x_cfg_ldo25, 1407 .efuse_grant = rtw8723x_efuse_grant, 1408 .set_ampdu_factor = NULL, 1409 .false_alarm_statistics = rtw8723x_false_alarm_statistics, 1410 .phy_calibration = rtw8723d_phy_calibration, 1411 .cck_pd_set = rtw8723d_phy_cck_pd_set, 1412 .pwr_track = rtw8723d_pwr_track, 1413 .config_bfee = NULL, 1414 .set_gid_table = NULL, 1415 .cfg_csi_rate = NULL, 1416 .fill_txdesc_checksum = rtw8723x_fill_txdesc_checksum, 1417 1418 .coex_set_init = rtw8723x_coex_cfg_init, 1419 .coex_set_ant_switch = NULL, 1420 .coex_set_gnt_fix = rtw8723d_coex_cfg_gnt_fix, 1421 .coex_set_gnt_debug = rtw8723d_coex_cfg_gnt_debug, 1422 .coex_set_rfe_type = rtw8723d_coex_cfg_rfe_type, 1423 .coex_set_wl_tx_power = rtw8723d_coex_cfg_wl_tx_power, 1424 .coex_set_wl_rx_gain = rtw8723d_coex_cfg_wl_rx_gain, 1425}; 1426 1427/* Shared-Antenna Coex Table */ 1428static const struct coex_table_para table_sant_8723d[] = { 1429 {0xffffffff, 0xffffffff}, /* case-0 */ 1430 {0x55555555, 0x55555555}, 1431 {0x66555555, 0x66555555}, 1432 {0xaaaaaaaa, 0xaaaaaaaa}, 1433 {0x5a5a5a5a, 0x5a5a5a5a}, 1434 {0xfafafafa, 0xfafafafa}, /* case-5 */ 1435 {0x6a5a5555, 0xaaaaaaaa}, 1436 {0x6a5a56aa, 0x6a5a56aa}, 1437 {0x6a5a5a5a, 0x6a5a5a5a}, 1438 {0x66555555, 0x5a5a5a5a}, 1439 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 1440 {0x66555555, 0x6a5a5aaa}, 1441 {0x66555555, 0x5a5a5aaa}, 1442 {0x66555555, 0x6aaa5aaa}, 1443 {0x66555555, 0xaaaa5aaa}, 1444 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 1445 {0xffff55ff, 0xfafafafa}, 1446 {0xffff55ff, 0x6afa5afa}, 1447 {0xaaffffaa, 0xfafafafa}, 1448 {0xaa5555aa, 0x5a5a5a5a}, 1449 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 1450 {0xaa5555aa, 0xaaaaaaaa}, 1451 {0xffffffff, 0x5a5a5a5a}, 1452 {0xffffffff, 0x5a5a5a5a}, 1453 {0xffffffff, 0x55555555}, 1454 {0xffffffff, 0x5a5a5aaa}, /* case-25 */ 1455 {0x55555555, 0x5a5a5a5a}, 1456 {0x55555555, 0xaaaaaaaa}, 1457 {0x55555555, 0x6a5a6a5a}, 1458 {0x66556655, 0x66556655}, 1459 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */ 1460 {0xffffffff, 0x5aaa5aaa}, 1461 {0x56555555, 0x5a5a5aaa}, 1462}; 1463 1464/* Non-Shared-Antenna Coex Table */ 1465static const struct coex_table_para table_nsant_8723d[] = { 1466 {0xffffffff, 0xffffffff}, /* case-100 */ 1467 {0x55555555, 0x55555555}, 1468 {0x66555555, 0x66555555}, 1469 {0xaaaaaaaa, 0xaaaaaaaa}, 1470 {0x5a5a5a5a, 0x5a5a5a5a}, 1471 {0xfafafafa, 0xfafafafa}, /* case-105 */ 1472 {0x5afa5afa, 0x5afa5afa}, 1473 {0x55555555, 0xfafafafa}, 1474 {0x66555555, 0xfafafafa}, 1475 {0x66555555, 0x5a5a5a5a}, 1476 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 1477 {0x66555555, 0xaaaaaaaa}, 1478 {0xffff55ff, 0xfafafafa}, 1479 {0xffff55ff, 0x5afa5afa}, 1480 {0xffff55ff, 0xaaaaaaaa}, 1481 {0xffff55ff, 0xffff55ff}, /* case-115 */ 1482 {0xaaffffaa, 0x5afa5afa}, 1483 {0xaaffffaa, 0xaaaaaaaa}, 1484 {0xffffffff, 0xfafafafa}, 1485 {0xffffffff, 0x5afa5afa}, 1486 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 1487 {0x55ff55ff, 0x5afa5afa}, 1488 {0x55ff55ff, 0xaaaaaaaa}, 1489 {0x55ff55ff, 0x55ff55ff} 1490}; 1491 1492/* Shared-Antenna TDMA */ 1493static const struct coex_tdma_para tdma_sant_8723d[] = { 1494 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 1495 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 1496 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 1497 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 1498 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1499 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 1500 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1501 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 1502 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1503 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1504 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 1505 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 1506 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1507 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1508 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1509 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 1510 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1511 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 1512 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1513 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 1514 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 1515 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 1516 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 1517 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 1518 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 1519 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 1520 { {0x51, 0x08, 0x03, 0x10, 0x50} }, 1521 { {0x61, 0x08, 0x03, 0x11, 0x11} } 1522}; 1523 1524/* Non-Shared-Antenna TDMA */ 1525static const struct coex_tdma_para tdma_nsant_8723d[] = { 1526 { {0x00, 0x00, 0x00, 0x00, 0x01} }, /* case-100 */ 1527 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */ 1528 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 1529 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 1530 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1531 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 1532 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1533 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 1534 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1535 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1536 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 1537 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 1538 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1539 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1540 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1541 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 1542 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1543 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 1544 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1545 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 1546 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */ 1547 { {0x51, 0x08, 0x03, 0x10, 0x50} } 1548}; 1549 1550/* rssi in percentage % (dbm = % - 100) */ 1551static const u8 wl_rssi_step_8723d[] = {60, 50, 44, 30}; 1552static const u8 bt_rssi_step_8723d[] = {30, 30, 30, 30}; 1553static const struct coex_5g_afh_map afh_5g_8723d[] = { {0, 0, 0} }; 1554 1555static const struct rtw_hw_reg btg_reg_8723d = { 1556 .addr = REG_BTG_SEL, .mask = BIT_MASK_BTG_WL, 1557}; 1558 1559/* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 1560static const struct coex_rf_para rf_para_tx_8723d[] = { 1561 {0, 0, false, 7}, /* for normal */ 1562 {0, 10, false, 7}, /* for WL-CPT */ 1563 {1, 0, true, 4}, 1564 {1, 2, true, 4}, 1565 {1, 10, true, 4}, 1566 {1, 15, true, 4} 1567}; 1568 1569static const struct coex_rf_para rf_para_rx_8723d[] = { 1570 {0, 0, false, 7}, /* for normal */ 1571 {0, 10, false, 7}, /* for WL-CPT */ 1572 {1, 0, true, 5}, 1573 {1, 2, true, 5}, 1574 {1, 10, true, 5}, 1575 {1, 15, true, 5} 1576}; 1577 1578static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8723d[] = { 1579 {0x0005, 1580 RTW_PWR_CUT_ALL_MSK, 1581 RTW_PWR_INTF_ALL_MSK, 1582 RTW_PWR_ADDR_MAC, 1583 RTW_PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, 1584 {0x0086, 1585 RTW_PWR_CUT_ALL_MSK, 1586 RTW_PWR_INTF_SDIO_MSK, 1587 RTW_PWR_ADDR_SDIO, 1588 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1589 {0x0086, 1590 RTW_PWR_CUT_ALL_MSK, 1591 RTW_PWR_INTF_SDIO_MSK, 1592 RTW_PWR_ADDR_SDIO, 1593 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1594 {0x004A, 1595 RTW_PWR_CUT_ALL_MSK, 1596 RTW_PWR_INTF_USB_MSK, 1597 RTW_PWR_ADDR_MAC, 1598 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1599 {0x0005, 1600 RTW_PWR_CUT_ALL_MSK, 1601 RTW_PWR_INTF_ALL_MSK, 1602 RTW_PWR_ADDR_MAC, 1603 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, 1604 {0x0023, 1605 RTW_PWR_CUT_ALL_MSK, 1606 RTW_PWR_INTF_SDIO_MSK, 1607 RTW_PWR_ADDR_MAC, 1608 RTW_PWR_CMD_WRITE, BIT(4), 0}, 1609 {0x0301, 1610 RTW_PWR_CUT_ALL_MSK, 1611 RTW_PWR_INTF_PCI_MSK, 1612 RTW_PWR_ADDR_MAC, 1613 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1614 {0xFFFF, 1615 RTW_PWR_CUT_ALL_MSK, 1616 RTW_PWR_INTF_ALL_MSK, 1617 0, 1618 RTW_PWR_CMD_END, 0, 0}, 1619}; 1620 1621static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8723d[] = { 1622 {0x0020, 1623 RTW_PWR_CUT_ALL_MSK, 1624 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1625 RTW_PWR_ADDR_MAC, 1626 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1627 {0x0001, 1628 RTW_PWR_CUT_ALL_MSK, 1629 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1630 RTW_PWR_ADDR_MAC, 1631 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 1632 {0x0000, 1633 RTW_PWR_CUT_ALL_MSK, 1634 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1635 RTW_PWR_ADDR_MAC, 1636 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1637 {0x0005, 1638 RTW_PWR_CUT_ALL_MSK, 1639 RTW_PWR_INTF_ALL_MSK, 1640 RTW_PWR_ADDR_MAC, 1641 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 1642 {0x0075, 1643 RTW_PWR_CUT_ALL_MSK, 1644 RTW_PWR_INTF_PCI_MSK, 1645 RTW_PWR_ADDR_MAC, 1646 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1647 {0x0006, 1648 RTW_PWR_CUT_ALL_MSK, 1649 RTW_PWR_INTF_ALL_MSK, 1650 RTW_PWR_ADDR_MAC, 1651 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1652 {0x0075, 1653 RTW_PWR_CUT_ALL_MSK, 1654 RTW_PWR_INTF_PCI_MSK, 1655 RTW_PWR_ADDR_MAC, 1656 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1657 {0x0006, 1658 RTW_PWR_CUT_ALL_MSK, 1659 RTW_PWR_INTF_ALL_MSK, 1660 RTW_PWR_ADDR_MAC, 1661 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1662 {0x0005, 1663 RTW_PWR_CUT_ALL_MSK, 1664 RTW_PWR_INTF_ALL_MSK, 1665 RTW_PWR_ADDR_MAC, 1666 RTW_PWR_CMD_POLLING, (BIT(1) | BIT(0)), 0}, 1667 {0x0005, 1668 RTW_PWR_CUT_ALL_MSK, 1669 RTW_PWR_INTF_ALL_MSK, 1670 RTW_PWR_ADDR_MAC, 1671 RTW_PWR_CMD_WRITE, BIT(7), 0}, 1672 {0x0005, 1673 RTW_PWR_CUT_ALL_MSK, 1674 RTW_PWR_INTF_ALL_MSK, 1675 RTW_PWR_ADDR_MAC, 1676 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 1677 {0x0005, 1678 RTW_PWR_CUT_ALL_MSK, 1679 RTW_PWR_INTF_ALL_MSK, 1680 RTW_PWR_ADDR_MAC, 1681 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1682 {0x0005, 1683 RTW_PWR_CUT_ALL_MSK, 1684 RTW_PWR_INTF_ALL_MSK, 1685 RTW_PWR_ADDR_MAC, 1686 RTW_PWR_CMD_POLLING, BIT(0), 0}, 1687 {0x0010, 1688 RTW_PWR_CUT_ALL_MSK, 1689 RTW_PWR_INTF_ALL_MSK, 1690 RTW_PWR_ADDR_MAC, 1691 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 1692 {0x0049, 1693 RTW_PWR_CUT_ALL_MSK, 1694 RTW_PWR_INTF_ALL_MSK, 1695 RTW_PWR_ADDR_MAC, 1696 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 1697 {0x0063, 1698 RTW_PWR_CUT_ALL_MSK, 1699 RTW_PWR_INTF_ALL_MSK, 1700 RTW_PWR_ADDR_MAC, 1701 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 1702 {0x0062, 1703 RTW_PWR_CUT_ALL_MSK, 1704 RTW_PWR_INTF_ALL_MSK, 1705 RTW_PWR_ADDR_MAC, 1706 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1707 {0x0058, 1708 RTW_PWR_CUT_ALL_MSK, 1709 RTW_PWR_INTF_ALL_MSK, 1710 RTW_PWR_ADDR_MAC, 1711 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1712 {0x005A, 1713 RTW_PWR_CUT_ALL_MSK, 1714 RTW_PWR_INTF_ALL_MSK, 1715 RTW_PWR_ADDR_MAC, 1716 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 1717 {0x0068, 1718 RTW_PWR_CUT_TEST_MSK, 1719 RTW_PWR_INTF_ALL_MSK, 1720 RTW_PWR_ADDR_MAC, 1721 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 1722 {0x0069, 1723 RTW_PWR_CUT_ALL_MSK, 1724 RTW_PWR_INTF_ALL_MSK, 1725 RTW_PWR_ADDR_MAC, 1726 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 1727 {0x001f, 1728 RTW_PWR_CUT_ALL_MSK, 1729 RTW_PWR_INTF_ALL_MSK, 1730 RTW_PWR_ADDR_MAC, 1731 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 1732 {0x0077, 1733 RTW_PWR_CUT_ALL_MSK, 1734 RTW_PWR_INTF_ALL_MSK, 1735 RTW_PWR_ADDR_MAC, 1736 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 1737 {0x001f, 1738 RTW_PWR_CUT_ALL_MSK, 1739 RTW_PWR_INTF_ALL_MSK, 1740 RTW_PWR_ADDR_MAC, 1741 RTW_PWR_CMD_WRITE, 0xFF, 0x07}, 1742 {0x0077, 1743 RTW_PWR_CUT_ALL_MSK, 1744 RTW_PWR_INTF_ALL_MSK, 1745 RTW_PWR_ADDR_MAC, 1746 RTW_PWR_CMD_WRITE, 0xFF, 0x07}, 1747 {0xFFFF, 1748 RTW_PWR_CUT_ALL_MSK, 1749 RTW_PWR_INTF_ALL_MSK, 1750 0, 1751 RTW_PWR_CMD_END, 0, 0}, 1752}; 1753 1754static const struct rtw_pwr_seq_cmd * const card_enable_flow_8723d[] = { 1755 trans_carddis_to_cardemu_8723d, 1756 trans_cardemu_to_act_8723d, 1757 NULL 1758}; 1759 1760static const struct rtw_pwr_seq_cmd trans_act_to_lps_8723d[] = { 1761 {0x0301, 1762 RTW_PWR_CUT_ALL_MSK, 1763 RTW_PWR_INTF_PCI_MSK, 1764 RTW_PWR_ADDR_MAC, 1765 RTW_PWR_CMD_WRITE, 0xFF, 0xFF}, 1766 {0x0522, 1767 RTW_PWR_CUT_ALL_MSK, 1768 RTW_PWR_INTF_ALL_MSK, 1769 RTW_PWR_ADDR_MAC, 1770 RTW_PWR_CMD_WRITE, 0xFF, 0xFF}, 1771 {0x05F8, 1772 RTW_PWR_CUT_ALL_MSK, 1773 RTW_PWR_INTF_ALL_MSK, 1774 RTW_PWR_ADDR_MAC, 1775 RTW_PWR_CMD_POLLING, 0xFF, 0}, 1776 {0x05F9, 1777 RTW_PWR_CUT_ALL_MSK, 1778 RTW_PWR_INTF_ALL_MSK, 1779 RTW_PWR_ADDR_MAC, 1780 RTW_PWR_CMD_POLLING, 0xFF, 0}, 1781 {0x05FA, 1782 RTW_PWR_CUT_ALL_MSK, 1783 RTW_PWR_INTF_ALL_MSK, 1784 RTW_PWR_ADDR_MAC, 1785 RTW_PWR_CMD_POLLING, 0xFF, 0}, 1786 {0x05FB, 1787 RTW_PWR_CUT_ALL_MSK, 1788 RTW_PWR_INTF_ALL_MSK, 1789 RTW_PWR_ADDR_MAC, 1790 RTW_PWR_CMD_POLLING, 0xFF, 0}, 1791 {0x0002, 1792 RTW_PWR_CUT_ALL_MSK, 1793 RTW_PWR_INTF_ALL_MSK, 1794 RTW_PWR_ADDR_MAC, 1795 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1796 {0x0002, 1797 RTW_PWR_CUT_ALL_MSK, 1798 RTW_PWR_INTF_ALL_MSK, 1799 RTW_PWR_ADDR_MAC, 1800 RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US}, 1801 {0x0002, 1802 RTW_PWR_CUT_ALL_MSK, 1803 RTW_PWR_INTF_ALL_MSK, 1804 RTW_PWR_ADDR_MAC, 1805 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1806 {0x0100, 1807 RTW_PWR_CUT_ALL_MSK, 1808 RTW_PWR_INTF_ALL_MSK, 1809 RTW_PWR_ADDR_MAC, 1810 RTW_PWR_CMD_WRITE, 0xFF, 0x03}, 1811 {0x0101, 1812 RTW_PWR_CUT_ALL_MSK, 1813 RTW_PWR_INTF_ALL_MSK, 1814 RTW_PWR_ADDR_MAC, 1815 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1816 {0x0093, 1817 RTW_PWR_CUT_ALL_MSK, 1818 RTW_PWR_INTF_SDIO_MSK, 1819 RTW_PWR_ADDR_MAC, 1820 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 1821 {0x0553, 1822 RTW_PWR_CUT_ALL_MSK, 1823 RTW_PWR_INTF_ALL_MSK, 1824 RTW_PWR_ADDR_MAC, 1825 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1826 {0xFFFF, 1827 RTW_PWR_CUT_ALL_MSK, 1828 RTW_PWR_INTF_ALL_MSK, 1829 0, 1830 RTW_PWR_CMD_END, 0, 0}, 1831}; 1832 1833static const struct rtw_pwr_seq_cmd trans_act_to_pre_carddis_8723d[] = { 1834 {0x0003, 1835 RTW_PWR_CUT_ALL_MSK, 1836 RTW_PWR_INTF_ALL_MSK, 1837 RTW_PWR_ADDR_MAC, 1838 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1839 {0x0080, 1840 RTW_PWR_CUT_ALL_MSK, 1841 RTW_PWR_INTF_ALL_MSK, 1842 RTW_PWR_ADDR_MAC, 1843 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1844 {0xFFFF, 1845 RTW_PWR_CUT_ALL_MSK, 1846 RTW_PWR_INTF_ALL_MSK, 1847 0, 1848 RTW_PWR_CMD_END, 0, 0}, 1849}; 1850 1851static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8723d[] = { 1852 {0x0002, 1853 RTW_PWR_CUT_ALL_MSK, 1854 RTW_PWR_INTF_ALL_MSK, 1855 RTW_PWR_ADDR_MAC, 1856 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1857 {0x0049, 1858 RTW_PWR_CUT_ALL_MSK, 1859 RTW_PWR_INTF_ALL_MSK, 1860 RTW_PWR_ADDR_MAC, 1861 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1862 {0x0006, 1863 RTW_PWR_CUT_ALL_MSK, 1864 RTW_PWR_INTF_ALL_MSK, 1865 RTW_PWR_ADDR_MAC, 1866 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1867 {0x0005, 1868 RTW_PWR_CUT_ALL_MSK, 1869 RTW_PWR_INTF_ALL_MSK, 1870 RTW_PWR_ADDR_MAC, 1871 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 1872 {0x0005, 1873 RTW_PWR_CUT_ALL_MSK, 1874 RTW_PWR_INTF_ALL_MSK, 1875 RTW_PWR_ADDR_MAC, 1876 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1877 {0x0010, 1878 RTW_PWR_CUT_ALL_MSK, 1879 RTW_PWR_INTF_ALL_MSK, 1880 RTW_PWR_ADDR_MAC, 1881 RTW_PWR_CMD_WRITE, BIT(6), 0}, 1882 {0x0000, 1883 RTW_PWR_CUT_ALL_MSK, 1884 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1885 RTW_PWR_ADDR_MAC, 1886 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1887 {0x0020, 1888 RTW_PWR_CUT_ALL_MSK, 1889 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1890 RTW_PWR_ADDR_MAC, 1891 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1892 {0xFFFF, 1893 RTW_PWR_CUT_ALL_MSK, 1894 RTW_PWR_INTF_ALL_MSK, 1895 0, 1896 RTW_PWR_CMD_END, 0, 0}, 1897}; 1898 1899static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8723d[] = { 1900 {0x0007, 1901 RTW_PWR_CUT_ALL_MSK, 1902 RTW_PWR_INTF_SDIO_MSK, 1903 RTW_PWR_ADDR_MAC, 1904 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 1905 {0x0005, 1906 RTW_PWR_CUT_ALL_MSK, 1907 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1908 RTW_PWR_ADDR_MAC, 1909 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 1910 {0x0005, 1911 RTW_PWR_CUT_ALL_MSK, 1912 RTW_PWR_INTF_PCI_MSK, 1913 RTW_PWR_ADDR_MAC, 1914 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 1915 {0x0005, 1916 RTW_PWR_CUT_ALL_MSK, 1917 RTW_PWR_INTF_PCI_MSK, 1918 RTW_PWR_ADDR_MAC, 1919 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)}, 1920 {0x004A, 1921 RTW_PWR_CUT_ALL_MSK, 1922 RTW_PWR_INTF_USB_MSK, 1923 RTW_PWR_ADDR_MAC, 1924 RTW_PWR_CMD_WRITE, BIT(0), 1}, 1925 {0x0023, 1926 RTW_PWR_CUT_ALL_MSK, 1927 RTW_PWR_INTF_SDIO_MSK, 1928 RTW_PWR_ADDR_MAC, 1929 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 1930 {0x0086, 1931 RTW_PWR_CUT_ALL_MSK, 1932 RTW_PWR_INTF_SDIO_MSK, 1933 RTW_PWR_ADDR_SDIO, 1934 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1935 {0x0086, 1936 RTW_PWR_CUT_ALL_MSK, 1937 RTW_PWR_INTF_SDIO_MSK, 1938 RTW_PWR_ADDR_SDIO, 1939 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1940 {0xFFFF, 1941 RTW_PWR_CUT_ALL_MSK, 1942 RTW_PWR_INTF_ALL_MSK, 1943 0, 1944 RTW_PWR_CMD_END, 0, 0}, 1945}; 1946 1947static const struct rtw_pwr_seq_cmd trans_act_to_post_carddis_8723d[] = { 1948 {0x001D, 1949 RTW_PWR_CUT_ALL_MSK, 1950 RTW_PWR_INTF_ALL_MSK, 1951 RTW_PWR_ADDR_MAC, 1952 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1953 {0x001D, 1954 RTW_PWR_CUT_ALL_MSK, 1955 RTW_PWR_INTF_ALL_MSK, 1956 RTW_PWR_ADDR_MAC, 1957 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1958 {0x001C, 1959 RTW_PWR_CUT_ALL_MSK, 1960 RTW_PWR_INTF_ALL_MSK, 1961 RTW_PWR_ADDR_MAC, 1962 RTW_PWR_CMD_WRITE, 0xFF, 0x0E}, 1963 {0xFFFF, 1964 RTW_PWR_CUT_ALL_MSK, 1965 RTW_PWR_INTF_ALL_MSK, 1966 0, 1967 RTW_PWR_CMD_END, 0, 0}, 1968}; 1969 1970static const struct rtw_pwr_seq_cmd * const card_disable_flow_8723d[] = { 1971 trans_act_to_lps_8723d, 1972 trans_act_to_pre_carddis_8723d, 1973 trans_act_to_cardemu_8723d, 1974 trans_cardemu_to_carddis_8723d, 1975 trans_act_to_post_carddis_8723d, 1976 NULL 1977}; 1978 1979static const struct rtw_page_table page_table_8723d[] = { 1980 {12, 2, 2, 0, 1}, 1981 {12, 2, 2, 0, 1}, 1982 {12, 2, 2, 0, 1}, 1983 {12, 2, 2, 0, 1}, 1984 {12, 2, 2, 0, 1}, 1985}; 1986 1987static const struct rtw_rqpn rqpn_table_8723d[] = { 1988 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1989 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1990 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1991 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1992 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1993 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1994 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1995 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 1996 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1997 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1998 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1999 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2000 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2001 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2002 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2003}; 2004 2005static const struct rtw_intf_phy_para pcie_gen1_param_8723d[] = { 2006 {0x0008, 0x4a22, 2007 RTW_IP_SEL_PHY, 2008 RTW_INTF_PHY_CUT_ALL, 2009 RTW_INTF_PHY_PLATFORM_ALL}, 2010 {0x0009, 0x1000, 2011 RTW_IP_SEL_PHY, 2012 ~(RTW_INTF_PHY_CUT_A | RTW_INTF_PHY_CUT_B), 2013 RTW_INTF_PHY_PLATFORM_ALL}, 2014 {0xFFFF, 0x0000, 2015 RTW_IP_SEL_PHY, 2016 RTW_INTF_PHY_CUT_ALL, 2017 RTW_INTF_PHY_PLATFORM_ALL}, 2018}; 2019 2020static const struct rtw_intf_phy_para_table phy_para_table_8723d = { 2021 .gen1_para = pcie_gen1_param_8723d, 2022 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8723d), 2023}; 2024 2025static const u8 rtw8723d_pwrtrk_2gb_n[] = { 2026 0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 2027 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10 2028}; 2029 2030static const u8 rtw8723d_pwrtrk_2gb_p[] = { 2031 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 2032 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10 2033}; 2034 2035static const u8 rtw8723d_pwrtrk_2ga_n[] = { 2036 0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 2037 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10 2038}; 2039 2040static const u8 rtw8723d_pwrtrk_2ga_p[] = { 2041 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 2042 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10 2043}; 2044 2045static const u8 rtw8723d_pwrtrk_2g_cck_b_n[] = { 2046 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 2047 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11 2048}; 2049 2050static const u8 rtw8723d_pwrtrk_2g_cck_b_p[] = { 2051 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 2052 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11 2053}; 2054 2055static const u8 rtw8723d_pwrtrk_2g_cck_a_n[] = { 2056 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 2057 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11 2058}; 2059 2060static const u8 rtw8723d_pwrtrk_2g_cck_a_p[] = { 2061 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 2062 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11 2063}; 2064 2065static const s8 rtw8723d_pwrtrk_xtal_n[] = { 2066 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2067 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 2068}; 2069 2070static const s8 rtw8723d_pwrtrk_xtal_p[] = { 2071 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2072 0, -10, -12, -14, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16 2073}; 2074 2075static const struct rtw_pwr_track_tbl rtw8723d_rtw_pwr_track_tbl = { 2076 .pwrtrk_2gb_n = rtw8723d_pwrtrk_2gb_n, 2077 .pwrtrk_2gb_p = rtw8723d_pwrtrk_2gb_p, 2078 .pwrtrk_2ga_n = rtw8723d_pwrtrk_2ga_n, 2079 .pwrtrk_2ga_p = rtw8723d_pwrtrk_2ga_p, 2080 .pwrtrk_2g_cckb_n = rtw8723d_pwrtrk_2g_cck_b_n, 2081 .pwrtrk_2g_cckb_p = rtw8723d_pwrtrk_2g_cck_b_p, 2082 .pwrtrk_2g_ccka_n = rtw8723d_pwrtrk_2g_cck_a_n, 2083 .pwrtrk_2g_ccka_p = rtw8723d_pwrtrk_2g_cck_a_p, 2084 .pwrtrk_xtal_p = rtw8723d_pwrtrk_xtal_p, 2085 .pwrtrk_xtal_n = rtw8723d_pwrtrk_xtal_n, 2086}; 2087 2088static const struct rtw_rfe_def rtw8723d_rfe_defs[] = { 2089 [0] = { .phy_pg_tbl = &rtw8723d_bb_pg_tbl, 2090 .txpwr_lmt_tbl = &rtw8723d_txpwr_lmt_tbl, 2091 .pwr_track_tbl = &rtw8723d_rtw_pwr_track_tbl, }, 2092}; 2093 2094static const struct rtw_reg_domain coex_info_hw_regs_8723d[] = { 2095 {0x948, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2096 {0x67, BIT(7), RTW_REG_DOMAIN_MAC8}, 2097 {0, 0, RTW_REG_DOMAIN_NL}, 2098 {0x964, BIT(1), RTW_REG_DOMAIN_MAC8}, 2099 {0x864, BIT(0), RTW_REG_DOMAIN_MAC8}, 2100 {0xab7, BIT(5), RTW_REG_DOMAIN_MAC8}, 2101 {0xa01, BIT(7), RTW_REG_DOMAIN_MAC8}, 2102 {0, 0, RTW_REG_DOMAIN_NL}, 2103 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2104 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2105 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 2106 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2107 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 2108 {0, 0, RTW_REG_DOMAIN_NL}, 2109 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 2110 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 2111 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2112 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2113 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 2114}; 2115 2116const struct rtw_chip_info rtw8723d_hw_spec = { 2117 .ops = &rtw8723d_ops, 2118 .id = RTW_CHIP_TYPE_8723D, 2119 .fw_name = "rtw88/rtw8723d_fw.bin", 2120 .wlan_cpu = RTW_WCPU_8051, 2121 .tx_pkt_desc_sz = 40, 2122 .tx_buf_desc_sz = 16, 2123 .rx_pkt_desc_sz = 24, 2124 .rx_buf_desc_sz = 8, 2125 .phy_efuse_size = 512, 2126 .log_efuse_size = 512, 2127 .ptct_efuse_size = 96 + 1, 2128 .txff_size = 32768, 2129 .rxff_size = 16384, 2130 .rsvd_drv_pg_num = 8, 2131 .txgi_factor = 1, 2132 .is_pwr_by_rate_dec = true, 2133 .max_power_index = 0x3f, 2134 .csi_buf_pg_num = 0, 2135 .band = RTW_BAND_2G, 2136 .page_size = TX_PAGE_SIZE, 2137 .dig_min = 0x20, 2138 .usb_tx_agg_desc_num = 1, 2139 .hw_feature_report = true, 2140 .c2h_ra_report_size = 7, 2141 .old_datarate_fb_limit = true, 2142 .ht_supported = true, 2143 .vht_supported = false, 2144 .lps_deep_mode_supported = 0, 2145 .sys_func_en = 0xFD, 2146 .pwr_on_seq = card_enable_flow_8723d, 2147 .pwr_off_seq = card_disable_flow_8723d, 2148 .page_table = page_table_8723d, 2149 .rqpn_table = rqpn_table_8723d, 2150 .prioq_addrs = &rtw8723x_common.prioq_addrs, 2151 .intf_table = &phy_para_table_8723d, 2152 .dig = rtw8723x_common.dig, 2153 .dig_cck = rtw8723x_common.dig_cck, 2154 .rf_sipi_addr = {0x840, 0x844}, 2155 .rf_sipi_read_addr = rtw8723x_common.rf_sipi_addr, 2156 .fix_rf_phy_num = 2, 2157 .ltecoex_addr = &rtw8723x_common.ltecoex_addr, 2158 .mac_tbl = &rtw8723d_mac_tbl, 2159 .agc_tbl = &rtw8723d_agc_tbl, 2160 .bb_tbl = &rtw8723d_bb_tbl, 2161 .rf_tbl = {&rtw8723d_rf_a_tbl}, 2162 .rfe_defs = rtw8723d_rfe_defs, 2163 .rfe_defs_size = ARRAY_SIZE(rtw8723d_rfe_defs), 2164 .rx_ldpc = false, 2165 .iqk_threshold = 8, 2166 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, 2167 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN, 2168 2169 .coex_para_ver = 0x2007022f, 2170 .bt_desired_ver = 0x2f, 2171 .scbd_support = true, 2172 .new_scbd10_def = true, 2173 .ble_hid_profile_support = false, 2174 .wl_mimo_ps_support = false, 2175 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 2176 .bt_rssi_type = COEX_BTRSSI_RATIO, 2177 .ant_isolation = 15, 2178 .rssi_tolerance = 2, 2179 .wl_rssi_step = wl_rssi_step_8723d, 2180 .bt_rssi_step = bt_rssi_step_8723d, 2181 .table_sant_num = ARRAY_SIZE(table_sant_8723d), 2182 .table_sant = table_sant_8723d, 2183 .table_nsant_num = ARRAY_SIZE(table_nsant_8723d), 2184 .table_nsant = table_nsant_8723d, 2185 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8723d), 2186 .tdma_sant = tdma_sant_8723d, 2187 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8723d), 2188 .tdma_nsant = tdma_nsant_8723d, 2189 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8723d), 2190 .wl_rf_para_tx = rf_para_tx_8723d, 2191 .wl_rf_para_rx = rf_para_rx_8723d, 2192 .bt_afh_span_bw20 = 0x20, 2193 .bt_afh_span_bw40 = 0x30, 2194 .afh_5g_num = ARRAY_SIZE(afh_5g_8723d), 2195 .afh_5g = afh_5g_8723d, 2196 .btg_reg = &btg_reg_8723d, 2197 2198 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8723d), 2199 .coex_info_hw_regs = coex_info_hw_regs_8723d, 2200}; 2201EXPORT_SYMBOL(rtw8723d_hw_spec); 2202 2203MODULE_FIRMWARE("rtw88/rtw8723d_fw.bin"); 2204 2205MODULE_AUTHOR("Realtek Corporation"); 2206MODULE_DESCRIPTION("Realtek 802.11n wireless 8723d driver"); 2207MODULE_LICENSE("Dual BSD/GPL");
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