FILE
rtw8703b.c
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linux-6.19.14/drivers/net/wireless/realtek/rtw88/rtw8703b.c
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* Copyright Fiona Klute <fiona.klute@gmx.de> */ 3 4#include <linux/of_net.h> 5#include "main.h" 6#include "coex.h" 7#include "debug.h" 8#include "mac.h" 9#include "phy.h" 10#include "reg.h" 11#include "rx.h" 12#include "rtw8703b.h" 13#include "rtw8703b_tables.h" 14#include "rtw8723x.h" 15 16#define BIT_MASK_TXQ_INIT (BIT(7)) 17#define WLAN_RL_VAL 0x3030 18/* disable BAR */ 19#define WLAN_BAR_VAL 0x0201ffff 20#define WLAN_PIFS_VAL 0 21#define WLAN_RX_PKT_LIMIT 0x18 22#define WLAN_SLOT_TIME 0x09 23#define WLAN_SPEC_SIFS 0x100a 24#define WLAN_MAX_AGG_NR 0x1f 25#define WLAN_AMPDU_MAX_TIME 0x70 26 27/* unit is 32us */ 28#define TBTT_PROHIBIT_SETUP_TIME 0x04 29#define TBTT_PROHIBIT_HOLD_TIME 0x80 30#define TBTT_PROHIBIT_HOLD_TIME_STOP_BCN 0x64 31 32#define TRANS_SEQ_END \ 33 0xFFFF, \ 34 RTW_PWR_CUT_ALL_MSK, \ 35 RTW_PWR_INTF_ALL_MSK, \ 36 0, \ 37 RTW_PWR_CMD_END, 0, 0 38 39/* rssi in percentage % (dbm = % - 100) */ 40/* These are used to select simple signal quality levels, might need 41 * tweaking. Same for rf_para tables below. 42 */ 43static const u8 wl_rssi_step_8703b[] = {60, 50, 44, 30}; 44static const u8 bt_rssi_step_8703b[] = {30, 30, 30, 30}; 45static const struct coex_5g_afh_map afh_5g_8703b[] = { {0, 0, 0} }; 46 47/* Actually decreasing wifi TX power/RX gain isn't implemented in 48 * rtw8703b, but hopefully adjusting the BT side helps. 49 */ 50static const struct coex_rf_para rf_para_tx_8703b[] = { 51 {0, 0, false, 7}, /* for normal */ 52 {0, 10, false, 7}, /* for WL-CPT */ 53 {1, 0, true, 4}, 54 {1, 2, true, 4}, 55 {1, 10, true, 4}, 56 {1, 15, true, 4} 57}; 58 59static const struct coex_rf_para rf_para_rx_8703b[] = { 60 {0, 0, false, 7}, /* for normal */ 61 {0, 10, false, 7}, /* for WL-CPT */ 62 {1, 0, true, 5}, 63 {1, 2, true, 5}, 64 {1, 10, true, 5}, 65 {1, 15, true, 5} 66}; 67 68static const u32 rtw8703b_ofdm_swing_table[] = { 69 0x0b40002d, /* 0, -15.0dB */ 70 0x0c000030, /* 1, -14.5dB */ 71 0x0cc00033, /* 2, -14.0dB */ 72 0x0d800036, /* 3, -13.5dB */ 73 0x0e400039, /* 4, -13.0dB */ 74 0x0f00003c, /* 5, -12.5dB */ 75 0x10000040, /* 6, -12.0dB */ 76 0x11000044, /* 7, -11.5dB */ 77 0x12000048, /* 8, -11.0dB */ 78 0x1300004c, /* 9, -10.5dB */ 79 0x14400051, /* 10, -10.0dB */ 80 0x15800056, /* 11, -9.5dB */ 81 0x16c0005b, /* 12, -9.0dB */ 82 0x18000060, /* 13, -8.5dB */ 83 0x19800066, /* 14, -8.0dB */ 84 0x1b00006c, /* 15, -7.5dB */ 85 0x1c800072, /* 16, -7.0dB */ 86 0x1e400079, /* 17, -6.5dB */ 87 0x20000080, /* 18, -6.0dB */ 88 0x22000088, /* 19, -5.5dB */ 89 0x24000090, /* 20, -5.0dB */ 90 0x26000098, /* 21, -4.5dB */ 91 0x288000a2, /* 22, -4.0dB */ 92 0x2ac000ab, /* 23, -3.5dB */ 93 0x2d4000b5, /* 24, -3.0dB */ 94 0x300000c0, /* 25, -2.5dB */ 95 0x32c000cb, /* 26, -2.0dB */ 96 0x35c000d7, /* 27, -1.5dB */ 97 0x390000e4, /* 28, -1.0dB */ 98 0x3c8000f2, /* 29, -0.5dB */ 99 0x40000100, /* 30, +0dB */ 100 0x43c0010f, /* 31, +0.5dB */ 101 0x47c0011f, /* 32, +1.0dB */ 102 0x4c000130, /* 33, +1.5dB */ 103 0x50800142, /* 34, +2.0dB */ 104 0x55400155, /* 35, +2.5dB */ 105 0x5a400169, /* 36, +3.0dB */ 106 0x5fc0017f, /* 37, +3.5dB */ 107 0x65400195, /* 38, +4.0dB */ 108 0x6b8001ae, /* 39, +4.5dB */ 109 0x71c001c7, /* 40, +5.0dB */ 110 0x788001e2, /* 41, +5.5dB */ 111 0x7f8001fe /* 42, +6.0dB */ 112}; 113 114static const u32 rtw8703b_cck_pwr_regs[] = { 115 0x0a22, 0x0a23, 0x0a24, 0x0a25, 0x0a26, 0x0a27, 0x0a28, 0x0a29, 116 0x0a9a, 0x0a9b, 0x0a9c, 0x0a9d, 0x0aa0, 0x0aa1, 0x0aa2, 0x0aa3, 117}; 118 119static const u8 rtw8703b_cck_swing_table[][16] = { 120 {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 121 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ 122 {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 123 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ 124 {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 125 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ 126 {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 127 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ 128 {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 129 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ 130 {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 131 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ 132 {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 133 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ 134 {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 135 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ 136 {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 137 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ 138 {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 139 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ 140 {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 141 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ 142 {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 143 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ 144 {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 145 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ 146 {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 147 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ 148 {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 149 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ 150 {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 151 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ 152 {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 153 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ 154 {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 155 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ 156 {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 157 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ 158 {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 159 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ 160 {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 161 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ 162}; 163 164#define RTW_OFDM_SWING_TABLE_SIZE ARRAY_SIZE(rtw8703b_ofdm_swing_table) 165#define RTW_CCK_SWING_TABLE_SIZE ARRAY_SIZE(rtw8703b_cck_swing_table) 166 167static const struct rtw_pwr_seq_cmd trans_pre_enable_8703b[] = { 168 /* set up external crystal (XTAL) */ 169 {REG_PAD_CTRL1 + 2, 170 RTW_PWR_CUT_ALL_MSK, 171 RTW_PWR_INTF_ALL_MSK, 172 RTW_PWR_ADDR_MAC, 173 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 174 /* set CLK_REQ to high active */ 175 {0x0069, 176 RTW_PWR_CUT_ALL_MSK, 177 RTW_PWR_INTF_ALL_MSK, 178 RTW_PWR_ADDR_MAC, 179 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 180 /* unlock ISO/CLK/power control register */ 181 {REG_RSV_CTRL, 182 RTW_PWR_CUT_ALL_MSK, 183 RTW_PWR_INTF_ALL_MSK, 184 RTW_PWR_ADDR_MAC, 185 RTW_PWR_CMD_WRITE, 0xff, 0}, 186 {TRANS_SEQ_END}, 187}; 188 189static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8703b[] = { 190 {0x0005, 191 RTW_PWR_CUT_ALL_MSK, 192 RTW_PWR_INTF_ALL_MSK, 193 RTW_PWR_ADDR_MAC, 194 RTW_PWR_CMD_WRITE, BIT(7), 0}, 195 {TRANS_SEQ_END}, 196}; 197 198static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8703b[] = { 199 {0x0023, 200 RTW_PWR_CUT_ALL_MSK, 201 RTW_PWR_INTF_SDIO_MSK, 202 RTW_PWR_ADDR_MAC, 203 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 204 {0x0007, 205 RTW_PWR_CUT_ALL_MSK, 206 RTW_PWR_INTF_SDIO_MSK | RTW_PWR_INTF_USB_MSK, 207 RTW_PWR_ADDR_MAC, 208 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 209 {0x0006, 210 RTW_PWR_CUT_ALL_MSK, 211 RTW_PWR_INTF_ALL_MSK, 212 RTW_PWR_ADDR_MAC, 213 RTW_PWR_CMD_WRITE, BIT(0), 0}, 214 {0x0005, 215 RTW_PWR_CUT_ALL_MSK, 216 RTW_PWR_INTF_ALL_MSK, 217 RTW_PWR_ADDR_MAC, 218 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 219 {TRANS_SEQ_END}, 220}; 221 222static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8703b[] = { 223 {0x0020, 224 RTW_PWR_CUT_ALL_MSK, 225 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 226 RTW_PWR_ADDR_MAC, 227 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 228 {0x0067, 229 RTW_PWR_CUT_ALL_MSK, 230 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 231 RTW_PWR_ADDR_MAC, 232 RTW_PWR_CMD_WRITE, BIT(4), 0}, 233 {0x0001, 234 RTW_PWR_CUT_ALL_MSK, 235 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 236 RTW_PWR_ADDR_MAC, 237 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 238 {0x0000, 239 RTW_PWR_CUT_ALL_MSK, 240 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 241 RTW_PWR_ADDR_MAC, 242 RTW_PWR_CMD_WRITE, BIT(5), 0}, 243 {0x0005, 244 RTW_PWR_CUT_ALL_MSK, 245 RTW_PWR_INTF_ALL_MSK, 246 RTW_PWR_ADDR_MAC, 247 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 248 {0x0075, 249 RTW_PWR_CUT_ALL_MSK, 250 RTW_PWR_INTF_PCI_MSK, 251 RTW_PWR_ADDR_MAC, 252 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 253 {0x0004, 254 RTW_PWR_CUT_ALL_MSK, 255 RTW_PWR_INTF_PCI_MSK, 256 RTW_PWR_ADDR_MAC, 257 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 258 {0x0004, 259 RTW_PWR_CUT_ALL_MSK, 260 RTW_PWR_INTF_PCI_MSK, 261 RTW_PWR_ADDR_MAC, 262 RTW_PWR_CMD_WRITE, BIT(3), 0}, 263 /* wait for power ready */ 264 {0x0006, 265 RTW_PWR_CUT_ALL_MSK, 266 RTW_PWR_INTF_ALL_MSK, 267 RTW_PWR_ADDR_MAC, 268 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 269 {0x0075, 270 RTW_PWR_CUT_ALL_MSK, 271 RTW_PWR_INTF_PCI_MSK, 272 RTW_PWR_ADDR_MAC, 273 RTW_PWR_CMD_WRITE, BIT(0), 0}, 274 {0x0006, 275 RTW_PWR_CUT_ALL_MSK, 276 RTW_PWR_INTF_ALL_MSK, 277 RTW_PWR_ADDR_MAC, 278 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 279 {0x0005, 280 RTW_PWR_CUT_ALL_MSK, 281 RTW_PWR_INTF_ALL_MSK, 282 RTW_PWR_ADDR_MAC, 283 RTW_PWR_CMD_WRITE, BIT(7), 0}, 284 {0x0005, 285 RTW_PWR_CUT_ALL_MSK, 286 RTW_PWR_INTF_ALL_MSK, 287 RTW_PWR_ADDR_MAC, 288 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 289 {0x0005, 290 RTW_PWR_CUT_ALL_MSK, 291 RTW_PWR_INTF_ALL_MSK, 292 RTW_PWR_ADDR_MAC, 293 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 294 {0x0005, 295 RTW_PWR_CUT_ALL_MSK, 296 RTW_PWR_INTF_ALL_MSK, 297 RTW_PWR_ADDR_MAC, 298 RTW_PWR_CMD_POLLING, BIT(0), 0}, 299 {0x0010, 300 RTW_PWR_CUT_ALL_MSK, 301 RTW_PWR_INTF_ALL_MSK, 302 RTW_PWR_ADDR_MAC, 303 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 304 {0x0049, 305 RTW_PWR_CUT_ALL_MSK, 306 RTW_PWR_INTF_ALL_MSK, 307 RTW_PWR_ADDR_MAC, 308 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 309 {0x0063, 310 RTW_PWR_CUT_ALL_MSK, 311 RTW_PWR_INTF_ALL_MSK, 312 RTW_PWR_ADDR_MAC, 313 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 314 {0x0062, 315 RTW_PWR_CUT_ALL_MSK, 316 RTW_PWR_INTF_ALL_MSK, 317 RTW_PWR_ADDR_MAC, 318 RTW_PWR_CMD_WRITE, BIT(1), 0}, 319 {0x0058, 320 RTW_PWR_CUT_ALL_MSK, 321 RTW_PWR_INTF_ALL_MSK, 322 RTW_PWR_ADDR_MAC, 323 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 324 {0x005A, 325 RTW_PWR_CUT_ALL_MSK, 326 RTW_PWR_INTF_ALL_MSK, 327 RTW_PWR_ADDR_MAC, 328 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 329 {0x0068, 330 RTW_PWR_CUT_TEST_MSK, 331 RTW_PWR_INTF_ALL_MSK, 332 RTW_PWR_ADDR_MAC, 333 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 334 {0x0069, 335 RTW_PWR_CUT_ALL_MSK, 336 RTW_PWR_INTF_ALL_MSK, 337 RTW_PWR_ADDR_MAC, 338 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 339 {TRANS_SEQ_END}, 340}; 341 342static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8703b[] = { 343 {0x001f, 344 RTW_PWR_CUT_ALL_MSK, 345 RTW_PWR_INTF_ALL_MSK, 346 RTW_PWR_ADDR_MAC, 347 RTW_PWR_CMD_WRITE, 0xff, 0}, 348 {0x0049, 349 RTW_PWR_CUT_ALL_MSK, 350 RTW_PWR_INTF_ALL_MSK, 351 RTW_PWR_ADDR_MAC, 352 RTW_PWR_CMD_WRITE, BIT(1), 0}, 353 {0x0006, 354 RTW_PWR_CUT_ALL_MSK, 355 RTW_PWR_INTF_ALL_MSK, 356 RTW_PWR_ADDR_MAC, 357 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 358 {0x0005, 359 RTW_PWR_CUT_ALL_MSK, 360 RTW_PWR_INTF_ALL_MSK, 361 RTW_PWR_ADDR_MAC, 362 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 363 {0x0005, 364 RTW_PWR_CUT_ALL_MSK, 365 RTW_PWR_INTF_ALL_MSK, 366 RTW_PWR_ADDR_MAC, 367 RTW_PWR_CMD_POLLING, BIT(1), 0}, 368 {0x0010, 369 RTW_PWR_CUT_ALL_MSK, 370 RTW_PWR_INTF_ALL_MSK, 371 RTW_PWR_ADDR_MAC, 372 RTW_PWR_CMD_WRITE, BIT(6), 0}, 373 {0x0000, 374 RTW_PWR_CUT_ALL_MSK, 375 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 376 RTW_PWR_ADDR_MAC, 377 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 378 {0x0020, 379 RTW_PWR_CUT_ALL_MSK, 380 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 381 RTW_PWR_ADDR_MAC, 382 RTW_PWR_CMD_WRITE, BIT(0), 0}, 383 {TRANS_SEQ_END}, 384}; 385 386static const struct rtw_pwr_seq_cmd trans_act_to_reset_mcu_8703b[] = { 387 {REG_SYS_FUNC_EN + 1, 388 RTW_PWR_CUT_ALL_MSK, 389 RTW_PWR_INTF_SDIO_MSK, 390 RTW_PWR_ADDR_MAC, 391 RTW_PWR_CMD_WRITE, BIT_FEN_CPUEN, 0}, 392 /* reset MCU ready */ 393 {REG_MCUFW_CTRL, 394 RTW_PWR_CUT_ALL_MSK, 395 RTW_PWR_INTF_SDIO_MSK, 396 RTW_PWR_ADDR_MAC, 397 RTW_PWR_CMD_WRITE, 0xff, 0}, 398 /* reset MCU IO wrapper */ 399 {REG_RSV_CTRL + 1, 400 RTW_PWR_CUT_ALL_MSK, 401 RTW_PWR_INTF_SDIO_MSK, 402 RTW_PWR_ADDR_MAC, 403 RTW_PWR_CMD_WRITE, BIT(0), 0}, 404 {REG_RSV_CTRL + 1, 405 RTW_PWR_CUT_ALL_MSK, 406 RTW_PWR_INTF_SDIO_MSK, 407 RTW_PWR_ADDR_MAC, 408 RTW_PWR_CMD_WRITE, BIT(0), 1}, 409 {TRANS_SEQ_END}, 410}; 411 412static const struct rtw_pwr_seq_cmd trans_act_to_lps_8703b[] = { 413 {0x0301, 414 RTW_PWR_CUT_ALL_MSK, 415 RTW_PWR_INTF_ALL_MSK, 416 RTW_PWR_ADDR_MAC, 417 RTW_PWR_CMD_WRITE, 0xff, 0xff}, 418 {0x0522, 419 RTW_PWR_CUT_ALL_MSK, 420 RTW_PWR_INTF_ALL_MSK, 421 RTW_PWR_ADDR_MAC, 422 RTW_PWR_CMD_WRITE, 0xff, 0xff}, 423 {0x05f8, 424 RTW_PWR_CUT_ALL_MSK, 425 RTW_PWR_INTF_ALL_MSK, 426 RTW_PWR_ADDR_MAC, 427 RTW_PWR_CMD_POLLING, 0xff, 0}, 428 {0x05f9, 429 RTW_PWR_CUT_ALL_MSK, 430 RTW_PWR_INTF_ALL_MSK, 431 RTW_PWR_ADDR_MAC, 432 RTW_PWR_CMD_POLLING, 0xff, 0}, 433 {0x05fa, 434 RTW_PWR_CUT_ALL_MSK, 435 RTW_PWR_INTF_ALL_MSK, 436 RTW_PWR_ADDR_MAC, 437 RTW_PWR_CMD_POLLING, 0xff, 0}, 438 {0x05fb, 439 RTW_PWR_CUT_ALL_MSK, 440 RTW_PWR_INTF_ALL_MSK, 441 RTW_PWR_ADDR_MAC, 442 RTW_PWR_CMD_POLLING, 0xff, 0}, 443 {0x0002, 444 RTW_PWR_CUT_ALL_MSK, 445 RTW_PWR_INTF_ALL_MSK, 446 RTW_PWR_ADDR_MAC, 447 RTW_PWR_CMD_WRITE, BIT(0), 0}, 448 {0x0002, 449 RTW_PWR_CUT_ALL_MSK, 450 RTW_PWR_INTF_ALL_MSK, 451 RTW_PWR_ADDR_MAC, 452 RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US}, 453 {0x0002, 454 RTW_PWR_CUT_ALL_MSK, 455 RTW_PWR_INTF_ALL_MSK, 456 RTW_PWR_ADDR_MAC, 457 RTW_PWR_CMD_WRITE, BIT(1), 0}, 458 {0x0100, 459 RTW_PWR_CUT_ALL_MSK, 460 RTW_PWR_INTF_ALL_MSK, 461 RTW_PWR_ADDR_MAC, 462 RTW_PWR_CMD_WRITE, 0xff, 0x03}, 463 {0x0101, 464 RTW_PWR_CUT_ALL_MSK, 465 RTW_PWR_INTF_ALL_MSK, 466 RTW_PWR_ADDR_MAC, 467 RTW_PWR_CMD_WRITE, BIT(1), 0}, 468 {0x0093, 469 RTW_PWR_CUT_ALL_MSK, 470 RTW_PWR_INTF_SDIO_MSK, 471 RTW_PWR_ADDR_MAC, 472 RTW_PWR_CMD_WRITE, 0xff, 0}, 473 {0x0553, 474 RTW_PWR_CUT_ALL_MSK, 475 RTW_PWR_INTF_ALL_MSK, 476 RTW_PWR_ADDR_MAC, 477 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 478 {TRANS_SEQ_END}, 479}; 480 481static const struct rtw_pwr_seq_cmd * const card_enable_flow_8703b[] = { 482 trans_pre_enable_8703b, 483 trans_carddis_to_cardemu_8703b, 484 trans_cardemu_to_act_8703b, 485 NULL 486}; 487 488static const struct rtw_pwr_seq_cmd * const card_disable_flow_8703b[] = { 489 trans_act_to_lps_8703b, 490 trans_act_to_reset_mcu_8703b, 491 trans_act_to_cardemu_8703b, 492 trans_cardemu_to_carddis_8703b, 493 NULL 494}; 495 496static const struct rtw_page_table page_table_8703b[] = { 497 {12, 2, 2, 0, 1}, 498 {12, 2, 2, 0, 1}, 499 {12, 2, 2, 0, 1}, 500 {12, 2, 2, 0, 1}, 501 {12, 2, 2, 0, 1}, 502}; 503 504static const struct rtw_rqpn rqpn_table_8703b[] = { 505 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 506 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 507 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 508 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 509 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 510 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 511 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 512 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 513 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 514 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 515 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 516 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 517 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 518 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 519 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 520}; 521 522static void try_mac_from_devicetree(struct rtw_dev *rtwdev) 523{ 524 struct device_node *node = rtwdev->dev->of_node; 525 struct rtw_efuse *efuse = &rtwdev->efuse; 526 int ret; 527 528 if (node) { 529 ret = of_get_mac_address(node, efuse->addr); 530 if (ret == 0) { 531 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 532 "got wifi mac address from DT: %pM\n", 533 efuse->addr); 534 } 535 } 536} 537 538static int rtw8703b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 539{ 540 struct rtw_efuse *efuse = &rtwdev->efuse; 541 int ret; 542 543 ret = rtw8723x_read_efuse(rtwdev, log_map); 544 if (ret != 0) 545 return ret; 546 547 if (!is_valid_ether_addr(efuse->addr)) 548 try_mac_from_devicetree(rtwdev); 549 550 return 0; 551} 552 553static void rtw8703b_pwrtrack_init(struct rtw_dev *rtwdev) 554{ 555 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 556 u8 path; 557 558 /* TODO: The vendor driver selects these using tables in 559 * halrf_powertracking_ce.c, functions are called 560 * get_swing_index and get_cck_swing_index. There the current 561 * fixed values are only the defaults in case no match is 562 * found. 563 */ 564 dm_info->default_ofdm_index = 30; 565 dm_info->default_cck_index = 20; 566 567 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { 568 ewma_thermal_init(&dm_info->avg_thermal[path]); 569 dm_info->delta_power_index[path] = 0; 570 } 571 dm_info->pwr_trk_triggered = false; 572 dm_info->pwr_trk_init_trigger = true; 573 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 574 dm_info->txagc_remnant_cck = 0; 575 dm_info->txagc_remnant_ofdm[RF_PATH_A] = 0; 576} 577 578static void rtw8703b_phy_set_param(struct rtw_dev *rtwdev) 579{ 580 u8 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; 581 582 /* power on BB/RF domain */ 583 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, 584 BIT_FEN_EN_25_1 | BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 585 rtw_write8_set(rtwdev, REG_RF_CTRL, 586 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 587 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, 0x0780); 588 rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80); 589 590 rtw_phy_load_tables(rtwdev); 591 592 rtw_write32_clr(rtwdev, REG_RCR, BIT_RCR_ADF); 593 /* 0xff is from vendor driver, rtw8723d uses 594 * BIT_HIQ_NO_LMT_EN_ROOT. Comment in vendor driver: "Packet 595 * in Hi Queue Tx immediately". I wonder if setting all bits 596 * is really necessary. 597 */ 598 rtw_write8_set(rtwdev, REG_HIQ_NO_LMT_EN, 0xff); 599 rtw_write16_set(rtwdev, REG_AFE_CTRL_4, BIT_CK320M_AFE_EN | BIT_EN_SYN); 600 601 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, 602 xtal_cap | (xtal_cap << 6)); 603 rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN); 604 605 /* Init EDCA */ 606 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SPEC_SIFS); 607 rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, WLAN_SPEC_SIFS); 608 rtw_write16(rtwdev, REG_SIFS, WLAN_SPEC_SIFS); /* CCK */ 609 rtw_write16(rtwdev, REG_SIFS + 2, WLAN_SPEC_SIFS); /* OFDM */ 610 /* TXOP */ 611 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, 0x002FA226); 612 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, 0x005EA324); 613 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, 0x005EA42B); 614 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, 0x0000A44F); 615 616 /* Init retry */ 617 rtw_write8(rtwdev, REG_ACKTO, 0x40); 618 619 /* Set up RX aggregation. sdio.c also sets DMA mode, but not 620 * the burst parameters. 621 */ 622 rtw_write8(rtwdev, REG_RXDMA_MODE, 623 BIT_DMA_MODE | 624 FIELD_PREP_CONST(BIT_MASK_AGG_BURST_NUM, AGG_BURST_NUM) | 625 FIELD_PREP_CONST(BIT_MASK_AGG_BURST_SIZE, AGG_BURST_SIZE)); 626 627 /* Init beacon parameters */ 628 rtw_write8(rtwdev, REG_BCN_CTRL, 629 BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION | BIT_EN_TXBCN_RPT); 630 rtw_write8(rtwdev, REG_TBTT_PROHIBIT, TBTT_PROHIBIT_SETUP_TIME); 631 rtw_write8(rtwdev, REG_TBTT_PROHIBIT + 1, 632 TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF); 633 rtw_write8(rtwdev, REG_TBTT_PROHIBIT + 2, 634 (rtw_read8(rtwdev, REG_TBTT_PROHIBIT + 2) & 0xF0) 635 | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8)); 636 637 /* configure packet burst */ 638 rtw_write8_set(rtwdev, REG_SINGLE_AMPDU_CTRL, BIT_EN_SINGLE_APMDU); 639 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RX_PKT_LIMIT); 640 rtw_write8(rtwdev, REG_MAX_AGGR_NUM, WLAN_MAX_AGG_NR); 641 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_VAL); 642 rtw_write8_clr(rtwdev, REG_FWHW_TXQ_CTRL, BIT_MASK_TXQ_INIT); 643 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, WLAN_AMPDU_MAX_TIME); 644 645 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 646 rtw_write16(rtwdev, REG_RETRY_LIMIT, WLAN_RL_VAL); 647 rtw_write32(rtwdev, REG_BAR_MODE_CTRL, WLAN_BAR_VAL); 648 rtw_write16(rtwdev, REG_ATIMWND, 0x2); 649 650 rtw_phy_init(rtwdev); 651 652 if (rtw_read32_mask(rtwdev, REG_BB_AMP, BIT_MASK_RX_LNA) != 0) { 653 rtwdev->dm_info.rx_cck_agc_report_type = 1; 654 } else { 655 rtwdev->dm_info.rx_cck_agc_report_type = 0; 656 rtw_warn(rtwdev, "unexpected cck agc report type"); 657 } 658 659 rtw8723x_lck(rtwdev); 660 661 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); 662 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20); 663 664 rtw8703b_pwrtrack_init(rtwdev); 665} 666 667static bool rtw8703b_check_spur_ov_thres(struct rtw_dev *rtwdev, 668 u32 freq, u32 thres) 669{ 670 bool ret = false; 671 672 rtw_write32(rtwdev, REG_ANALOG_P4, DIS_3WIRE); 673 rtw_write32(rtwdev, REG_PSDFN, freq); 674 rtw_write32(rtwdev, REG_PSDFN, START_PSD | freq); 675 676 msleep(30); 677 if (rtw_read32(rtwdev, REG_PSDRPT) >= thres) 678 ret = true; 679 680 rtw_write32(rtwdev, REG_PSDFN, freq); 681 rtw_write32(rtwdev, REG_ANALOG_P4, EN_3WIRE); 682 683 return ret; 684} 685 686static void rtw8703b_cfg_notch(struct rtw_dev *rtwdev, u8 channel, bool notch) 687{ 688 if (!notch) { 689 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f); 690 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); 691 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 692 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 693 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 694 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 695 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); 696 return; 697 } 698 699 switch (channel) { 700 case 5: 701 fallthrough; 702 case 13: 703 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb); 704 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 705 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x06000000); 706 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 707 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 708 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 709 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 710 break; 711 case 6: 712 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x4); 713 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 714 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000600); 715 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 716 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 717 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 718 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 719 break; 720 case 7: 721 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x3); 722 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 723 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 724 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 725 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 726 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x06000000); 727 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 728 break; 729 case 8: 730 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xa); 731 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 732 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 733 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 734 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 735 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000380); 736 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 737 break; 738 case 14: 739 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5); 740 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 741 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 742 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 743 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 744 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00180000); 745 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 746 break; 747 default: 748 rtw_warn(rtwdev, 749 "Bug: Notch filter enable called for channel %u!", 750 channel); 751 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); 752 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); 753 break; 754 } 755} 756 757static void rtw8703b_spur_cal(struct rtw_dev *rtwdev, u8 channel) 758{ 759 bool notch; 760 u32 freq; 761 762 if (channel == 5) { 763 freq = FREQ_CH5; 764 } else if (channel == 6) { 765 freq = FREQ_CH6; 766 } else if (channel == 7) { 767 freq = FREQ_CH7; 768 } else if (channel == 8) { 769 freq = FREQ_CH8; 770 } else if (channel == 13) { 771 freq = FREQ_CH13; 772 } else if (channel == 14) { 773 freq = FREQ_CH14; 774 } else { 775 rtw8703b_cfg_notch(rtwdev, channel, false); 776 return; 777 } 778 779 notch = rtw8703b_check_spur_ov_thres(rtwdev, freq, SPUR_THRES); 780 rtw8703b_cfg_notch(rtwdev, channel, notch); 781} 782 783static void rtw8703b_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 784{ 785 u32 rf_cfgch_a; 786 u32 rf_cfgch_b; 787 /* default value for 20M */ 788 u32 rf_rck = 0x00000C08; 789 790 rf_cfgch_a = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); 791 rf_cfgch_b = rtw_read_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK); 792 793 rf_cfgch_a &= ~RFCFGCH_CHANNEL_MASK; 794 rf_cfgch_b &= ~RFCFGCH_CHANNEL_MASK; 795 rf_cfgch_a |= (channel & RFCFGCH_CHANNEL_MASK); 796 rf_cfgch_b |= (channel & RFCFGCH_CHANNEL_MASK); 797 798 rf_cfgch_a &= ~RFCFGCH_BW_MASK; 799 switch (bw) { 800 case RTW_CHANNEL_WIDTH_20: 801 rf_cfgch_a |= RFCFGCH_BW_20M; 802 break; 803 case RTW_CHANNEL_WIDTH_40: 804 rf_cfgch_a |= RFCFGCH_BW_40M; 805 rf_rck = 0x00000C4C; 806 break; 807 default: 808 break; 809 } 810 811 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_cfgch_a); 812 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_cfgch_b); 813 814 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK1, RFREG_MASK, rf_rck); 815 rtw8703b_spur_cal(rtwdev, channel); 816} 817 818#define CCK_DFIR_NR_8703B 2 819static const struct rtw_backup_info cck_dfir_cfg[][CCK_DFIR_NR_8703B] = { 820 [0] = { 821 { .len = 4, .reg = REG_CCK_TXSF2, .val = 0x5A7DA0BD }, 822 { .len = 4, .reg = REG_CCK_DBG, .val = 0x0000223B }, 823 }, 824 [1] = { 825 { .len = 4, .reg = REG_CCK_TXSF2, .val = 0x00000000 }, 826 { .len = 4, .reg = REG_CCK_DBG, .val = 0x00000000 }, 827 }, 828}; 829 830static void rtw8703b_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 831 u8 primary_ch_idx) 832{ 833 const struct rtw_backup_info *cck_dfir; 834 int i; 835 836 cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1]; 837 838 for (i = 0; i < CCK_DFIR_NR_8703B; i++, cck_dfir++) 839 rtw_write32(rtwdev, cck_dfir->reg, cck_dfir->val); 840 841 switch (bw) { 842 case RTW_CHANNEL_WIDTH_20: 843 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0); 844 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0); 845 rtw_write32_mask(rtwdev, REG_OFDM0_TX_PSD_NOISE, 846 GENMASK(31, 30), 0x0); 847 rtw_write32(rtwdev, REG_BBRX_DFIR, 0x4A880000); 848 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x19F60000); 849 break; 850 case RTW_CHANNEL_WIDTH_40: 851 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1); 852 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1); 853 rtw_write32(rtwdev, REG_BBRX_DFIR, 0x40100000); 854 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x51F60000); 855 rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND, 856 primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0); 857 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, 0xC00, 858 primary_ch_idx == RTW_SC_20_UPPER ? 2 : 1); 859 860 rtw_write32_mask(rtwdev, REG_BB_PWR_SAV5_11N, GENMASK(27, 26), 861 primary_ch_idx == RTW_SC_20_UPPER ? 1 : 2); 862 break; 863 default: 864 break; 865 } 866} 867 868static void rtw8703b_set_channel(struct rtw_dev *rtwdev, u8 channel, 869 u8 bw, u8 primary_chan_idx) 870{ 871 rtw8703b_set_channel_rf(rtwdev, channel, bw); 872 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 873 rtw8703b_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 874} 875 876/* Not all indices are valid, based on available data. None of the 877 * known valid values are positive, so use 0x7f as "invalid". 878 */ 879#define LNA_IDX_INVALID 0x7f 880static const s8 lna_gain_table[16] = { 881 -2, LNA_IDX_INVALID, LNA_IDX_INVALID, LNA_IDX_INVALID, 882 -6, LNA_IDX_INVALID, LNA_IDX_INVALID, -19, 883 -32, LNA_IDX_INVALID, -36, -42, 884 LNA_IDX_INVALID, LNA_IDX_INVALID, LNA_IDX_INVALID, -48, 885}; 886 887static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx) 888{ 889 s8 lna_gain = 0; 890 891 if (lna_idx < ARRAY_SIZE(lna_gain_table)) 892 lna_gain = lna_gain_table[lna_idx]; 893 894 if (lna_gain >= 0) { 895 rtw_warn(rtwdev, "incorrect lna index (%d)\n", lna_idx); 896 return -120; 897 } 898 899 return lna_gain - 2 * vga_idx; 900} 901 902static void query_phy_status_cck(struct rtw_dev *rtwdev, u8 *phy_raw, 903 struct rtw_rx_pkt_stat *pkt_stat) 904{ 905 struct phy_status_8703b *phy_status = (struct phy_status_8703b *)phy_raw; 906 u8 vga_idx = phy_status->cck_agc_rpt_ofdm_cfosho_a & VGA_BITS; 907 u8 lna_idx = phy_status->cck_agc_rpt_ofdm_cfosho_a & LNA_L_BITS; 908 s8 rx_power; 909 910 if (rtwdev->dm_info.rx_cck_agc_report_type == 1) 911 lna_idx = FIELD_PREP(BIT_LNA_H_MASK, 912 phy_status->cck_rpt_b_ofdm_cfosho_b & LNA_H_BIT) 913 | FIELD_PREP(BIT_LNA_L_MASK, lna_idx); 914 else 915 lna_idx = FIELD_PREP(BIT_LNA_L_MASK, lna_idx); 916 rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx); 917 918 pkt_stat->rx_power[RF_PATH_A] = rx_power; 919 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 920 rtwdev->dm_info.rssi[RF_PATH_A] = pkt_stat->rssi; 921 pkt_stat->signal_power = rx_power; 922} 923 924static void query_phy_status_ofdm(struct rtw_dev *rtwdev, u8 *phy_raw, 925 struct rtw_rx_pkt_stat *pkt_stat) 926{ 927 struct phy_status_8703b *phy_status = (struct phy_status_8703b *)phy_raw; 928 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 929 s8 val_s8; 930 931 val_s8 = phy_status->path_agc[RF_PATH_A].gain & 0x3F; 932 pkt_stat->rx_power[RF_PATH_A] = (val_s8 * 2) - 110; 933 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 934 pkt_stat->rx_snr[RF_PATH_A] = (s8)(phy_status->path_rxsnr[RF_PATH_A] / 2); 935 936 /* signal power reported by HW */ 937 val_s8 = phy_status->cck_sig_qual_ofdm_pwdb_all >> 1; 938 pkt_stat->signal_power = (val_s8 & 0x7f) - 110; 939 940 pkt_stat->rx_evm[RF_PATH_A] = phy_status->stream_rxevm[RF_PATH_A]; 941 pkt_stat->cfo_tail[RF_PATH_A] = phy_status->path_cfotail[RF_PATH_A]; 942 943 dm_info->curr_rx_rate = pkt_stat->rate; 944 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 945 dm_info->rx_snr[RF_PATH_A] = pkt_stat->rx_snr[RF_PATH_A] >> 1; 946 /* convert to KHz (used only for debugfs) */ 947 dm_info->cfo_tail[RF_PATH_A] = (pkt_stat->cfo_tail[RF_PATH_A] * 5) >> 1; 948 949 /* (EVM value as s8 / 2) is dbm, should usually be in -33 to 0 950 * range. rx_evm_dbm needs the absolute (positive) value. 951 */ 952 val_s8 = (s8)pkt_stat->rx_evm[RF_PATH_A]; 953 val_s8 = clamp_t(s8, -val_s8 >> 1, 0, 64); 954 val_s8 &= 0x3F; /* 64->0: second path of 1SS rate is 64 */ 955 dm_info->rx_evm_dbm[RF_PATH_A] = val_s8; 956} 957 958static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 959 struct rtw_rx_pkt_stat *pkt_stat) 960{ 961 if (pkt_stat->rate <= DESC_RATE11M) 962 query_phy_status_cck(rtwdev, phy_status, pkt_stat); 963 else 964 query_phy_status_ofdm(rtwdev, phy_status, pkt_stat); 965} 966 967#define ADDA_ON_VAL_8703B 0x03c00014 968 969static 970void rtw8703b_iqk_config_mac(struct rtw_dev *rtwdev, 971 const struct rtw8723x_iqk_backup_regs *backup) 972{ 973 rtw_write8(rtwdev, rtw8723x_common.iqk_mac8_regs[0], 0x3F); 974 for (int i = 1; i < RTW8723X_IQK_MAC8_REG_NUM; i++) 975 rtw_write8(rtwdev, rtw8723x_common.iqk_mac8_regs[i], 976 backup->mac8[i] & (~BIT(3))); 977} 978 979#define IQK_LTE_WRITE_VAL_8703B 0x00007700 980#define IQK_DELAY_TIME_8703B 4 981 982static void rtw8703b_iqk_one_shot(struct rtw_dev *rtwdev, bool tx) 983{ 984 u32 regval; 985 ktime_t t; 986 s64 dur; 987 int ret; 988 989 /* enter IQK mode */ 990 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); 991 rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8703B); 992 993 /* One shot, LOK & IQK */ 994 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf9000000); 995 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000); 996 997 t = ktime_get(); 998 msleep(IQK_DELAY_TIME_8703B); 999 ret = read_poll_timeout(rtw_read32, regval, regval != 0, 1000, 1000 100000, false, rtwdev, 1001 REG_IQK_RDY); 1002 dur = ktime_us_delta(ktime_get(), t); 1003 1004 if (ret) 1005 rtw_warn(rtwdev, "[IQK] %s timed out after %lldus!\n", 1006 tx ? "TX" : "RX", dur); 1007 else 1008 rtw_dbg(rtwdev, RTW_DBG_RFK, 1009 "[IQK] %s done after %lldus\n", 1010 tx ? "TX" : "RX", dur); 1011} 1012 1013static void rtw8703b_iqk_txrx_path_post(struct rtw_dev *rtwdev, 1014 const struct rtw8723x_iqk_backup_regs *backup) 1015{ 1016 rtw8723x_iqk_restore_lte_path_gnt(rtwdev, backup); 1017 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup->bb_sel_btg); 1018 1019 /* leave IQK mode */ 1020 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1021 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x0); 1022} 1023 1024static u8 rtw8703b_iqk_check_tx_failed(struct rtw_dev *rtwdev) 1025{ 1026 s32 tx_x, tx_y; 1027 u32 tx_fail; 1028 1029 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n", 1030 rtw_read32(rtwdev, REG_IQK_RES_RY)); 1031 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n", 1032 rtw_read32(rtwdev, REG_IQK_RES_TX), 1033 rtw_read32(rtwdev, REG_IQK_RES_TY)); 1034 rtw_dbg(rtwdev, RTW_DBG_RFK, 1035 "[IQK] 0xe90(before IQK) = 0x%x, 0xe98(after IQK) = 0x%x\n", 1036 rtw_read32(rtwdev, REG_IQK_RDY), 1037 rtw_read32(rtwdev, 0xe98)); 1038 1039 tx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_TX_FAIL); 1040 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 1041 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 1042 1043 if (!tx_fail && tx_x != IQK_TX_X_ERR && tx_y != IQK_TX_Y_ERR) 1044 return IQK_TX_OK; 1045 1046 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] A TX IQK failed\n"); 1047 1048 return 0; 1049} 1050 1051static u8 rtw8703b_iqk_check_rx_failed(struct rtw_dev *rtwdev) 1052{ 1053 s32 rx_x, rx_y; 1054 u32 rx_fail; 1055 1056 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n", 1057 rtw_read32(rtwdev, REG_IQK_RES_RX), 1058 rtw_read32(rtwdev, REG_IQK_RES_RY)); 1059 1060 rtw_dbg(rtwdev, RTW_DBG_RFK, 1061 "[IQK] 0xea0(before IQK) = 0x%x, 0xea8(after IQK) = 0x%x\n", 1062 rtw_read32(rtwdev, 0xea0), 1063 rtw_read32(rtwdev, 0xea8)); 1064 1065 rx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_RX_FAIL); 1066 rx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX); 1067 rx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY); 1068 rx_y = abs(iqkxy_to_s32(rx_y)); 1069 1070 if (!rx_fail && rx_x != IQK_RX_X_ERR && rx_y != IQK_RX_Y_ERR && 1071 rx_x < IQK_RX_X_UPPER && rx_x > IQK_RX_X_LOWER && 1072 rx_y < IQK_RX_Y_LMT) 1073 return IQK_RX_OK; 1074 1075 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] A RX IQK failed\n"); 1076 1077 return 0; 1078} 1079 1080static u8 rtw8703b_iqk_tx_path(struct rtw_dev *rtwdev, 1081 const struct rtw8723x_iqk_backup_regs *backup) 1082{ 1083 u8 status; 1084 1085 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A TX IQK!\n"); 1086 1087 /* IQK setting */ 1088 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); 1089 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1090 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c); 1091 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); 1092 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); 1093 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); 1094 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x8214030f); 1095 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28110000); 1096 rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000); 1097 rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000); 1098 1099 /* LO calibration setting */ 1100 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911); 1101 1102 /* leave IQK mode */ 1103 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000); 1104 1105 /* PA, PAD setting */ 1106 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x1); 1107 rtw_write_rf(rtwdev, RF_PATH_A, 0x55, 0x7f, 0x7); 1108 rtw_write_rf(rtwdev, RF_PATH_A, 0x7f, RFREG_MASK, 0xd400); 1109 1110 rtw8703b_iqk_one_shot(rtwdev, true); 1111 status = rtw8703b_iqk_check_tx_failed(rtwdev); 1112 1113 rtw8703b_iqk_txrx_path_post(rtwdev, backup); 1114 1115 return status; 1116} 1117 1118static u8 rtw8703b_iqk_rx_path(struct rtw_dev *rtwdev, 1119 const struct rtw8723x_iqk_backup_regs *backup) 1120{ 1121 u8 status; 1122 u32 tx_x, tx_y; 1123 1124 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK step 1!\n"); 1125 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @A RX IQK1 = 0x%x\n", 1126 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 1127 rtw_write32(rtwdev, REG_BB_SEL_BTG, 0x99000000); 1128 1129 /* disable IQC mode */ 1130 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1131 1132 /* IQK setting */ 1133 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); 1134 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1135 1136 /* path IQK setting */ 1137 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c); 1138 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); 1139 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); 1140 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); 1141 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x8214030f); 1142 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28110000); 1143 rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000); 1144 rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000); 1145 1146 /* LOK setting */ 1147 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911); 1148 1149 /* RX IQK mode */ 1150 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, 0x80000, 0x1); 1151 rtw_write_rf(rtwdev, RF_PATH_A, 0x30, RFREG_MASK, 0x30000); 1152 rtw_write_rf(rtwdev, RF_PATH_A, 0x31, RFREG_MASK, 0x00007); 1153 rtw_write_rf(rtwdev, RF_PATH_A, 0x32, RFREG_MASK, 0x57db7); 1154 1155 rtw8703b_iqk_one_shot(rtwdev, true); 1156 /* leave IQK mode */ 1157 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000); 1158 status = rtw8703b_iqk_check_tx_failed(rtwdev); 1159 1160 if (!status) 1161 goto restore; 1162 1163 /* second round */ 1164 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 1165 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 1166 1167 rtw_write32(rtwdev, REG_TXIQK_11N, BIT_SET_TXIQK_11N(tx_x, tx_y)); 1168 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n", 1169 rtw_read32(rtwdev, REG_TXIQK_11N), 1170 BIT_SET_TXIQK_11N(tx_x, tx_y)); 1171 1172 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK step 2!\n"); 1173 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @A RX IQK 2 = 0x%x\n", 1174 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 1175 1176 /* IQK setting */ 1177 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1178 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c); 1179 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c); 1180 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); 1181 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); 1182 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82110000); 1183 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160c1f); 1184 rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000); 1185 rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000); 1186 1187 /* LO calibration setting */ 1188 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1); 1189 1190 /* leave IQK mode */ 1191 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000); 1192 /* modify RX IQK mode table */ 1193 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, 0x80000, 0x1); 1194 /* RF_RCK_OS, RF_TXPA_G1, RF_TXPA_G2 */ 1195 rtw_write_rf(rtwdev, RF_PATH_A, 0x30, RFREG_MASK, 0x30000); 1196 rtw_write_rf(rtwdev, RF_PATH_A, 0x31, RFREG_MASK, 0x00007); 1197 rtw_write_rf(rtwdev, RF_PATH_A, 0x32, RFREG_MASK, 0xf7d77); 1198 1199 /* PA, PAD setting */ 1200 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x1); 1201 rtw_write_rf(rtwdev, RF_PATH_A, 0x55, 0x7f, 0x5); 1202 1203 rtw8703b_iqk_one_shot(rtwdev, false); 1204 status |= rtw8703b_iqk_check_rx_failed(rtwdev); 1205 1206restore: 1207 rtw8703b_iqk_txrx_path_post(rtwdev, backup); 1208 1209 return status; 1210} 1211 1212static 1213void rtw8703b_iqk_one_round(struct rtw_dev *rtwdev, s32 result[][IQK_NR], u8 t, 1214 const struct rtw8723x_iqk_backup_regs *backup) 1215{ 1216 u32 i; 1217 u8 a_ok; 1218 1219 rtw_dbg(rtwdev, RTW_DBG_RFK, 1220 "[IQK] IQ Calibration for 1T1R_S0/S1 for %d times\n", t); 1221 1222 rtw8723x_iqk_path_adda_on(rtwdev, ADDA_ON_VAL_8703B); 1223 rtw8703b_iqk_config_mac(rtwdev, backup); 1224 rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf); 1225 rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05600); 1226 rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4); 1227 rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204000); 1228 1229 for (i = 0; i < PATH_IQK_RETRY; i++) { 1230 a_ok = rtw8703b_iqk_tx_path(rtwdev, backup); 1231 if (a_ok == IQK_TX_OK) { 1232 rtw_dbg(rtwdev, RTW_DBG_RFK, 1233 "[IQK] path A TX IQK success!\n"); 1234 result[t][IQK_S1_TX_X] = 1235 rtw_read32_mask(rtwdev, REG_IQK_RES_TX, 1236 BIT_MASK_RES_TX); 1237 result[t][IQK_S1_TX_Y] = 1238 rtw_read32_mask(rtwdev, REG_IQK_RES_TY, 1239 BIT_MASK_RES_TY); 1240 break; 1241 } 1242 1243 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A TX IQK fail!\n"); 1244 result[t][IQK_S1_TX_X] = 0x100; 1245 result[t][IQK_S1_TX_Y] = 0x0; 1246 } 1247 1248 for (i = 0; i < PATH_IQK_RETRY; i++) { 1249 a_ok = rtw8703b_iqk_rx_path(rtwdev, backup); 1250 if (a_ok == (IQK_TX_OK | IQK_RX_OK)) { 1251 rtw_dbg(rtwdev, RTW_DBG_RFK, 1252 "[IQK] path A RX IQK success!\n"); 1253 result[t][IQK_S1_RX_X] = 1254 rtw_read32_mask(rtwdev, REG_IQK_RES_RX, 1255 BIT_MASK_RES_RX); 1256 result[t][IQK_S1_RX_Y] = 1257 rtw_read32_mask(rtwdev, REG_IQK_RES_RY, 1258 BIT_MASK_RES_RY); 1259 break; 1260 } 1261 1262 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK fail!\n"); 1263 result[t][IQK_S1_RX_X] = 0x100; 1264 result[t][IQK_S1_RX_Y] = 0x0; 1265 } 1266 1267 if (a_ok == 0x0) 1268 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A IQK fail!\n"); 1269 1270 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1271 mdelay(1); 1272} 1273 1274static 1275void rtw8703b_iqk_fill_a_matrix(struct rtw_dev *rtwdev, const s32 result[]) 1276{ 1277 u32 tmp_rx_iqi = 0x40000100 & GENMASK(31, 16); 1278 s32 tx1_a, tx1_a_ext; 1279 s32 tx1_c, tx1_c_ext; 1280 s32 oldval_1; 1281 s32 x, y; 1282 1283 if (result[IQK_S1_TX_X] == 0) 1284 return; 1285 1286 oldval_1 = rtw_read32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1287 BIT_MASK_TXIQ_ELM_D); 1288 1289 x = iqkxy_to_s32(result[IQK_S1_TX_X]); 1290 tx1_a = iqk_mult(x, oldval_1, &tx1_a_ext); 1291 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1292 BIT_MASK_TXIQ_ELM_A, tx1_a); 1293 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, 1294 BIT_MASK_OFDM0_EXT_A, tx1_a_ext); 1295 1296 y = iqkxy_to_s32(result[IQK_S1_TX_Y]); 1297 tx1_c = iqk_mult(y, oldval_1, &tx1_c_ext); 1298 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1299 BIT_SET_TXIQ_ELM_C1(tx1_c)); 1300 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1301 BIT_MASK_TXIQ_ELM_C, BIT_SET_TXIQ_ELM_C2(tx1_c)); 1302 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, 1303 BIT_MASK_OFDM0_EXT_C, tx1_c_ext); 1304 1305 rtw_dbg(rtwdev, RTW_DBG_RFK, 1306 "[IQK] X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n", 1307 x, tx1_a, oldval_1); 1308 rtw_dbg(rtwdev, RTW_DBG_RFK, 1309 "[IQK] Y = 0x%x, TX1_C = 0x%x\n", y, tx1_c); 1310 1311 if (result[IQK_S1_RX_X] == 0) 1312 return; 1313 1314 tmp_rx_iqi |= FIELD_PREP(BIT_MASK_RXIQ_S1_X, result[IQK_S1_RX_X]); 1315 tmp_rx_iqi |= FIELD_PREP(BIT_MASK_RXIQ_S1_Y1, result[IQK_S1_RX_Y]); 1316 rtw_write32(rtwdev, REG_A_RXIQI, tmp_rx_iqi); 1317 rtw_write32_mask(rtwdev, REG_RXIQK_MATRIX_LSB_11N, BIT_MASK_RXIQ_S1_Y2, 1318 BIT_SET_RXIQ_S1_Y2(result[IQK_S1_RX_Y])); 1319} 1320 1321static void rtw8703b_phy_calibration(struct rtw_dev *rtwdev) 1322{ 1323 /* For some reason path A is called S1 and B S0 in shared 1324 * rtw88 calibration data. 1325 */ 1326 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1327 struct rtw8723x_iqk_backup_regs backup; 1328 u8 final_candidate = IQK_ROUND_INVALID; 1329 s32 result[IQK_ROUND_SIZE][IQK_NR]; 1330 bool good; 1331 u8 i, j; 1332 1333 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Start!\n"); 1334 1335 memset(result, 0, sizeof(result)); 1336 1337 rtw8723x_iqk_backup_path_ctrl(rtwdev, &backup); 1338 rtw8723x_iqk_backup_lte_path_gnt(rtwdev, &backup); 1339 rtw8723x_iqk_backup_regs(rtwdev, &backup); 1340 1341 for (i = IQK_ROUND_0; i <= IQK_ROUND_2; i++) { 1342 rtw8723x_iqk_config_path_ctrl(rtwdev); 1343 rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8703B); 1344 1345 rtw8703b_iqk_one_round(rtwdev, result, i, &backup); 1346 1347 rtw_dbg(rtwdev, RTW_DBG_RFK, 1348 "[IQK] back to BB mode, load original values!\n"); 1349 if (i > IQK_ROUND_0) 1350 rtw8723x_iqk_restore_regs(rtwdev, &backup); 1351 rtw8723x_iqk_restore_lte_path_gnt(rtwdev, &backup); 1352 rtw8723x_iqk_restore_path_ctrl(rtwdev, &backup); 1353 1354 for (j = IQK_ROUND_0; j < i; j++) { 1355 good = rtw8723x_iqk_similarity_cmp(rtwdev, result, j, i); 1356 1357 if (good) { 1358 final_candidate = j; 1359 rtw_dbg(rtwdev, RTW_DBG_RFK, 1360 "[IQK] cmp %d:%d final_candidate is %x\n", 1361 j, i, final_candidate); 1362 goto iqk_done; 1363 } 1364 } 1365 } 1366 1367 if (final_candidate == IQK_ROUND_INVALID) { 1368 s32 reg_tmp = 0; 1369 1370 for (i = 0; i < IQK_NR; i++) 1371 reg_tmp += result[IQK_ROUND_HYBRID][i]; 1372 1373 if (reg_tmp != 0) { 1374 final_candidate = IQK_ROUND_HYBRID; 1375 } else { 1376 WARN(1, "IQK failed\n"); 1377 goto out; 1378 } 1379 } 1380 1381iqk_done: 1382 /* only path A is calibrated in rtl8703b */ 1383 rtw8703b_iqk_fill_a_matrix(rtwdev, result[final_candidate]); 1384 1385 dm_info->iqk.result.s1_x = result[final_candidate][IQK_S1_TX_X]; 1386 dm_info->iqk.result.s1_y = result[final_candidate][IQK_S1_TX_Y]; 1387 dm_info->iqk.result.s0_x = result[final_candidate][IQK_S0_TX_X]; 1388 dm_info->iqk.result.s0_y = result[final_candidate][IQK_S0_TX_Y]; 1389 dm_info->iqk.done = true; 1390 1391out: 1392 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup.bb_sel_btg); 1393 1394 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] final_candidate is %x\n", 1395 final_candidate); 1396 1397 for (i = IQK_ROUND_0; i < IQK_ROUND_SIZE; i++) 1398 rtw_dbg(rtwdev, RTW_DBG_RFK, 1399 "[IQK] Result %u: rege94_s1=%x rege9c_s1=%x regea4_s1=%x regeac_s1=%x rege94_s0=%x rege9c_s0=%x regea4_s0=%x regeac_s0=%x %s\n", 1400 i, 1401 result[i][0], result[i][1], result[i][2], result[i][3], 1402 result[i][4], result[i][5], result[i][6], result[i][7], 1403 final_candidate == i ? "(final candidate)" : ""); 1404 1405 rtw_dbg(rtwdev, RTW_DBG_RFK, 1406 "[IQK] 0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n", 1407 rtw_read32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE), 1408 rtw_read32(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N), 1409 rtw_read32(rtwdev, REG_A_RXIQI), 1410 rtw_read32(rtwdev, REG_RXIQK_MATRIX_LSB_11N)); 1411 rtw_dbg(rtwdev, RTW_DBG_RFK, 1412 "[IQK] 0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n", 1413 rtw_read32(rtwdev, REG_TXIQ_AB_S0), 1414 rtw_read32(rtwdev, REG_TXIQ_CD_S0), 1415 rtw_read32(rtwdev, REG_RXIQ_AB_S0)); 1416 1417 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Finished.\n"); 1418} 1419 1420static void rtw8703b_set_iqk_matrix_by_result(struct rtw_dev *rtwdev, 1421 u32 ofdm_swing, u8 rf_path) 1422{ 1423 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1424 s32 ele_A, ele_D, ele_C; 1425 s32 ele_A_ext, ele_C_ext, ele_D_ext; 1426 s32 iqk_result_x; 1427 s32 iqk_result_y; 1428 s32 value32; 1429 1430 switch (rf_path) { 1431 default: 1432 case RF_PATH_A: 1433 iqk_result_x = dm_info->iqk.result.s1_x; 1434 iqk_result_y = dm_info->iqk.result.s1_y; 1435 break; 1436 case RF_PATH_B: 1437 iqk_result_x = dm_info->iqk.result.s0_x; 1438 iqk_result_y = dm_info->iqk.result.s0_y; 1439 break; 1440 } 1441 1442 /* new element D */ 1443 ele_D = OFDM_SWING_D(ofdm_swing); 1444 iqk_mult(iqk_result_x, ele_D, &ele_D_ext); 1445 /* new element A */ 1446 iqk_result_x = iqkxy_to_s32(iqk_result_x); 1447 ele_A = iqk_mult(iqk_result_x, ele_D, &ele_A_ext); 1448 /* new element C */ 1449 iqk_result_y = iqkxy_to_s32(iqk_result_y); 1450 ele_C = iqk_mult(iqk_result_y, ele_D, &ele_C_ext); 1451 1452 switch (rf_path) { 1453 case RF_PATH_A: 1454 default: 1455 /* write new elements A, C, D, and element B is always 0 */ 1456 value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D); 1457 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, value32); 1458 value32 = BIT_SET_TXIQ_ELM_C1(ele_C); 1459 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1460 value32); 1461 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1462 value32 &= ~BIT_MASK_OFDM0_EXTS; 1463 value32 |= BIT_SET_OFDM0_EXTS(ele_A_ext, ele_C_ext, ele_D_ext); 1464 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1465 break; 1466 1467 case RF_PATH_B: 1468 /* write new elements A, C, D, and element B is always 0 */ 1469 value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D); 1470 rtw_write32(rtwdev, REG_OFDM_0_XB_TX_IQ_IMBALANCE, value32); 1471 value32 = BIT_SET_TXIQ_ELM_C1(ele_C); 1472 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXB_LSB2_11N, MASKH4BITS, 1473 value32); 1474 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1475 value32 &= ~BIT_MASK_OFDM0_EXTS_B; 1476 value32 |= BIT_SET_OFDM0_EXTS_B(ele_A_ext, ele_C_ext, ele_D_ext); 1477 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1478 break; 1479 } 1480} 1481 1482static void rtw8703b_set_iqk_matrix(struct rtw_dev *rtwdev, s8 ofdm_index, 1483 u8 rf_path) 1484{ 1485 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1486 s32 value32; 1487 u32 ofdm_swing; 1488 1489 ofdm_index = clamp_t(s8, ofdm_index, 0, RTW_OFDM_SWING_TABLE_SIZE - 1); 1490 1491 ofdm_swing = rtw8703b_ofdm_swing_table[ofdm_index]; 1492 1493 if (dm_info->iqk.done) { 1494 rtw8703b_set_iqk_matrix_by_result(rtwdev, ofdm_swing, rf_path); 1495 return; 1496 } 1497 1498 switch (rf_path) { 1499 case RF_PATH_A: 1500 default: 1501 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, ofdm_swing); 1502 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1503 0x00); 1504 1505 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1506 value32 &= ~BIT_MASK_OFDM0_EXTS; 1507 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1508 break; 1509 1510 case RF_PATH_B: 1511 rtw_write32(rtwdev, REG_OFDM_0_XB_TX_IQ_IMBALANCE, ofdm_swing); 1512 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXB_LSB2_11N, MASKH4BITS, 1513 0x00); 1514 1515 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1516 value32 &= ~BIT_MASK_OFDM0_EXTS_B; 1517 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1518 break; 1519 } 1520} 1521 1522static void rtw8703b_pwrtrack_set_ofdm_pwr(struct rtw_dev *rtwdev, s8 swing_idx, 1523 s8 txagc_idx) 1524{ 1525 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1526 1527 dm_info->txagc_remnant_ofdm[RF_PATH_A] = txagc_idx; 1528 1529 /* Only path A is calibrated for rtl8703b */ 1530 rtw8703b_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_A); 1531} 1532 1533static void rtw8703b_pwrtrack_set_cck_pwr(struct rtw_dev *rtwdev, s8 swing_idx, 1534 s8 txagc_idx) 1535{ 1536 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1537 1538 dm_info->txagc_remnant_cck = txagc_idx; 1539 1540 swing_idx = clamp_t(s8, swing_idx, 0, RTW_CCK_SWING_TABLE_SIZE - 1); 1541 1542 BUILD_BUG_ON(ARRAY_SIZE(rtw8703b_cck_pwr_regs) 1543 != ARRAY_SIZE(rtw8703b_cck_swing_table[0])); 1544 1545 for (int i = 0; i < ARRAY_SIZE(rtw8703b_cck_pwr_regs); i++) 1546 rtw_write8(rtwdev, rtw8703b_cck_pwr_regs[i], 1547 rtw8703b_cck_swing_table[swing_idx][i]); 1548} 1549 1550static void rtw8703b_pwrtrack_set(struct rtw_dev *rtwdev, u8 path) 1551{ 1552 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1553 struct rtw_hal *hal = &rtwdev->hal; 1554 u8 limit_ofdm; 1555 u8 limit_cck = 21; 1556 s8 final_ofdm_swing_index; 1557 s8 final_cck_swing_index; 1558 1559 limit_ofdm = rtw8723x_pwrtrack_get_limit_ofdm(rtwdev); 1560 1561 final_ofdm_swing_index = dm_info->default_ofdm_index + 1562 dm_info->delta_power_index[path]; 1563 final_cck_swing_index = dm_info->default_cck_index + 1564 dm_info->delta_power_index[path]; 1565 1566 if (final_ofdm_swing_index > limit_ofdm) 1567 rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, limit_ofdm, 1568 final_ofdm_swing_index - limit_ofdm); 1569 else if (final_ofdm_swing_index < 0) 1570 rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, 0, 1571 final_ofdm_swing_index); 1572 else 1573 rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0); 1574 1575 if (final_cck_swing_index > limit_cck) 1576 rtw8703b_pwrtrack_set_cck_pwr(rtwdev, limit_cck, 1577 final_cck_swing_index - limit_cck); 1578 else if (final_cck_swing_index < 0) 1579 rtw8703b_pwrtrack_set_cck_pwr(rtwdev, 0, 1580 final_cck_swing_index); 1581 else 1582 rtw8703b_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0); 1583 1584 rtw_phy_set_tx_power_level(rtwdev, hal->current_channel); 1585} 1586 1587static void rtw8703b_phy_pwrtrack(struct rtw_dev *rtwdev) 1588{ 1589 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1590 struct rtw_swing_table swing_table; 1591 u8 thermal_value, delta, path; 1592 bool do_iqk = false; 1593 1594 rtw_phy_config_swing_table(rtwdev, &swing_table); 1595 1596 if (rtwdev->efuse.thermal_meter[0] == 0xff) 1597 return; 1598 1599 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1600 1601 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1602 1603 do_iqk = rtw_phy_pwrtrack_need_iqk(rtwdev); 1604 1605 if (do_iqk) 1606 rtw8723x_lck(rtwdev); 1607 1608 if (dm_info->pwr_trk_init_trigger) 1609 dm_info->pwr_trk_init_trigger = false; 1610 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1611 RF_PATH_A)) 1612 goto iqk; 1613 1614 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1615 1616 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); 1617 1618 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1619 s8 delta_cur, delta_last; 1620 1621 delta_last = dm_info->delta_power_index[path]; 1622 delta_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, 1623 path, RF_PATH_A, delta); 1624 if (delta_last == delta_cur) 1625 continue; 1626 1627 dm_info->delta_power_index[path] = delta_cur; 1628 rtw8703b_pwrtrack_set(rtwdev, path); 1629 } 1630 1631 rtw8723x_pwrtrack_set_xtal(rtwdev, RF_PATH_A, delta); 1632 1633iqk: 1634 if (do_iqk) 1635 rtw8703b_phy_calibration(rtwdev); 1636} 1637 1638static void rtw8703b_pwr_track(struct rtw_dev *rtwdev) 1639{ 1640 struct rtw_efuse *efuse = &rtwdev->efuse; 1641 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1642 1643 if (efuse->power_track_type != 0) { 1644 rtw_warn(rtwdev, "unsupported power track type"); 1645 return; 1646 } 1647 1648 if (!dm_info->pwr_trk_triggered) { 1649 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1650 GENMASK(17, 16), 0x03); 1651 dm_info->pwr_trk_triggered = true; 1652 return; 1653 } 1654 1655 rtw8703b_phy_pwrtrack(rtwdev); 1656 dm_info->pwr_trk_triggered = false; 1657} 1658 1659static void rtw8703b_coex_set_gnt_fix(struct rtw_dev *rtwdev) 1660{ 1661} 1662 1663static void rtw8703b_coex_set_gnt_debug(struct rtw_dev *rtwdev) 1664{ 1665} 1666 1667static void rtw8703b_coex_set_rfe_type(struct rtw_dev *rtwdev) 1668{ 1669 struct rtw_coex *coex = &rtwdev->coex; 1670 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1671 1672 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 1673 coex_rfe->ant_switch_polarity = 0; 1674 coex_rfe->ant_switch_exist = false; 1675 coex_rfe->ant_switch_with_bt = false; 1676 coex_rfe->ant_switch_diversity = false; 1677 coex_rfe->wlg_at_btg = true; 1678 1679 /* disable LTE coex on wifi side */ 1680 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0); 1681 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); 1682 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); 1683} 1684 1685static void rtw8703b_coex_set_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 1686{ 1687} 1688 1689static void rtw8703b_coex_set_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 1690{ 1691} 1692 1693static const u8 rtw8703b_pwrtrk_2gb_n[] = { 1694 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 1695 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 1696}; 1697 1698static const u8 rtw8703b_pwrtrk_2gb_p[] = { 1699 0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, 1700 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15 1701}; 1702 1703static const u8 rtw8703b_pwrtrk_2ga_n[] = { 1704 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 1705 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 1706}; 1707 1708static const u8 rtw8703b_pwrtrk_2ga_p[] = { 1709 0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, 1710 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15 1711}; 1712 1713static const u8 rtw8703b_pwrtrk_2g_cck_b_n[] = { 1714 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 1715 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 1716}; 1717 1718static const u8 rtw8703b_pwrtrk_2g_cck_b_p[] = { 1719 0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 1720 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13 1721}; 1722 1723static const u8 rtw8703b_pwrtrk_2g_cck_a_n[] = { 1724 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 1725 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 1726}; 1727 1728static const u8 rtw8703b_pwrtrk_2g_cck_a_p[] = { 1729 0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 1730 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13 1731}; 1732 1733static const s8 rtw8703b_pwrtrk_xtal_n[] = { 1734 0, 0, 0, -1, -1, -1, -1, -2, -2, -2, -3, -3, -3, -3, -3, 1735 -4, -2, -2, -1, -1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1 1736}; 1737 1738static const s8 rtw8703b_pwrtrk_xtal_p[] = { 1739 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 1, 0, -1, -1, -1, 1740 -2, -3, -7, -9, -10, -11, -14, -16, -18, -20, -22, -24, -26, -28, -30 1741}; 1742 1743static const struct rtw_pwr_track_tbl rtw8703b_rtw_pwr_track_tbl = { 1744 .pwrtrk_2gb_n = rtw8703b_pwrtrk_2gb_n, 1745 .pwrtrk_2gb_p = rtw8703b_pwrtrk_2gb_p, 1746 .pwrtrk_2ga_n = rtw8703b_pwrtrk_2ga_n, 1747 .pwrtrk_2ga_p = rtw8703b_pwrtrk_2ga_p, 1748 .pwrtrk_2g_cckb_n = rtw8703b_pwrtrk_2g_cck_b_n, 1749 .pwrtrk_2g_cckb_p = rtw8703b_pwrtrk_2g_cck_b_p, 1750 .pwrtrk_2g_ccka_n = rtw8703b_pwrtrk_2g_cck_a_n, 1751 .pwrtrk_2g_ccka_p = rtw8703b_pwrtrk_2g_cck_a_p, 1752 .pwrtrk_xtal_n = rtw8703b_pwrtrk_xtal_n, 1753 .pwrtrk_xtal_p = rtw8703b_pwrtrk_xtal_p, 1754}; 1755 1756static const struct rtw_rfe_def rtw8703b_rfe_defs[] = { 1757 [0] = { .phy_pg_tbl = &rtw8703b_bb_pg_tbl, 1758 .txpwr_lmt_tbl = &rtw8703b_txpwr_lmt_tbl, 1759 .pwr_track_tbl = &rtw8703b_rtw_pwr_track_tbl, }, 1760}; 1761 1762/* Shared-Antenna Coex Table */ 1763static const struct coex_table_para table_sant_8703b[] = { 1764 {0xffffffff, 0xffffffff}, /* case-0 */ 1765 {0x55555555, 0x55555555}, 1766 {0x66555555, 0x66555555}, 1767 {0xaaaaaaaa, 0xaaaaaaaa}, 1768 {0x5a5a5a5a, 0x5a5a5a5a}, 1769 {0xfafafafa, 0xfafafafa}, /* case-5 */ 1770 {0x6a5a5555, 0xaaaaaaaa}, 1771 {0x6a5a56aa, 0x6a5a56aa}, 1772 {0x6a5a5a5a, 0x6a5a5a5a}, 1773 {0x66555555, 0x5a5a5a5a}, 1774 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 1775 {0x66555555, 0x6a5a5aaa}, 1776 {0x66555555, 0x5a5a5aaa}, 1777 {0x66555555, 0x6aaa5aaa}, 1778 {0x66555555, 0xaaaa5aaa}, 1779 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 1780 {0xffff55ff, 0xfafafafa}, 1781 {0xffff55ff, 0x6afa5afa}, 1782 {0xaaffffaa, 0xfafafafa}, 1783 {0xaa5555aa, 0x5a5a5a5a}, 1784 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 1785 {0xaa5555aa, 0xaaaaaaaa}, 1786 {0xffffffff, 0x5a5a5a5a}, 1787 {0xffffffff, 0x5a5a5a5a}, 1788 {0xffffffff, 0x55555555}, 1789 {0xffffffff, 0x5a5a5aaa}, /* case-25 */ 1790 {0x55555555, 0x5a5a5a5a}, 1791 {0x55555555, 0xaaaaaaaa}, 1792 {0x55555555, 0x6a5a6a5a}, 1793 {0x66556655, 0x66556655}, 1794 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */ 1795 {0xffffffff, 0x5aaa5aaa}, 1796 {0x56555555, 0x5a5a5aaa}, 1797}; 1798 1799/* Shared-Antenna TDMA */ 1800static const struct coex_tdma_para tdma_sant_8703b[] = { 1801 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 1802 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 1803 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 1804 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 1805 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1806 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 1807 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1808 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 1809 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1810 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1811 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 1812 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 1813 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1814 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1815 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1816 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 1817 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1818 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 1819 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1820 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 1821 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 1822 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 1823 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 1824 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 1825 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 1826 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 1827 { {0x51, 0x08, 0x03, 0x10, 0x50} }, 1828 { {0x61, 0x08, 0x03, 0x11, 0x11} }, 1829}; 1830 1831static const struct rtw_chip_ops rtw8703b_ops = { 1832 .power_on = rtw_power_on, 1833 .power_off = rtw_power_off, 1834 .mac_init = rtw8723x_mac_init, 1835 .mac_postinit = rtw8723x_mac_postinit, 1836 .dump_fw_crash = NULL, 1837 .shutdown = NULL, 1838 .read_efuse = rtw8703b_read_efuse, 1839 .phy_set_param = rtw8703b_phy_set_param, 1840 .set_channel = rtw8703b_set_channel, 1841 .query_phy_status = query_phy_status, 1842 .read_rf = rtw_phy_read_rf_sipi, 1843 .write_rf = rtw_phy_write_rf_reg_sipi, 1844 .set_tx_power_index = rtw8723x_set_tx_power_index, 1845 .set_antenna = NULL, 1846 .cfg_ldo25 = rtw8723x_cfg_ldo25, 1847 .efuse_grant = rtw8723x_efuse_grant, 1848 .set_ampdu_factor = NULL, 1849 .false_alarm_statistics = rtw8723x_false_alarm_statistics, 1850 .phy_calibration = rtw8703b_phy_calibration, 1851 .dpk_track = NULL, 1852 /* 8723d uses REG_CSRATIO to set dm_info.cck_pd_default, which 1853 * is used in its cck_pd_set function. According to comments 1854 * in the vendor driver code it doesn't exist in this chip 1855 * generation, only 0xa0a ("ODM_CCK_PD_THRESH", which is only 1856 * *written* to). 1857 */ 1858 .cck_pd_set = NULL, 1859 .pwr_track = rtw8703b_pwr_track, 1860 .config_bfee = NULL, 1861 .set_gid_table = NULL, 1862 .cfg_csi_rate = NULL, 1863 .adaptivity_init = NULL, 1864 .adaptivity = NULL, 1865 .cfo_init = NULL, 1866 .cfo_track = NULL, 1867 .config_tx_path = NULL, 1868 .config_txrx_mode = NULL, 1869 .fill_txdesc_checksum = rtw8723x_fill_txdesc_checksum, 1870 1871 /* for coex */ 1872 .coex_set_init = rtw8723x_coex_cfg_init, 1873 .coex_set_ant_switch = NULL, 1874 .coex_set_gnt_fix = rtw8703b_coex_set_gnt_fix, 1875 .coex_set_gnt_debug = rtw8703b_coex_set_gnt_debug, 1876 .coex_set_rfe_type = rtw8703b_coex_set_rfe_type, 1877 .coex_set_wl_tx_power = rtw8703b_coex_set_wl_tx_power, 1878 .coex_set_wl_rx_gain = rtw8703b_coex_set_wl_rx_gain, 1879}; 1880 1881const struct rtw_chip_info rtw8703b_hw_spec = { 1882 .ops = &rtw8703b_ops, 1883 .id = RTW_CHIP_TYPE_8703B, 1884 1885 .fw_name = "rtw88/rtw8703b_fw.bin", 1886 .wlan_cpu = RTW_WCPU_8051, 1887 .tx_pkt_desc_sz = 40, 1888 .tx_buf_desc_sz = 16, 1889 .rx_pkt_desc_sz = 24, 1890 .rx_buf_desc_sz = 8, 1891 .phy_efuse_size = 256, 1892 .log_efuse_size = 512, 1893 .ptct_efuse_size = 15, 1894 .txff_size = 32768, 1895 .rxff_size = 16384, 1896 .rsvd_drv_pg_num = 8, 1897 .band = RTW_BAND_2G, 1898 .page_size = TX_PAGE_SIZE, 1899 .csi_buf_pg_num = 0, 1900 .dig_min = 0x20, 1901 .txgi_factor = 1, 1902 .is_pwr_by_rate_dec = true, 1903 .rx_ldpc = false, 1904 .tx_stbc = false, 1905 .max_power_index = 0x3f, 1906 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, 1907 .usb_tx_agg_desc_num = 1, /* Not sure if this chip has USB interface */ 1908 .hw_feature_report = true, 1909 .c2h_ra_report_size = 7, 1910 .old_datarate_fb_limit = true, 1911 1912 .path_div_supported = false, 1913 .ht_supported = true, 1914 .vht_supported = false, 1915 .lps_deep_mode_supported = 0, 1916 1917 .sys_func_en = 0xFD, 1918 .pwr_on_seq = card_enable_flow_8703b, 1919 .pwr_off_seq = card_disable_flow_8703b, 1920 .rqpn_table = rqpn_table_8703b, 1921 .prioq_addrs = &rtw8723x_common.prioq_addrs, 1922 .page_table = page_table_8703b, 1923 /* used only in pci.c, not needed for SDIO devices */ 1924 .intf_table = NULL, 1925 1926 .dig = rtw8723x_common.dig, 1927 .dig_cck = rtw8723x_common.dig_cck, 1928 1929 .rf_sipi_addr = {0x840, 0x844}, 1930 .rf_sipi_read_addr = rtw8723x_common.rf_sipi_addr, 1931 .fix_rf_phy_num = 2, 1932 .ltecoex_addr = &rtw8723x_common.ltecoex_addr, 1933 1934 .mac_tbl = &rtw8703b_mac_tbl, 1935 .agc_tbl = &rtw8703b_agc_tbl, 1936 .bb_tbl = &rtw8703b_bb_tbl, 1937 .rf_tbl = {&rtw8703b_rf_a_tbl}, 1938 1939 .rfe_defs = rtw8703b_rfe_defs, 1940 .rfe_defs_size = ARRAY_SIZE(rtw8703b_rfe_defs), 1941 1942 .iqk_threshold = 8, 1943 1944 /* WOWLAN firmware exists, but not implemented yet */ 1945 .wow_fw_name = "rtw88/rtw8703b_wow_fw.bin", 1946 .wowlan_stub = NULL, 1947 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN, 1948 1949 /* Vendor driver has a time-based format, converted from 1950 * 20180330 1951 */ 1952 .coex_para_ver = 0x0133ed6a, 1953 .bt_desired_ver = 0x1c, 1954 .scbd_support = true, 1955 .new_scbd10_def = true, 1956 .ble_hid_profile_support = false, 1957 .wl_mimo_ps_support = false, 1958 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 1959 .bt_rssi_type = COEX_BTRSSI_RATIO, 1960 .ant_isolation = 15, 1961 .rssi_tolerance = 2, 1962 .bt_rssi_step = bt_rssi_step_8703b, 1963 .wl_rssi_step = wl_rssi_step_8703b, 1964 /* sant -> shared antenna, nsant -> non-shared antenna 1965 * Not sure if 8703b versions with non-shard antenna even exist. 1966 */ 1967 .table_sant_num = ARRAY_SIZE(table_sant_8703b), 1968 .table_sant = table_sant_8703b, 1969 .table_nsant_num = 0, 1970 .table_nsant = NULL, 1971 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8703b), 1972 .tdma_sant = tdma_sant_8703b, 1973 .tdma_nsant_num = 0, 1974 .tdma_nsant = NULL, 1975 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8703b), 1976 .wl_rf_para_tx = rf_para_tx_8703b, 1977 .wl_rf_para_rx = rf_para_rx_8703b, 1978 .bt_afh_span_bw20 = 0x20, 1979 .bt_afh_span_bw40 = 0x30, 1980 .afh_5g_num = ARRAY_SIZE(afh_5g_8703b), 1981 .afh_5g = afh_5g_8703b, 1982 /* REG_BTG_SEL doesn't seem to have a counterpart in the 1983 * vendor driver. Mathematically it's REG_PAD_CTRL1 + 3. 1984 * 1985 * It is used in the cardemu_to_act power sequence by though 1986 * (by address, 0x0067), comment: "0x67[0] = 0 to disable 1987 * BT_GPS_SEL pins" That seems to fit. 1988 */ 1989 .btg_reg = NULL, 1990 /* These registers are used to read (and print) from if 1991 * CONFIG_RTW88_DEBUGFS is enabled. 1992 */ 1993 .coex_info_hw_regs_num = 0, 1994 .coex_info_hw_regs = NULL, 1995}; 1996EXPORT_SYMBOL(rtw8703b_hw_spec); 1997 1998MODULE_FIRMWARE("rtw88/rtw8703b_fw.bin"); 1999MODULE_FIRMWARE("rtw88/rtw8703b_wow_fw.bin"); 2000 2001MODULE_AUTHOR("Fiona Klute <fiona.klute@gmx.de>"); 2002MODULE_DESCRIPTION("Realtek 802.11n wireless 8703b driver"); 2003MODULE_LICENSE("Dual BSD/GPL");
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