reg.h

   1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2/* Copyright(c) 2018-2019  Realtek Corporation
   3 */
   4
   5#ifndef __RTW_REG_DEF_H__
   6#define __RTW_REG_DEF_H__
   7
   8#define REG_SYS_FUNC_EN		0x0002
   9#define BIT_FEN_EN_25_1		BIT(13)
  10#define BIT_FEN_ELDR		BIT(12)
  11#define BIT_FEN_PCIEA		BIT(6)
  12#define BIT_FEN_CPUEN		BIT(2)
  13#define BIT_FEN_USBA		BIT(2)
  14#define BIT_FEN_BB_GLB_RST	BIT(1)
  15#define BIT_FEN_BB_RSTB		BIT(0)
  16#define BIT_R_DIS_PRST		BIT(6)
  17#define BIT_WLOCK_1C_B6		BIT(5)
  18#define REG_SYS_PW_CTRL		0x0004
  19#define BIT_PFM_WOWL		BIT(3)
  20#define BIT_APFM_OFFMAC		BIT(9)
  21#define REG_APS_FSMCO		0x0004
  22#define APS_FSMCO_MAC_ENABLE	BIT(8)
  23#define APS_FSMCO_MAC_OFF	BIT(9)
  24#define APS_FSMCO_HW_POWERDOWN	BIT(15)
  25#define REG_SYS_CLK_CTRL	0x0008
  26#define BIT_CPU_CLK_EN		BIT(14)
  27
  28#define REG_SYS_CLKR		0x0008
  29#define BIT_ANA8M		BIT(1)
  30#define BIT_WAKEPAD_EN		BIT(3)
  31#define BIT_LOADER_CLK_EN	BIT(5)
  32
  33#define REG_RSV_CTRL		0x001C
  34#define DISABLE_PI		0x3
  35#define ENABLE_PI		0x2
  36#define BITS_RFC_DIRECT		(BIT(31) | BIT(30))
  37#define BIT_WLMCU_IOIF		BIT(0)
  38#define REG_RF_CTRL		0x001F
  39#define BIT_RF_SDM_RSTB		BIT(2)
  40#define BIT_RF_RSTB		BIT(1)
  41#define BIT_RF_EN		BIT(0)
  42
  43#define REG_RF_CTRL1		0x0020
  44#define REG_RF_CTRL2		0x0021
  45
  46#define REG_AFE_CTRL1		0x0024
  47#define BIT_MAC_CLK_SEL		(BIT(20) | BIT(21))
  48#define REG_EFUSE_CTRL		0x0030
  49#define BIT_EF_FLAG		BIT(31)
  50#define BIT_SHIFT_EF_ADDR	8
  51#define BIT_MASK_EF_ADDR	0x3ff
  52#define BIT_MASK_EF_DATA	0xff
  53#define BITS_EF_ADDR		(BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR)
  54#define BITS_PLL		0xf0
  55
  56#define REG_AFE_XTAL_CTRL	0x24
  57#define REG_AFE_PLL_CTRL	0x28
  58#define REG_AFE_CTRL3		0x2c
  59#define BIT_MASK_XTAL		0x00FFF000
  60#define BIT_XTAL_GMP_BIT4	BIT(28)
  61
  62#define REG_LDO_EFUSE_CTRL	0x0034
  63#define BIT_MASK_EFUSE_BANK_SEL	(BIT(8) | BIT(9))
  64
  65#define BIT_LDO25_VOLTAGE_V25	0x03
  66#define BIT_MASK_LDO25_VOLTAGE	GENMASK(6, 4)
  67#define BIT_SHIFT_LDO25_VOLTAGE	4
  68#define BIT_LDO25_EN		BIT(7)
  69
  70#define REG_ACLK_MON		0x3e
  71
  72#define REG_GPIO_MUXCFG		0x0040
  73#define BIT_FSPI_EN		BIT(19)
  74#define BIT_EN_SIC		BIT(12)
  75
  76#define BIT_PO_BT_PTA_PINS	BIT(9)
  77#define BIT_BT_PTA_EN		BIT(5)
  78#define BIT_WLRFE_4_5_EN	BIT(2)
  79
  80#define REG_GPIO_PIN_CTRL	0x0044
  81
  82#define REG_LED_CFG		0x004C
  83#define BIT_LNAON_SEL_EN	BIT(26)
  84#define BIT_PAPE_SEL_EN		BIT(25)
  85#define BIT_DPDT_WL_SEL		BIT(24)
  86#define BIT_DPDT_SEL_EN		BIT(23)
  87#define BIT_GPIO13_14_WL_CTRL_EN	BIT(22)
  88#define BIT_LED2_SV		BIT(19)
  89#define BIT_LED2_CM		GENMASK(18, 16)
  90#define BIT_LED1_SV		BIT(11)
  91#define BIT_LED1_CM		GENMASK(10, 8)
  92#define BIT_LED0_SV		BIT(3)
  93#define BIT_LED0_CM		GENMASK(2, 0)
  94#define BIT_LED_MODE_SW_CTRL	0
  95#define BIT_LED_MODE_RX		6
  96#define BIT_LED_MODE_TX		4
  97#define BIT_LED_MODE_TRX	2
  98#define REG_LEDCFG2		0x004E
  99#define REG_GPIO_PIN_CTRL_2	0x0060
 100#define REG_PAD_CTRL1		0x0064
 101#define BIT_BT_BTG_SEL		BIT(31)
 102#define BIT_PAPE_WLBT_SEL	BIT(29)
 103#define BIT_LNAON_WLBT_SEL	BIT(28)
 104#define BIT_BTGP_JTAG_EN	BIT(24)
 105#define BIT_BTGP_SPI_EN		BIT(20)
 106#define BIT_LED1DIS		BIT(15)
 107#define BIT_SW_DPDT_SEL_DATA	BIT(0)
 108#define REG_WL_BT_PWR_CTRL	0x0068
 109#define BIT_BT_FUNC_EN		BIT(18)
 110#define BIT_BT_DIG_CLK_EN	BIT(8)
 111#define REG_SYS_SDIO_CTRL	0x0070
 112#define BIT_DBG_GNT_WL_BT	BIT(27)
 113#define BIT_LTE_MUX_CTRL_PATH	BIT(26)
 114#define REG_HCI_OPT_CTRL	0x0074
 115#define BIT_USB_SUS_DIS		BIT(8)
 116#define BIT_SDIO_PAD_E5		BIT(18)
 117
 118#define REG_RF_B_CTRL		0x76
 119#define REG_RF_CTRL3		0x0076
 120
 121#define REG_AFE_CTRL_4		0x0078
 122#define BIT_CK320M_AFE_EN	BIT(4)
 123#define BIT_EN_SYN		BIT(15)
 124
 125#define REG_LDO_SWR_CTRL	0x007C
 126#define LDO_SEL			0xC3
 127#define SPS_SEL			0x83
 128#define BIT_XTA1		BIT(29)
 129#define BIT_XTA0		BIT(28)
 130
 131#define REG_MCUFW_CTRL		0x0080
 132#define BIT_ANA_PORT_EN		BIT(22)
 133#define BIT_MAC_PORT_EN		BIT(21)
 134#define BIT_BOOT_FSPI_EN	BIT(20)
 135#define BIT_ROM_DLEN		BIT(19)
 136#define BIT_ROM_PGE		GENMASK(18, 16)	/* legacy only */
 137#define BIT_SHIFT_ROM_PGE	16
 138#define BIT_FW_INIT_RDY		BIT(15)
 139#define BIT_FW_DW_RDY		BIT(14)
 140#define BIT_CPU_CLK_SEL		(BIT(12) | BIT(13))
 141#define BIT_RPWM_TOGGLE		BIT(7)
 142#define BIT_RAM_DL_SEL		BIT(7)	/* legacy only */
 143#define BIT_DMEM_CHKSUM_OK	BIT(6)
 144#define BIT_WINTINI_RDY		BIT(6)	/* legacy only */
 145#define BIT_DMEM_DW_OK		BIT(5)
 146#define BIT_IMEM_CHKSUM_OK	BIT(4)
 147#define BIT_IMEM_DW_OK		BIT(3)
 148#define BIT_IMEM_BOOT_LOAD_CHECKSUM_OK BIT(2)
 149#define BIT_FWDL_CHK_RPT	BIT(2)	/* legacy only */
 150#define BIT_MCUFWDL_RDY		BIT(1)	/* legacy only */
 151#define BIT_MCUFWDL_EN		BIT(0)
 152#define BIT_CHECK_SUM_OK	(BIT(4) | BIT(6))
 153#define FW_READY		(BIT_FW_INIT_RDY | BIT_FW_DW_RDY |             \
 154				 BIT_IMEM_DW_OK | BIT_DMEM_DW_OK |             \
 155				 BIT_CHECK_SUM_OK)
 156#define FW_READY_LEGACY		(BIT_MCUFWDL_RDY | BIT_FWDL_CHK_RPT |	       \
 157				 BIT_WINTINI_RDY | BIT_RAM_DL_SEL)
 158#define FW_READY_MASK		(0xffff & ~BIT_CPU_CLK_SEL)
 159
 160#define REG_MCU_TST_CFG		0x84
 161#define VAL_FW_TRIGGER		0x1
 162
 163#define REG_PMC_DBG_CTRL1	0xa8
 164#define BITS_PMC_BT_IQK_STS	GENMASK(22, 21)
 165
 166#define REG_HIMR0		0xb0
 167#define REG_HISR0		0xb4
 168#define REG_HIMR1		0xb8
 169#define REG_HISR1		0xbc
 170
 171#define REG_PAD_CTRL2		0x00C4
 172#define BIT_RSM_EN_V1		BIT(16)
 173#define BIT_NO_PDN_CHIPOFF_V1	BIT(17)
 174#define BIT_MASK_USB23_SW_MODE_V1	GENMASK(19, 18)
 175#define BIT_USB3_USB2_TRANSITION	BIT(20)
 176#define BIT_USB_MODE_U2		1
 177#define BIT_USB_MODE_U3		2
 178
 179#define REG_EFUSE_ACCESS	0x00CF
 180#define EFUSE_ACCESS_ON		0x69
 181#define EFUSE_ACCESS_OFF	0x00
 182
 183#define REG_WLRF1		0x00EC
 184#define REG_WIFI_BT_INFO	0x00AA
 185#define BIT_BT_INT_EN		BIT(15)
 186#define REG_SYS_CFG1		0x00F0
 187#define	BIT_RTL_ID		BIT(23)
 188#define BIT_LDO			BIT(24)
 189#define BIT_RF_TYPE_ID		BIT(27)
 190#define BIT_SHIFT_VENDOR_ID	16
 191#define BIT_MASK_VENDOR_ID	0xf
 192#define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID)
 193#define BITS_VENDOR_ID		(BIT_MASK_VENDOR_ID << BIT_SHIFT_VENDOR_ID)
 194#define BIT_CLEAR_VENDOR_ID(x)	((x) & (~BITS_VENDOR_ID))
 195#define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID)
 196#define BIT_SHIFT_CHIP_VER	12
 197#define BIT_MASK_CHIP_VER	0xf
 198#define BIT_CHIP_VER(x)	 (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER)
 199#define BITS_CHIP_VER		(BIT_MASK_CHIP_VER << BIT_SHIFT_CHIP_VER)
 200#define BIT_CLEAR_CHIP_VER(x)	((x) & (~BITS_CHIP_VER))
 201#define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER)
 202#define REG_SYS_STATUS1		0x00F4
 203#define REG_SYS_STATUS2		0x00F8
 204#define REG_SYS_CFG2		0x00FC
 205#define REG_WLRF1		0x00EC
 206#define BIT_WLRF1_BBRF_EN	(BIT(24) | BIT(25) | BIT(26))
 207#define REG_CR			0x0100
 208#define BIT_32K_CAL_TMR_EN	BIT(10)
 209#define BIT_MAC_SEC_EN		BIT(9)
 210#define BIT_ENSWBCN		BIT(8)
 211#define BIT_MACRXEN		BIT(7)
 212#define BIT_MACTXEN		BIT(6)
 213#define BIT_SCHEDULE_EN		BIT(5)
 214#define BIT_PROTOCOL_EN		BIT(4)
 215#define BIT_RXDMA_EN		BIT(3)
 216#define BIT_TXDMA_EN		BIT(2)
 217#define BIT_HCI_RXDMA_EN	BIT(1)
 218#define BIT_HCI_TXDMA_EN	BIT(0)
 219#define MAC_TRX_ENABLE	(BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \
 220			BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \
 221			BIT_MACTXEN | BIT_MACRXEN)
 222#define REG_PBP			0x104
 223#define PBP_RX_MASK		0x0f
 224#define PBP_TX_MASK		0xf0
 225#define PBP_64			0x0
 226#define PBP_128			0x1
 227#define PBP_256			0x2
 228#define PBP_512			0x3
 229#define PBP_1024		0x4
 230
 231#define BIT_SHIFT_TXDMA_VOQ_MAP	4
 232#define BIT_MASK_TXDMA_VOQ_MAP	0x3
 233#define BIT_TXDMA_VOQ_MAP(x)                                                   \
 234	(((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP)
 235#define BIT_SHIFT_TXDMA_VIQ_MAP	6
 236#define BIT_MASK_TXDMA_VIQ_MAP	0x3
 237#define BIT_TXDMA_VIQ_MAP(x)                                                   \
 238	(((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP)
 239#define REG_TXDMA_PQ_MAP	0x010C
 240#define BIT_RXDMA_ARBBW_EN	BIT(0)
 241#define BIT_RXSHFT_EN		BIT(1)
 242#define BIT_RXDMA_AGG_EN	BIT(2)
 243#define BIT_TXDMA_BW_EN		BIT(3)
 244#define BIT_SHIFT_TXDMA_BEQ_MAP	8
 245#define BIT_MASK_TXDMA_BEQ_MAP	0x3
 246#define BIT_TXDMA_BEQ_MAP(x)                                                   \
 247	(((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP)
 248#define BIT_SHIFT_TXDMA_BKQ_MAP	10
 249#define BIT_MASK_TXDMA_BKQ_MAP	0x3
 250#define BIT_TXDMA_BKQ_MAP(x)                                                   \
 251	(((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP)
 252#define BIT_SHIFT_TXDMA_MGQ_MAP	12
 253#define BIT_MASK_TXDMA_MGQ_MAP	0x3
 254#define BIT_TXDMA_MGQ_MAP(x)                                                   \
 255	(((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP)
 256#define BIT_SHIFT_TXDMA_HIQ_MAP	14
 257#define BIT_MASK_TXDMA_HIQ_MAP	0x3
 258#define BIT_TXDMA_HIQ_MAP(x)                                                   \
 259	(((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP)
 260#define BIT_SHIFT_TXSC_40M	4
 261#define BIT_MASK_TXSC_40M	0xf
 262#define BIT_TXSC_40M(x)							       \
 263	(((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M)
 264#define BIT_SHIFT_TXSC_20M	0
 265#define BIT_MASK_TXSC_20M	0xf
 266#define BIT_TXSC_20M(x)							       \
 267	(((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M)
 268#define BIT_SHIFT_MAC_CLK_SEL	20
 269#define MAC_CLK_HW_DEF_80M	0
 270#define MAC_CLK_HW_DEF_40M	1
 271#define MAC_CLK_HW_DEF_20M	2
 272#define MAC_CLK_SPEED		80
 273
 274#define REG_CR			0x0100
 275#define REG_TRXFF_BNDY		0x0114
 276#define REG_RXFF_BNDY		0x011C
 277#define REG_FE1IMR		0x0120
 278#define BIT_FS_RXDONE		BIT(16)
 279#define REG_CPWM		0x012C
 280#define REG_FWIMR		0x0130
 281#define BIT_FS_H2CCMD_INT_EN	BIT(4)
 282#define BIT_FS_HRCV_INT_EN	BIT(5)
 283#define REG_FWISR		0x0134
 284#define BIT_FS_H2CCMD_INT	BIT(4)
 285#define BIT_FS_HRCV_INT		BIT(5)
 286#define REG_PKTBUF_DBG_CTRL	0x0140
 287#define REG_C2HEVT		0x01A0
 288#define REG_MCUTST_1		0x01C0
 289#define REG_MCUTST_II		0x01C4
 290#define REG_WOWLAN_WAKE_REASON	0x01C7
 291#define REG_HMETFR		0x01CC
 292#define BIT_INT_BOX0		BIT(0)
 293#define BIT_INT_BOX1		BIT(1)
 294#define BIT_INT_BOX2		BIT(2)
 295#define BIT_INT_BOX3		BIT(3)
 296#define BIT_INT_BOX_ALL		(BIT_INT_BOX0 | BIT_INT_BOX1 | BIT_INT_BOX2 | \
 297				 BIT_INT_BOX3)
 298#define REG_HMEBOX0		0x01D0
 299#define REG_HMEBOX1		0x01D4
 300#define REG_HMEBOX2		0x01D8
 301#define REG_HMEBOX3		0x01DC
 302#define REG_LLT_INIT		0x01E0
 303#define BIT_LLT_WRITE_ACCESS	BIT(30)
 304#define REG_HMEBOX0_EX		0x01F0
 305#define REG_HMEBOX1_EX		0x01F4
 306#define REG_HMEBOX2_EX		0x01F8
 307#define REG_HMEBOX3_EX		0x01FC
 308
 309#define REG_RQPN		0x0200
 310#define BIT_MASK_HPQ		0xff
 311#define BIT_SHIFT_HPQ		0
 312#define BIT_RQPN_HPQ(x)		(((x) & BIT_MASK_HPQ) << BIT_SHIFT_HPQ)
 313#define BIT_MASK_LPQ		0xff
 314#define BIT_SHIFT_LPQ		8
 315#define BIT_RQPN_LPQ(x)		(((x) & BIT_MASK_LPQ) << BIT_SHIFT_LPQ)
 316#define BIT_MASK_PUBQ		0xff
 317#define BIT_SHIFT_PUBQ		16
 318#define BIT_RQPN_PUBQ(x)	(((x) & BIT_MASK_PUBQ) << BIT_SHIFT_PUBQ)
 319#define BIT_RQPN_HLP(h, l, p)	(BIT_LD_RQPN | BIT_RQPN_HPQ(h) |	       \
 320				 BIT_RQPN_LPQ(l) | BIT_RQPN_PUBQ(p))
 321
 322#define REG_FIFOPAGE_CTRL_2	0x0204
 323#define BIT_BCN_VALID_V1	BIT(15)
 324#define BIT_MASK_BCN_HEAD_1_V1	0xfff
 325#define REG_AUTO_LLT_V1		0x0208
 326#define BIT_AUTO_INIT_LLT_V1	BIT(0)
 327#define BIT_MASK_BLK_DESC_NUM	GENMASK(7, 4)
 328#define REG_DWBCN0_CTRL		0x0208
 329#define BIT_BCN_VALID		BIT(16)
 330#define REG_TXDMA_OFFSET_CHK	0x020C
 331#define BIT_DROP_DATA_EN	BIT(9)
 332#define REG_TXDMA_STATUS	0x0210
 333#define BTI_PAGE_OVF		BIT(2)
 334
 335#define REG_RQPN_NPQ		0x0214
 336#define BIT_MASK_NPQ		0xff
 337#define BIT_SHIFT_NPQ		0
 338#define BIT_MASK_EPQ		0xff
 339#define BIT_SHIFT_EPQ		16
 340#define BIT_RQPN_NPQ(x)		(((x) & BIT_MASK_NPQ) << BIT_SHIFT_NPQ)
 341#define BIT_RQPN_EPQ(x)		(((x) & BIT_MASK_EPQ) << BIT_SHIFT_EPQ)
 342#define BIT_RQPN_NE(n, e)	(BIT_RQPN_NPQ(n) | BIT_RQPN_EPQ(e))
 343
 344#define REG_AUTO_LLT		0x0224
 345#define BIT_AUTO_INIT_LLT	BIT(16)
 346#define REG_DWBCN1_CTRL		0x0228
 347#define REG_RQPN_CTRL_1		0x0228
 348#define REG_RQPN_CTRL_2		0x022C
 349#define BIT_LD_RQPN		BIT(31)
 350#define REG_FIFOPAGE_INFO_1	0x0230
 351#define REG_FIFOPAGE_INFO_2	0x0234
 352#define REG_FIFOPAGE_INFO_3	0x0238
 353#define REG_FIFOPAGE_INFO_4	0x023C
 354#define REG_FIFOPAGE_INFO_5	0x0240
 355#define REG_H2C_HEAD		0x0244
 356#define REG_H2C_TAIL		0x0248
 357#define REG_H2C_READ_ADDR	0x024C
 358#define REG_H2C_INFO		0x0254
 359#define REG_RXDMA_AGG_PG_TH	0x0280
 360#define BIT_RXDMA_AGG_PG_TH	GENMASK(7, 0)
 361#define BIT_DMA_AGG_TO_V1	GENMASK(15, 8)
 362#define BIT_EN_PRE_CALC		BIT(29)
 363#define REG_RXPKT_NUM		0x0284
 364#define BIT_RXDMA_REQ		BIT(19)
 365#define BIT_RW_RELEASE		BIT(18)
 366#define BIT_RXDMA_IDLE		BIT(17)
 367#define REG_RXDMA_STATUS	0x0288
 368#define REG_RXDMA_DPR		0x028C
 369#define REG_RXDMA_MODE		0x0290
 370#define BIT_DMA_MODE		BIT(1)
 371#define BIT_DMA_BURST_CNT	GENMASK(3, 2)
 372#define BIT_DMA_BURST_SIZE	GENMASK(5, 4)
 373#define BIT_DMA_BURST_SIZE_64	2
 374#define BIT_DMA_BURST_SIZE_512	1
 375#define BIT_DMA_BURST_SIZE_1024	0
 376
 377#define REG_RXPKTNUM		0x02B0
 378#define REG_EARLY_MODE_CONTROL	0x02BC
 379
 380#define REG_INT_MIG		0x0304
 381#define REG_HCI_MIX_CFG		0x03FC
 382#define BIT_PCIE_EMAC_PDN_AUX_TO_FAST_CLK BIT(26)
 383
 384#define REG_BCNQ_INFO		0x0418
 385#define BIT_MGQ_CPU_EMPTY	BIT(24)
 386#define REG_TXPKT_EMPTY		0x041A
 387#define REG_FWHW_TXQ_CTRL	0x0420
 388#define BIT_EN_BCNQ_DL		BIT(22)
 389#define BIT_EN_WR_FREE_TAIL	BIT(20)
 390#define REG_HWSEQ_CTRL		0x0423
 391
 392#define REG_BCNQ_BDNY_V1	0x0424
 393#define REG_BCNQ_BDNY		0x0424
 394#define REG_MGQ_BDNY		0x0425
 395#define REG_LIFETIME_EN		0x0426
 396#define BIT_BA_PARSER_EN	BIT(5)
 397#define REG_SPEC_SIFS		0x0428
 398#define REG_RETRY_LIMIT		0x042a
 399#define REG_DARFRC		0x0430
 400#define REG_DARFRCH		0x0434
 401#define REG_RARFRCH		0x043C
 402#define REG_RRSR		0x0440
 403#define BITS_RRSR_RSC		GENMASK(22, 21)
 404#define REG_ARFR0		0x0444
 405#define REG_ARFRH0		0x0448
 406#define REG_ARFR1_V1		0x044C
 407#define REG_ARFRH1_V1		0x0450
 408#define REG_CCK_CHECK		0x0454
 409#define BIT_CHECK_CCK_EN	BIT(7)
 410#define REG_AMPDU_MAX_TIME_V1	0x0455
 411#define REG_BCNQ1_BDNY_V1	0x0456
 412#define REG_AMPDU_MAX_TIME	0x0456
 413#define REG_AMPDU_MAX_LENGTH	0x0458
 414#define REG_WMAC_LBK_BF_HD	0x045D
 415#define REG_TX_HANG_CTRL	0x045E
 416#define BIT_EN_GNT_BT_AWAKE	BIT(3)
 417#define BIT_EN_EOF_V1		BIT(2)
 418#define REG_FAST_EDCA_CTRL	0x0460
 419#define REG_DATA_SC		0x0483
 420#define REG_ARFR2_V1		0x048C
 421#define REG_ARFRH2_V1		0x0490
 422#define REG_ARFR3_V1		0x0494
 423#define BIT_EXC_CODE		GENMASK(6, 2)
 424#define REG_ARFRH3_V1		0x0498
 425#define REG_ARFR4		0x049C
 426#define BIT_WL_RFK		BIT(0)
 427#define REG_ARFRH4		0x04A0
 428#define REG_ARFR5		0x04A4
 429#define REG_ARFRH5		0x04A8
 430#define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC
 431#define BIT_PRE_TX_CMD		BIT(6)
 432#define REG_QUEUE_CTRL		0x04C6
 433#define BIT_PTA_WL_TX_EN	BIT(4)
 434#define BIT_PTA_EDCCA_EN	BIT(5)
 435#define REG_SINGLE_AMPDU_CTRL	0x04C7
 436#define BIT_EN_SINGLE_APMDU	BIT(7)
 437#define REG_PROT_MODE_CTRL	0x04C8
 438#define REG_MAX_AGGR_NUM	0x04CA
 439#define REG_BAR_MODE_CTRL	0x04CC
 440#define REG_PRECNT_CTRL		0x04E5
 441#define BIT_BTCCA_CTRL		(BIT(0) | BIT(1))
 442#define BIT_EN_PRECNT		BIT(11)
 443#define REG_TX_RPT_CTRL		0x04EC
 444#define REG_TX_RPT_TIME		0x04F0
 445#define REG_DUMMY_PAGE4_V1	0x04FC
 446
 447#define REG_EDCA_VO_PARAM	0x0500
 448#define REG_EDCA_VI_PARAM	0x0504
 449#define REG_EDCA_BE_PARAM	0x0508
 450#define REG_EDCA_BK_PARAM	0x050C
 451#define BIT_MASK_TXOP_LMT	GENMASK(26, 16)
 452#define BIT_MASK_CWMAX		GENMASK(15, 12)
 453#define BIT_MASK_CWMIN		GENMASK(11, 8)
 454#define BIT_MASK_AIFS		GENMASK(7, 0)
 455#define REG_BCNTCFG		0x0510
 456#define REG_PIFS		0x0512
 457#define REG_SIFS		0x0514
 458#define BIT_SHIFT_SIFS_OFDM_CTX	8
 459#define BIT_SHIFT_SIFS_CCK_TRX	16
 460#define BIT_SHIFT_SIFS_OFDM_TRX	24
 461#define REG_AGGR_BREAK_TIME	0x051A
 462#define REG_SLOT		0x051B
 463#define REG_TX_PTCL_CTRL	0x0520
 464#define BIT_DIS_EDCCA		BIT(15)
 465#define BIT_SIFS_BK_EN		BIT(12)
 466#define REG_TXPAUSE		0x0522
 467#define BIT_AC_QUEUE		GENMASK(7, 0)
 468#define BIT_HIGH_QUEUE		BIT(5)
 469#define REG_RD_CTRL		0x0524
 470#define BIT_EDCCA_MSK_CNTDOWN_EN BIT(11)
 471#define BIT_DIS_TXOP_CFE	BIT(10)
 472#define BIT_DIS_LSIG_CFE	BIT(9)
 473#define BIT_DIS_STBC_CFE	BIT(8)
 474#define REG_TBTT_PROHIBIT	0x0540
 475#define BIT_SHIFT_TBTT_HOLD_TIME_AP 8
 476#define REG_RD_NAV_NXT		0x0544
 477#define REG_NAV_PROT_LEN	0x0546
 478#define REG_BCN_CTRL		0x0550
 479#define BIT_DIS_TSF_UDT		BIT(4)
 480#define BIT_EN_BCN_FUNCTION	BIT(3)
 481#define BIT_EN_TXBCN_RPT	BIT(2)
 482#define REG_BCN_CTRL_CLINT0	0x0551
 483#define REG_DRVERLYINT		0x0558
 484#define REG_BCNDMATIM		0x0559
 485#define REG_ATIMWND		0x055A
 486#define REG_USTIME_TSF		0x055C
 487#define REG_BCN_MAX_ERR		0x055D
 488#define REG_RXTSF_OFFSET_CCK	0x055E
 489#define REG_MISC_CTRL		0x0577
 490#define BIT_EN_FREE_CNT		BIT(3)
 491#define BIT_DIS_SECOND_CCA	(BIT(0) | BIT(1))
 492#define REG_HIQ_NO_LMT_EN	0x5A7
 493#define REG_DTIM_COUNTER_ROOT	0x5A8
 494#define BIT_HIQ_NO_LMT_EN_ROOT	BIT(0)
 495#define REG_TIMER0_SRC_SEL	0x05B4
 496#define BIT_TSFT_SEL_TIMER0	(BIT(4) | BIT(5) | BIT(6))
 497
 498#define REG_TCR			0x0604
 499#define BIT_PWRMGT_HWDATA_EN	BIT(7)
 500#define BIT_TCR_UPDATE_TIMIE	BIT(5)
 501#define BIT_TCR_UPDATE_HGQMD	BIT(4)
 502#define REG_RCR			0x0608
 503#define BIT_APP_FCS		BIT(31)
 504#define BIT_APP_MIC		BIT(30)
 505#define BIT_APP_ICV		BIT(29)
 506#define BIT_APP_PHYSTS		BIT(28)
 507#define BIT_APP_BASSN		BIT(27)
 508#define BIT_VHT_DACK		BIT(26)
 509#define BIT_TCPOFLD_EN		BIT(25)
 510#define BIT_ENMBID		BIT(24)
 511#define BIT_LSIGEN		BIT(23)
 512#define BIT_MFBEN		BIT(22)
 513#define BIT_DISCHKPPDLLEN	BIT(21)
 514#define BIT_PKTCTL_DLEN		BIT(20)
 515#define BIT_DISGCLK		BIT(19)
 516#define BIT_TIM_PARSER_EN	BIT(18)
 517#define BIT_BC_MD_EN		BIT(17)
 518#define BIT_UC_MD_EN		BIT(16)
 519#define BIT_RXSK_PERPKT		BIT(15)
 520#define BIT_HTC_LOC_CTRL	BIT(14)
 521#define BIT_RPFM_CAM_ENABLE	BIT(12)
 522#define BIT_TA_BCN		BIT(11)
 523#define BIT_RCR_ADF		BIT(11)
 524#define BIT_DISDECMYPKT		BIT(10)
 525#define BIT_AICV		BIT(9)
 526#define BIT_ACRC32		BIT(8)
 527#define BIT_CBSSID_BCN		BIT(7)
 528#define BIT_CBSSID_DATA		BIT(6)
 529#define BIT_APWRMGT		BIT(5)
 530#define BIT_ADD3		BIT(4)
 531#define BIT_AB			BIT(3)
 532#define BIT_AM			BIT(2)
 533#define BIT_APM			BIT(1)
 534#define BIT_AAP			BIT(0)
 535#define REG_RX_PKT_LIMIT	0x060C
 536#define REG_RX_DRVINFO_SZ	0x060F
 537#define BIT_APP_PHYSTS		BIT(28)
 538#define REG_MAR			0x0620
 539#define REG_USTIME_EDCA		0x0638
 540#define REG_ACKTO_CCK		0x0639
 541#define REG_MAC_SPEC_SIFS	0x063A
 542#define REG_RESP_SIFS_CCK	0x063C
 543#define REG_RESP_SIFS_OFDM	0x063E
 544#define REG_ACKTO		0x0640
 545#define REG_EIFS		0x0642
 546#define REG_NAV_CTRL		0x0650
 547#define REG_WMAC_TRXPTCL_CTL	0x0668
 548#define BIT_RFMOD		(BIT(7) | BIT(8))
 549#define BIT_RFMOD_80M		BIT(8)
 550#define BIT_RFMOD_40M		BIT(7)
 551#define REG_WMAC_TRXPTCL_CTL_H	0x066C
 552#define REG_WKFMCAM_CMD		0x0698
 553#define BIT_WKFCAM_POLLING_V1	BIT(31)
 554#define BIT_WKFCAM_CLR_V1	BIT(30)
 555#define BIT_WKFCAM_WE		BIT(16)
 556#define BIT_SHIFT_WKFCAM_ADDR_V2	8
 557#define BIT_MASK_WKFCAM_ADDR_V2		0xff
 558#define BIT_WKFCAM_ADDR_V2(x)						       \
 559	(((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2)
 560#define REG_WKFMCAM_RWD         0x069C
 561#define BIT_WKFMCAM_VALID	BIT(31)
 562#define BIT_WKFMCAM_BC		BIT(26)
 563#define BIT_WKFMCAM_MC		BIT(25)
 564#define BIT_WKFMCAM_UC		BIT(24)
 565
 566#define REG_RXFLTMAP0		0x06A0
 567#define REG_RXFLTMAP1		0x06A2
 568#define REG_RXFLTMAP2		0x06A4
 569#define REG_RXFLTMAP4		0x068A
 570#define REG_BT_COEX_TABLE0	0x06C0
 571#define REG_BT_COEX_TABLE1	0x06C4
 572#define REG_BT_COEX_BRK_TABLE	0x06C8
 573#define REG_BT_COEX_TABLE_H	0x06CC
 574#define REG_BT_COEX_TABLE_H1	0x06CD
 575#define REG_BT_COEX_TABLE_H2	0x06CE
 576#define REG_BT_COEX_TABLE_H3	0x06CF
 577#define REG_BBPSF_CTRL		0x06DC
 578
 579#define REG_BT_COEX_V2		0x0762
 580#define BIT_GNT_BT_POLARITY	BIT(12)
 581#define BIT_LTE_COEX_EN		BIT(7)
 582#define REG_GNT_BT		0x0765
 583#define BIT_PTA_SW_CTL		GENMASK(4, 3)
 584#define REG_BT_COEX_ENH_INTR_CTRL	0x76E
 585#define BIT_R_GRANTALL_WLMASK	BIT(3)
 586#define BIT_STATIS_BT_EN	BIT(2)
 587#define REG_BT_ACT_STATISTICS	0x0770
 588#define REG_BT_ACT_STATISTICS_1	0x0774
 589#define REG_BT_STAT_CTRL	0x0778
 590#define REG_BT_TDMA_TIME	0x0790
 591#define BIT_MASK_SAMPLE_RATE	GENMASK(5, 0)
 592#define REG_LTR_IDLE_LATENCY	0x0798
 593#define REG_LTR_ACTIVE_LATENCY	0x079C
 594#define REG_LTR_CTRL_BASIC	0x07A4
 595#define REG_WMAC_OPTION_FUNCTION 0x07D0
 596#define REG_WMAC_OPTION_FUNCTION_1 0x07D4
 597
 598#define REG_FPGA0_RFMOD		0x0800
 599#define BIT_CCKEN		BIT(24)
 600#define BIT_OFDMEN		BIT(25)
 601#define REG_CCK_RPT_FORMAT	0x0804
 602#define BIT_CCK_RPT_FORMAT	BIT(16)
 603#define REG_RXPSEL		0x0808
 604#define BIT_RX_PSEL_RST		(BIT(28) | BIT(29))
 605#define REG_TXPSEL		0x080C
 606#define REG_RX_GAIN_EN		0x081c
 607#define REG_CCASEL		0x082C
 608#define REG_PDMFTH		0x0830
 609#define REG_BWINDICATION	0x0834
 610#define REG_CCA2ND		0x0838
 611#define REG_L1PKTH		0x0848
 612#define REG_CLKTRK		0x0860
 613#define REG_CSI_MASK_SETTING1	0x0874
 614#define REG_NBI_SETTING		0x087c
 615#define BIT_NBI_ENABLE		BIT(13)
 616#define REG_CSI_FIX_MASK0	0x0880
 617#define REG_CSI_FIX_MASK1	0x0884
 618#define REG_CSI_FIX_MASK6	0x0898
 619#define REG_CSI_FIX_MASK7	0x089c
 620#define REG_ADCCLK		0x08AC
 621#define REG_HSSI_READ		0x08B0
 622#define REG_FPGA0_XCD_RF_PARA	0x08B4
 623#define REG_RX_MCS_LIMIT	0x08BC
 624#define REG_ADC160		0x08C4
 625#define REG_DBGSEL		0x08fc
 626#define REG_ANTSEL_SW		0x0900
 627#define REG_DAC_RSTB		0x090c
 628#define REG_PSD			0x0910
 629#define BIT_PSD_INI		GENMASK(23, 22)
 630#define REG_SINGLE_TONE_CONT_TX	0x0914
 631#define REG_AGC_TABLE		0x0958
 632#define REG_RFE_CTRL_E		0x0974
 633#define REG_2ND_CCA_CTRL	0x0976
 634#define REG_IQK_COM00		0x0978
 635#define REG_IQK_COM32		0x097c
 636#define REG_IQK_COM64		0x0980
 637#define REG_IQK_COM96		0x0984
 638
 639#define REG_FAS			0x09a4
 640#define REG_RXSB		0x0a00
 641#define BIT_RXSB_ANA_DIV	BIT(15)
 642#define REG_CCK_RX		0x0a04
 643#define REG_CCK_PD_TH		0x0a0a
 644#define REG_PRECTRL		0x0a14
 645#define BIT_DIS_CO_PATHSEL	BIT(7)
 646#define BIT_IQ_WGT		GENMASK(9, 8)
 647#define REG_CCA_MF		0x0a20
 648#define BIT_MBC_WIN		GENMASK(5, 4)
 649#define REG_CCK0_TX_FILTER1	0x0a20
 650#define REG_CCK0_TX_FILTER2	0x0a24
 651#define REG_CCK0_DEBUG_PORT	0x0a28
 652#define REG_CCK0_FAREPORT	0x0a2c
 653#define BIT_CCK0_2RX		BIT(18)
 654#define BIT_CCK0_MRC		BIT(22)
 655#define REG_FA_CCK		0x0a5c
 656
 657#define REG_DIS_DPD		0x0a70
 658#define DIS_DPD_MASK		GENMASK(9, 0)
 659#define DIS_DPD_RATE6M		BIT(0)
 660#define DIS_DPD_RATE9M		BIT(1)
 661#define DIS_DPD_RATEMCS0	BIT(2)
 662#define DIS_DPD_RATEMCS1	BIT(3)
 663#define DIS_DPD_RATEMCS8	BIT(4)
 664#define DIS_DPD_RATEMCS9	BIT(5)
 665#define DIS_DPD_RATEVHT1SS_MCS0	BIT(6)
 666#define DIS_DPD_RATEVHT1SS_MCS1	BIT(7)
 667#define DIS_DPD_RATEVHT2SS_MCS0	BIT(8)
 668#define DIS_DPD_RATEVHT2SS_MCS1	BIT(9)
 669#define DIS_DPD_RATEALL		GENMASK(9, 0)
 670
 671#define REG_CCA			0x0a70
 672#define BIT_CCA_CO		BIT(7)
 673#define REG_ANTSEL		0x0a74
 674#define BIT_ANT_BYCO		BIT(8)
 675#define REG_CCKTX		0x0a84
 676#define BIT_CMB_CCA_2R		BIT(28)
 677
 678#define REG_CNTRST		0x0b58
 679
 680#define REG_3WIRE_SWA		0x0c00
 681#define REG_RX_IQC_AB_A		0x0c10
 682#define REG_RX_IQC_CD_A		0x0c14
 683#define REG_TXSCALE_A		0x0c1c
 684#define BB_SWING_MASK		GENMASK(31, 21)
 685#define REG_TX_AGC_A_CCK_11_CCK_1		0xc20
 686#define REG_TX_AGC_A_OFDM18_OFDM6		0xc24
 687#define REG_TX_AGC_A_OFDM54_OFDM24		0xc28
 688#define REG_TX_AGC_A_MCS3_MCS0			0xc2c
 689#define REG_TX_AGC_A_MCS7_MCS4			0xc30
 690#define REG_TX_AGC_A_MCS11_MCS8			0xc34
 691#define REG_TX_AGC_A_MCS15_MCS12		0xc38
 692#define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0	0xc3c
 693#define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4	0xc40
 694#define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8	0xc44
 695#define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2	0xc48
 696#define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6	0xc4c
 697#define REG_RXIGI_A		0x0c50
 698#define REG_TX_PWR_TRAINING_A	0x0c54
 699#define REG_CK_MONHA		0x0c5c
 700#define REG_AFE_PWR1_A		0x0c60
 701#define REG_AFE_PWR2_A		0x0c64
 702#define REG_RX_WAIT_CCA_TX_CCK_RFON_A	0x0c68
 703#define REG_OFDM0_XA_TX_IQ_IMBALANCE	0x0c80
 704#define REG_OFDM0_A_TX_AFE	0x0c84
 705#define REG_OFDM0_XB_TX_IQ_IMBALANCE	0x0c88
 706#define REG_TSSI_TRK_SW		0x0c8c
 707#define REG_LSSI_WRITE_A	0x0c90
 708#define REG_PREDISTA		0x0c90
 709#define REG_TXAGCIDX		0x0c94
 710#define REG_TX_AGC_A		0x0c94
 711#define REG_RFE_PINMUX_A	0x0cb0
 712#define REG_RFE_INV_A		0x0cb4
 713#define REG_RFE_CTRL8		0x0cb4
 714#define BIT_MASK_RFE_SEL89	GENMASK(7, 0)
 715#define PTA_CTRL_PIN		0x66
 716#define DPDT_CTRL_PIN		0x77
 717#define RFE_INV_MASK		0x3ff00000
 718#define REG_RFECTL_A		0x0cb8
 719#define REG_RFE_INV0		0x0cbc
 720#define REG_RFE_INV8		0x0cbd
 721#define BIT_MASK_RFE_INV89	GENMASK(1, 0)
 722#define REG_RFE_INV16		0x0cbe
 723#define BIT_RFE_BUF_EN		BIT(3)
 724
 725#define REG_IQK_DPD_CFG		0x0cc4
 726#define REG_CFG_PMPD		0x0cc8
 727#define REG_IQC_Y		0x0ccc
 728#define REG_IQC_X		0x0cd4
 729#define REG_INTPO_SETA		0x0ce8
 730
 731#define REG_IQKA_END		0x0d00
 732#define REG_PI_READ_A		0x0d04
 733#define REG_SI_READ_A		0x0d08
 734#define REG_IQKB_END		0x0d40
 735#define REG_PI_READ_B		0x0d44
 736#define REG_SI_READ_B		0x0d48
 737
 738#define REG_3WIRE_SWB		0x0e00
 739#define REG_RX_IQC_AB_B		0x0e10
 740#define REG_RX_IQC_CD_B		0x0e14
 741#define REG_TXSCALE_B		0x0e1c
 742#define REG_TX_AGC_B_CCK_11_CCK_1		0xe20
 743#define REG_TX_AGC_B_OFDM18_OFDM6		0xe24
 744#define REG_TX_AGC_B_OFDM54_OFDM24		0xe28
 745#define REG_TX_AGC_B_MCS3_MCS0			0xe2c
 746#define REG_TX_AGC_B_MCS7_MCS4			0xe30
 747#define REG_TX_AGC_B_MCS11_MCS8			0xe34
 748#define REG_TX_AGC_B_MCS15_MCS12		0xe38
 749#define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0	0xe3c
 750#define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4	0xe40
 751#define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8	0xe44
 752#define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2	0xe48
 753#define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6	0xe4c
 754#define REG_RXIGI_B		0x0e50
 755#define REG_TX_PWR_TRAINING_B	0x0e54
 756#define REG_CK_MONHB		0x0e5c
 757#define REG_AFE_PWR1_B		0x0e60
 758#define REG_AFE_PWR2_B		0x0e64
 759#define REG_RX_WAIT_CCA_TX_CCK_RFON_B	0x0e68
 760#define REG_TXTONEB		0x0e80
 761#define REG_RXTONEB		0x0e84
 762#define REG_TXPITMB		0x0e88
 763#define REG_RXPITMB		0x0e8c
 764#define REG_LSSI_WRITE_B	0x0e90
 765#define REG_PREDISTB		0x0e90
 766#define REG_INIDLYB		0x0e94
 767#define REG_TX_AGC_B		0x0e94
 768#define REG_RFE_PINMUX_B	0x0eb0
 769#define REG_RFE_INV_B		0x0eb4
 770#define REG_RFECTL_B		0x0eb8
 771#define REG_BPBDB		0x0ec4
 772#define REG_PHYTXONB		0x0ec8
 773#define REG_IQKYB		0x0ecc
 774#define REG_IQKXB		0x0ed4
 775#define REG_INTPO_SETB		0x0ee8
 776
 777#define REG_CRC_CCK		0x0f04
 778#define REG_CCA_OFDM		0x0f08
 779#define REG_CRC_VHT		0x0f0c
 780#define REG_CRC_HT		0x0f10
 781#define REG_CRC_OFDM		0x0f14
 782#define REG_FA_OFDM		0x0f48
 783#define REG_DBGRPT		0x0fa0
 784#define REG_CCA_CCK		0x0fcc
 785
 786#define REG_SYS_CFG3_8814A	0x1000
 787
 788#define REG_ANAPARSW_MAC_0	0x1010
 789#define BIT_CF_L_V2		GENMASK(29, 28)
 790
 791#define REG_ANAPAR_XTAL_0	0x1040
 792#define BIT_XCAP_0		GENMASK(23, 10)
 793#define REG_CPU_DMEM_CON	0x1080
 794#define BIT_WL_PLATFORM_RST	BIT(16)
 795#define BIT_WL_SECURITY_CLK	BIT(15)
 796#define BIT_DDMA_EN		BIT(8)
 797
 798#define REG_SW_MDIO		0x10C0
 799
 800#define REG_H2C_PKT_READADDR	0x10D0
 801#define REG_H2C_PKT_WRITEADDR	0x10D4
 802#define REG_FW_DBG6		0x10F8
 803#define REG_FW_DBG7		0x10FC
 804#define FW_KEY_MASK		0xffffff00
 805
 806#define REG_CR_EXT		0x1100
 807
 808#define REG_FT1IMR		0x1138
 809#define BIT_FS_H2C_CMD_OK_INT_EN BIT(25)
 810#define REG_FT1ISR		0x113c
 811#define BIT_FS_H2C_CMD_OK_INT	BIT(25)
 812#define REG_DDMA_CH0SA		0x1200
 813#define REG_DDMA_CH0DA		0x1204
 814#define REG_DDMA_CH0CTRL	0x1208
 815#define BIT_DDMACH0_OWN		BIT(31)
 816#define BIT_DDMACH0_CHKSUM_EN	BIT(29)
 817#define BIT_DDMACH0_CHKSUM_STS	BIT(27)
 818#define BIT_DDMACH0_DDMA_MODE	BIT(26)
 819#define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25)
 820#define BIT_DDMACH0_CHKSUM_CONT	BIT(24)
 821#define BIT_MASK_DDMACH0_DLEN	0x3ffff
 822
 823#define REG_H2CQ_CSR		0x1330
 824#define BIT_H2CQ_FULL		BIT(31)
 825#define REG_FAST_EDCA_VOVI_SETTING 0x1448
 826#define REG_FAST_EDCA_BEBK_SETTING 0x144C
 827
 828#define REG_RXPSF_CTRL		0x1610
 829#define BIT_RXGCK_FIFOTHR_EN	BIT(28)
 830
 831#define BIT_SHIFT_RXGCK_VHT_FIFOTHR 26
 832#define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3
 833#define BIT_RXGCK_VHT_FIFOTHR(x)                                               \
 834	(((x) & BIT_MASK_RXGCK_VHT_FIFOTHR) << BIT_SHIFT_RXGCK_VHT_FIFOTHR)
 835#define BITS_RXGCK_VHT_FIFOTHR                                                 \
 836	(BIT_MASK_RXGCK_VHT_FIFOTHR << BIT_SHIFT_RXGCK_VHT_FIFOTHR)
 837
 838#define BIT_SHIFT_RXGCK_HT_FIFOTHR 24
 839#define BIT_MASK_RXGCK_HT_FIFOTHR 0x3
 840#define BIT_RXGCK_HT_FIFOTHR(x)                                                \
 841	(((x) & BIT_MASK_RXGCK_HT_FIFOTHR) << BIT_SHIFT_RXGCK_HT_FIFOTHR)
 842#define BITS_RXGCK_HT_FIFOTHR                                                  \
 843	(BIT_MASK_RXGCK_HT_FIFOTHR << BIT_SHIFT_RXGCK_HT_FIFOTHR)
 844
 845#define BIT_SHIFT_RXGCK_OFDM_FIFOTHR 22
 846#define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3
 847#define BIT_RXGCK_OFDM_FIFOTHR(x)                                              \
 848	(((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR) << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)
 849#define BITS_RXGCK_OFDM_FIFOTHR                                                \
 850	(BIT_MASK_RXGCK_OFDM_FIFOTHR << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)
 851
 852#define BIT_SHIFT_RXGCK_CCK_FIFOTHR 20
 853#define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3
 854#define BIT_RXGCK_CCK_FIFOTHR(x)                                               \
 855	(((x) & BIT_MASK_RXGCK_CCK_FIFOTHR) << BIT_SHIFT_RXGCK_CCK_FIFOTHR)
 856#define BITS_RXGCK_CCK_FIFOTHR                                                 \
 857	(BIT_MASK_RXGCK_CCK_FIFOTHR << BIT_SHIFT_RXGCK_CCK_FIFOTHR)
 858
 859#define BIT_RXGCK_OFDMCCA_EN BIT(16)
 860
 861#define BIT_SHIFT_RXPSF_PKTLENTHR 13
 862#define BIT_MASK_RXPSF_PKTLENTHR 0x7
 863#define BIT_RXPSF_PKTLENTHR(x)                                                 \
 864	(((x) & BIT_MASK_RXPSF_PKTLENTHR) << BIT_SHIFT_RXPSF_PKTLENTHR)
 865#define BITS_RXPSF_PKTLENTHR                                                   \
 866	(BIT_MASK_RXPSF_PKTLENTHR << BIT_SHIFT_RXPSF_PKTLENTHR)
 867#define BIT_CLEAR_RXPSF_PKTLENTHR(x) ((x) & (~BITS_RXPSF_PKTLENTHR))
 868#define BIT_SET_RXPSF_PKTLENTHR(x, v)                                          \
 869	(BIT_CLEAR_RXPSF_PKTLENTHR(x) | BIT_RXPSF_PKTLENTHR(v))
 870
 871#define BIT_RXPSF_CTRLEN	BIT(12)
 872#define BIT_RXPSF_VHTCHKEN	BIT(11)
 873#define BIT_RXPSF_HTCHKEN	BIT(10)
 874#define BIT_RXPSF_OFDMCHKEN	BIT(9)
 875#define BIT_RXPSF_CCKCHKEN	BIT(8)
 876#define BIT_RXPSF_OFDMRST	BIT(7)
 877#define BIT_RXPSF_CCKRST	BIT(6)
 878#define BIT_RXPSF_MHCHKEN	BIT(5)
 879#define BIT_RXPSF_CONT_ERRCHKEN	BIT(4)
 880#define BIT_RXPSF_ALL_ERRCHKEN	BIT(3)
 881
 882#define BIT_SHIFT_RXPSF_ERRTHR 0
 883#define BIT_MASK_RXPSF_ERRTHR 0x7
 884#define BIT_RXPSF_ERRTHR(x)                                                    \
 885	(((x) & BIT_MASK_RXPSF_ERRTHR) << BIT_SHIFT_RXPSF_ERRTHR)
 886#define BITS_RXPSF_ERRTHR (BIT_MASK_RXPSF_ERRTHR << BIT_SHIFT_RXPSF_ERRTHR)
 887#define BIT_CLEAR_RXPSF_ERRTHR(x) ((x) & (~BITS_RXPSF_ERRTHR))
 888#define BIT_GET_RXPSF_ERRTHR(x)                                                \
 889	(((x) >> BIT_SHIFT_RXPSF_ERRTHR) & BIT_MASK_RXPSF_ERRTHR)
 890#define BIT_SET_RXPSF_ERRTHR(x, v)                                             \
 891	(BIT_CLEAR_RXPSF_ERRTHR(x) | BIT_RXPSF_ERRTHR(v))
 892
 893#define REG_RXPSF_TYPE_CTRL	0x1614
 894#define REG_GENERAL_OPTION	0x1664
 895#define BIT_DUMMY_FCS_READY_MASK_EN BIT(9)
 896
 897#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1		0x1700
 898#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1	0x1704
 899#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1	0x1708
 900#define LTECOEX_READY		BIT(29)
 901#define LTECOEX_ACCESS_CTRL REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1
 902#define LTECOEX_WRITE_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1
 903#define LTECOEX_READ_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1
 904
 905#define REG_RX_IQC_AB_C		0x1810
 906#define REG_RX_IQC_CD_C		0x1814
 907#define REG_TXSCALE_C		0x181c
 908#define REG_CK_MONHC		0x185c
 909#define REG_AFE_PWR1_C		0x1860
 910#define REG_IGN_GNT_BT1	0x1860
 911#define REG_TX_AGC_C		0x1894
 912#define REG_RFE_PINMUX_C	0x18b4
 913
 914#define REG_RFESEL_CTRL	0x1990
 915#define REG_AGC_TBL		0x1998
 916
 917#define REG_RX_IQC_AB_D		0x1a10
 918#define REG_RX_IQC_CD_D		0x1a14
 919#define REG_TXSCALE_D		0x1a1c
 920#define REG_CK_MONHD		0x1a5c
 921#define REG_AFE_PWR1_D		0x1a60
 922#define REG_TX_AGC_D		0x1a94
 923#define REG_RFE_PINMUX_D	0x1ab4
 924#define REG_RFE_INVSEL_D	0x1abc
 925#define BIT_RFE_SELSW0_D	GENMASK(27, 20)
 926
 927#define REG_NOMASK_TXBT	0x1ca7
 928#define REG_ANAPAR	0x1c30
 929#define BIT_ANAPAR_BTPS	BIT(22)
 930#define REG_RSTB_SEL	0x1c38
 931#define BIT_DAC_OFF_ENABLE	BIT(4)
 932#define BIT_PI_IGNORE_GNT_BT	BIT(3)
 933#define BIT_NOMASK_TXBT_ENABLE	BIT(3)
 934
 935#define REG_HRCV_MSG	0x1cf
 936
 937#define REG_EDCCA_REPORT	0x2d38
 938#define BIT_EDCCA_FLAG		BIT(24)
 939
 940#define REG_IGN_GNTBT4	0x4160
 941
 942#define REG_USB_MOD	0xf008
 943#define REG_USB3_RXITV	0xf050
 944#define REG_USB2_PHY_ADR	0xfe40
 945#define REG_USB2_PHY_DAT	0xfe41
 946#define REG_USB2_PHY_CMD	0xfe42
 947#define BIT_USB2_PHY_CMD_TRG	0x81
 948#define REG_USB_HRPWM	0xfe58
 949#define REG_USB3_PHY_ADR	0xff0c
 950#define REG_USB3_PHY_DAT_L	0xff0d
 951#define REG_USB3_PHY_DAT_H	0xff0e
 952#define BIT_USB3_PHY_ADR_WR	BIT(7)
 953#define BIT_USB3_PHY_ADR_RD	BIT(6)
 954#define BIT_USB3_PHY_ADR_MASK	GENMASK(5, 0)
 955
 956#define RF_MODE		0x00
 957#define RF_MODOPT	0x01
 958#define RF_WLINT	0x01
 959#define RF_WLSEL	0x02
 960#define RF_DTXLOK	0x08
 961#define RF_CFGCH	0x18
 962#define BIT_BAND	GENMASK(18, 16)
 963#define RF18_BAND_MASK	(BIT(16) | BIT(9) | BIT(8))
 964#define RF18_CHANNEL_MASK	(MASKBYTE0)
 965#define RF18_RFSI_MASK	(BIT(18) | BIT(17))
 966#define RF_RCK1_V1	0x1c
 967#define RF_RCK		0x1d
 968#define RF_MODE_TABLE_ADDR	0x30
 969#define RF_MODE_TABLE_DATA0	0x31
 970#define RF_MODE_TABLE_DATA1	0x32
 971#define RF_LUTWA	0x33
 972#define RF_LUTWD1	0x3e
 973#define RF_LUTWD0	0x3f
 974#define BIT_GAIN_EXT	BIT(12)
 975#define BIT_DATA_L	GENMASK(11, 0)
 976#define RF_T_METER	0x42
 977#define RF_BSPAD	0x54
 978#define RF_GAINTX	0x56
 979#define RF_TXMOD	0x58
 980#define RF_TXATANK	0x64
 981#define RF_TXA_PREPAD	0x65
 982#define RF_TRXIQ	0x66
 983#define RF_RXIQGEN	0x8d
 984#define RF_RXBB2	0x8f
 985#define RF_SYN_PFD	0xb0
 986#define RF_LCK		0xb4
 987#define RF_XTALX2	0xb8
 988#define RF_SYN_CTRL	0xbb
 989#define RF_MALSEL	0xbe
 990#define RF_SYN_AAC	0xc9
 991#define RF_AAC_CTRL	0xca
 992#define RF_FAST_LCK	0xcc
 993#define RF_RCKD		0xde
 994#define RF_TXADBG	0xde
 995#define RF_LUTDBG	0xdf
 996#define BIT_TXA_TANK	BIT(4)
 997#define RF_LUTWE2	0xee
 998#define RF_LUTWE	0xef
 999
1000#define LTE_COEX_CTRL	0x38
1001#define LTE_WL_TRX_CTRL	0xa0
1002#define LTE_BT_TRX_CTRL	0xa4
1003
1004#endif