phy.h

  1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
  2/* Copyright(c) 2018-2019  Realtek Corporation
  3 */
  4
  5#ifndef __RTW_PHY_H_
  6#define __RTW_PHY_H_
  7
  8#include "debug.h"
  9
 10extern const u8 rtw_cck_rates[];
 11extern const u8 rtw_ofdm_rates[];
 12extern const u8 rtw_ht_1s_rates[];
 13extern const u8 rtw_ht_2s_rates[];
 14extern const u8 rtw_vht_1s_rates[];
 15extern const u8 rtw_vht_2s_rates[];
 16extern const u8 rtw_ht_3s_rates[];
 17extern const u8 rtw_ht_4s_rates[];
 18extern const u8 rtw_vht_3s_rates[];
 19extern const u8 rtw_vht_4s_rates[];
 20extern const u8 * const rtw_rate_section[];
 21extern const u8 rtw_rate_size[];
 22
 23void rtw_phy_init(struct rtw_dev *rtwdev);
 24void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev);
 25u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num);
 26u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
 27		    u32 addr, u32 mask);
 28u32 rtw_phy_read_rf_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
 29			 u32 addr, u32 mask);
 30bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
 31			       u32 addr, u32 mask, u32 data);
 32bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
 33			  u32 addr, u32 mask, u32 data);
 34bool rtw_phy_write_rf_reg_mix(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
 35			      u32 addr, u32 mask, u32 data);
 36void rtw_phy_setup_phy_cond(struct rtw_dev *rtwdev, u32 pkg);
 37void rtw_parse_tbl_phy_cond(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
 38void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
 39void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
 40void rtw_phy_cfg_mac(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
 41		     u32 addr, u32 data);
 42void rtw_phy_cfg_agc(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
 43		     u32 addr, u32 data);
 44void rtw_phy_cfg_bb(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
 45		    u32 addr, u32 data);
 46void rtw_phy_cfg_rf(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
 47		    u32 addr, u32 data);
 48void rtw_phy_init_tx_power(struct rtw_dev *rtwdev);
 49void rtw_phy_load_tables(struct rtw_dev *rtwdev);
 50u8 rtw_phy_get_tx_power_index(struct rtw_dev *rtwdev, u8 rf_path, u8 rate,
 51			      enum rtw_bandwidth bw, u8 channel, u8 regd);
 52void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel);
 53void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal);
 54void rtw_phy_tx_power_limit_config(struct rtw_hal *hal);
 55void rtw_phy_pwrtrack_avg(struct rtw_dev *rtwdev, u8 thermal, u8 path);
 56bool rtw_phy_pwrtrack_thermal_changed(struct rtw_dev *rtwdev, u8 thermal,
 57				      u8 path);
 58u8 rtw_phy_pwrtrack_get_delta(struct rtw_dev *rtwdev, u8 path);
 59s8 rtw_phy_pwrtrack_get_pwridx(struct rtw_dev *rtwdev,
 60			       struct rtw_swing_table *swing_table,
 61			       u8 tbl_path, u8 therm_path, u8 delta);
 62bool rtw_phy_pwrtrack_need_lck(struct rtw_dev *rtwdev);
 63bool rtw_phy_pwrtrack_need_iqk(struct rtw_dev *rtwdev);
 64void rtw_phy_config_swing_table(struct rtw_dev *rtwdev,
 65				struct rtw_swing_table *swing_table);
 66void rtw_phy_set_edcca_th(struct rtw_dev *rtwdev, u8 l2h, u8 h2l);
 67void rtw_phy_adaptivity_set_mode(struct rtw_dev *rtwdev);
 68void rtw_phy_parsing_cfo(struct rtw_dev *rtwdev,
 69			 struct rtw_rx_pkt_stat *pkt_stat);
 70void rtw_phy_tx_path_diversity(struct rtw_dev *rtwdev);
 71
 72struct rtw_txpwr_lmt_cfg_pair {
 73	u8 regd;
 74	u8 band;
 75	u8 bw;
 76	u8 rs;
 77	u8 ch;
 78	s8 txpwr_lmt;
 79};
 80
 81struct rtw_phy_pg_cfg_pair {
 82	u32 band;
 83	u32 rf_path;
 84	u32 tx_num;
 85	u32 addr;
 86	u32 bitmask;
 87	u32 data;
 88};
 89
 90#define RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, path)	\
 91const struct rtw_table name ## _tbl = {			\
 92	.data = name,					\
 93	.size = ARRAY_SIZE(name),			\
 94	.parse = rtw_parse_tbl_phy_cond,		\
 95	.do_cfg = cfg,					\
 96	.rf_path = path,				\
 97}
 98
 99#define RTW_DECL_TABLE_PHY_COND(name, cfg)		\
100	RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, 0)
101
102#define RTW_DECL_TABLE_RF_RADIO(name, path)		\
103	RTW_DECL_TABLE_PHY_COND_CORE(name, rtw_phy_cfg_rf, RF_PATH_ ## path)
104
105#define RTW_DECL_TABLE_BB_PG(name)			\
106const struct rtw_table name ## _tbl = {			\
107	.data = name,					\
108	.size = ARRAY_SIZE(name),			\
109	.parse = rtw_parse_tbl_bb_pg,			\
110}
111
112#define RTW_DECL_TABLE_TXPWR_LMT(name)			\
113const struct rtw_table name ## _tbl = {			\
114	.data = name,					\
115	.size = ARRAY_SIZE(name),			\
116	.parse = rtw_parse_tbl_txpwr_lmt,		\
117}
118
119static inline const struct rtw_rfe_def *rtw_get_rfe_def(struct rtw_dev *rtwdev)
120{
121	const struct rtw_chip_info *chip = rtwdev->chip;
122	struct rtw_efuse *efuse = &rtwdev->efuse;
123	const struct rtw_rfe_def *rfe_def = NULL;
124
125	if (chip->rfe_defs_size == 0)
126		return NULL;
127
128	if (efuse->rfe_option < chip->rfe_defs_size)
129		rfe_def = &chip->rfe_defs[efuse->rfe_option];
130
131	rtw_dbg(rtwdev, RTW_DBG_PHY, "use rfe_def[%d]\n", efuse->rfe_option);
132	return rfe_def;
133}
134
135static inline int rtw_check_supported_rfe(struct rtw_dev *rtwdev)
136{
137	const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
138
139	if (!rfe_def || !rfe_def->phy_pg_tbl || !rfe_def->txpwr_lmt_tbl) {
140		rtw_err(rtwdev, "rfe %d isn't supported\n",
141			rtwdev->efuse.rfe_option);
142		return -ENODEV;
143	}
144
145	return 0;
146}
147
148void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi);
149
150struct rtw_power_params {
151	u8 pwr_base;
152	s8 pwr_offset;
153	s8 pwr_limit;
154	s8 pwr_remnant;
155	s8 pwr_sar;
156};
157
158void
159rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path,
160			u8 rate, u8 bw, u8 ch, u8 regd,
161			struct rtw_power_params *pwr_param);
162
163enum rtw_phy_cck_pd_lv {
164	CCK_PD_LV0,
165	CCK_PD_LV1,
166	CCK_PD_LV2,
167	CCK_PD_LV3,
168	CCK_PD_LV4,
169	CCK_PD_LV_MAX,
170};
171
172#define	MASKBYTE0		0xff
173#define	MASKBYTE1		0xff00
174#define	MASKBYTE2		0xff0000
175#define	MASKBYTE3		0xff000000
176#define	MASKHWORD		0xffff0000
177#define	MASKLWORD		0x0000ffff
178#define	MASKDWORD		0xffffffff
179#define RFREG_MASK		0xfffff
180
181#define	MASK7BITS		0x7f
182#define	MASK12BITS		0xfff
183#define	MASKH4BITS		0xf0000000
184#define	MASK20BITS		0xfffff
185#define	MASK24BITS		0xffffff
186
187#define MASKH3BYTES		0xffffff00
188#define MASKL3BYTES		0x00ffffff
189#define MASKBYTE2HIGHNIBBLE	0x00f00000
190#define MASKBYTE3LOWNIBBLE	0x0f000000
191#define	MASKL3BYTES		0x00ffffff
192
193#define CCK_FA_AVG_RESET 0xffffffff
194
195#define LSSI_READ_ADDR_MASK	0x7f800000
196#define LSSI_READ_EDGE_MASK	0x80000000
197#define LSSI_READ_DATA_MASK	0xfffff
198
199#define RRSR_RATE_ORDER_MAX	0xfffff
200#define RRSR_RATE_ORDER_CCK_LEN	4
201
202#endif