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mac.c
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linux-6.19.14/drivers/net/wireless/realtek/rtw88/mac.c
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5#include "main.h" 6#include "mac.h" 7#include "reg.h" 8#include "fw.h" 9#include "debug.h" 10#include "sdio.h" 11 12void rtw_set_channel_mac(struct rtw_dev *rtwdev, u8 channel, u8 bw, 13 u8 primary_ch_idx) 14{ 15 u8 txsc40 = 0, txsc20 = 0; 16 u32 value32; 17 u8 value8; 18 19 txsc20 = primary_ch_idx; 20 if (bw == RTW_CHANNEL_WIDTH_80) { 21 if (txsc20 == RTW_SC_20_UPPER || txsc20 == RTW_SC_20_UPMOST) 22 txsc40 = RTW_SC_40_UPPER; 23 else 24 txsc40 = RTW_SC_40_LOWER; 25 } 26 rtw_write8(rtwdev, REG_DATA_SC, 27 BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40)); 28 29 value32 = rtw_read32(rtwdev, REG_WMAC_TRXPTCL_CTL); 30 value32 &= ~BIT_RFMOD; 31 switch (bw) { 32 case RTW_CHANNEL_WIDTH_80: 33 value32 |= BIT_RFMOD_80M; 34 break; 35 case RTW_CHANNEL_WIDTH_40: 36 value32 |= BIT_RFMOD_40M; 37 break; 38 case RTW_CHANNEL_WIDTH_20: 39 default: 40 break; 41 } 42 rtw_write32(rtwdev, REG_WMAC_TRXPTCL_CTL, value32); 43 44 if (rtw_chip_wcpu_8051(rtwdev)) 45 return; 46 47 value32 = rtw_read32(rtwdev, REG_AFE_CTRL1) & ~(BIT_MAC_CLK_SEL); 48 value32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL); 49 rtw_write32(rtwdev, REG_AFE_CTRL1, value32); 50 51 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED); 52 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED); 53 54 value8 = rtw_read8(rtwdev, REG_CCK_CHECK); 55 value8 = value8 & ~BIT_CHECK_CCK_EN; 56 if (IS_CH_5G_BAND(channel)) 57 value8 |= BIT_CHECK_CCK_EN; 58 rtw_write8(rtwdev, REG_CCK_CHECK, value8); 59} 60EXPORT_SYMBOL(rtw_set_channel_mac); 61 62static int rtw_mac_pre_system_cfg(struct rtw_dev *rtwdev) 63{ 64 unsigned int retry; 65 u32 value32; 66 u8 value8; 67 68 rtw_write8(rtwdev, REG_RSV_CTRL, 0); 69 70 if (rtw_chip_wcpu_8051(rtwdev)) { 71 if (rtw_read32(rtwdev, REG_SYS_CFG1) & BIT_LDO) 72 rtw_write8(rtwdev, REG_LDO_SWR_CTRL, LDO_SEL); 73 else 74 rtw_write8(rtwdev, REG_LDO_SWR_CTRL, SPS_SEL); 75 return 0; 76 } 77 78 switch (rtw_hci_type(rtwdev)) { 79 case RTW_HCI_TYPE_PCIE: 80 rtw_write32_set(rtwdev, REG_HCI_OPT_CTRL, BIT_USB_SUS_DIS); 81 break; 82 case RTW_HCI_TYPE_SDIO: 83 rtw_write8_clr(rtwdev, REG_SDIO_HSUS_CTRL, BIT_HCI_SUS_REQ); 84 85 for (retry = 0; retry < RTW_PWR_POLLING_CNT; retry++) { 86 if (rtw_read8(rtwdev, REG_SDIO_HSUS_CTRL) & BIT_HCI_RESUME_RDY) 87 break; 88 89 usleep_range(10, 50); 90 } 91 92 if (retry == RTW_PWR_POLLING_CNT) { 93 rtw_err(rtwdev, "failed to poll REG_SDIO_HSUS_CTRL[1]"); 94 return -ETIMEDOUT; 95 } 96 97 if (rtw_sdio_is_sdio30_supported(rtwdev)) 98 rtw_write8_set(rtwdev, REG_HCI_OPT_CTRL + 2, 99 BIT_SDIO_PAD_E5 >> 16); 100 else 101 rtw_write8_clr(rtwdev, REG_HCI_OPT_CTRL + 2, 102 BIT_SDIO_PAD_E5 >> 16); 103 break; 104 case RTW_HCI_TYPE_USB: 105 break; 106 default: 107 return -EINVAL; 108 } 109 110 /* config PIN Mux */ 111 value32 = rtw_read32(rtwdev, REG_PAD_CTRL1); 112 value32 |= BIT_PAPE_WLBT_SEL | BIT_LNAON_WLBT_SEL; 113 rtw_write32(rtwdev, REG_PAD_CTRL1, value32); 114 115 value32 = rtw_read32(rtwdev, REG_LED_CFG); 116 value32 &= ~(BIT_PAPE_SEL_EN | BIT_LNAON_SEL_EN); 117 rtw_write32(rtwdev, REG_LED_CFG, value32); 118 119 value32 = rtw_read32(rtwdev, REG_GPIO_MUXCFG); 120 value32 |= BIT_WLRFE_4_5_EN; 121 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value32); 122 123 /* disable BB/RF */ 124 value8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN); 125 value8 &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 126 rtw_write8(rtwdev, REG_SYS_FUNC_EN, value8); 127 128 value8 = rtw_read8(rtwdev, REG_RF_CTRL); 129 value8 &= ~(BIT_RF_SDM_RSTB | BIT_RF_RSTB | BIT_RF_EN); 130 rtw_write8(rtwdev, REG_RF_CTRL, value8); 131 132 value32 = rtw_read32(rtwdev, REG_WLRF1); 133 value32 &= ~BIT_WLRF1_BBRF_EN; 134 rtw_write32(rtwdev, REG_WLRF1, value32); 135 136 return 0; 137} 138 139static bool do_pwr_poll_cmd(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target) 140{ 141 u32 val; 142 143 target &= mask; 144 145 return read_poll_timeout_atomic(rtw_read8, val, (val & mask) == target, 146 50, 50 * RTW_PWR_POLLING_CNT, false, 147 rtwdev, addr) == 0; 148} 149 150static int rtw_pwr_cmd_polling(struct rtw_dev *rtwdev, 151 const struct rtw_pwr_seq_cmd *cmd) 152{ 153 u8 value; 154 u32 offset; 155 156 if (cmd->base == RTW_PWR_ADDR_SDIO) 157 offset = cmd->offset | SDIO_LOCAL_OFFSET; 158 else 159 offset = cmd->offset; 160 161 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value)) 162 return 0; 163 164 if (rtw_hci_type(rtwdev) != RTW_HCI_TYPE_PCIE) 165 goto err; 166 167 /* if PCIE, toggle BIT_PFM_WOWL and try again */ 168 value = rtw_read8(rtwdev, REG_SYS_PW_CTRL); 169 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D) 170 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL); 171 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL); 172 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL); 173 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D) 174 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL); 175 176 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value)) 177 return 0; 178 179err: 180 rtw_err(rtwdev, "failed to poll offset=0x%x mask=0x%x value=0x%x\n", 181 offset, cmd->mask, cmd->value); 182 return -EBUSY; 183} 184 185static int rtw_sub_pwr_seq_parser(struct rtw_dev *rtwdev, u8 intf_mask, 186 u8 cut_mask, 187 const struct rtw_pwr_seq_cmd *cmd) 188{ 189 const struct rtw_pwr_seq_cmd *cur_cmd; 190 u32 offset; 191 u8 value; 192 193 for (cur_cmd = cmd; cur_cmd->cmd != RTW_PWR_CMD_END; cur_cmd++) { 194 if (!(cur_cmd->intf_mask & intf_mask) || 195 !(cur_cmd->cut_mask & cut_mask)) 196 continue; 197 198 switch (cur_cmd->cmd) { 199 case RTW_PWR_CMD_WRITE: 200 offset = cur_cmd->offset; 201 202 if (cur_cmd->base == RTW_PWR_ADDR_SDIO) 203 offset |= SDIO_LOCAL_OFFSET; 204 205 value = rtw_read8(rtwdev, offset); 206 value &= ~cur_cmd->mask; 207 value |= (cur_cmd->value & cur_cmd->mask); 208 rtw_write8(rtwdev, offset, value); 209 break; 210 case RTW_PWR_CMD_POLLING: 211 if (rtw_pwr_cmd_polling(rtwdev, cur_cmd)) 212 return -EBUSY; 213 break; 214 case RTW_PWR_CMD_DELAY: 215 if (cur_cmd->value == RTW_PWR_DELAY_US) 216 udelay(cur_cmd->offset); 217 else 218 mdelay(cur_cmd->offset); 219 break; 220 case RTW_PWR_CMD_READ: 221 break; 222 default: 223 return -EINVAL; 224 } 225 } 226 227 return 0; 228} 229 230int rtw_pwr_seq_parser(struct rtw_dev *rtwdev, 231 const struct rtw_pwr_seq_cmd * const *cmd_seq) 232{ 233 u8 cut_mask; 234 u8 intf_mask; 235 u8 cut; 236 u32 idx = 0; 237 const struct rtw_pwr_seq_cmd *cmd; 238 int ret; 239 240 cut = rtwdev->hal.cut_version; 241 cut_mask = cut_version_to_mask(cut); 242 switch (rtw_hci_type(rtwdev)) { 243 case RTW_HCI_TYPE_PCIE: 244 intf_mask = RTW_PWR_INTF_PCI_MSK; 245 break; 246 case RTW_HCI_TYPE_USB: 247 intf_mask = RTW_PWR_INTF_USB_MSK; 248 break; 249 case RTW_HCI_TYPE_SDIO: 250 intf_mask = RTW_PWR_INTF_SDIO_MSK; 251 break; 252 default: 253 return -EINVAL; 254 } 255 256 do { 257 cmd = cmd_seq[idx]; 258 if (!cmd) 259 break; 260 261 ret = rtw_sub_pwr_seq_parser(rtwdev, intf_mask, cut_mask, cmd); 262 if (ret) 263 return ret; 264 265 idx++; 266 } while (1); 267 268 return 0; 269} 270EXPORT_SYMBOL(rtw_pwr_seq_parser); 271 272static int rtw_mac_power_switch(struct rtw_dev *rtwdev, bool pwr_on) 273{ 274 const struct rtw_chip_info *chip = rtwdev->chip; 275 const struct rtw_pwr_seq_cmd * const *pwr_seq; 276 u32 imr = 0; 277 u8 rpwm; 278 bool cur_pwr; 279 int ret; 280 281 if (rtw_chip_wcpu_3081(rtwdev)) { 282 rpwm = rtw_read8(rtwdev, rtwdev->hci.rpwm_addr); 283 284 /* Check FW still exist or not */ 285 if (rtw_read16(rtwdev, REG_MCUFW_CTRL) == 0xC078) { 286 rpwm = (rpwm ^ BIT_RPWM_TOGGLE) & BIT_RPWM_TOGGLE; 287 rtw_write8(rtwdev, rtwdev->hci.rpwm_addr, rpwm); 288 } 289 } 290 291 if (rtw_read8(rtwdev, REG_CR) == 0xea) 292 cur_pwr = false; 293 else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && 294 chip->id != RTW_CHIP_TYPE_8814A && 295 (rtw_read8(rtwdev, REG_SYS_STATUS1 + 1) & BIT(0))) 296 cur_pwr = false; 297 else 298 cur_pwr = true; 299 300 if (pwr_on == cur_pwr) 301 return -EALREADY; 302 303 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) { 304 imr = rtw_read32(rtwdev, REG_SDIO_HIMR); 305 rtw_write32(rtwdev, REG_SDIO_HIMR, 0); 306 } 307 308 if (!pwr_on) 309 clear_bit(RTW_FLAG_POWERON, rtwdev->flags); 310 311 pwr_seq = pwr_on ? chip->pwr_on_seq : chip->pwr_off_seq; 312 ret = rtw_pwr_seq_parser(rtwdev, pwr_seq); 313 314 if (pwr_on && rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) { 315 if (chip->id == RTW_CHIP_TYPE_8822C || 316 chip->id == RTW_CHIP_TYPE_8822B || 317 chip->id == RTW_CHIP_TYPE_8821C) 318 rtw_write8_clr(rtwdev, REG_SYS_STATUS1 + 1, BIT(0)); 319 } 320 321 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) 322 rtw_write32(rtwdev, REG_SDIO_HIMR, imr); 323 324 if (!ret && pwr_on) 325 set_bit(RTW_FLAG_POWERON, rtwdev->flags); 326 327 return ret; 328} 329 330static int __rtw_mac_init_system_cfg(struct rtw_dev *rtwdev) 331{ 332 u8 sys_func_en = rtwdev->chip->sys_func_en; 333 u8 value8; 334 u32 value, tmp; 335 336 value = rtw_read32(rtwdev, REG_CPU_DMEM_CON); 337 value |= BIT_WL_PLATFORM_RST | BIT_DDMA_EN; 338 rtw_write32(rtwdev, REG_CPU_DMEM_CON, value); 339 340 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, sys_func_en); 341 value8 = (rtw_read8(rtwdev, REG_CR_EXT + 3) & 0xF0) | 0x0C; 342 rtw_write8(rtwdev, REG_CR_EXT + 3, value8); 343 344 /* disable boot-from-flash for driver's DL FW */ 345 tmp = rtw_read32(rtwdev, REG_MCUFW_CTRL); 346 if (tmp & BIT_BOOT_FSPI_EN) { 347 rtw_write32(rtwdev, REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN)); 348 value = rtw_read32(rtwdev, REG_GPIO_MUXCFG) & (~BIT_FSPI_EN); 349 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value); 350 } 351 352 return 0; 353} 354 355static int __rtw_mac_init_system_cfg_legacy(struct rtw_dev *rtwdev) 356{ 357 rtw_write8(rtwdev, REG_CR, 0xff); 358 mdelay(2); 359 rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0x7f); 360 mdelay(2); 361 362 rtw_write8_set(rtwdev, REG_SYS_CLKR, BIT_WAKEPAD_EN); 363 rtw_write16_clr(rtwdev, REG_GPIO_MUXCFG, BIT_EN_SIC); 364 365 rtw_write16(rtwdev, REG_CR, 0x2ff); 366 367 return 0; 368} 369 370static int rtw_mac_init_system_cfg(struct rtw_dev *rtwdev) 371{ 372 if (rtw_chip_wcpu_8051(rtwdev)) 373 return __rtw_mac_init_system_cfg_legacy(rtwdev); 374 375 return __rtw_mac_init_system_cfg(rtwdev); 376} 377 378int rtw_mac_power_on(struct rtw_dev *rtwdev) 379{ 380 int ret = 0; 381 382 ret = rtw_mac_pre_system_cfg(rtwdev); 383 if (ret) 384 goto err; 385 386 ret = rtw_mac_power_switch(rtwdev, true); 387 if (ret == -EALREADY) { 388 rtw_mac_power_switch(rtwdev, false); 389 390 ret = rtw_mac_pre_system_cfg(rtwdev); 391 if (ret) 392 goto err; 393 394 ret = rtw_mac_power_switch(rtwdev, true); 395 if (ret) 396 goto err; 397 } else if (ret) { 398 goto err; 399 } 400 401 ret = rtw_mac_init_system_cfg(rtwdev); 402 if (ret) 403 goto err; 404 405 return 0; 406 407err: 408 rtw_err(rtwdev, "mac power on failed"); 409 return ret; 410} 411 412void rtw_mac_power_off(struct rtw_dev *rtwdev) 413{ 414 rtw_mac_power_switch(rtwdev, false); 415} 416 417static bool check_firmware_size(const u8 *data, u32 size) 418{ 419 const struct rtw_fw_hdr *fw_hdr = (const struct rtw_fw_hdr *)data; 420 u32 dmem_size; 421 u32 imem_size; 422 u32 emem_size; 423 u32 real_size; 424 425 dmem_size = le32_to_cpu(fw_hdr->dmem_size); 426 imem_size = le32_to_cpu(fw_hdr->imem_size); 427 emem_size = (fw_hdr->mem_usage & BIT(4)) ? 428 le32_to_cpu(fw_hdr->emem_size) : 0; 429 430 dmem_size += FW_HDR_CHKSUM_SIZE; 431 imem_size += FW_HDR_CHKSUM_SIZE; 432 emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0; 433 real_size = FW_HDR_SIZE + dmem_size + imem_size + emem_size; 434 if (real_size != size) 435 return false; 436 437 return true; 438} 439 440static void wlan_cpu_enable(struct rtw_dev *rtwdev, bool enable) 441{ 442 if (enable) { 443 /* cpu io interface enable */ 444 rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF); 445 446 /* cpu enable */ 447 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 448 } else { 449 /* cpu io interface disable */ 450 rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 451 452 /* cpu disable */ 453 rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF); 454 } 455} 456 457#define DLFW_RESTORE_REG_NUM 6 458 459static void download_firmware_reg_backup(struct rtw_dev *rtwdev, 460 struct rtw_backup_info *bckp) 461{ 462 u8 tmp; 463 u8 bckp_idx = 0; 464 465 /* set HIQ to hi priority */ 466 bckp[bckp_idx].len = 1; 467 bckp[bckp_idx].reg = REG_TXDMA_PQ_MAP + 1; 468 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_TXDMA_PQ_MAP + 1); 469 bckp_idx++; 470 tmp = RTW_DMA_MAPPING_HIGH << 6; 471 rtw_write8(rtwdev, REG_TXDMA_PQ_MAP + 1, tmp); 472 473 /* DLFW only use HIQ, map HIQ to hi priority */ 474 bckp[bckp_idx].len = 1; 475 bckp[bckp_idx].reg = REG_CR; 476 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_CR); 477 bckp_idx++; 478 bckp[bckp_idx].len = 4; 479 bckp[bckp_idx].reg = REG_H2CQ_CSR; 480 bckp[bckp_idx].val = BIT_H2CQ_FULL; 481 bckp_idx++; 482 tmp = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN; 483 rtw_write8(rtwdev, REG_CR, tmp); 484 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL); 485 486 /* Config hi priority queue and public priority queue page number */ 487 bckp[bckp_idx].len = 2; 488 bckp[bckp_idx].reg = REG_FIFOPAGE_INFO_1; 489 bckp[bckp_idx].val = rtw_read16(rtwdev, REG_FIFOPAGE_INFO_1); 490 bckp_idx++; 491 bckp[bckp_idx].len = 4; 492 bckp[bckp_idx].reg = REG_RQPN_CTRL_2; 493 bckp[bckp_idx].val = rtw_read32(rtwdev, REG_RQPN_CTRL_2) | BIT_LD_RQPN; 494 bckp_idx++; 495 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, 0x200); 496 rtw_write32(rtwdev, REG_RQPN_CTRL_2, bckp[bckp_idx - 1].val); 497 498 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) 499 rtw_read32(rtwdev, REG_SDIO_FREE_TXPG); 500 501 /* Disable beacon related functions */ 502 tmp = rtw_read8(rtwdev, REG_BCN_CTRL); 503 bckp[bckp_idx].len = 1; 504 bckp[bckp_idx].reg = REG_BCN_CTRL; 505 bckp[bckp_idx].val = tmp; 506 bckp_idx++; 507 tmp = (u8)((tmp & (~BIT_EN_BCN_FUNCTION)) | BIT_DIS_TSF_UDT); 508 rtw_write8(rtwdev, REG_BCN_CTRL, tmp); 509 510 WARN(bckp_idx != DLFW_RESTORE_REG_NUM, "wrong backup number\n"); 511} 512 513static void download_firmware_reset_platform(struct rtw_dev *rtwdev) 514{ 515 rtw_write8_clr(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16); 516 rtw_write8_clr(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8); 517 rtw_write8_set(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16); 518 rtw_write8_set(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8); 519} 520 521static void download_firmware_reg_restore(struct rtw_dev *rtwdev, 522 struct rtw_backup_info *bckp, 523 u8 bckp_num) 524{ 525 rtw_restore_reg(rtwdev, bckp, bckp_num); 526} 527 528#define TX_DESC_SIZE 48 529 530static int send_firmware_pkt_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr, 531 const u8 *data, u32 size) 532{ 533 u8 *buf; 534 int ret; 535 536 buf = kmemdup(data, size, GFP_KERNEL); 537 if (!buf) 538 return -ENOMEM; 539 540 ret = rtw_fw_write_data_rsvd_page(rtwdev, pg_addr, buf, size); 541 kfree(buf); 542 return ret; 543} 544 545static int 546send_firmware_pkt(struct rtw_dev *rtwdev, u16 pg_addr, const u8 *data, u32 size) 547{ 548 int ret; 549 550 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && 551 !((size + TX_DESC_SIZE) & (512 - 1))) 552 size += 1; 553 554 ret = send_firmware_pkt_rsvd_page(rtwdev, pg_addr, data, size); 555 if (ret) 556 rtw_err(rtwdev, "failed to download rsvd page\n"); 557 558 return ret; 559} 560 561static int 562iddma_enable(struct rtw_dev *rtwdev, u32 src, u32 dst, u32 ctrl) 563{ 564 rtw_write32(rtwdev, REG_DDMA_CH0SA, src); 565 rtw_write32(rtwdev, REG_DDMA_CH0DA, dst); 566 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, ctrl); 567 568 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) 569 return -EBUSY; 570 571 return 0; 572} 573 574static int iddma_download_firmware(struct rtw_dev *rtwdev, u32 src, u32 dst, 575 u32 len, u8 first) 576{ 577 u32 ch0_ctrl = BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN; 578 579 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) 580 return -EBUSY; 581 582 ch0_ctrl |= len & BIT_MASK_DDMACH0_DLEN; 583 if (!first) 584 ch0_ctrl |= BIT_DDMACH0_CHKSUM_CONT; 585 586 if (iddma_enable(rtwdev, src, dst, ch0_ctrl)) 587 return -EBUSY; 588 589 return 0; 590} 591 592int rtw_ddma_to_fw_fifo(struct rtw_dev *rtwdev, u32 ocp_src, u32 size) 593{ 594 u32 ch0_ctrl = BIT_DDMACH0_OWN | BIT_DDMACH0_DDMA_MODE; 595 596 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) { 597 rtw_dbg(rtwdev, RTW_DBG_FW, "busy to start ddma\n"); 598 return -EBUSY; 599 } 600 601 ch0_ctrl |= size & BIT_MASK_DDMACH0_DLEN; 602 603 if (iddma_enable(rtwdev, ocp_src, OCPBASE_RXBUF_FW_88XX, ch0_ctrl)) { 604 rtw_dbg(rtwdev, RTW_DBG_FW, "busy to complete ddma\n"); 605 return -EBUSY; 606 } 607 608 return 0; 609} 610 611static bool 612check_fw_checksum(struct rtw_dev *rtwdev, u32 addr) 613{ 614 u8 fw_ctrl; 615 616 fw_ctrl = rtw_read8(rtwdev, REG_MCUFW_CTRL); 617 618 if (rtw_read32(rtwdev, REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) { 619 if (addr < OCPBASE_DMEM_88XX) { 620 fw_ctrl |= BIT_IMEM_DW_OK; 621 fw_ctrl &= ~BIT_IMEM_CHKSUM_OK; 622 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 623 } else { 624 fw_ctrl |= BIT_DMEM_DW_OK; 625 fw_ctrl &= ~BIT_DMEM_CHKSUM_OK; 626 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 627 } 628 629 rtw_err(rtwdev, "invalid fw checksum\n"); 630 631 return false; 632 } 633 634 if (addr < OCPBASE_DMEM_88XX) { 635 fw_ctrl |= (BIT_IMEM_DW_OK | BIT_IMEM_CHKSUM_OK); 636 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 637 } else { 638 fw_ctrl |= (BIT_DMEM_DW_OK | BIT_DMEM_CHKSUM_OK); 639 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 640 } 641 642 return true; 643} 644 645static int 646download_firmware_to_mem(struct rtw_dev *rtwdev, const u8 *data, 647 u32 src, u32 dst, u32 size) 648{ 649 const struct rtw_chip_info *chip = rtwdev->chip; 650 u32 desc_size = chip->tx_pkt_desc_sz; 651 u8 first_part; 652 u32 mem_offset; 653 u32 residue_size; 654 u32 pkt_size; 655 u32 max_size = 0x1000; 656 u32 val; 657 int ret; 658 659 mem_offset = 0; 660 first_part = 1; 661 residue_size = size; 662 663 val = rtw_read32(rtwdev, REG_DDMA_CH0CTRL); 664 val |= BIT_DDMACH0_RESET_CHKSUM_STS; 665 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, val); 666 667 while (residue_size) { 668 if (residue_size >= max_size) 669 pkt_size = max_size; 670 else 671 pkt_size = residue_size; 672 673 ret = send_firmware_pkt(rtwdev, (u16)(src >> 7), 674 data + mem_offset, pkt_size); 675 if (ret) 676 return ret; 677 678 ret = iddma_download_firmware(rtwdev, OCPBASE_TXBUF_88XX + 679 src + desc_size, 680 dst + mem_offset, pkt_size, 681 first_part); 682 if (ret) 683 return ret; 684 685 first_part = 0; 686 mem_offset += pkt_size; 687 residue_size -= pkt_size; 688 } 689 690 if (!check_fw_checksum(rtwdev, dst)) 691 return -EINVAL; 692 693 return 0; 694} 695 696static int 697start_download_firmware(struct rtw_dev *rtwdev, const u8 *data, u32 size) 698{ 699 const struct rtw_fw_hdr *fw_hdr = (const struct rtw_fw_hdr *)data; 700 const u8 *cur_fw; 701 u16 val; 702 u32 imem_size; 703 u32 dmem_size; 704 u32 emem_size; 705 u32 addr; 706 int ret; 707 708 dmem_size = le32_to_cpu(fw_hdr->dmem_size); 709 imem_size = le32_to_cpu(fw_hdr->imem_size); 710 emem_size = (fw_hdr->mem_usage & BIT(4)) ? 711 le32_to_cpu(fw_hdr->emem_size) : 0; 712 dmem_size += FW_HDR_CHKSUM_SIZE; 713 imem_size += FW_HDR_CHKSUM_SIZE; 714 emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0; 715 716 val = (u16)(rtw_read16(rtwdev, REG_MCUFW_CTRL) & 0x3800); 717 val |= BIT_MCUFWDL_EN; 718 rtw_write16(rtwdev, REG_MCUFW_CTRL, val); 719 720 cur_fw = data + FW_HDR_SIZE; 721 addr = le32_to_cpu(fw_hdr->dmem_addr); 722 addr &= ~BIT(31); 723 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, dmem_size); 724 if (ret) 725 return ret; 726 727 cur_fw = data + FW_HDR_SIZE + dmem_size; 728 addr = le32_to_cpu(fw_hdr->imem_addr); 729 addr &= ~BIT(31); 730 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, imem_size); 731 if (ret) 732 return ret; 733 734 if (emem_size) { 735 cur_fw = data + FW_HDR_SIZE + dmem_size + imem_size; 736 addr = le32_to_cpu(fw_hdr->emem_addr); 737 addr &= ~BIT(31); 738 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, 739 emem_size); 740 if (ret) 741 return ret; 742 } 743 744 return 0; 745} 746 747static int download_firmware_validate(struct rtw_dev *rtwdev) 748{ 749 u32 fw_key; 750 751 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, FW_READY_MASK, FW_READY)) { 752 fw_key = rtw_read32(rtwdev, REG_FW_DBG7) & FW_KEY_MASK; 753 if (fw_key == ILLEGAL_KEY_GROUP) 754 rtw_err(rtwdev, "invalid fw key\n"); 755 return -EINVAL; 756 } 757 758 return 0; 759} 760 761static void download_firmware_end_flow(struct rtw_dev *rtwdev) 762{ 763 u16 fw_ctrl; 764 765 rtw_write32(rtwdev, REG_TXDMA_STATUS, BTI_PAGE_OVF); 766 767 /* Check IMEM & DMEM checksum is OK or not */ 768 fw_ctrl = rtw_read16(rtwdev, REG_MCUFW_CTRL); 769 if ((fw_ctrl & BIT_CHECK_SUM_OK) != BIT_CHECK_SUM_OK) 770 return; 771 772 fw_ctrl = (fw_ctrl | BIT_FW_DW_RDY) & ~BIT_MCUFWDL_EN; 773 rtw_write16(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 774} 775 776static int __rtw_download_firmware(struct rtw_dev *rtwdev, 777 struct rtw_fw_state *fw) 778{ 779 struct rtw_backup_info bckp[DLFW_RESTORE_REG_NUM]; 780 const u8 *data = fw->firmware->data; 781 u32 size = fw->firmware->size; 782 u32 ltecoex_bckp; 783 int ret; 784 785 if (!check_firmware_size(data, size)) 786 return -EINVAL; 787 788 if (rtwdev->chip->ltecoex_addr && 789 !ltecoex_read_reg(rtwdev, 0x38, <ecoex_bckp)) 790 return -EBUSY; 791 792 wlan_cpu_enable(rtwdev, false); 793 794 download_firmware_reg_backup(rtwdev, bckp); 795 download_firmware_reset_platform(rtwdev); 796 797 ret = start_download_firmware(rtwdev, data, size); 798 if (ret) 799 goto dlfw_fail; 800 801 download_firmware_reg_restore(rtwdev, bckp, DLFW_RESTORE_REG_NUM); 802 803 download_firmware_end_flow(rtwdev); 804 805 wlan_cpu_enable(rtwdev, true); 806 807 if (rtwdev->chip->ltecoex_addr && 808 !ltecoex_reg_write(rtwdev, 0x38, ltecoex_bckp)) { 809 ret = -EBUSY; 810 goto dlfw_fail; 811 } 812 813 ret = download_firmware_validate(rtwdev); 814 if (ret) 815 goto dlfw_fail; 816 817 /* reset desc and index */ 818 rtw_hci_setup(rtwdev); 819 820 rtwdev->h2c.last_box_num = 0; 821 rtwdev->h2c.seq = 0; 822 823 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 824 825 return 0; 826 827dlfw_fail: 828 /* Disable FWDL_EN */ 829 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 830 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 831 832 return ret; 833} 834 835static void en_download_firmware_legacy(struct rtw_dev *rtwdev, bool en) 836{ 837 int try; 838 839 if (en) { 840 wlan_cpu_enable(rtwdev, false); 841 wlan_cpu_enable(rtwdev, true); 842 843 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 844 845 for (try = 0; try < 10; try++) { 846 if (rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_MCUFWDL_EN) 847 goto fwdl_ready; 848 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 849 msleep(20); 850 } 851 rtw_err(rtwdev, "failed to check fw download ready\n"); 852fwdl_ready: 853 rtw_write32_clr(rtwdev, REG_MCUFW_CTRL, BIT_ROM_DLEN); 854 } else { 855 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 856 } 857} 858 859void rtw_write_firmware_page(struct rtw_dev *rtwdev, u32 page, 860 const u8 *data, u32 size) 861{ 862 u32 val32; 863 u32 block_nr; 864 u32 remain_size; 865 u32 write_addr = FW_START_ADDR_LEGACY; 866 const __le32 *ptr = (const __le32 *)data; 867 u32 block; 868 __le32 remain_data = 0; 869 870 block_nr = size >> DLFW_BLK_SIZE_SHIFT_LEGACY; 871 remain_size = size & (DLFW_BLK_SIZE_LEGACY - 1); 872 873 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL); 874 val32 &= ~BIT_ROM_PGE; 875 val32 |= (page << BIT_SHIFT_ROM_PGE) & BIT_ROM_PGE; 876 rtw_write32(rtwdev, REG_MCUFW_CTRL, val32); 877 878 for (block = 0; block < block_nr; block++) { 879 rtw_write32(rtwdev, write_addr, le32_to_cpu(*ptr)); 880 881 write_addr += DLFW_BLK_SIZE_LEGACY; 882 ptr++; 883 } 884 885 if (remain_size) { 886 memcpy(&remain_data, ptr, remain_size); 887 rtw_write32(rtwdev, write_addr, le32_to_cpu(remain_data)); 888 } 889} 890EXPORT_SYMBOL(rtw_write_firmware_page); 891 892static int 893download_firmware_legacy(struct rtw_dev *rtwdev, const u8 *data, u32 size) 894{ 895 u32 page; 896 u32 total_page; 897 u32 last_page_size; 898 899 data += sizeof(struct rtw_fw_hdr_legacy); 900 size -= sizeof(struct rtw_fw_hdr_legacy); 901 902 total_page = size >> DLFW_PAGE_SIZE_SHIFT_LEGACY; 903 last_page_size = size & (DLFW_PAGE_SIZE_LEGACY - 1); 904 905 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT); 906 907 for (page = 0; page < total_page; page++) { 908 rtw_hci_write_firmware_page(rtwdev, page, data, 909 DLFW_PAGE_SIZE_LEGACY); 910 data += DLFW_PAGE_SIZE_LEGACY; 911 } 912 if (last_page_size) 913 rtw_hci_write_firmware_page(rtwdev, page, data, 914 last_page_size); 915 916 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT, 1)) { 917 rtw_err(rtwdev, "failed to check download firmware report\n"); 918 return -EINVAL; 919 } 920 921 return 0; 922} 923 924static int download_firmware_validate_legacy(struct rtw_dev *rtwdev) 925{ 926 u32 val32; 927 int try; 928 929 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL); 930 val32 |= BIT_MCUFWDL_RDY; 931 val32 &= ~BIT_WINTINI_RDY; 932 rtw_write32(rtwdev, REG_MCUFW_CTRL, val32); 933 934 wlan_cpu_enable(rtwdev, false); 935 wlan_cpu_enable(rtwdev, true); 936 937 for (try = 0; try < 10; try++) { 938 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL); 939 if ((val32 & FW_READY_LEGACY) == FW_READY_LEGACY) 940 return 0; 941 msleep(20); 942 } 943 944 rtw_err(rtwdev, "failed to validate firmware\n"); 945 return -EINVAL; 946} 947 948static int __rtw_download_firmware_legacy(struct rtw_dev *rtwdev, 949 struct rtw_fw_state *fw) 950{ 951 int ret = 0; 952 953 /* reset firmware if still present */ 954 if (rtwdev->chip->id == RTW_CHIP_TYPE_8703B && 955 rtw_read8_mask(rtwdev, REG_MCUFW_CTRL, BIT_RAM_DL_SEL)) { 956 rtw_write8(rtwdev, REG_MCUFW_CTRL, 0x00); 957 } 958 959 en_download_firmware_legacy(rtwdev, true); 960 ret = download_firmware_legacy(rtwdev, fw->firmware->data, fw->firmware->size); 961 en_download_firmware_legacy(rtwdev, false); 962 if (ret) 963 goto out; 964 965 ret = download_firmware_validate_legacy(rtwdev); 966 if (ret) 967 goto out; 968 969 /* reset desc and index */ 970 rtw_hci_setup(rtwdev); 971 972 rtwdev->h2c.last_box_num = 0; 973 rtwdev->h2c.seq = 0; 974 975 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 976 977out: 978 return ret; 979} 980 981static 982int _rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw) 983{ 984 if (rtw_chip_wcpu_8051(rtwdev)) 985 return __rtw_download_firmware_legacy(rtwdev, fw); 986 987 return __rtw_download_firmware(rtwdev, fw); 988} 989 990int rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw) 991{ 992 int ret; 993 994 ret = _rtw_download_firmware(rtwdev, fw); 995 if (ret) 996 return ret; 997 998 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE && 999 rtwdev->chip->id == RTW_CHIP_TYPE_8821C) 1000 rtw_fw_set_recover_bt_device(rtwdev); 1001 1002 return 0; 1003} 1004EXPORT_SYMBOL(rtw_download_firmware); 1005 1006static u32 get_priority_queues(struct rtw_dev *rtwdev, u32 queues) 1007{ 1008 const struct rtw_rqpn *rqpn = rtwdev->fifo.rqpn; 1009 u32 prio_queues = 0; 1010 1011 if (queues & BIT(IEEE80211_AC_VO)) 1012 prio_queues |= BIT(rqpn->dma_map_vo); 1013 if (queues & BIT(IEEE80211_AC_VI)) 1014 prio_queues |= BIT(rqpn->dma_map_vi); 1015 if (queues & BIT(IEEE80211_AC_BE)) 1016 prio_queues |= BIT(rqpn->dma_map_be); 1017 if (queues & BIT(IEEE80211_AC_BK)) 1018 prio_queues |= BIT(rqpn->dma_map_bk); 1019 1020 return prio_queues; 1021} 1022 1023static void __rtw_mac_flush_prio_queue(struct rtw_dev *rtwdev, 1024 u32 prio_queue, bool drop) 1025{ 1026 const struct rtw_chip_info *chip = rtwdev->chip; 1027 const struct rtw_prioq_addr *addr; 1028 bool wsize; 1029 u16 avail_page, rsvd_page; 1030 int i; 1031 1032 if (prio_queue >= RTW_DMA_MAPPING_MAX) 1033 return; 1034 1035 addr = &chip->prioq_addrs->prio[prio_queue]; 1036 wsize = chip->prioq_addrs->wsize; 1037 1038 /* check if all of the reserved pages are available for 100 msecs */ 1039 for (i = 0; i < 5; i++) { 1040 rsvd_page = wsize ? rtw_read16(rtwdev, addr->rsvd) : 1041 rtw_read8(rtwdev, addr->rsvd); 1042 avail_page = wsize ? rtw_read16(rtwdev, addr->avail) : 1043 rtw_read8(rtwdev, addr->avail); 1044 if (rsvd_page == avail_page) 1045 return; 1046 1047 msleep(20); 1048 } 1049 1050 /* priority queue is still not empty, throw a debug message 1051 * 1052 * Note that if we want to flush the tx queue when having a lot of 1053 * traffic (ex, 100Mbps up), some of the packets could be dropped. 1054 * And it requires like ~2secs to flush the full priority queue. 1055 */ 1056 if (!drop) 1057 rtw_dbg(rtwdev, RTW_DBG_UNEXP, 1058 "timed out to flush queue %d\n", prio_queue); 1059} 1060 1061static void rtw_mac_flush_prio_queues(struct rtw_dev *rtwdev, 1062 u32 prio_queues, bool drop) 1063{ 1064 u32 q; 1065 1066 for (q = 0; q < RTW_DMA_MAPPING_MAX; q++) 1067 if (prio_queues & BIT(q)) 1068 __rtw_mac_flush_prio_queue(rtwdev, q, drop); 1069} 1070 1071void rtw_mac_flush_queues(struct rtw_dev *rtwdev, u32 queues, bool drop) 1072{ 1073 u32 prio_queues = 0; 1074 1075 /* If all of the hardware queues are requested to flush, 1076 * or the priority queues are not mapped yet, 1077 * flush all of the priority queues 1078 */ 1079 if (queues == BIT(rtwdev->hw->queues) - 1 || !rtwdev->fifo.rqpn) 1080 prio_queues = BIT(RTW_DMA_MAPPING_MAX) - 1; 1081 else 1082 prio_queues = get_priority_queues(rtwdev, queues); 1083 1084 rtw_mac_flush_prio_queues(rtwdev, prio_queues, drop); 1085} 1086 1087static int txdma_queue_mapping(struct rtw_dev *rtwdev) 1088{ 1089 const struct rtw_chip_info *chip = rtwdev->chip; 1090 const struct rtw_rqpn *rqpn = NULL; 1091 u16 txdma_pq_map = 0; 1092 1093 switch (rtw_hci_type(rtwdev)) { 1094 case RTW_HCI_TYPE_PCIE: 1095 rqpn = &chip->rqpn_table[1]; 1096 break; 1097 case RTW_HCI_TYPE_USB: 1098 if (rtwdev->hci.bulkout_num == 2) 1099 rqpn = &chip->rqpn_table[2]; 1100 else if (rtwdev->hci.bulkout_num == 3) 1101 rqpn = &chip->rqpn_table[3]; 1102 else if (rtwdev->hci.bulkout_num == 4) 1103 rqpn = &chip->rqpn_table[4]; 1104 else 1105 return -EINVAL; 1106 break; 1107 case RTW_HCI_TYPE_SDIO: 1108 rqpn = &chip->rqpn_table[0]; 1109 break; 1110 default: 1111 return -EINVAL; 1112 } 1113 1114 rtwdev->fifo.rqpn = rqpn; 1115 txdma_pq_map |= BIT_TXDMA_HIQ_MAP(rqpn->dma_map_hi); 1116 txdma_pq_map |= BIT_TXDMA_MGQ_MAP(rqpn->dma_map_mg); 1117 txdma_pq_map |= BIT_TXDMA_BKQ_MAP(rqpn->dma_map_bk); 1118 txdma_pq_map |= BIT_TXDMA_BEQ_MAP(rqpn->dma_map_be); 1119 txdma_pq_map |= BIT_TXDMA_VIQ_MAP(rqpn->dma_map_vi); 1120 txdma_pq_map |= BIT_TXDMA_VOQ_MAP(rqpn->dma_map_vo); 1121 rtw_write16(rtwdev, REG_TXDMA_PQ_MAP, txdma_pq_map); 1122 1123 rtw_write8(rtwdev, REG_CR, 0); 1124 rtw_write8(rtwdev, REG_CR, MAC_TRX_ENABLE); 1125 if (rtw_chip_wcpu_3081(rtwdev)) 1126 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL); 1127 1128 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) { 1129 rtw_read32(rtwdev, REG_SDIO_FREE_TXPG); 1130 rtw_write32(rtwdev, REG_SDIO_TX_CTRL, 0); 1131 } else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) { 1132 rtw_write8_set(rtwdev, REG_TXDMA_PQ_MAP, BIT_RXDMA_ARBBW_EN); 1133 } 1134 1135 return 0; 1136} 1137 1138int rtw_set_trx_fifo_info(struct rtw_dev *rtwdev) 1139{ 1140 const struct rtw_chip_info *chip = rtwdev->chip; 1141 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1142 u16 cur_pg_addr; 1143 u8 csi_buf_pg_num = chip->csi_buf_pg_num; 1144 1145 /* config rsvd page num */ 1146 fifo->rsvd_drv_pg_num = chip->rsvd_drv_pg_num; 1147 fifo->txff_pg_num = chip->txff_size / chip->page_size; 1148 if (rtw_chip_wcpu_8051(rtwdev)) 1149 fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num; 1150 else 1151 fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num + 1152 RSVD_PG_H2C_EXTRAINFO_NUM + 1153 RSVD_PG_H2C_STATICINFO_NUM + 1154 RSVD_PG_H2CQ_NUM + 1155 RSVD_PG_CPU_INSTRUCTION_NUM + 1156 RSVD_PG_FW_TXBUF_NUM + 1157 csi_buf_pg_num; 1158 1159 if (fifo->rsvd_pg_num > fifo->txff_pg_num) 1160 return -ENOMEM; 1161 1162 fifo->acq_pg_num = fifo->txff_pg_num - fifo->rsvd_pg_num; 1163 fifo->rsvd_boundary = fifo->txff_pg_num - fifo->rsvd_pg_num; 1164 1165 cur_pg_addr = fifo->txff_pg_num; 1166 if (rtw_chip_wcpu_3081(rtwdev)) { 1167 cur_pg_addr -= csi_buf_pg_num; 1168 fifo->rsvd_csibuf_addr = cur_pg_addr; 1169 cur_pg_addr -= RSVD_PG_FW_TXBUF_NUM; 1170 fifo->rsvd_fw_txbuf_addr = cur_pg_addr; 1171 cur_pg_addr -= RSVD_PG_CPU_INSTRUCTION_NUM; 1172 fifo->rsvd_cpu_instr_addr = cur_pg_addr; 1173 cur_pg_addr -= RSVD_PG_H2CQ_NUM; 1174 fifo->rsvd_h2cq_addr = cur_pg_addr; 1175 cur_pg_addr -= RSVD_PG_H2C_STATICINFO_NUM; 1176 fifo->rsvd_h2c_sta_info_addr = cur_pg_addr; 1177 cur_pg_addr -= RSVD_PG_H2C_EXTRAINFO_NUM; 1178 fifo->rsvd_h2c_info_addr = cur_pg_addr; 1179 } 1180 cur_pg_addr -= fifo->rsvd_drv_pg_num; 1181 fifo->rsvd_drv_addr = cur_pg_addr; 1182 1183 if (fifo->rsvd_boundary != fifo->rsvd_drv_addr) { 1184 rtw_err(rtwdev, "wrong rsvd driver address\n"); 1185 return -EINVAL; 1186 } 1187 1188 return 0; 1189} 1190EXPORT_SYMBOL(rtw_set_trx_fifo_info); 1191 1192static int __priority_queue_cfg(struct rtw_dev *rtwdev, 1193 const struct rtw_page_table *pg_tbl, 1194 u16 pubq_num) 1195{ 1196 const struct rtw_chip_info *chip = rtwdev->chip; 1197 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1198 1199 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, pg_tbl->hq_num); 1200 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_2, pg_tbl->lq_num); 1201 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_3, pg_tbl->nq_num); 1202 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_4, pg_tbl->exq_num); 1203 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_5, pubq_num); 1204 rtw_write32_set(rtwdev, REG_RQPN_CTRL_2, BIT_LD_RQPN); 1205 1206 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2, fifo->rsvd_boundary); 1207 rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL + 2, BIT_EN_WR_FREE_TAIL >> 16); 1208 1209 rtw_write16(rtwdev, REG_BCNQ_BDNY_V1, fifo->rsvd_boundary); 1210 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2 + 2, fifo->rsvd_boundary); 1211 rtw_write16(rtwdev, REG_BCNQ1_BDNY_V1, fifo->rsvd_boundary); 1212 rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1); 1213 1214 if (rtwdev->hci.type == RTW_HCI_TYPE_USB) { 1215 rtw_write8_mask(rtwdev, REG_AUTO_LLT_V1, BIT_MASK_BLK_DESC_NUM, 1216 chip->usb_tx_agg_desc_num); 1217 1218 rtw_write8(rtwdev, REG_AUTO_LLT_V1 + 3, chip->usb_tx_agg_desc_num); 1219 rtw_write8_set(rtwdev, REG_TXDMA_OFFSET_CHK + 1, BIT(1)); 1220 } 1221 1222 rtw_write8_set(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1); 1223 1224 if (!check_hw_ready(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1, 0)) 1225 return -EBUSY; 1226 1227 rtw_write8(rtwdev, REG_CR + 3, 0); 1228 1229 return 0; 1230} 1231 1232static int __priority_queue_cfg_legacy(struct rtw_dev *rtwdev, 1233 const struct rtw_page_table *pg_tbl, 1234 u16 pubq_num) 1235{ 1236 const struct rtw_chip_info *chip = rtwdev->chip; 1237 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1238 u32 val32; 1239 1240 val32 = BIT_RQPN_NE(pg_tbl->nq_num, pg_tbl->exq_num); 1241 rtw_write32(rtwdev, REG_RQPN_NPQ, val32); 1242 val32 = BIT_RQPN_HLP(pg_tbl->hq_num, pg_tbl->lq_num, pubq_num); 1243 rtw_write32(rtwdev, REG_RQPN, val32); 1244 1245 rtw_write8(rtwdev, REG_TRXFF_BNDY, fifo->rsvd_boundary); 1246 rtw_write16(rtwdev, REG_TRXFF_BNDY + 2, chip->rxff_size - REPORT_BUF - 1); 1247 rtw_write8(rtwdev, REG_DWBCN0_CTRL + 1, fifo->rsvd_boundary); 1248 rtw_write8(rtwdev, REG_BCNQ_BDNY, fifo->rsvd_boundary); 1249 rtw_write8(rtwdev, REG_MGQ_BDNY, fifo->rsvd_boundary); 1250 rtw_write8(rtwdev, REG_WMAC_LBK_BF_HD, fifo->rsvd_boundary); 1251 1252 rtw_write32_set(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT); 1253 1254 if (!check_hw_ready(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT, 0)) 1255 return -EBUSY; 1256 1257 return 0; 1258} 1259 1260static int priority_queue_cfg(struct rtw_dev *rtwdev) 1261{ 1262 const struct rtw_chip_info *chip = rtwdev->chip; 1263 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1264 const struct rtw_page_table *pg_tbl = NULL; 1265 u16 pubq_num; 1266 int ret; 1267 1268 ret = rtw_set_trx_fifo_info(rtwdev); 1269 if (ret) 1270 return ret; 1271 1272 switch (rtw_hci_type(rtwdev)) { 1273 case RTW_HCI_TYPE_PCIE: 1274 pg_tbl = &chip->page_table[1]; 1275 break; 1276 case RTW_HCI_TYPE_USB: 1277 if (rtwdev->hci.bulkout_num == 2) 1278 pg_tbl = &chip->page_table[2]; 1279 else if (rtwdev->hci.bulkout_num == 3) 1280 pg_tbl = &chip->page_table[3]; 1281 else if (rtwdev->hci.bulkout_num == 4) 1282 pg_tbl = &chip->page_table[4]; 1283 else 1284 return -EINVAL; 1285 break; 1286 case RTW_HCI_TYPE_SDIO: 1287 pg_tbl = &chip->page_table[0]; 1288 break; 1289 default: 1290 return -EINVAL; 1291 } 1292 1293 pubq_num = fifo->acq_pg_num - pg_tbl->hq_num - pg_tbl->lq_num - 1294 pg_tbl->nq_num - pg_tbl->exq_num - pg_tbl->gapq_num; 1295 if (rtw_chip_wcpu_8051(rtwdev)) 1296 return __priority_queue_cfg_legacy(rtwdev, pg_tbl, pubq_num); 1297 else 1298 return __priority_queue_cfg(rtwdev, pg_tbl, pubq_num); 1299} 1300 1301static int init_h2c(struct rtw_dev *rtwdev) 1302{ 1303 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1304 u8 value8; 1305 u32 value32; 1306 u32 h2cq_addr; 1307 u32 h2cq_size; 1308 u32 h2cq_free; 1309 u32 wp, rp; 1310 1311 if (rtw_chip_wcpu_8051(rtwdev)) 1312 return 0; 1313 1314 h2cq_addr = fifo->rsvd_h2cq_addr << TX_PAGE_SIZE_SHIFT; 1315 h2cq_size = RSVD_PG_H2CQ_NUM << TX_PAGE_SIZE_SHIFT; 1316 1317 value32 = rtw_read32(rtwdev, REG_H2C_HEAD); 1318 value32 = (value32 & 0xFFFC0000) | h2cq_addr; 1319 rtw_write32(rtwdev, REG_H2C_HEAD, value32); 1320 1321 value32 = rtw_read32(rtwdev, REG_H2C_READ_ADDR); 1322 value32 = (value32 & 0xFFFC0000) | h2cq_addr; 1323 rtw_write32(rtwdev, REG_H2C_READ_ADDR, value32); 1324 1325 value32 = rtw_read32(rtwdev, REG_H2C_TAIL); 1326 value32 &= 0xFFFC0000; 1327 value32 |= (h2cq_addr + h2cq_size); 1328 rtw_write32(rtwdev, REG_H2C_TAIL, value32); 1329 1330 value8 = rtw_read8(rtwdev, REG_H2C_INFO); 1331 value8 = (u8)((value8 & 0xFC) | 0x01); 1332 rtw_write8(rtwdev, REG_H2C_INFO, value8); 1333 1334 value8 = rtw_read8(rtwdev, REG_H2C_INFO); 1335 value8 = (u8)((value8 & 0xFB) | 0x04); 1336 rtw_write8(rtwdev, REG_H2C_INFO, value8); 1337 1338 value8 = rtw_read8(rtwdev, REG_TXDMA_OFFSET_CHK + 1); 1339 value8 = (u8)((value8 & 0x7f) | 0x80); 1340 rtw_write8(rtwdev, REG_TXDMA_OFFSET_CHK + 1, value8); 1341 1342 wp = rtw_read32(rtwdev, REG_H2C_PKT_WRITEADDR) & 0x3FFFF; 1343 rp = rtw_read32(rtwdev, REG_H2C_PKT_READADDR) & 0x3FFFF; 1344 h2cq_free = wp >= rp ? h2cq_size - (wp - rp) : rp - wp; 1345 1346 if (h2cq_size != h2cq_free) { 1347 rtw_err(rtwdev, "H2C queue mismatch\n"); 1348 return -EINVAL; 1349 } 1350 1351 return 0; 1352} 1353 1354static int rtw_init_trx_cfg(struct rtw_dev *rtwdev) 1355{ 1356 int ret; 1357 1358 ret = txdma_queue_mapping(rtwdev); 1359 if (ret) 1360 return ret; 1361 1362 ret = priority_queue_cfg(rtwdev); 1363 if (ret) 1364 return ret; 1365 1366 ret = init_h2c(rtwdev); 1367 if (ret) 1368 return ret; 1369 1370 return 0; 1371} 1372 1373static int rtw_drv_info_cfg(struct rtw_dev *rtwdev) 1374{ 1375 u8 value8; 1376 1377 rtw_write8(rtwdev, REG_RX_DRVINFO_SZ, PHY_STATUS_SIZE); 1378 if (rtw_chip_wcpu_3081(rtwdev)) { 1379 value8 = rtw_read8(rtwdev, REG_TRXFF_BNDY + 1); 1380 value8 &= 0xF0; 1381 /* For rxdesc len = 0 issue */ 1382 value8 |= 0xF; 1383 rtw_write8(rtwdev, REG_TRXFF_BNDY + 1, value8); 1384 } 1385 rtw_write32_set(rtwdev, REG_RCR, BIT_APP_PHYSTS); 1386 rtw_write32_clr(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, BIT(8) | BIT(9)); 1387 1388 return 0; 1389} 1390 1391int rtw_mac_init(struct rtw_dev *rtwdev) 1392{ 1393 const struct rtw_chip_info *chip = rtwdev->chip; 1394 int ret; 1395 1396 ret = rtw_init_trx_cfg(rtwdev); 1397 if (ret) 1398 return ret; 1399 1400 ret = chip->ops->mac_init(rtwdev); 1401 if (ret) 1402 return ret; 1403 1404 ret = rtw_drv_info_cfg(rtwdev); 1405 if (ret) 1406 return ret; 1407 1408 rtw_hci_interface_cfg(rtwdev); 1409 1410 return 0; 1411} 1412 1413int rtw_mac_postinit(struct rtw_dev *rtwdev) 1414{ 1415 const struct rtw_chip_info *chip = rtwdev->chip; 1416 1417 if (!chip->ops->mac_postinit) 1418 return 0; 1419 1420 return chip->ops->mac_postinit(rtwdev); 1421}
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