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hw.c
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linux-6.19.14/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c
1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2009-2010 Realtek Corporation.*/ 3 4#include "../wifi.h" 5#include "../efuse.h" 6#include "../base.h" 7#include "../regd.h" 8#include "../cam.h" 9#include "../ps.h" 10#include "../pci.h" 11#include "reg.h" 12#include "def.h" 13#include "phy.h" 14#include "dm.h" 15#include "fw.h" 16#include "led.h" 17#include "hw.h" 18#include "../pwrseqcmd.h" 19#include "pwrseq.h" 20#include "../btcoexist/rtl_btc.h" 21 22#define LLT_CONFIG 5 23 24static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw) 25{ 26 struct rtl_priv *rtlpriv = rtl_priv(hw); 27 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 28 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE]; 29 struct sk_buff_head free_list; 30 unsigned long flags; 31 32 skb_queue_head_init(&free_list); 33 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 34 while (skb_queue_len(&ring->queue)) { 35 struct rtl_tx_desc *entry = &ring->desc[ring->idx]; 36 struct sk_buff *skb = __skb_dequeue(&ring->queue); 37 38 dma_unmap_single(&rtlpci->pdev->dev, 39 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 40 true, HW_DESC_TXBUFF_ADDR), 41 skb->len, DMA_TO_DEVICE); 42 __skb_queue_tail(&free_list, skb); 43 ring->idx = (ring->idx + 1) % ring->entries; 44 } 45 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 46 47 __skb_queue_purge(&free_list); 48} 49 50static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 51 u8 set_bits, u8 clear_bits) 52{ 53 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 54 struct rtl_priv *rtlpriv = rtl_priv(hw); 55 56 rtlpci->reg_bcn_ctrl_val |= set_bits; 57 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; 58 59 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); 60} 61 62void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw) 63{ 64 struct rtl_priv *rtlpriv = rtl_priv(hw); 65 u8 tmp1byte; 66 67 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 68 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); 69 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 70 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 71 tmp1byte &= ~(BIT(0)); 72 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 73} 74 75void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw) 76{ 77 struct rtl_priv *rtlpriv = rtl_priv(hw); 78 u8 tmp1byte; 79 80 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 81 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); 82 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 83 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 84 tmp1byte |= BIT(0); 85 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 86} 87 88static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw) 89{ 90 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1)); 91} 92 93static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw) 94{ 95 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0); 96} 97 98static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw, 99 u8 rpwm_val, bool b_need_turn_off_ckk) 100{ 101 struct rtl_priv *rtlpriv = rtl_priv(hw); 102 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 103 bool b_support_remote_wake_up; 104 u32 count = 0, isr_regaddr, content; 105 bool b_schedule_timer = b_need_turn_off_ckk; 106 107 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 108 (u8 *)(&b_support_remote_wake_up)); 109 110 if (!rtlhal->fw_ready) 111 return; 112 if (!rtlpriv->psc.fw_current_inpsmode) 113 return; 114 115 while (1) { 116 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 117 if (rtlhal->fw_clk_change_in_progress) { 118 while (rtlhal->fw_clk_change_in_progress) { 119 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 120 count++; 121 udelay(100); 122 if (count > 1000) 123 goto change_done; 124 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 125 } 126 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 127 } else { 128 rtlhal->fw_clk_change_in_progress = false; 129 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 130 goto change_done; 131 } 132 } 133change_done: 134 if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) { 135 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, 136 (u8 *)(&rpwm_val)); 137 if (FW_PS_IS_ACK(rpwm_val)) { 138 isr_regaddr = REG_HISR; 139 content = rtl_read_dword(rtlpriv, isr_regaddr); 140 while (!(content & IMR_CPWM) && (count < 500)) { 141 udelay(50); 142 count++; 143 content = rtl_read_dword(rtlpriv, isr_regaddr); 144 } 145 146 if (content & IMR_CPWM) { 147 rtl_write_word(rtlpriv, isr_regaddr, 0x0100); 148 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE; 149 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 150 "Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n", 151 rtlhal->fw_ps_state); 152 } 153 } 154 155 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 156 rtlhal->fw_clk_change_in_progress = false; 157 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 158 if (b_schedule_timer) 159 mod_timer(&rtlpriv->works.fw_clockoff_timer, 160 jiffies + MSECS(10)); 161 } else { 162 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 163 rtlhal->fw_clk_change_in_progress = false; 164 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 165 } 166} 167 168static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw, 169 u8 rpwm_val) 170{ 171 struct rtl_priv *rtlpriv = rtl_priv(hw); 172 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 173 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 174 struct rtl8192_tx_ring *ring; 175 enum rf_pwrstate rtstate; 176 bool b_schedule_timer = false; 177 u8 queue; 178 179 if (!rtlhal->fw_ready) 180 return; 181 if (!rtlpriv->psc.fw_current_inpsmode) 182 return; 183 if (!rtlhal->allow_sw_to_change_hwclc) 184 return; 185 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate)); 186 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF) 187 return; 188 189 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) { 190 ring = &rtlpci->tx_ring[queue]; 191 if (skb_queue_len(&ring->queue)) { 192 b_schedule_timer = true; 193 break; 194 } 195 } 196 197 if (b_schedule_timer) { 198 mod_timer(&rtlpriv->works.fw_clockoff_timer, 199 jiffies + MSECS(10)); 200 return; 201 } 202 203 if (FW_PS_STATE(rtlhal->fw_ps_state) != 204 FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) { 205 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 206 if (!rtlhal->fw_clk_change_in_progress) { 207 rtlhal->fw_clk_change_in_progress = true; 208 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 209 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val); 210 rtl_write_word(rtlpriv, REG_HISR, 0x0100); 211 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 212 (u8 *)(&rpwm_val)); 213 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 214 rtlhal->fw_clk_change_in_progress = false; 215 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 216 } else { 217 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 218 mod_timer(&rtlpriv->works.fw_clockoff_timer, 219 jiffies + MSECS(10)); 220 } 221 } 222} 223 224static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw) 225{ 226 u8 rpwm_val = 0; 227 228 rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK); 229 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true); 230} 231 232static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw) 233{ 234 struct rtl_priv *rtlpriv = rtl_priv(hw); 235 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 236 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 237 bool fw_current_inps = false; 238 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE; 239 240 if (ppsc->low_power_enable) { 241 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */ 242 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false); 243 rtlhal->allow_sw_to_change_hwclc = false; 244 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 245 (u8 *)(&fw_pwrmode)); 246 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 247 (u8 *)(&fw_current_inps)); 248 } else { 249 rpwm_val = FW_PS_STATE_ALL_ON_8821AE; /* RF on */ 250 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 251 (u8 *)(&rpwm_val)); 252 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 253 (u8 *)(&fw_pwrmode)); 254 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 255 (u8 *)(&fw_current_inps)); 256 } 257} 258 259static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw) 260{ 261 struct rtl_priv *rtlpriv = rtl_priv(hw); 262 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 263 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 264 bool fw_current_inps = true; 265 u8 rpwm_val; 266 267 if (ppsc->low_power_enable) { 268 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE; /* RF off */ 269 rtlpriv->cfg->ops->set_hw_reg(hw, 270 HW_VAR_FW_PSMODE_STATUS, 271 (u8 *)(&fw_current_inps)); 272 rtlpriv->cfg->ops->set_hw_reg(hw, 273 HW_VAR_H2C_FW_PWRMODE, 274 (u8 *)(&ppsc->fwctrl_psmode)); 275 rtlhal->allow_sw_to_change_hwclc = true; 276 _rtl8821ae_set_fw_clock_off(hw, rpwm_val); 277 } else { 278 rpwm_val = FW_PS_STATE_RF_OFF_8821AE; /* RF off */ 279 rtlpriv->cfg->ops->set_hw_reg(hw, 280 HW_VAR_FW_PSMODE_STATUS, 281 (u8 *)(&fw_current_inps)); 282 rtlpriv->cfg->ops->set_hw_reg(hw, 283 HW_VAR_H2C_FW_PWRMODE, 284 (u8 *)(&ppsc->fwctrl_psmode)); 285 rtlpriv->cfg->ops->set_hw_reg(hw, 286 HW_VAR_SET_RPWM, 287 (u8 *)(&rpwm_val)); 288 } 289} 290 291static void _rtl8821ae_download_rsvd_page(struct ieee80211_hw *hw, 292 bool dl_whole_packets) 293{ 294 struct rtl_priv *rtlpriv = rtl_priv(hw); 295 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 296 u8 tmp_regcr, tmp_reg422, bcnvalid_reg; 297 u8 count = 0, dlbcn_count = 0; 298 bool send_beacon = false; 299 300 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 301 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr | BIT(0))); 302 303 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3)); 304 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0); 305 306 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 307 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 308 tmp_reg422 & (~BIT(6))); 309 if (tmp_reg422 & BIT(6)) 310 send_beacon = true; 311 312 do { 313 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2); 314 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, 315 (bcnvalid_reg | BIT(0))); 316 _rtl8821ae_return_beacon_queue_skb(hw); 317 318 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 319 rtl8812ae_set_fw_rsvdpagepkt(hw, false, 320 dl_whole_packets); 321 else 322 rtl8821ae_set_fw_rsvdpagepkt(hw, false, 323 dl_whole_packets); 324 325 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2); 326 count = 0; 327 while (!(bcnvalid_reg & BIT(0)) && count < 20) { 328 count++; 329 udelay(10); 330 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2); 331 } 332 dlbcn_count++; 333 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); 334 335 if (!(bcnvalid_reg & BIT(0))) 336 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 337 "Download RSVD page failed!\n"); 338 if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) { 339 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0)); 340 _rtl8821ae_return_beacon_queue_skb(hw); 341 if (send_beacon) { 342 dlbcn_count = 0; 343 do { 344 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, 345 bcnvalid_reg | BIT(0)); 346 347 _rtl8821ae_return_beacon_queue_skb(hw); 348 349 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 350 rtl8812ae_set_fw_rsvdpagepkt(hw, true, 351 false); 352 else 353 rtl8821ae_set_fw_rsvdpagepkt(hw, true, 354 false); 355 356 /* check rsvd page download OK. */ 357 bcnvalid_reg = rtl_read_byte(rtlpriv, 358 REG_TDECTRL + 2); 359 count = 0; 360 while (!(bcnvalid_reg & BIT(0)) && count < 20) { 361 count++; 362 udelay(10); 363 bcnvalid_reg = 364 rtl_read_byte(rtlpriv, 365 REG_TDECTRL + 2); 366 } 367 dlbcn_count++; 368 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); 369 370 if (!(bcnvalid_reg & BIT(0))) 371 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 372 "2 Download RSVD page failed!\n"); 373 } 374 } 375 376 if (bcnvalid_reg & BIT(0)) 377 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0)); 378 379 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0); 380 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4)); 381 382 if (send_beacon) 383 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422); 384 385 if (!rtlhal->enter_pnp_sleep) { 386 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 387 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0)))); 388 } 389} 390 391void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 392{ 393 struct rtl_priv *rtlpriv = rtl_priv(hw); 394 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 395 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 396 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 397 398 switch (variable) { 399 case HW_VAR_ETHER_ADDR: 400 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID); 401 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4); 402 break; 403 case HW_VAR_BSSID: 404 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID); 405 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4); 406 break; 407 case HW_VAR_MEDIA_STATUS: 408 val[0] = rtl_read_byte(rtlpriv, MSR) & 0x3; 409 break; 410 case HW_VAR_SLOT_TIME: 411 *((u8 *)(val)) = mac->slot_time; 412 break; 413 case HW_VAR_BEACON_INTERVAL: 414 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL); 415 break; 416 case HW_VAR_ATIM_WINDOW: 417 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_ATIMWND); 418 break; 419 case HW_VAR_RCR: 420 *((u32 *)(val)) = rtlpci->receive_config; 421 break; 422 case HW_VAR_RF_STATE: 423 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 424 break; 425 case HW_VAR_FWLPS_RF_ON:{ 426 enum rf_pwrstate rfstate; 427 u32 val_rcr; 428 429 rtlpriv->cfg->ops->get_hw_reg(hw, 430 HW_VAR_RF_STATE, 431 (u8 *)(&rfstate)); 432 if (rfstate == ERFOFF) { 433 *((bool *)(val)) = true; 434 } else { 435 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 436 val_rcr &= 0x00070000; 437 if (val_rcr) 438 *((bool *)(val)) = false; 439 else 440 *((bool *)(val)) = true; 441 } 442 break; } 443 case HW_VAR_FW_PSMODE_STATUS: 444 *((bool *)(val)) = ppsc->fw_current_inpsmode; 445 break; 446 case HW_VAR_CORRECT_TSF:{ 447 u64 tsf; 448 u32 *ptsf_low = (u32 *)&tsf; 449 u32 *ptsf_high = ((u32 *)&tsf) + 1; 450 451 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 452 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 453 454 *((u64 *)(val)) = tsf; 455 456 break; } 457 case HAL_DEF_WOWLAN: 458 if (ppsc->wo_wlan_mode) 459 *((bool *)(val)) = true; 460 else 461 *((bool *)(val)) = false; 462 break; 463 default: 464 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 465 "switch case %#x not processed\n", variable); 466 break; 467 } 468} 469 470void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 471{ 472 struct rtl_priv *rtlpriv = rtl_priv(hw); 473 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 474 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 475 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 476 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 477 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 478 u8 idx; 479 480 switch (variable) { 481 case HW_VAR_ETHER_ADDR:{ 482 for (idx = 0; idx < ETH_ALEN; idx++) { 483 rtl_write_byte(rtlpriv, (REG_MACID + idx), 484 val[idx]); 485 } 486 break; 487 } 488 case HW_VAR_BASIC_RATE:{ 489 u16 b_rate_cfg = ((u16 *)val)[0]; 490 b_rate_cfg = b_rate_cfg & 0x15f; 491 rtl_write_word(rtlpriv, REG_RRSR, b_rate_cfg); 492 break; 493 } 494 case HW_VAR_BSSID:{ 495 for (idx = 0; idx < ETH_ALEN; idx++) { 496 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 497 val[idx]); 498 } 499 break; 500 } 501 case HW_VAR_SIFS: 502 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 503 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[0]); 504 505 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 506 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 507 508 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]); 509 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM, val[0]); 510 break; 511 case HW_VAR_R2T_SIFS: 512 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]); 513 break; 514 case HW_VAR_SLOT_TIME:{ 515 u8 e_aci; 516 517 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 518 "HW_VAR_SLOT_TIME %x\n", val[0]); 519 520 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 521 522 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 523 rtlpriv->cfg->ops->set_hw_reg(hw, 524 HW_VAR_AC_PARAM, 525 (u8 *)(&e_aci)); 526 } 527 break; } 528 case HW_VAR_ACK_PREAMBLE:{ 529 u8 reg_tmp; 530 u8 short_preamble = (bool)(*(u8 *)val); 531 532 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2); 533 if (short_preamble) { 534 reg_tmp |= BIT(1); 535 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, 536 reg_tmp); 537 } else { 538 reg_tmp &= (~BIT(1)); 539 rtl_write_byte(rtlpriv, 540 REG_TRXPTCL_CTL + 2, 541 reg_tmp); 542 } 543 break; } 544 case HW_VAR_WPA_CONFIG: 545 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val)); 546 break; 547 case HW_VAR_AMPDU_MIN_SPACE:{ 548 u8 min_spacing_to_set; 549 550 min_spacing_to_set = *((u8 *)val); 551 if (min_spacing_to_set <= 7) { 552 553 mac->min_space_cfg = ((mac->min_space_cfg & 554 0xf8) | 555 min_spacing_to_set); 556 557 *val = min_spacing_to_set; 558 559 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 560 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 561 mac->min_space_cfg); 562 563 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 564 mac->min_space_cfg); 565 } 566 break; } 567 case HW_VAR_SHORTGI_DENSITY:{ 568 u8 density_to_set; 569 570 density_to_set = *((u8 *)val); 571 mac->min_space_cfg |= (density_to_set << 3); 572 573 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 574 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 575 mac->min_space_cfg); 576 577 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 578 mac->min_space_cfg); 579 580 break; } 581 case HW_VAR_AMPDU_FACTOR:{ 582 u32 ampdu_len = (*((u8 *)val)); 583 584 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 585 if (ampdu_len < VHT_AGG_SIZE_128K) 586 ampdu_len = 587 (0x2000 << (*((u8 *)val))) - 1; 588 else 589 ampdu_len = 0x1ffff; 590 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 591 if (ampdu_len < HT_AGG_SIZE_64K) 592 ampdu_len = 593 (0x2000 << (*((u8 *)val))) - 1; 594 else 595 ampdu_len = 0xffff; 596 } 597 ampdu_len |= BIT(31); 598 599 rtl_write_dword(rtlpriv, 600 REG_AMPDU_MAX_LENGTH_8812, ampdu_len); 601 break; } 602 case HW_VAR_AC_PARAM:{ 603 u8 e_aci = *((u8 *)val); 604 605 rtl8821ae_dm_init_edca_turbo(hw); 606 if (rtlpci->acm_method != EACMWAY2_SW) 607 rtlpriv->cfg->ops->set_hw_reg(hw, 608 HW_VAR_ACM_CTRL, 609 (u8 *)(&e_aci)); 610 break; } 611 case HW_VAR_ACM_CTRL:{ 612 u8 e_aci = *((u8 *)val); 613 union aci_aifsn *p_aci_aifsn = 614 (union aci_aifsn *)(&mac->ac[0].aifs); 615 u8 acm = p_aci_aifsn->f.acm; 616 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); 617 618 acm_ctrl = 619 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); 620 621 if (acm) { 622 switch (e_aci) { 623 case AC0_BE: 624 acm_ctrl |= ACMHW_BEQEN; 625 break; 626 case AC2_VI: 627 acm_ctrl |= ACMHW_VIQEN; 628 break; 629 case AC3_VO: 630 acm_ctrl |= ACMHW_VOQEN; 631 break; 632 default: 633 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 634 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 635 acm); 636 break; 637 } 638 } else { 639 switch (e_aci) { 640 case AC0_BE: 641 acm_ctrl &= (~ACMHW_BEQEN); 642 break; 643 case AC2_VI: 644 acm_ctrl &= (~ACMHW_VIQEN); 645 break; 646 case AC3_VO: 647 acm_ctrl &= (~ACMHW_VOQEN); 648 break; 649 default: 650 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 651 "switch case %#x not processed\n", 652 e_aci); 653 break; 654 } 655 } 656 657 rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE, 658 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 659 acm_ctrl); 660 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 661 break; } 662 case HW_VAR_RCR: 663 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); 664 rtlpci->receive_config = ((u32 *)(val))[0]; 665 break; 666 case HW_VAR_RETRY_LIMIT:{ 667 u8 retry_limit = ((u8 *)(val))[0]; 668 669 rtl_write_word(rtlpriv, REG_RL, 670 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 671 retry_limit << RETRY_LIMIT_LONG_SHIFT); 672 break; } 673 case HW_VAR_DUAL_TSF_RST: 674 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 675 break; 676 case HW_VAR_EFUSE_BYTES: 677 rtlefuse->efuse_usedbytes = *((u16 *)val); 678 break; 679 case HW_VAR_EFUSE_USAGE: 680 rtlefuse->efuse_usedpercentage = *((u8 *)val); 681 break; 682 case HW_VAR_IO_CMD: 683 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val)); 684 break; 685 case HW_VAR_SET_RPWM:{ 686 u8 rpwm_val; 687 688 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); 689 udelay(1); 690 691 if (rpwm_val & BIT(7)) { 692 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 693 (*(u8 *)val)); 694 } else { 695 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 696 ((*(u8 *)val) | BIT(7))); 697 } 698 699 break; } 700 case HW_VAR_H2C_FW_PWRMODE: 701 rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *)val)); 702 break; 703 case HW_VAR_FW_PSMODE_STATUS: 704 ppsc->fw_current_inpsmode = *((bool *)val); 705 break; 706 case HW_VAR_INIT_RTS_RATE: 707 break; 708 case HW_VAR_RESUME_CLK_ON: 709 _rtl8821ae_set_fw_ps_rf_on(hw); 710 break; 711 case HW_VAR_FW_LPS_ACTION:{ 712 bool b_enter_fwlps = *((bool *)val); 713 714 if (b_enter_fwlps) 715 _rtl8821ae_fwlps_enter(hw); 716 else 717 _rtl8821ae_fwlps_leave(hw); 718 break; } 719 case HW_VAR_H2C_FW_JOINBSSRPT:{ 720 u8 mstatus = (*(u8 *)val); 721 722 if (mstatus == RT_MEDIA_CONNECT) { 723 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, 724 NULL); 725 _rtl8821ae_download_rsvd_page(hw, false); 726 } 727 rtl8821ae_set_fw_media_status_rpt_cmd(hw, mstatus); 728 729 break; } 730 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: 731 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val)); 732 break; 733 case HW_VAR_AID:{ 734 u16 u2btmp; 735 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 736 u2btmp &= 0xC000; 737 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | 738 mac->assoc_id)); 739 break; } 740 case HW_VAR_CORRECT_TSF:{ 741 u8 btype_ibss = ((u8 *)(val))[0]; 742 743 if (btype_ibss) 744 _rtl8821ae_stop_tx_beacon(hw); 745 746 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3)); 747 748 rtl_write_dword(rtlpriv, REG_TSFTR, 749 (u32)(mac->tsf & 0xffffffff)); 750 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 751 (u32)((mac->tsf >> 32) & 0xffffffff)); 752 753 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0); 754 755 if (btype_ibss) 756 _rtl8821ae_resume_tx_beacon(hw); 757 break; } 758 case HW_VAR_NAV_UPPER: { 759 u32 us_nav_upper = *(u32 *)val; 760 761 if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) { 762 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING, 763 "The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n", 764 us_nav_upper, HAL_92C_NAV_UPPER_UNIT); 765 break; 766 } 767 rtl_write_byte(rtlpriv, REG_NAV_UPPER, 768 ((u8)((us_nav_upper + 769 HAL_92C_NAV_UPPER_UNIT - 1) / 770 HAL_92C_NAV_UPPER_UNIT))); 771 break; } 772 case HW_VAR_KEEP_ALIVE: { 773 u8 array[2]; 774 array[0] = 0xff; 775 array[1] = *((u8 *)val); 776 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2, 777 array); 778 break; } 779 default: 780 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 781 "switch case %#x not processed\n", variable); 782 break; 783 } 784} 785 786static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 787{ 788 struct rtl_priv *rtlpriv = rtl_priv(hw); 789 bool status = true; 790 long count = 0; 791 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | 792 _LLT_OP(_LLT_WRITE_ACCESS); 793 794 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 795 796 do { 797 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 798 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 799 break; 800 801 if (count > POLLING_LLT_THRESHOLD) { 802 pr_err("Failed to polling write LLT done at address %d!\n", 803 address); 804 status = false; 805 break; 806 } 807 } while (++count); 808 809 return status; 810} 811 812static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw) 813{ 814 struct rtl_priv *rtlpriv = rtl_priv(hw); 815 unsigned short i; 816 u8 txpktbuf_bndy; 817 u32 rqpn; 818 u8 maxpage; 819 bool status; 820 821 maxpage = 255; 822 txpktbuf_bndy = 0xF7; 823 rqpn = 0x80e60808; 824 825 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy); 826 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1); 827 828 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); 829 830 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 831 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 832 833 rtl_write_byte(rtlpriv, REG_PBP, 0x31); 834 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); 835 836 for (i = 0; i < (txpktbuf_bndy - 1); i++) { 837 status = _rtl8821ae_llt_write(hw, i, i + 1); 838 if (!status) 839 return status; 840 } 841 842 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 843 if (!status) 844 return status; 845 846 for (i = txpktbuf_bndy; i < maxpage; i++) { 847 status = _rtl8821ae_llt_write(hw, i, (i + 1)); 848 if (!status) 849 return status; 850 } 851 852 status = _rtl8821ae_llt_write(hw, maxpage, txpktbuf_bndy); 853 if (!status) 854 return status; 855 856 rtl_write_dword(rtlpriv, REG_RQPN, rqpn); 857 858 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00); 859 860 return true; 861} 862 863static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw) 864{ 865 struct rtl_priv *rtlpriv = rtl_priv(hw); 866 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 867 enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0; 868 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 869 870 if (rtlpriv->rtlhal.up_first_time) 871 return; 872 873 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 874 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 875 rtl8812ae_sw_led_on(hw, pin0); 876 else 877 rtl8821ae_sw_led_on(hw, pin0); 878 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) 879 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 880 rtl8812ae_sw_led_on(hw, pin0); 881 else 882 rtl8821ae_sw_led_on(hw, pin0); 883 else 884 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 885 rtl8812ae_sw_led_off(hw, pin0); 886 else 887 rtl8821ae_sw_led_off(hw, pin0); 888} 889 890static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw) 891{ 892 struct rtl_priv *rtlpriv = rtl_priv(hw); 893 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 894 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 895 896 u8 bytetmp = 0; 897 u16 wordtmp = 0; 898 bool mac_func_enable = rtlhal->mac_func_enable; 899 900 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); 901 902 /*Auto Power Down to CHIP-off State*/ 903 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7)); 904 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp); 905 906 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 907 /* HW Power on sequence*/ 908 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, 909 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, 910 RTL8812_NIC_ENABLE_FLOW)) { 911 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 912 "init 8812 MAC Fail as power on failure\n"); 913 return false; 914 } 915 } else { 916 /* HW Power on sequence */ 917 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK, 918 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, 919 RTL8821A_NIC_ENABLE_FLOW)){ 920 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 921 "init 8821 MAC Fail as power on failure\n"); 922 return false; 923 } 924 } 925 926 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4); 927 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp); 928 929 bytetmp = rtl_read_byte(rtlpriv, REG_CR); 930 bytetmp = 0xff; 931 rtl_write_byte(rtlpriv, REG_CR, bytetmp); 932 mdelay(2); 933 934 bytetmp = 0xff; 935 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp); 936 mdelay(2); 937 938 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 939 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3); 940 if (bytetmp & BIT(0)) { 941 bytetmp = rtl_read_byte(rtlpriv, 0x7c); 942 bytetmp |= BIT(6); 943 rtl_write_byte(rtlpriv, 0x7c, bytetmp); 944 } 945 } 946 947 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1); 948 bytetmp &= ~BIT(4); 949 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp); 950 951 rtl_write_word(rtlpriv, REG_CR, 0x2ff); 952 953 if (!mac_func_enable) { 954 if (!_rtl8821ae_llt_table_init(hw)) 955 return false; 956 } 957 958 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); 959 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff); 960 961 /* Enable FW Beamformer Interrupt */ 962 bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3); 963 rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6)); 964 965 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); 966 wordtmp &= 0xf; 967 wordtmp |= 0xF5B1; 968 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); 969 970 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); 971 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 972 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF); 973 /*low address*/ 974 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 975 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32)); 976 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 977 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32)); 978 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 979 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); 980 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 981 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); 982 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 983 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); 984 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 985 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); 986 rtl_write_dword(rtlpriv, REG_HQ_DESA, 987 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32)); 988 rtl_write_dword(rtlpriv, REG_RX_DESA, 989 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32)); 990 991 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77); 992 993 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 994 995 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0); 996 997 rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3); 998 _rtl8821ae_gen_refresh_led_state(hw); 999 1000 return true; 1001} 1002 1003static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw) 1004{ 1005 struct rtl_priv *rtlpriv = rtl_priv(hw); 1006 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1007 u32 reg_rrsr; 1008 1009 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 1010 1011 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr); 1012 /* ARFB table 9 for 11ac 5G 2SS */ 1013 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000); 1014 /* ARFB table 10 for 11ac 5G 1SS */ 1015 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000); 1016 /* ARFB table 11 for 11ac 24G 1SS */ 1017 rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015); 1018 rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000); 1019 /* ARFB table 12 for 11ac 24G 1SS */ 1020 rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015); 1021 rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000); 1022 /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */ 1023 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00); 1024 rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70); 1025 1026 /*Set retry limit*/ 1027 rtl_write_word(rtlpriv, REG_RL, 0x0707); 1028 1029 /* Set Data / Response auto rate fallback retry count*/ 1030 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); 1031 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); 1032 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); 1033 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); 1034 1035 rtlpci->reg_bcn_ctrl_val = 0x1d; 1036 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); 1037 1038 /* TBTT prohibit hold time. Suggested by designer TimChen. */ 1039 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 1040 1041 /* AGGR_BK_TIME Reg51A 0x16 */ 1042 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040); 1043 1044 /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/ 1045 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); 1046 1047 rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80); 1048 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20); 1049 rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F); 1050} 1051 1052static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr) 1053{ 1054 u16 ret = 0; 1055 u8 tmp = 0, count = 0; 1056 1057 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6)); 1058 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6); 1059 count = 0; 1060 while (tmp && count < 20) { 1061 udelay(10); 1062 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6); 1063 count++; 1064 } 1065 if (0 == tmp) 1066 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA); 1067 1068 return ret; 1069} 1070 1071static void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data) 1072{ 1073 u8 tmp = 0, count = 0; 1074 1075 rtl_write_word(rtlpriv, REG_MDIO_WDATA, data); 1076 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5)); 1077 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5); 1078 count = 0; 1079 while (tmp && count < 20) { 1080 udelay(10); 1081 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5); 1082 count++; 1083 } 1084} 1085 1086static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr) 1087{ 1088 u16 read_addr = addr & 0xfffc; 1089 u8 tmp = 0, count = 0, ret = 0; 1090 1091 rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr); 1092 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2); 1093 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1094 count = 0; 1095 while (tmp && count < 20) { 1096 udelay(10); 1097 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1098 count++; 1099 } 1100 if (0 == tmp) { 1101 read_addr = REG_DBI_RDATA + addr % 4; 1102 ret = rtl_read_byte(rtlpriv, read_addr); 1103 } 1104 return ret; 1105} 1106 1107static void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data) 1108{ 1109 u8 tmp = 0, count = 0; 1110 u16 write_addr, remainder = addr % 4; 1111 1112 write_addr = REG_DBI_WDATA + remainder; 1113 rtl_write_byte(rtlpriv, write_addr, data); 1114 1115 write_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12)); 1116 rtl_write_word(rtlpriv, REG_DBI_ADDR, write_addr); 1117 1118 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1); 1119 1120 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1121 count = 0; 1122 while (tmp && count < 20) { 1123 udelay(10); 1124 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1125 count++; 1126 } 1127} 1128 1129static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw) 1130{ 1131 struct rtl_priv *rtlpriv = rtl_priv(hw); 1132 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1133 u8 tmp; 1134 1135 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1136 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544) 1137 _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544); 1138 1139 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070) 1140 _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070); 1141 } 1142 1143 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f); 1144 _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7) | 1145 ASPM_L1_LATENCY << 3); 1146 1147 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719); 1148 _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4)); 1149 1150 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 1151 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718); 1152 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4)); 1153 } 1154} 1155 1156void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw) 1157{ 1158 struct rtl_priv *rtlpriv = rtl_priv(hw); 1159 u8 sec_reg_value; 1160 u8 tmp; 1161 1162 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1163 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 1164 rtlpriv->sec.pairwise_enc_algorithm, 1165 rtlpriv->sec.group_enc_algorithm); 1166 1167 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 1168 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 1169 "not open hw encryption\n"); 1170 return; 1171 } 1172 1173 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE; 1174 1175 if (rtlpriv->sec.use_defaultkey) { 1176 sec_reg_value |= SCR_TXUSEDK; 1177 sec_reg_value |= SCR_RXUSEDK; 1178 } 1179 1180 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 1181 1182 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1183 rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1)); 1184 1185 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 1186 "The SECR-value %x\n", sec_reg_value); 1187 1188 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 1189} 1190 1191/* Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ---------- */ 1192#define MAC_ID_STATIC_FOR_DEFAULT_PORT 0 1193#define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST 1 1194#define MAC_ID_STATIC_FOR_BT_CLIENT_START 2 1195#define MAC_ID_STATIC_FOR_BT_CLIENT_END 3 1196/* ----------------------------------------------------------- */ 1197 1198static void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw) 1199{ 1200 struct rtl_priv *rtlpriv = rtl_priv(hw); 1201 u8 media_rpt[4] = {RT_MEDIA_CONNECT, 1, 1202 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST, 1203 MAC_ID_STATIC_FOR_BT_CLIENT_END}; 1204 1205 rtlpriv->cfg->ops->set_hw_reg(hw, 1206 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt); 1207 1208 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1209 "Initialize MacId media status: from %d to %d\n", 1210 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST, 1211 MAC_ID_STATIC_FOR_BT_CLIENT_END); 1212} 1213 1214static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw) 1215{ 1216 struct rtl_priv *rtlpriv = rtl_priv(hw); 1217 u8 tmp; 1218 1219 /* write reg 0x350 Bit[26]=1. Enable debug port. */ 1220 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3); 1221 if (!(tmp & BIT(2))) { 1222 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2))); 1223 mdelay(100); 1224 } 1225 1226 /* read reg 0x350 Bit[25] if 1 : RX hang */ 1227 /* read reg 0x350 Bit[24] if 1 : TX hang */ 1228 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3); 1229 if ((tmp & BIT(0)) || (tmp & BIT(1))) { 1230 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1231 "CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n"); 1232 return true; 1233 } else { 1234 return false; 1235 } 1236} 1237 1238static bool _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw, 1239 bool mac_power_on, 1240 bool in_watchdog) 1241{ 1242 struct rtl_priv *rtlpriv = rtl_priv(hw); 1243 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1244 u8 tmp; 1245 bool release_mac_rx_pause; 1246 u8 backup_pcie_dma_pause; 1247 1248 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "\n"); 1249 1250 /* 1. Disable register write lock. 0x1c[1] = 0 */ 1251 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL); 1252 tmp &= ~(BIT(1)); 1253 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp); 1254 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1255 /* write 0xCC bit[2] = 1'b1 */ 1256 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2); 1257 tmp |= BIT(2); 1258 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp); 1259 } 1260 1261 /* 2. Check and pause TRX DMA */ 1262 /* write 0x284 bit[18] = 1'b1 */ 1263 /* write 0x301 = 0xFF */ 1264 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1265 if (tmp & BIT(2)) { 1266 /* Already pause before the function for another purpose. */ 1267 release_mac_rx_pause = false; 1268 } else { 1269 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2))); 1270 release_mac_rx_pause = true; 1271 } 1272 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1); 1273 if (backup_pcie_dma_pause != 0xFF) 1274 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF); 1275 1276 if (mac_power_on) { 1277 /* 3. reset TRX function */ 1278 /* write 0x100 = 0x00 */ 1279 rtl_write_byte(rtlpriv, REG_CR, 0); 1280 } 1281 1282 /* 4. Reset PCIe DMA. 0x3[0] = 0 */ 1283 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1284 tmp &= ~(BIT(0)); 1285 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp); 1286 1287 /* 5. Enable PCIe DMA. 0x3[0] = 1 */ 1288 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1289 tmp |= BIT(0); 1290 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp); 1291 1292 if (mac_power_on) { 1293 /* 6. enable TRX function */ 1294 /* write 0x100 = 0xFF */ 1295 rtl_write_byte(rtlpriv, REG_CR, 0xFF); 1296 1297 /* We should init LLT & RQPN and 1298 * prepare Tx/Rx descriptor address later 1299 * because MAC function is reset.*/ 1300 } 1301 1302 /* 7. Restore PCIe autoload down bit */ 1303 /* 8812AE does not have the definition. */ 1304 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1305 /* write 0xF8 bit[17] = 1'b1 */ 1306 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2); 1307 tmp |= BIT(1); 1308 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp); 1309 } 1310 1311 /* In MAC power on state, BB and RF may be in ON state, 1312 * if we release TRx DMA here. 1313 * it will cause packets to be started to Tx/Rx, 1314 * so we release Tx/Rx DMA later.*/ 1315 if (!mac_power_on/* || in_watchdog*/) { 1316 /* 8. release TRX DMA */ 1317 /* write 0x284 bit[18] = 1'b0 */ 1318 /* write 0x301 = 0x00 */ 1319 if (release_mac_rx_pause) { 1320 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1321 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 1322 tmp & (~BIT(2))); 1323 } 1324 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 1325 backup_pcie_dma_pause); 1326 } 1327 1328 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1329 /* 9. lock system register */ 1330 /* write 0xCC bit[2] = 1'b0 */ 1331 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2); 1332 tmp &= ~(BIT(2)); 1333 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp); 1334 } 1335 return true; 1336} 1337 1338static void _rtl8821ae_get_wakeup_reason(struct ieee80211_hw *hw) 1339{ 1340 struct rtl_priv *rtlpriv = rtl_priv(hw); 1341 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1342 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); 1343 u8 fw_reason = 0; 1344 1345 fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN); 1346 1347 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n", 1348 fw_reason); 1349 1350 ppsc->wakeup_reason = 0; 1351 1352 rtlhal->last_suspend_sec = ktime_get_real_seconds(); 1353 1354 switch (fw_reason) { 1355 case FW_WOW_V2_PTK_UPDATE_EVENT: 1356 ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE; 1357 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 1358 "It's a WOL PTK Key update event!\n"); 1359 break; 1360 case FW_WOW_V2_GTK_UPDATE_EVENT: 1361 ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE; 1362 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 1363 "It's a WOL GTK Key update event!\n"); 1364 break; 1365 case FW_WOW_V2_DISASSOC_EVENT: 1366 ppsc->wakeup_reason = WOL_REASON_DISASSOC; 1367 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 1368 "It's a disassociation event!\n"); 1369 break; 1370 case FW_WOW_V2_DEAUTH_EVENT: 1371 ppsc->wakeup_reason = WOL_REASON_DEAUTH; 1372 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 1373 "It's a deauth event!\n"); 1374 break; 1375 case FW_WOW_V2_FW_DISCONNECT_EVENT: 1376 ppsc->wakeup_reason = WOL_REASON_AP_LOST; 1377 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 1378 "It's a Fw disconnect decision (AP lost) event!\n"); 1379 break; 1380 case FW_WOW_V2_MAGIC_PKT_EVENT: 1381 ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT; 1382 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 1383 "It's a magic packet event!\n"); 1384 break; 1385 case FW_WOW_V2_UNICAST_PKT_EVENT: 1386 ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT; 1387 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 1388 "It's an unicast packet event!\n"); 1389 break; 1390 case FW_WOW_V2_PATTERN_PKT_EVENT: 1391 ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT; 1392 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 1393 "It's a pattern match event!\n"); 1394 break; 1395 case FW_WOW_V2_RTD3_SSID_MATCH_EVENT: 1396 ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH; 1397 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 1398 "It's an RTD3 Ssid match event!\n"); 1399 break; 1400 case FW_WOW_V2_REALWOW_V2_WAKEUPPKT: 1401 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT; 1402 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 1403 "It's an RealWoW wake packet event!\n"); 1404 break; 1405 case FW_WOW_V2_REALWOW_V2_ACKLOST: 1406 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST; 1407 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 1408 "It's an RealWoW ack lost event!\n"); 1409 break; 1410 default: 1411 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 1412 "WOL Read 0x1c7 = %02X, Unknown reason!\n", 1413 fw_reason); 1414 break; 1415 } 1416} 1417 1418static void _rtl8821ae_init_trx_desc_hw_address(struct ieee80211_hw *hw) 1419{ 1420 struct rtl_priv *rtlpriv = rtl_priv(hw); 1421 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1422 1423 /*low address*/ 1424 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 1425 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32)); 1426 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 1427 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32)); 1428 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 1429 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); 1430 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 1431 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); 1432 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 1433 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); 1434 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 1435 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); 1436 rtl_write_dword(rtlpriv, REG_HQ_DESA, 1437 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32)); 1438 rtl_write_dword(rtlpriv, REG_RX_DESA, 1439 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32)); 1440} 1441 1442static bool _rtl8821ae_init_llt_table(struct ieee80211_hw *hw, u32 boundary) 1443{ 1444 bool status = true; 1445 u32 i; 1446 u32 txpktbuf_bndy = boundary; 1447 u32 last_entry_of_txpktbuf = LAST_ENTRY_OF_TX_PKT_BUFFER; 1448 1449 for (i = 0 ; i < (txpktbuf_bndy - 1) ; i++) { 1450 status = _rtl8821ae_llt_write(hw, i , i + 1); 1451 if (!status) 1452 return status; 1453 } 1454 1455 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 1456 if (!status) 1457 return status; 1458 1459 for (i = txpktbuf_bndy ; i < last_entry_of_txpktbuf ; i++) { 1460 status = _rtl8821ae_llt_write(hw, i, (i + 1)); 1461 if (!status) 1462 return status; 1463 } 1464 1465 status = _rtl8821ae_llt_write(hw, last_entry_of_txpktbuf, 1466 txpktbuf_bndy); 1467 if (!status) 1468 return status; 1469 1470 return status; 1471} 1472 1473static bool _rtl8821ae_dynamic_rqpn(struct ieee80211_hw *hw, u32 boundary, 1474 u16 npq_rqpn_value, u32 rqpn_val) 1475{ 1476 struct rtl_priv *rtlpriv = rtl_priv(hw); 1477 u8 tmp; 1478 bool ret = true; 1479 u16 count = 0, tmp16; 1480 bool support_remote_wakeup; 1481 1482 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 1483 (u8 *)(&support_remote_wakeup)); 1484 1485 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1486 "boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n", 1487 boundary, npq_rqpn_value, rqpn_val); 1488 1489 /* stop PCIe DMA 1490 * 1. 0x301[7:0] = 0xFE */ 1491 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE); 1492 1493 /* wait TXFF empty 1494 * 2. polling till 0x41A[15:0]=0x07FF */ 1495 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY); 1496 while ((tmp16 & 0x07FF) != 0x07FF) { 1497 udelay(100); 1498 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY); 1499 count++; 1500 if ((count % 200) == 0) { 1501 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1502 "Tx queue is not empty for 20ms!\n"); 1503 } 1504 if (count >= 1000) { 1505 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1506 "Wait for Tx FIFO empty timeout!\n"); 1507 break; 1508 } 1509 } 1510 1511 /* TX pause 1512 * 3. reg 0x522=0xFF */ 1513 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1514 1515 /* Wait TX State Machine OK 1516 * 4. polling till reg 0x5FB~0x5F8 = 0x00000000 for 50ms */ 1517 count = 0; 1518 while (rtl_read_byte(rtlpriv, REG_SCH_TXCMD) != 0) { 1519 udelay(100); 1520 count++; 1521 if (count >= 500) { 1522 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1523 "Wait for TX State Machine ready timeout !!\n"); 1524 break; 1525 } 1526 } 1527 1528 /* stop RX DMA path 1529 * 5. 0x284[18] = 1 1530 * 6. wait till 0x284[17] == 1 1531 * wait RX DMA idle */ 1532 count = 0; 1533 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1534 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2))); 1535 do { 1536 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1537 udelay(10); 1538 count++; 1539 } while (!(tmp & BIT(1)) && count < 100); 1540 1541 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1542 "Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n", 1543 count, tmp); 1544 1545 /* reset BB 1546 * 7. 0x02 [0] = 0 */ 1547 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN); 1548 tmp &= ~(BIT(0)); 1549 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmp); 1550 1551 /* Reset TRX MAC 1552 * 8. 0x100 = 0x00 1553 * Delay (1ms) */ 1554 rtl_write_byte(rtlpriv, REG_CR, 0x00); 1555 udelay(1000); 1556 1557 /* Disable MAC Security Engine 1558 * 9. 0x100 bit[9]=0 */ 1559 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1560 tmp &= ~(BIT(1)); 1561 rtl_write_byte(rtlpriv, REG_CR + 1, tmp); 1562 1563 /* To avoid DD-Tim Circuit hang 1564 * 10. 0x553 bit[5]=1 */ 1565 tmp = rtl_read_byte(rtlpriv, REG_DUAL_TSF_RST); 1566 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (tmp | BIT(5))); 1567 1568 /* Enable MAC Security Engine 1569 * 11. 0x100 bit[9]=1 */ 1570 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1571 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(1))); 1572 1573 /* Enable TRX MAC 1574 * 12. 0x100 = 0xFF 1575 * Delay (1ms) */ 1576 rtl_write_byte(rtlpriv, REG_CR, 0xFF); 1577 udelay(1000); 1578 1579 /* Enable BB 1580 * 13. 0x02 [0] = 1 */ 1581 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN); 1582 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmp | BIT(0))); 1583 1584 /* beacon setting 1585 * 14,15. set beacon head page (reg 0x209 and 0x424) */ 1586 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, (u8)boundary); 1587 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, (u8)boundary); 1588 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, (u8)boundary); 1589 1590 /* 16. WMAC_LBK_BF_HD 0x45D[7:0] 1591 * WMAC_LBK_BF_HD */ 1592 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, 1593 (u8)boundary); 1594 1595 rtl_write_word(rtlpriv, REG_TRXFF_BNDY, boundary); 1596 1597 /* init LLT 1598 * 17. init LLT */ 1599 if (!_rtl8821ae_init_llt_table(hw, boundary)) { 1600 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING, 1601 "Failed to init LLT table!\n"); 1602 return false; 1603 } 1604 1605 /* reallocate RQPN 1606 * 18. reallocate RQPN and init LLT */ 1607 rtl_write_word(rtlpriv, REG_RQPN_NPQ, npq_rqpn_value); 1608 rtl_write_dword(rtlpriv, REG_RQPN, rqpn_val); 1609 1610 /* release Tx pause 1611 * 19. 0x522=0x00 */ 1612 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 1613 1614 /* enable PCIE DMA 1615 * 20. 0x301[7:0] = 0x00 1616 * 21. 0x284[18] = 0 */ 1617 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00); 1618 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1619 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2))); 1620 1621 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n"); 1622 return ret; 1623} 1624 1625static void _rtl8821ae_simple_initialize_adapter(struct ieee80211_hw *hw) 1626{ 1627 struct rtl_priv *rtlpriv = rtl_priv(hw); 1628 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1629 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); 1630 1631#if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1) 1632 /* Re-download normal Fw. */ 1633 rtl8821ae_set_fw_related_for_wowlan(hw, false); 1634#endif 1635 1636 /* Re-Initialize LLT table. */ 1637 if (rtlhal->re_init_llt_table) { 1638 u32 rqpn = 0x80e70808; 1639 u8 rqpn_npq = 0, boundary = 0xF8; 1640 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 1641 rqpn = 0x80e90808; 1642 boundary = 0xFA; 1643 } 1644 if (_rtl8821ae_dynamic_rqpn(hw, boundary, rqpn_npq, rqpn)) 1645 rtlhal->re_init_llt_table = false; 1646 } 1647 1648 ppsc->rfpwr_state = ERFON; 1649} 1650 1651static void _rtl8821ae_enable_l1off(struct ieee80211_hw *hw) 1652{ 1653 u8 tmp = 0; 1654 struct rtl_priv *rtlpriv = rtl_priv(hw); 1655 1656 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n"); 1657 1658 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160); 1659 if (!(tmp & (BIT(2) | BIT(3)))) { 1660 rtl_dbg(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD, 1661 "0x160(%#x)return!!\n", tmp); 1662 return; 1663 } 1664 1665 tmp = _rtl8821ae_mdio_read(rtlpriv, 0x1b); 1666 _rtl8821ae_mdio_write(rtlpriv, 0x1b, (tmp | BIT(4))); 1667 1668 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718); 1669 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5)); 1670 1671 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n"); 1672} 1673 1674static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw) 1675{ 1676 u8 tmp = 0; 1677 struct rtl_priv *rtlpriv = rtl_priv(hw); 1678 1679 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n"); 1680 1681 /* Check 0x98[10] */ 1682 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99); 1683 if (!(tmp & BIT(2))) { 1684 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1685 "<---0x99(%#x) return!!\n", tmp); 1686 return; 1687 } 1688 1689 /* LTR idle latency, 0x90 for 144us */ 1690 rtl_write_dword(rtlpriv, 0x798, 0x88908890); 1691 1692 /* LTR active latency, 0x3c for 60us */ 1693 rtl_write_dword(rtlpriv, 0x79c, 0x883c883c); 1694 1695 tmp = rtl_read_byte(rtlpriv, 0x7a4); 1696 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(4))); 1697 1698 tmp = rtl_read_byte(rtlpriv, 0x7a4); 1699 rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0)))); 1700 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0))); 1701 1702 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n"); 1703} 1704 1705static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw) 1706{ 1707 struct rtl_priv *rtlpriv = rtl_priv(hw); 1708 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1709 bool init_finished = true; 1710 u8 tmp = 0; 1711 1712 /* Get Fw wake up reason. */ 1713 _rtl8821ae_get_wakeup_reason(hw); 1714 1715 /* Patch Pcie Rx DMA hang after S3/S4 several times. 1716 * The root cause has not been found. */ 1717 if (_rtl8821ae_check_pcie_dma_hang(hw)) 1718 _rtl8821ae_reset_pcie_interface_dma(hw, true, false); 1719 1720 /* Prepare Tx/Rx Desc Hw address. */ 1721 _rtl8821ae_init_trx_desc_hw_address(hw); 1722 1723 /* Release Pcie Interface Rx DMA to allow wake packet DMA. */ 1724 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE); 1725 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n"); 1726 1727 /* Check wake up event. 1728 * We should check wake packet bit before disable wowlan by H2C or 1729 * Fw will clear the bit. */ 1730 tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3); 1731 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 1732 "Read REG_FTISR 0x13f = %#X\n", tmp); 1733 1734 /* Set the WoWLAN related function control disable. */ 1735 rtl8821ae_set_fw_wowlan_mode(hw, false); 1736 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 0); 1737 1738 if (rtlhal->hw_rof_enable) { 1739 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3); 1740 if (tmp & BIT(1)) { 1741 /* Clear GPIO9 ISR */ 1742 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1)); 1743 init_finished = false; 1744 } else { 1745 init_finished = true; 1746 } 1747 } 1748 1749 if (init_finished) { 1750 _rtl8821ae_simple_initialize_adapter(hw); 1751 1752 /* Release Pcie Interface Tx DMA. */ 1753 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00); 1754 /* Release Pcie RX DMA */ 1755 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 0x02); 1756 1757 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1758 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & (~BIT(0)))); 1759 1760 _rtl8821ae_enable_l1off(hw); 1761 _rtl8821ae_enable_ltr(hw); 1762 } 1763 1764 return init_finished; 1765} 1766 1767static void _rtl8812ae_bb8812_config_1t(struct ieee80211_hw *hw) 1768{ 1769 /* BB OFDM RX Path_A */ 1770 rtl_set_bbreg(hw, 0x808, 0xff, 0x11); 1771 /* BB OFDM TX Path_A */ 1772 rtl_set_bbreg(hw, 0x80c, MASKLWORD, 0x1111); 1773 /* BB CCK R/Rx Path_A */ 1774 rtl_set_bbreg(hw, 0xa04, 0x0c000000, 0x0); 1775 /* MCS support */ 1776 rtl_set_bbreg(hw, 0x8bc, 0xc0000060, 0x4); 1777 /* RF Path_B HSSI OFF */ 1778 rtl_set_bbreg(hw, 0xe00, 0xf, 0x4); 1779 /* RF Path_B Power Down */ 1780 rtl_set_bbreg(hw, 0xe90, MASKDWORD, 0); 1781 /* ADDA Path_B OFF */ 1782 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0); 1783 rtl_set_bbreg(hw, 0xe64, MASKDWORD, 0); 1784} 1785 1786static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw) 1787{ 1788 struct rtl_priv *rtlpriv = rtl_priv(hw); 1789 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1790 u8 u1b_tmp; 1791 1792 rtlhal->mac_func_enable = false; 1793 1794 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1795 /* Combo (PCIe + USB) Card and PCIe-MF Card */ 1796 /* 1. Run LPS WL RFOFF flow */ 1797 /* rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1798 "=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n"); 1799 */ 1800 rtl_hal_pwrseqcmdparsing(rtlpriv, 1801 PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1802 PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW); 1803 } 1804 /* 2. 0x1F[7:0] = 0 */ 1805 /* turn off RF */ 1806 /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */ 1807 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && 1808 rtlhal->fw_ready) { 1809 rtl8821ae_firmware_selfreset(hw); 1810 } 1811 1812 /* Reset MCU. Suggested by Filen. */ 1813 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1); 1814 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2)))); 1815 1816 /* g. MCUFWDL 0x80[1:0]=0 */ 1817 /* reset MCU ready status */ 1818 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1819 1820 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1821 /* HW card disable configuration. */ 1822 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1823 PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW); 1824 } else { 1825 /* HW card disable configuration. */ 1826 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1827 PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW); 1828 } 1829 1830 /* Reset MCU IO Wrapper */ 1831 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1832 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0)))); 1833 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1834 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0)); 1835 1836 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */ 1837 /* lock ISO/CLK/Power control register */ 1838 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); 1839} 1840 1841int rtl8821ae_hw_init(struct ieee80211_hw *hw) 1842{ 1843 struct rtl_priv *rtlpriv = rtl_priv(hw); 1844 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1845 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1846 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1847 bool rtstatus = true; 1848 int err; 1849 u8 tmp_u1b; 1850 bool support_remote_wakeup; 1851 u32 nav_upper = WIFI_NAV_UPPER_US; 1852 1853 rtlhal->being_init_adapter = true; 1854 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 1855 (u8 *)(&support_remote_wakeup)); 1856 rtlpriv->intf_ops->disable_aspm(hw); 1857 1858 /*YP wowlan not considered*/ 1859 1860 tmp_u1b = rtl_read_byte(rtlpriv, REG_CR); 1861 if (tmp_u1b != 0 && tmp_u1b != 0xEA) { 1862 rtlhal->mac_func_enable = true; 1863 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1864 "MAC has already power on.\n"); 1865 } else { 1866 rtlhal->mac_func_enable = false; 1867 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE; 1868 } 1869 1870 if (support_remote_wakeup && 1871 rtlhal->wake_from_pnp_sleep && 1872 rtlhal->mac_func_enable) { 1873 if (_rtl8821ae_wowlan_initialize_adapter(hw)) { 1874 rtlhal->being_init_adapter = false; 1875 return 0; 1876 } 1877 } 1878 1879 if (_rtl8821ae_check_pcie_dma_hang(hw)) { 1880 _rtl8821ae_reset_pcie_interface_dma(hw, 1881 rtlhal->mac_func_enable, 1882 false); 1883 rtlhal->mac_func_enable = false; 1884 } 1885 1886 /* Reset MAC/BB/RF status if it is not powered off 1887 * before calling initialize Hw flow to prevent 1888 * from interface and MAC status mismatch. 1889 * 2013.06.21, by tynli. Suggested by SD1 JackieLau. */ 1890 if (rtlhal->mac_func_enable) { 1891 _rtl8821ae_poweroff_adapter(hw); 1892 rtlhal->mac_func_enable = false; 1893 } 1894 1895 rtstatus = _rtl8821ae_init_mac(hw); 1896 if (!rtstatus) { 1897 pr_err("Init MAC failed\n"); 1898 err = 1; 1899 return err; 1900 } 1901 1902 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG); 1903 tmp_u1b &= 0x7F; 1904 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b); 1905 1906 err = rtl8821ae_download_fw(hw, false); 1907 if (err) { 1908 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1909 "Failed to download FW. Init HW without FW now\n"); 1910 err = 1; 1911 rtlhal->fw_ready = false; 1912 return err; 1913 } else { 1914 rtlhal->fw_ready = true; 1915 } 1916 ppsc->fw_current_inpsmode = false; 1917 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE; 1918 rtlhal->fw_clk_change_in_progress = false; 1919 rtlhal->allow_sw_to_change_hwclc = false; 1920 rtlhal->last_hmeboxnum = 0; 1921 1922 /*SIC_Init(Adapter); 1923 if(rtlhal->AMPDUBurstMode) 1924 rtl_write_byte(rtlpriv,REG_AMPDU_BURST_MODE_8812, 0x7F);*/ 1925 1926 rtl8821ae_phy_mac_config(hw); 1927 /* because last function modify RCR, so we update 1928 * rcr var here, or TP will unstable for receive_config 1929 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx 1930 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252 1931 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); 1932 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 1933 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/ 1934 rtl8821ae_phy_bb_config(hw); 1935 1936 rtl8821ae_phy_rf_config(hw); 1937 1938 if (rtlpriv->phy.rf_type == RF_1T1R && 1939 rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 1940 _rtl8812ae_bb8812_config_1t(hw); 1941 1942 _rtl8821ae_hw_configure(hw); 1943 1944 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G); 1945 1946 /*set wireless mode*/ 1947 1948 rtlhal->mac_func_enable = true; 1949 1950 rtl_cam_reset_all_entry(hw); 1951 1952 rtl8821ae_enable_hw_security_config(hw); 1953 1954 ppsc->rfpwr_state = ERFON; 1955 1956 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1957 _rtl8821ae_enable_aspm_back_door(hw); 1958 rtlpriv->intf_ops->enable_aspm(hw); 1959 1960 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE && 1961 (rtlhal->rfe_type == 1 || rtlhal->rfe_type == 5)) 1962 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x0302); 1963 1964 rtl8821ae_bt_hw_init(hw); 1965 rtlpriv->rtlhal.being_init_adapter = false; 1966 1967 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper); 1968 1969 /* rtl8821ae_dm_check_txpower_tracking(hw); */ 1970 /* rtl8821ae_phy_lc_calibrate(hw); */ 1971 if (support_remote_wakeup) 1972 rtl_write_byte(rtlpriv, REG_WOW_CTRL, 0); 1973 1974 /* Release Rx DMA*/ 1975 tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1976 if (tmp_u1b & BIT(2)) { 1977 /* Release Rx DMA if needed*/ 1978 tmp_u1b &= ~BIT(2); 1979 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b); 1980 } 1981 1982 /* Release Tx/Rx PCIE DMA if*/ 1983 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0); 1984 1985 rtl8821ae_dm_init(hw); 1986 rtl8821ae_macid_initialize_mediastatus(hw); 1987 1988 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "%s() <====\n", __func__); 1989 return err; 1990} 1991 1992static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw) 1993{ 1994 struct rtl_priv *rtlpriv = rtl_priv(hw); 1995 struct rtl_phy *rtlphy = &rtlpriv->phy; 1996 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1997 enum version_8821ae version = VERSION_UNKNOWN; 1998 u32 value32; 1999 2000 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 2001 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2002 "ReadChipVersion8812A 0xF0 = 0x%x\n", value32); 2003 2004 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 2005 rtlphy->rf_type = RF_2T2R; 2006 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) 2007 rtlphy->rf_type = RF_1T1R; 2008 2009 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2010 "RF_Type is %x!!\n", rtlphy->rf_type); 2011 2012 if (value32 & TRP_VAUX_EN) { 2013 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 2014 if (rtlphy->rf_type == RF_2T2R) 2015 version = VERSION_TEST_CHIP_2T2R_8812; 2016 else 2017 version = VERSION_TEST_CHIP_1T1R_8812; 2018 } else 2019 version = VERSION_TEST_CHIP_8821; 2020 } else { 2021 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 2022 u32 rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) + 1; 2023 2024 if (rtlphy->rf_type == RF_2T2R) 2025 version = 2026 (enum version_8821ae)(CHIP_8812 2027 | NORMAL_CHIP | 2028 RF_TYPE_2T2R); 2029 else 2030 version = (enum version_8821ae)(CHIP_8812 2031 | NORMAL_CHIP); 2032 2033 version = (enum version_8821ae)(version | (rtl_id << 12)); 2034 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 2035 u32 rtl_id = value32 & CHIP_VER_RTL_MASK; 2036 2037 version = (enum version_8821ae)(CHIP_8821 2038 | NORMAL_CHIP | rtl_id); 2039 } 2040 } 2041 2042 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 2043 /*WL_HWROF_EN.*/ 2044 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); 2045 rtlhal->hw_rof_enable = ((value32 & WL_HWROF_EN) ? 1 : 0); 2046 } 2047 2048 switch (version) { 2049 case VERSION_TEST_CHIP_1T1R_8812: 2050 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2051 "Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n"); 2052 break; 2053 case VERSION_TEST_CHIP_2T2R_8812: 2054 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2055 "Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n"); 2056 break; 2057 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812: 2058 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2059 "Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n"); 2060 break; 2061 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812: 2062 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2063 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n"); 2064 break; 2065 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT: 2066 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2067 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n"); 2068 break; 2069 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT: 2070 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2071 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n"); 2072 break; 2073 case VERSION_TEST_CHIP_8821: 2074 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2075 "Chip Version ID: VERSION_TEST_CHIP_8821\n"); 2076 break; 2077 case VERSION_NORMAL_TSMC_CHIP_8821: 2078 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2079 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n"); 2080 break; 2081 case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT: 2082 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2083 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n"); 2084 break; 2085 default: 2086 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2087 "Chip Version ID: Unknown (0x%X)\n", version); 2088 break; 2089 } 2090 2091 return version; 2092} 2093 2094static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw, 2095 enum nl80211_iftype type) 2096{ 2097 struct rtl_priv *rtlpriv = rtl_priv(hw); 2098 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 2099 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 2100 bt_msr &= 0xfc; 2101 2102 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0); 2103 rtl_dbg(rtlpriv, COMP_BEACON, DBG_LOUD, 2104 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n"); 2105 2106 if (type == NL80211_IFTYPE_UNSPECIFIED || 2107 type == NL80211_IFTYPE_STATION) { 2108 _rtl8821ae_stop_tx_beacon(hw); 2109 _rtl8821ae_enable_bcn_sub_func(hw); 2110 } else if (type == NL80211_IFTYPE_ADHOC || 2111 type == NL80211_IFTYPE_AP) { 2112 _rtl8821ae_resume_tx_beacon(hw); 2113 _rtl8821ae_disable_bcn_sub_func(hw); 2114 } else { 2115 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 2116 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n", 2117 type); 2118 } 2119 2120 switch (type) { 2121 case NL80211_IFTYPE_UNSPECIFIED: 2122 bt_msr |= MSR_NOLINK; 2123 ledaction = LED_CTL_LINK; 2124 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 2125 "Set Network type to NO LINK!\n"); 2126 break; 2127 case NL80211_IFTYPE_ADHOC: 2128 bt_msr |= MSR_ADHOC; 2129 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 2130 "Set Network type to Ad Hoc!\n"); 2131 break; 2132 case NL80211_IFTYPE_STATION: 2133 bt_msr |= MSR_INFRA; 2134 ledaction = LED_CTL_LINK; 2135 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 2136 "Set Network type to STA!\n"); 2137 break; 2138 case NL80211_IFTYPE_AP: 2139 bt_msr |= MSR_AP; 2140 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 2141 "Set Network type to AP!\n"); 2142 break; 2143 default: 2144 pr_err("Network type %d not support!\n", type); 2145 return 1; 2146 } 2147 2148 rtl_write_byte(rtlpriv, MSR, bt_msr); 2149 rtlpriv->cfg->ops->led_control(hw, ledaction); 2150 if ((bt_msr & MSR_MASK) == MSR_AP) 2151 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 2152 else 2153 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 2154 2155 return 0; 2156} 2157 2158void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 2159{ 2160 struct rtl_priv *rtlpriv = rtl_priv(hw); 2161 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2162 u32 reg_rcr = rtlpci->receive_config; 2163 2164 if (rtlpriv->psc.rfpwr_state != ERFON) 2165 return; 2166 2167 if (check_bssid) { 2168 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 2169 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 2170 (u8 *)(®_rcr)); 2171 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4)); 2172 } else if (!check_bssid) { 2173 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 2174 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0); 2175 rtlpriv->cfg->ops->set_hw_reg(hw, 2176 HW_VAR_RCR, (u8 *)(®_rcr)); 2177 } 2178} 2179 2180int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 2181{ 2182 struct rtl_priv *rtlpriv = rtl_priv(hw); 2183 2184 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "%s!\n", __func__); 2185 2186 if (_rtl8821ae_set_media_status(hw, type)) 2187 return -EOPNOTSUPP; 2188 2189 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 2190 if (type != NL80211_IFTYPE_AP) 2191 rtl8821ae_set_check_bssid(hw, true); 2192 } else { 2193 rtl8821ae_set_check_bssid(hw, false); 2194 } 2195 2196 return 0; 2197} 2198 2199/* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */ 2200void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci) 2201{ 2202 struct rtl_priv *rtlpriv = rtl_priv(hw); 2203 rtl8821ae_dm_init_edca_turbo(hw); 2204 switch (aci) { 2205 case AC1_BK: 2206 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); 2207 break; 2208 case AC0_BE: 2209 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */ 2210 break; 2211 case AC2_VI: 2212 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); 2213 break; 2214 case AC3_VO: 2215 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); 2216 break; 2217 default: 2218 WARN_ONCE(true, "rtl8821ae: invalid aci: %d !\n", aci); 2219 break; 2220 } 2221} 2222 2223static void rtl8821ae_clear_interrupt(struct ieee80211_hw *hw) 2224{ 2225 struct rtl_priv *rtlpriv = rtl_priv(hw); 2226 u32 tmp = rtl_read_dword(rtlpriv, REG_HISR); 2227 2228 rtl_write_dword(rtlpriv, REG_HISR, tmp); 2229 2230 tmp = rtl_read_dword(rtlpriv, REG_HISRE); 2231 rtl_write_dword(rtlpriv, REG_HISRE, tmp); 2232 2233 tmp = rtl_read_dword(rtlpriv, REG_HSISR); 2234 rtl_write_dword(rtlpriv, REG_HSISR, tmp); 2235} 2236 2237void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw) 2238{ 2239 struct rtl_priv *rtlpriv = rtl_priv(hw); 2240 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2241 2242 if (rtlpci->int_clear) 2243 rtl8821ae_clear_interrupt(hw);/*clear it here first*/ 2244 2245 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); 2246 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); 2247 rtlpci->irq_enabled = true; 2248 /* there are some C2H CMDs have been sent before 2249 system interrupt is enabled, e.g., C2H, CPWM. 2250 *So we need to clear all C2H events that FW has 2251 notified, otherwise FW won't schedule any commands anymore. 2252 */ 2253 /* rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); */ 2254 /*enable system interrupt*/ 2255 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF); 2256} 2257 2258void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw) 2259{ 2260 struct rtl_priv *rtlpriv = rtl_priv(hw); 2261 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2262 2263 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED); 2264 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED); 2265 rtlpci->irq_enabled = false; 2266 /*synchronize_irq(rtlpci->pdev->irq);*/ 2267} 2268 2269static void _rtl8821ae_clear_pci_pme_status(struct ieee80211_hw *hw) 2270{ 2271 struct rtl_priv *rtlpriv = rtl_priv(hw); 2272 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2273 struct pci_dev *pdev = rtlpci->pdev; 2274 u16 pmcs_reg; 2275 u8 pm_cap; 2276 2277 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 2278 if (!pm_cap) { 2279 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING, 2280 "Cannot find PME Capability\n"); 2281 return; 2282 } 2283 2284 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pmcs_reg); 2285 if (pmcs_reg & PCI_PM_CTRL_PME_STATUS) { 2286 /* Clear PME_Status with write */ 2287 pci_write_config_word(pdev, pm_cap + PCI_PM_CTRL, pmcs_reg); 2288 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pmcs_reg); 2289 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 2290 "Cleared PME status, PMCS reg = 0x%4x\n", pmcs_reg); 2291 } else { 2292 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 2293 "PMCS reg = 0x%4x\n", pmcs_reg); 2294 } 2295} 2296 2297void rtl8821ae_card_disable(struct ieee80211_hw *hw) 2298{ 2299 struct rtl_priv *rtlpriv = rtl_priv(hw); 2300 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2301 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); 2302 struct rtl_mac *mac = rtl_mac(rtlpriv); 2303 enum nl80211_iftype opmode; 2304 bool support_remote_wakeup; 2305 u8 tmp; 2306 u32 count = 0; 2307 2308 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 2309 (u8 *)(&support_remote_wakeup)); 2310 2311 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2312 2313 if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION) 2314 || !rtlhal->enter_pnp_sleep) { 2315 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n"); 2316 mac->link_state = MAC80211_NOLINK; 2317 opmode = NL80211_IFTYPE_UNSPECIFIED; 2318 _rtl8821ae_set_media_status(hw, opmode); 2319 _rtl8821ae_poweroff_adapter(hw); 2320 } else { 2321 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n"); 2322 /* 3 <1> Prepare for configuring wowlan related infomations */ 2323 /* Clear Fw WoWLAN event. */ 2324 rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0); 2325 2326#if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1) 2327 rtl8821ae_set_fw_related_for_wowlan(hw, true); 2328#endif 2329 /* Dynamically adjust Tx packet boundary 2330 * for download reserved page packet. 2331 * reserve 30 pages for rsvd page */ 2332 if (_rtl8821ae_dynamic_rqpn(hw, 0xE0, 0x3, 0x80c20d0d)) 2333 rtlhal->re_init_llt_table = true; 2334 2335 /* 3 <2> Set Fw related H2C cmd. */ 2336 2337 /* Set WoWLAN related security information. */ 2338 rtl8821ae_set_fw_global_info_cmd(hw); 2339 2340 _rtl8821ae_download_rsvd_page(hw, true); 2341 2342 /* Just enable AOAC related functions when we connect to AP. */ 2343 printk("mac->link_state = %d\n", mac->link_state); 2344 if (mac->link_state >= MAC80211_LINKED && 2345 mac->opmode == NL80211_IFTYPE_STATION) { 2346 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL); 2347 rtl8821ae_set_fw_media_status_rpt_cmd(hw, 2348 RT_MEDIA_CONNECT); 2349 2350 rtl8821ae_set_fw_wowlan_mode(hw, true); 2351 /* Enable Fw Keep alive mechanism. */ 2352 rtl8821ae_set_fw_keep_alive_cmd(hw, true); 2353 2354 /* Enable disconnect decision control. */ 2355 rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(hw, true); 2356 } 2357 2358 /* 3 <3> Hw Configutations */ 2359 2360 /* Wait until Rx DMA Finished before host sleep. 2361 * FW Pause Rx DMA may happen when received packet doing DMA. 2362 */ 2363 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, BIT(2)); 2364 2365 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 2366 count = 0; 2367 while (!(tmp & BIT(1)) && (count++ < 100)) { 2368 udelay(10); 2369 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 2370 } 2371 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2372 "Wait Rx DMA Finished before host sleep. count=%d\n", 2373 count); 2374 2375 /* reset trx ring */ 2376 rtlpriv->intf_ops->reset_trx_ring(hw); 2377 2378 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x0); 2379 2380 _rtl8821ae_clear_pci_pme_status(hw); 2381 tmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR); 2382 rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmp | BIT(3)); 2383 /* prevent 8051 to be reset by PERST */ 2384 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x20); 2385 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x60); 2386 } 2387 2388 if (rtlpriv->rtlhal.driver_is_goingto_unload || 2389 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 2390 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 2391 /* For wowlan+LPS+32k. */ 2392 if (support_remote_wakeup && rtlhal->enter_pnp_sleep) { 2393 /* Set the WoWLAN related function control enable. 2394 * It should be the last H2C cmd in the WoWLAN flow. */ 2395 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 1); 2396 2397 /* Stop Pcie Interface Tx DMA. */ 2398 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff); 2399 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n"); 2400 2401 /* Wait for TxDMA idle. */ 2402 count = 0; 2403 do { 2404 tmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG); 2405 udelay(10); 2406 count++; 2407 } while ((tmp != 0) && (count < 100)); 2408 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2409 "Wait Tx DMA Finished before host sleep. count=%d\n", 2410 count); 2411 2412 if (rtlhal->hw_rof_enable) { 2413 printk("hw_rof_enable\n"); 2414 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3); 2415 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1)); 2416 } 2417 } 2418 /* after power off we should do iqk again */ 2419 rtlpriv->phy.iqk_initialized = false; 2420} 2421 2422void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw, 2423 struct rtl_int *intvec) 2424{ 2425 struct rtl_priv *rtlpriv = rtl_priv(hw); 2426 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2427 2428 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; 2429 rtl_write_dword(rtlpriv, ISR, intvec->inta); 2430 2431 intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1]; 2432 rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb); 2433} 2434 2435void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw) 2436{ 2437 struct rtl_priv *rtlpriv = rtl_priv(hw); 2438 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2439 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2440 u16 bcn_interval, atim_window; 2441 2442 bcn_interval = mac->beacon_interval; 2443 atim_window = 2; /*FIX MERGE */ 2444 rtl8821ae_disable_interrupt(hw); 2445 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 2446 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 2447 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); 2448 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); 2449 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); 2450 rtl_write_byte(rtlpriv, 0x606, 0x30); 2451 rtlpci->reg_bcn_ctrl_val |= BIT(3); 2452 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); 2453 rtl8821ae_enable_interrupt(hw); 2454} 2455 2456void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw) 2457{ 2458 struct rtl_priv *rtlpriv = rtl_priv(hw); 2459 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2460 u16 bcn_interval = mac->beacon_interval; 2461 2462 rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG, 2463 "beacon_interval:%d\n", bcn_interval); 2464 rtl8821ae_disable_interrupt(hw); 2465 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 2466 rtl8821ae_enable_interrupt(hw); 2467} 2468 2469void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw, 2470 u32 add_msr, u32 rm_msr) 2471{ 2472 struct rtl_priv *rtlpriv = rtl_priv(hw); 2473 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2474 2475 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, 2476 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr); 2477 2478 if (add_msr) 2479 rtlpci->irq_mask[0] |= add_msr; 2480 if (rm_msr) 2481 rtlpci->irq_mask[0] &= (~rm_msr); 2482 rtl8821ae_disable_interrupt(hw); 2483 rtl8821ae_enable_interrupt(hw); 2484} 2485 2486static u8 _rtl8821ae_get_chnl_group(u8 chnl) 2487{ 2488 u8 group = 0; 2489 2490 if (chnl <= 14) { 2491 if (1 <= chnl && chnl <= 2) 2492 group = 0; 2493 else if (3 <= chnl && chnl <= 5) 2494 group = 1; 2495 else if (6 <= chnl && chnl <= 8) 2496 group = 2; 2497 else if (9 <= chnl && chnl <= 11) 2498 group = 3; 2499 else /*if (12 <= chnl && chnl <= 14)*/ 2500 group = 4; 2501 } else { 2502 if (36 <= chnl && chnl <= 42) 2503 group = 0; 2504 else if (44 <= chnl && chnl <= 48) 2505 group = 1; 2506 else if (50 <= chnl && chnl <= 58) 2507 group = 2; 2508 else if (60 <= chnl && chnl <= 64) 2509 group = 3; 2510 else if (100 <= chnl && chnl <= 106) 2511 group = 4; 2512 else if (108 <= chnl && chnl <= 114) 2513 group = 5; 2514 else if (116 <= chnl && chnl <= 122) 2515 group = 6; 2516 else if (124 <= chnl && chnl <= 130) 2517 group = 7; 2518 else if (132 <= chnl && chnl <= 138) 2519 group = 8; 2520 else if (140 <= chnl && chnl <= 144) 2521 group = 9; 2522 else if (149 <= chnl && chnl <= 155) 2523 group = 10; 2524 else if (157 <= chnl && chnl <= 161) 2525 group = 11; 2526 else if (165 <= chnl && chnl <= 171) 2527 group = 12; 2528 else if (173 <= chnl && chnl <= 177) 2529 group = 13; 2530 else 2531 WARN_ONCE(true, 2532 "rtl8821ae: 5G, Channel %d in Group not found\n", 2533 chnl); 2534 } 2535 return group; 2536} 2537 2538static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw, 2539 struct txpower_info_2g *pwrinfo24g, 2540 struct txpower_info_5g *pwrinfo5g, 2541 bool autoload_fail, 2542 u8 *hwinfo) 2543{ 2544 struct rtl_priv *rtlpriv = rtl_priv(hw); 2545 u32 rfpath, eeaddr = EEPROM_TX_PWR_INX, group, txcount = 0; 2546 2547 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2548 "hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n", 2549 (eeaddr + 1), hwinfo[eeaddr + 1]); 2550 if (hwinfo[eeaddr + 1] == 0xFF) /*YJ,add,120316*/ 2551 autoload_fail = true; 2552 2553 if (autoload_fail) { 2554 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2555 "auto load fail : Use Default value!\n"); 2556 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) { 2557 /*2.4G default value*/ 2558 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { 2559 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D; 2560 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D; 2561 } 2562 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) { 2563 if (txcount == 0) { 2564 pwrinfo24g->bw20_diff[rfpath][0] = 0x02; 2565 pwrinfo24g->ofdm_diff[rfpath][0] = 0x04; 2566 } else { 2567 pwrinfo24g->bw20_diff[rfpath][txcount] = 0xFE; 2568 pwrinfo24g->bw40_diff[rfpath][txcount] = 0xFE; 2569 pwrinfo24g->cck_diff[rfpath][txcount] = 0xFE; 2570 pwrinfo24g->ofdm_diff[rfpath][txcount] = 0xFE; 2571 } 2572 } 2573 /*5G default value*/ 2574 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) 2575 pwrinfo5g->index_bw40_base[rfpath][group] = 0x2A; 2576 2577 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) { 2578 if (txcount == 0) { 2579 pwrinfo5g->ofdm_diff[rfpath][0] = 0x04; 2580 pwrinfo5g->bw20_diff[rfpath][0] = 0x00; 2581 pwrinfo5g->bw80_diff[rfpath][0] = 0xFE; 2582 pwrinfo5g->bw160_diff[rfpath][0] = 0xFE; 2583 } else { 2584 pwrinfo5g->ofdm_diff[rfpath][0] = 0xFE; 2585 pwrinfo5g->bw20_diff[rfpath][0] = 0xFE; 2586 pwrinfo5g->bw40_diff[rfpath][0] = 0xFE; 2587 pwrinfo5g->bw80_diff[rfpath][0] = 0xFE; 2588 pwrinfo5g->bw160_diff[rfpath][0] = 0xFE; 2589 } 2590 } 2591 } 2592 return; 2593 } 2594 2595 rtl_priv(hw)->efuse.txpwr_fromeprom = true; 2596 2597 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) { 2598 /*2.4G default value*/ 2599 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { 2600 pwrinfo24g->index_cck_base[rfpath][group] = hwinfo[eeaddr++]; 2601 if (pwrinfo24g->index_cck_base[rfpath][group] == 0xFF) 2602 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D; 2603 } 2604 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) { 2605 pwrinfo24g->index_bw40_base[rfpath][group] = hwinfo[eeaddr++]; 2606 if (pwrinfo24g->index_bw40_base[rfpath][group] == 0xFF) 2607 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D; 2608 } 2609 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) { 2610 if (txcount == 0) { 2611 pwrinfo24g->bw40_diff[rfpath][txcount] = 0; 2612 /*bit sign number to 8 bit sign number*/ 2613 pwrinfo24g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4; 2614 if (pwrinfo24g->bw20_diff[rfpath][txcount] & BIT(3)) 2615 pwrinfo24g->bw20_diff[rfpath][txcount] |= 0xF0; 2616 /*bit sign number to 8 bit sign number*/ 2617 pwrinfo24g->ofdm_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f); 2618 if (pwrinfo24g->ofdm_diff[rfpath][txcount] & BIT(3)) 2619 pwrinfo24g->ofdm_diff[rfpath][txcount] |= 0xF0; 2620 2621 pwrinfo24g->cck_diff[rfpath][txcount] = 0; 2622 eeaddr++; 2623 } else { 2624 pwrinfo24g->bw40_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4; 2625 if (pwrinfo24g->bw40_diff[rfpath][txcount] & BIT(3)) 2626 pwrinfo24g->bw40_diff[rfpath][txcount] |= 0xF0; 2627 2628 pwrinfo24g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f); 2629 if (pwrinfo24g->bw20_diff[rfpath][txcount] & BIT(3)) 2630 pwrinfo24g->bw20_diff[rfpath][txcount] |= 0xF0; 2631 2632 eeaddr++; 2633 2634 pwrinfo24g->ofdm_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4; 2635 if (pwrinfo24g->ofdm_diff[rfpath][txcount] & BIT(3)) 2636 pwrinfo24g->ofdm_diff[rfpath][txcount] |= 0xF0; 2637 2638 pwrinfo24g->cck_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f); 2639 if (pwrinfo24g->cck_diff[rfpath][txcount] & BIT(3)) 2640 pwrinfo24g->cck_diff[rfpath][txcount] |= 0xF0; 2641 2642 eeaddr++; 2643 } 2644 } 2645 2646 /*5G default value*/ 2647 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) { 2648 pwrinfo5g->index_bw40_base[rfpath][group] = hwinfo[eeaddr++]; 2649 if (pwrinfo5g->index_bw40_base[rfpath][group] == 0xFF) 2650 pwrinfo5g->index_bw40_base[rfpath][group] = 0xFE; 2651 } 2652 2653 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) { 2654 if (txcount == 0) { 2655 pwrinfo5g->bw40_diff[rfpath][txcount] = 0; 2656 2657 pwrinfo5g->bw20_diff[rfpath][0] = (hwinfo[eeaddr] & 0xf0) >> 4; 2658 if (pwrinfo5g->bw20_diff[rfpath][txcount] & BIT(3)) 2659 pwrinfo5g->bw20_diff[rfpath][txcount] |= 0xF0; 2660 2661 pwrinfo5g->ofdm_diff[rfpath][0] = (hwinfo[eeaddr] & 0x0f); 2662 if (pwrinfo5g->ofdm_diff[rfpath][txcount] & BIT(3)) 2663 pwrinfo5g->ofdm_diff[rfpath][txcount] |= 0xF0; 2664 2665 eeaddr++; 2666 } else { 2667 pwrinfo5g->bw40_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4; 2668 if (pwrinfo5g->bw40_diff[rfpath][txcount] & BIT(3)) 2669 pwrinfo5g->bw40_diff[rfpath][txcount] |= 0xF0; 2670 2671 pwrinfo5g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f); 2672 if (pwrinfo5g->bw20_diff[rfpath][txcount] & BIT(3)) 2673 pwrinfo5g->bw20_diff[rfpath][txcount] |= 0xF0; 2674 2675 eeaddr++; 2676 } 2677 } 2678 2679 pwrinfo5g->ofdm_diff[rfpath][1] = (hwinfo[eeaddr] & 0xf0) >> 4; 2680 pwrinfo5g->ofdm_diff[rfpath][2] = (hwinfo[eeaddr] & 0x0f); 2681 2682 eeaddr++; 2683 2684 pwrinfo5g->ofdm_diff[rfpath][3] = (hwinfo[eeaddr] & 0x0f); 2685 2686 eeaddr++; 2687 2688 for (txcount = 1; txcount < MAX_TX_COUNT; txcount++) { 2689 if (pwrinfo5g->ofdm_diff[rfpath][txcount] & BIT(3)) 2690 pwrinfo5g->ofdm_diff[rfpath][txcount] |= 0xF0; 2691 } 2692 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) { 2693 pwrinfo5g->bw80_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4; 2694 /* 4bit sign number to 8 bit sign number */ 2695 if (pwrinfo5g->bw80_diff[rfpath][txcount] & BIT(3)) 2696 pwrinfo5g->bw80_diff[rfpath][txcount] |= 0xF0; 2697 /* 4bit sign number to 8 bit sign number */ 2698 pwrinfo5g->bw160_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f); 2699 if (pwrinfo5g->bw160_diff[rfpath][txcount] & BIT(3)) 2700 pwrinfo5g->bw160_diff[rfpath][txcount] |= 0xF0; 2701 2702 eeaddr++; 2703 } 2704 } 2705} 2706#if 0 2707static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 2708 bool autoload_fail, 2709 u8 *hwinfo) 2710{ 2711 struct rtl_priv *rtlpriv = rtl_priv(hw); 2712 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2713 struct txpower_info_2g pwrinfo24g; 2714 struct txpower_info_5g pwrinfo5g; 2715 u8 rf_path, index; 2716 u8 i; 2717 2718 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g, 2719 &pwrinfo5g, autoload_fail, hwinfo); 2720 2721 for (rf_path = 0; rf_path < 2; rf_path++) { 2722 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) { 2723 index = _rtl8821ae_get_chnl_group(i + 1); 2724 2725 if (i == CHANNEL_MAX_NUMBER_2G - 1) { 2726 rtlefuse->txpwrlevel_cck[rf_path][i] = 2727 pwrinfo24g.index_cck_base[rf_path][5]; 2728 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 2729 pwrinfo24g.index_bw40_base[rf_path][index]; 2730 } else { 2731 rtlefuse->txpwrlevel_cck[rf_path][i] = 2732 pwrinfo24g.index_cck_base[rf_path][index]; 2733 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 2734 pwrinfo24g.index_bw40_base[rf_path][index]; 2735 } 2736 } 2737 2738 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) { 2739 index = _rtl8821ae_get_chnl_group(channel5g[i]); 2740 rtlefuse->txpwr_5g_bw40base[rf_path][i] = 2741 pwrinfo5g.index_bw40_base[rf_path][index]; 2742 } 2743 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) { 2744 u8 upper, lower; 2745 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]); 2746 upper = pwrinfo5g.index_bw40_base[rf_path][index]; 2747 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1]; 2748 2749 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2; 2750 } 2751 for (i = 0; i < MAX_TX_COUNT; i++) { 2752 rtlefuse->txpwr_cckdiff[rf_path][i] = 2753 pwrinfo24g.cck_diff[rf_path][i]; 2754 rtlefuse->txpwr_legacyhtdiff[rf_path][i] = 2755 pwrinfo24g.ofdm_diff[rf_path][i]; 2756 rtlefuse->txpwr_ht20diff[rf_path][i] = 2757 pwrinfo24g.bw20_diff[rf_path][i]; 2758 rtlefuse->txpwr_ht40diff[rf_path][i] = 2759 pwrinfo24g.bw40_diff[rf_path][i]; 2760 2761 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] = 2762 pwrinfo5g.ofdm_diff[rf_path][i]; 2763 rtlefuse->txpwr_5g_bw20diff[rf_path][i] = 2764 pwrinfo5g.bw20_diff[rf_path][i]; 2765 rtlefuse->txpwr_5g_bw40diff[rf_path][i] = 2766 pwrinfo5g.bw40_diff[rf_path][i]; 2767 rtlefuse->txpwr_5g_bw80diff[rf_path][i] = 2768 pwrinfo5g.bw80_diff[rf_path][i]; 2769 } 2770 } 2771 2772 if (!autoload_fail) { 2773 rtlefuse->eeprom_regulatory = 2774 hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/ 2775 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF) 2776 rtlefuse->eeprom_regulatory = 0; 2777 } else { 2778 rtlefuse->eeprom_regulatory = 0; 2779 } 2780 2781 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 2782 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 2783} 2784#endif 2785static noinline_for_stack void 2786_rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 2787 bool autoload_fail, u8 *hwinfo) 2788{ 2789 struct rtl_priv *rtlpriv = rtl_priv(hw); 2790 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2791 struct txpower_info_2g pwrinfo24g; 2792 struct txpower_info_5g pwrinfo5g; 2793 u8 rf_path, index; 2794 u8 i; 2795 2796 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g, 2797 &pwrinfo5g, autoload_fail, hwinfo); 2798 2799 for (rf_path = 0; rf_path < 2; rf_path++) { 2800 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) { 2801 index = _rtl8821ae_get_chnl_group(i + 1); 2802 2803 if (i == CHANNEL_MAX_NUMBER_2G - 1) { 2804 rtlefuse->txpwrlevel_cck[rf_path][i] = 2805 pwrinfo24g.index_cck_base[rf_path][5]; 2806 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 2807 pwrinfo24g.index_bw40_base[rf_path][index]; 2808 } else { 2809 rtlefuse->txpwrlevel_cck[rf_path][i] = 2810 pwrinfo24g.index_cck_base[rf_path][index]; 2811 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 2812 pwrinfo24g.index_bw40_base[rf_path][index]; 2813 } 2814 } 2815 2816 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) { 2817 index = _rtl8821ae_get_chnl_group(channel5g[i]); 2818 rtlefuse->txpwr_5g_bw40base[rf_path][i] = 2819 pwrinfo5g.index_bw40_base[rf_path][index]; 2820 } 2821 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) { 2822 u8 upper, lower; 2823 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]); 2824 upper = pwrinfo5g.index_bw40_base[rf_path][index]; 2825 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1]; 2826 2827 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2; 2828 } 2829 for (i = 0; i < MAX_TX_COUNT; i++) { 2830 rtlefuse->txpwr_cckdiff[rf_path][i] = 2831 pwrinfo24g.cck_diff[rf_path][i]; 2832 rtlefuse->txpwr_legacyhtdiff[rf_path][i] = 2833 pwrinfo24g.ofdm_diff[rf_path][i]; 2834 rtlefuse->txpwr_ht20diff[rf_path][i] = 2835 pwrinfo24g.bw20_diff[rf_path][i]; 2836 rtlefuse->txpwr_ht40diff[rf_path][i] = 2837 pwrinfo24g.bw40_diff[rf_path][i]; 2838 2839 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] = 2840 pwrinfo5g.ofdm_diff[rf_path][i]; 2841 rtlefuse->txpwr_5g_bw20diff[rf_path][i] = 2842 pwrinfo5g.bw20_diff[rf_path][i]; 2843 rtlefuse->txpwr_5g_bw40diff[rf_path][i] = 2844 pwrinfo5g.bw40_diff[rf_path][i]; 2845 rtlefuse->txpwr_5g_bw80diff[rf_path][i] = 2846 pwrinfo5g.bw80_diff[rf_path][i]; 2847 } 2848 } 2849 /*bit0~2*/ 2850 if (!autoload_fail) { 2851 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07; 2852 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF) 2853 rtlefuse->eeprom_regulatory = 0; 2854 } else { 2855 rtlefuse->eeprom_regulatory = 0; 2856 } 2857 2858 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 2859 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 2860} 2861 2862static void _rtl8812ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo, 2863 bool autoload_fail) 2864{ 2865 struct rtl_priv *rtlpriv = rtl_priv(hw); 2866 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2867 2868 if (!autoload_fail) { 2869 rtlhal->pa_type_2g = hwinfo[0XBC]; 2870 rtlhal->lna_type_2g = hwinfo[0XBD]; 2871 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) { 2872 rtlhal->pa_type_2g = 0; 2873 rtlhal->lna_type_2g = 0; 2874 } 2875 rtlhal->external_pa_2g = ((rtlhal->pa_type_2g & BIT(5)) && 2876 (rtlhal->pa_type_2g & BIT(4))) ? 2877 1 : 0; 2878 rtlhal->external_lna_2g = ((rtlhal->lna_type_2g & BIT(7)) && 2879 (rtlhal->lna_type_2g & BIT(3))) ? 2880 1 : 0; 2881 2882 rtlhal->pa_type_5g = hwinfo[0XBC]; 2883 rtlhal->lna_type_5g = hwinfo[0XBF]; 2884 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) { 2885 rtlhal->pa_type_5g = 0; 2886 rtlhal->lna_type_5g = 0; 2887 } 2888 rtlhal->external_pa_5g = ((rtlhal->pa_type_5g & BIT(1)) && 2889 (rtlhal->pa_type_5g & BIT(0))) ? 2890 1 : 0; 2891 rtlhal->external_lna_5g = ((rtlhal->lna_type_5g & BIT(7)) && 2892 (rtlhal->lna_type_5g & BIT(3))) ? 2893 1 : 0; 2894 } else { 2895 rtlhal->external_pa_2g = 0; 2896 rtlhal->external_lna_2g = 0; 2897 rtlhal->external_pa_5g = 0; 2898 rtlhal->external_lna_5g = 0; 2899 } 2900} 2901 2902static void _rtl8812ae_read_amplifier_type(struct ieee80211_hw *hw, u8 *hwinfo, 2903 bool autoload_fail) 2904{ 2905 struct rtl_priv *rtlpriv = rtl_priv(hw); 2906 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2907 2908 u8 ext_type_pa_2g_a = (hwinfo[0XBD] & BIT(2)) >> 2; /* 0XBD[2] */ 2909 u8 ext_type_pa_2g_b = (hwinfo[0XBD] & BIT(6)) >> 6; /* 0XBD[6] */ 2910 u8 ext_type_pa_5g_a = (hwinfo[0XBF] & BIT(2)) >> 2; /* 0XBF[2] */ 2911 u8 ext_type_pa_5g_b = (hwinfo[0XBF] & BIT(6)) >> 6; /* 0XBF[6] */ 2912 /* 0XBD[1:0] */ 2913 u8 ext_type_lna_2g_a = (hwinfo[0XBD] & (BIT(1) | BIT(0))) >> 0; 2914 /* 0XBD[5:4] */ 2915 u8 ext_type_lna_2g_b = (hwinfo[0XBD] & (BIT(5) | BIT(4))) >> 4; 2916 /* 0XBF[1:0] */ 2917 u8 ext_type_lna_5g_a = (hwinfo[0XBF] & (BIT(1) | BIT(0))) >> 0; 2918 /* 0XBF[5:4] */ 2919 u8 ext_type_lna_5g_b = (hwinfo[0XBF] & (BIT(5) | BIT(4))) >> 4; 2920 2921 _rtl8812ae_read_pa_type(hw, hwinfo, autoload_fail); 2922 2923 /* [2.4G] Path A and B are both extPA */ 2924 if ((rtlhal->pa_type_2g & (BIT(5) | BIT(4))) == (BIT(5) | BIT(4))) 2925 rtlhal->type_gpa = ext_type_pa_2g_b << 2 | ext_type_pa_2g_a; 2926 2927 /* [5G] Path A and B are both extPA */ 2928 if ((rtlhal->pa_type_5g & (BIT(1) | BIT(0))) == (BIT(1) | BIT(0))) 2929 rtlhal->type_apa = ext_type_pa_5g_b << 2 | ext_type_pa_5g_a; 2930 2931 /* [2.4G] Path A and B are both extLNA */ 2932 if ((rtlhal->lna_type_2g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3))) 2933 rtlhal->type_glna = ext_type_lna_2g_b << 2 | ext_type_lna_2g_a; 2934 2935 /* [5G] Path A and B are both extLNA */ 2936 if ((rtlhal->lna_type_5g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3))) 2937 rtlhal->type_alna = ext_type_lna_5g_b << 2 | ext_type_lna_5g_a; 2938} 2939 2940static void _rtl8821ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo, 2941 bool autoload_fail) 2942{ 2943 struct rtl_priv *rtlpriv = rtl_priv(hw); 2944 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2945 2946 if (!autoload_fail) { 2947 rtlhal->pa_type_2g = hwinfo[0XBC]; 2948 rtlhal->lna_type_2g = hwinfo[0XBD]; 2949 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) { 2950 rtlhal->pa_type_2g = 0; 2951 rtlhal->lna_type_2g = 0; 2952 } 2953 rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0; 2954 rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0; 2955 2956 rtlhal->pa_type_5g = hwinfo[0XBC]; 2957 rtlhal->lna_type_5g = hwinfo[0XBF]; 2958 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) { 2959 rtlhal->pa_type_5g = 0; 2960 rtlhal->lna_type_5g = 0; 2961 } 2962 rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(1)) ? 1 : 0; 2963 rtlhal->external_lna_5g = (rtlhal->lna_type_5g & BIT(7)) ? 1 : 0; 2964 } else { 2965 rtlhal->external_pa_2g = 0; 2966 rtlhal->external_lna_2g = 0; 2967 rtlhal->external_pa_5g = 0; 2968 rtlhal->external_lna_5g = 0; 2969 } 2970} 2971 2972static void _rtl8821ae_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo, 2973 bool autoload_fail) 2974{ 2975 struct rtl_priv *rtlpriv = rtl_priv(hw); 2976 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2977 2978 if (!autoload_fail) { 2979 if (hwinfo[EEPROM_RFE_OPTION] & BIT(7)) { 2980 if (rtlhal->external_lna_5g) { 2981 if (rtlhal->external_pa_5g) { 2982 if (rtlhal->external_lna_2g && 2983 rtlhal->external_pa_2g) 2984 rtlhal->rfe_type = 3; 2985 else 2986 rtlhal->rfe_type = 0; 2987 } else { 2988 rtlhal->rfe_type = 2; 2989 } 2990 } else { 2991 rtlhal->rfe_type = 4; 2992 } 2993 } else { 2994 rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION] & 0x3F; 2995 2996 if (rtlhal->rfe_type == 4 && 2997 (rtlhal->external_pa_5g || 2998 rtlhal->external_pa_2g || 2999 rtlhal->external_lna_5g || 3000 rtlhal->external_lna_2g)) { 3001 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 3002 rtlhal->rfe_type = 2; 3003 } 3004 } 3005 } else { 3006 rtlhal->rfe_type = 0x04; 3007 } 3008 3009 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 3010 "RFE Type: 0x%2x\n", rtlhal->rfe_type); 3011} 3012 3013static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 3014 bool auto_load_fail, u8 *hwinfo) 3015{ 3016 struct rtl_priv *rtlpriv = rtl_priv(hw); 3017 u8 value; 3018 3019 if (!auto_load_fail) { 3020 value = *(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION]; 3021 if (((value & 0xe0) >> 5) == 0x1) 3022 rtlpriv->btcoexist.btc_info.btcoexist = 1; 3023 else 3024 rtlpriv->btcoexist.btc_info.btcoexist = 0; 3025 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A; 3026 3027 value = hwinfo[EEPROM_RF_BT_SETTING]; 3028 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1); 3029 } else { 3030 rtlpriv->btcoexist.btc_info.btcoexist = 0; 3031 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A; 3032 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2; 3033 } 3034 /*move BT_InitHalVars() to init_sw_vars*/ 3035} 3036 3037static void _rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 3038 bool auto_load_fail, u8 *hwinfo) 3039{ 3040 struct rtl_priv *rtlpriv = rtl_priv(hw); 3041 u8 value; 3042 u32 tmpu_32; 3043 3044 if (!auto_load_fail) { 3045 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); 3046 if (tmpu_32 & BIT(18)) 3047 rtlpriv->btcoexist.btc_info.btcoexist = 1; 3048 else 3049 rtlpriv->btcoexist.btc_info.btcoexist = 0; 3050 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A; 3051 3052 value = hwinfo[EEPROM_RF_BT_SETTING]; 3053 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1); 3054 } else { 3055 rtlpriv->btcoexist.btc_info.btcoexist = 0; 3056 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A; 3057 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2; 3058 } 3059 /*move BT_InitHalVars() to init_sw_vars*/ 3060} 3061 3062static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test) 3063{ 3064 struct rtl_priv *rtlpriv = rtl_priv(hw); 3065 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 3066 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3067 static const int params[] = { 3068 RTL_EEPROM_ID, EEPROM_VID, EEPROM_DID, 3069 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 3070 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 3071 COUNTRY_CODE_WORLD_WIDE_13 3072 }; 3073 u8 *hwinfo; 3074 3075 if (b_pseudo_test) { 3076 ;/* need add */ 3077 } 3078 3079 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 3080 if (!hwinfo) 3081 return; 3082 3083 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 3084 goto exit; 3085 3086 _rtl8821ae_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag, 3087 hwinfo); 3088 3089 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 3090 _rtl8812ae_read_amplifier_type(hw, hwinfo, 3091 rtlefuse->autoload_failflag); 3092 _rtl8812ae_read_bt_coexist_info_from_hwpg(hw, 3093 rtlefuse->autoload_failflag, hwinfo); 3094 } else { 3095 _rtl8821ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag); 3096 _rtl8821ae_read_bt_coexist_info_from_hwpg(hw, 3097 rtlefuse->autoload_failflag, hwinfo); 3098 } 3099 3100 _rtl8821ae_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag); 3101 /*board type*/ 3102 rtlefuse->board_type = ODM_BOARD_DEFAULT; 3103 if (rtlhal->external_lna_2g != 0) 3104 rtlefuse->board_type |= ODM_BOARD_EXT_LNA; 3105 if (rtlhal->external_lna_5g != 0) 3106 rtlefuse->board_type |= ODM_BOARD_EXT_LNA_5G; 3107 if (rtlhal->external_pa_2g != 0) 3108 rtlefuse->board_type |= ODM_BOARD_EXT_PA; 3109 if (rtlhal->external_pa_5g != 0) 3110 rtlefuse->board_type |= ODM_BOARD_EXT_PA_5G; 3111 3112 if (rtlpriv->btcoexist.btc_info.btcoexist == 1) 3113 rtlefuse->board_type |= ODM_BOARD_BT; 3114 3115 rtlhal->board_type = rtlefuse->board_type; 3116 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 3117 "board_type = 0x%x\n", rtlefuse->board_type); 3118 3119 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN]; 3120 if (rtlefuse->eeprom_channelplan == 0xff) 3121 rtlefuse->eeprom_channelplan = 0x7F; 3122 3123 /* set channel plan from efuse */ 3124 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan; 3125 3126 /*parse xtal*/ 3127 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE]; 3128 if (rtlefuse->crystalcap == 0xFF) 3129 rtlefuse->crystalcap = 0x20; 3130 3131 rtlefuse->eeprom_thermalmeter = *(u8 *)&hwinfo[EEPROM_THERMAL_METER]; 3132 if ((rtlefuse->eeprom_thermalmeter == 0xff) || 3133 rtlefuse->autoload_failflag) { 3134 rtlefuse->apk_thermalmeterignore = true; 3135 rtlefuse->eeprom_thermalmeter = 0xff; 3136 } 3137 3138 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 3139 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 3140 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 3141 3142 if (!rtlefuse->autoload_failflag) { 3143 rtlefuse->antenna_div_cfg = 3144 (hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18) >> 3; 3145 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff) 3146 rtlefuse->antenna_div_cfg = 0; 3147 3148 if (rtlpriv->btcoexist.btc_info.btcoexist == 1 && 3149 rtlpriv->btcoexist.btc_info.ant_num == ANT_X1) 3150 rtlefuse->antenna_div_cfg = 0; 3151 3152 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E]; 3153 if (rtlefuse->antenna_div_type == 0xff) 3154 rtlefuse->antenna_div_type = FIXED_HW_ANTDIV; 3155 } else { 3156 rtlefuse->antenna_div_cfg = 0; 3157 rtlefuse->antenna_div_type = 0; 3158 } 3159 3160 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 3161 "SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n", 3162 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type); 3163 3164 rtlpriv->ledctl.led_opendrain = true; 3165 3166 if (rtlhal->oem_id == RT_CID_DEFAULT) { 3167 switch (rtlefuse->eeprom_oemid) { 3168 case RT_CID_DEFAULT: 3169 break; 3170 case EEPROM_CID_TOSHIBA: 3171 rtlhal->oem_id = RT_CID_TOSHIBA; 3172 break; 3173 case EEPROM_CID_CCX: 3174 rtlhal->oem_id = RT_CID_CCX; 3175 break; 3176 case EEPROM_CID_QMI: 3177 rtlhal->oem_id = RT_CID_819X_QMI; 3178 break; 3179 case EEPROM_CID_WHQL: 3180 break; 3181 default: 3182 break; 3183 } 3184 } 3185exit: 3186 kfree(hwinfo); 3187} 3188 3189/*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw) 3190{ 3191 struct rtl_priv *rtlpriv = rtl_priv(hw); 3192 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 3193 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3194 3195 rtlpriv->ledctl.led_opendrain = true; 3196 switch (rtlhal->oem_id) { 3197 case RT_CID_819X_HP: 3198 rtlpriv->ledctl.led_opendrain = true; 3199 break; 3200 case RT_CID_819X_LENOVO: 3201 case RT_CID_DEFAULT: 3202 case RT_CID_TOSHIBA: 3203 case RT_CID_CCX: 3204 case RT_CID_819X_ACER: 3205 case RT_CID_WHQL: 3206 default: 3207 break; 3208 } 3209 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 3210 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); 3211}*/ 3212 3213void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw) 3214{ 3215 struct rtl_priv *rtlpriv = rtl_priv(hw); 3216 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 3217 struct rtl_phy *rtlphy = &rtlpriv->phy; 3218 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3219 u8 tmp_u1b; 3220 3221 rtlhal->version = _rtl8821ae_read_chip_version(hw); 3222 if (get_rf_type(rtlphy) == RF_1T1R) 3223 rtlpriv->dm.rfpath_rxenable[0] = true; 3224 else 3225 rtlpriv->dm.rfpath_rxenable[0] = 3226 rtlpriv->dm.rfpath_rxenable[1] = true; 3227 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 3228 rtlhal->version); 3229 3230 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 3231 if (tmp_u1b & BIT(4)) { 3232 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 3233 rtlefuse->epromtype = EEPROM_93C46; 3234 } else { 3235 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 3236 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 3237 } 3238 3239 if (tmp_u1b & BIT(5)) { 3240 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 3241 rtlefuse->autoload_failflag = false; 3242 _rtl8821ae_read_adapter_info(hw, false); 3243 } else { 3244 pr_err("Autoload ERR!!\n"); 3245 } 3246 /*hal_ReadRFType_8812A()*/ 3247 /* _rtl8821ae_hal_customized_behavior(hw); */ 3248} 3249 3250static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw, 3251 struct ieee80211_sta *sta) 3252{ 3253 struct rtl_priv *rtlpriv = rtl_priv(hw); 3254 struct rtl_phy *rtlphy = &rtlpriv->phy; 3255 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3256 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3257 u32 ratr_value; 3258 u8 ratr_index = 0; 3259 u8 b_nmode = mac->ht_enable; 3260 u8 mimo_ps = IEEE80211_SMPS_OFF; 3261 u16 shortgi_rate; 3262 u32 tmp_ratr_value; 3263 u8 curtxbw_40mhz = mac->bw_40; 3264 u8 b_curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 3265 1 : 0; 3266 u8 b_curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 3267 1 : 0; 3268 enum wireless_mode wirelessmode = mac->mode; 3269 3270 if (rtlhal->current_bandtype == BAND_ON_5G) 3271 ratr_value = sta->deflink.supp_rates[1] << 4; 3272 else 3273 ratr_value = sta->deflink.supp_rates[0]; 3274 if (mac->opmode == NL80211_IFTYPE_ADHOC) 3275 ratr_value = 0xfff; 3276 ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | 3277 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 3278 switch (wirelessmode) { 3279 case WIRELESS_MODE_B: 3280 if (ratr_value & 0x0000000c) 3281 ratr_value &= 0x0000000d; 3282 else 3283 ratr_value &= 0x0000000f; 3284 break; 3285 case WIRELESS_MODE_G: 3286 ratr_value &= 0x00000FF5; 3287 break; 3288 case WIRELESS_MODE_N_24G: 3289 case WIRELESS_MODE_N_5G: 3290 b_nmode = 1; 3291 if (mimo_ps == IEEE80211_SMPS_STATIC) { 3292 ratr_value &= 0x0007F005; 3293 } else { 3294 u32 ratr_mask; 3295 3296 if (get_rf_type(rtlphy) == RF_1T2R || 3297 get_rf_type(rtlphy) == RF_1T1R) 3298 ratr_mask = 0x000ff005; 3299 else 3300 ratr_mask = 0x0f0ff005; 3301 3302 ratr_value &= ratr_mask; 3303 } 3304 break; 3305 default: 3306 if (rtlphy->rf_type == RF_1T2R) 3307 ratr_value &= 0x000ff0ff; 3308 else 3309 ratr_value &= 0x0f0ff0ff; 3310 3311 break; 3312 } 3313 3314 if ((rtlpriv->btcoexist.bt_coexistence) && 3315 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) && 3316 (rtlpriv->btcoexist.bt_cur_state) && 3317 (rtlpriv->btcoexist.bt_ant_isolation) && 3318 ((rtlpriv->btcoexist.bt_service == BT_SCO) || 3319 (rtlpriv->btcoexist.bt_service == BT_BUSY))) 3320 ratr_value &= 0x0fffcfc0; 3321 else 3322 ratr_value &= 0x0FFFFFFF; 3323 3324 if (b_nmode && ((curtxbw_40mhz && 3325 b_curshortgi_40mhz) || (!curtxbw_40mhz && 3326 b_curshortgi_20mhz))) { 3327 ratr_value |= 0x10000000; 3328 tmp_ratr_value = (ratr_value >> 12); 3329 3330 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 3331 if ((1 << shortgi_rate) & tmp_ratr_value) 3332 break; 3333 } 3334 3335 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 3336 (shortgi_rate << 4) | (shortgi_rate); 3337 } 3338 3339 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 3340 3341 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, 3342 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)); 3343} 3344 3345static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate) 3346{ 3347 u8 i, j, tmp_rate; 3348 u32 rate_bitmap = 0; 3349 3350 for (i = j = 0; i < 4; i += 2, j += 10) { 3351 tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3; 3352 3353 switch (tmp_rate) { 3354 case 2: 3355 rate_bitmap = rate_bitmap | (0x03ff << j); 3356 break; 3357 case 1: 3358 rate_bitmap = rate_bitmap | (0x01ff << j); 3359 break; 3360 case 0: 3361 rate_bitmap = rate_bitmap | (0x00ff << j); 3362 break; 3363 default: 3364 break; 3365 } 3366 } 3367 3368 return rate_bitmap; 3369} 3370 3371static u32 _rtl8821ae_set_ra_vht_ratr_bitmap(struct ieee80211_hw *hw, 3372 enum wireless_mode wirelessmode, 3373 u32 ratr_bitmap) 3374{ 3375 struct rtl_priv *rtlpriv = rtl_priv(hw); 3376 struct rtl_phy *rtlphy = &rtlpriv->phy; 3377 u32 ret_bitmap = ratr_bitmap; 3378 3379 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40 3380 || rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) 3381 ret_bitmap = ratr_bitmap; 3382 else if (wirelessmode == WIRELESS_MODE_AC_5G 3383 || wirelessmode == WIRELESS_MODE_AC_24G) { 3384 if (rtlphy->rf_type == RF_1T1R) 3385 ret_bitmap = ratr_bitmap & (~BIT21); 3386 else 3387 ret_bitmap = ratr_bitmap & (~(BIT31|BIT21)); 3388 } 3389 3390 return ret_bitmap; 3391} 3392 3393static u8 _rtl8821ae_get_vht_eni(enum wireless_mode wirelessmode, 3394 u32 ratr_bitmap) 3395{ 3396 u8 ret = 0; 3397 if (wirelessmode < WIRELESS_MODE_N_24G) 3398 ret = 0; 3399 else if (wirelessmode == WIRELESS_MODE_AC_24G) { 3400 if (ratr_bitmap & 0xfff00000) /* Mix , 2SS */ 3401 ret = 3; 3402 else /* Mix, 1SS */ 3403 ret = 2; 3404 } else if (wirelessmode == WIRELESS_MODE_AC_5G) { 3405 ret = 1; 3406 } /* VHT */ 3407 3408 return ret << 4; 3409} 3410 3411static u8 _rtl8821ae_get_ra_ldpc(struct ieee80211_hw *hw, 3412 u8 mac_id, struct rtl_sta_info *sta_entry, 3413 enum wireless_mode wirelessmode) 3414{ 3415 u8 b_ldpc = 0; 3416 /*not support ldpc, do not open*/ 3417 return b_ldpc << 2; 3418} 3419 3420static u8 _rtl8821ae_get_ra_rftype(struct ieee80211_hw *hw, 3421 enum wireless_mode wirelessmode, 3422 u32 ratr_bitmap) 3423{ 3424 struct rtl_priv *rtlpriv = rtl_priv(hw); 3425 struct rtl_phy *rtlphy = &rtlpriv->phy; 3426 u8 rf_type = RF_1T1R; 3427 3428 if (rtlphy->rf_type == RF_1T1R) 3429 rf_type = RF_1T1R; 3430 else if (wirelessmode == WIRELESS_MODE_AC_5G 3431 || wirelessmode == WIRELESS_MODE_AC_24G 3432 || wirelessmode == WIRELESS_MODE_AC_ONLY) { 3433 if (ratr_bitmap & 0xffc00000) 3434 rf_type = RF_2T2R; 3435 } else if (wirelessmode == WIRELESS_MODE_N_5G 3436 || wirelessmode == WIRELESS_MODE_N_24G) { 3437 if (ratr_bitmap & 0xfff00000) 3438 rf_type = RF_2T2R; 3439 } 3440 3441 return rf_type; 3442} 3443 3444static bool _rtl8821ae_get_ra_shortgi(struct ieee80211_hw *hw, struct ieee80211_sta *sta, 3445 u8 mac_id) 3446{ 3447 bool b_short_gi = false; 3448 u8 b_curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 3449 1 : 0; 3450 u8 b_curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 3451 1 : 0; 3452 u8 b_curshortgi_80mhz = 0; 3453 b_curshortgi_80mhz = (sta->deflink.vht_cap.cap & 3454 IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0; 3455 3456 if (mac_id == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST) 3457 b_short_gi = false; 3458 3459 if (b_curshortgi_40mhz || b_curshortgi_80mhz 3460 || b_curshortgi_20mhz) 3461 b_short_gi = true; 3462 3463 return b_short_gi; 3464} 3465 3466static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw, 3467 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw) 3468{ 3469 struct rtl_priv *rtlpriv = rtl_priv(hw); 3470 struct rtl_phy *rtlphy = &rtlpriv->phy; 3471 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3472 struct rtl_sta_info *sta_entry = NULL; 3473 u32 ratr_bitmap; 3474 u8 ratr_index; 3475 enum wireless_mode wirelessmode = 0; 3476 u8 curtxbw_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) 3477 ? 1 : 0; 3478 bool b_shortgi = false; 3479 u8 rate_mask[7]; 3480 u8 macid = 0; 3481 u8 mimo_ps = IEEE80211_SMPS_OFF; 3482 u8 rf_type; 3483 3484 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 3485 wirelessmode = sta_entry->wireless_mode; 3486 3487 rtl_dbg(rtlpriv, COMP_RATR, DBG_LOUD, 3488 "wireless mode = 0x%x\n", wirelessmode); 3489 if (mac->opmode == NL80211_IFTYPE_STATION || 3490 mac->opmode == NL80211_IFTYPE_MESH_POINT) { 3491 curtxbw_40mhz = mac->bw_40; 3492 } else if (mac->opmode == NL80211_IFTYPE_AP || 3493 mac->opmode == NL80211_IFTYPE_ADHOC) 3494 macid = sta->aid + 1; 3495 if (wirelessmode == WIRELESS_MODE_N_5G || 3496 wirelessmode == WIRELESS_MODE_AC_5G || 3497 wirelessmode == WIRELESS_MODE_A) 3498 ratr_bitmap = sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 3499 else 3500 ratr_bitmap = sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 3501 3502 if (mac->opmode == NL80211_IFTYPE_ADHOC) 3503 ratr_bitmap = 0xfff; 3504 3505 if (wirelessmode == WIRELESS_MODE_N_24G 3506 || wirelessmode == WIRELESS_MODE_N_5G) 3507 ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | 3508 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 3509 else if (wirelessmode == WIRELESS_MODE_AC_24G 3510 || wirelessmode == WIRELESS_MODE_AC_5G 3511 || wirelessmode == WIRELESS_MODE_AC_ONLY) 3512 ratr_bitmap |= _rtl8821ae_rate_to_bitmap_2ssvht( 3513 sta->deflink.vht_cap.vht_mcs.rx_mcs_map) << 12; 3514 3515 b_shortgi = _rtl8821ae_get_ra_shortgi(hw, sta, macid); 3516 rf_type = _rtl8821ae_get_ra_rftype(hw, wirelessmode, ratr_bitmap); 3517 3518/*mac id owner*/ 3519 switch (wirelessmode) { 3520 case WIRELESS_MODE_B: 3521 ratr_index = RATR_INX_WIRELESS_B; 3522 if (ratr_bitmap & 0x0000000c) 3523 ratr_bitmap &= 0x0000000d; 3524 else 3525 ratr_bitmap &= 0x0000000f; 3526 break; 3527 case WIRELESS_MODE_G: 3528 ratr_index = RATR_INX_WIRELESS_GB; 3529 3530 if (rssi_level == 1) 3531 ratr_bitmap &= 0x00000f00; 3532 else if (rssi_level == 2) 3533 ratr_bitmap &= 0x00000ff0; 3534 else 3535 ratr_bitmap &= 0x00000ff5; 3536 break; 3537 case WIRELESS_MODE_A: 3538 ratr_index = RATR_INX_WIRELESS_G; 3539 ratr_bitmap &= 0x00000ff0; 3540 break; 3541 case WIRELESS_MODE_N_24G: 3542 case WIRELESS_MODE_N_5G: 3543 if (wirelessmode == WIRELESS_MODE_N_24G) 3544 ratr_index = RATR_INX_WIRELESS_NGB; 3545 else 3546 ratr_index = RATR_INX_WIRELESS_NG; 3547 3548 if (mimo_ps == IEEE80211_SMPS_STATIC 3549 || mimo_ps == IEEE80211_SMPS_DYNAMIC) { 3550 if (rssi_level == 1) 3551 ratr_bitmap &= 0x000f0000; 3552 else if (rssi_level == 2) 3553 ratr_bitmap &= 0x000ff000; 3554 else 3555 ratr_bitmap &= 0x000ff005; 3556 } else { 3557 if (rf_type == RF_1T1R) { 3558 if (curtxbw_40mhz) { 3559 if (rssi_level == 1) 3560 ratr_bitmap &= 0x000f0000; 3561 else if (rssi_level == 2) 3562 ratr_bitmap &= 0x000ff000; 3563 else 3564 ratr_bitmap &= 0x000ff015; 3565 } else { 3566 if (rssi_level == 1) 3567 ratr_bitmap &= 0x000f0000; 3568 else if (rssi_level == 2) 3569 ratr_bitmap &= 0x000ff000; 3570 else 3571 ratr_bitmap &= 0x000ff005; 3572 } 3573 } else { 3574 if (curtxbw_40mhz) { 3575 if (rssi_level == 1) 3576 ratr_bitmap &= 0x0fff0000; 3577 else if (rssi_level == 2) 3578 ratr_bitmap &= 0x0ffff000; 3579 else 3580 ratr_bitmap &= 0x0ffff015; 3581 } else { 3582 if (rssi_level == 1) 3583 ratr_bitmap &= 0x0fff0000; 3584 else if (rssi_level == 2) 3585 ratr_bitmap &= 0x0ffff000; 3586 else 3587 ratr_bitmap &= 0x0ffff005; 3588 } 3589 } 3590 } 3591 break; 3592 3593 case WIRELESS_MODE_AC_24G: 3594 ratr_index = RATR_INX_WIRELESS_AC_24N; 3595 if (rssi_level == 1) 3596 ratr_bitmap &= 0xfc3f0000; 3597 else if (rssi_level == 2) 3598 ratr_bitmap &= 0xfffff000; 3599 else 3600 ratr_bitmap &= 0xffffffff; 3601 break; 3602 3603 case WIRELESS_MODE_AC_5G: 3604 ratr_index = RATR_INX_WIRELESS_AC_5N; 3605 3606 if (rf_type == RF_1T1R) { 3607 if (rssi_level == 1) /*add by Gary for ac-series*/ 3608 ratr_bitmap &= 0x003f8000; 3609 else if (rssi_level == 2) 3610 ratr_bitmap &= 0x003ff000; 3611 else 3612 ratr_bitmap &= 0x003ff010; 3613 } else { 3614 if (rssi_level == 1) 3615 ratr_bitmap &= 0xfe3f8000; 3616 else if (rssi_level == 2) 3617 ratr_bitmap &= 0xfffff000; 3618 else 3619 ratr_bitmap &= 0xfffff010; 3620 } 3621 break; 3622 3623 default: 3624 ratr_index = RATR_INX_WIRELESS_NGB; 3625 3626 if (rf_type == RF_1T2R) 3627 ratr_bitmap &= 0x000ff0ff; 3628 else 3629 ratr_bitmap &= 0x0f8ff0ff; 3630 break; 3631 } 3632 3633 ratr_index = rtl_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode); 3634 sta_entry->ratr_index = ratr_index; 3635 ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode, 3636 ratr_bitmap); 3637 3638 rtl_dbg(rtlpriv, COMP_RATR, DBG_LOUD, 3639 "ratr_bitmap :%x\n", ratr_bitmap); 3640 3641 /* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) | 3642 (ratr_index << 28)); */ 3643 3644 rate_mask[0] = macid; 3645 rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00); 3646 rate_mask[2] = rtlphy->current_chan_bw | ((!update_bw) << 3) 3647 | _rtl8821ae_get_vht_eni(wirelessmode, ratr_bitmap) 3648 | _rtl8821ae_get_ra_ldpc(hw, macid, sta_entry, wirelessmode); 3649 3650 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff); 3651 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8); 3652 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16); 3653 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24); 3654 3655 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, 3656 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n", 3657 ratr_index, ratr_bitmap, 3658 rate_mask[0], rate_mask[1], 3659 rate_mask[2], rate_mask[3], 3660 rate_mask[4], rate_mask[5], 3661 rate_mask[6]); 3662 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask); 3663 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0); 3664} 3665 3666void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw, 3667 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw) 3668{ 3669 struct rtl_priv *rtlpriv = rtl_priv(hw); 3670 if (rtlpriv->dm.useramask) 3671 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level, update_bw); 3672 else 3673 /*rtl_dbg(rtlpriv, COMP_RATR,DBG_LOUD, 3674 "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only\n");*/ 3675 rtl8821ae_update_hal_rate_table(hw, sta); 3676} 3677 3678void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw) 3679{ 3680 struct rtl_priv *rtlpriv = rtl_priv(hw); 3681 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3682 u16 wireless_mode = mac->mode; 3683 u8 sifs_timer, r2t_sifs; 3684 3685 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 3686 (u8 *)&mac->slot_time); 3687 if (wireless_mode == WIRELESS_MODE_G) 3688 sifs_timer = 0x0a; 3689 else 3690 sifs_timer = 0x0e; 3691 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 3692 3693 r2t_sifs = 0xa; 3694 3695 if (wireless_mode == WIRELESS_MODE_AC_5G && 3696 (mac->vht_ldpc_cap & LDPC_VHT_ENABLE_RX) && 3697 (mac->vht_stbc_cap & STBC_VHT_ENABLE_RX)) { 3698 if (mac->vendor == PEER_ATH) 3699 r2t_sifs = 0x8; 3700 else 3701 r2t_sifs = 0xa; 3702 } else if (wireless_mode == WIRELESS_MODE_AC_5G) { 3703 r2t_sifs = 0xa; 3704 } 3705 3706 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_R2T_SIFS, (u8 *)&r2t_sifs); 3707} 3708 3709bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 3710{ 3711 struct rtl_priv *rtlpriv = rtl_priv(hw); 3712 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 3713 struct rtl_phy *rtlphy = &rtlpriv->phy; 3714 enum rf_pwrstate e_rfpowerstate_toset; 3715 u8 u1tmp = 0; 3716 bool b_actuallyset = false; 3717 3718 if (rtlpriv->rtlhal.being_init_adapter) 3719 return false; 3720 3721 if (ppsc->swrf_processing) 3722 return false; 3723 3724 spin_lock(&rtlpriv->locks.rf_ps_lock); 3725 if (ppsc->rfchange_inprogress) { 3726 spin_unlock(&rtlpriv->locks.rf_ps_lock); 3727 return false; 3728 } else { 3729 ppsc->rfchange_inprogress = true; 3730 spin_unlock(&rtlpriv->locks.rf_ps_lock); 3731 } 3732 3733 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2, 3734 rtl_read_byte(rtlpriv, 3735 REG_GPIO_IO_SEL_2) & ~(BIT(1))); 3736 3737 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2); 3738 3739 if (rtlphy->polarity_ctl) 3740 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON; 3741 else 3742 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF; 3743 3744 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) { 3745 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 3746 "GPIOChangeRF - HW Radio ON, RF ON\n"); 3747 3748 e_rfpowerstate_toset = ERFON; 3749 ppsc->hwradiooff = false; 3750 b_actuallyset = true; 3751 } else if ((!ppsc->hwradiooff) 3752 && (e_rfpowerstate_toset == ERFOFF)) { 3753 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 3754 "GPIOChangeRF - HW Radio OFF, RF OFF\n"); 3755 3756 e_rfpowerstate_toset = ERFOFF; 3757 ppsc->hwradiooff = true; 3758 b_actuallyset = true; 3759 } 3760 3761 if (b_actuallyset) { 3762 spin_lock(&rtlpriv->locks.rf_ps_lock); 3763 ppsc->rfchange_inprogress = false; 3764 spin_unlock(&rtlpriv->locks.rf_ps_lock); 3765 } else { 3766 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) 3767 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 3768 3769 spin_lock(&rtlpriv->locks.rf_ps_lock); 3770 ppsc->rfchange_inprogress = false; 3771 spin_unlock(&rtlpriv->locks.rf_ps_lock); 3772 } 3773 3774 *valid = 1; 3775 return !ppsc->hwradiooff; 3776} 3777 3778void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index, 3779 u8 *p_macaddr, bool is_group, u8 enc_algo, 3780 bool is_wepkey, bool clear_all) 3781{ 3782 struct rtl_priv *rtlpriv = rtl_priv(hw); 3783 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3784 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 3785 u8 *macaddr = p_macaddr; 3786 u32 entry_id = 0; 3787 bool is_pairwise = false; 3788 3789 static u8 cam_const_addr[4][6] = { 3790 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 3791 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 3792 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 3793 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 3794 }; 3795 static u8 cam_const_broad[] = { 3796 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 3797 }; 3798 3799 if (clear_all) { 3800 u8 idx = 0; 3801 u8 cam_offset = 0; 3802 u8 clear_number = 5; 3803 3804 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 3805 3806 for (idx = 0; idx < clear_number; idx++) { 3807 rtl_cam_mark_invalid(hw, cam_offset + idx); 3808 rtl_cam_empty_entry(hw, cam_offset + idx); 3809 3810 if (idx < 5) { 3811 memset(rtlpriv->sec.key_buf[idx], 0, 3812 MAX_KEY_LEN); 3813 rtlpriv->sec.key_len[idx] = 0; 3814 } 3815 } 3816 } else { 3817 switch (enc_algo) { 3818 case WEP40_ENCRYPTION: 3819 enc_algo = CAM_WEP40; 3820 break; 3821 case WEP104_ENCRYPTION: 3822 enc_algo = CAM_WEP104; 3823 break; 3824 case TKIP_ENCRYPTION: 3825 enc_algo = CAM_TKIP; 3826 break; 3827 case AESCCMP_ENCRYPTION: 3828 enc_algo = CAM_AES; 3829 break; 3830 default: 3831 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 3832 "switch case %#x not processed\n", enc_algo); 3833 enc_algo = CAM_TKIP; 3834 break; 3835 } 3836 3837 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 3838 macaddr = cam_const_addr[key_index]; 3839 entry_id = key_index; 3840 } else { 3841 if (is_group) { 3842 macaddr = cam_const_broad; 3843 entry_id = key_index; 3844 } else { 3845 if (mac->opmode == NL80211_IFTYPE_AP) { 3846 entry_id = rtl_cam_get_free_entry(hw, p_macaddr); 3847 if (entry_id >= TOTAL_CAM_ENTRY) { 3848 pr_err("an not find free hwsecurity cam entry\n"); 3849 return; 3850 } 3851 } else { 3852 entry_id = CAM_PAIRWISE_KEY_POSITION; 3853 } 3854 3855 key_index = PAIRWISE_KEYIDX; 3856 is_pairwise = true; 3857 } 3858 } 3859 3860 if (rtlpriv->sec.key_len[key_index] == 0) { 3861 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 3862 "delete one entry, entry_id is %d\n", 3863 entry_id); 3864 if (mac->opmode == NL80211_IFTYPE_AP) 3865 rtl_cam_del_entry(hw, p_macaddr); 3866 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 3867 } else { 3868 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 3869 "add one entry\n"); 3870 if (is_pairwise) { 3871 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 3872 "set Pairwise key\n"); 3873 3874 rtl_cam_add_one_entry(hw, macaddr, key_index, 3875 entry_id, enc_algo, 3876 CAM_CONFIG_NO_USEDK, 3877 rtlpriv->sec.key_buf[key_index]); 3878 } else { 3879 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 3880 "set group key\n"); 3881 3882 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 3883 rtl_cam_add_one_entry(hw, 3884 rtlefuse->dev_addr, 3885 PAIRWISE_KEYIDX, 3886 CAM_PAIRWISE_KEY_POSITION, 3887 enc_algo, 3888 CAM_CONFIG_NO_USEDK, 3889 rtlpriv->sec.key_buf 3890 [entry_id]); 3891 } 3892 3893 rtl_cam_add_one_entry(hw, macaddr, key_index, 3894 entry_id, enc_algo, 3895 CAM_CONFIG_NO_USEDK, 3896 rtlpriv->sec.key_buf[entry_id]); 3897 } 3898 } 3899 } 3900} 3901 3902void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw) 3903{ 3904 struct rtl_priv *rtlpriv = rtl_priv(hw); 3905 3906 /* 0:Low, 1:High, 2:From Efuse. */ 3907 rtlpriv->btcoexist.reg_bt_iso = 2; 3908 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ 3909 rtlpriv->btcoexist.reg_bt_sco = 3; 3910 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ 3911 rtlpriv->btcoexist.reg_bt_sco = 0; 3912} 3913 3914void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw) 3915{ 3916 struct rtl_priv *rtlpriv = rtl_priv(hw); 3917 3918 if (rtlpriv->cfg->ops->get_btc_status()) 3919 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv); 3920} 3921 3922void rtl8821ae_suspend(struct ieee80211_hw *hw) 3923{ 3924} 3925 3926void rtl8821ae_resume(struct ieee80211_hw *hw) 3927{ 3928} 3929 3930/* Turn on AAP (RCR:bit 0) for promiscuous mode. */ 3931void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw, 3932 bool allow_all_da, bool write_into_reg) 3933{ 3934 struct rtl_priv *rtlpriv = rtl_priv(hw); 3935 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 3936 3937 if (allow_all_da) /* Set BIT0 */ 3938 rtlpci->receive_config |= RCR_AAP; 3939 else /* Clear BIT0 */ 3940 rtlpci->receive_config &= ~RCR_AAP; 3941 3942 if (write_into_reg) 3943 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 3944 3945 rtl_dbg(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD, 3946 "receive_config=0x%08X, write_into_reg=%d\n", 3947 rtlpci->receive_config, write_into_reg); 3948} 3949 3950/* WKFMCAMAddAllEntry8812 */ 3951void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw, 3952 struct rtl_wow_pattern *rtl_pattern, 3953 u8 index) 3954{ 3955 struct rtl_priv *rtlpriv = rtl_priv(hw); 3956 u32 cam = 0; 3957 u8 addr = 0; 3958 u16 rxbuf_addr; 3959 u8 tmp, count = 0; 3960 u16 cam_start; 3961 u16 offset; 3962 3963 /* Count the WFCAM entry start offset. */ 3964 3965 /* RX page size = 128 byte */ 3966 offset = MAX_RX_DMA_BUFFER_SIZE_8812 / 128; 3967 /* We should start from the boundary */ 3968 cam_start = offset * 128; 3969 3970 /* Enable Rx packet buffer access. */ 3971 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT); 3972 for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) { 3973 /* Set Rx packet buffer offset. 3974 * RXBufer pointer increases 1, 3975 * we can access 8 bytes in Rx packet buffer. 3976 * CAM start offset (unit: 1 byte) = index*WKFMCAM_SIZE 3977 * RXBufer addr = (CAM start offset + 3978 * per entry offset of a WKFM CAM)/8 3979 * * index: The index of the wake up frame mask 3980 * * WKFMCAM_SIZE: the total size of one WKFM CAM 3981 * * per entry offset of a WKFM CAM: Addr*4 bytes 3982 */ 3983 rxbuf_addr = (cam_start + index * WKFMCAM_SIZE + addr * 4) >> 3; 3984 /* Set R/W start offset */ 3985 rtl_write_word(rtlpriv, REG_PKTBUF_DBG_CTRL, rxbuf_addr); 3986 3987 if (addr == 0) { 3988 cam = BIT(31) | rtl_pattern->crc; 3989 3990 if (rtl_pattern->type == UNICAST_PATTERN) 3991 cam |= BIT(24); 3992 else if (rtl_pattern->type == MULTICAST_PATTERN) 3993 cam |= BIT(25); 3994 else if (rtl_pattern->type == BROADCAST_PATTERN) 3995 cam |= BIT(26); 3996 3997 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam); 3998 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, 3999 "WRITE entry[%d] 0x%x: %x\n", addr, 4000 REG_PKTBUF_DBG_DATA_L, cam); 4001 4002 /* Write to Rx packet buffer. */ 4003 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01); 4004 } else if (addr == 2 || addr == 4) {/* WKFM[127:0] */ 4005 cam = rtl_pattern->mask[addr - 2]; 4006 4007 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam); 4008 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, 4009 "WRITE entry[%d] 0x%x: %x\n", addr, 4010 REG_PKTBUF_DBG_DATA_L, cam); 4011 4012 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01); 4013 } else if (addr == 3 || addr == 5) {/* WKFM[127:0] */ 4014 cam = rtl_pattern->mask[addr - 2]; 4015 4016 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam); 4017 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, 4018 "WRITE entry[%d] 0x%x: %x\n", addr, 4019 REG_PKTBUF_DBG_DATA_H, cam); 4020 4021 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001); 4022 } 4023 4024 count = 0; 4025 do { 4026 tmp = rtl_read_byte(rtlpriv, REG_RXPKTBUF_CTRL); 4027 udelay(2); 4028 count++; 4029 } while (tmp && count < 100); 4030 4031 WARN_ONCE((count >= 100), 4032 "rtl8821ae: Write wake up frame mask FAIL %d value!\n", 4033 tmp); 4034 } 4035 /* Disable Rx packet buffer access. */ 4036 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, 4037 DISABLE_TRXPKT_BUF_ACCESS); 4038}
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