sw.c

  1// SPDX-License-Identifier: GPL-2.0
  2/* Copyright(c) 2009-2012  Realtek Corporation.*/
  3
  4#include "../wifi.h"
  5#include "../core.h"
  6#include "../pci.h"
  7#include "reg.h"
  8#include "def.h"
  9#include "phy.h"
 10#include "dm.h"
 11#include "fw.h"
 12#include "../rtl8723com/fw_common.h"
 13#include "hw.h"
 14#include "trx.h"
 15#include "led.h"
 16#include "table.h"
 17#include "hal_btc.h"
 18#include "../btcoexist/rtl_btc.h"
 19#include "../rtl8723com/phy_common.h"
 20
 21#include <linux/vmalloc.h>
 22#include <linux/module.h>
 23
 24static void rtl8723e_init_aspm_vars(struct ieee80211_hw *hw)
 25{
 26	struct rtl_priv *rtlpriv = rtl_priv(hw);
 27	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 28
 29	/**
 30	 * ASPM PS mode.
 31	 * 0 - Disable ASPM,
 32	 * 1 - Enable ASPM without Clock Req,
 33	 * 2 - Enable ASPM with Clock Req,
 34	 * 3 - Alwyas Enable ASPM with Clock Req,
 35	 * 4 - Always Enable ASPM without Clock Req.
 36	 * set default to RTL8192CE:3 RTL8192E:2
 37	 */
 38	rtlpci->const_pci_aspm = 3;
 39
 40	/*Setting for PCI-E device */
 41	rtlpci->const_devicepci_aspm_setting = 0x03;
 42
 43	/*Setting for PCI-E bridge */
 44	rtlpci->const_hostpci_aspm_setting = 0x02;
 45
 46	/**
 47	 * In Hw/Sw Radio Off situation.
 48	 * 0 - Default,
 49	 * 1 - From ASPM setting without low Mac Pwr,
 50	 * 2 - From ASPM setting with low Mac Pwr,
 51	 * 3 - Bus D3
 52	 * set default to RTL8192CE:0 RTL8192SE:2
 53	 */
 54	rtlpci->const_hwsw_rfoff_d3 = 0;
 55
 56	/**
 57	 * This setting works for those device with
 58	 * backdoor ASPM setting such as EPHY setting.
 59	 * 0 - Not support ASPM,
 60	 * 1 - Support ASPM,
 61	 * 2 - According to chipset.
 62	 */
 63	rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
 64}
 65
 66static int rtl8723e_init_sw_vars(struct ieee80211_hw *hw)
 67{
 68	struct rtl_priv *rtlpriv = rtl_priv(hw);
 69	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 70	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 71	int err = 0;
 72	char *fw_name = "rtlwifi/rtl8723fw.bin";
 73
 74	rtl8723e_bt_reg_init(hw);
 75
 76	rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
 77
 78	rtlpriv->dm.dm_initialgain_enable = true;
 79	rtlpriv->dm.dm_flag = 0;
 80	rtlpriv->dm.disable_framebursting = false;
 81	rtlpriv->dm.thermalvalue = 0;
 82	rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
 83
 84	/* compatible 5G band 88ce just 2.4G band & smsp */
 85	rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
 86	rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
 87	rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
 88
 89	rtlpci->receive_config = (RCR_APPFCS |
 90				  RCR_APP_MIC |
 91				  RCR_APP_ICV |
 92				  RCR_APP_PHYST_RXFF |
 93				  RCR_HTC_LOC_CTRL |
 94				  RCR_AMF |
 95				  RCR_ACF |
 96				  RCR_ADF |
 97				  RCR_AICV |
 98				  RCR_AB |
 99				  RCR_AM |
100				  RCR_APM |
101				  0);
102
103	rtlpci->irq_mask[0] =
104	    (u32) (PHIMR_ROK |
105		   PHIMR_RDU |
106		   PHIMR_VODOK |
107		   PHIMR_VIDOK |
108		   PHIMR_BEDOK |
109		   PHIMR_BKDOK |
110		   PHIMR_MGNTDOK |
111		   PHIMR_HIGHDOK |
112		   PHIMR_C2HCMD |
113		   PHIMR_HISRE_IND |
114		   PHIMR_TSF_BIT32_TOGGLE |
115		   PHIMR_TXBCNOK |
116		   PHIMR_PSTIMEOUT |
117		   0);
118
119	rtlpci->irq_mask[1]	=
120		 (u32)(PHIMR_RXFOVW |
121				0);
122
123	/* for LPS & IPS */
124	rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
125	rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
126	rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
127	rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
128	if (rtlpriv->cfg->mod_params->disable_watchdog)
129		pr_info("watchdog disabled\n");
130	rtlpriv->psc.reg_fwctrl_lps = 3;
131	rtlpriv->psc.reg_max_lps_awakeintvl = 5;
132	rtl8723e_init_aspm_vars(hw);
133
134	if (rtlpriv->psc.reg_fwctrl_lps == 1)
135		rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
136	else if (rtlpriv->psc.reg_fwctrl_lps == 2)
137		rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
138	else if (rtlpriv->psc.reg_fwctrl_lps == 3)
139		rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
140
141	/* for firmware buf */
142	rtlpriv->rtlhal.pfirmware = vzalloc(0x6000);
143	if (!rtlpriv->rtlhal.pfirmware) {
144		pr_err("Can't alloc buffer for fw.\n");
145		return 1;
146	}
147
148	if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version))
149		fw_name = "rtlwifi/rtl8723fw_B.bin";
150
151	rtlpriv->max_fw_size = 0x6000;
152	pr_info("Using firmware %s\n", fw_name);
153	err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
154				      rtlpriv->io.dev, GFP_KERNEL, hw,
155				      rtl_fw_cb);
156	if (err) {
157		pr_err("Failed to request firmware!\n");
158		vfree(rtlpriv->rtlhal.pfirmware);
159		rtlpriv->rtlhal.pfirmware = NULL;
160		return 1;
161	}
162	return 0;
163}
164
165static void rtl8723e_deinit_sw_vars(struct ieee80211_hw *hw)
166{
167	struct rtl_priv *rtlpriv = rtl_priv(hw);
168
169	if (rtlpriv->rtlhal.pfirmware) {
170		vfree(rtlpriv->rtlhal.pfirmware);
171		rtlpriv->rtlhal.pfirmware = NULL;
172	}
173}
174
175/* get bt coexist status */
176static bool rtl8723e_get_btc_status(void)
177{
178	return true;
179}
180
181static bool is_fw_header(struct rtlwifi_firmware_header *hdr)
182{
183	return (le16_to_cpu(hdr->signature) & 0xfff0) == 0x2300;
184}
185
186static const struct rtl_hal_ops rtl8723e_hal_ops = {
187	.init_sw_vars = rtl8723e_init_sw_vars,
188	.deinit_sw_vars = rtl8723e_deinit_sw_vars,
189	.read_eeprom_info = rtl8723e_read_eeprom_info,
190	.interrupt_recognized = rtl8723e_interrupt_recognized,
191	.hw_init = rtl8723e_hw_init,
192	.hw_disable = rtl8723e_card_disable,
193	.hw_suspend = rtl8723e_suspend,
194	.hw_resume = rtl8723e_resume,
195	.enable_interrupt = rtl8723e_enable_interrupt,
196	.disable_interrupt = rtl8723e_disable_interrupt,
197	.set_network_type = rtl8723e_set_network_type,
198	.set_chk_bssid = rtl8723e_set_check_bssid,
199	.set_qos = rtl8723e_set_qos,
200	.set_bcn_reg = rtl8723e_set_beacon_related_registers,
201	.set_bcn_intv = rtl8723e_set_beacon_interval,
202	.update_interrupt_mask = rtl8723e_update_interrupt_mask,
203	.get_hw_reg = rtl8723e_get_hw_reg,
204	.set_hw_reg = rtl8723e_set_hw_reg,
205	.update_rate_tbl = rtl8723e_update_hal_rate_tbl,
206	.fill_tx_desc = rtl8723e_tx_fill_desc,
207	.fill_tx_cmddesc = rtl8723e_tx_fill_cmddesc,
208	.query_rx_desc = rtl8723e_rx_query_desc,
209	.set_channel_access = rtl8723e_update_channel_access_setting,
210	.radio_onoff_checking = rtl8723e_gpio_radio_on_off_checking,
211	.set_bw_mode = rtl8723e_phy_set_bw_mode,
212	.switch_channel = rtl8723e_phy_sw_chnl,
213	.dm_watchdog = rtl8723e_dm_watchdog,
214	.scan_operation_backup = rtl8723e_phy_scan_operation_backup,
215	.set_rf_power_state = rtl8723e_phy_set_rf_power_state,
216	.led_control = rtl8723e_led_control,
217	.set_desc = rtl8723e_set_desc,
218	.get_desc = rtl8723e_get_desc,
219	.is_tx_desc_closed = rtl8723e_is_tx_desc_closed,
220	.tx_polling = rtl8723e_tx_polling,
221	.enable_hw_sec = rtl8723e_enable_hw_security_config,
222	.set_key = rtl8723e_set_key,
223	.get_bbreg = rtl8723_phy_query_bb_reg,
224	.set_bbreg = rtl8723_phy_set_bb_reg,
225	.get_rfreg = rtl8723e_phy_query_rf_reg,
226	.set_rfreg = rtl8723e_phy_set_rf_reg,
227	.c2h_command_handle = rtl_8723e_c2h_command_handle,
228	.bt_wifi_media_status_notify = rtl_8723e_bt_wifi_media_status_notify,
229	.bt_coex_off_before_lps =
230		rtl8723e_dm_bt_turn_off_bt_coexist_before_enter_lps,
231	.get_btc_status = rtl8723e_get_btc_status,
232	.is_fw_header = is_fw_header,
233};
234
235static struct rtl_mod_params rtl8723e_mod_params = {
236	.sw_crypto = false,
237	.inactiveps = true,
238	.swctrl_lps = true,
239	.fwctrl_lps = false,
240	.aspm_support = 1,
241	.debug_level = 0,
242	.debug_mask = 0,
243	.msi_support = false,
244	.disable_watchdog = false,
245};
246
247static const struct rtl_hal_cfg rtl8723e_hal_cfg = {
248	.bar_id = 2,
249	.write_readback = true,
250	.name = "rtl8723e_pci",
251	.ops = &rtl8723e_hal_ops,
252	.mod_params = &rtl8723e_mod_params,
253	.maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
254	.maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
255	.maps[SYS_CLK] = REG_SYS_CLKR,
256	.maps[MAC_RCR_AM] = AM,
257	.maps[MAC_RCR_AB] = AB,
258	.maps[MAC_RCR_ACRC32] = ACRC32,
259	.maps[MAC_RCR_ACF] = ACF,
260	.maps[MAC_RCR_AAP] = AAP,
261	.maps[MAC_HIMR] = REG_HIMR,
262	.maps[MAC_HIMRE] = REG_HIMRE,
263	.maps[EFUSE_TEST] = REG_EFUSE_TEST,
264	.maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
265	.maps[EFUSE_CLK] = 0,
266	.maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
267	.maps[EFUSE_PWC_EV12V] = PWC_EV12V,
268	.maps[EFUSE_FEN_ELDR] = FEN_ELDR,
269	.maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
270	.maps[EFUSE_ANA8M] = ANA8M,
271	.maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
272	.maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
273	.maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
274	.maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
275
276	.maps[RWCAM] = REG_CAMCMD,
277	.maps[WCAMI] = REG_CAMWRITE,
278	.maps[RCAMO] = REG_CAMREAD,
279	.maps[CAMDBG] = REG_CAMDBG,
280	.maps[SECR] = REG_SECCFG,
281	.maps[SEC_CAM_NONE] = CAM_NONE,
282	.maps[SEC_CAM_WEP40] = CAM_WEP40,
283	.maps[SEC_CAM_TKIP] = CAM_TKIP,
284	.maps[SEC_CAM_AES] = CAM_AES,
285	.maps[SEC_CAM_WEP104] = CAM_WEP104,
286
287	.maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
288	.maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
289	.maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
290	.maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
291	.maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
292	.maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
293	.maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
294	.maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
295	.maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
296	.maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
297	.maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
298	.maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
299	.maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
300	.maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
301	.maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
302	.maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
303
304	.maps[RTL_IMR_TXFOVW] = PHIMR_TXFOVW,
305	.maps[RTL_IMR_PSTIMEOUT] = PHIMR_PSTIMEOUT,
306	.maps[RTL_IMR_BCNINT] = PHIMR_BCNDMAINT0,
307	.maps[RTL_IMR_RXFOVW] = PHIMR_RXFOVW,
308	.maps[RTL_IMR_RDU] = PHIMR_RDU,
309	.maps[RTL_IMR_ATIMEND] = PHIMR_ATIMEND_E,
310	.maps[RTL_IMR_BDOK] = PHIMR_BCNDOK0,
311	.maps[RTL_IMR_MGNTDOK] = PHIMR_MGNTDOK,
312	.maps[RTL_IMR_TBDER] = PHIMR_TXBCNERR,
313	.maps[RTL_IMR_HIGHDOK] = PHIMR_HIGHDOK,
314	.maps[RTL_IMR_TBDOK] = PHIMR_TXBCNOK,
315	.maps[RTL_IMR_BKDOK] = PHIMR_BKDOK,
316	.maps[RTL_IMR_BEDOK] = PHIMR_BEDOK,
317	.maps[RTL_IMR_VIDOK] = PHIMR_VIDOK,
318	.maps[RTL_IMR_VODOK] = PHIMR_VODOK,
319	.maps[RTL_IMR_ROK] = PHIMR_ROK,
320	.maps[RTL_IBSS_INT_MASKS] =
321		(PHIMR_BCNDMAINT0 | PHIMR_TXBCNOK | PHIMR_TXBCNERR),
322	.maps[RTL_IMR_C2HCMD] = PHIMR_C2HCMD,
323
324
325	.maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
326	.maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
327	.maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
328	.maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
329	.maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
330	.maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
331	.maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
332	.maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
333	.maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
334	.maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
335	.maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
336	.maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
337
338	.maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
339	.maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
340};
341
342static const struct pci_device_id rtl8723e_pci_ids[] = {
343	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8723, rtl8723e_hal_cfg)},
344	{},
345};
346
347MODULE_DEVICE_TABLE(pci, rtl8723e_pci_ids);
348
349MODULE_AUTHOR("lizhaoming	<chaoming_li@realsil.com.cn>");
350MODULE_AUTHOR("Realtek WlanFAE	<wlanfae@realtek.com>");
351MODULE_LICENSE("GPL");
352MODULE_DESCRIPTION("Realtek 8723E 802.11n PCI wireless");
353MODULE_FIRMWARE("rtlwifi/rtl8723fw.bin");
354MODULE_FIRMWARE("rtlwifi/rtl8723fw_B.bin");
355
356module_param_named(swenc, rtl8723e_mod_params.sw_crypto, bool, 0444);
357module_param_named(debug_level, rtl8723e_mod_params.debug_level, int, 0644);
358module_param_named(debug_mask, rtl8723e_mod_params.debug_mask, ullong, 0644);
359module_param_named(ips, rtl8723e_mod_params.inactiveps, bool, 0444);
360module_param_named(swlps, rtl8723e_mod_params.swctrl_lps, bool, 0444);
361module_param_named(fwlps, rtl8723e_mod_params.fwctrl_lps, bool, 0444);
362module_param_named(msi, rtl8723e_mod_params.msi_support, bool, 0444);
363module_param_named(aspm, rtl8723e_mod_params.aspm_support, int, 0444);
364module_param_named(disable_watchdog, rtl8723e_mod_params.disable_watchdog,
365		   bool, 0444);
366MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
367MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
368MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 1)\n");
369MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 0)\n");
370MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 0)\n");
371MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
372MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
373MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
374MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
375
376static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
377
378static struct pci_driver rtl8723e_driver = {
379	.name = KBUILD_MODNAME,
380	.id_table = rtl8723e_pci_ids,
381	.probe = rtl_pci_probe,
382	.remove = rtl_pci_disconnect,
383	.driver.pm = &rtlwifi_pm_ops,
384};
385
386module_pci_driver(rtl8723e_driver);