hw.c

   1// SPDX-License-Identifier: GPL-2.0
   2/* Copyright(c) 2009-2012  Realtek Corporation.*/
   3
   4#include "../wifi.h"
   5#include "../efuse.h"
   6#include "../base.h"
   7#include "../regd.h"
   8#include "../cam.h"
   9#include "../ps.h"
  10#include "../pci.h"
  11#include "reg.h"
  12#include "def.h"
  13#include "phy.h"
  14#include "../rtl8723com/phy_common.h"
  15#include "dm.h"
  16#include "../rtl8723com/dm_common.h"
  17#include "fw.h"
  18#include "../rtl8723com/fw_common.h"
  19#include "led.h"
  20#include "hw.h"
  21#include "../pwrseqcmd.h"
  22#include "pwrseq.h"
  23#include "btc.h"
  24
  25#define LLT_CONFIG	5
  26
  27static void _rtl8723e_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  28				       u8 set_bits, u8 clear_bits)
  29{
  30	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  31	struct rtl_priv *rtlpriv = rtl_priv(hw);
  32
  33	rtlpci->reg_bcn_ctrl_val |= set_bits;
  34	rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  35
  36	rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  37}
  38
  39static void _rtl8723e_stop_tx_beacon(struct ieee80211_hw *hw)
  40{
  41	struct rtl_priv *rtlpriv = rtl_priv(hw);
  42	u8 tmp1byte;
  43
  44	tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  45	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  46	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  47	tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  48	tmp1byte &= ~(BIT(0));
  49	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  50}
  51
  52static void _rtl8723e_resume_tx_beacon(struct ieee80211_hw *hw)
  53{
  54	struct rtl_priv *rtlpriv = rtl_priv(hw);
  55	u8 tmp1byte;
  56
  57	tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  58	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
  59	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  60	tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  61	tmp1byte |= BIT(1);
  62	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  63}
  64
  65static void _rtl8723e_enable_bcn_sub_func(struct ieee80211_hw *hw)
  66{
  67	_rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(1));
  68}
  69
  70static void _rtl8723e_disable_bcn_sub_func(struct ieee80211_hw *hw)
  71{
  72	_rtl8723e_set_bcn_ctrl_reg(hw, BIT(1), 0);
  73}
  74
  75void rtl8723e_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  76{
  77	struct rtl_priv *rtlpriv = rtl_priv(hw);
  78	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  79	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  80
  81	switch (variable) {
  82	case HW_VAR_RCR:
  83		*((u32 *)(val)) = rtlpci->receive_config;
  84		break;
  85	case HW_VAR_RF_STATE:
  86		*((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
  87		break;
  88	case HW_VAR_FWLPS_RF_ON:{
  89			enum rf_pwrstate rfstate;
  90			u32 val_rcr;
  91
  92			rtlpriv->cfg->ops->get_hw_reg(hw,
  93						      HW_VAR_RF_STATE,
  94						      (u8 *)(&rfstate));
  95			if (rfstate == ERFOFF) {
  96				*((bool *)(val)) = true;
  97			} else {
  98				val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
  99				val_rcr &= 0x00070000;
 100				if (val_rcr)
 101					*((bool *)(val)) = false;
 102				else
 103					*((bool *)(val)) = true;
 104			}
 105			break;
 106		}
 107	case HW_VAR_FW_PSMODE_STATUS:
 108		*((bool *)(val)) = ppsc->fw_current_inpsmode;
 109		break;
 110	case HW_VAR_CORRECT_TSF:{
 111			u64 tsf;
 112			u32 *ptsf_low = (u32 *)&tsf;
 113			u32 *ptsf_high = ((u32 *)&tsf) + 1;
 114
 115			*ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 116			*ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 117
 118			*((u64 *)(val)) = tsf;
 119
 120			break;
 121		}
 122	case HAL_DEF_WOWLAN:
 123		break;
 124	default:
 125		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
 126			"switch case %#x not processed\n", variable);
 127		break;
 128	}
 129}
 130
 131void rtl8723e_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 132{
 133	struct rtl_priv *rtlpriv = rtl_priv(hw);
 134	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 135	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 136	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 137	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 138	u8 idx;
 139
 140	switch (variable) {
 141	case HW_VAR_ETHER_ADDR:{
 142			for (idx = 0; idx < ETH_ALEN; idx++) {
 143				rtl_write_byte(rtlpriv, (REG_MACID + idx),
 144					       val[idx]);
 145			}
 146			break;
 147		}
 148	case HW_VAR_BASIC_RATE:{
 149			u16 b_rate_cfg = ((u16 *)val)[0];
 150			u8 rate_index = 0;
 151
 152			b_rate_cfg = b_rate_cfg & 0x15f;
 153			b_rate_cfg |= 0x01;
 154			rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
 155			rtl_write_byte(rtlpriv, REG_RRSR + 1,
 156				       (b_rate_cfg >> 8) & 0xff);
 157			while (b_rate_cfg > 0x1) {
 158				b_rate_cfg = (b_rate_cfg >> 1);
 159				rate_index++;
 160			}
 161			rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
 162				       rate_index);
 163			break;
 164		}
 165	case HW_VAR_BSSID:{
 166			for (idx = 0; idx < ETH_ALEN; idx++) {
 167				rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 168					       val[idx]);
 169			}
 170			break;
 171		}
 172	case HW_VAR_SIFS:{
 173			rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 174			rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 175
 176			rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 177			rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 178
 179			if (!mac->ht_enable)
 180				rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 181					       0x0e0e);
 182			else
 183				rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 184					       *((u16 *)val));
 185			break;
 186		}
 187	case HW_VAR_SLOT_TIME:{
 188			u8 e_aci;
 189
 190			rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
 191				"HW_VAR_SLOT_TIME %x\n", val[0]);
 192
 193			rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 194
 195			for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 196				rtlpriv->cfg->ops->set_hw_reg(hw,
 197							      HW_VAR_AC_PARAM,
 198							      (u8 *)(&e_aci));
 199			}
 200			break;
 201		}
 202	case HW_VAR_ACK_PREAMBLE:{
 203			u8 reg_tmp;
 204			u8 short_preamble = (bool)(*(u8 *)val);
 205
 206			reg_tmp = (mac->cur_40_prime_sc) << 5;
 207			if (short_preamble)
 208				reg_tmp |= 0x80;
 209
 210			rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
 211			break;
 212		}
 213	case HW_VAR_AMPDU_MIN_SPACE:{
 214			u8 min_spacing_to_set;
 215
 216			min_spacing_to_set = *((u8 *)val);
 217			if (min_spacing_to_set <= 7) {
 218
 219				mac->min_space_cfg = ((mac->min_space_cfg &
 220						       0xf8) |
 221						      min_spacing_to_set);
 222
 223				*val = min_spacing_to_set;
 224
 225				rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
 226					"Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 227					mac->min_space_cfg);
 228
 229				rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 230					       mac->min_space_cfg);
 231			}
 232			break;
 233		}
 234	case HW_VAR_SHORTGI_DENSITY:{
 235			u8 density_to_set;
 236
 237			density_to_set = *((u8 *)val);
 238			mac->min_space_cfg |= (density_to_set << 3);
 239
 240			rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
 241				"Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 242				mac->min_space_cfg);
 243
 244			rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 245				       mac->min_space_cfg);
 246
 247			break;
 248		}
 249	case HW_VAR_AMPDU_FACTOR:{
 250			u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
 251			u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
 252			u8 factor_toset;
 253			u8 *p_regtoset = NULL;
 254			u8 index = 0;
 255
 256			if ((rtlpriv->btcoexist.bt_coexistence) &&
 257			    (rtlpriv->btcoexist.bt_coexist_type ==
 258				BT_CSR_BC4))
 259				p_regtoset = regtoset_bt;
 260			else
 261				p_regtoset = regtoset_normal;
 262
 263			factor_toset = *((u8 *)val);
 264			if (factor_toset <= 3) {
 265				factor_toset = (1 << (factor_toset + 2));
 266				if (factor_toset > 0xf)
 267					factor_toset = 0xf;
 268
 269				for (index = 0; index < 4; index++) {
 270					if ((p_regtoset[index] & 0xf0) >
 271					    (factor_toset << 4))
 272						p_regtoset[index] =
 273						    (p_regtoset[index] & 0x0f) |
 274						    (factor_toset << 4);
 275
 276					if ((p_regtoset[index] & 0x0f) >
 277					    factor_toset)
 278						p_regtoset[index] =
 279						    (p_regtoset[index] & 0xf0) |
 280						    (factor_toset);
 281
 282					rtl_write_byte(rtlpriv,
 283						       (REG_AGGLEN_LMT + index),
 284						       p_regtoset[index]);
 285				}
 286
 287				rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
 288					"Set HW_VAR_AMPDU_FACTOR: %#x\n",
 289					factor_toset);
 290			}
 291			break;
 292		}
 293	case HW_VAR_AC_PARAM:{
 294			u8 e_aci = *((u8 *)val);
 295
 296			rtl8723_dm_init_edca_turbo(hw);
 297
 298			if (rtlpci->acm_method != EACMWAY2_SW)
 299				rtlpriv->cfg->ops->set_hw_reg(hw,
 300							      HW_VAR_ACM_CTRL,
 301							      (u8 *)(&e_aci));
 302			break;
 303		}
 304	case HW_VAR_ACM_CTRL:{
 305			u8 e_aci = *((u8 *)val);
 306			union aci_aifsn *p_aci_aifsn =
 307			    (union aci_aifsn *)(&mac->ac[0].aifs);
 308			u8 acm = p_aci_aifsn->f.acm;
 309			u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 310
 311			acm_ctrl =
 312			    acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 313
 314			if (acm) {
 315				switch (e_aci) {
 316				case AC0_BE:
 317					acm_ctrl |= ACMHW_BEQEN;
 318					break;
 319				case AC2_VI:
 320					acm_ctrl |= ACMHW_VIQEN;
 321					break;
 322				case AC3_VO:
 323					acm_ctrl |= ACMHW_VOQEN;
 324					break;
 325				default:
 326					rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
 327						"HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 328						acm);
 329					break;
 330				}
 331			} else {
 332				switch (e_aci) {
 333				case AC0_BE:
 334					acm_ctrl &= (~ACMHW_BEQEN);
 335					break;
 336				case AC2_VI:
 337					acm_ctrl &= (~ACMHW_VIQEN);
 338					break;
 339				case AC3_VO:
 340					acm_ctrl &= (~ACMHW_VOQEN);
 341					break;
 342				default:
 343					rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
 344						"switch case %#x not processed\n",
 345						e_aci);
 346					break;
 347				}
 348			}
 349
 350			rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,
 351				"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 352				acm_ctrl);
 353			rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 354			break;
 355		}
 356	case HW_VAR_RCR:{
 357			rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 358			rtlpci->receive_config = ((u32 *)(val))[0];
 359			break;
 360		}
 361	case HW_VAR_RETRY_LIMIT:{
 362			u8 retry_limit = ((u8 *)(val))[0];
 363
 364			rtl_write_word(rtlpriv, REG_RL,
 365				       retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 366				       retry_limit << RETRY_LIMIT_LONG_SHIFT);
 367			break;
 368		}
 369	case HW_VAR_DUAL_TSF_RST:
 370		rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 371		break;
 372	case HW_VAR_EFUSE_BYTES:
 373		rtlefuse->efuse_usedbytes = *((u16 *)val);
 374		break;
 375	case HW_VAR_EFUSE_USAGE:
 376		rtlefuse->efuse_usedpercentage = *((u8 *)val);
 377		break;
 378	case HW_VAR_IO_CMD:
 379		rtl8723e_phy_set_io_cmd(hw, (*(enum io_type *)val));
 380		break;
 381	case HW_VAR_WPA_CONFIG:
 382		rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
 383		break;
 384	case HW_VAR_SET_RPWM:{
 385			u8 rpwm_val;
 386
 387			rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 388			udelay(1);
 389
 390			if (rpwm_val & BIT(7)) {
 391				rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 392					       (*(u8 *)val));
 393			} else {
 394				rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 395					       ((*(u8 *)val) | BIT(7)));
 396			}
 397
 398			break;
 399		}
 400	case HW_VAR_H2C_FW_PWRMODE:{
 401			u8 psmode = (*(u8 *)val);
 402
 403			if (psmode != FW_PS_ACTIVE_MODE)
 404				rtl8723e_dm_rf_saving(hw, true);
 405
 406			rtl8723e_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
 407			break;
 408		}
 409	case HW_VAR_FW_PSMODE_STATUS:
 410		ppsc->fw_current_inpsmode = *((bool *)val);
 411		break;
 412	case HW_VAR_H2C_FW_JOINBSSRPT:{
 413			u8 mstatus = (*(u8 *)val);
 414			u8 tmp_regcr, tmp_reg422;
 415			bool b_recover = false;
 416
 417			if (mstatus == RT_MEDIA_CONNECT) {
 418				rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 419							      NULL);
 420
 421				tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 422				rtl_write_byte(rtlpriv, REG_CR + 1,
 423					       (tmp_regcr | BIT(0)));
 424
 425				_rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(3));
 426				_rtl8723e_set_bcn_ctrl_reg(hw, BIT(4), 0);
 427
 428				tmp_reg422 =
 429				    rtl_read_byte(rtlpriv,
 430						  REG_FWHW_TXQ_CTRL + 2);
 431				if (tmp_reg422 & BIT(6))
 432					b_recover = true;
 433				rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 434					       tmp_reg422 & (~BIT(6)));
 435
 436				rtl8723e_set_fw_rsvdpagepkt(hw, 0);
 437
 438				_rtl8723e_set_bcn_ctrl_reg(hw, BIT(3), 0);
 439				_rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(4));
 440
 441				if (b_recover) {
 442					rtl_write_byte(rtlpriv,
 443						       REG_FWHW_TXQ_CTRL + 2,
 444						       tmp_reg422);
 445				}
 446
 447				rtl_write_byte(rtlpriv, REG_CR + 1,
 448					       (tmp_regcr & ~(BIT(0))));
 449			}
 450			rtl8723e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val));
 451
 452			break;
 453		}
 454	case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:{
 455		rtl8723e_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
 456		break;
 457	}
 458	case HW_VAR_AID:{
 459			u16 u2btmp;
 460
 461			u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 462			u2btmp &= 0xC000;
 463			rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
 464				       (u2btmp | mac->assoc_id));
 465
 466			break;
 467		}
 468	case HW_VAR_CORRECT_TSF:{
 469			u8 btype_ibss = ((u8 *)(val))[0];
 470
 471			if (btype_ibss)
 472				_rtl8723e_stop_tx_beacon(hw);
 473
 474			_rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(3));
 475
 476			rtl_write_dword(rtlpriv, REG_TSFTR,
 477					(u32)(mac->tsf & 0xffffffff));
 478			rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 479					(u32)((mac->tsf >> 32) & 0xffffffff));
 480
 481			_rtl8723e_set_bcn_ctrl_reg(hw, BIT(3), 0);
 482
 483			if (btype_ibss)
 484				_rtl8723e_resume_tx_beacon(hw);
 485
 486			break;
 487		}
 488	case HW_VAR_FW_LPS_ACTION:{
 489			bool b_enter_fwlps = *((bool *)val);
 490			u8 rpwm_val, fw_pwrmode;
 491			bool fw_current_inps;
 492
 493			if (b_enter_fwlps) {
 494				rpwm_val = 0x02;	/* RF off */
 495				fw_current_inps = true;
 496				rtlpriv->cfg->ops->set_hw_reg(hw,
 497						HW_VAR_FW_PSMODE_STATUS,
 498						(u8 *)(&fw_current_inps));
 499				rtlpriv->cfg->ops->set_hw_reg(hw,
 500						HW_VAR_H2C_FW_PWRMODE,
 501						(u8 *)(&ppsc->fwctrl_psmode));
 502
 503				rtlpriv->cfg->ops->set_hw_reg(hw,
 504						HW_VAR_SET_RPWM,
 505						(u8 *)(&rpwm_val));
 506			} else {
 507				rpwm_val = 0x0C;	/* RF on */
 508				fw_pwrmode = FW_PS_ACTIVE_MODE;
 509				fw_current_inps = false;
 510				rtlpriv->cfg->ops->set_hw_reg(hw,
 511							      HW_VAR_SET_RPWM,
 512							      (u8 *)(&rpwm_val));
 513				rtlpriv->cfg->ops->set_hw_reg(hw,
 514						HW_VAR_H2C_FW_PWRMODE,
 515						(u8 *)(&fw_pwrmode));
 516
 517				rtlpriv->cfg->ops->set_hw_reg(hw,
 518						HW_VAR_FW_PSMODE_STATUS,
 519						(u8 *)(&fw_current_inps));
 520			}
 521			 break;
 522		}
 523	default:
 524		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
 525			"switch case %#x not processed\n", variable);
 526		break;
 527	}
 528}
 529
 530static bool _rtl8723e_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 531{
 532	struct rtl_priv *rtlpriv = rtl_priv(hw);
 533	bool status = true;
 534	long count = 0;
 535	u32 value = _LLT_INIT_ADDR(address) |
 536	    _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
 537
 538	rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 539
 540	do {
 541		value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 542		if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 543			break;
 544
 545		if (count > POLLING_LLT_THRESHOLD) {
 546			pr_err("Failed to polling write LLT done at address %d!\n",
 547			       address);
 548			status = false;
 549			break;
 550		}
 551	} while (++count);
 552
 553	return status;
 554}
 555
 556static bool _rtl8723e_llt_table_init(struct ieee80211_hw *hw)
 557{
 558	struct rtl_priv *rtlpriv = rtl_priv(hw);
 559	unsigned short i;
 560	u8 txpktbuf_bndy;
 561	u8 maxpage;
 562	bool status;
 563	u8 ubyte;
 564
 565#if LLT_CONFIG == 1
 566	maxpage = 255;
 567	txpktbuf_bndy = 252;
 568#elif LLT_CONFIG == 2
 569	maxpage = 127;
 570	txpktbuf_bndy = 124;
 571#elif LLT_CONFIG == 3
 572	maxpage = 255;
 573	txpktbuf_bndy = 174;
 574#elif LLT_CONFIG == 4
 575	maxpage = 255;
 576	txpktbuf_bndy = 246;
 577#elif LLT_CONFIG == 5
 578	maxpage = 255;
 579	txpktbuf_bndy = 246;
 580#endif
 581
 582	rtl_write_byte(rtlpriv, REG_CR, 0x8B);
 583
 584#if LLT_CONFIG == 1
 585	rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
 586	rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
 587#elif LLT_CONFIG == 2
 588	rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
 589#elif LLT_CONFIG == 3
 590	rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
 591#elif LLT_CONFIG == 4
 592	rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
 593#elif LLT_CONFIG == 5
 594	rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
 595
 596	rtl_write_dword(rtlpriv, REG_RQPN, 0x80ac1c29);
 597	rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x03);
 598#endif
 599
 600	rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
 601	rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 602
 603	rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 604	rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 605
 606	rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 607	rtl_write_byte(rtlpriv, REG_PBP, 0x11);
 608	rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 609
 610	for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 611		status = _rtl8723e_llt_write(hw, i, i + 1);
 612		if (!status)
 613			return status;
 614	}
 615
 616	status = _rtl8723e_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 617	if (!status)
 618		return status;
 619
 620	for (i = txpktbuf_bndy; i < maxpage; i++) {
 621		status = _rtl8723e_llt_write(hw, i, (i + 1));
 622		if (!status)
 623			return status;
 624	}
 625
 626	status = _rtl8723e_llt_write(hw, maxpage, txpktbuf_bndy);
 627	if (!status)
 628		return status;
 629
 630	rtl_write_byte(rtlpriv, REG_CR, 0xff);
 631	ubyte = rtl_read_byte(rtlpriv, REG_RQPN + 3);
 632	rtl_write_byte(rtlpriv, REG_RQPN + 3, ubyte | BIT(7));
 633
 634	return true;
 635}
 636
 637static void _rtl8723e_gen_refresh_led_state(struct ieee80211_hw *hw)
 638{
 639	struct rtl_priv *rtlpriv = rtl_priv(hw);
 640	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 641	enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
 642
 643	if (rtlpriv->rtlhal.up_first_time)
 644		return;
 645
 646	if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 647		rtl8723e_sw_led_on(hw, pin0);
 648	else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 649		rtl8723e_sw_led_on(hw, pin0);
 650	else
 651		rtl8723e_sw_led_off(hw, pin0);
 652}
 653
 654static bool _rtl8712e_init_mac(struct ieee80211_hw *hw)
 655{
 656	struct rtl_priv *rtlpriv = rtl_priv(hw);
 657	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 658
 659	unsigned char bytetmp;
 660	unsigned short wordtmp;
 661	u16 retry = 0;
 662	u16 tmpu2b;
 663	bool mac_func_enable;
 664
 665	rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 666	bytetmp = rtl_read_byte(rtlpriv, REG_CR);
 667	if (bytetmp == 0xFF)
 668		mac_func_enable = true;
 669	else
 670		mac_func_enable = false;
 671
 672	/* HW Power on sequence */
 673	if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
 674		PWR_INTF_PCI_MSK, RTL8723_NIC_ENABLE_FLOW))
 675		return false;
 676
 677	bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
 678	rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp | BIT(4));
 679
 680	/* eMAC time out function enable, 0x369[7]=1 */
 681	bytetmp = rtl_read_byte(rtlpriv, 0x369);
 682	rtl_write_byte(rtlpriv, 0x369, bytetmp | BIT(7));
 683
 684	/* ePHY reg 0x1e bit[4]=1 using MDIO interface,
 685	 * we should do this before Enabling ASPM backdoor.
 686	 */
 687	do {
 688		rtl_write_word(rtlpriv, 0x358, 0x5e);
 689		udelay(100);
 690		rtl_write_word(rtlpriv, 0x356, 0xc280);
 691		rtl_write_word(rtlpriv, 0x354, 0xc290);
 692		rtl_write_word(rtlpriv, 0x358, 0x3e);
 693		udelay(100);
 694		rtl_write_word(rtlpriv, 0x358, 0x5e);
 695		udelay(100);
 696		tmpu2b = rtl_read_word(rtlpriv, 0x356);
 697		retry++;
 698	} while (tmpu2b != 0xc290 && retry < 100);
 699
 700	if (retry >= 100) {
 701		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
 702			"InitMAC(): ePHY configure fail!!!\n");
 703		return false;
 704	}
 705
 706	rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 707	rtl_write_word(rtlpriv, REG_CR + 1, 0x06);
 708
 709	if (!mac_func_enable) {
 710		if (!_rtl8723e_llt_table_init(hw))
 711			return false;
 712	}
 713
 714	rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 715	rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
 716
 717	rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
 718
 719	wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 720	wordtmp &= 0xf;
 721	wordtmp |= 0xF771;
 722	rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 723
 724	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 725	rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 726	rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
 727	rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 728
 729	rtl_write_byte(rtlpriv, 0x4d0, 0x0);
 730
 731	rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 732			((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 733			DMA_BIT_MASK(32));
 734	rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 735			(u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 736			DMA_BIT_MASK(32));
 737	rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 738			(u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 739	rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 740			(u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 741	rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 742			(u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 743	rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 744			(u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 745	rtl_write_dword(rtlpriv, REG_HQ_DESA,
 746			(u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 747			DMA_BIT_MASK(32));
 748	rtl_write_dword(rtlpriv, REG_RX_DESA,
 749			(u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 750			DMA_BIT_MASK(32));
 751
 752	rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x74);
 753
 754	rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 755
 756	bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 757	rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
 758	do {
 759		retry++;
 760		bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 761	} while ((retry < 200) && (bytetmp & BIT(7)));
 762
 763	_rtl8723e_gen_refresh_led_state(hw);
 764
 765	rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 766
 767	return true;
 768}
 769
 770static void _rtl8723e_hw_configure(struct ieee80211_hw *hw)
 771{
 772	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 773	struct rtl_priv *rtlpriv = rtl_priv(hw);
 774	u8 reg_bw_opmode;
 775	u32 reg_prsr;
 776
 777	reg_bw_opmode = BW_OPMODE_20MHZ;
 778	reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 779
 780	rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
 781
 782	rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 783
 784	rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
 785
 786	rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
 787
 788	rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
 789
 790	rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
 791
 792	rtl_write_word(rtlpriv, REG_RL, 0x0707);
 793
 794	rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
 795
 796	rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 797
 798	rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 799	rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 800	rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 801	rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 802
 803	if ((rtlpriv->btcoexist.bt_coexistence) &&
 804	    (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
 805		rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
 806	else
 807		rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
 808
 809	rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
 810
 811	rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
 812
 813	rtlpci->reg_bcn_ctrl_val = 0x1f;
 814	rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 815
 816	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 817
 818	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 819
 820	rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
 821	rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
 822
 823	if ((rtlpriv->btcoexist.bt_coexistence) &&
 824	    (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) {
 825		rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 826		rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
 827	} else {
 828		rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 829		rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 830	}
 831
 832	if ((rtlpriv->btcoexist.bt_coexistence) &&
 833	    (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
 834		rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
 835	else
 836		rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
 837
 838	rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
 839
 840	rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
 841	rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
 842
 843	rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
 844
 845	rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
 846
 847	rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
 848	rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
 849
 850	rtl_write_dword(rtlpriv, 0x394, 0x1);
 851}
 852
 853static void _rtl8723e_enable_aspm_back_door(struct ieee80211_hw *hw)
 854{
 855	struct rtl_priv *rtlpriv = rtl_priv(hw);
 856	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 857
 858	rtl_write_byte(rtlpriv, 0x34b, 0x93);
 859	rtl_write_word(rtlpriv, 0x350, 0x870c);
 860	rtl_write_byte(rtlpriv, 0x352, 0x1);
 861
 862	if (ppsc->support_backdoor)
 863		rtl_write_byte(rtlpriv, 0x349, 0x1b);
 864	else
 865		rtl_write_byte(rtlpriv, 0x349, 0x03);
 866
 867	rtl_write_word(rtlpriv, 0x350, 0x2718);
 868	rtl_write_byte(rtlpriv, 0x352, 0x1);
 869}
 870
 871void rtl8723e_enable_hw_security_config(struct ieee80211_hw *hw)
 872{
 873	struct rtl_priv *rtlpriv = rtl_priv(hw);
 874	u8 sec_reg_value;
 875
 876	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
 877		"PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 878		rtlpriv->sec.pairwise_enc_algorithm,
 879		rtlpriv->sec.group_enc_algorithm);
 880
 881	if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 882		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
 883			"not open hw encryption\n");
 884		return;
 885	}
 886
 887	sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
 888
 889	if (rtlpriv->sec.use_defaultkey) {
 890		sec_reg_value |= SCR_TXUSEDK;
 891		sec_reg_value |= SCR_RXUSEDK;
 892	}
 893
 894	sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
 895
 896	rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
 897
 898	rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
 899		"The SECR-value %x\n", sec_reg_value);
 900
 901	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 902
 903}
 904
 905int rtl8723e_hw_init(struct ieee80211_hw *hw)
 906{
 907	struct rtl_priv *rtlpriv = rtl_priv(hw);
 908	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 909	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 910	struct rtl_phy *rtlphy = &(rtlpriv->phy);
 911	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 912	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 913	bool rtstatus;
 914	int err;
 915	u8 tmp_u1b;
 916	unsigned long flags;
 917
 918	rtlpriv->rtlhal.being_init_adapter = true;
 919	/* As this function can take a very long time (up to 350 ms)
 920	 * and can be called with irqs disabled, reenable the irqs
 921	 * to let the other devices continue being serviced.
 922	 *
 923	 * It is safe doing so since our own interrupts will only be enabled
 924	 * in a subsequent step.
 925	 */
 926	local_save_flags(flags);
 927	local_irq_enable();
 928	rtlhal->fw_ready = false;
 929
 930	rtlpriv->intf_ops->disable_aspm(hw);
 931	rtstatus = _rtl8712e_init_mac(hw);
 932	if (!rtstatus) {
 933		pr_err("Init MAC failed\n");
 934		err = 1;
 935		goto exit;
 936	}
 937
 938	err = rtl8723_download_fw(hw, false, FW_8723A_POLLING_TIMEOUT_COUNT);
 939	if (err) {
 940		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
 941			"Failed to download FW. Init HW without FW now..\n");
 942		err = 1;
 943		goto exit;
 944	}
 945	rtlhal->fw_ready = true;
 946
 947	rtlhal->last_hmeboxnum = 0;
 948	rtl8723e_phy_mac_config(hw);
 949	/* because last function modify RCR, so we update
 950	 * rcr var here, or TP will unstable for receive_config
 951	 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
 952	 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
 953	 */
 954	rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
 955	rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
 956	rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 957
 958	rtl8723e_phy_bb_config(hw);
 959	rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
 960	rtl8723e_phy_rf_config(hw);
 961	if (IS_VENDOR_UMC_A_CUT(rtlhal->version)) {
 962		rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
 963		rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
 964	} else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) {
 965		rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE);
 966		rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31);
 967		rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425);
 968		rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200);
 969		rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053);
 970		rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201);
 971	}
 972	rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
 973						 RF_CHNLBW, RFREG_OFFSET_MASK);
 974	rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
 975						 RF_CHNLBW, RFREG_OFFSET_MASK);
 976	rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
 977	rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
 978	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
 979	_rtl8723e_hw_configure(hw);
 980	rtl_cam_reset_all_entry(hw);
 981	rtl8723e_enable_hw_security_config(hw);
 982
 983	ppsc->rfpwr_state = ERFON;
 984
 985	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
 986	_rtl8723e_enable_aspm_back_door(hw);
 987	rtlpriv->intf_ops->enable_aspm(hw);
 988
 989	rtl8723e_bt_hw_init(hw);
 990
 991	if (ppsc->rfpwr_state == ERFON) {
 992		rtl8723e_phy_set_rfpath_switch(hw, 1);
 993		if (rtlphy->iqk_initialized) {
 994			rtl8723e_phy_iq_calibrate(hw, true);
 995		} else {
 996			rtl8723e_phy_iq_calibrate(hw, false);
 997			rtlphy->iqk_initialized = true;
 998		}
 999
1000		rtl8723e_dm_check_txpower_tracking(hw);
1001		rtl8723e_phy_lc_calibrate(hw);
1002	}
1003
1004	tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1005	if (!(tmp_u1b & BIT(0))) {
1006		rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1007		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
1008	}
1009
1010	if (!(tmp_u1b & BIT(4))) {
1011		tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1012		tmp_u1b &= 0x0F;
1013		rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1014		udelay(10);
1015		rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1016		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
1017	}
1018	rtl8723e_dm_init(hw);
1019exit:
1020	local_irq_restore(flags);
1021	rtlpriv->rtlhal.being_init_adapter = false;
1022	return err;
1023}
1024
1025static enum version_8723e _rtl8723e_read_chip_version(struct ieee80211_hw *hw)
1026{
1027	struct rtl_priv *rtlpriv = rtl_priv(hw);
1028	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1029	enum version_8723e version = 0x0000;
1030	u32 value32;
1031
1032	value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1033	if (value32 & TRP_VAUX_EN) {
1034		version = (enum version_8723e)(version |
1035			((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1036		/* RTL8723 with BT function. */
1037		version = (enum version_8723e)(version |
1038			((value32 & BT_FUNC) ? CHIP_8723 : 0));
1039
1040	} else {
1041		/* Normal mass production chip. */
1042		version = (enum version_8723e) NORMAL_CHIP;
1043		version = (enum version_8723e)(version |
1044			((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1045		/* RTL8723 with BT function. */
1046		version = (enum version_8723e)(version |
1047			((value32 & BT_FUNC) ? CHIP_8723 : 0));
1048		if (IS_CHIP_VENDOR_UMC(version))
1049			version = (enum version_8723e)(version |
1050			((value32 & CHIP_VER_RTL_MASK)));/* IC version (CUT) */
1051		if (IS_8723_SERIES(version)) {
1052			value32 = rtl_read_dword(rtlpriv, REG_GPIO_OUTSTS);
1053			/* ROM code version. */
1054			version = (enum version_8723e)(version |
1055				((value32 & RF_RL_ID)>>20));
1056		}
1057	}
1058
1059	if (IS_8723_SERIES(version)) {
1060		value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
1061		rtlphy->polarity_ctl = ((value32 & WL_HWPDN_SL) ?
1062					RT_POLARITY_HIGH_ACT :
1063					RT_POLARITY_LOW_ACT);
1064	}
1065	switch (version) {
1066	case VERSION_TEST_UMC_CHIP_8723:
1067		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1068			"Chip Version ID: VERSION_TEST_UMC_CHIP_8723.\n");
1069		break;
1070	case VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT:
1071		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1072			"Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT.\n");
1073		break;
1074	case VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT:
1075		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1076			"Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT.\n");
1077		break;
1078	default:
1079		pr_err("Chip Version ID: Unknown. Bug?\n");
1080		break;
1081	}
1082
1083	if (IS_8723_SERIES(version))
1084		rtlphy->rf_type = RF_1T1R;
1085
1086	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1087		(rtlphy->rf_type == RF_2T2R) ? "RF_2T2R" : "RF_1T1R");
1088
1089	return version;
1090}
1091
1092static int _rtl8723e_set_media_status(struct ieee80211_hw *hw,
1093				      enum nl80211_iftype type)
1094{
1095	struct rtl_priv *rtlpriv = rtl_priv(hw);
1096	u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1097	enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1098	u8 mode = MSR_NOLINK;
1099
1100	rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
1101	rtl_dbg(rtlpriv, COMP_BEACON, DBG_LOUD,
1102		"clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
1103
1104	switch (type) {
1105	case NL80211_IFTYPE_UNSPECIFIED:
1106		mode = MSR_NOLINK;
1107		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1108			"Set Network type to NO LINK!\n");
1109		break;
1110	case NL80211_IFTYPE_ADHOC:
1111		mode = MSR_ADHOC;
1112		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1113			"Set Network type to Ad Hoc!\n");
1114		break;
1115	case NL80211_IFTYPE_STATION:
1116		mode = MSR_INFRA;
1117		ledaction = LED_CTL_LINK;
1118		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1119			"Set Network type to STA!\n");
1120		break;
1121	case NL80211_IFTYPE_AP:
1122		mode = MSR_AP;
1123		ledaction = LED_CTL_LINK;
1124		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1125			"Set Network type to AP!\n");
1126		break;
1127	default:
1128		pr_err("Network type %d not support!\n", type);
1129		return 1;
1130	}
1131
1132	/* MSR_INFRA == Link in infrastructure network;
1133	 * MSR_ADHOC == Link in ad hoc network;
1134	 * Therefore, check link state is necessary.
1135	 *
1136	 * MSR_AP == AP mode; link state is not cared here.
1137	 */
1138	if (mode != MSR_AP &&
1139	    rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1140		mode = MSR_NOLINK;
1141		ledaction = LED_CTL_NO_LINK;
1142	}
1143	if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1144		_rtl8723e_stop_tx_beacon(hw);
1145		_rtl8723e_enable_bcn_sub_func(hw);
1146	} else if (mode == MSR_ADHOC || mode == MSR_AP) {
1147		_rtl8723e_resume_tx_beacon(hw);
1148		_rtl8723e_disable_bcn_sub_func(hw);
1149	} else {
1150		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1151			"Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1152			mode);
1153	}
1154
1155	rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1156	rtlpriv->cfg->ops->led_control(hw, ledaction);
1157	if (mode == MSR_AP)
1158		rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1159	else
1160		rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1161	return 0;
1162}
1163
1164void rtl8723e_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1165{
1166	struct rtl_priv *rtlpriv = rtl_priv(hw);
1167	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1168	u32 reg_rcr = rtlpci->receive_config;
1169
1170	if (rtlpriv->psc.rfpwr_state != ERFON)
1171		return;
1172
1173	if (check_bssid) {
1174		reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1175		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1176					      (u8 *)(&reg_rcr));
1177		_rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(4));
1178	} else if (!check_bssid) {
1179		reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1180		_rtl8723e_set_bcn_ctrl_reg(hw, BIT(4), 0);
1181		rtlpriv->cfg->ops->set_hw_reg(hw,
1182			HW_VAR_RCR, (u8 *)(&reg_rcr));
1183	}
1184}
1185
1186int rtl8723e_set_network_type(struct ieee80211_hw *hw,
1187			      enum nl80211_iftype type)
1188{
1189	struct rtl_priv *rtlpriv = rtl_priv(hw);
1190
1191	if (_rtl8723e_set_media_status(hw, type))
1192		return -EOPNOTSUPP;
1193
1194	if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1195		if (type != NL80211_IFTYPE_AP)
1196			rtl8723e_set_check_bssid(hw, true);
1197	} else {
1198		rtl8723e_set_check_bssid(hw, false);
1199	}
1200
1201	return 0;
1202}
1203
1204/* don't set REG_EDCA_BE_PARAM here
1205 * because mac80211 will send pkt when scan
1206 */
1207void rtl8723e_set_qos(struct ieee80211_hw *hw, int aci)
1208{
1209	struct rtl_priv *rtlpriv = rtl_priv(hw);
1210
1211	rtl8723_dm_init_edca_turbo(hw);
1212	switch (aci) {
1213	case AC1_BK:
1214		rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1215		break;
1216	case AC0_BE:
1217		break;
1218	case AC2_VI:
1219		rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1220		break;
1221	case AC3_VO:
1222		rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1223		break;
1224	default:
1225		WARN_ONCE(true, "rtl8723ae: invalid aci: %d !\n", aci);
1226		break;
1227	}
1228}
1229
1230void rtl8723e_enable_interrupt(struct ieee80211_hw *hw)
1231{
1232	struct rtl_priv *rtlpriv = rtl_priv(hw);
1233	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1234
1235	rtl_write_dword(rtlpriv, 0x3a8, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1236	rtl_write_dword(rtlpriv, 0x3ac, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1237	rtlpci->irq_enabled = true;
1238}
1239
1240void rtl8723e_disable_interrupt(struct ieee80211_hw *hw)
1241{
1242	struct rtl_priv *rtlpriv = rtl_priv(hw);
1243	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1244	rtl_write_dword(rtlpriv, 0x3a8, IMR8190_DISABLED);
1245	rtl_write_dword(rtlpriv, 0x3ac, IMR8190_DISABLED);
1246	rtlpci->irq_enabled = false;
1247	/*synchronize_irq(rtlpci->pdev->irq);*/
1248}
1249
1250static void _rtl8723e_poweroff_adapter(struct ieee80211_hw *hw)
1251{
1252	struct rtl_priv *rtlpriv = rtl_priv(hw);
1253	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1254	u8 u1b_tmp;
1255
1256	/* Combo (PCIe + USB) Card and PCIe-MF Card */
1257	/* 1. Run LPS WL RFOFF flow */
1258	rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1259				 PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW);
1260
1261	/* 2. 0x1F[7:0] = 0 */
1262	/* turn off RF */
1263	rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1264	if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1265	    rtlhal->fw_ready) {
1266		rtl8723ae_firmware_selfreset(hw);
1267	}
1268
1269	/* Reset MCU. Suggested by Filen. */
1270	u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1271	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1272
1273	/* g.	MCUFWDL 0x80[1:0]=0	 */
1274	/* reset MCU ready status */
1275	rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1276
1277	/* HW card disable configuration. */
1278	rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1279		PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW);
1280
1281	/* Reset MCU IO Wrapper */
1282	u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1283	rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1284	u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1285	rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1286
1287	/* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1288	/* lock ISO/CLK/Power control register */
1289	rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1290}
1291
1292void rtl8723e_card_disable(struct ieee80211_hw *hw)
1293{
1294	struct rtl_priv *rtlpriv = rtl_priv(hw);
1295	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1296	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1297	enum nl80211_iftype opmode;
1298
1299	mac->link_state = MAC80211_NOLINK;
1300	opmode = NL80211_IFTYPE_UNSPECIFIED;
1301	_rtl8723e_set_media_status(hw, opmode);
1302	if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1303	    ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1304		rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1305	RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1306	_rtl8723e_poweroff_adapter(hw);
1307
1308	/* after power off we should do iqk again */
1309	rtlpriv->phy.iqk_initialized = false;
1310}
1311
1312void rtl8723e_interrupt_recognized(struct ieee80211_hw *hw,
1313				   struct rtl_int *intvec)
1314{
1315	struct rtl_priv *rtlpriv = rtl_priv(hw);
1316	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1317
1318	intvec->inta = rtl_read_dword(rtlpriv, 0x3a0) & rtlpci->irq_mask[0];
1319	rtl_write_dword(rtlpriv, 0x3a0, intvec->inta);
1320}
1321
1322void rtl8723e_set_beacon_related_registers(struct ieee80211_hw *hw)
1323{
1324
1325	struct rtl_priv *rtlpriv = rtl_priv(hw);
1326	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1327	u16 bcn_interval, atim_window;
1328
1329	bcn_interval = mac->beacon_interval;
1330	atim_window = 2;	/*FIX MERGE */
1331	rtl8723e_disable_interrupt(hw);
1332	rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1333	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1334	rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1335	rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1336	rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1337	rtl_write_byte(rtlpriv, 0x606, 0x30);
1338	rtl8723e_enable_interrupt(hw);
1339}
1340
1341void rtl8723e_set_beacon_interval(struct ieee80211_hw *hw)
1342{
1343	struct rtl_priv *rtlpriv = rtl_priv(hw);
1344	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1345	u16 bcn_interval = mac->beacon_interval;
1346
1347	rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,
1348		"beacon_interval:%d\n", bcn_interval);
1349	rtl8723e_disable_interrupt(hw);
1350	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1351	rtl8723e_enable_interrupt(hw);
1352}
1353
1354void rtl8723e_update_interrupt_mask(struct ieee80211_hw *hw,
1355				    u32 add_msr, u32 rm_msr)
1356{
1357	struct rtl_priv *rtlpriv = rtl_priv(hw);
1358	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1359
1360	rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
1361		"add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1362
1363	if (add_msr)
1364		rtlpci->irq_mask[0] |= add_msr;
1365	if (rm_msr)
1366		rtlpci->irq_mask[0] &= (~rm_msr);
1367	rtl8723e_disable_interrupt(hw);
1368	rtl8723e_enable_interrupt(hw);
1369}
1370
1371static u8 _rtl8723e_get_chnl_group(u8 chnl)
1372{
1373	u8 group;
1374
1375	if (chnl < 3)
1376		group = 0;
1377	else if (chnl < 9)
1378		group = 1;
1379	else
1380		group = 2;
1381	return group;
1382}
1383
1384static noinline_for_stack void
1385_rtl8723e_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1386				      bool autoload_fail, u8 *hwinfo)
1387{
1388	struct rtl_priv *rtlpriv = rtl_priv(hw);
1389	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1390	u8 rf_path, index, tempval;
1391	u16 i;
1392
1393	for (rf_path = 0; rf_path < 1; rf_path++) {
1394		for (i = 0; i < 3; i++) {
1395			if (!autoload_fail) {
1396				rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1397				    hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1398				rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1399				    hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + i];
1400			} else {
1401				rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1402				    EEPROM_DEFAULT_TXPOWERLEVEL;
1403				rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1404				    EEPROM_DEFAULT_TXPOWERLEVEL;
1405			}
1406		}
1407	}
1408
1409	for (i = 0; i < 3; i++) {
1410		if (!autoload_fail)
1411			tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1412		else
1413			tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1414		rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
1415		    (tempval & 0xf);
1416		rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
1417		    ((tempval & 0xf0) >> 4);
1418	}
1419
1420	for (rf_path = 0; rf_path < 2; rf_path++)
1421		for (i = 0; i < 3; i++)
1422			RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1423				"RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1424				 i, rtlefuse->eeprom_chnlarea_txpwr_cck
1425					[rf_path][i]);
1426	for (rf_path = 0; rf_path < 2; rf_path++)
1427		for (i = 0; i < 3; i++)
1428			RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1429				"RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1430				rf_path, i,
1431				rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1432					[rf_path][i]);
1433	for (rf_path = 0; rf_path < 2; rf_path++)
1434		for (i = 0; i < 3; i++)
1435			RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1436				"RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1437				 rf_path, i,
1438				 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1439					[rf_path][i]);
1440
1441	for (rf_path = 0; rf_path < 2; rf_path++) {
1442		for (i = 0; i < 14; i++) {
1443			index = _rtl8723e_get_chnl_group((u8)i);
1444
1445			rtlefuse->txpwrlevel_cck[rf_path][i] =
1446				rtlefuse->eeprom_chnlarea_txpwr_cck
1447					[rf_path][index];
1448			rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1449				rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1450					[rf_path][index];
1451
1452			rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1453				max(rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1454				    rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path][index], 0);
1455		}
1456
1457		for (i = 0; i < 14; i++) {
1458			RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1459				"RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1460				rf_path, i,
1461				rtlefuse->txpwrlevel_cck[rf_path][i],
1462				rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1463				rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1464		}
1465	}
1466
1467	for (i = 0; i < 3; i++) {
1468		if (!autoload_fail) {
1469			rtlefuse->eeprom_pwrlimit_ht40[i] =
1470			    hwinfo[EEPROM_TXPWR_GROUP + i];
1471			rtlefuse->eeprom_pwrlimit_ht20[i] =
1472			    hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1473		} else {
1474			rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1475			rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1476		}
1477	}
1478
1479	for (rf_path = 0; rf_path < 2; rf_path++) {
1480		for (i = 0; i < 14; i++) {
1481			index = _rtl8723e_get_chnl_group((u8)i);
1482
1483			if (rf_path == RF90_PATH_A) {
1484				rtlefuse->pwrgroup_ht20[rf_path][i] =
1485				  (rtlefuse->eeprom_pwrlimit_ht20[index] & 0xf);
1486				rtlefuse->pwrgroup_ht40[rf_path][i] =
1487				  (rtlefuse->eeprom_pwrlimit_ht40[index] & 0xf);
1488			} else if (rf_path == RF90_PATH_B) {
1489				rtlefuse->pwrgroup_ht20[rf_path][i] =
1490				  ((rtlefuse->eeprom_pwrlimit_ht20[index] &
1491				   0xf0) >> 4);
1492				rtlefuse->pwrgroup_ht40[rf_path][i] =
1493				  ((rtlefuse->eeprom_pwrlimit_ht40[index] &
1494				   0xf0) >> 4);
1495			}
1496
1497			RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1498				"RF-%d pwrgroup_ht20[%d] = 0x%x\n", rf_path, i,
1499				rtlefuse->pwrgroup_ht20[rf_path][i]);
1500			RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1501				"RF-%d pwrgroup_ht40[%d] = 0x%x\n", rf_path, i,
1502				rtlefuse->pwrgroup_ht40[rf_path][i]);
1503		}
1504	}
1505
1506	for (i = 0; i < 14; i++) {
1507		index = _rtl8723e_get_chnl_group((u8)i);
1508
1509		if (!autoload_fail)
1510			tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1511		else
1512			tempval = EEPROM_DEFAULT_HT20_DIFF;
1513
1514		rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1515		rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1516		    ((tempval >> 4) & 0xF);
1517
1518		if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1519			rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1520
1521		if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1522			rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1523
1524		index = _rtl8723e_get_chnl_group((u8)i);
1525
1526		if (!autoload_fail)
1527			tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1528		else
1529			tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1530
1531		rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1532		rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1533		    ((tempval >> 4) & 0xF);
1534	}
1535
1536	rtlefuse->legacy_ht_txpowerdiff =
1537	    rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1538
1539	for (i = 0; i < 14; i++)
1540		RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1541			"RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1542			 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1543	for (i = 0; i < 14; i++)
1544		RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1545			"RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1546			 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1547	for (i = 0; i < 14; i++)
1548		RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1549			"RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1550			 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1551	for (i = 0; i < 14; i++)
1552		RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1553			"RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1554			 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1555
1556	if (!autoload_fail)
1557		rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1558	else
1559		rtlefuse->eeprom_regulatory = 0;
1560	RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1561		"eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1562
1563	if (!autoload_fail)
1564		rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1565	else
1566		rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1567
1568	RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1569		"TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1570		 rtlefuse->eeprom_tssi[RF90_PATH_A],
1571		 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1572
1573	if (!autoload_fail)
1574		tempval = hwinfo[EEPROM_THERMAL_METER];
1575	else
1576		tempval = EEPROM_DEFAULT_THERMALMETER;
1577	rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1578
1579	if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1580		rtlefuse->apk_thermalmeterignore = true;
1581
1582	rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1583	RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1584		"thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1585}
1586
1587static void _rtl8723e_read_adapter_info(struct ieee80211_hw *hw,
1588					bool b_pseudo_test)
1589{
1590	struct rtl_priv *rtlpriv = rtl_priv(hw);
1591	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1592	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1593	int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1594			EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
1595			EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1596			COUNTRY_CODE_WORLD_WIDE_13};
1597	u8 *hwinfo;
1598
1599	if (b_pseudo_test) {
1600		/* need add */
1601		return;
1602	}
1603	hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1604	if (!hwinfo)
1605		return;
1606
1607	if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1608		goto exit;
1609
1610	_rtl8723e_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
1611					      hwinfo);
1612
1613	rtl8723e_read_bt_coexist_info_from_hwpg(hw,
1614			rtlefuse->autoload_failflag, hwinfo);
1615
1616	if (rtlhal->oem_id != RT_CID_DEFAULT)
1617		goto exit;
1618
1619	switch (rtlefuse->eeprom_oemid) {
1620	case EEPROM_CID_DEFAULT:
1621		switch (rtlefuse->eeprom_did) {
1622		case 0x8176:
1623			switch (rtlefuse->eeprom_svid) {
1624			case 0x10EC:
1625				switch (rtlefuse->eeprom_smid) {
1626				case 0x6151 ... 0x6152:
1627				case 0x6154 ... 0x6155:
1628				case 0x6177 ... 0x6180:
1629				case 0x7151 ... 0x7152:
1630				case 0x7154 ... 0x7155:
1631				case 0x7177 ... 0x7180:
1632				case 0x8151 ... 0x8152:
1633				case 0x8154 ... 0x8155:
1634				case 0x8181 ... 0x8182:
1635				case 0x8184 ... 0x8185:
1636				case 0x9151 ... 0x9152:
1637				case 0x9154 ... 0x9155:
1638				case 0x9181 ... 0x9182:
1639				case 0x9184 ... 0x9185:
1640					rtlhal->oem_id = RT_CID_TOSHIBA;
1641					break;
1642				case 0x6191 ... 0x6193:
1643				case 0x7191 ... 0x7193:
1644				case 0x8191 ... 0x8193:
1645				case 0x9191 ... 0x9193:
1646					rtlhal->oem_id = RT_CID_819X_SAMSUNG;
1647					break;
1648				case 0x8197:
1649				case 0x9196:
1650					rtlhal->oem_id = RT_CID_819X_CLEVO;
1651					break;
1652				case 0x8203:
1653					rtlhal->oem_id = RT_CID_819X_PRONETS;
1654					break;
1655				case 0x8195:
1656				case 0x9195:
1657				case 0x7194:
1658				case 0x8200 ... 0x8202:
1659				case 0x9200:
1660					rtlhal->oem_id = RT_CID_819X_LENOVO;
1661					break;
1662				}
1663				break;
1664			case 0x1025:
1665				rtlhal->oem_id = RT_CID_819X_ACER;
1666				break;
1667			case 0x1028:
1668				switch (rtlefuse->eeprom_smid) {
1669				case 0x8194:
1670				case 0x8198:
1671				case 0x9197 ... 0x9198:
1672					rtlhal->oem_id = RT_CID_819X_DELL;
1673					break;
1674				}
1675				break;
1676			case 0x103C:
1677				switch (rtlefuse->eeprom_smid) {
1678				case 0x1629:
1679					rtlhal->oem_id = RT_CID_819X_HP;
1680				}
1681				break;
1682			case 0x1A32:
1683				switch (rtlefuse->eeprom_smid) {
1684				case 0x2315:
1685					rtlhal->oem_id = RT_CID_819X_QMI;
1686					break;
1687				}
1688				break;
1689			case 0x1043:
1690				switch (rtlefuse->eeprom_smid) {
1691				case 0x84B5:
1692					rtlhal->oem_id =
1693						RT_CID_819X_EDIMAX_ASUS;
1694				}
1695				break;
1696			}
1697			break;
1698		case 0x8178:
1699			switch (rtlefuse->eeprom_svid) {
1700			case 0x10ec:
1701				switch (rtlefuse->eeprom_smid) {
1702				case 0x6181 ... 0x6182:
1703				case 0x6184 ... 0x6185:
1704				case 0x7181 ... 0x7182:
1705				case 0x7184 ... 0x7185:
1706				case 0x8181 ... 0x8182:
1707				case 0x8184 ... 0x8185:
1708				case 0x9181 ... 0x9182:
1709				case 0x9184 ... 0x9185:
1710					rtlhal->oem_id = RT_CID_TOSHIBA;
1711					break;
1712				case 0x8186:
1713					rtlhal->oem_id =
1714						RT_CID_819X_PRONETS;
1715					break;
1716				}
1717				break;
1718			case 0x1025:
1719				rtlhal->oem_id = RT_CID_819X_ACER;
1720				break;
1721			case 0x1043:
1722				switch (rtlefuse->eeprom_smid) {
1723				case 0x8486:
1724					rtlhal->oem_id =
1725					     RT_CID_819X_EDIMAX_ASUS;
1726				}
1727				break;
1728			}
1729			break;
1730		}
1731		break;
1732	case EEPROM_CID_TOSHIBA:
1733		rtlhal->oem_id = RT_CID_TOSHIBA;
1734		break;
1735	case EEPROM_CID_CCX:
1736		rtlhal->oem_id = RT_CID_CCX;
1737		break;
1738	case EEPROM_CID_QMI:
1739		rtlhal->oem_id = RT_CID_819X_QMI;
1740		break;
1741	case EEPROM_CID_WHQL:
1742		break;
1743	default:
1744		rtlhal->oem_id = RT_CID_DEFAULT;
1745		break;
1746	}
1747exit:
1748	kfree(hwinfo);
1749}
1750
1751static void _rtl8723e_hal_customized_behavior(struct ieee80211_hw *hw)
1752{
1753	struct rtl_priv *rtlpriv = rtl_priv(hw);
1754	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1755
1756	rtlpriv->ledctl.led_opendrain = true;
1757	switch (rtlhal->oem_id) {
1758	case RT_CID_819X_HP:
1759		rtlpriv->ledctl.led_opendrain = true;
1760		break;
1761	case RT_CID_819X_LENOVO:
1762	case RT_CID_DEFAULT:
1763	case RT_CID_TOSHIBA:
1764	case RT_CID_CCX:
1765	case RT_CID_819X_ACER:
1766	case RT_CID_WHQL:
1767	default:
1768		break;
1769	}
1770	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1771		"RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1772}
1773
1774void rtl8723e_read_eeprom_info(struct ieee80211_hw *hw)
1775{
1776	struct rtl_priv *rtlpriv = rtl_priv(hw);
1777	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1778	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1779	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1780	u8 tmp_u1b;
1781	u32 value32;
1782
1783	value32 = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST]);
1784	value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1785	rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST], value32);
1786
1787	rtlhal->version = _rtl8723e_read_chip_version(hw);
1788
1789	if (get_rf_type(rtlphy) == RF_1T1R)
1790		rtlpriv->dm.rfpath_rxenable[0] = true;
1791	else
1792		rtlpriv->dm.rfpath_rxenable[0] =
1793		    rtlpriv->dm.rfpath_rxenable[1] = true;
1794	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1795		rtlhal->version);
1796
1797	tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1798	if (tmp_u1b & BIT(4)) {
1799		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1800		rtlefuse->epromtype = EEPROM_93C46;
1801	} else {
1802		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1803		rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1804	}
1805	if (tmp_u1b & BIT(5)) {
1806		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1807		rtlefuse->autoload_failflag = false;
1808		_rtl8723e_read_adapter_info(hw, false);
1809	} else {
1810		rtlefuse->autoload_failflag = true;
1811		_rtl8723e_read_adapter_info(hw, false);
1812		pr_err("Autoload ERR!!\n");
1813	}
1814	_rtl8723e_hal_customized_behavior(hw);
1815}
1816
1817static void rtl8723e_update_hal_rate_table(struct ieee80211_hw *hw,
1818					   struct ieee80211_sta *sta)
1819{
1820	struct rtl_priv *rtlpriv = rtl_priv(hw);
1821	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1822	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1823	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1824	u32 ratr_value;
1825	u8 ratr_index = 0;
1826	u8 b_nmode = mac->ht_enable;
1827	u16 shortgi_rate;
1828	u32 tmp_ratr_value;
1829	u8 curtxbw_40mhz = mac->bw_40;
1830	u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1831				1 : 0;
1832	u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1833				1 : 0;
1834	enum wireless_mode wirelessmode = mac->mode;
1835	u32 ratr_mask;
1836
1837	if (rtlhal->current_bandtype == BAND_ON_5G)
1838		ratr_value = sta->deflink.supp_rates[1] << 4;
1839	else
1840		ratr_value = sta->deflink.supp_rates[0];
1841	if (mac->opmode == NL80211_IFTYPE_ADHOC)
1842		ratr_value = 0xfff;
1843	ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
1844			sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1845	switch (wirelessmode) {
1846	case WIRELESS_MODE_B:
1847		if (ratr_value & 0x0000000c)
1848			ratr_value &= 0x0000000d;
1849		else
1850			ratr_value &= 0x0000000f;
1851		break;
1852	case WIRELESS_MODE_G:
1853		ratr_value &= 0x00000FF5;
1854		break;
1855	case WIRELESS_MODE_N_24G:
1856	case WIRELESS_MODE_N_5G:
1857		b_nmode = 1;
1858		if (get_rf_type(rtlphy) == RF_1T2R ||
1859		    get_rf_type(rtlphy) == RF_1T1R)
1860			ratr_mask = 0x000ff005;
1861		else
1862			ratr_mask = 0x0f0ff005;
1863
1864		ratr_value &= ratr_mask;
1865		break;
1866	default:
1867		if (rtlphy->rf_type == RF_1T2R)
1868			ratr_value &= 0x000ff0ff;
1869		else
1870			ratr_value &= 0x0f0ff0ff;
1871
1872		break;
1873	}
1874
1875	if ((rtlpriv->btcoexist.bt_coexistence) &&
1876	    (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
1877	    (rtlpriv->btcoexist.bt_cur_state) &&
1878	    (rtlpriv->btcoexist.bt_ant_isolation) &&
1879	    ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
1880	    (rtlpriv->btcoexist.bt_service == BT_BUSY)))
1881		ratr_value &= 0x0fffcfc0;
1882	else
1883		ratr_value &= 0x0FFFFFFF;
1884
1885	if (b_nmode &&
1886	    ((curtxbw_40mhz && curshortgi_40mhz) ||
1887	     (!curtxbw_40mhz && curshortgi_20mhz))) {
1888		ratr_value |= 0x10000000;
1889		tmp_ratr_value = (ratr_value >> 12);
1890
1891		for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1892			if ((1 << shortgi_rate) & tmp_ratr_value)
1893				break;
1894		}
1895
1896		shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1897		    (shortgi_rate << 4) | (shortgi_rate);
1898	}
1899
1900	rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1901
1902	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
1903		"%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
1904}
1905
1906static void rtl8723e_update_hal_rate_mask(struct ieee80211_hw *hw,
1907					  struct ieee80211_sta *sta,
1908					  u8 rssi_level, bool update_bw)
1909{
1910	struct rtl_priv *rtlpriv = rtl_priv(hw);
1911	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1912	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1913	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1914	struct rtl_sta_info *sta_entry = NULL;
1915	u32 ratr_bitmap;
1916	u8 ratr_index;
1917	u8 curtxbw_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
1918				? 1 : 0;
1919	u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1920				1 : 0;
1921	u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1922				1 : 0;
1923	enum wireless_mode wirelessmode = 0;
1924	bool shortgi = false;
1925	u8 rate_mask[5];
1926	u8 macid = 0;
1927	/*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
1928
1929	sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1930	wirelessmode = sta_entry->wireless_mode;
1931	if (mac->opmode == NL80211_IFTYPE_STATION)
1932		curtxbw_40mhz = mac->bw_40;
1933	else if (mac->opmode == NL80211_IFTYPE_AP ||
1934		mac->opmode == NL80211_IFTYPE_ADHOC)
1935		macid = sta->aid + 1;
1936
1937	if (rtlhal->current_bandtype == BAND_ON_5G)
1938		ratr_bitmap = sta->deflink.supp_rates[1] << 4;
1939	else
1940		ratr_bitmap = sta->deflink.supp_rates[0];
1941	if (mac->opmode == NL80211_IFTYPE_ADHOC)
1942		ratr_bitmap = 0xfff;
1943	ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
1944			sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1945	switch (wirelessmode) {
1946	case WIRELESS_MODE_B:
1947		ratr_index = RATR_INX_WIRELESS_B;
1948		if (ratr_bitmap & 0x0000000c)
1949			ratr_bitmap &= 0x0000000d;
1950		else
1951			ratr_bitmap &= 0x0000000f;
1952		break;
1953	case WIRELESS_MODE_G:
1954		ratr_index = RATR_INX_WIRELESS_GB;
1955
1956		if (rssi_level == 1)
1957			ratr_bitmap &= 0x00000f00;
1958		else if (rssi_level == 2)
1959			ratr_bitmap &= 0x00000ff0;
1960		else
1961			ratr_bitmap &= 0x00000ff5;
1962		break;
1963	case WIRELESS_MODE_A:
1964		ratr_index = RATR_INX_WIRELESS_G;
1965		ratr_bitmap &= 0x00000ff0;
1966		break;
1967	case WIRELESS_MODE_N_24G:
1968	case WIRELESS_MODE_N_5G:
1969		ratr_index = RATR_INX_WIRELESS_NGB;
1970		if (rtlphy->rf_type == RF_1T2R ||
1971		    rtlphy->rf_type == RF_1T1R) {
1972			if (curtxbw_40mhz) {
1973				if (rssi_level == 1)
1974					ratr_bitmap &= 0x000f0000;
1975				else if (rssi_level == 2)
1976					ratr_bitmap &= 0x000ff000;
1977				else
1978					ratr_bitmap &= 0x000ff015;
1979			} else {
1980				if (rssi_level == 1)
1981					ratr_bitmap &= 0x000f0000;
1982				else if (rssi_level == 2)
1983					ratr_bitmap &= 0x000ff000;
1984				else
1985					ratr_bitmap &= 0x000ff005;
1986			}
1987		} else {
1988			if (curtxbw_40mhz) {
1989				if (rssi_level == 1)
1990					ratr_bitmap &= 0x0f0f0000;
1991				else if (rssi_level == 2)
1992					ratr_bitmap &= 0x0f0ff000;
1993				else
1994					ratr_bitmap &= 0x0f0ff015;
1995			} else {
1996				if (rssi_level == 1)
1997					ratr_bitmap &= 0x0f0f0000;
1998				else if (rssi_level == 2)
1999					ratr_bitmap &= 0x0f0ff000;
2000				else
2001					ratr_bitmap &= 0x0f0ff005;
2002			}
2003		}
2004
2005		if ((curtxbw_40mhz && curshortgi_40mhz) ||
2006		    (!curtxbw_40mhz && curshortgi_20mhz)) {
2007			if (macid == 0)
2008				shortgi = true;
2009			else if (macid == 1)
2010				shortgi = false;
2011		}
2012		break;
2013	default:
2014		ratr_index = RATR_INX_WIRELESS_NGB;
2015
2016		if (rtlphy->rf_type == RF_1T2R)
2017			ratr_bitmap &= 0x000ff0ff;
2018		else
2019			ratr_bitmap &= 0x0f0ff0ff;
2020		break;
2021	}
2022	sta_entry->ratr_index = ratr_index;
2023
2024	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2025		"ratr_bitmap :%x\n", ratr_bitmap);
2026	*(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2027			     (ratr_index << 28);
2028	rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2029	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2030		"Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2031		ratr_index, ratr_bitmap,
2032		rate_mask[0], rate_mask[1],
2033		rate_mask[2], rate_mask[3],
2034		rate_mask[4]);
2035	rtl8723e_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2036}
2037
2038void rtl8723e_update_hal_rate_tbl(struct ieee80211_hw *hw,
2039				  struct ieee80211_sta *sta, u8 rssi_level,
2040				  bool update_bw)
2041{
2042	struct rtl_priv *rtlpriv = rtl_priv(hw);
2043
2044	if (rtlpriv->dm.useramask)
2045		rtl8723e_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
2046	else
2047		rtl8723e_update_hal_rate_table(hw, sta);
2048}
2049
2050void rtl8723e_update_channel_access_setting(struct ieee80211_hw *hw)
2051{
2052	struct rtl_priv *rtlpriv = rtl_priv(hw);
2053	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2054	u16 sifs_timer;
2055
2056	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2057	if (!mac->ht_enable)
2058		sifs_timer = 0x0a0a;
2059	else
2060		sifs_timer = 0x1010;
2061	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2062}
2063
2064bool rtl8723e_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2065{
2066	struct rtl_priv *rtlpriv = rtl_priv(hw);
2067	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2068	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2069	enum rf_pwrstate e_rfpowerstate_toset;
2070	u8 u1tmp;
2071	bool b_actuallyset = false;
2072
2073	if (rtlpriv->rtlhal.being_init_adapter)
2074		return false;
2075
2076	if (ppsc->swrf_processing)
2077		return false;
2078
2079	spin_lock(&rtlpriv->locks.rf_ps_lock);
2080	if (ppsc->rfchange_inprogress) {
2081		spin_unlock(&rtlpriv->locks.rf_ps_lock);
2082		return false;
2083	} else {
2084		ppsc->rfchange_inprogress = true;
2085		spin_unlock(&rtlpriv->locks.rf_ps_lock);
2086	}
2087
2088	rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
2089		       rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2)&~(BIT(1)));
2090
2091	u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
2092
2093	if (rtlphy->polarity_ctl)
2094		e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
2095	else
2096		e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
2097
2098	if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2099		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2100			"GPIOChangeRF  - HW Radio ON, RF ON\n");
2101
2102		e_rfpowerstate_toset = ERFON;
2103		ppsc->hwradiooff = false;
2104		b_actuallyset = true;
2105	} else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2106		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2107			"GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2108
2109		e_rfpowerstate_toset = ERFOFF;
2110		ppsc->hwradiooff = true;
2111		b_actuallyset = true;
2112	}
2113
2114	if (b_actuallyset) {
2115		spin_lock(&rtlpriv->locks.rf_ps_lock);
2116		ppsc->rfchange_inprogress = false;
2117		spin_unlock(&rtlpriv->locks.rf_ps_lock);
2118	} else {
2119		if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2120			RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2121
2122		spin_lock(&rtlpriv->locks.rf_ps_lock);
2123		ppsc->rfchange_inprogress = false;
2124		spin_unlock(&rtlpriv->locks.rf_ps_lock);
2125	}
2126
2127	*valid = 1;
2128	return !ppsc->hwradiooff;
2129
2130}
2131
2132void rtl8723e_set_key(struct ieee80211_hw *hw, u32 key_index,
2133		      u8 *p_macaddr, bool is_group, u8 enc_algo,
2134		      bool is_wepkey, bool clear_all)
2135{
2136	struct rtl_priv *rtlpriv = rtl_priv(hw);
2137	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2138	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2139	u8 *macaddr = p_macaddr;
2140	u32 entry_id = 0;
2141	bool is_pairwise = false;
2142
2143	static u8 cam_const_addr[4][6] = {
2144		{0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2145		{0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2146		{0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2147		{0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2148	};
2149	static u8 cam_const_broad[] = {
2150		0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2151	};
2152
2153	if (clear_all) {
2154		u8 idx = 0;
2155		u8 cam_offset = 0;
2156		u8 clear_number = 5;
2157
2158		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2159
2160		for (idx = 0; idx < clear_number; idx++) {
2161			rtl_cam_mark_invalid(hw, cam_offset + idx);
2162			rtl_cam_empty_entry(hw, cam_offset + idx);
2163
2164			if (idx < 5) {
2165				memset(rtlpriv->sec.key_buf[idx], 0,
2166				       MAX_KEY_LEN);
2167				rtlpriv->sec.key_len[idx] = 0;
2168			}
2169		}
2170
2171	} else {
2172		switch (enc_algo) {
2173		case WEP40_ENCRYPTION:
2174			enc_algo = CAM_WEP40;
2175			break;
2176		case WEP104_ENCRYPTION:
2177			enc_algo = CAM_WEP104;
2178			break;
2179		case TKIP_ENCRYPTION:
2180			enc_algo = CAM_TKIP;
2181			break;
2182		case AESCCMP_ENCRYPTION:
2183			enc_algo = CAM_AES;
2184			break;
2185		default:
2186			rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
2187				"switch case %#x not processed\n", enc_algo);
2188			enc_algo = CAM_TKIP;
2189			break;
2190		}
2191
2192		if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2193			macaddr = cam_const_addr[key_index];
2194			entry_id = key_index;
2195		} else {
2196			if (is_group) {
2197				macaddr = cam_const_broad;
2198				entry_id = key_index;
2199			} else {
2200				if (mac->opmode == NL80211_IFTYPE_AP) {
2201					entry_id =
2202					  rtl_cam_get_free_entry(hw, p_macaddr);
2203					if (entry_id >=  TOTAL_CAM_ENTRY) {
2204						pr_err("Can not find free hw security cam entry\n");
2205						return;
2206					}
2207				} else {
2208					entry_id = CAM_PAIRWISE_KEY_POSITION;
2209				}
2210
2211				key_index = PAIRWISE_KEYIDX;
2212				is_pairwise = true;
2213			}
2214		}
2215
2216		if (rtlpriv->sec.key_len[key_index] == 0) {
2217			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2218				"delete one entry, entry_id is %d\n",
2219				entry_id);
2220			if (mac->opmode == NL80211_IFTYPE_AP)
2221				rtl_cam_del_entry(hw, p_macaddr);
2222			rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2223		} else {
2224			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2225				"add one entry\n");
2226			if (is_pairwise) {
2227				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2228					"set Pairwise key\n");
2229
2230				rtl_cam_add_one_entry(hw, macaddr, key_index,
2231						      entry_id, enc_algo,
2232						      CAM_CONFIG_NO_USEDK,
2233						      rtlpriv->sec.key_buf[key_index]);
2234			} else {
2235				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2236					"set group key\n");
2237
2238				if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2239					rtl_cam_add_one_entry(hw,
2240							rtlefuse->dev_addr,
2241							PAIRWISE_KEYIDX,
2242							CAM_PAIRWISE_KEY_POSITION,
2243							enc_algo,
2244							CAM_CONFIG_NO_USEDK,
2245							rtlpriv->sec.key_buf
2246							[entry_id]);
2247				}
2248
2249				rtl_cam_add_one_entry(hw, macaddr, key_index,
2250						entry_id, enc_algo,
2251						CAM_CONFIG_NO_USEDK,
2252						rtlpriv->sec.key_buf[entry_id]);
2253			}
2254
2255		}
2256	}
2257}
2258
2259static void rtl8723e_bt_var_init(struct ieee80211_hw *hw)
2260{
2261	struct rtl_priv *rtlpriv = rtl_priv(hw);
2262
2263	rtlpriv->btcoexist.bt_coexistence =
2264		rtlpriv->btcoexist.eeprom_bt_coexist;
2265	rtlpriv->btcoexist.bt_ant_num =
2266		rtlpriv->btcoexist.eeprom_bt_ant_num;
2267	rtlpriv->btcoexist.bt_coexist_type =
2268		rtlpriv->btcoexist.eeprom_bt_type;
2269
2270	rtlpriv->btcoexist.bt_ant_isolation =
2271		rtlpriv->btcoexist.eeprom_bt_ant_isol;
2272
2273	rtlpriv->btcoexist.bt_radio_shared_type =
2274		rtlpriv->btcoexist.eeprom_bt_radio_shared;
2275
2276	rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2277		"BT Coexistence = 0x%x\n",
2278		rtlpriv->btcoexist.bt_coexistence);
2279
2280	if (rtlpriv->btcoexist.bt_coexistence) {
2281		rtlpriv->btcoexist.bt_busy_traffic = false;
2282		rtlpriv->btcoexist.bt_traffic_mode_set = false;
2283		rtlpriv->btcoexist.bt_non_traffic_mode_set = false;
2284
2285		rtlpriv->btcoexist.cstate = 0;
2286		rtlpriv->btcoexist.previous_state = 0;
2287
2288		if (rtlpriv->btcoexist.bt_ant_num == ANT_X2) {
2289			rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2290				"BlueTooth BT_Ant_Num = Antx2\n");
2291		} else if (rtlpriv->btcoexist.bt_ant_num == ANT_X1) {
2292			rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2293				"BlueTooth BT_Ant_Num = Antx1\n");
2294		}
2295		switch (rtlpriv->btcoexist.bt_coexist_type) {
2296		case BT_2WIRE:
2297			rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2298				"BlueTooth BT_CoexistType = BT_2Wire\n");
2299			break;
2300		case BT_ISSC_3WIRE:
2301			rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2302				"BlueTooth BT_CoexistType = BT_ISSC_3Wire\n");
2303			break;
2304		case BT_ACCEL:
2305			rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2306				"BlueTooth BT_CoexistType = BT_ACCEL\n");
2307			break;
2308		case BT_CSR_BC4:
2309			rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2310				"BlueTooth BT_CoexistType = BT_CSR_BC4\n");
2311			break;
2312		case BT_CSR_BC8:
2313			rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2314				"BlueTooth BT_CoexistType = BT_CSR_BC8\n");
2315			break;
2316		case BT_RTL8756:
2317			rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2318				"BlueTooth BT_CoexistType = BT_RTL8756\n");
2319			break;
2320		default:
2321			rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2322				"BlueTooth BT_CoexistType = Unknown\n");
2323			break;
2324		}
2325		rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2326			"BlueTooth BT_Ant_isolation = %d\n",
2327			 rtlpriv->btcoexist.bt_ant_isolation);
2328		rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2329			"BT_RadioSharedType = 0x%x\n",
2330			 rtlpriv->btcoexist.bt_radio_shared_type);
2331		rtlpriv->btcoexist.bt_active_zero_cnt = 0;
2332		rtlpriv->btcoexist.cur_bt_disabled = false;
2333		rtlpriv->btcoexist.pre_bt_disabled = false;
2334	}
2335}
2336
2337void rtl8723e_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2338					     bool auto_load_fail, u8 *hwinfo)
2339{
2340	struct rtl_priv *rtlpriv = rtl_priv(hw);
2341	u8 value;
2342	u32 tmpu_32;
2343
2344	if (!auto_load_fail) {
2345		tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2346		if (tmpu_32 & BIT(18))
2347			rtlpriv->btcoexist.eeprom_bt_coexist = 1;
2348		else
2349			rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2350		value = hwinfo[RF_OPTION4];
2351		rtlpriv->btcoexist.eeprom_bt_type = BT_RTL8723A;
2352		rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1);
2353		rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4);
2354		rtlpriv->btcoexist.eeprom_bt_radio_shared =
2355		  ((value & 0x20) >> 5);
2356	} else {
2357		rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2358		rtlpriv->btcoexist.eeprom_bt_type = BT_RTL8723A;
2359		rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2360		rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2361		rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2362	}
2363
2364	rtl8723e_bt_var_init(hw);
2365}
2366
2367void rtl8723e_bt_reg_init(struct ieee80211_hw *hw)
2368{
2369	struct rtl_priv *rtlpriv = rtl_priv(hw);
2370
2371	/* 0:Low, 1:High, 2:From Efuse. */
2372	rtlpriv->btcoexist.reg_bt_iso = 2;
2373	/* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2374	rtlpriv->btcoexist.reg_bt_sco = 3;
2375	/* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2376	rtlpriv->btcoexist.reg_bt_sco = 0;
2377}
2378
2379void rtl8723e_bt_hw_init(struct ieee80211_hw *hw)
2380{
2381	struct rtl_priv *rtlpriv = rtl_priv(hw);
2382
2383	if (rtlpriv->cfg->ops->get_btc_status())
2384		rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2385}
2386
2387void rtl8723e_suspend(struct ieee80211_hw *hw)
2388{
2389}
2390
2391void rtl8723e_resume(struct ieee80211_hw *hw)
2392{
2393}