reg.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Copyright(c) 2009-2012  Realtek Corporation.*/
   3
   4#ifndef __REALTEK_92S_REG_H__
   5#define __REALTEK_92S_REG_H__
   6
   7/* 1. System Configuration Registers  */
   8#define	REG_SYS_ISO_CTRL			0x0000
   9#define	REG_SYS_FUNC_EN				0x0002
  10#define	PMC_FSM					0x0004
  11#define	SYS_CLKR				0x0008
  12#define	EPROM_CMD				0x000A
  13#define	EE_VPD					0x000C
  14#define	AFE_MISC				0x0010
  15#define	SPS0_CTRL				0x0011
  16#define	SPS1_CTRL				0x0018
  17#define	RF_CTRL					0x001F
  18#define	LDOA15_CTRL				0x0020
  19#define	LDOV12D_CTRL				0x0021
  20#define	LDOHCI12_CTRL				0x0022
  21#define	LDO_USB_SDIO				0x0023
  22#define	LPLDO_CTRL				0x0024
  23#define	AFE_XTAL_CTRL				0x0026
  24#define	AFE_PLL_CTRL				0x0028
  25#define	REG_EFUSE_CTRL				0x0030
  26#define	REG_EFUSE_TEST				0x0034
  27#define	PWR_DATA				0x0038
  28#define	DBG_PORT				0x003A
  29#define	DPS_TIMER				0x003C
  30#define	RCLK_MON				0x003E
  31
  32/* 2. Command Control Registers	  */
  33#define	CMDR					0x0040
  34#define	TXPAUSE					0x0042
  35#define	LBKMD_SEL				0x0043
  36#define	TCR					0x0044
  37#define	RCR					0x0048
  38#define	MSR					0x004C
  39#define	SYSF_CFG				0x004D
  40#define	RX_PKY_LIMIT				0x004E
  41#define	MBIDCTRL				0x004F
  42
  43/* 3. MACID Setting Registers	 */
  44#define	MACIDR					0x0050
  45#define	MACIDR0					0x0050
  46#define	MACIDR4					0x0054
  47#define	BSSIDR					0x0058
  48#define	HWVID					0x005E
  49#define	MAR					0x0060
  50#define	MBIDCAMCONTENT				0x0068
  51#define	MBIDCAMCFG				0x0070
  52#define	BUILDTIME				0x0074
  53#define	BUILDUSER				0x0078
  54
  55#define	IDR0					MACIDR0
  56#define	IDR4					MACIDR4
  57
  58/* 4. Timing Control Registers	 */
  59#define	TSFR					0x0080
  60#define	SLOT_TIME				0x0089
  61#define	USTIME					0x008A
  62#define	SIFS_CCK				0x008C
  63#define	SIFS_OFDM				0x008E
  64#define	PIFS_TIME				0x0090
  65#define	ACK_TIMEOUT				0x0091
  66#define	EIFSTR					0x0092
  67#define	BCN_INTERVAL				0x0094
  68#define	ATIMWND					0x0096
  69#define	BCN_DRV_EARLY_INT			0x0098
  70#define	BCN_DMATIME				0x009A
  71#define	BCN_ERR_THRESH				0x009C
  72#define	MLT					0x009D
  73#define	RSVD_MAC_TUNE_US			0x009E
  74
  75/* 5. FIFO Control Registers	  */
  76#define RQPN					0x00A0
  77#define	RQPN1					0x00A0
  78#define	RQPN2					0x00A1
  79#define	RQPN3					0x00A2
  80#define	RQPN4					0x00A3
  81#define	RQPN5					0x00A4
  82#define	RQPN6					0x00A5
  83#define	RQPN7					0x00A6
  84#define	RQPN8					0x00A7
  85#define	RQPN9					0x00A8
  86#define	RQPN10					0x00A9
  87#define	LD_RQPN					0x00AB
  88#define	RXFF_BNDY				0x00AC
  89#define	RXRPT_BNDY				0x00B0
  90#define	TXPKTBUF_PGBNDY				0x00B4
  91#define	PBP					0x00B5
  92#define	RXDRVINFO_SZ				0x00B6
  93#define	TXFF_STATUS				0x00B7
  94#define	RXFF_STATUS				0x00B8
  95#define	TXFF_EMPTY_TH				0x00B9
  96#define	SDIO_RX_BLKSZ				0x00BC
  97#define	RXDMA					0x00BD
  98#define	RXPKT_NUM				0x00BE
  99#define	C2HCMD_UDT_SIZE				0x00C0
 100#define	C2HCMD_UDT_ADDR				0x00C2
 101#define	FIFOPAGE1				0x00C4
 102#define	FIFOPAGE2				0x00C8
 103#define	FIFOPAGE3				0x00CC
 104#define	FIFOPAGE4				0x00D0
 105#define	FIFOPAGE5				0x00D4
 106#define	FW_RSVD_PG_CRTL				0x00D8
 107#define	RXDMA_AGG_PG_TH				0x00D9
 108#define	TXDESC_MSK				0x00DC
 109#define	TXRPTFF_RDPTR				0x00E0
 110#define	TXRPTFF_WTPTR				0x00E4
 111#define	C2HFF_RDPTR				0x00E8
 112#define	C2HFF_WTPTR				0x00EC
 113#define	RXFF0_RDPTR				0x00F0
 114#define	RXFF0_WTPTR				0x00F4
 115#define	RXFF1_RDPTR				0x00F8
 116#define	RXFF1_WTPTR				0x00FC
 117#define	RXRPT0_RDPTR				0x0100
 118#define	RXRPT0_WTPTR				0x0104
 119#define	RXRPT1_RDPTR				0x0108
 120#define	RXRPT1_WTPTR				0x010C
 121#define	RX0_UDT_SIZE				0x0110
 122#define	RX1PKTNUM				0x0114
 123#define	RXFILTERMAP				0x0116
 124#define	RXFILTERMAP_GP1				0x0118
 125#define	RXFILTERMAP_GP2				0x011A
 126#define	RXFILTERMAP_GP3				0x011C
 127#define	BCNQ_CTRL				0x0120
 128#define	MGTQ_CTRL				0x0124
 129#define	HIQ_CTRL				0x0128
 130#define	VOTID7_CTRL				0x012c
 131#define	VOTID6_CTRL				0x0130
 132#define	VITID5_CTRL				0x0134
 133#define	VITID4_CTRL				0x0138
 134#define	BETID3_CTRL				0x013c
 135#define	BETID0_CTRL				0x0140
 136#define	BKTID2_CTRL				0x0144
 137#define	BKTID1_CTRL				0x0148
 138#define	CMDQ_CTRL				0x014c
 139#define	TXPKT_NUM_CTRL				0x0150
 140#define	TXQ_PGADD				0x0152
 141#define	TXFF_PG_NUM				0x0154
 142#define	TRXDMA_STATUS				0x0156
 143
 144/* 6. Adaptive Control Registers   */
 145#define	INIMCS_SEL				0x0160
 146#define	TX_RATE_REG				INIMCS_SEL
 147#define	INIRTSMCS_SEL				0x0180
 148#define	RRSR					0x0181
 149#define	ARFR0					0x0184
 150#define	ARFR1					0x0188
 151#define	ARFR2					0x018C
 152#define	ARFR3					0x0190
 153#define	ARFR4					0x0194
 154#define	ARFR5					0x0198
 155#define	ARFR6					0x019C
 156#define	ARFR7					0x01A0
 157#define	AGGLEN_LMT_H				0x01A7
 158#define	AGGLEN_LMT_L				0x01A8
 159#define	DARFRC					0x01B0
 160#define	RARFRC					0x01B8
 161#define	MCS_TXAGC				0x01C0
 162#define	CCK_TXAGC				0x01C8
 163
 164/* 7. EDCA Setting Registers */
 165#define	EDCAPARA_VO				0x01D0
 166#define	EDCAPARA_VI				0x01D4
 167#define	EDCAPARA_BE				0x01D8
 168#define	EDCAPARA_BK				0x01DC
 169#define	BCNTCFG					0x01E0
 170#define	CWRR					0x01E2
 171#define	ACMAVG					0x01E4
 172#define	ACMHWCTRL				0x01E7
 173#define	VO_ADMTM				0x01E8
 174#define	VI_ADMTM				0x01EC
 175#define	BE_ADMTM				0x01F0
 176#define	RETRY_LIMIT				0x01F4
 177#define	SG_RATE					0x01F6
 178
 179/* 8. WMAC, BA and CCX related Register. */
 180#define	NAV_CTRL				0x0200
 181#define	BW_OPMODE				0x0203
 182#define	BACAMCMD				0x0204
 183#define	BACAMCONTENT				0x0208
 184
 185/* the 0x2xx register WMAC definition */
 186#define	LBDLY					0x0210
 187#define	FWDLY					0x0211
 188#define	HWPC_RX_CTRL				0x0218
 189#define	MQIR					0x0220
 190#define	MAIR					0x0222
 191#define	MSIR					0x0224
 192#define	CLM_RESULT				0x0227
 193#define	NHM_RPI_CNT				0x0228
 194#define	RXERR_RPT				0x0230
 195#define	NAV_PROT_LEN				0x0234
 196#define	CFEND_TH				0x0236
 197#define	AMPDU_MIN_SPACE				0x0237
 198#define	TXOP_STALL_CTRL				0x0238
 199
 200/* 9. Security Control Registers */
 201#define	REG_RWCAM				0x0240
 202#define	REG_WCAMI				0x0244
 203#define	REG_RCAMO				0x0248
 204#define	REG_CAMDBG				0x024C
 205#define	REG_SECR				0x0250
 206
 207/* 10. Power Save Control Registers */
 208#define	WOW_CTRL				0x0260
 209#define	PSSTATUS				0x0261
 210#define	PSSWITCH				0x0262
 211#define	MIMOPS_WAIT_PERIOD			0x0263
 212#define	LPNAV_CTRL				0x0264
 213#define	WFM0					0x0270
 214#define	WFM1					0x0280
 215#define	WFM2					0x0290
 216#define	WFM3					0x02A0
 217#define	WFM4					0x02B0
 218#define	WFM5					0x02C0
 219#define	WFCRC					0x02D0
 220#define	FW_RPT_REG				0x02c4
 221
 222/* 11. General Purpose Registers */
 223#define	PSTIME					0x02E0
 224#define	TIMER0					0x02E4
 225#define	TIMER1					0x02E8
 226#define	GPIO_IN_SE				0x02EC
 227#define	GPIO_IO_SEL				0x02EE
 228#define	MAC_PINMUX_CFG				0x02F1
 229#define	LEDCFG					0x02F2
 230#define	PHY_REG					0x02F3
 231#define	PHY_REG_DATA				0x02F4
 232#define	REG_EFUSE_CLK				0x02F8
 233
 234/* 12. Host Interrupt Status Registers */
 235#define	INTA_MASK				0x0300
 236#define	ISR					0x0308
 237
 238/* 13. Test mode and Debug Control Registers */
 239#define	DBG_PORT_SWITCH				0x003A
 240#define	BIST					0x0310
 241#define	DBS					0x0314
 242#define	CPUINST					0x0318
 243#define	CPUCAUSE				0x031C
 244#define	LBUS_ERR_ADDR				0x0320
 245#define	LBUS_ERR_CMD				0x0324
 246#define	LBUS_ERR_DATA_L				0x0328
 247#define	LBUS_ERR_DATA_H				0x032C
 248#define	LX_EXCEPTION_ADDR			0x0330
 249#define	WDG_CTRL				0x0334
 250#define	INTMTU					0x0338
 251#define	INTM					0x033A
 252#define	FDLOCKTURN0				0x033C
 253#define	FDLOCKTURN1				0x033D
 254#define	TRXPKTBUF_DBG_DATA			0x0340
 255#define	TRXPKTBUF_DBG_CTRL			0x0348
 256#define	DPLL					0x034A
 257#define	CBUS_ERR_ADDR				0x0350
 258#define	CBUS_ERR_CMD				0x0354
 259#define	CBUS_ERR_DATA_L				0x0358
 260#define	CBUS_ERR_DATA_H				0x035C
 261#define	USB_SIE_INTF_ADDR			0x0360
 262#define	USB_SIE_INTF_WD				0x0361
 263#define	USB_SIE_INTF_RD				0x0362
 264#define	USB_SIE_INTF_CTRL			0x0363
 265#define LBUS_MON_ADDR				0x0364
 266#define LBUS_ADDR_MASK				0x0368
 267
 268/* Boundary is 0x37F */
 269
 270/* 14. PCIE config register */
 271#define	TP_POLL					0x0500
 272#define	PM_CTRL					0x0502
 273#define	PCIF					0x0503
 274
 275#define	THPDA					0x0514
 276#define	TMDA					0x0518
 277#define	TCDA					0x051C
 278#define	HDA					0x0520
 279#define	TVODA					0x0524
 280#define	TVIDA					0x0528
 281#define	TBEDA					0x052C
 282#define	TBKDA					0x0530
 283#define	TBDA					0x0534
 284#define	RCDA					0x0538
 285#define	RDQDA					0x053C
 286#define	DBI_WDATA				0x0540
 287#define	DBI_RDATA				0x0544
 288#define	DBI_CTRL				0x0548
 289#define	MDIO_DATA				0x0550
 290#define	MDIO_CTRL				0x0554
 291#define	PCI_RPWM				0x0561
 292#define	PCI_CPWM				0x0563
 293
 294/* Config register	(Offset 0x800-) */
 295#define	PHY_CCA					0x803
 296
 297/* Min Spacing related settings. */
 298#define	MAX_MSS_DENSITY_2T			0x13
 299#define	MAX_MSS_DENSITY_1T			0x0A
 300
 301/* Rx DMA Control related settings */
 302#define	RXDMA_AGG_EN				BIT(7)
 303
 304#define	RPWM					PCI_RPWM
 305
 306/* Regsiter Bit and Content definition  */
 307
 308#define	ISO_MD2PP				BIT(0)
 309#define	ISO_PA2PCIE				BIT(3)
 310#define	ISO_PLL2MD				BIT(4)
 311#define	ISO_PWC_DV2RP				BIT(11)
 312#define	ISO_PWC_RV2RP				BIT(12)
 313
 314
 315#define	FEN_MREGEN				BIT(15)
 316#define	FEN_DCORE				BIT(11)
 317#define	FEN_CPUEN				BIT(10)
 318
 319#define	PAD_HWPD_IDN				BIT(22)
 320
 321#define	SYS_CLKSEL_80M				BIT(0)
 322#define	SYS_PS_CLKSEL				BIT(1)
 323#define	SYS_CPU_CLKSEL				BIT(2)
 324#define	SYS_MAC_CLK_EN				BIT(11)
 325#define	SYS_SWHW_SEL				BIT(14)
 326#define	SYS_FWHW_SEL				BIT(15)
 327
 328#define	CMDEEPROM_EN				BIT(5)
 329#define	CMDEERPOMSEL				BIT(4)
 330#define	CMD9346CR_9356SEL			BIT(4)
 331
 332#define	AFE_MBEN				BIT(1)
 333#define	AFE_BGEN				BIT(0)
 334
 335#define	SPS1_SWEN				BIT(1)
 336#define	SPS1_LDEN				BIT(0)
 337
 338#define	RF_EN					BIT(0)
 339#define	RF_RSTB					BIT(1)
 340#define	RF_SDMRSTB				BIT(2)
 341
 342#define	LDA15_EN				BIT(0)
 343
 344#define	LDV12_EN				BIT(0)
 345#define	LDV12_SDBY				BIT(1)
 346
 347#define	XTAL_GATE_AFE				BIT(10)
 348
 349#define	APLL_EN					BIT(0)
 350
 351#define	AFR_CARDBEN				BIT(0)
 352#define	AFR_CLKRUN_SEL				BIT(1)
 353#define	AFR_FUNCREGEN				BIT(2)
 354
 355#define	APSDOFF_STATUS				BIT(15)
 356#define	APSDOFF					BIT(14)
 357#define	BBRSTN					BIT(13)
 358#define	BB_GLB_RSTN				BIT(12)
 359#define	SCHEDULE_EN				BIT(10)
 360#define	MACRXEN					BIT(9)
 361#define	MACTXEN					BIT(8)
 362#define	DDMA_EN					BIT(7)
 363#define	FW2HW_EN				BIT(6)
 364#define	RXDMA_EN				BIT(5)
 365#define	TXDMA_EN				BIT(4)
 366#define	HCI_RXDMA_EN				BIT(3)
 367#define	HCI_TXDMA_EN				BIT(2)
 368
 369#define	STOPHCCA				BIT(6)
 370#define	STOPHIGH				BIT(5)
 371#define	STOPMGT					BIT(4)
 372#define	STOPVO					BIT(3)
 373#define	STOPVI					BIT(2)
 374#define	STOPBE					BIT(1)
 375#define	STOPBK					BIT(0)
 376
 377#define	LBK_NORMAL				0x00
 378#define	LBK_MAC_LB				(BIT(0) | BIT(1) | BIT(3))
 379#define	LBK_MAC_DLB				(BIT(0) | BIT(1))
 380#define	LBK_DMA_LB				(BIT(0) | BIT(1) | BIT(2))
 381
 382#define	TCP_OFDL_EN				BIT(25)
 383#define	HWPC_TX_EN				BIT(24)
 384#define	TXDMAPRE2FULL				BIT(23)
 385#define	DISCW					BIT(20)
 386#define	TCRICV					BIT(19)
 387#define	cfendform				BIT(17)
 388#define	TCRCRC					BIT(16)
 389#define	FAKE_IMEM_EN				BIT(15)
 390#define	TSFRST					BIT(9)
 391#define	TSFEN					BIT(8)
 392#define	FWALLRDY				(BIT(0) | BIT(1) | BIT(2) | \
 393						BIT(3) | BIT(4) | BIT(5) | \
 394						BIT(6) | BIT(7))
 395#define	FWRDY					BIT(7)
 396#define	BASECHG					BIT(6)
 397#define	IMEM					BIT(5)
 398#define	DMEM_CODE_DONE				BIT(4)
 399#define	EXT_IMEM_CHK_RPT			BIT(3)
 400#define	EXT_IMEM_CODE_DONE			BIT(2)
 401#define	IMEM_CHK_RPT				BIT(1)
 402#define	IMEM_CODE_DONE				BIT(0)
 403#define	EMEM_CODE_DONE				BIT(2)
 404#define	EMEM_CHK_RPT				BIT(3)
 405#define	IMEM_RDY				BIT(5)
 406#define	LOAD_FW_READY				(IMEM_CODE_DONE | \
 407						IMEM_CHK_RPT | \
 408						EMEM_CODE_DONE | \
 409						EMEM_CHK_RPT | \
 410						DMEM_CODE_DONE | \
 411						IMEM_RDY | \
 412						BASECHG | \
 413						FWRDY)
 414#define	TCR_TSFEN				BIT(8)
 415#define	TCR_TSFRST				BIT(9)
 416#define	TCR_FAKE_IMEM_EN			BIT(15)
 417#define	TCR_CRC					BIT(16)
 418#define	TCR_ICV					BIT(19)
 419#define	TCR_DISCW				BIT(20)
 420#define	TCR_HWPC_TX_EN				BIT(24)
 421#define	TCR_TCP_OFDL_EN				BIT(25)
 422#define	TXDMA_INIT_VALUE			(IMEM_CHK_RPT | \
 423						EXT_IMEM_CHK_RPT)
 424
 425#define	RCR_APPFCS				BIT(31)
 426#define	RCR_DIS_ENC_2BYTE			BIT(30)
 427#define	RCR_DIS_AES_2BYTE			BIT(29)
 428#define	RCR_HTC_LOC_CTRL			BIT(28)
 429#define	RCR_ENMBID				BIT(27)
 430#define	RCR_RX_TCPOFDL_EN			BIT(26)
 431#define	RCR_APP_PHYST_RXFF			BIT(25)
 432#define	RCR_APP_PHYST_STAFF			BIT(24)
 433#define	RCR_CBSSID				BIT(23)
 434#define	RCR_APWRMGT				BIT(22)
 435#define	RCR_ADD3				BIT(21)
 436#define	RCR_AMF					BIT(20)
 437#define	RCR_ACF					BIT(19)
 438#define	RCR_ADF					BIT(18)
 439#define	RCR_APP_MIC				BIT(17)
 440#define	RCR_APP_ICV				BIT(16)
 441#define	RCR_RXFTH				BIT(13)
 442#define	RCR_AICV				BIT(12)
 443#define	RCR_RXDESC_LK_EN			BIT(11)
 444#define	RCR_APP_BA_SSN				BIT(6)
 445#define	RCR_ACRC32				BIT(5)
 446#define	RCR_RXSHFT_EN				BIT(4)
 447#define	RCR_AB					BIT(3)
 448#define	RCR_AM					BIT(2)
 449#define	RCR_APM					BIT(1)
 450#define	RCR_AAP					BIT(0)
 451#define	RCR_MXDMA_OFFSET			8
 452#define	RCR_FIFO_OFFSET				13
 453
 454
 455#define MSR_LINK_MASK				((1 << 0) | (1 << 1))
 456#define MSR_LINK_MANAGED			2
 457#define MSR_LINK_NONE				0
 458#define MSR_LINK_SHIFT				0
 459#define MSR_LINK_ADHOC				1
 460#define MSR_LINK_MASTER				3
 461#define	MSR_NOLINK				0x00
 462#define	MSR_ADHOC				0x01
 463#define	MSR_INFRA				0x02
 464#define	MSR_AP					0x03
 465
 466#define	ENUART					BIT(7)
 467#define	ENJTAG					BIT(3)
 468#define	BTMODE					(BIT(2) | BIT(1))
 469#define	ENBT					BIT(0)
 470
 471#define	ENMBID					BIT(7)
 472#define	BCNUM					(BIT(6) | BIT(5) | BIT(4))
 473
 474#define	USTIME_EDCA				0xFF00
 475#define	USTIME_TSF				0x00FF
 476
 477#define	SIFS_TRX				0xFF00
 478#define	SIFS_CTX				0x00FF
 479
 480#define	ENSWBCN					BIT(15)
 481#define	DRVERLY_TU				0x0FF0
 482#define	DRVERLY_US				0x000F
 483#define	BCN_TCFG_CW_SHIFT			8
 484#define	BCN_TCFG_IFS				0
 485
 486#define	RRSR_RSC_OFFSET				21
 487#define	RRSR_SHORT_OFFSET			23
 488#define	RRSR_RSC_BW_40M				0x600000
 489#define	RRSR_RSC_UPSUBCHNL			0x400000
 490#define	RRSR_RSC_LOWSUBCHNL			0x200000
 491#define	RRSR_SHORT				0x800000
 492#define	RRSR_1M					BIT(0)
 493#define	RRSR_2M					BIT(1)
 494#define	RRSR_5_5M				BIT(2)
 495#define	RRSR_11M				BIT(3)
 496#define	RRSR_6M					BIT(4)
 497#define	RRSR_9M					BIT(5)
 498#define	RRSR_12M				BIT(6)
 499#define	RRSR_18M				BIT(7)
 500#define	RRSR_24M				BIT(8)
 501#define	RRSR_36M				BIT(9)
 502#define	RRSR_48M				BIT(10)
 503#define	RRSR_54M				BIT(11)
 504#define	RRSR_MCS0				BIT(12)
 505#define	RRSR_MCS1				BIT(13)
 506#define	RRSR_MCS2				BIT(14)
 507#define	RRSR_MCS3				BIT(15)
 508#define	RRSR_MCS4				BIT(16)
 509#define	RRSR_MCS5				BIT(17)
 510#define	RRSR_MCS6				BIT(18)
 511#define	RRSR_MCS7				BIT(19)
 512#define	BRSR_ACKSHORTPMB			BIT(23)
 513
 514#define	RATR_1M					0x00000001
 515#define	RATR_2M					0x00000002
 516#define	RATR_55M				0x00000004
 517#define	RATR_11M				0x00000008
 518#define	RATR_6M					0x00000010
 519#define	RATR_9M					0x00000020
 520#define	RATR_12M				0x00000040
 521#define	RATR_18M				0x00000080
 522#define	RATR_24M				0x00000100
 523#define	RATR_36M				0x00000200
 524#define	RATR_48M				0x00000400
 525#define	RATR_54M				0x00000800
 526#define	RATR_MCS0				0x00001000
 527#define	RATR_MCS1				0x00002000
 528#define	RATR_MCS2				0x00004000
 529#define	RATR_MCS3				0x00008000
 530#define	RATR_MCS4				0x00010000
 531#define	RATR_MCS5				0x00020000
 532#define	RATR_MCS6				0x00040000
 533#define	RATR_MCS7				0x00080000
 534#define	RATR_MCS8				0x00100000
 535#define	RATR_MCS9				0x00200000
 536#define	RATR_MCS10				0x00400000
 537#define	RATR_MCS11				0x00800000
 538#define	RATR_MCS12				0x01000000
 539#define	RATR_MCS13				0x02000000
 540#define	RATR_MCS14				0x04000000
 541#define	RATR_MCS15				0x08000000
 542
 543#define	RATE_ALL_CCK				(RATR_1M | RATR_2M | \
 544						RATR_55M | RATR_11M)
 545#define	RATE_ALL_OFDM_AG			(RATR_6M | RATR_9M | \
 546						RATR_12M | RATR_18M | \
 547						RATR_24M | RATR_36M | \
 548						RATR_48M | RATR_54M)
 549#define	RATE_ALL_OFDM_1SS			(RATR_MCS0 | RATR_MCS1 | \
 550						RATR_MCS2 | RATR_MCS3 | \
 551						RATR_MCS4 | RATR_MCS5 | \
 552						RATR_MCS6 | RATR_MCS7)
 553#define	RATE_ALL_OFDM_2SS			(RATR_MCS8 | RATR_MCS9 | \
 554						RATR_MCS10 | RATR_MCS11 | \
 555						RATR_MCS12 | RATR_MCS13 | \
 556						RATR_MCS14 | RATR_MCS15)
 557
 558#define	AC_PARAM_TXOP_LIMIT_OFFSET		16
 559#define	AC_PARAM_ECW_MAX_OFFSET			12
 560#define	AC_PARAM_ECW_MIN_OFFSET			8
 561#define	AC_PARAM_AIFS_OFFSET			0
 562
 563#define	ACMHW_HWEN				BIT(0)
 564#define	ACMHW_BEQEN				BIT(1)
 565#define	ACMHW_VIQEN				BIT(2)
 566#define	ACMHW_VOQEN				BIT(3)
 567#define	ACMHW_BEQSTATUS				BIT(4)
 568#define	ACMHW_VIQSTATUS				BIT(5)
 569#define	ACMHW_VOQSTATUS				BIT(6)
 570
 571#define	RETRY_LIMIT_SHORT_SHIFT			8
 572#define	RETRY_LIMIT_LONG_SHIFT			0
 573
 574#define	NAV_UPPER_EN				BIT(16)
 575#define	NAV_UPPER				0xFF00
 576#define	NAV_RTSRST				0xFF
 577
 578#define	BW_OPMODE_20MHZ				BIT(2)
 579#define	BW_OPMODE_5G				BIT(1)
 580#define	BW_OPMODE_11J				BIT(0)
 581
 582#define	RXERR_RPT_RST				BIT(27)
 583#define	RXERR_OFDM_PPDU				0
 584#define	RXERR_OFDM_FALSE_ALARM			1
 585#define	RXERR_OFDM_MPDU_OK			2
 586#define	RXERR_OFDM_MPDU_FAIL			3
 587#define	RXERR_CCK_PPDU				4
 588#define	RXERR_CCK_FALSE_ALARM			5
 589#define	RXERR_CCK_MPDU_OK			6
 590#define	RXERR_CCK_MPDU_FAIL			7
 591#define	RXERR_HT_PPDU				8
 592#define	RXERR_HT_FALSE_ALARM			9
 593#define	RXERR_HT_MPDU_TOTAL			10
 594#define	RXERR_HT_MPDU_OK			11
 595#define	RXERR_HT_MPDU_FAIL			12
 596#define	RXERR_RX_FULL_DROP			15
 597
 598#define	SCR_TXUSEDK				BIT(0)
 599#define	SCR_RXUSEDK				BIT(1)
 600#define	SCR_TXENCENABLE				BIT(2)
 601#define	SCR_RXENCENABLE				BIT(3)
 602#define	SCR_SKBYA2				BIT(4)
 603#define	SCR_NOSKMC				BIT(5)
 604
 605#define	CAM_VALID				BIT(15)
 606#define	CAM_NOTVALID				0x0000
 607#define	CAM_USEDK				BIT(5)
 608
 609#define	CAM_NONE				0x0
 610#define	CAM_WEP40				0x01
 611#define	CAM_TKIP				0x02
 612#define	CAM_AES					0x04
 613#define	CAM_WEP104				0x05
 614
 615#define	TOTAL_CAM_ENTRY				32
 616#define	HALF_CAM_ENTRY				16
 617
 618#define	CAM_WRITE				BIT(16)
 619#define	CAM_READ				0x00000000
 620#define	CAM_POLLINIG				BIT(31)
 621
 622#define	WOW_PMEN				BIT(0)
 623#define	WOW_WOMEN				BIT(1)
 624#define	WOW_MAGIC				BIT(2)
 625#define	WOW_UWF					BIT(3)
 626
 627#define	GPIOMUX_EN				BIT(3)
 628#define	GPIOSEL_GPIO				0
 629#define	GPIOSEL_PHYDBG				1
 630#define	GPIOSEL_BT				2
 631#define	GPIOSEL_WLANDBG				3
 632#define	GPIOSEL_GPIO_MASK			(~(BIT(0)|BIT(1)))
 633
 634#define	HST_RDBUSY				BIT(0)
 635#define	CPU_WTBUSY				BIT(1)
 636
 637#define	IMR8190_DISABLED			0x0
 638#define	IMR_CPUERR				BIT(5)
 639#define	IMR_ATIMEND				BIT(4)
 640#define	IMR_TBDOK				BIT(3)
 641#define	IMR_TBDER				BIT(2)
 642#define	IMR_BCNDMAINT8				BIT(1)
 643#define	IMR_BCNDMAINT7				BIT(0)
 644#define	IMR_BCNDMAINT6				BIT(31)
 645#define	IMR_BCNDMAINT5				BIT(30)
 646#define	IMR_BCNDMAINT4				BIT(29)
 647#define	IMR_BCNDMAINT3				BIT(28)
 648#define	IMR_BCNDMAINT2				BIT(27)
 649#define	IMR_BCNDMAINT1				BIT(26)
 650#define	IMR_BCNDOK8				BIT(25)
 651#define	IMR_BCNDOK7				BIT(24)
 652#define	IMR_BCNDOK6				BIT(23)
 653#define	IMR_BCNDOK5				BIT(22)
 654#define	IMR_BCNDOK4				BIT(21)
 655#define	IMR_BCNDOK3				BIT(20)
 656#define	IMR_BCNDOK2				BIT(19)
 657#define	IMR_BCNDOK1				BIT(18)
 658#define	IMR_TIMEOUT2				BIT(17)
 659#define	IMR_TIMEOUT1				BIT(16)
 660#define	IMR_TXFOVW				BIT(15)
 661#define	IMR_PSTIMEOUT				BIT(14)
 662#define	IMR_BCNINT				BIT(13)
 663#define	IMR_RXFOVW				BIT(12)
 664#define	IMR_RDU					BIT(11)
 665#define	IMR_RXCMDOK				BIT(10)
 666#define	IMR_BDOK				BIT(9)
 667#define	IMR_HIGHDOK				BIT(8)
 668#define	IMR_COMDOK				BIT(7)
 669#define	IMR_MGNTDOK				BIT(6)
 670#define	IMR_HCCADOK				BIT(5)
 671#define	IMR_BKDOK				BIT(4)
 672#define	IMR_BEDOK				BIT(3)
 673#define	IMR_VIDOK				BIT(2)
 674#define	IMR_VODOK				BIT(1)
 675#define	IMR_ROK					BIT(0)
 676
 677#define	TPPOLL_BKQ				BIT(0)
 678#define	TPPOLL_BEQ				BIT(1)
 679#define	TPPOLL_VIQ				BIT(2)
 680#define	TPPOLL_VOQ				BIT(3)
 681#define	TPPOLL_BQ				BIT(4)
 682#define	TPPOLL_CQ				BIT(5)
 683#define	TPPOLL_MQ				BIT(6)
 684#define	TPPOLL_HQ				BIT(7)
 685#define	TPPOLL_HCCAQ				BIT(8)
 686#define	TPPOLL_STOPBK				BIT(9)
 687#define	TPPOLL_STOPBE				BIT(10)
 688#define	TPPOLL_STOPVI				BIT(11)
 689#define	TPPOLL_STOPVO				BIT(12)
 690#define	TPPOLL_STOPMGT				BIT(13)
 691#define	TPPOLL_STOPHIGH				BIT(14)
 692#define	TPPOLL_STOPHCCA				BIT(15)
 693#define	TPPOLL_SHIFT				8
 694
 695#define	CCX_CMD_CLM_ENABLE			BIT(0)
 696#define	CCX_CMD_NHM_ENABLE			BIT(1)
 697#define	CCX_CMD_FUNCTION_ENABLE			BIT(8)
 698#define	CCX_CMD_IGNORE_CCA			BIT(9)
 699#define	CCX_CMD_IGNORE_TXON			BIT(10)
 700#define	CCX_CLM_RESULT_READY			BIT(16)
 701#define	CCX_NHM_RESULT_READY			BIT(16)
 702#define	CCX_CMD_RESET				0x0
 703
 704
 705#define	HWSET_MAX_SIZE_92S			128
 706#define EFUSE_MAX_SECTION			16
 707#define EFUSE_REAL_CONTENT_LEN			512
 708#define EFUSE_OOB_PROTECT_BYTES			15
 709
 710#define RTL8190_EEPROM_ID			0x8129
 711#define EEPROM_HPON				0x02
 712#define EEPROM_CLK				0x06
 713#define EEPROM_TESTR				0x08
 714
 715#define EEPROM_VID				0x0A
 716#define EEPROM_DID				0x0C
 717#define EEPROM_SVID				0x0E
 718#define EEPROM_SMID				0x10
 719
 720#define EEPROM_MAC_ADDR				0x12
 721#define EEPROM_NODE_ADDRESS_BYTE_0		0x12
 722
 723#define EEPROM_PWDIFF				0x54
 724
 725#define EEPROM_TXPOWERBASE			0x50
 726#define	EEPROM_TX_PWR_INDEX_RANGE		28
 727
 728#define EEPROM_TX_PWR_HT20_DIFF			0x62
 729#define DEFAULT_HT20_TXPWR_DIFF			2
 730#define EEPROM_TX_PWR_OFDM_DIFF			0x65
 731
 732#define	EEPROM_TXPWRGROUP			0x67
 733#define EEPROM_REGULATORY			0x6D
 734
 735#define TX_PWR_SAFETY_CHK			0x6D
 736#define EEPROM_TXPWINDEX_CCK_24G		0x5D
 737#define EEPROM_TXPWINDEX_OFDM_24G		0x6B
 738#define EEPROM_HT2T_CH1_A			0x6c
 739#define EEPROM_HT2T_CH7_A			0x6d
 740#define EEPROM_HT2T_CH13_A			0x6e
 741#define EEPROM_HT2T_CH1_B			0x6f
 742#define EEPROM_HT2T_CH7_B			0x70
 743#define EEPROM_HT2T_CH13_B			0x71
 744
 745#define EEPROM_TSSI_A				0x74
 746#define EEPROM_TSSI_B				0x75
 747
 748#define	EEPROM_RFIND_POWERDIFF			0x76
 749#define	EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF	0x3
 750
 751#define EEPROM_THERMALMETER			0x77
 752#define	EEPROM_BLUETOOTH_COEXIST		0x78
 753#define	EEPROM_BLUETOOTH_TYPE			0x4f
 754
 755#define	EEPROM_OPTIONAL				0x78
 756#define	EEPROM_WOWLAN				0x78
 757
 758#define EEPROM_CRYSTALCAP			0x79
 759#define EEPROM_CHANNELPLAN			0x7B
 760#define EEPROM_VERSION				0x7C
 761#define	EEPROM_CUSTOMID				0x7A
 762#define EEPROM_BOARDTYPE			0x7E
 763
 764#define	EEPROM_CHANNEL_PLAN_FCC			0x0
 765#define	EEPROM_CHANNEL_PLAN_IC			0x1
 766#define	EEPROM_CHANNEL_PLAN_ETSI		0x2
 767#define	EEPROM_CHANNEL_PLAN_SPAIN		0x3
 768#define	EEPROM_CHANNEL_PLAN_FRANCE		0x4
 769#define	EEPROM_CHANNEL_PLAN_MKK			0x5
 770#define	EEPROM_CHANNEL_PLAN_MKK1		0x6
 771#define	EEPROM_CHANNEL_PLAN_ISRAEL		0x7
 772#define	EEPROM_CHANNEL_PLAN_TELEC		0x8
 773#define	EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN	0x9
 774#define	EEPROM_CHANNEL_PLAN_WORLD_WIDE_13	0xA
 775#define	EEPROM_CHANNEL_PLAN_NCC			0xB
 776#define	EEPROM_CHANNEL_PLAN_BY_HW_MASK		0x80
 777
 778#define	FW_DIG_DISABLE				0xfd00cc00
 779#define	FW_DIG_ENABLE				0xfd000000
 780#define	FW_DIG_HALT				0xfd000001
 781#define	FW_DIG_RESUME				0xfd000002
 782#define	FW_HIGH_PWR_DISABLE			0xfd000008
 783#define	FW_HIGH_PWR_ENABLE			0xfd000009
 784#define	FW_ADD_A2_ENTRY				0xfd000016
 785#define	FW_TXPWR_TRACK_ENABLE			0xfd000017
 786#define	FW_TXPWR_TRACK_DISABLE			0xfd000018
 787#define	FW_TXPWR_TRACK_THERMAL			0xfd000019
 788#define	FW_TXANT_SWITCH_ENABLE			0xfd000023
 789#define	FW_TXANT_SWITCH_DISABLE			0xfd000024
 790#define	FW_RA_INIT				0xfd000026
 791#define	FW_CTRL_DM_BY_DRIVER			0Xfd00002a
 792#define	FW_RA_IOT_BG_COMB			0xfd000030
 793#define	FW_RA_IOT_N_COMB			0xfd000031
 794#define	FW_RA_REFRESH				0xfd0000a0
 795#define	FW_RA_UPDATE_MASK			0xfd0000a2
 796#define	FW_RA_DISABLE				0xfd0000a4
 797#define	FW_RA_ACTIVE				0xfd0000a6
 798#define	FW_RA_DISABLE_RSSI_MASK			0xfd0000ac
 799#define	FW_RA_ENABLE_RSSI_MASK			0xfd0000ad
 800#define	FW_RA_RESET				0xfd0000af
 801#define	FW_DM_DISABLE				0xfd00aa00
 802#define	FW_IQK_ENABLE				0xf0000020
 803#define	FW_IQK_SUCCESS				0x0000dddd
 804#define	FW_IQK_FAIL				0x0000ffff
 805#define	FW_OP_FAILURE				0xffffffff
 806#define	FW_TX_FEEDBACK_NONE			0xfb000000
 807#define	FW_TX_FEEDBACK_DTM_ENABLE		(FW_TX_FEEDBACK_NONE | 0x1)
 808#define	FW_TX_FEEDBACK_CCX_ENABL		(FW_TX_FEEDBACK_NONE | 0x2)
 809#define	FW_BB_RESET_ENABLE			0xff00000d
 810#define	FW_BB_RESET_DISABLE			0xff00000e
 811#define	FW_CCA_CHK_ENABLE			0xff000011
 812#define	FW_CCK_RESET_CNT			0xff000013
 813#define	FW_LPS_ENTER				0xfe000010
 814#define	FW_LPS_LEAVE				0xfe000011
 815#define	FW_INDIRECT_READ			0xf2000000
 816#define	FW_INDIRECT_WRITE			0xf2000001
 817#define	FW_CHAN_SET				0xf3000001
 818
 819#define RFPC					0x5F
 820#define RCR_9356SEL				BIT(6)
 821#define TCR_LRL_OFFSET				0
 822#define TCR_SRL_OFFSET				8
 823#define TCR_MXDMA_OFFSET			21
 824#define TCR_SAT					BIT(24)
 825#define RCR_MXDMA_OFFSET			8
 826#define RCR_FIFO_OFFSET				13
 827#define RCR_ONLYERLPKT				BIT(31)
 828#define CWR					0xDC
 829#define RETRYCTR				0xDE
 830
 831#define CPU_GEN_SYSTEM_RESET			0x00000001
 832
 833#define	CCX_COMMAND_REG				0x890
 834#define	CLM_PERIOD_REG				0x894
 835#define	NHM_PERIOD_REG				0x896
 836
 837#define	NHM_THRESHOLD0				0x898
 838#define	NHM_THRESHOLD1				0x899
 839#define	NHM_THRESHOLD2				0x89A
 840#define	NHM_THRESHOLD3				0x89B
 841#define	NHM_THRESHOLD4				0x89C
 842#define	NHM_THRESHOLD5				0x89D
 843#define	NHM_THRESHOLD6				0x89E
 844#define	CLM_RESULT_REG				0x8D0
 845#define	NHM_RESULT_REG				0x8D4
 846#define	NHM_RPI_COUNTER0			0x8D8
 847#define	NHM_RPI_COUNTER1			0x8D9
 848#define	NHM_RPI_COUNTER2			0x8DA
 849#define	NHM_RPI_COUNTER3			0x8DB
 850#define	NHM_RPI_COUNTER4			0x8DC
 851#define	NHM_RPI_COUNTER5			0x8DD
 852#define	NHM_RPI_COUNTER6			0x8DE
 853#define	NHM_RPI_COUNTER7			0x8DF
 854
 855#define	HAL_8192S_HW_GPIO_OFF_BIT		BIT(3)
 856#define	HAL_8192S_HW_GPIO_OFF_MASK		0xF7
 857#define	HAL_8192S_HW_GPIO_WPS_BIT		BIT(4)
 858
 859#define	RPMAC_RESET				0x100
 860#define	RPMAC_TXSTART				0x104
 861#define	RPMAC_TXLEGACYSIG			0x108
 862#define	RPMAC_TXHTSIG1				0x10c
 863#define	RPMAC_TXHTSIG2				0x110
 864#define	RPMAC_PHYDEBUG				0x114
 865#define	RPMAC_TXPACKETNNM			0x118
 866#define	RPMAC_TXIDLE				0x11c
 867#define	RPMAC_TXMACHEADER0			0x120
 868#define	RPMAC_TXMACHEADER1			0x124
 869#define	RPMAC_TXMACHEADER2			0x128
 870#define	RPMAC_TXMACHEADER3			0x12c
 871#define	RPMAC_TXMACHEADER4			0x130
 872#define	RPMAC_TXMACHEADER5			0x134
 873#define	RPMAC_TXDATATYPE			0x138
 874#define	RPMAC_TXRANDOMSEED			0x13c
 875#define	RPMAC_CCKPLCPPREAMBLE			0x140
 876#define	RPMAC_CCKPLCPHEADER			0x144
 877#define	RPMAC_CCKCRC16				0x148
 878#define	RPMAC_OFDMRXCRC32OK			0x170
 879#define	RPMAC_OFDMRXCRC32ER			0x174
 880#define	RPMAC_OFDMRXPARITYER			0x178
 881#define	RPMAC_OFDMRXCRC8ER			0x17c
 882#define	RPMAC_CCKCRXRC16ER			0x180
 883#define	RPMAC_CCKCRXRC32ER			0x184
 884#define	RPMAC_CCKCRXRC32OK			0x188
 885#define	RPMAC_TXSTATUS				0x18c
 886
 887#define	RF_BB_CMD_ADDR				0x02c0
 888#define	RF_BB_CMD_DATA				0x02c4
 889
 890#define	RFPGA0_RFMOD				0x800
 891
 892#define	RFPGA0_TXINFO				0x804
 893#define	RFPGA0_PSDFUNCTION			0x808
 894
 895#define	RFPGA0_TXGAINSTAGE			0x80c
 896
 897#define	RFPGA0_RFTIMING1			0x810
 898#define	RFPGA0_RFTIMING2			0x814
 899#define	RFPGA0_XA_HSSIPARAMETER1		0x820
 900#define	RFPGA0_XA_HSSIPARAMETER2		0x824
 901#define	RFPGA0_XB_HSSIPARAMETER1		0x828
 902#define	RFPGA0_XB_HSSIPARAMETER2		0x82c
 903#define	RFPGA0_XC_HSSIPARAMETER1		0x830
 904#define	RFPGA0_XC_HSSIPARAMETER2		0x834
 905#define	RFPGA0_XD_HSSIPARAMETER1		0x838
 906#define	RFPGA0_XD_HSSIPARAMETER2		0x83c
 907#define	RFPGA0_XA_LSSIPARAMETER			0x840
 908#define	RFPGA0_XB_LSSIPARAMETER			0x844
 909#define	RFPGA0_XC_LSSIPARAMETER			0x848
 910#define	RFPGA0_XD_LSSIPARAMETER			0x84c
 911
 912#define	RFPGA0_RFWAKEUP_PARAMETER		0x850
 913#define	RFPGA0_RFSLEEPUP_PARAMETER		0x854
 914
 915#define	RFPGA0_XAB_SWITCHCONTROL		0x858
 916#define	RFPGA0_XCD_SWITCHCONTROL		0x85c
 917
 918#define	RFPGA0_XA_RFINTERFACEOE			0x860
 919#define	RFPGA0_XB_RFINTERFACEOE			0x864
 920#define	RFPGA0_XC_RFINTERFACEOE			0x868
 921#define	RFPGA0_XD_RFINTERFACEOE			0x86c
 922
 923#define	RFPGA0_XAB_RFINTERFACESW		0x870
 924#define	RFPGA0_XCD_RFINTERFACESW		0x874
 925
 926#define	RFPGA0_XAB_RFPARAMETER			0x878
 927#define	RFPGA0_XCD_RFPARAMETER			0x87c
 928
 929#define	RFPGA0_ANALOGPARAMETER1			0x880
 930#define	RFPGA0_ANALOGPARAMETER2			0x884
 931#define	RFPGA0_ANALOGPARAMETER3			0x888
 932#define	RFPGA0_ANALOGPARAMETER4			0x88c
 933
 934#define	RFPGA0_XA_LSSIREADBACK			0x8a0
 935#define	RFPGA0_XB_LSSIREADBACK			0x8a4
 936#define	RFPGA0_XC_LSSIREADBACK			0x8a8
 937#define	RFPGA0_XD_LSSIREADBACK			0x8ac
 938
 939#define	RFPGA0_PSDREPORT			0x8b4
 940#define	TRANSCEIVERA_HSPI_READBACK		0x8b8
 941#define	TRANSCEIVERB_HSPI_READBACK		0x8bc
 942#define	RFPGA0_XAB_RFINTERFACERB		0x8e0
 943#define	RFPGA0_XCD_RFINTERFACERB		0x8e4
 944#define	RFPGA1_RFMOD				0x900
 945
 946#define	RFPGA1_TXBLOCK				0x904
 947#define	RFPGA1_DEBUGSELECT			0x908
 948#define	RFPGA1_TXINFO				0x90c
 949
 950#define	RCCK0_SYSTEM				0xa00
 951
 952#define	RCCK0_AFESETTING			0xa04
 953#define	RCCK0_CCA				0xa08
 954
 955#define	RCCK0_RXAGC1				0xa0c
 956#define	RCCK0_RXAGC2				0xa10
 957
 958#define	RCCK0_RXHP				0xa14
 959
 960#define	RCCK0_DSPPARAMETER1			0xa18
 961#define	RCCK0_DSPPARAMETER2			0xa1c
 962
 963#define	RCCK0_TXFILTER1				0xa20
 964#define	RCCK0_TXFILTER2				0xa24
 965#define	RCCK0_DEBUGPORT				0xa28
 966#define	RCCK0_FALSEALARMREPORT			0xa2c
 967#define	RCCK0_TRSSIREPORT			0xa50
 968#define	RCCK0_RXREPORT				0xa54
 969#define	RCCK0_FACOUNTERLOWER			0xa5c
 970#define	RCCK0_FACOUNTERUPPER			0xa58
 971
 972#define	ROFDM0_LSTF				0xc00
 973
 974#define	ROFDM0_TRXPATHENABLE			0xc04
 975#define	ROFDM0_TRMUXPAR				0xc08
 976#define	ROFDM0_TRSWISOLATION			0xc0c
 977
 978#define	ROFDM0_XARXAFE				0xc10
 979#define	ROFDM0_XARXIQIMBALANCE			0xc14
 980#define	ROFDM0_XBRXAFE				0xc18
 981#define	ROFDM0_XBRXIQIMBALANCE			0xc1c
 982#define	ROFDM0_XCRXAFE				0xc20
 983#define	ROFDM0_XCRXIQIMBALANCE			0xc24
 984#define	ROFDM0_XDRXAFE				0xc28
 985#define	ROFDM0_XDRXIQIMBALANCE			0xc2c
 986
 987#define	ROFDM0_RXDETECTOR1			0xc30
 988#define	ROFDM0_RXDETECTOR2			0xc34
 989#define	ROFDM0_RXDETECTOR3			0xc38
 990#define	ROFDM0_RXDETECTOR4			0xc3c
 991
 992#define	ROFDM0_RXDSP				0xc40
 993#define	ROFDM0_CFO_AND_DAGC			0xc44
 994#define	ROFDM0_CCADROP_THRESHOLD		0xc48
 995#define	ROFDM0_ECCA_THRESHOLD			0xc4c
 996
 997#define	ROFDM0_XAAGCCORE1			0xc50
 998#define	ROFDM0_XAAGCCORE2			0xc54
 999#define	ROFDM0_XBAGCCORE1			0xc58
1000#define	ROFDM0_XBAGCCORE2			0xc5c
1001#define	ROFDM0_XCAGCCORE1			0xc60
1002#define	ROFDM0_XCAGCCORE2			0xc64
1003#define	ROFDM0_XDAGCCORE1			0xc68
1004#define	ROFDM0_XDAGCCORE2			0xc6c
1005
1006#define	ROFDM0_AGCPARAMETER1			0xc70
1007#define	ROFDM0_AGCPARAMETER2			0xc74
1008#define	ROFDM0_AGCRSSITABLE			0xc78
1009#define	ROFDM0_HTSTFAGC				0xc7c
1010
1011#define	ROFDM0_XATXIQIMBALANCE			0xc80
1012#define	ROFDM0_XATXAFE				0xc84
1013#define	ROFDM0_XBTXIQIMBALANCE			0xc88
1014#define	ROFDM0_XBTXAFE				0xc8c
1015#define	ROFDM0_XCTXIQIMBALANCE			0xc90
1016#define	ROFDM0_XCTXAFE				0xc94
1017#define	ROFDM0_XDTXIQIMBALANCE			0xc98
1018#define	ROFDM0_XDTXAFE				0xc9c
1019
1020#define	ROFDM0_RXHP_PARAMETER			0xce0
1021#define	ROFDM0_TXPSEUDO_NOISE_WGT		0xce4
1022#define	ROFDM0_FRAME_SYNC			0xcf0
1023#define	ROFDM0_DFSREPORT			0xcf4
1024#define	ROFDM0_TXCOEFF1				0xca4
1025#define	ROFDM0_TXCOEFF2				0xca8
1026#define	ROFDM0_TXCOEFF3				0xcac
1027#define	ROFDM0_TXCOEFF4				0xcb0
1028#define	ROFDM0_TXCOEFF5				0xcb4
1029#define	ROFDM0_TXCOEFF6				0xcb8
1030
1031
1032#define	ROFDM1_LSTF				0xd00
1033#define	ROFDM1_TRXPATHENABLE			0xd04
1034
1035#define	ROFDM1_CFO				0xd08
1036#define	ROFDM1_CSI1				0xd10
1037#define	ROFDM1_SBD				0xd14
1038#define	ROFDM1_CSI2				0xd18
1039#define	ROFDM1_CFOTRACKING			0xd2c
1040#define	ROFDM1_TRXMESAURE1			0xd34
1041#define	ROFDM1_INTF_DET				0xd3c
1042#define	ROFDM1_PSEUDO_NOISESTATEAB		0xd50
1043#define	ROFDM1_PSEUDO_NOISESTATECD		0xd54
1044#define	ROFDM1_RX_PSEUDO_NOISE_WGT		0xd58
1045
1046#define	ROFDM_PHYCOUNTER1			0xda0
1047#define	ROFDM_PHYCOUNTER2			0xda4
1048#define	ROFDM_PHYCOUNTER3			0xda8
1049
1050#define	ROFDM_SHORT_CFOAB			0xdac
1051#define	ROFDM_SHORT_CFOCD			0xdb0
1052#define	ROFDM_LONG_CFOAB			0xdb4
1053#define	ROFDM_LONG_CFOCD			0xdb8
1054#define	ROFDM_TAIL_CFOAB			0xdbc
1055#define	ROFDM_TAIL_CFOCD			0xdc0
1056#define	ROFDM_PW_MEASURE1			0xdc4
1057#define	ROFDM_PW_MEASURE2			0xdc8
1058#define	ROFDM_BW_REPORT				0xdcc
1059#define	ROFDM_AGC_REPORT			0xdd0
1060#define	ROFDM_RXSNR				0xdd4
1061#define	ROFDM_RXEVMCSI				0xdd8
1062#define	ROFDM_SIG_REPORT			0xddc
1063
1064
1065#define	RTXAGC_RATE18_06			0xe00
1066#define	RTXAGC_RATE54_24			0xe04
1067#define	RTXAGC_CCK_MCS32			0xe08
1068#define	RTXAGC_MCS03_MCS00			0xe10
1069#define	RTXAGC_MCS07_MCS04			0xe14
1070#define	RTXAGC_MCS11_MCS08			0xe18
1071#define	RTXAGC_MCS15_MCS12			0xe1c
1072
1073
1074#define	RF_AC					0x00
1075#define	RF_IQADJ_G1				0x01
1076#define	RF_IQADJ_G2				0x02
1077#define	RF_POW_TRSW				0x05
1078#define	RF_GAIN_RX				0x06
1079#define	RF_GAIN_TX				0x07
1080#define	RF_TXM_IDAC				0x08
1081#define	RF_BS_IQGEN				0x0F
1082
1083#define	RF_MODE1				0x10
1084#define	RF_MODE2				0x11
1085#define	RF_RX_AGC_HP				0x12
1086#define	RF_TX_AGC				0x13
1087#define	RF_BIAS					0x14
1088#define	RF_IPA					0x15
1089#define	RF_POW_ABILITY				0x17
1090#define	RF_MODE_AG				0x18
1091#define	RF_CHANNEL				0x18
1092#define	RF_CHNLBW				0x18
1093#define	RF_TOP					0x19
1094#define	RF_RX_G1				0x1A
1095#define	RF_RX_G2				0x1B
1096#define	RF_RX_BB2				0x1C
1097#define	RF_RX_BB1				0x1D
1098#define	RF_RCK1					0x1E
1099#define	RF_RCK2					0x1F
1100
1101#define	RF_TX_G1				0x20
1102#define	RF_TX_G2				0x21
1103#define	RF_TX_G3				0x22
1104#define	RF_TX_BB1				0x23
1105#define	RF_T_METER				0x24
1106#define	RF_SYN_G1				0x25
1107#define	RF_SYN_G2				0x26
1108#define	RF_SYN_G3				0x27
1109#define	RF_SYN_G4				0x28
1110#define	RF_SYN_G5				0x29
1111#define	RF_SYN_G6				0x2A
1112#define	RF_SYN_G7				0x2B
1113#define	RF_SYN_G8				0x2C
1114
1115#define	RF_RCK_OS				0x30
1116#define	RF_TXPA_G1				0x31
1117#define	RF_TXPA_G2				0x32
1118#define	RF_TXPA_G3				0x33
1119
1120#define	BRFMOD					0x1
1121#define	BCCKEN					0x1000000
1122#define	BOFDMEN					0x2000000
1123
1124#define	BXBTXAGC				0xf00
1125#define	BXCTXAGC				0xf000
1126#define	BXDTXAGC				0xf0000
1127
1128#define	B3WIRE_DATALENGTH			0x800
1129#define	B3WIRE_ADDRESSLENGTH			0x400
1130
1131#define	BRFSI_RFENV				0x10
1132
1133#define	BLSSI_READADDRESS			0x7f800000
1134#define	BLSSI_READEDGE				0x80000000
1135#define	BLSSI_READBACK_DATA			0xfffff
1136
1137#define	BADCLKPHASE				0x4000000
1138
1139#define	BCCK_SIDEBAND				0x10
1140
1141#define	BTX_AGCRATECCK				0x7f00
1142
1143#endif