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phy.c
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linux-6.19.14/drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.c
1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2024 Realtek Corporation.*/ 3 4#include "../wifi.h" 5#include "../ps.h" 6#include "../core.h" 7#include "../efuse.h" 8#include "../usb.h" 9#include "../rtl8192d/reg.h" 10#include "../rtl8192d/def.h" 11#include "../rtl8192d/phy_common.h" 12#include "../rtl8192d/rf_common.h" 13#include "phy.h" 14#include "rf.h" 15#include "table.h" 16 17#define MAX_RF_IMR_INDEX 12 18#define MAX_RF_IMR_INDEX_NORMAL 13 19#define RF_REG_NUM_FOR_C_CUT_5G 6 20#define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA 7 21#define RF_REG_NUM_FOR_C_CUT_2G 5 22#define RF_CHNL_NUM_5G 19 23#define RF_CHNL_NUM_5G_40M 17 24#define CV_CURVE_CNT 64 25 26static const u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = { 27 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0 28}; 29 30static const u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = { 31 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6 32}; 33 34static const u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = { 35 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8 36}; 37 38static const u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = { 39 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E 40}; 41 42static const u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = { 43 BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1), 44 BIT(10) | BIT(9), 45 BIT(18) | BIT(17) | BIT(16) | BIT(1), 46 BIT(2) | BIT(1), 47 BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11) 48}; 49 50static const u8 rf_chnl_5g[RF_CHNL_NUM_5G] = { 51 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 52 112, 116, 120, 124, 128, 132, 136, 140 53}; 54 55static const u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = { 56 38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114, 57 118, 122, 126, 130, 134, 138 58}; 59 60static const u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = { 61 {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04}, 62 {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04}, 63 {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04}, 64 {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04}, 65 {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04} 66}; 67 68static const u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = { 69 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}, 70 {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840}, 71 {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41} 72}; 73 74static const u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF; 75 76static const u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = { 77 {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12}, 78 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52}, 79 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12} 80}; 81 82/* [patha+b][reg] */ 83static const u32 rf_imr_param_normal[3][MAX_RF_IMR_INDEX_NORMAL] = { 84 /* channels 1-14. */ 85 { 86 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0, 87 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff 88 }, 89 /* channels 36-64 */ 90 { 91 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000, 92 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090, 93 0x32c9a 94 }, 95 /* channels 100-165 */ 96 { 97 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000, 98 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a 99 } 100}; 101 102static const u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = { 103 25141, 25116, 25091, 25066, 25041, 104 25016, 24991, 24966, 24941, 24917, 105 24892, 24867, 24843, 24818, 24794, 106 24770, 24765, 24721, 24697, 24672, 107 24648, 24624, 24600, 24576, 24552, 108 24528, 24504, 24480, 24457, 24433, 109 24409, 24385, 24362, 24338, 24315, 110 24291, 24268, 24245, 24221, 24198, 111 24175, 24151, 24128, 24105, 24082, 112 24059, 24036, 24013, 23990, 23967, 113 23945, 23922, 23899, 23876, 23854, 114 23831, 23809, 23786, 23764, 23741, 115 23719, 23697, 23674, 23652, 23630, 116 23608, 23586, 23564, 23541, 23519, 117 23498, 23476, 23454, 23432, 23410, 118 23388, 23367, 23345, 23323, 23302, 119 23280, 23259, 23237, 23216, 23194, 120 23173, 23152, 23130, 23109, 23088, 121 23067, 23046, 23025, 23003, 22982, 122 22962, 22941, 22920, 22899, 22878, 123 22857, 22837, 22816, 22795, 22775, 124 22754, 22733, 22713, 22692, 22672, 125 22652, 22631, 22611, 22591, 22570, 126 22550, 22530, 22510, 22490, 22469, 127 22449, 22429, 22409, 22390, 22370, 128 22350, 22336, 22310, 22290, 22271, 129 22251, 22231, 22212, 22192, 22173, 130 22153, 22134, 22114, 22095, 22075, 131 22056, 22037, 22017, 21998, 21979, 132 21960, 21941, 21921, 21902, 21883, 133 21864, 21845, 21826, 21807, 21789, 134 21770, 21751, 21732, 21713, 21695, 135 21676, 21657, 21639, 21620, 21602, 136 21583, 21565, 21546, 21528, 21509, 137 21491, 21473, 21454, 21436, 21418, 138 21400, 21381, 21363, 21345, 21327, 139 21309, 21291, 21273, 21255, 21237, 140 21219, 21201, 21183, 21166, 21148, 141 21130, 21112, 21095, 21077, 21059, 142 21042, 21024, 21007, 20989, 20972, 143 25679, 25653, 25627, 25601, 25575, 144 25549, 25523, 25497, 25471, 25446, 145 25420, 25394, 25369, 25343, 25318, 146 25292, 25267, 25242, 25216, 25191, 147 25166 148}; 149 150/* channel 1~14 */ 151static const u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = { 152 26084, 26030, 25976, 25923, 25869, 25816, 25764, 153 25711, 25658, 25606, 25554, 25502, 25451, 25328 154}; 155 156u32 rtl92du_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) 157{ 158 struct rtl_priv *rtlpriv = rtl_priv(hw); 159 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 160 u32 returnvalue, originalvalue, bitshift; 161 162 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n", 163 regaddr, bitmask); 164 165 if (rtlhal->during_mac1init_radioa) 166 regaddr |= MAC1_ACCESS_PHY0; 167 else if (rtlhal->during_mac0init_radiob) 168 regaddr |= MAC0_ACCESS_PHY1; 169 170 originalvalue = rtl_read_dword(rtlpriv, regaddr); 171 bitshift = calculate_bit_shift(bitmask); 172 returnvalue = (originalvalue & bitmask) >> bitshift; 173 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 174 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", 175 bitmask, regaddr, originalvalue); 176 return returnvalue; 177} 178 179void rtl92du_phy_set_bb_reg(struct ieee80211_hw *hw, 180 u32 regaddr, u32 bitmask, u32 data) 181{ 182 struct rtl_priv *rtlpriv = rtl_priv(hw); 183 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 184 u32 originalvalue, bitshift; 185 186 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 187 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 188 regaddr, bitmask, data); 189 190 if (rtlhal->during_mac1init_radioa) 191 regaddr |= MAC1_ACCESS_PHY0; 192 else if (rtlhal->during_mac0init_radiob) 193 regaddr |= MAC0_ACCESS_PHY1; 194 195 if (bitmask != MASKDWORD) { 196 originalvalue = rtl_read_dword(rtlpriv, regaddr); 197 bitshift = calculate_bit_shift(bitmask); 198 data = (originalvalue & (~bitmask)) | 199 ((data << bitshift) & bitmask); 200 } 201 202 rtl_write_dword(rtlpriv, regaddr, data); 203 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 204 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 205 regaddr, bitmask, data); 206} 207 208/* To avoid miswrite Reg0x800 for 92D */ 209static void rtl92du_phy_set_bb_reg_1byte(struct ieee80211_hw *hw, 210 u32 regaddr, u32 bitmask, u32 data) 211{ 212 struct rtl_priv *rtlpriv = rtl_priv(hw); 213 u32 originalvalue, bitshift, offset; 214 u8 value; 215 216 /* BitMask only support bit0~bit7 or bit8~bit15, bit16~bit23, 217 * bit24~bit31, should be in 1 byte scale; 218 */ 219 bitshift = calculate_bit_shift(bitmask); 220 offset = bitshift / 8; 221 222 originalvalue = rtl_read_dword(rtlpriv, regaddr); 223 data = (originalvalue & (~bitmask)) | ((data << bitshift) & bitmask); 224 225 value = data >> (8 * offset); 226 227 rtl_write_byte(rtlpriv, regaddr + offset, value); 228} 229 230bool rtl92du_phy_mac_config(struct ieee80211_hw *hw) 231{ 232 struct rtl_priv *rtlpriv = rtl_priv(hw); 233 u32 arraylength; 234 const u32 *ptrarray; 235 u32 i; 236 237 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n"); 238 239 arraylength = MAC_2T_ARRAYLENGTH; 240 ptrarray = rtl8192du_mac_2tarray; 241 242 for (i = 0; i < arraylength; i = i + 2) 243 rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]); 244 245 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) { 246 /* improve 2-stream TX EVM */ 247 /* rtl_write_byte(rtlpriv, 0x14,0x71); */ 248 /* AMPDU aggregation number 9 */ 249 /* rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */ 250 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B); 251 } else { 252 /* 92D need to test to decide the num. */ 253 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07); 254 } 255 256 return true; 257} 258 259static bool _rtl92du_phy_config_bb(struct ieee80211_hw *hw, u8 configtype) 260{ 261 struct rtl_priv *rtlpriv = rtl_priv(hw); 262 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 263 u16 phy_reg_arraylen, agctab_arraylen = 0; 264 const u32 *agctab_array_table = NULL; 265 const u32 *phy_regarray_table; 266 int i; 267 268 /* Normal chip, Mac0 use AGC_TAB.txt for 2G and 5G band. */ 269 if (rtlhal->interfaceindex == 0) { 270 agctab_arraylen = AGCTAB_ARRAYLENGTH; 271 agctab_array_table = rtl8192du_agctab_array; 272 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 273 " ===> phy:MAC0, Rtl819XAGCTAB_Array\n"); 274 } else { 275 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 276 agctab_arraylen = AGCTAB_2G_ARRAYLENGTH; 277 agctab_array_table = rtl8192du_agctab_2garray; 278 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 279 " ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n"); 280 } else { 281 agctab_arraylen = AGCTAB_5G_ARRAYLENGTH; 282 agctab_array_table = rtl8192du_agctab_5garray; 283 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 284 " ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n"); 285 } 286 } 287 phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH; 288 phy_regarray_table = rtl8192du_phy_reg_2tarray; 289 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 290 " ===> phy:Rtl819XPHY_REG_Array_PG\n"); 291 292 if (configtype == BASEBAND_CONFIG_PHY_REG) { 293 for (i = 0; i < phy_reg_arraylen; i = i + 2) { 294 rtl_addr_delay(phy_regarray_table[i]); 295 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, 296 phy_regarray_table[i + 1]); 297 udelay(1); 298 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 299 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n", 300 phy_regarray_table[i], 301 phy_regarray_table[i + 1]); 302 } 303 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) { 304 for (i = 0; i < agctab_arraylen; i = i + 2) { 305 rtl_set_bbreg(hw, agctab_array_table[i], 306 MASKDWORD, agctab_array_table[i + 1]); 307 308 /* Add 1us delay between BB/RF register setting. */ 309 udelay(1); 310 311 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 312 "AGC table %u %u\n", 313 agctab_array_table[i], 314 agctab_array_table[i + 1]); 315 } 316 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 317 "Normal Chip, loaded AGC table\n"); 318 } 319 return true; 320} 321 322static bool _rtl92du_phy_config_bb_pg(struct ieee80211_hw *hw, u8 configtype) 323{ 324 struct rtl_priv *rtlpriv = rtl_priv(hw); 325 const u32 *phy_regarray_table_pg; 326 u16 phy_regarray_pg_len; 327 int i; 328 329 phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH; 330 phy_regarray_table_pg = rtl8192du_phy_reg_array_pg; 331 332 if (configtype == BASEBAND_CONFIG_PHY_REG) { 333 for (i = 0; i < phy_regarray_pg_len; i = i + 3) { 334 rtl_addr_delay(phy_regarray_table_pg[i]); 335 rtl92d_store_pwrindex_diffrate_offset(hw, 336 phy_regarray_table_pg[i], 337 phy_regarray_table_pg[i + 1], 338 phy_regarray_table_pg[i + 2]); 339 } 340 } else { 341 rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE, 342 "configtype != BaseBand_Config_PHY_REG\n"); 343 } 344 return true; 345} 346 347static bool _rtl92du_phy_bb_config(struct ieee80211_hw *hw) 348{ 349 struct rtl_priv *rtlpriv = rtl_priv(hw); 350 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); 351 struct rtl_phy *rtlphy = &rtlpriv->phy; 352 bool ret; 353 354 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n"); 355 ret = _rtl92du_phy_config_bb(hw, BASEBAND_CONFIG_PHY_REG); 356 if (!ret) { 357 pr_err("Write BB Reg Fail!!\n"); 358 return false; 359 } 360 361 if (!rtlefuse->autoload_failflag) { 362 rtlphy->pwrgroup_cnt = 0; 363 ret = _rtl92du_phy_config_bb_pg(hw, BASEBAND_CONFIG_PHY_REG); 364 } 365 if (!ret) { 366 pr_err("BB_PG Reg Fail!!\n"); 367 return false; 368 } 369 370 ret = _rtl92du_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB); 371 if (!ret) { 372 pr_err("AGC Table Fail\n"); 373 return false; 374 } 375 376 rtlphy->cck_high_power = (bool)rtl_get_bbreg(hw, 377 RFPGA0_XA_HSSIPARAMETER2, 378 0x200); 379 380 return true; 381} 382 383bool rtl92du_phy_bb_config(struct ieee80211_hw *hw) 384{ 385 struct rtl_priv *rtlpriv = rtl_priv(hw); 386 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 387 bool rtstatus; 388 u32 regvaldw; 389 u16 regval; 390 u8 value; 391 392 rtl92d_phy_init_bb_rf_register_definition(hw); 393 394 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 395 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, 396 regval | BIT(13) | BIT(0) | BIT(1)); 397 398 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83); 399 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb); 400 401 /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */ 402 value = rtl_read_byte(rtlpriv, REG_RF_CTRL); 403 rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB | 404 RF_SDMRSTB); 405 406 value = FEN_BB_GLB_RSTN | FEN_BBRSTB; 407 if (rtlhal->interface == INTF_PCI) 408 value |= FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE; 409 else if (rtlhal->interface == INTF_USB) 410 value |= FEN_USBA | FEN_USBD; 411 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value); 412 413 regvaldw = rtl_read_dword(rtlpriv, RFPGA0_XCD_RFPARAMETER); 414 regvaldw &= ~BIT(31); 415 rtl_write_dword(rtlpriv, RFPGA0_XCD_RFPARAMETER, regvaldw); 416 417 /* To Fix MAC loopback mode fail. */ 418 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f); 419 rtl_write_byte(rtlpriv, 0x15, 0xe9); 420 421 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); 422 if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version)) && 423 rtlhal->interface == INTF_PCI) { 424 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0); 425 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23)); 426 } 427 428 rtstatus = _rtl92du_phy_bb_config(hw); 429 430 /* Crystal calibration */ 431 rtl_set_bbreg(hw, REG_AFE_XTAL_CTRL, 0xf0, 432 rtlpriv->efuse.crystalcap & 0x0f); 433 rtl_set_bbreg(hw, REG_AFE_PLL_CTRL, 0xf0000000, 434 (rtlpriv->efuse.crystalcap & 0xf0) >> 4); 435 436 return rtstatus; 437} 438 439bool rtl92du_phy_rf_config(struct ieee80211_hw *hw) 440{ 441 return rtl92du_phy_rf6052_config(hw); 442} 443 444bool rtl92du_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 445 enum rf_content content, 446 enum radio_path rfpath) 447{ 448 struct rtl_priv *rtlpriv = rtl_priv(hw); 449 u16 radioa_arraylen, radiob_arraylen; 450 const u32 *radioa_array_table; 451 const u32 *radiob_array_table; 452 int i; 453 454 radioa_arraylen = RADIOA_2T_ARRAYLENGTH; 455 radioa_array_table = rtl8192du_radioa_2tarray; 456 radiob_arraylen = RADIOB_2T_ARRAYLENGTH; 457 radiob_array_table = rtl8192du_radiob_2tarray; 458 if (rtlpriv->efuse.internal_pa_5g[0]) { 459 radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH; 460 radioa_array_table = rtl8192du_radioa_2t_int_paarray; 461 } 462 if (rtlpriv->efuse.internal_pa_5g[1]) { 463 radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH; 464 radiob_array_table = rtl8192du_radiob_2t_int_paarray; 465 } 466 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 467 "PHY_ConfigRFWithHeaderFile() Radio_A:Rtl819XRadioA_1TArray\n"); 468 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 469 "PHY_ConfigRFWithHeaderFile() Radio_B:Rtl819XRadioB_1TArray\n"); 470 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath); 471 472 /* this only happens when DMDP, mac0 start on 2.4G, 473 * mac1 start on 5G, mac 0 has to set phy0 & phy1 474 * pathA or mac1 has to set phy0 & phy1 pathA 475 */ 476 if (content == radiob_txt && rfpath == RF90_PATH_A) { 477 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 478 " ===> althougth Path A, we load radiob.txt\n"); 479 radioa_arraylen = radiob_arraylen; 480 radioa_array_table = radiob_array_table; 481 } 482 483 switch (rfpath) { 484 case RF90_PATH_A: 485 for (i = 0; i < radioa_arraylen; i = i + 2) { 486 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i], 487 RFREG_OFFSET_MASK, 488 radioa_array_table[i + 1]); 489 } 490 break; 491 case RF90_PATH_B: 492 for (i = 0; i < radiob_arraylen; i = i + 2) { 493 rtl_rfreg_delay(hw, rfpath, radiob_array_table[i], 494 RFREG_OFFSET_MASK, 495 radiob_array_table[i + 1]); 496 } 497 break; 498 case RF90_PATH_C: 499 case RF90_PATH_D: 500 pr_err("switch case %#x not processed\n", rfpath); 501 break; 502 } 503 504 return true; 505} 506 507void rtl92du_phy_set_bw_mode(struct ieee80211_hw *hw, 508 enum nl80211_channel_type ch_type) 509{ 510 struct rtl_priv *rtlpriv = rtl_priv(hw); 511 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 512 struct rtl_phy *rtlphy = &rtlpriv->phy; 513 struct rtl_mac *mac = rtl_mac(rtlpriv); 514 u8 reg_bw_opmode; 515 u8 reg_prsr_rsc; 516 517 if (rtlphy->set_bwmode_inprogress) 518 return; 519 520 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { 521 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 522 "FALSE driver sleep or unload\n"); 523 return; 524 } 525 526 rtlphy->set_bwmode_inprogress = true; 527 528 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n", 529 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? 530 "20MHz" : "40MHz"); 531 532 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE); 533 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2); 534 535 switch (rtlphy->current_chan_bw) { 536 case HT_CHANNEL_WIDTH_20: 537 reg_bw_opmode |= BW_OPMODE_20MHZ; 538 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 539 break; 540 case HT_CHANNEL_WIDTH_20_40: 541 reg_bw_opmode &= ~BW_OPMODE_20MHZ; 542 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 543 544 reg_prsr_rsc = (reg_prsr_rsc & 0x90) | 545 (mac->cur_40_prime_sc << 5); 546 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc); 547 break; 548 default: 549 pr_err("unknown bandwidth: %#X\n", 550 rtlphy->current_chan_bw); 551 break; 552 } 553 554 switch (rtlphy->current_chan_bw) { 555 case HT_CHANNEL_WIDTH_20: 556 rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BRFMOD, 0x0); 557 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); 558 /* SET BIT10 BIT11 for receive cck */ 559 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | BIT(11), 3); 560 break; 561 case HT_CHANNEL_WIDTH_20_40: 562 rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BRFMOD, 0x1); 563 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); 564 /* Set Control channel to upper or lower. 565 * These settings are required only for 40MHz 566 */ 567 if (rtlhal->current_bandtype == BAND_ON_2_4G) 568 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND, 569 mac->cur_40_prime_sc >> 1); 570 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); 571 /* SET BIT10 BIT11 for receive cck */ 572 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, 573 BIT(10) | BIT(11), 0); 574 rtl_set_bbreg(hw, 0x818, BIT(26) | BIT(27), 575 mac->cur_40_prime_sc == 576 HAL_PRIME_CHNL_OFFSET_LOWER ? 2 : 1); 577 break; 578 default: 579 pr_err("unknown bandwidth: %#X\n", 580 rtlphy->current_chan_bw); 581 break; 582 } 583 584 rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); 585 586 rtlphy->set_bwmode_inprogress = false; 587 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 588} 589 590static void _rtl92du_phy_stop_trx_before_changeband(struct ieee80211_hw *hw) 591{ 592 rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BCCKEN | BOFDMEN, 0); 593 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00); 594 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0); 595} 596 597static void rtl92du_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band) 598{ 599 struct rtl_priv *rtlpriv = rtl_priv(hw); 600 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 601 u16 basic_rates; 602 u32 reg_mac; 603 u8 value8; 604 605 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n"); 606 rtlhal->bandset = band; 607 rtlhal->current_bandtype = band; 608 if (IS_92D_SINGLEPHY(rtlhal->version)) 609 rtlhal->bandset = BAND_ON_BOTH; 610 611 /* stop RX/Tx */ 612 _rtl92du_phy_stop_trx_before_changeband(hw); 613 614 /* reconfig BB/RF according to wireless mode */ 615 if (rtlhal->current_bandtype == BAND_ON_2_4G) 616 /* BB & RF Config */ 617 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "====>2.4G\n"); 618 else 619 /* 5G band */ 620 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "====>5G\n"); 621 622 if (rtlhal->interfaceindex == 1) 623 _rtl92du_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB); 624 625 rtl92du_update_bbrf_configuration(hw); 626 627 basic_rates = RRSR_6M | RRSR_12M | RRSR_24M; 628 if (rtlhal->current_bandtype == BAND_ON_2_4G) 629 basic_rates |= RRSR_1M | RRSR_2M | RRSR_5_5M | RRSR_11M; 630 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BASIC_RATE, 631 (u8 *)&basic_rates); 632 633 rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BCCKEN | BOFDMEN, 0x3); 634 635 /* 20M BW. */ 636 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */ 637 rtlhal->reloadtxpowerindex = true; 638 639 reg_mac = rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1; 640 641 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ 642 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 643 value8 = rtl_read_byte(rtlpriv, reg_mac); 644 value8 |= BIT(1); 645 rtl_write_byte(rtlpriv, reg_mac, value8); 646 } else { 647 value8 = rtl_read_byte(rtlpriv, reg_mac); 648 value8 &= ~BIT(1); 649 rtl_write_byte(rtlpriv, reg_mac, value8); 650 } 651 mdelay(1); 652 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n"); 653} 654 655static void _rtl92du_phy_reload_imr_setting(struct ieee80211_hw *hw, 656 u8 channel, u8 rfpath) 657{ 658 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 659 struct rtl_priv *rtlpriv = rtl_priv(hw); 660 u8 group, i; 661 662 if (rtlusb->udev->speed != USB_SPEED_HIGH) 663 return; 664 665 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>path %d\n", rfpath); 666 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) { 667 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n"); 668 rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, 669 BOFDMEN | BCCKEN, 0); 670 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); 671 672 /* fc area 0xd2c */ 673 if (channel >= 149) 674 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | 675 BIT(14), 2); 676 else 677 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | 678 BIT(14), 1); 679 680 /* leave 0 for channel1-14. */ 681 group = channel <= 64 ? 1 : 2; 682 for (i = 0; i < MAX_RF_IMR_INDEX_NORMAL; i++) 683 rtl_set_rfreg(hw, (enum radio_path)rfpath, 684 rf_reg_for_5g_swchnl_normal[i], 685 RFREG_OFFSET_MASK, 686 rf_imr_param_normal[group][i]); 687 688 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); 689 rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, 690 BOFDMEN | BCCKEN, 3); 691 } else { 692 /* G band. */ 693 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, 694 "Load RF IMR parameters for G band. IMR already setting %d\n", 695 rtlpriv->rtlhal.load_imrandiqk_setting_for2g); 696 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n"); 697 698 if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) { 699 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, 700 "Load RF IMR parameters for G band. %d\n", 701 rfpath); 702 rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, 703 BOFDMEN | BCCKEN, 0); 704 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 705 0x00f00000, 0xf); 706 707 for (i = 0; i < MAX_RF_IMR_INDEX_NORMAL; i++) { 708 rtl_set_rfreg(hw, (enum radio_path)rfpath, 709 rf_reg_for_5g_swchnl_normal[i], 710 RFREG_OFFSET_MASK, 711 rf_imr_param_normal[0][i]); 712 } 713 714 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 715 0x00f00000, 0); 716 rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, 717 BOFDMEN | BCCKEN, 3); 718 } 719 } 720 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); 721} 722 723static void _rtl92du_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel) 724{ 725 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 726 struct rtl_priv *rtlpriv = rtl_priv(hw); 727 struct rtl_hal *rtlhal = &rtlpriv->rtlhal; 728 struct rtl_phy *rtlphy = &rtlpriv->phy; 729 u8 path = rtlhal->current_bandtype == BAND_ON_5G ? RF90_PATH_A 730 : RF90_PATH_B; 731 u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2; 732 bool need_pwr_down = false, internal_pa = false; 733 u32 regb30 = rtl_get_bbreg(hw, 0xb30, BIT(27)); 734 u8 index = 0, i, rfpath; 735 736 if (rtlusb->udev->speed != USB_SPEED_HIGH) 737 return; 738 739 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>\n"); 740 /* config path A for 5G */ 741 if (rtlhal->current_bandtype == BAND_ON_5G) { 742 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n"); 743 u4tmp = rtlpriv->curveindex_5g[channel - 1]; 744 RTPRINT(rtlpriv, FINIT, INIT_IQK, 745 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); 746 747 for (i = 0; i < RF_CHNL_NUM_5G; i++) { 748 if (channel == rf_chnl_5g[i] && channel <= 140) 749 index = 0; 750 } 751 for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) { 752 if (channel == rf_chnl_5g_40m[i] && channel <= 140) 753 index = 1; 754 } 755 if (channel == 149 || channel == 155 || channel == 161) 756 index = 2; 757 else if (channel == 151 || channel == 153 || channel == 163 || 758 channel == 165) 759 index = 3; 760 else if (channel == 157 || channel == 159) 761 index = 4; 762 763 if (rtlhal->macphymode == DUALMAC_DUALPHY && 764 rtlhal->interfaceindex == 1) { 765 need_pwr_down = rtl92du_phy_enable_anotherphy(hw, false); 766 rtlhal->during_mac1init_radioa = true; 767 /* asume no this case */ 768 if (need_pwr_down) 769 rtl92d_phy_enable_rf_env(hw, path, 770 &u4regvalue); 771 } 772 773 /* DMDP, if band = 5G, Mac0 need to set PHY1 when regB30[27]=1 */ 774 if (regb30 && rtlhal->interfaceindex == 0) { 775 need_pwr_down = rtl92du_phy_enable_anotherphy(hw, true); 776 rtlhal->during_mac0init_radiob = true; 777 if (need_pwr_down) 778 rtl92d_phy_enable_rf_env(hw, path, 779 &u4regvalue); 780 } 781 782 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) { 783 if (i == 0 && rtlhal->macphymode == DUALMAC_DUALPHY) { 784 rtl_set_rfreg(hw, (enum radio_path)path, 785 rf_reg_for_c_cut_5g[i], 786 RFREG_OFFSET_MASK, 0xE439D); 787 } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) { 788 u4tmp2 = (rf_reg_pram_c_5g[index][i] & 789 0x7FF) | (u4tmp << 11); 790 if (channel == 36) 791 u4tmp2 &= ~(BIT(7) | BIT(6)); 792 rtl_set_rfreg(hw, (enum radio_path)path, 793 rf_reg_for_c_cut_5g[i], 794 RFREG_OFFSET_MASK, u4tmp2); 795 } else { 796 rtl_set_rfreg(hw, (enum radio_path)path, 797 rf_reg_for_c_cut_5g[i], 798 RFREG_OFFSET_MASK, 799 rf_reg_pram_c_5g[index][i]); 800 } 801 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 802 "offset 0x%x value 0x%x path %d index %d readback 0x%x\n", 803 rf_reg_for_c_cut_5g[i], 804 rf_reg_pram_c_5g[index][i], 805 path, index, 806 rtl_get_rfreg(hw, (enum radio_path)path, 807 rf_reg_for_c_cut_5g[i], 808 RFREG_OFFSET_MASK)); 809 } 810 if (rtlhal->macphymode == DUALMAC_DUALPHY && 811 rtlhal->interfaceindex == 1) { 812 if (need_pwr_down) 813 rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); 814 815 rtl92du_phy_powerdown_anotherphy(hw, false); 816 } 817 818 if (regb30 && rtlhal->interfaceindex == 0) { 819 if (need_pwr_down) 820 rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); 821 822 rtl92du_phy_powerdown_anotherphy(hw, true); 823 } 824 825 if (channel < 149) 826 value = 0x07; 827 else if (channel >= 149) 828 value = 0x02; 829 if (channel >= 36 && channel <= 64) 830 index = 0; 831 else if (channel >= 100 && channel <= 140) 832 index = 1; 833 else 834 index = 2; 835 836 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; 837 rfpath++) { 838 if (rtlhal->macphymode == DUALMAC_DUALPHY && 839 rtlhal->interfaceindex == 1) /* MAC 1 5G */ 840 internal_pa = rtlpriv->efuse.internal_pa_5g[1]; 841 else 842 internal_pa = 843 rtlpriv->efuse.internal_pa_5g[rfpath]; 844 845 if (internal_pa) { 846 for (i = 0; 847 i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA; 848 i++) { 849 if (rf_for_c_cut_5g_internal_pa[i] == 0x03 && 850 channel >= 36 && channel <= 64) 851 rtl_set_rfreg(hw, rfpath, 852 rf_for_c_cut_5g_internal_pa[i], 853 RFREG_OFFSET_MASK, 854 0x7bdef); 855 else 856 rtl_set_rfreg(hw, rfpath, 857 rf_for_c_cut_5g_internal_pa[i], 858 RFREG_OFFSET_MASK, 859 rf_pram_c_5g_int_pa[index][i]); 860 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, 861 "offset 0x%x value 0x%x path %d index %d\n", 862 rf_for_c_cut_5g_internal_pa[i], 863 rf_pram_c_5g_int_pa[index][i], 864 rfpath, index); 865 } 866 } else { 867 rtl_set_rfreg(hw, (enum radio_path)rfpath, RF_TXPA_AG, 868 mask, value); 869 } 870 } 871 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) { 872 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n"); 873 u4tmp = rtlpriv->curveindex_2g[channel - 1]; 874 RTPRINT(rtlpriv, FINIT, INIT_IQK, 875 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); 876 877 if (channel == 1 || channel == 2 || channel == 4 || 878 channel == 9 || channel == 10 || channel == 11 || 879 channel == 12) 880 index = 0; 881 else if (channel == 3 || channel == 13 || channel == 14) 882 index = 1; 883 else if (channel >= 5 && channel <= 8) 884 index = 2; 885 886 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 887 path = RF90_PATH_A; 888 if (rtlhal->interfaceindex == 0) { 889 need_pwr_down = 890 rtl92du_phy_enable_anotherphy(hw, true); 891 rtlhal->during_mac0init_radiob = true; 892 893 if (need_pwr_down) 894 rtl92d_phy_enable_rf_env(hw, path, 895 &u4regvalue); 896 } 897 898 /* DMDP, if band = 2G, MAC1 need to set PHY0 when regB30[27]=1 */ 899 if (regb30 && rtlhal->interfaceindex == 1) { 900 need_pwr_down = 901 rtl92du_phy_enable_anotherphy(hw, false); 902 rtlhal->during_mac1init_radioa = true; 903 904 if (need_pwr_down) 905 rtl92d_phy_enable_rf_env(hw, path, 906 &u4regvalue); 907 } 908 } 909 910 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) { 911 if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7) 912 rtl_set_rfreg(hw, (enum radio_path)path, 913 rf_reg_for_c_cut_2g[i], 914 RFREG_OFFSET_MASK, 915 rf_reg_param_for_c_cut_2g[index][i] | 916 BIT(17)); 917 else 918 rtl_set_rfreg(hw, (enum radio_path)path, 919 rf_reg_for_c_cut_2g[i], 920 RFREG_OFFSET_MASK, 921 rf_reg_param_for_c_cut_2g 922 [index][i]); 923 924 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 925 "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n", 926 rf_reg_for_c_cut_2g[i], 927 rf_reg_param_for_c_cut_2g[index][i], 928 rf_reg_mask_for_c_cut_2g[i], path, index, 929 rtl_get_rfreg(hw, (enum radio_path)path, 930 rf_reg_for_c_cut_2g[i], 931 RFREG_OFFSET_MASK)); 932 } 933 RTPRINT(rtlpriv, FINIT, INIT_IQK, 934 "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", 935 rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); 936 937 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4, 938 RFREG_OFFSET_MASK, 939 rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); 940 941 if (rtlhal->macphymode == DUALMAC_DUALPHY && 942 rtlhal->interfaceindex == 0) { 943 if (need_pwr_down) 944 rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); 945 946 rtl92du_phy_powerdown_anotherphy(hw, true); 947 } 948 949 if (regb30 && rtlhal->interfaceindex == 1) { 950 if (need_pwr_down) 951 rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); 952 953 rtl92du_phy_powerdown_anotherphy(hw, false); 954 } 955 } 956 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); 957} 958 959/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 960static u8 _rtl92du_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb) 961{ 962 struct rtl_priv *rtlpriv = rtl_priv(hw); 963 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 964 u32 regeac, rege94, rege9c, regea4; 965 u8 result = 0; 966 967 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); 968 969 if (rtlhal->interfaceindex == 0) { 970 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c1f); 971 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c1f); 972 } else { 973 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c22); 974 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c22); 975 } 976 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140102); 977 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 978 configpathb ? 0x28160202 : 0x28160502); 979 /* path-B IQK setting */ 980 if (configpathb) { 981 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x10008c22); 982 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x10008c22); 983 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82140102); 984 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160206); 985 } 986 987 /* LO calibration setting */ 988 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 989 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); 990 991 /* One shot, path A LOK & IQK */ 992 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n"); 993 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); 994 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); 995 996 RTPRINT(rtlpriv, FINIT, INIT_IQK, 997 "Delay %d ms for One shot, path A LOK & IQK\n", 998 IQK_DELAY_TIME); 999 mdelay(IQK_DELAY_TIME); 1000 1001 /* Check failed */ 1002 regeac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); 1003 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1004 rege94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); 1005 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); 1006 rege9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); 1007 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); 1008 regea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); 1009 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); 1010 1011 if (!(regeac & BIT(28)) && 1012 (((rege94 & 0x03FF0000) >> 16) != 0x142) && 1013 (((rege9c & 0x03FF0000) >> 16) != 0x42)) 1014 result |= 0x01; 1015 else /* if Tx not OK, ignore Rx */ 1016 return result; 1017 1018 /* if Tx is OK, check whether Rx is OK */ 1019 if (!(regeac & BIT(27)) && 1020 (((regea4 & 0x03FF0000) >> 16) != 0x132) && 1021 (((regeac & 0x03FF0000) >> 16) != 0x36)) 1022 result |= 0x02; 1023 else 1024 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A Rx IQK fail!!\n"); 1025 1026 return result; 1027} 1028 1029/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 1030static u8 _rtl92du_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw, 1031 bool configpathb) 1032{ 1033 struct rtl_priv *rtlpriv = rtl_priv(hw); 1034 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1035 struct rtl_phy *rtlphy = &rtlpriv->phy; 1036 u32 TXOKBIT = BIT(28), RXOKBIT = BIT(27); 1037 u32 regeac, rege94, rege9c, regea4; 1038 u8 timeout = 20, timecount = 0; 1039 u8 retrycount = 2; 1040 u8 result = 0; 1041 u8 i; 1042 1043 if (rtlhal->interfaceindex == 1) { /* PHY1 */ 1044 TXOKBIT = BIT(31); 1045 RXOKBIT = BIT(30); 1046 } 1047 1048 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); 1049 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1f); 1050 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1f); 1051 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140307); 1052 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160960); 1053 /* path-B IQK setting */ 1054 if (configpathb) { 1055 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c2f); 1056 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c2f); 1057 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); 1058 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68110000); 1059 } 1060 1061 /* LO calibration setting */ 1062 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 1063 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); 1064 1065 /* path-A PA on */ 1066 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); 1067 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); 1068 1069 for (i = 0; i < retrycount; i++) { 1070 /* One shot, path A LOK & IQK */ 1071 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1072 "One shot, path A LOK & IQK!\n"); 1073 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); 1074 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); 1075 1076 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1077 "Delay %d ms for One shot, path A LOK & IQK.\n", 1078 IQK_DELAY_TIME); 1079 mdelay(IQK_DELAY_TIME * 10); 1080 1081 while (timecount < timeout && 1082 rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, BIT(26)) == 0) { 1083 udelay(IQK_DELAY_TIME * 1000 * 2); 1084 timecount++; 1085 } 1086 1087 timecount = 0; 1088 while (timecount < timeout && 1089 rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASK_IQK_RESULT) == 0) { 1090 udelay(IQK_DELAY_TIME * 1000 * 2); 1091 timecount++; 1092 } 1093 1094 /* Check failed */ 1095 regeac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); 1096 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1097 rege94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); 1098 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); 1099 rege9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); 1100 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); 1101 regea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); 1102 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); 1103 1104 if (!(regeac & TXOKBIT) && 1105 (((rege94 & 0x03FF0000) >> 16) != 0x142)) { 1106 result |= 0x01; 1107 } else { /* if Tx not OK, ignore Rx */ 1108 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1109 "Path A Tx IQK fail!!\n"); 1110 continue; 1111 } 1112 1113 /* if Tx is OK, check whether Rx is OK */ 1114 if (!(regeac & RXOKBIT) && 1115 (((regea4 & 0x03FF0000) >> 16) != 0x132)) { 1116 result |= 0x02; 1117 break; 1118 } 1119 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A Rx IQK fail!!\n"); 1120 } 1121 1122 /* path A PA off */ 1123 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 1124 rtlphy->iqk_bb_backup[0]); 1125 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 1126 rtlphy->iqk_bb_backup[1]); 1127 1128 if (!(result & 0x01)) /* Tx IQK fail */ 1129 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x19008c00); 1130 1131 if (!(result & 0x02)) { /* Rx IQK fail */ 1132 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); 1133 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x19008c00); 1134 1135 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1136 "Path A Rx IQK fail!! 0xe34 = %#x\n", 1137 rtl_get_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD)); 1138 } 1139 1140 return result; 1141} 1142 1143/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 1144static u8 _rtl92du_phy_pathb_iqk(struct ieee80211_hw *hw) 1145{ 1146 struct rtl_priv *rtlpriv = rtl_priv(hw); 1147 u32 regeac, regeb4, regebc, regec4, regecc; 1148 u8 result = 0; 1149 1150 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path B LOK & IQK!\n"); 1151 rtl_set_bbreg(hw, RIQK_AGC_CONT, MASKDWORD, 0x00000002); 1152 rtl_set_bbreg(hw, RIQK_AGC_CONT, MASKDWORD, 0x00000000); 1153 1154 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1155 "Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME); 1156 mdelay(IQK_DELAY_TIME); 1157 1158 /* Check failed */ 1159 regeac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); 1160 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1161 regeb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD); 1162 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); 1163 regebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD); 1164 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); 1165 regec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD); 1166 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); 1167 regecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD); 1168 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); 1169 1170 if (!(regeac & BIT(31)) && 1171 (((regeb4 & 0x03FF0000) >> 16) != 0x142) && 1172 (((regebc & 0x03FF0000) >> 16) != 0x42)) 1173 result |= 0x01; 1174 else 1175 return result; 1176 1177 if (!(regeac & BIT(30)) && 1178 (((regec4 & 0x03FF0000) >> 16) != 0x132) && 1179 (((regecc & 0x03FF0000) >> 16) != 0x36)) 1180 result |= 0x02; 1181 else 1182 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B Rx IQK fail!!\n"); 1183 1184 return result; 1185} 1186 1187/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 1188static u8 _rtl92du_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw) 1189{ 1190 struct rtl_priv *rtlpriv = rtl_priv(hw); 1191 struct rtl_phy *rtlphy = &rtlpriv->phy; 1192 u32 regeac, regeb4, regebc, regec4, regecc; 1193 u8 timeout = 20, timecount = 0; 1194 u8 retrycount = 2; 1195 u8 result = 0; 1196 u8 i; 1197 1198 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-B IQK setting!\n"); 1199 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1f); 1200 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1f); 1201 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000); 1202 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68110000); 1203 1204 /* path-B IQK setting */ 1205 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c2f); 1206 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c2f); 1207 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82140307); 1208 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160960); 1209 1210 /* LO calibration setting */ 1211 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 1212 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); 1213 1214 /* path-B PA on */ 1215 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); 1216 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); 1217 1218 for (i = 0; i < retrycount; i++) { 1219 /* One shot, path B LOK & IQK */ 1220 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1221 "One shot, path A LOK & IQK!\n"); 1222 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); 1223 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); 1224 1225 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1226 "Delay %d ms for One shot, path B LOK & IQK.\n", 10); 1227 mdelay(IQK_DELAY_TIME * 10); 1228 1229 while (timecount < timeout && 1230 rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, BIT(29)) == 0) { 1231 udelay(IQK_DELAY_TIME * 1000 * 2); 1232 timecount++; 1233 } 1234 1235 timecount = 0; 1236 while (timecount < timeout && 1237 rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASK_IQK_RESULT) == 0) { 1238 udelay(IQK_DELAY_TIME * 1000 * 2); 1239 timecount++; 1240 } 1241 1242 /* Check failed */ 1243 regeac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); 1244 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1245 regeb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD); 1246 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); 1247 regebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD); 1248 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); 1249 regec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD); 1250 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); 1251 regecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD); 1252 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); 1253 1254 if (!(regeac & BIT(31)) && 1255 (((regeb4 & 0x03FF0000) >> 16) != 0x142)) 1256 result |= 0x01; 1257 else 1258 continue; 1259 1260 if (!(regeac & BIT(30)) && 1261 (((regec4 & 0x03FF0000) >> 16) != 0x132)) { 1262 result |= 0x02; 1263 break; 1264 } 1265 1266 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B Rx IQK fail!!\n"); 1267 } 1268 1269 /* path B PA off */ 1270 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 1271 rtlphy->iqk_bb_backup[0]); 1272 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 1273 rtlphy->iqk_bb_backup[2]); 1274 1275 if (!(result & 0x01)) 1276 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x19008c00); 1277 1278 if (!(result & 0x02)) { 1279 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); 1280 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x19008c00); 1281 1282 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1283 "Path B Rx IQK fail!! 0xe54 = %#x\n", 1284 rtl_get_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD)); 1285 } 1286 1287 return result; 1288} 1289 1290static void _rtl92du_phy_reload_adda_registers(struct ieee80211_hw *hw, 1291 const u32 *adda_reg, 1292 u32 *adda_backup, u32 regnum) 1293{ 1294 struct rtl_priv *rtlpriv = rtl_priv(hw); 1295 u32 i; 1296 1297 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1298 "Reload ADDA power saving parameters !\n"); 1299 for (i = 0; i < regnum; i++) { 1300 /* path-A/B BB to initial gain */ 1301 if (adda_reg[i] == ROFDM0_XAAGCCORE1 || 1302 adda_reg[i] == ROFDM0_XBAGCCORE1) 1303 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, 0x50); 1304 1305 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]); 1306 } 1307} 1308 1309static void _rtl92du_phy_reload_mac_registers(struct ieee80211_hw *hw, 1310 const u32 *macreg, u32 *macbackup) 1311{ 1312 struct rtl_priv *rtlpriv = rtl_priv(hw); 1313 u32 i; 1314 1315 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Reload MAC parameters !\n"); 1316 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 1317 rtl_write_byte(rtlpriv, macreg[i], (u8)macbackup[i]); 1318 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]); 1319} 1320 1321static void _rtl92du_phy_patha_standby(struct ieee80211_hw *hw) 1322{ 1323 struct rtl_priv *rtlpriv = rtl_priv(hw); 1324 1325 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A standby mode!\n"); 1326 1327 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x0); 1328 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); 1329 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x808000); 1330} 1331 1332static void _rtl92du_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode) 1333{ 1334 struct rtl_priv *rtlpriv = rtl_priv(hw); 1335 u32 mode; 1336 1337 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1338 "BB Switch to %s mode!\n", pi_mode ? "PI" : "SI"); 1339 mode = pi_mode ? 0x01000100 : 0x01000000; 1340 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, MASKDWORD, mode); 1341 rtl_set_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, MASKDWORD, mode); 1342} 1343 1344static void _rtl92du_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8], 1345 u8 t, bool is2t) 1346{ 1347 static const u32 adda_reg[IQK_ADDA_REG_NUM] = { 1348 RFPGA0_XCD_SWITCHCONTROL, RBLUE_TOOTH, RRX_WAIT_CCA, 1349 RTX_CCK_RFON, RTX_CCK_BBON, RTX_OFDM_RFON, RTX_OFDM_BBON, 1350 RTX_TO_RX, RTX_TO_TX, RRX_CCK, RRX_OFDM, RRX_WAIT_RIFS, 1351 RRX_TO_RX, RSTANDBY, RSLEEP, RPMPD_ANAEN 1352 }; 1353 static const u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { 1354 REG_TXPAUSE, REG_BCN_CTRL, REG_BCN_CTRL_1, REG_GPIO_MUXCFG 1355 }; 1356 static const u32 iqk_bb_reg[IQK_BB_REG_NUM] = { 1357 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE, 1358 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR, 1359 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE, 1360 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4, 1361 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1 1362 }; 1363 struct rtl_priv *rtlpriv = rtl_priv(hw); 1364 struct rtl_phy *rtlphy = &rtlpriv->phy; 1365 const u32 retrycount = 2; 1366 u8 patha_ok, pathb_ok; 1367 u32 bbvalue; 1368 u32 i; 1369 1370 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 2.4G :Start!!!\n"); 1371 if (t == 0) { 1372 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); 1373 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); 1374 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", 1375 is2t ? "2T2R" : "1T1R"); 1376 1377 /* Save ADDA parameters, turn Path A ADDA on */ 1378 rtl92d_phy_save_adda_registers(hw, adda_reg, 1379 rtlphy->adda_backup, 1380 IQK_ADDA_REG_NUM); 1381 rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, 1382 rtlphy->iqk_mac_backup); 1383 rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, 1384 rtlphy->iqk_bb_backup, 1385 IQK_BB_REG_NUM); 1386 } 1387 rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); 1388 1389 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017038); 1390 1391 if (t == 0) 1392 rtlphy->rfpi_enable = (u8)rtl_get_bbreg(hw, 1393 RFPGA0_XA_HSSIPARAMETER1, BIT(8)); 1394 1395 /* Switch BB to PI mode to do IQ Calibration. */ 1396 if (!rtlphy->rfpi_enable) 1397 _rtl92du_phy_pimode_switch(hw, true); 1398 1399 rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BCCKEN, 0x00); 1400 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); 1401 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); 1402 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); 1403 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); 1404 if (is2t) { 1405 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 1406 0x00010000); 1407 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD, 1408 0x00010000); 1409 } 1410 1411 /* MAC settings */ 1412 rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, 1413 rtlphy->iqk_mac_backup); 1414 1415 /* Page B init */ 1416 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x0f600000); 1417 if (is2t) 1418 rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x0f600000); 1419 1420 /* IQ calibration setting */ 1421 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n"); 1422 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x808000); 1423 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); 1424 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); 1425 1426 for (i = 0; i < retrycount; i++) { 1427 patha_ok = _rtl92du_phy_patha_iqk(hw, is2t); 1428 if (patha_ok == 0x03) { 1429 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1430 "Path A IQK Success!!\n"); 1431 result[t][0] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, 1432 MASK_IQK_RESULT); 1433 result[t][1] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, 1434 MASK_IQK_RESULT); 1435 result[t][2] = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, 1436 MASK_IQK_RESULT); 1437 result[t][3] = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, 1438 MASK_IQK_RESULT); 1439 break; 1440 } else if (i == (retrycount - 1) && patha_ok == 0x01) { 1441 /* Tx IQK OK */ 1442 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1443 "Path A IQK Only Tx Success!!\n"); 1444 1445 result[t][0] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, 1446 MASK_IQK_RESULT); 1447 result[t][1] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, 1448 MASK_IQK_RESULT); 1449 } 1450 } 1451 if (patha_ok == 0x00) 1452 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK failed!!\n"); 1453 1454 if (is2t) { 1455 _rtl92du_phy_patha_standby(hw); 1456 /* Turn Path B ADDA on */ 1457 rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); 1458 1459 for (i = 0; i < retrycount; i++) { 1460 pathb_ok = _rtl92du_phy_pathb_iqk(hw); 1461 if (pathb_ok == 0x03) { 1462 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1463 "Path B IQK Success!!\n"); 1464 result[t][4] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, 1465 MASK_IQK_RESULT); 1466 result[t][5] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, 1467 MASK_IQK_RESULT); 1468 result[t][6] = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, 1469 MASK_IQK_RESULT); 1470 result[t][7] = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, 1471 MASK_IQK_RESULT); 1472 break; 1473 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { 1474 /* Tx IQK OK */ 1475 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1476 "Path B Only Tx IQK Success!!\n"); 1477 result[t][4] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, 1478 MASK_IQK_RESULT); 1479 result[t][5] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, 1480 MASK_IQK_RESULT); 1481 } 1482 } 1483 if (pathb_ok == 0x00) 1484 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1485 "Path B IQK failed!!\n"); 1486 } 1487 1488 /* Back to BB mode, load original value */ 1489 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1490 "IQK:Back to BB mode, load original value!\n"); 1491 1492 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x000000); 1493 1494 if (t != 0) { 1495 /* Switch back BB to SI mode after finish IQ Calibration. */ 1496 if (!rtlphy->rfpi_enable) 1497 _rtl92du_phy_pimode_switch(hw, false); 1498 1499 /* Reload ADDA power saving parameters */ 1500 _rtl92du_phy_reload_adda_registers(hw, adda_reg, 1501 rtlphy->adda_backup, 1502 IQK_ADDA_REG_NUM); 1503 1504 /* Reload MAC parameters */ 1505 _rtl92du_phy_reload_mac_registers(hw, iqk_mac_reg, 1506 rtlphy->iqk_mac_backup); 1507 1508 if (is2t) 1509 _rtl92du_phy_reload_adda_registers(hw, iqk_bb_reg, 1510 rtlphy->iqk_bb_backup, 1511 IQK_BB_REG_NUM); 1512 else 1513 _rtl92du_phy_reload_adda_registers(hw, iqk_bb_reg, 1514 rtlphy->iqk_bb_backup, 1515 IQK_BB_REG_NUM - 1); 1516 1517 /* load 0xe30 IQC default value */ 1518 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00); 1519 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00); 1520 } 1521 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n"); 1522} 1523 1524static void _rtl92du_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw, 1525 long result[][8], u8 t) 1526{ 1527 static const u32 adda_reg[IQK_ADDA_REG_NUM] = { 1528 RFPGA0_XCD_SWITCHCONTROL, RBLUE_TOOTH, RRX_WAIT_CCA, 1529 RTX_CCK_RFON, RTX_CCK_BBON, RTX_OFDM_RFON, RTX_OFDM_BBON, 1530 RTX_TO_RX, RTX_TO_TX, RRX_CCK, RRX_OFDM, RRX_WAIT_RIFS, 1531 RRX_TO_RX, RSTANDBY, RSLEEP, RPMPD_ANAEN 1532 }; 1533 static const u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { 1534 REG_TXPAUSE, REG_BCN_CTRL, REG_BCN_CTRL_1, REG_GPIO_MUXCFG 1535 }; 1536 static const u32 iqk_bb_reg[IQK_BB_REG_NUM] = { 1537 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE, 1538 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR, 1539 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE, 1540 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4, 1541 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1 1542 }; 1543 struct rtl_priv *rtlpriv = rtl_priv(hw); 1544 struct rtl_phy *rtlphy = &rtlpriv->phy; 1545 struct rtl_hal *rtlhal = &rtlpriv->rtlhal; 1546 bool is2t = IS_92D_SINGLEPHY(rtlhal->version); 1547 u8 patha_ok, pathb_ok; 1548 bool rf_path_div; 1549 u32 bbvalue; 1550 1551 /* Note: IQ calibration must be performed after loading 1552 * PHY_REG.txt , and radio_a, radio_b.txt 1553 */ 1554 1555 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 5G NORMAL:Start!!!\n"); 1556 1557 mdelay(IQK_DELAY_TIME * 20); 1558 1559 if (t == 0) { 1560 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); 1561 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); 1562 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", 1563 is2t ? "2T2R" : "1T1R"); 1564 1565 /* Save ADDA parameters, turn Path A ADDA on */ 1566 rtl92d_phy_save_adda_registers(hw, adda_reg, 1567 rtlphy->adda_backup, 1568 IQK_ADDA_REG_NUM); 1569 rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, 1570 rtlphy->iqk_mac_backup); 1571 if (is2t) 1572 rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, 1573 rtlphy->iqk_bb_backup, 1574 IQK_BB_REG_NUM); 1575 else 1576 rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, 1577 rtlphy->iqk_bb_backup, 1578 IQK_BB_REG_NUM - 1); 1579 } 1580 1581 rf_path_div = rtl_get_bbreg(hw, 0xb30, BIT(27)); 1582 rtl92d_phy_path_adda_on(hw, adda_reg, !rf_path_div, is2t); 1583 1584 if (t == 0) 1585 rtlphy->rfpi_enable = rtl_get_bbreg(hw, 1586 RFPGA0_XA_HSSIPARAMETER1, 1587 BIT(8)); 1588 1589 /* Switch BB to PI mode to do IQ Calibration. */ 1590 if (!rtlphy->rfpi_enable) 1591 _rtl92du_phy_pimode_switch(hw, true); 1592 1593 /* MAC settings */ 1594 rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, 1595 rtlphy->iqk_mac_backup); 1596 1597 rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BCCKEN, 0x00); 1598 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); 1599 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); 1600 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); 1601 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); 1602 1603 /* Page A AP setting for IQK */ 1604 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0); 1605 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x20000000); 1606 if (is2t) { 1607 /* Page B AP setting for IQK */ 1608 rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0); 1609 rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x20000000); 1610 } 1611 1612 /* IQ calibration setting */ 1613 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n"); 1614 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x808000); 1615 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x10007c00); 1616 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); 1617 1618 patha_ok = _rtl92du_phy_patha_iqk_5g_normal(hw, is2t); 1619 if (patha_ok == 0x03) { 1620 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Success!!\n"); 1621 result[t][0] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, 1622 MASK_IQK_RESULT); 1623 result[t][1] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, 1624 MASK_IQK_RESULT); 1625 result[t][2] = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, 1626 MASK_IQK_RESULT); 1627 result[t][3] = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, 1628 MASK_IQK_RESULT); 1629 } else if (patha_ok == 0x01) { /* Tx IQK OK */ 1630 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1631 "Path A IQK Only Tx Success!!\n"); 1632 1633 result[t][0] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, 1634 MASK_IQK_RESULT); 1635 result[t][1] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, 1636 MASK_IQK_RESULT); 1637 } else { 1638 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x000000); 1639 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe70 = %#x\n", 1640 rtl_get_bbreg(hw, RRX_WAIT_CCA, MASKDWORD)); 1641 RTPRINT(rtlpriv, FINIT, INIT_IQK, "RF path A 0x0 = %#x\n", 1642 rtl_get_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK)); 1643 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x808000); 1644 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Fail!!\n"); 1645 } 1646 1647 if (is2t) { 1648 /* _rtl92d_phy_patha_standby(hw); */ 1649 /* Turn Path B ADDA on */ 1650 rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); 1651 1652 pathb_ok = _rtl92du_phy_pathb_iqk_5g_normal(hw); 1653 if (pathb_ok == 0x03) { 1654 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1655 "Path B IQK Success!!\n"); 1656 result[t][4] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, 1657 MASK_IQK_RESULT); 1658 result[t][5] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, 1659 MASK_IQK_RESULT); 1660 result[t][6] = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, 1661 MASK_IQK_RESULT); 1662 result[t][7] = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, 1663 MASK_IQK_RESULT); 1664 } else if (pathb_ok == 0x01) { /* Tx IQK OK */ 1665 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1666 "Path B Only Tx IQK Success!!\n"); 1667 result[t][4] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, 1668 MASK_IQK_RESULT); 1669 result[t][5] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, 1670 MASK_IQK_RESULT); 1671 } else { 1672 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1673 "Path B IQK failed!!\n"); 1674 } 1675 } 1676 1677 /* Back to BB mode, load original value */ 1678 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1679 "IQK:Back to BB mode, load original value!\n"); 1680 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0); 1681 1682 if (is2t) 1683 _rtl92du_phy_reload_adda_registers(hw, iqk_bb_reg, 1684 rtlphy->iqk_bb_backup, 1685 IQK_BB_REG_NUM); 1686 else 1687 _rtl92du_phy_reload_adda_registers(hw, iqk_bb_reg, 1688 rtlphy->iqk_bb_backup, 1689 IQK_BB_REG_NUM - 1); 1690 1691 /* path A IQ path to DP block */ 1692 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x010170b8); 1693 if (is2t) /* path B IQ path to DP block */ 1694 rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0x010170b8); 1695 1696 /* Reload MAC parameters */ 1697 _rtl92du_phy_reload_mac_registers(hw, iqk_mac_reg, 1698 rtlphy->iqk_mac_backup); 1699 1700 /* Switch back BB to SI mode after finish IQ Calibration. */ 1701 if (!rtlphy->rfpi_enable) 1702 _rtl92du_phy_pimode_switch(hw, false); 1703 1704 /* Reload ADDA power saving parameters */ 1705 _rtl92du_phy_reload_adda_registers(hw, adda_reg, 1706 rtlphy->adda_backup, 1707 IQK_ADDA_REG_NUM); 1708 1709 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n"); 1710} 1711 1712static bool _rtl92du_phy_simularity_compare(struct ieee80211_hw *hw, 1713 long result[][8], u8 c1, u8 c2) 1714{ 1715 struct rtl_priv *rtlpriv = rtl_priv(hw); 1716 struct rtl_hal *rtlhal = &rtlpriv->rtlhal; 1717 u32 i, j, diff, sim_bitmap, bound, u4temp = 0; 1718 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */ 1719 bool is2t = IS_92D_SINGLEPHY(rtlhal->version); 1720 bool bresult = true; 1721 1722 if (is2t) 1723 bound = 8; 1724 else 1725 bound = 4; 1726 1727 sim_bitmap = 0; 1728 1729 for (i = 0; i < bound; i++) { 1730 diff = abs_diff(result[c1][i], result[c2][i]); 1731 1732 if (diff > MAX_TOLERANCE_92D) { 1733 if ((i == 2 || i == 6) && !sim_bitmap) { 1734 if (result[c1][i] + result[c1][i + 1] == 0) 1735 final_candidate[(i / 4)] = c2; 1736 else if (result[c2][i] + result[c2][i + 1] == 0) 1737 final_candidate[(i / 4)] = c1; 1738 else 1739 sim_bitmap = sim_bitmap | (1 << i); 1740 } else { 1741 sim_bitmap = sim_bitmap | (1 << i); 1742 } 1743 } 1744 } 1745 1746 if (sim_bitmap == 0) { 1747 for (i = 0; i < (bound / 4); i++) { 1748 if (final_candidate[i] != 0xFF) { 1749 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 1750 result[3][j] = 1751 result[final_candidate[i]][j]; 1752 bresult = false; 1753 } 1754 } 1755 1756 for (i = 0; i < bound; i++) 1757 u4temp += result[c1][i] + result[c2][i]; 1758 1759 if (u4temp == 0) /* IQK fail for c1 & c2 */ 1760 bresult = false; 1761 1762 return bresult; 1763 } 1764 1765 if (!(sim_bitmap & 0x0F)) { /* path A OK */ 1766 for (i = 0; i < 4; i++) 1767 result[3][i] = result[c1][i]; 1768 } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */ 1769 for (i = 0; i < 2; i++) 1770 result[3][i] = result[c1][i]; 1771 } 1772 1773 if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */ 1774 for (i = 4; i < 8; i++) 1775 result[3][i] = result[c1][i]; 1776 } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */ 1777 for (i = 4; i < 6; i++) 1778 result[3][i] = result[c1][i]; 1779 } 1780 1781 return false; 1782} 1783 1784static void _rtl92du_phy_patha_fill_iqk_matrix_5g_normal(struct ieee80211_hw *hw, 1785 bool iqk_ok, 1786 long result[][8], 1787 u8 final_candidate, 1788 bool txonly) 1789{ 1790 struct rtl_priv *rtlpriv = rtl_priv(hw); 1791 struct rtl_hal *rtlhal = &rtlpriv->rtlhal; 1792 u32 val_x, reg; 1793 int val_y; 1794 1795 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1796 "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed"); 1797 if (iqk_ok && final_candidate != 0xFF) { 1798 val_x = result[final_candidate][0]; 1799 if ((val_x & 0x00000200) != 0) 1800 val_x = val_x | 0xFFFFFC00; 1801 1802 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x\n", val_x); 1803 rtl_set_bbreg(hw, RTX_IQK_TONE_A, 0x3FF0000, val_x); 1804 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), 0); 1805 1806 val_y = result[final_candidate][1]; 1807 if ((val_y & 0x00000200) != 0) 1808 val_y = val_y | 0xFFFFFC00; 1809 1810 /* path B IQK result + 3 */ 1811 if (rtlhal->current_bandtype == BAND_ON_5G) 1812 val_y += 3; 1813 1814 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%x\n", val_y); 1815 1816 rtl_set_bbreg(hw, RTX_IQK_TONE_A, 0x3FF, val_y); 1817 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26), 0); 1818 1819 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe30 = 0x%x\n", 1820 rtl_get_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD)); 1821 1822 if (txonly) { 1823 RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n"); 1824 return; 1825 } 1826 1827 reg = result[final_candidate][2]; 1828 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); 1829 reg = result[final_candidate][3] & 0x3F; 1830 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); 1831 reg = (result[final_candidate][3] >> 6) & 0xF; 1832 rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg); 1833 } else { 1834 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1835 "%s: Tx/Rx fail restore default value\n", __func__); 1836 1837 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x19008c00); 1838 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); 1839 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x19008c00); 1840 } 1841} 1842 1843static void _rtl92du_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw, 1844 bool iqk_ok, long result[][8], 1845 u8 final_candidate, bool txonly) 1846{ 1847 struct rtl_priv *rtlpriv = rtl_priv(hw); 1848 struct rtl_hal *rtlhal = &rtlpriv->rtlhal; 1849 u32 oldval_0, val_x, tx0_a, reg; 1850 long val_y, tx0_c; 1851 bool is2t = IS_92D_SINGLEPHY(rtlhal->version) || 1852 rtlhal->macphymode == DUALMAC_DUALPHY; 1853 1854 if (rtlhal->current_bandtype == BAND_ON_5G) { 1855 _rtl92du_phy_patha_fill_iqk_matrix_5g_normal(hw, iqk_ok, result, 1856 final_candidate, 1857 txonly); 1858 return; 1859 } 1860 1861 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1862 "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed"); 1863 if (final_candidate == 0xFF || !iqk_ok) 1864 return; 1865 1866 /* OFDM0_D */ 1867 oldval_0 = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0xffc00000); 1868 1869 val_x = result[final_candidate][0]; 1870 if ((val_x & 0x00000200) != 0) 1871 val_x = val_x | 0xFFFFFC00; 1872 1873 tx0_a = (val_x * oldval_0) >> 8; 1874 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1875 "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n", 1876 val_x, tx0_a, oldval_0); 1877 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); 1878 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), 1879 ((val_x * oldval_0 >> 7) & 0x1)); 1880 1881 val_y = result[final_candidate][1]; 1882 if ((val_y & 0x00000200) != 0) 1883 val_y = val_y | 0xFFFFFC00; 1884 1885 /* path B IQK result + 3 */ 1886 if (rtlhal->interfaceindex == 1 && 1887 rtlhal->current_bandtype == BAND_ON_5G) 1888 val_y += 3; 1889 1890 tx0_c = (val_y * oldval_0) >> 8; 1891 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1892 "Y = 0x%lx, tx0_c = 0x%lx\n", 1893 val_y, tx0_c); 1894 1895 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, (tx0_c & 0x3C0) >> 6); 1896 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, tx0_c & 0x3F); 1897 if (is2t) 1898 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26), 1899 (val_y * oldval_0 >> 7) & 0x1); 1900 1901 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n", 1902 rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 1903 MASKDWORD)); 1904 1905 if (txonly) { 1906 RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n"); 1907 return; 1908 } 1909 1910 reg = result[final_candidate][2]; 1911 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); 1912 reg = result[final_candidate][3] & 0x3F; 1913 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); 1914 reg = (result[final_candidate][3] >> 6) & 0xF; 1915 rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg); 1916} 1917 1918static void _rtl92du_phy_pathb_fill_iqk_matrix_5g_normal(struct ieee80211_hw *hw, 1919 bool iqk_ok, 1920 long result[][8], 1921 u8 final_candidate, 1922 bool txonly) 1923{ 1924 struct rtl_priv *rtlpriv = rtl_priv(hw); 1925 struct rtl_hal *rtlhal = &rtlpriv->rtlhal; 1926 u32 val_x, reg; 1927 int val_y; 1928 1929 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1930 "Path B IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed"); 1931 if (iqk_ok && final_candidate != 0xFF) { 1932 val_x = result[final_candidate][4]; 1933 if ((val_x & 0x00000200) != 0) 1934 val_x = val_x | 0xFFFFFC00; 1935 1936 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x\n", val_x); 1937 rtl_set_bbreg(hw, RTX_IQK_TONE_B, 0x3FF0000, val_x); 1938 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), 0); 1939 1940 val_y = result[final_candidate][5]; 1941 if ((val_y & 0x00000200) != 0) 1942 val_y = val_y | 0xFFFFFC00; 1943 1944 /* path B IQK result + 3 */ 1945 if (rtlhal->current_bandtype == BAND_ON_5G) 1946 val_y += 3; 1947 1948 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%x\n", val_y); 1949 1950 rtl_set_bbreg(hw, RTX_IQK_TONE_B, 0x3FF, val_y); 1951 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30), 0); 1952 1953 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe50 = 0x%x\n", 1954 rtl_get_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD)); 1955 1956 if (txonly) { 1957 RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n"); 1958 return; 1959 } 1960 1961 reg = result[final_candidate][6]; 1962 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); 1963 reg = result[final_candidate][7] & 0x3F; 1964 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); 1965 reg = (result[final_candidate][7] >> 6) & 0xF; 1966 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); 1967 } else { 1968 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1969 "%s: Tx/Rx fail restore default value\n", __func__); 1970 1971 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x19008c00); 1972 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); 1973 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x19008c00); 1974 } 1975} 1976 1977static void _rtl92du_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw, 1978 bool iqk_ok, long result[][8], 1979 u8 final_candidate, bool txonly) 1980{ 1981 struct rtl_priv *rtlpriv = rtl_priv(hw); 1982 struct rtl_hal *rtlhal = &rtlpriv->rtlhal; 1983 u32 oldval_1, val_x, tx1_a, reg; 1984 long val_y, tx1_c; 1985 1986 if (rtlhal->current_bandtype == BAND_ON_5G) { 1987 _rtl92du_phy_pathb_fill_iqk_matrix_5g_normal(hw, iqk_ok, result, 1988 final_candidate, 1989 txonly); 1990 return; 1991 } 1992 1993 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n", 1994 iqk_ok ? "Success" : "Failed"); 1995 1996 if (final_candidate == 0xFF || !iqk_ok) 1997 return; 1998 1999 oldval_1 = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0xffc00000); 2000 2001 val_x = result[final_candidate][4]; 2002 if ((val_x & 0x00000200) != 0) 2003 val_x = val_x | 0xFFFFFC00; 2004 2005 tx1_a = (val_x * oldval_1) >> 8; 2006 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n", 2007 val_x, tx1_a); 2008 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a); 2009 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), 2010 (val_x * oldval_1 >> 7) & 0x1); 2011 2012 val_y = result[final_candidate][5]; 2013 if ((val_y & 0x00000200) != 0) 2014 val_y = val_y | 0xFFFFFC00; 2015 2016 if (rtlhal->current_bandtype == BAND_ON_5G) 2017 val_y += 3; 2018 2019 tx1_c = (val_y * oldval_1) >> 8; 2020 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n", 2021 val_y, tx1_c); 2022 2023 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, (tx1_c & 0x3C0) >> 6); 2024 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, tx1_c & 0x3F); 2025 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30), 2026 (val_y * oldval_1 >> 7) & 0x1); 2027 2028 if (txonly) 2029 return; 2030 2031 reg = result[final_candidate][6]; 2032 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); 2033 reg = result[final_candidate][7] & 0x3F; 2034 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); 2035 reg = (result[final_candidate][7] >> 6) & 0xF; 2036 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); 2037} 2038 2039void rtl92du_phy_iq_calibrate(struct ieee80211_hw *hw) 2040{ 2041 long rege94, rege9c, regea4, regeac, regeb4; 2042 bool is12simular, is13simular, is23simular; 2043 struct rtl_priv *rtlpriv = rtl_priv(hw); 2044 struct rtl_hal *rtlhal = &rtlpriv->rtlhal; 2045 long regebc, regec4, regecc, regtmp = 0; 2046 struct rtl_phy *rtlphy = &rtlpriv->phy; 2047 u8 i, final_candidate, indexforchannel; 2048 bool patha_ok, pathb_ok; 2049 long result[4][8] = {}; 2050 2051 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2052 "IQK:Start!!!channel %d\n", rtlphy->current_channel); 2053 2054 final_candidate = 0xff; 2055 patha_ok = false; 2056 pathb_ok = false; 2057 is12simular = false; 2058 is23simular = false; 2059 is13simular = false; 2060 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2061 "IQK !!!currentband %d\n", rtlhal->current_bandtype); 2062 2063 for (i = 0; i < 3; i++) { 2064 if (rtlhal->current_bandtype == BAND_ON_5G) { 2065 _rtl92du_phy_iq_calibrate_5g_normal(hw, result, i); 2066 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) { 2067 if (IS_92D_SINGLEPHY(rtlhal->version)) 2068 _rtl92du_phy_iq_calibrate(hw, result, i, true); 2069 else 2070 _rtl92du_phy_iq_calibrate(hw, result, i, false); 2071 } 2072 2073 if (i == 1) { 2074 is12simular = _rtl92du_phy_simularity_compare(hw, result, 2075 0, 1); 2076 if (is12simular) { 2077 final_candidate = 0; 2078 break; 2079 } 2080 } 2081 2082 if (i == 2) { 2083 is13simular = _rtl92du_phy_simularity_compare(hw, result, 2084 0, 2); 2085 if (is13simular) { 2086 final_candidate = 0; 2087 break; 2088 } 2089 2090 is23simular = _rtl92du_phy_simularity_compare(hw, result, 2091 1, 2); 2092 if (is23simular) { 2093 final_candidate = 1; 2094 } else { 2095 for (i = 0; i < 8; i++) 2096 regtmp += result[3][i]; 2097 2098 if (regtmp != 0) 2099 final_candidate = 3; 2100 else 2101 final_candidate = 0xFF; 2102 } 2103 } 2104 } 2105 2106 for (i = 0; i < 4; i++) { 2107 rege94 = result[i][0]; 2108 rege9c = result[i][1]; 2109 regea4 = result[i][2]; 2110 regeac = result[i][3]; 2111 regeb4 = result[i][4]; 2112 regebc = result[i][5]; 2113 regec4 = result[i][6]; 2114 regecc = result[i][7]; 2115 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2116 "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n", 2117 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, 2118 regecc); 2119 } 2120 2121 if (final_candidate != 0xff) { 2122 rege94 = result[final_candidate][0]; 2123 rtlphy->reg_e94 = rege94; 2124 rege9c = result[final_candidate][1]; 2125 rtlphy->reg_e9c = rege9c; 2126 regea4 = result[final_candidate][2]; 2127 regeac = result[final_candidate][3]; 2128 regeb4 = result[final_candidate][4]; 2129 rtlphy->reg_eb4 = regeb4; 2130 regebc = result[final_candidate][5]; 2131 rtlphy->reg_ebc = regebc; 2132 regec4 = result[final_candidate][6]; 2133 regecc = result[final_candidate][7]; 2134 2135 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2136 "IQK: final_candidate is %x\n", final_candidate); 2137 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2138 "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n", 2139 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, 2140 regecc); 2141 2142 patha_ok = true; 2143 pathb_ok = true; 2144 } else { 2145 rtlphy->reg_e94 = 0x100; 2146 rtlphy->reg_eb4 = 0x100; /* X default value */ 2147 rtlphy->reg_e9c = 0x0; 2148 rtlphy->reg_ebc = 0x0; /* Y default value */ 2149 } 2150 if (rege94 != 0 /*&& regea4 != 0*/) 2151 _rtl92du_phy_patha_fill_iqk_matrix(hw, patha_ok, result, 2152 final_candidate, 2153 regea4 == 0); 2154 if (IS_92D_SINGLEPHY(rtlhal->version) && 2155 regeb4 != 0 /*&& regec4 != 0*/) 2156 _rtl92du_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result, 2157 final_candidate, 2158 regec4 == 0); 2159 2160 if (final_candidate != 0xFF) { 2161 indexforchannel = 2162 rtl92d_get_rightchnlplace_for_iqk(rtlphy->current_channel); 2163 2164 for (i = 0; i < IQK_MATRIX_REG_NUM; i++) 2165 rtlphy->iqk_matrix[indexforchannel].value[0][i] = 2166 result[final_candidate][i]; 2167 2168 rtlphy->iqk_matrix[indexforchannel].iqk_done = true; 2169 2170 rtl_dbg(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD, 2171 "IQK OK indexforchannel %d\n", indexforchannel); 2172 } 2173} 2174 2175void rtl92du_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel) 2176{ 2177 struct rtl_priv *rtlpriv = rtl_priv(hw); 2178 struct rtl_hal *rtlhal = &rtlpriv->rtlhal; 2179 struct rtl_phy *rtlphy = &rtlpriv->phy; 2180 struct rtl_mac *mac = rtl_mac(rtlpriv); 2181 u8 indexforchannel; 2182 bool need_iqk; 2183 2184 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "channel %d\n", channel); 2185 /*------Do IQK for normal chip and test chip 5G band------- */ 2186 2187 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel); 2188 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "indexforchannel %d done %d\n", 2189 indexforchannel, 2190 rtlphy->iqk_matrix[indexforchannel].iqk_done); 2191 2192 /* We need to do IQK if we're about to connect to a network on 5 GHz. 2193 * On 5 GHz a channel switch outside of scanning happens only before 2194 * connecting. 2195 */ 2196 need_iqk = !mac->act_scanning; 2197 2198 if (!rtlphy->iqk_matrix[indexforchannel].iqk_done && need_iqk) { 2199 rtl_dbg(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD, 2200 "Do IQK Matrix reg for channel:%d....\n", channel); 2201 rtl92du_phy_iq_calibrate(hw); 2202 return; 2203 } 2204 2205 /* Just load the value. */ 2206 /* 2G band just load once. */ 2207 if ((!rtlhal->load_imrandiqk_setting_for2g && indexforchannel == 0) || 2208 indexforchannel > 0) { 2209 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, 2210 "Just Read IQK Matrix reg for channel:%d....\n", 2211 channel); 2212 2213 if (rtlphy->iqk_matrix[indexforchannel].value[0][0] != 0) 2214 _rtl92du_phy_patha_fill_iqk_matrix(hw, true, 2215 rtlphy->iqk_matrix[indexforchannel].value, 0, 2216 rtlphy->iqk_matrix[indexforchannel].value[0][2] == 0); 2217 2218 if (IS_92D_SINGLEPHY(rtlhal->version) && 2219 rtlphy->iqk_matrix[indexforchannel].value[0][4] != 0) 2220 _rtl92du_phy_pathb_fill_iqk_matrix(hw, true, 2221 rtlphy->iqk_matrix[indexforchannel].value, 0, 2222 rtlphy->iqk_matrix[indexforchannel].value[0][6] == 0); 2223 } 2224 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); 2225} 2226 2227static void _rtl92du_phy_reload_lck_setting(struct ieee80211_hw *hw, u8 channel) 2228{ 2229 struct rtl_priv *rtlpriv = rtl_priv(hw); 2230 struct rtl_hal *rtlhal = &rtlpriv->rtlhal; 2231 u8 erfpath = rtlhal->current_bandtype == BAND_ON_5G ? RF90_PATH_A : 2232 IS_92D_SINGLEPHY(rtlhal->version) ? RF90_PATH_B : RF90_PATH_A; 2233 bool bneed_powerdown_radio = false; 2234 u32 u4tmp, u4regvalue; 2235 2236 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath); 2237 RTPRINT(rtlpriv, FINIT, INIT_IQK, "band type = %d\n", 2238 rtlpriv->rtlhal.current_bandtype); 2239 RTPRINT(rtlpriv, FINIT, INIT_IQK, "channel = %d\n", channel); 2240 2241 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */ 2242 u4tmp = rtlpriv->curveindex_5g[channel - 1]; 2243 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2244 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); 2245 2246 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY && 2247 rtlpriv->rtlhal.interfaceindex == 1) { 2248 bneed_powerdown_radio = 2249 rtl92du_phy_enable_anotherphy(hw, false); 2250 rtlpriv->rtlhal.during_mac1init_radioa = true; 2251 /* asume no this case */ 2252 if (bneed_powerdown_radio) 2253 rtl92d_phy_enable_rf_env(hw, erfpath, 2254 &u4regvalue); 2255 } 2256 2257 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); 2258 2259 if (bneed_powerdown_radio) { 2260 rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); 2261 rtl92du_phy_powerdown_anotherphy(hw, false); 2262 } 2263 } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) { 2264 u4tmp = rtlpriv->curveindex_2g[channel - 1]; 2265 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2266 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); 2267 2268 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY && 2269 rtlpriv->rtlhal.interfaceindex == 0) { 2270 bneed_powerdown_radio = 2271 rtl92du_phy_enable_anotherphy(hw, true); 2272 rtlpriv->rtlhal.during_mac0init_radiob = true; 2273 if (bneed_powerdown_radio) 2274 rtl92d_phy_enable_rf_env(hw, erfpath, 2275 &u4regvalue); 2276 } 2277 2278 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); 2279 2280 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2281 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", 2282 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800)); 2283 2284 if (bneed_powerdown_radio) { 2285 rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); 2286 rtl92du_phy_powerdown_anotherphy(hw, true); 2287 } 2288 } 2289 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); 2290} 2291 2292static void _rtl92du_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t) 2293{ 2294 struct rtl_priv *rtlpriv = rtl_priv(hw); 2295 struct rtl_hal *rtlhal = &rtlpriv->rtlhal; 2296 u32 curvecount_val[CV_CURVE_CNT * 2]; 2297 u16 timeout = 800, timecount = 0; 2298 u32 u4tmp, offset, rf_syn_g4[2]; 2299 u8 tmpreg, index, rf_mode[2]; 2300 u8 path = is2t ? 2 : 1; 2301 u8 i; 2302 2303 /* Check continuous TX and Packet TX */ 2304 tmpreg = rtl_read_byte(rtlpriv, 0xd03); 2305 if ((tmpreg & 0x70) != 0) 2306 /* if Deal with contisuous TX case, disable all continuous TX */ 2307 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); 2308 else 2309 /* if Deal with Packet TX case, block all queues */ 2310 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 2311 2312 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F); 2313 2314 for (index = 0; index < path; index++) { 2315 /* 1. Read original RF mode */ 2316 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; 2317 rf_mode[index] = rtl_read_byte(rtlpriv, offset); 2318 2319 /* 2. Set RF mode = standby mode */ 2320 rtl_set_rfreg(hw, (enum radio_path)index, RF_AC, 2321 RFREG_OFFSET_MASK, 0x010000); 2322 2323 rf_syn_g4[index] = rtl_get_rfreg(hw, index, RF_SYN_G4, 2324 RFREG_OFFSET_MASK); 2325 rtl_set_rfreg(hw, index, RF_SYN_G4, 0x700, 0x7); 2326 2327 /* switch CV-curve control by LC-calibration */ 2328 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, 2329 BIT(17), 0x0); 2330 2331 /* 4. Set LC calibration begin */ 2332 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW, 2333 0x08000, 0x01); 2334 } 2335 2336 for (index = 0; index < path; index++) { 2337 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6, 2338 RFREG_OFFSET_MASK); 2339 2340 while ((!(u4tmp & BIT(11))) && timecount <= timeout) { 2341 mdelay(50); 2342 timecount += 50; 2343 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, 2344 RF_SYN_G6, RFREG_OFFSET_MASK); 2345 } 2346 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2347 "PHY_LCK finish delay for %d ms=2\n", timecount); 2348 } 2349 2350 if ((tmpreg & 0x70) != 0) 2351 rtl_write_byte(rtlpriv, 0xd03, tmpreg); 2352 else /* Deal with Packet TX case */ 2353 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 2354 2355 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00); 2356 2357 for (index = 0; index < path; index++) { 2358 rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK); 2359 2360 if (index == 0 && rtlhal->interfaceindex == 0) { 2361 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2362 "path-A / 5G LCK\n"); 2363 } else { 2364 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2365 "path-B / 2.4G LCK\n"); 2366 } 2367 2368 memset(curvecount_val, 0, sizeof(curvecount_val)); 2369 2370 /* Set LC calibration off */ 2371 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW, 2372 0x08000, 0x0); 2373 2374 RTPRINT(rtlpriv, FINIT, INIT_IQK, "set RF 0x18[15] = 0\n"); 2375 2376 /* save Curve-counting number */ 2377 for (i = 0; i < CV_CURVE_CNT; i++) { 2378 u32 readval = 0, readval2 = 0; 2379 2380 rtl_set_rfreg(hw, (enum radio_path)index, 0x3F, 2381 0x7f, i); 2382 2383 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D, 2384 RFREG_OFFSET_MASK, 0x0); 2385 2386 readval = rtl_get_rfreg(hw, (enum radio_path)index, 2387 0x4F, RFREG_OFFSET_MASK); 2388 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5; 2389 2390 /* reg 0x4f [4:0] */ 2391 /* reg 0x50 [19:10] */ 2392 readval2 = rtl_get_rfreg(hw, (enum radio_path)index, 2393 0x50, 0xffc00); 2394 curvecount_val[2 * i] = (((readval & 0x1F) << 10) | 2395 readval2); 2396 } 2397 2398 if (index == 0 && rtlhal->interfaceindex == 0) 2399 rtl92d_phy_calc_curvindex(hw, targetchnl_5g, 2400 curvecount_val, 2401 true, rtlpriv->curveindex_5g); 2402 else 2403 rtl92d_phy_calc_curvindex(hw, targetchnl_2g, 2404 curvecount_val, 2405 false, rtlpriv->curveindex_2g); 2406 2407 /* switch CV-curve control mode */ 2408 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, 2409 BIT(17), 0x1); 2410 } 2411 2412 /* Restore original situation */ 2413 for (index = 0; index < path; index++) { 2414 rtl_set_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK, 2415 rf_syn_g4[index]); 2416 2417 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; 2418 rtl_write_byte(rtlpriv, offset, 0x50); 2419 rtl_write_byte(rtlpriv, offset, rf_mode[index]); 2420 } 2421 2422 _rtl92du_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel); 2423} 2424 2425void rtl92du_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) 2426{ 2427 struct rtl_priv *rtlpriv = rtl_priv(hw); 2428 struct rtl_hal *rtlhal = &rtlpriv->rtlhal; 2429 struct rtl_phy *rtlphy = &rtlpriv->phy; 2430 u32 timeout = 2000, timecount = 0; 2431 2432 while (rtlpriv->mac80211.act_scanning && timecount < timeout) { 2433 udelay(50); 2434 timecount += 50; 2435 } 2436 2437 rtlphy->lck_inprogress = true; 2438 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2439 "LCK:Start!!! currentband %x delay %d ms\n", 2440 rtlhal->current_bandtype, timecount); 2441 2442 _rtl92du_phy_lc_calibrate_sw(hw, is2t); 2443 2444 rtlphy->lck_inprogress = false; 2445 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LCK:Finish!!!\n"); 2446} 2447 2448u8 rtl92du_phy_sw_chnl(struct ieee80211_hw *hw) 2449{ 2450 struct rtl_priv *rtlpriv = rtl_priv(hw); 2451 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2452 struct rtl_phy *rtlphy = &rtlpriv->phy; 2453 u8 num_total_rfpath = rtlphy->num_total_rfpath; 2454 u8 channel = rtlphy->current_channel; 2455 u32 timeout = 1000, timecount = 0; 2456 u32 ret_value; 2457 u8 rfpath; 2458 2459 if (rtlphy->sw_chnl_inprogress) 2460 return 0; 2461 if (rtlphy->set_bwmode_inprogress) 2462 return 0; 2463 2464 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { 2465 rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD, 2466 "sw_chnl_inprogress false driver sleep or unload\n"); 2467 return 0; 2468 } 2469 2470 while (rtlphy->lck_inprogress && timecount < timeout) { 2471 mdelay(50); 2472 timecount += 50; 2473 } 2474 2475 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY && 2476 rtlhal->bandset == BAND_ON_BOTH) { 2477 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER, 2478 MASKDWORD); 2479 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0))) 2480 rtl92du_phy_switch_wirelessband(hw, BAND_ON_5G); 2481 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0))) 2482 rtl92du_phy_switch_wirelessband(hw, BAND_ON_2_4G); 2483 } 2484 2485 switch (rtlhal->current_bandtype) { 2486 case BAND_ON_5G: 2487 /* Get first channel error when change between 2488 * 5G and 2.4G band. 2489 */ 2490 if (WARN_ONCE(channel <= 14, "rtl8192du: 5G but channel<=14\n")) 2491 return 0; 2492 break; 2493 case BAND_ON_2_4G: 2494 /* Get first channel error when change between 2495 * 5G and 2.4G band. 2496 */ 2497 if (WARN_ONCE(channel > 14, "rtl8192du: 2G but channel>14\n")) 2498 return 0; 2499 break; 2500 default: 2501 WARN_ONCE(true, "rtl8192du: Invalid WirelessMode(%#x)!!\n", 2502 rtlpriv->mac80211.mode); 2503 break; 2504 } 2505 2506 rtlphy->sw_chnl_inprogress = true; 2507 2508 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, 2509 "switch to channel%d\n", rtlphy->current_channel); 2510 2511 rtl92d_phy_set_txpower_level(hw, channel); 2512 2513 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { 2514 u32p_replace_bits(&rtlphy->rfreg_chnlval[rfpath], 2515 channel, 0xff); 2516 2517 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) { 2518 if (channel > 99) 2519 rtlphy->rfreg_chnlval[rfpath] |= (BIT(18)); 2520 else 2521 rtlphy->rfreg_chnlval[rfpath] &= ~BIT(18); 2522 rtlphy->rfreg_chnlval[rfpath] |= (BIT(16) | BIT(8)); 2523 } else { 2524 rtlphy->rfreg_chnlval[rfpath] &= 2525 ~(BIT(8) | BIT(16) | BIT(18)); 2526 } 2527 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, RFREG_OFFSET_MASK, 2528 rtlphy->rfreg_chnlval[rfpath]); 2529 2530 _rtl92du_phy_reload_imr_setting(hw, channel, rfpath); 2531 } 2532 2533 _rtl92du_phy_switch_rf_setting(hw, channel); 2534 2535 /* do IQK when all parameters are ready */ 2536 rtl92du_phy_reload_iqk_setting(hw, channel); 2537 2538 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 2539 rtlphy->sw_chnl_inprogress = false; 2540 return 1; 2541} 2542 2543static void _rtl92du_phy_set_rfon(struct ieee80211_hw *hw) 2544{ 2545 struct rtl_priv *rtlpriv = rtl_priv(hw); 2546 2547 /* a. SYS_CLKR 0x08[11] = 1 restore MAC clock */ 2548 /* b. SPS_CTRL 0x11[7:0] = 0x2b */ 2549 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) 2550 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 2551 2552 /* c. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */ 2553 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 2554 2555 /* RF_ON_EXCEP(d~g): */ 2556 /* d. APSD_CTRL 0x600[7:0] = 0x00 */ 2557 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); 2558 2559 /* e. SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function again */ 2560 /* f. SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function*/ 2561 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 2562 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 2563 2564 /* g. txpause 0x522[7:0] = 0x00 enable mac tx queue */ 2565 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 2566} 2567 2568static void _rtl92du_phy_set_rfsleep(struct ieee80211_hw *hw) 2569{ 2570 struct rtl_priv *rtlpriv = rtl_priv(hw); 2571 u32 u4btmp; 2572 u8 retry = 5; 2573 2574 /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */ 2575 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 2576 2577 /* b. RF path 0 offset 0x00 = 0x00 disable RF */ 2578 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 2579 2580 /* c. APSD_CTRL 0x600[7:0] = 0x40 */ 2581 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 2582 2583 /* d. APSD_CTRL 0x600[7:0] = 0x00 2584 * APSD_CTRL 0x600[7:0] = 0x00 2585 * RF path 0 offset 0x00 = 0x00 2586 * APSD_CTRL 0x600[7:0] = 0x40 2587 */ 2588 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); 2589 while (u4btmp != 0 && retry > 0) { 2590 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0); 2591 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 2592 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 2593 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); 2594 retry--; 2595 } 2596 if (retry == 0) { 2597 /* Jump out the LPS turn off sequence to RF_ON_EXCEP */ 2598 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); 2599 2600 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 2601 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 2602 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 2603 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 2604 "Fail !!! Switch RF timeout\n"); 2605 return; 2606 } 2607 2608 /* e. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */ 2609 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 2610 2611 /* f. SPS_CTRL 0x11[7:0] = 0x22 */ 2612 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) 2613 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); 2614} 2615 2616bool rtl92du_phy_set_rf_power_state(struct ieee80211_hw *hw, 2617 enum rf_pwrstate rfpwr_state) 2618{ 2619 struct rtl_priv *rtlpriv = rtl_priv(hw); 2620 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); 2621 struct rtl_mac *mac = rtl_mac(rtlpriv); 2622 bool bresult = true; 2623 2624 if (rfpwr_state == ppsc->rfpwr_state) 2625 return false; 2626 2627 switch (rfpwr_state) { 2628 case ERFON: 2629 if (ppsc->rfpwr_state == ERFOFF && 2630 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 2631 u32 initializecount = 0; 2632 bool rtstatus; 2633 2634 do { 2635 initializecount++; 2636 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 2637 "IPS Set eRf nic enable\n"); 2638 rtstatus = rtl_ps_enable_nic(hw); 2639 } while (!rtstatus && (initializecount < 10)); 2640 2641 RT_CLEAR_PS_LEVEL(ppsc, 2642 RT_RF_OFF_LEVL_HALT_NIC); 2643 } else { 2644 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 2645 "awake, slept:%d ms state_inap:%x\n", 2646 jiffies_to_msecs(jiffies - 2647 ppsc->last_sleep_jiffies), 2648 rtlpriv->psc.state_inap); 2649 ppsc->last_awake_jiffies = jiffies; 2650 _rtl92du_phy_set_rfon(hw); 2651 } 2652 2653 if (mac->link_state == MAC80211_LINKED) 2654 rtlpriv->cfg->ops->led_control(hw, LED_CTL_LINK); 2655 else 2656 rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK); 2657 break; 2658 case ERFOFF: 2659 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) { 2660 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 2661 "IPS Set eRf nic disable\n"); 2662 rtl_ps_disable_nic(hw); 2663 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2664 } else { 2665 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 2666 rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK); 2667 else 2668 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 2669 } 2670 break; 2671 case ERFSLEEP: 2672 if (ppsc->rfpwr_state == ERFOFF) 2673 return false; 2674 2675 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 2676 "sleep awakened:%d ms state_inap:%x\n", 2677 jiffies_to_msecs(jiffies - 2678 ppsc->last_awake_jiffies), 2679 rtlpriv->psc.state_inap); 2680 ppsc->last_sleep_jiffies = jiffies; 2681 _rtl92du_phy_set_rfsleep(hw); 2682 break; 2683 default: 2684 pr_err("switch case %#x not processed\n", 2685 rfpwr_state); 2686 return false; 2687 } 2688 2689 if (bresult) 2690 ppsc->rfpwr_state = rfpwr_state; 2691 2692 return bresult; 2693} 2694 2695void rtl92du_phy_set_poweron(struct ieee80211_hw *hw) 2696{ 2697 struct rtl_priv *rtlpriv = rtl_priv(hw); 2698 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2699 u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1); 2700 u8 value8; 2701 u16 i; 2702 2703 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ 2704 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 2705 value8 = rtl_read_byte(rtlpriv, mac_reg); 2706 value8 |= BIT(1); 2707 rtl_write_byte(rtlpriv, mac_reg, value8); 2708 } else { 2709 value8 = rtl_read_byte(rtlpriv, mac_reg); 2710 value8 &= ~BIT(1); 2711 rtl_write_byte(rtlpriv, mac_reg, value8); 2712 } 2713 2714 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) { 2715 value8 = rtl_read_byte(rtlpriv, REG_MAC0); 2716 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON); 2717 } else { 2718 mutex_lock(rtlpriv->mutex_for_power_on_off); 2719 if (rtlhal->interfaceindex == 0) { 2720 value8 = rtl_read_byte(rtlpriv, REG_MAC0); 2721 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON); 2722 } else { 2723 value8 = rtl_read_byte(rtlpriv, REG_MAC1); 2724 rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON); 2725 } 2726 value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); 2727 mutex_unlock(rtlpriv->mutex_for_power_on_off); 2728 2729 for (i = 0; i < 200; i++) { 2730 if ((value8 & BIT(7)) == 0) 2731 break; 2732 2733 udelay(500); 2734 mutex_lock(rtlpriv->mutex_for_power_on_off); 2735 value8 = rtl_read_byte(rtlpriv, 2736 REG_POWER_OFF_IN_PROCESS); 2737 mutex_unlock(rtlpriv->mutex_for_power_on_off); 2738 } 2739 if (i == 200) 2740 WARN_ONCE(true, "rtl8192du: Another mac power off over time\n"); 2741 } 2742} 2743 2744void rtl92du_update_bbrf_configuration(struct ieee80211_hw *hw) 2745{ 2746 struct rtl_priv *rtlpriv = rtl_priv(hw); 2747 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); 2748 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2749 struct rtl_phy *rtlphy = &rtlpriv->phy; 2750 u8 rfpath, i; 2751 2752 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n"); 2753 /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */ 2754 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 2755 /* r_select_5G for path_A/B, 0x878 */ 2756 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0); 2757 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0); 2758 if (rtlhal->macphymode != DUALMAC_DUALPHY) { 2759 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0); 2760 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0); 2761 } 2762 2763 /* rssi_table_select: index 0 for 2.4G. 1~3 for 5G, 0xc78 */ 2764 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0); 2765 2766 /* fc_area 0xd2c */ 2767 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0); 2768 2769 /* 5G LAN ON */ 2770 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa); 2771 2772 /* TX BB gain shift*1, Just for testchip, 0xc80, 0xc88 */ 2773 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, 0x40000100); 2774 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, 0x40000100); 2775 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 2776 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 2777 BIT(10) | BIT(6) | BIT(5), 2778 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) | 2779 (rtlefuse->eeprom_c9 & BIT(1)) | 2780 ((rtlefuse->eeprom_cc & BIT(1)) << 4)); 2781 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 2782 BIT(10) | BIT(6) | BIT(5), 2783 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) | 2784 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | 2785 ((rtlefuse->eeprom_cc & BIT(0)) << 5)); 2786 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0); 2787 2788 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017038); 2789 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x0f600000); 2790 } else { 2791 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 2792 BIT(26) | BIT(22) | BIT(21) | BIT(10) | 2793 BIT(6) | BIT(5), 2794 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) | 2795 (rtlefuse->eeprom_c9 & BIT(1)) | 2796 ((rtlefuse->eeprom_cc & BIT(1)) << 4) | 2797 ((rtlefuse->eeprom_c9 & BIT(7)) << 9) | 2798 ((rtlefuse->eeprom_c9 & BIT(5)) << 12) | 2799 ((rtlefuse->eeprom_cc & BIT(3)) << 18)); 2800 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 2801 BIT(10) | BIT(6) | BIT(5), 2802 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) | 2803 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | 2804 ((rtlefuse->eeprom_cc & BIT(0)) << 5)); 2805 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 2806 BIT(10) | BIT(6) | BIT(5), 2807 ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) | 2808 ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) | 2809 ((rtlefuse->eeprom_cc & BIT(2)) << 3)); 2810 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, 2811 BIT(31) | BIT(15), 0); 2812 2813 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017038); 2814 rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0x01017038); 2815 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x0f600000); 2816 rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x0f600000); 2817 } 2818 /* 1.5V_LDO */ 2819 } else { 2820 /* r_select_5G for path_A/B */ 2821 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1); 2822 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1); 2823 if (rtlhal->macphymode != DUALMAC_DUALPHY) { 2824 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1); 2825 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1); 2826 } 2827 2828 /* rssi_table_select: index 0 for 2.4G. 1~3 for 5G */ 2829 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1); 2830 2831 /* fc_area */ 2832 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1); 2833 2834 /* 5G LAN ON */ 2835 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0); 2836 2837 /* TX BB gain shift, Just for testchip, 0xc80, 0xc88 */ 2838 if (rtlefuse->internal_pa_5g[rtlhal->interfaceindex]) 2839 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, 2840 0x2d4000b5); 2841 else 2842 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, 2843 0x20000080); 2844 2845 if (rtlhal->macphymode != DUALMAC_DUALPHY) { 2846 if (rtlefuse->internal_pa_5g[1]) 2847 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 2848 MASKDWORD, 0x2d4000b5); 2849 else 2850 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 2851 MASKDWORD, 0x20000080); 2852 } 2853 2854 rtl_set_bbreg(hw, 0xB30, BIT(27), 0); 2855 2856 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 2857 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 2858 BIT(10) | BIT(6) | BIT(5), 2859 (rtlefuse->eeprom_cc & BIT(5))); 2860 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 2861 ((rtlefuse->eeprom_cc & BIT(4)) >> 4)); 2862 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 2863 (rtlefuse->eeprom_cc & BIT(4)) >> 4); 2864 2865 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017098); 2866 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x20000000); 2867 } else { 2868 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 2869 BIT(26) | BIT(22) | BIT(21) | BIT(10) | 2870 BIT(6) | BIT(5), 2871 (rtlefuse->eeprom_cc & BIT(5)) | 2872 ((rtlefuse->eeprom_cc & BIT(7)) << 14)); 2873 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 2874 ((rtlefuse->eeprom_cc & BIT(4)) >> 4)); 2875 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), 2876 ((rtlefuse->eeprom_cc & BIT(6)) >> 6)); 2877 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, 2878 BIT(31) | BIT(15), 2879 ((rtlefuse->eeprom_cc & BIT(4)) >> 4) | 2880 ((rtlefuse->eeprom_cc & BIT(6)) << 10)); 2881 2882 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017098); 2883 rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0x01017098); 2884 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x20000000); 2885 rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x20000000); 2886 } 2887 } 2888 2889 /* update IQK related settings */ 2890 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); 2891 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); 2892 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 0x00); 2893 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) | 2894 BIT(26) | BIT(24), 0x00); 2895 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 0x00); 2896 rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, 0x00); 2897 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00); 2898 2899 /* Update RF */ 2900 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; 2901 rfpath++) { 2902 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 2903 /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ 2904 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) | 2905 BIT(18) | 0xff, 1); 2906 2907 /* RF0x0b[16:14] =3b'111 */ 2908 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, 2909 0x1c000, 0x07); 2910 } else { 2911 /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ 2912 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, 2913 0x97524); 2914 } 2915 2916 /* Set right channel on RF reg0x18 for another mac. */ 2917 if (rtlhal->interfaceindex == 0 && rtlhal->bandset == BAND_ON_2_4G) { 2918 /* Set MAC1 default channel if MAC1 not up. */ 2919 if (!(rtl_read_byte(rtlpriv, REG_MAC1) & MAC1_ON)) { 2920 rtl92du_phy_enable_anotherphy(hw, true); 2921 rtlhal->during_mac0init_radiob = true; 2922 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, 2923 RFREG_OFFSET_MASK, 0x97524); 2924 rtl92du_phy_powerdown_anotherphy(hw, true); 2925 } 2926 } else if (rtlhal->interfaceindex == 1 && rtlhal->bandset == BAND_ON_5G) { 2927 /* Set MAC0 default channel */ 2928 if (!(rtl_read_byte(rtlpriv, REG_MAC0) & MAC0_ON)) { 2929 rtl92du_phy_enable_anotherphy(hw, false); 2930 rtlhal->during_mac1init_radioa = true; 2931 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, 2932 RFREG_OFFSET_MASK, 0x87401); 2933 rtl92du_phy_powerdown_anotherphy(hw, false); 2934 } 2935 } 2936 } 2937 2938 /* Update for all band. */ 2939 /* DMDP */ 2940 if (rtlphy->rf_type == RF_1T1R) { 2941 /* Use antenna 0, 0xc04, 0xd04 */ 2942 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11); 2943 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1); 2944 2945 /* enable ad/da clock1 for dual-phy reg0x888 */ 2946 if (rtlhal->interfaceindex == 0) { 2947 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | 2948 BIT(13), 0x3); 2949 } else if (rtl92du_phy_enable_anotherphy(hw, false)) { 2950 rtlhal->during_mac1init_radioa = true; 2951 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, 2952 BIT(12) | BIT(13), 0x3); 2953 rtl92du_phy_powerdown_anotherphy(hw, false); 2954 } 2955 2956 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(19) | BIT(20), 0x0); 2957 } else { 2958 /* Single PHY */ 2959 /* Use antenna 0 & 1, 0xc04, 0xd04 */ 2960 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33); 2961 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3); 2962 /* disable ad/da clock1,0x888 */ 2963 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0); 2964 2965 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(19) | BIT(20), 0x1); 2966 } 2967 2968 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; 2969 rfpath++) { 2970 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath, 2971 RF_CHNLBW, 2972 RFREG_OFFSET_MASK); 2973 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C, 2974 RFREG_OFFSET_MASK); 2975 } 2976 2977 for (i = 0; i < 2; i++) 2978 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n", 2979 rtlphy->rfreg_chnlval[i]); 2980 2981 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<==\n"); 2982} 2983 2984bool rtl92du_phy_check_poweroff(struct ieee80211_hw *hw) 2985{ 2986 struct rtl_priv *rtlpriv = rtl_priv(hw); 2987 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2988 u8 u1btmp; 2989 2990 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) { 2991 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); 2992 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & ~MAC0_ON); 2993 return true; 2994 } 2995 2996 mutex_lock(rtlpriv->mutex_for_power_on_off); 2997 if (rtlhal->interfaceindex == 0) { 2998 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); 2999 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & ~MAC0_ON); 3000 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1); 3001 u1btmp &= MAC1_ON; 3002 } else { 3003 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1); 3004 rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & ~MAC1_ON); 3005 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); 3006 u1btmp &= MAC0_ON; 3007 } 3008 if (u1btmp) { 3009 mutex_unlock(rtlpriv->mutex_for_power_on_off); 3010 return false; 3011 } 3012 u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); 3013 u1btmp |= BIT(7); 3014 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp); 3015 mutex_unlock(rtlpriv->mutex_for_power_on_off); 3016 3017 return true; 3018} 3019 3020void rtl92du_phy_init_pa_bias(struct ieee80211_hw *hw) 3021{ 3022 struct rtl_priv *rtlpriv = rtl_priv(hw); 3023 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 3024 bool is_single_mac = rtlhal->macphymode == SINGLEMAC_SINGLEPHY; 3025 enum radio_path rf_path; 3026 u8 val8; 3027 3028 read_efuse_byte(hw, 0x3FA, &val8); 3029 3030 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "%s: 0x3FA %#x\n", 3031 __func__, val8); 3032 3033 if (!(val8 & BIT(0)) && (is_single_mac || rtlhal->interfaceindex == 0)) { 3034 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, 0x07401); 3035 rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x70000); 3036 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x0F425); 3037 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x4F425); 3038 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x8F425); 3039 3040 /* Back to RX Mode */ 3041 rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x30000); 3042 3043 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "2G PA BIAS path A\n"); 3044 } 3045 3046 if (!(val8 & BIT(1)) && (is_single_mac || rtlhal->interfaceindex == 1)) { 3047 rf_path = rtlhal->interfaceindex == 1 ? RF90_PATH_A : RF90_PATH_B; 3048 3049 rtl_set_rfreg(hw, rf_path, RF_CHNLBW, RFREG_OFFSET_MASK, 0x07401); 3050 rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x70000); 3051 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x0F425); 3052 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x4F425); 3053 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x8F425); 3054 3055 /* Back to RX Mode */ 3056 rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x30000); 3057 3058 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "2G PA BIAS path B\n"); 3059 } 3060 3061 if (!(val8 & BIT(2)) && (is_single_mac || rtlhal->interfaceindex == 0)) { 3062 /* 5GL_channel */ 3063 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, 0x17524); 3064 rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x70000); 3065 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x0F496); 3066 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x4F496); 3067 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x8F496); 3068 3069 /* 5GM_channel */ 3070 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, 0x37564); 3071 rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x70000); 3072 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x0F496); 3073 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x4F496); 3074 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x8F496); 3075 3076 /* 5GH_channel */ 3077 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, 0x57595); 3078 rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x70000); 3079 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x0F496); 3080 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x4F496); 3081 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x8F496); 3082 3083 /* Back to RX Mode */ 3084 rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x30000); 3085 3086 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "5G PA BIAS path A\n"); 3087 } 3088 3089 if (!(val8 & BIT(3)) && (is_single_mac || rtlhal->interfaceindex == 1)) { 3090 rf_path = rtlhal->interfaceindex == 1 ? RF90_PATH_A : RF90_PATH_B; 3091 3092 /* 5GL_channel */ 3093 rtl_set_rfreg(hw, rf_path, RF_CHNLBW, RFREG_OFFSET_MASK, 0x17524); 3094 rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x70000); 3095 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x0F496); 3096 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x4F496); 3097 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x8F496); 3098 3099 /* 5GM_channel */ 3100 rtl_set_rfreg(hw, rf_path, RF_CHNLBW, RFREG_OFFSET_MASK, 0x37564); 3101 rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x70000); 3102 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x0F496); 3103 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x4F496); 3104 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x8F496); 3105 3106 /* 5GH_channel */ 3107 rtl_set_rfreg(hw, rf_path, RF_CHNLBW, RFREG_OFFSET_MASK, 0x57595); 3108 rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x70000); 3109 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x0F496); 3110 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x4F496); 3111 rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x8F496); 3112 3113 /* Back to RX Mode */ 3114 rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x30000); 3115 3116 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "5G PA BIAS path B\n"); 3117 } 3118}
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