trx.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright(c) 2009-2012  Realtek Corporation.*/
  3
  4#ifndef __RTL92DE_TRX_H__
  5#define __RTL92DE_TRX_H__
  6
  7#define TX_DESC_SIZE				64
  8#define TX_DESC_AGGR_SUBFRAME_SIZE		32
  9
 10#define RX_DESC_SIZE				32
 11
 12#define	TX_DESC_NEXT_DESC_OFFSET		40
 13#define USB_HWDESC_HEADER_LEN			32
 14#define CRCLENGTH				4
 15
 16static inline void clear_pci_tx_desc_content(__le32 *__pdesc, u32 _size)
 17{
 18	memset((void *)__pdesc, 0,
 19	       min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET));
 20}
 21
 22struct tx_desc_92d {
 23	u32 pktsize:16;
 24	u32 offset:8;
 25	u32 bmc:1;
 26	u32 htc:1;
 27	u32 lastseg:1;
 28	u32 firstseg:1;
 29	u32 linip:1;
 30	u32 noacm:1;
 31	u32 gf:1;
 32	u32 own:1;
 33
 34	u32 macid:5;
 35	u32 agg_en:1;
 36	u32 bk:1;
 37	u32 rdg_en:1;
 38	u32 queuesel:5;
 39	u32 rd_nav_ext:1;
 40	u32 lsig_txop_en:1;
 41	u32 pifs:1;
 42	u32 rateid:4;
 43	u32 nav_usehdr:1;
 44	u32 en_descid:1;
 45	u32 sectype:2;
 46	u32 pktoffset:8;
 47
 48	u32 rts_rc:6;
 49	u32 data_rc:6;
 50	u32 rsvd0:2;
 51	u32 bar_retryht:2;
 52	u32 rsvd1:1;
 53	u32 morefrag:1;
 54	u32 raw:1;
 55	u32 ccx:1;
 56	u32 ampdudensity:3;
 57	u32 rsvd2:1;
 58	u32 ant_sela:1;
 59	u32 ant_selb:1;
 60	u32 txant_cck:2;
 61	u32 txant_l:2;
 62	u32 txant_ht:2;
 63
 64	u32 nextheadpage:8;
 65	u32 tailpage:8;
 66	u32 seq:12;
 67	u32 pktid:4;
 68
 69	u32 rtsrate:5;
 70	u32 apdcfe:1;
 71	u32 qos:1;
 72	u32 hwseq_enable:1;
 73	u32 userrate:1;
 74	u32 dis_rtsfb:1;
 75	u32 dis_datafb:1;
 76	u32 cts2self:1;
 77	u32 rts_en:1;
 78	u32 hwrts_en:1;
 79	u32 portid:1;
 80	u32 rsvd3:3;
 81	u32 waitdcts:1;
 82	u32 cts2ap_en:1;
 83	u32 txsc:2;
 84	u32 stbc:2;
 85	u32 txshort:1;
 86	u32 txbw:1;
 87	u32 rtsshort:1;
 88	u32 rtsbw:1;
 89	u32 rtssc:2;
 90	u32 rtsstbc:2;
 91
 92	u32 txrate:6;
 93	u32 shortgi:1;
 94	u32 ccxt:1;
 95	u32 txrate_fb_lmt:5;
 96	u32 rtsrate_fb_lmt:4;
 97	u32 retrylmt_en:1;
 98	u32 txretrylmt:6;
 99	u32 usb_txaggnum:8;
100
101	u32 txagca:5;
102	u32 txagcb:5;
103	u32 usemaxlen:1;
104	u32 maxaggnum:5;
105	u32 mcsg1maxlen:4;
106	u32 mcsg2maxlen:4;
107	u32 mcsg3maxlen:4;
108	u32 mcs7sgimaxlen:4;
109
110	u32 txbuffersize:16;
111	u32 mcsg4maxlen:4;
112	u32 mcsg5maxlen:4;
113	u32 mcsg6maxlen:4;
114	u32 mcsg15sgimaxlen:4;
115
116	u32 txbuffaddr;
117	u32 txbufferaddr64;
118	u32 nextdescaddress;
119	u32 nextdescaddress64;
120
121	u32 reserve_pass_pcie_mm_limit[4];
122} __packed;
123
124void rtl92de_tx_fill_desc(struct ieee80211_hw *hw,
125			  struct ieee80211_hdr *hdr, u8 *pdesc,
126			  u8 *pbd_desc_tx, struct ieee80211_tx_info *info,
127			  struct ieee80211_sta *sta,
128			  struct sk_buff *skb, u8 hw_queue,
129			  struct rtl_tcb_desc *ptcb_desc);
130bool rtl92de_is_tx_desc_closed(struct ieee80211_hw *hw,
131			       u8 hw_queue, u16 index);
132void rtl92de_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
133void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
134			     struct sk_buff *skb);
135
136#endif