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phy.c
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linux-6.19.14/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c
1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4#include "../wifi.h" 5#include "../pci.h" 6#include "../ps.h" 7#include "../core.h" 8#include "../rtl8192d/reg.h" 9#include "../rtl8192d/def.h" 10#include "../rtl8192d/dm_common.h" 11#include "../rtl8192d/phy_common.h" 12#include "../rtl8192d/rf_common.h" 13#include "phy.h" 14#include "rf.h" 15#include "dm.h" 16#include "table.h" 17#include "sw.h" 18#include "hw.h" 19 20#define MAX_RF_IMR_INDEX 12 21#define MAX_RF_IMR_INDEX_NORMAL 13 22#define RF_REG_NUM_FOR_C_CUT_5G 6 23#define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA 7 24#define RF_REG_NUM_FOR_C_CUT_2G 5 25#define RF_CHNL_NUM_5G 19 26#define RF_CHNL_NUM_5G_40M 17 27 28static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = { 29 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0 30}; 31 32static u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = { 33 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6 34}; 35 36static u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = { 37 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8 38}; 39 40static u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = { 41 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E 42}; 43 44static u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = { 45 BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1), 46 BIT(10) | BIT(9), 47 BIT(18) | BIT(17) | BIT(16) | BIT(1), 48 BIT(2) | BIT(1), 49 BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11) 50}; 51 52static u8 rf_chnl_5g[RF_CHNL_NUM_5G] = { 53 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 54 112, 116, 120, 124, 128, 132, 136, 140 55}; 56 57static u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = { 58 38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114, 59 118, 122, 126, 130, 134, 138 60}; 61static u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = { 62 {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04}, 63 {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04}, 64 {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04}, 65 {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04}, 66 {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04} 67}; 68 69static u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = { 70 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}, 71 {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840}, 72 {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41} 73}; 74 75static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF; 76 77static u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = { 78 {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12}, 79 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52}, 80 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12} 81}; 82 83/* [mode][patha+b][reg] */ 84static u32 rf_imr_param_normal[1][3][MAX_RF_IMR_INDEX_NORMAL] = { 85 { 86 /* channel 1-14. */ 87 { 88 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0, 89 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff 90 }, 91 /* path 36-64 */ 92 { 93 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000, 94 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090, 95 0x32c9a 96 }, 97 /* 100 -165 */ 98 { 99 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000, 100 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a 101 } 102 } 103}; 104 105static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0}; 106 107static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0}; 108 109static u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = { 110 25141, 25116, 25091, 25066, 25041, 111 25016, 24991, 24966, 24941, 24917, 112 24892, 24867, 24843, 24818, 24794, 113 24770, 24765, 24721, 24697, 24672, 114 24648, 24624, 24600, 24576, 24552, 115 24528, 24504, 24480, 24457, 24433, 116 24409, 24385, 24362, 24338, 24315, 117 24291, 24268, 24245, 24221, 24198, 118 24175, 24151, 24128, 24105, 24082, 119 24059, 24036, 24013, 23990, 23967, 120 23945, 23922, 23899, 23876, 23854, 121 23831, 23809, 23786, 23764, 23741, 122 23719, 23697, 23674, 23652, 23630, 123 23608, 23586, 23564, 23541, 23519, 124 23498, 23476, 23454, 23432, 23410, 125 23388, 23367, 23345, 23323, 23302, 126 23280, 23259, 23237, 23216, 23194, 127 23173, 23152, 23130, 23109, 23088, 128 23067, 23046, 23025, 23003, 22982, 129 22962, 22941, 22920, 22899, 22878, 130 22857, 22837, 22816, 22795, 22775, 131 22754, 22733, 22713, 22692, 22672, 132 22652, 22631, 22611, 22591, 22570, 133 22550, 22530, 22510, 22490, 22469, 134 22449, 22429, 22409, 22390, 22370, 135 22350, 22336, 22310, 22290, 22271, 136 22251, 22231, 22212, 22192, 22173, 137 22153, 22134, 22114, 22095, 22075, 138 22056, 22037, 22017, 21998, 21979, 139 21960, 21941, 21921, 21902, 21883, 140 21864, 21845, 21826, 21807, 21789, 141 21770, 21751, 21732, 21713, 21695, 142 21676, 21657, 21639, 21620, 21602, 143 21583, 21565, 21546, 21528, 21509, 144 21491, 21473, 21454, 21436, 21418, 145 21400, 21381, 21363, 21345, 21327, 146 21309, 21291, 21273, 21255, 21237, 147 21219, 21201, 21183, 21166, 21148, 148 21130, 21112, 21095, 21077, 21059, 149 21042, 21024, 21007, 20989, 20972, 150 25679, 25653, 25627, 25601, 25575, 151 25549, 25523, 25497, 25471, 25446, 152 25420, 25394, 25369, 25343, 25318, 153 25292, 25267, 25242, 25216, 25191, 154 25166 155}; 156 157/* channel 1~14 */ 158static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = { 159 26084, 26030, 25976, 25923, 25869, 25816, 25764, 160 25711, 25658, 25606, 25554, 25502, 25451, 25328 161}; 162 163u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) 164{ 165 struct rtl_priv *rtlpriv = rtl_priv(hw); 166 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 167 u32 returnvalue, originalvalue, bitshift; 168 169 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n", 170 regaddr, bitmask); 171 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) { 172 u8 dbi_direct = 0; 173 174 /* mac1 use phy0 read radio_b. */ 175 /* mac0 use phy1 read radio_b. */ 176 if (rtlhal->during_mac1init_radioa) 177 dbi_direct = BIT(3); 178 else if (rtlhal->during_mac0init_radiob) 179 dbi_direct = BIT(3) | BIT(2); 180 originalvalue = rtl92de_read_dword_dbi(hw, (u16)regaddr, 181 dbi_direct); 182 } else { 183 originalvalue = rtl_read_dword(rtlpriv, regaddr); 184 } 185 bitshift = calculate_bit_shift(bitmask); 186 returnvalue = (originalvalue & bitmask) >> bitshift; 187 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 188 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", 189 bitmask, regaddr, originalvalue); 190 return returnvalue; 191} 192 193void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw, 194 u32 regaddr, u32 bitmask, u32 data) 195{ 196 struct rtl_priv *rtlpriv = rtl_priv(hw); 197 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 198 u8 dbi_direct = 0; 199 u32 originalvalue, bitshift; 200 201 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 202 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 203 regaddr, bitmask, data); 204 if (rtlhal->during_mac1init_radioa) 205 dbi_direct = BIT(3); 206 else if (rtlhal->during_mac0init_radiob) 207 /* mac0 use phy1 write radio_b. */ 208 dbi_direct = BIT(3) | BIT(2); 209 if (bitmask != MASKDWORD) { 210 if (rtlhal->during_mac1init_radioa || 211 rtlhal->during_mac0init_radiob) 212 originalvalue = rtl92de_read_dword_dbi(hw, 213 (u16) regaddr, 214 dbi_direct); 215 else 216 originalvalue = rtl_read_dword(rtlpriv, regaddr); 217 bitshift = calculate_bit_shift(bitmask); 218 data = ((originalvalue & (~bitmask)) | (data << bitshift)); 219 } 220 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) 221 rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct); 222 else 223 rtl_write_dword(rtlpriv, regaddr, data); 224 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 225 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 226 regaddr, bitmask, data); 227} 228 229bool rtl92d_phy_mac_config(struct ieee80211_hw *hw) 230{ 231 struct rtl_priv *rtlpriv = rtl_priv(hw); 232 u32 i; 233 u32 arraylength; 234 u32 *ptrarray; 235 236 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n"); 237 arraylength = MAC_2T_ARRAYLENGTH; 238 ptrarray = rtl8192de_mac_2tarray; 239 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Img:Rtl819XMAC_Array\n"); 240 for (i = 0; i < arraylength; i = i + 2) 241 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]); 242 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) { 243 /* improve 2-stream TX EVM */ 244 /* rtl_write_byte(rtlpriv, 0x14,0x71); */ 245 /* AMPDU aggregation number 9 */ 246 /* rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */ 247 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B); 248 } else { 249 /* 92D need to test to decide the num. */ 250 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07); 251 } 252 return true; 253} 254 255static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, 256 u8 configtype) 257{ 258 int i; 259 u32 *phy_regarray_table; 260 u32 *agctab_array_table = NULL; 261 u32 *agctab_5garray_table; 262 u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen; 263 struct rtl_priv *rtlpriv = rtl_priv(hw); 264 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 265 266 /* Normal chip,Mac0 use AGC_TAB.txt for 2G and 5G band. */ 267 if (rtlhal->interfaceindex == 0) { 268 agctab_arraylen = AGCTAB_ARRAYLENGTH; 269 agctab_array_table = rtl8192de_agctab_array; 270 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 271 " ===> phy:MAC0, Rtl819XAGCTAB_Array\n"); 272 } else { 273 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 274 agctab_arraylen = AGCTAB_2G_ARRAYLENGTH; 275 agctab_array_table = rtl8192de_agctab_2garray; 276 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 277 " ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n"); 278 } else { 279 agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH; 280 agctab_5garray_table = rtl8192de_agctab_5garray; 281 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 282 " ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n"); 283 284 } 285 } 286 phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH; 287 phy_regarray_table = rtl8192de_phy_reg_2tarray; 288 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 289 " ===> phy:Rtl819XPHY_REG_Array_PG\n"); 290 if (configtype == BASEBAND_CONFIG_PHY_REG) { 291 for (i = 0; i < phy_reg_arraylen; i = i + 2) { 292 rtl_addr_delay(phy_regarray_table[i]); 293 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, 294 phy_regarray_table[i + 1]); 295 udelay(1); 296 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 297 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n", 298 phy_regarray_table[i], 299 phy_regarray_table[i + 1]); 300 } 301 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) { 302 if (rtlhal->interfaceindex == 0) { 303 for (i = 0; i < agctab_arraylen; i = i + 2) { 304 rtl_set_bbreg(hw, agctab_array_table[i], 305 MASKDWORD, 306 agctab_array_table[i + 1]); 307 /* Add 1us delay between BB/RF register 308 * setting. */ 309 udelay(1); 310 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 311 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", 312 agctab_array_table[i], 313 agctab_array_table[i + 1]); 314 } 315 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 316 "Normal Chip, MAC0, load Rtl819XAGCTAB_Array\n"); 317 } else { 318 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 319 for (i = 0; i < agctab_arraylen; i = i + 2) { 320 rtl_set_bbreg(hw, agctab_array_table[i], 321 MASKDWORD, 322 agctab_array_table[i + 1]); 323 /* Add 1us delay between BB/RF register 324 * setting. */ 325 udelay(1); 326 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 327 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", 328 agctab_array_table[i], 329 agctab_array_table[i + 1]); 330 } 331 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 332 "Load Rtl819XAGCTAB_2GArray\n"); 333 } else { 334 for (i = 0; i < agctab_5garraylen; i = i + 2) { 335 rtl_set_bbreg(hw, 336 agctab_5garray_table[i], 337 MASKDWORD, 338 agctab_5garray_table[i + 1]); 339 /* Add 1us delay between BB/RF registeri 340 * setting. */ 341 udelay(1); 342 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 343 "The Rtl819XAGCTAB_5GArray_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", 344 agctab_5garray_table[i], 345 agctab_5garray_table[i + 1]); 346 } 347 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 348 "Load Rtl819XAGCTAB_5GArray\n"); 349 } 350 } 351 } 352 return true; 353} 354 355static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, 356 u8 configtype) 357{ 358 struct rtl_priv *rtlpriv = rtl_priv(hw); 359 int i; 360 u32 *phy_regarray_table_pg; 361 u16 phy_regarray_pg_len; 362 363 phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH; 364 phy_regarray_table_pg = rtl8192de_phy_reg_array_pg; 365 if (configtype == BASEBAND_CONFIG_PHY_REG) { 366 for (i = 0; i < phy_regarray_pg_len; i = i + 3) { 367 rtl_addr_delay(phy_regarray_table_pg[i]); 368 rtl92d_store_pwrindex_diffrate_offset(hw, 369 phy_regarray_table_pg[i], 370 phy_regarray_table_pg[i + 1], 371 phy_regarray_table_pg[i + 2]); 372 } 373 } else { 374 rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE, 375 "configtype != BaseBand_Config_PHY_REG\n"); 376 } 377 return true; 378} 379 380static bool _rtl92d_phy_bb_config(struct ieee80211_hw *hw) 381{ 382 struct rtl_priv *rtlpriv = rtl_priv(hw); 383 struct rtl_phy *rtlphy = &(rtlpriv->phy); 384 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 385 bool rtstatus; 386 387 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n"); 388 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw, 389 BASEBAND_CONFIG_PHY_REG); 390 if (!rtstatus) { 391 pr_err("Write BB Reg Fail!!\n"); 392 return false; 393 } 394 395 /* if (rtlphy->rf_type == RF_1T2R) { 396 * _rtl92c_phy_bb_config_1t(hw); 397 * rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n"); 398 *} */ 399 400 if (rtlefuse->autoload_failflag == false) { 401 rtlphy->pwrgroup_cnt = 0; 402 rtstatus = _rtl92d_phy_config_bb_with_pgheaderfile(hw, 403 BASEBAND_CONFIG_PHY_REG); 404 } 405 if (!rtstatus) { 406 pr_err("BB_PG Reg Fail!!\n"); 407 return false; 408 } 409 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw, 410 BASEBAND_CONFIG_AGC_TAB); 411 if (!rtstatus) { 412 pr_err("AGC Table Fail\n"); 413 return false; 414 } 415 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw, 416 RFPGA0_XA_HSSIPARAMETER2, 0x200)); 417 418 return true; 419} 420 421bool rtl92d_phy_bb_config(struct ieee80211_hw *hw) 422{ 423 struct rtl_priv *rtlpriv = rtl_priv(hw); 424 u16 regval; 425 u32 regvaldw; 426 u8 value; 427 428 rtl92d_phy_init_bb_rf_register_definition(hw); 429 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 430 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, 431 regval | BIT(13) | BIT(0) | BIT(1)); 432 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83); 433 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb); 434 /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */ 435 value = rtl_read_byte(rtlpriv, REG_RF_CTRL); 436 rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB | 437 RF_SDMRSTB); 438 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA | 439 FEN_DIO_PCIE | FEN_BB_GLB_RSTN | FEN_BBRSTB); 440 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); 441 if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) { 442 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0); 443 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23)); 444 } 445 446 return _rtl92d_phy_bb_config(hw); 447} 448 449bool rtl92d_phy_rf_config(struct ieee80211_hw *hw) 450{ 451 return rtl92d_phy_rf6052_config(hw); 452} 453 454bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 455 enum rf_content content, 456 enum radio_path rfpath) 457{ 458 int i; 459 u32 *radioa_array_table; 460 u32 *radiob_array_table; 461 u16 radioa_arraylen, radiob_arraylen; 462 struct rtl_priv *rtlpriv = rtl_priv(hw); 463 464 radioa_arraylen = RADIOA_2T_ARRAYLENGTH; 465 radioa_array_table = rtl8192de_radioa_2tarray; 466 radiob_arraylen = RADIOB_2T_ARRAYLENGTH; 467 radiob_array_table = rtl8192de_radiob_2tarray; 468 if (rtlpriv->efuse.internal_pa_5g[0]) { 469 radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH; 470 radioa_array_table = rtl8192de_radioa_2t_int_paarray; 471 } 472 if (rtlpriv->efuse.internal_pa_5g[1]) { 473 radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH; 474 radiob_array_table = rtl8192de_radiob_2t_int_paarray; 475 } 476 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 477 "PHY_ConfigRFWithHeaderFile() Radio_A:Rtl819XRadioA_1TArray\n"); 478 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 479 "PHY_ConfigRFWithHeaderFile() Radio_B:Rtl819XRadioB_1TArray\n"); 480 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath); 481 482 /* this only happens when DMDP, mac0 start on 2.4G, 483 * mac1 start on 5G, mac 0 has to set phy0&phy1 484 * pathA or mac1 has to set phy0&phy1 pathA */ 485 if ((content == radiob_txt) && (rfpath == RF90_PATH_A)) { 486 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 487 " ===> although Path A, we load radiob.txt\n"); 488 radioa_arraylen = radiob_arraylen; 489 radioa_array_table = radiob_array_table; 490 } 491 switch (rfpath) { 492 case RF90_PATH_A: 493 for (i = 0; i < radioa_arraylen; i = i + 2) { 494 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i], 495 RFREG_OFFSET_MASK, 496 radioa_array_table[i + 1]); 497 } 498 break; 499 case RF90_PATH_B: 500 for (i = 0; i < radiob_arraylen; i = i + 2) { 501 rtl_rfreg_delay(hw, rfpath, radiob_array_table[i], 502 RFREG_OFFSET_MASK, 503 radiob_array_table[i + 1]); 504 } 505 break; 506 case RF90_PATH_C: 507 case RF90_PATH_D: 508 pr_err("switch case %#x not processed\n", rfpath); 509 break; 510 } 511 return true; 512} 513 514void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw, 515 enum nl80211_channel_type ch_type) 516{ 517 struct rtl_priv *rtlpriv = rtl_priv(hw); 518 struct rtl_phy *rtlphy = &(rtlpriv->phy); 519 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 520 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 521 unsigned long flag = 0; 522 u8 reg_prsr_rsc; 523 u8 reg_bw_opmode; 524 525 if (rtlphy->set_bwmode_inprogress) 526 return; 527 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { 528 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 529 "FALSE driver sleep or unload\n"); 530 return; 531 } 532 rtlphy->set_bwmode_inprogress = true; 533 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n", 534 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? 535 "20MHz" : "40MHz"); 536 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE); 537 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2); 538 switch (rtlphy->current_chan_bw) { 539 case HT_CHANNEL_WIDTH_20: 540 reg_bw_opmode |= BW_OPMODE_20MHZ; 541 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 542 break; 543 case HT_CHANNEL_WIDTH_20_40: 544 reg_bw_opmode &= ~BW_OPMODE_20MHZ; 545 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 546 547 reg_prsr_rsc = (reg_prsr_rsc & 0x90) | 548 (mac->cur_40_prime_sc << 5); 549 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc); 550 break; 551 default: 552 pr_err("unknown bandwidth: %#X\n", 553 rtlphy->current_chan_bw); 554 break; 555 } 556 switch (rtlphy->current_chan_bw) { 557 case HT_CHANNEL_WIDTH_20: 558 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); 559 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); 560 /* SET BIT10 BIT11 for receive cck */ 561 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | 562 BIT(11), 3); 563 break; 564 case HT_CHANNEL_WIDTH_20_40: 565 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); 566 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); 567 /* Set Control channel to upper or lower. 568 * These settings are required only for 40MHz */ 569 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 570 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 571 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND, 572 (mac->cur_40_prime_sc >> 1)); 573 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 574 } 575 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); 576 /* SET BIT10 BIT11 for receive cck */ 577 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | 578 BIT(11), 0); 579 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), 580 (mac->cur_40_prime_sc == 581 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); 582 break; 583 default: 584 pr_err("unknown bandwidth: %#X\n", 585 rtlphy->current_chan_bw); 586 break; 587 588 } 589 rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); 590 rtlphy->set_bwmode_inprogress = false; 591 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 592} 593 594static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw) 595{ 596 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0); 597 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0); 598 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00); 599 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0); 600} 601 602static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band) 603{ 604 struct rtl_priv *rtlpriv = rtl_priv(hw); 605 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 606 u8 value8; 607 608 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n"); 609 rtlhal->bandset = band; 610 rtlhal->current_bandtype = band; 611 if (IS_92D_SINGLEPHY(rtlhal->version)) 612 rtlhal->bandset = BAND_ON_BOTH; 613 /* stop RX/Tx */ 614 _rtl92d_phy_stop_trx_before_changeband(hw); 615 /* reconfig BB/RF according to wireless mode */ 616 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 617 /* BB & RF Config */ 618 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "====>2.4G\n"); 619 if (rtlhal->interfaceindex == 1) 620 _rtl92d_phy_config_bb_with_headerfile(hw, 621 BASEBAND_CONFIG_AGC_TAB); 622 } else { 623 /* 5G band */ 624 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "====>5G\n"); 625 if (rtlhal->interfaceindex == 1) 626 _rtl92d_phy_config_bb_with_headerfile(hw, 627 BASEBAND_CONFIG_AGC_TAB); 628 } 629 rtl92d_update_bbrf_configuration(hw); 630 if (rtlhal->current_bandtype == BAND_ON_2_4G) 631 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 632 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 633 634 /* 20M BW. */ 635 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */ 636 rtlhal->reloadtxpowerindex = true; 637 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ 638 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 639 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex == 640 0 ? REG_MAC0 : REG_MAC1)); 641 value8 |= BIT(1); 642 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex == 643 0 ? REG_MAC0 : REG_MAC1), value8); 644 } else { 645 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex == 646 0 ? REG_MAC0 : REG_MAC1)); 647 value8 &= (~BIT(1)); 648 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex == 649 0 ? REG_MAC0 : REG_MAC1), value8); 650 } 651 mdelay(1); 652 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n"); 653} 654 655static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw, 656 u8 channel, u8 rfpath) 657{ 658 struct rtl_priv *rtlpriv = rtl_priv(hw); 659 u32 imr_num = MAX_RF_IMR_INDEX; 660 u32 rfmask = RFREG_OFFSET_MASK; 661 u8 group, i; 662 unsigned long flag = 0; 663 664 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>path %d\n", rfpath); 665 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) { 666 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n"); 667 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); 668 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); 669 /* fc area 0xd2c */ 670 if (channel > 99) 671 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | 672 BIT(14), 2); 673 else 674 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | 675 BIT(14), 1); 676 /* leave 0 for channel1-14. */ 677 group = channel <= 64 ? 1 : 2; 678 imr_num = MAX_RF_IMR_INDEX_NORMAL; 679 for (i = 0; i < imr_num; i++) 680 rtl_set_rfreg(hw, (enum radio_path)rfpath, 681 rf_reg_for_5g_swchnl_normal[i], rfmask, 682 rf_imr_param_normal[0][group][i]); 683 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); 684 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1); 685 } else { 686 /* G band. */ 687 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, 688 "Load RF IMR parameters for G band. IMR already setting %d\n", 689 rtlpriv->rtlhal.load_imrandiqk_setting_for2g); 690 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n"); 691 if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) { 692 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, 693 "Load RF IMR parameters for G band. %d\n", 694 rfpath); 695 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 696 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); 697 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 698 0x00f00000, 0xf); 699 imr_num = MAX_RF_IMR_INDEX_NORMAL; 700 for (i = 0; i < imr_num; i++) { 701 rtl_set_rfreg(hw, (enum radio_path)rfpath, 702 rf_reg_for_5g_swchnl_normal[i], 703 RFREG_OFFSET_MASK, 704 rf_imr_param_normal[0][0][i]); 705 } 706 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 707 0x00f00000, 0); 708 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3); 709 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 710 } 711 } 712 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); 713} 714 715static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel) 716{ 717 struct rtl_priv *rtlpriv = rtl_priv(hw); 718 struct rtl_phy *rtlphy = &(rtlpriv->phy); 719 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 720 u8 path = rtlhal->current_bandtype == 721 BAND_ON_5G ? RF90_PATH_A : RF90_PATH_B; 722 u8 index = 0, i = 0, rfpath = RF90_PATH_A; 723 bool need_pwr_down = false, internal_pa = false; 724 u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2; 725 726 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>\n"); 727 /* config path A for 5G */ 728 if (rtlhal->current_bandtype == BAND_ON_5G) { 729 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n"); 730 u4tmp = curveindex_5g[channel - 1]; 731 RTPRINT(rtlpriv, FINIT, INIT_IQK, 732 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); 733 for (i = 0; i < RF_CHNL_NUM_5G; i++) { 734 if (channel == rf_chnl_5g[i] && channel <= 140) 735 index = 0; 736 } 737 for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) { 738 if (channel == rf_chnl_5g_40m[i] && channel <= 140) 739 index = 1; 740 } 741 if (channel == 149 || channel == 155 || channel == 161) 742 index = 2; 743 else if (channel == 151 || channel == 153 || channel == 163 744 || channel == 165) 745 index = 3; 746 else if (channel == 157 || channel == 159) 747 index = 4; 748 749 if (rtlhal->macphymode == DUALMAC_DUALPHY 750 && rtlhal->interfaceindex == 1) { 751 need_pwr_down = rtl92d_phy_enable_anotherphy(hw, false); 752 rtlhal->during_mac1init_radioa = true; 753 /* assume no this case */ 754 if (need_pwr_down) 755 rtl92d_phy_enable_rf_env(hw, path, 756 &u4regvalue); 757 } 758 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) { 759 if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) { 760 rtl_set_rfreg(hw, (enum radio_path)path, 761 rf_reg_for_c_cut_5g[i], 762 RFREG_OFFSET_MASK, 0xE439D); 763 } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) { 764 u4tmp2 = (rf_reg_pram_c_5g[index][i] & 765 0x7FF) | (u4tmp << 11); 766 if (channel == 36) 767 u4tmp2 &= ~(BIT(7) | BIT(6)); 768 rtl_set_rfreg(hw, (enum radio_path)path, 769 rf_reg_for_c_cut_5g[i], 770 RFREG_OFFSET_MASK, u4tmp2); 771 } else { 772 rtl_set_rfreg(hw, (enum radio_path)path, 773 rf_reg_for_c_cut_5g[i], 774 RFREG_OFFSET_MASK, 775 rf_reg_pram_c_5g[index][i]); 776 } 777 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 778 "offset 0x%x value 0x%x path %d index %d readback 0x%x\n", 779 rf_reg_for_c_cut_5g[i], 780 rf_reg_pram_c_5g[index][i], 781 path, index, 782 rtl_get_rfreg(hw, (enum radio_path)path, 783 rf_reg_for_c_cut_5g[i], 784 RFREG_OFFSET_MASK)); 785 } 786 if (need_pwr_down) 787 rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); 788 if (rtlhal->during_mac1init_radioa) 789 rtl92d_phy_powerdown_anotherphy(hw, false); 790 if (channel < 149) 791 value = 0x07; 792 else if (channel >= 149) 793 value = 0x02; 794 if (channel >= 36 && channel <= 64) 795 index = 0; 796 else if (channel >= 100 && channel <= 140) 797 index = 1; 798 else 799 index = 2; 800 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; 801 rfpath++) { 802 if (rtlhal->macphymode == DUALMAC_DUALPHY && 803 rtlhal->interfaceindex == 1) /* MAC 1 5G */ 804 internal_pa = rtlpriv->efuse.internal_pa_5g[1]; 805 else 806 internal_pa = 807 rtlpriv->efuse.internal_pa_5g[rfpath]; 808 if (internal_pa) { 809 for (i = 0; 810 i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA; 811 i++) { 812 rtl_set_rfreg(hw, rfpath, 813 rf_for_c_cut_5g_internal_pa[i], 814 RFREG_OFFSET_MASK, 815 rf_pram_c_5g_int_pa[index][i]); 816 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, 817 "offset 0x%x value 0x%x path %d index %d\n", 818 rf_for_c_cut_5g_internal_pa[i], 819 rf_pram_c_5g_int_pa[index][i], 820 rfpath, index); 821 } 822 } else { 823 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, 824 mask, value); 825 } 826 } 827 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) { 828 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n"); 829 u4tmp = curveindex_2g[channel - 1]; 830 RTPRINT(rtlpriv, FINIT, INIT_IQK, 831 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); 832 if (channel == 1 || channel == 2 || channel == 4 || channel == 9 833 || channel == 10 || channel == 11 || channel == 12) 834 index = 0; 835 else if (channel == 3 || channel == 13 || channel == 14) 836 index = 1; 837 else if (channel >= 5 && channel <= 8) 838 index = 2; 839 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 840 path = RF90_PATH_A; 841 if (rtlhal->interfaceindex == 0) { 842 need_pwr_down = 843 rtl92d_phy_enable_anotherphy(hw, true); 844 rtlhal->during_mac0init_radiob = true; 845 846 if (need_pwr_down) 847 rtl92d_phy_enable_rf_env(hw, path, 848 &u4regvalue); 849 } 850 } 851 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) { 852 if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7) 853 rtl_set_rfreg(hw, (enum radio_path)path, 854 rf_reg_for_c_cut_2g[i], 855 RFREG_OFFSET_MASK, 856 (rf_reg_param_for_c_cut_2g[index][i] | 857 BIT(17))); 858 else 859 rtl_set_rfreg(hw, (enum radio_path)path, 860 rf_reg_for_c_cut_2g[i], 861 RFREG_OFFSET_MASK, 862 rf_reg_param_for_c_cut_2g 863 [index][i]); 864 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 865 "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n", 866 rf_reg_for_c_cut_2g[i], 867 rf_reg_param_for_c_cut_2g[index][i], 868 rf_reg_mask_for_c_cut_2g[i], path, index, 869 rtl_get_rfreg(hw, (enum radio_path)path, 870 rf_reg_for_c_cut_2g[i], 871 RFREG_OFFSET_MASK)); 872 } 873 RTPRINT(rtlpriv, FINIT, INIT_IQK, 874 "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", 875 rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); 876 877 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4, 878 RFREG_OFFSET_MASK, 879 rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); 880 if (need_pwr_down) 881 rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); 882 if (rtlhal->during_mac0init_radiob) 883 rtl92d_phy_powerdown_anotherphy(hw, true); 884 } 885 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); 886} 887 888/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 889static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb) 890{ 891 struct rtl_priv *rtlpriv = rtl_priv(hw); 892 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 893 u32 regeac, rege94, rege9c, regea4; 894 u8 result = 0; 895 896 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n"); 897 /* path-A IQK setting */ 898 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); 899 if (rtlhal->interfaceindex == 0) { 900 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); 901 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); 902 } else { 903 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22); 904 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22); 905 } 906 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); 907 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206); 908 /* path-B IQK setting */ 909 if (configpathb) { 910 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); 911 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); 912 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); 913 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206); 914 } 915 /* LO calibration setting */ 916 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 917 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); 918 /* One shot, path A LOK & IQK */ 919 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n"); 920 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); 921 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); 922 /* delay x ms */ 923 RTPRINT(rtlpriv, FINIT, INIT_IQK, 924 "Delay %d ms for One shot, path A LOK & IQK\n", 925 IQK_DELAY_TIME); 926 mdelay(IQK_DELAY_TIME); 927 /* Check failed */ 928 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 929 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 930 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); 931 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); 932 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); 933 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); 934 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); 935 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); 936 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) && 937 (((rege9c & 0x03FF0000) >> 16) != 0x42)) 938 result |= 0x01; 939 else /* if Tx not OK, ignore Rx */ 940 return result; 941 /* if Tx is OK, check whether Rx is OK */ 942 if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) && 943 (((regeac & 0x03FF0000) >> 16) != 0x36)) 944 result |= 0x02; 945 else 946 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A Rx IQK fail!!\n"); 947 return result; 948} 949 950/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 951static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw, 952 bool configpathb) 953{ 954 struct rtl_priv *rtlpriv = rtl_priv(hw); 955 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 956 struct rtl_phy *rtlphy = &(rtlpriv->phy); 957 u32 regeac, rege94, rege9c, regea4; 958 u8 result = 0; 959 u8 i; 960 u8 retrycount = 2; 961 u32 TXOKBIT = BIT(28), RXOKBIT = BIT(27); 962 963 if (rtlhal->interfaceindex == 1) { /* PHY1 */ 964 TXOKBIT = BIT(31); 965 RXOKBIT = BIT(30); 966 } 967 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n"); 968 /* path-A IQK setting */ 969 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); 970 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); 971 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); 972 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307); 973 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960); 974 /* path-B IQK setting */ 975 if (configpathb) { 976 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); 977 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); 978 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000); 979 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000); 980 } 981 /* LO calibration setting */ 982 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 983 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); 984 /* path-A PA on */ 985 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); 986 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); 987 for (i = 0; i < retrycount; i++) { 988 /* One shot, path A LOK & IQK */ 989 RTPRINT(rtlpriv, FINIT, INIT_IQK, 990 "One shot, path A LOK & IQK!\n"); 991 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); 992 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); 993 /* delay x ms */ 994 RTPRINT(rtlpriv, FINIT, INIT_IQK, 995 "Delay %d ms for One shot, path A LOK & IQK.\n", 996 IQK_DELAY_TIME); 997 mdelay(IQK_DELAY_TIME * 10); 998 /* Check failed */ 999 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1000 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1001 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); 1002 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); 1003 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); 1004 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); 1005 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); 1006 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); 1007 if (!(regeac & TXOKBIT) && 1008 (((rege94 & 0x03FF0000) >> 16) != 0x142)) { 1009 result |= 0x01; 1010 } else { /* if Tx not OK, ignore Rx */ 1011 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1012 "Path A Tx IQK fail!!\n"); 1013 continue; 1014 } 1015 1016 /* if Tx is OK, check whether Rx is OK */ 1017 if (!(regeac & RXOKBIT) && 1018 (((regea4 & 0x03FF0000) >> 16) != 0x132)) { 1019 result |= 0x02; 1020 break; 1021 } else { 1022 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1023 "Path A Rx IQK fail!!\n"); 1024 } 1025 } 1026 /* path A PA off */ 1027 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 1028 rtlphy->iqk_bb_backup[0]); 1029 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 1030 rtlphy->iqk_bb_backup[1]); 1031 return result; 1032} 1033 1034/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 1035static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw) 1036{ 1037 struct rtl_priv *rtlpriv = rtl_priv(hw); 1038 u32 regeac, regeb4, regebc, regec4, regecc; 1039 u8 result = 0; 1040 1041 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n"); 1042 /* One shot, path B LOK & IQK */ 1043 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n"); 1044 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); 1045 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); 1046 /* delay x ms */ 1047 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1048 "Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME); 1049 mdelay(IQK_DELAY_TIME); 1050 /* Check failed */ 1051 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1052 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1053 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); 1054 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); 1055 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); 1056 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); 1057 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); 1058 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); 1059 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); 1060 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); 1061 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) && 1062 (((regebc & 0x03FF0000) >> 16) != 0x42)) 1063 result |= 0x01; 1064 else 1065 return result; 1066 if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) && 1067 (((regecc & 0x03FF0000) >> 16) != 0x36)) 1068 result |= 0x02; 1069 else 1070 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B Rx IQK fail!!\n"); 1071 return result; 1072} 1073 1074/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 1075static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw) 1076{ 1077 struct rtl_priv *rtlpriv = rtl_priv(hw); 1078 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1079 u32 regeac, regeb4, regebc, regec4, regecc; 1080 u8 result = 0; 1081 u8 i; 1082 u8 retrycount = 2; 1083 1084 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n"); 1085 /* path-A IQK setting */ 1086 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); 1087 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); 1088 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); 1089 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000); 1090 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000); 1091 1092 /* path-B IQK setting */ 1093 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); 1094 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); 1095 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307); 1096 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960); 1097 1098 /* LO calibration setting */ 1099 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 1100 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); 1101 1102 /* path-B PA on */ 1103 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); 1104 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); 1105 1106 for (i = 0; i < retrycount; i++) { 1107 /* One shot, path B LOK & IQK */ 1108 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1109 "One shot, path A LOK & IQK!\n"); 1110 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000); 1111 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); 1112 1113 /* delay x ms */ 1114 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1115 "Delay %d ms for One shot, path B LOK & IQK.\n", 10); 1116 mdelay(IQK_DELAY_TIME * 10); 1117 1118 /* Check failed */ 1119 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1120 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1121 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); 1122 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); 1123 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); 1124 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); 1125 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); 1126 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); 1127 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); 1128 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); 1129 if (!(regeac & BIT(31)) && 1130 (((regeb4 & 0x03FF0000) >> 16) != 0x142)) 1131 result |= 0x01; 1132 else 1133 continue; 1134 if (!(regeac & BIT(30)) && 1135 (((regec4 & 0x03FF0000) >> 16) != 0x132)) { 1136 result |= 0x02; 1137 break; 1138 } else { 1139 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1140 "Path B Rx IQK fail!!\n"); 1141 } 1142 } 1143 1144 /* path B PA off */ 1145 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 1146 rtlphy->iqk_bb_backup[0]); 1147 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 1148 rtlphy->iqk_bb_backup[2]); 1149 return result; 1150} 1151 1152static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw, 1153 u32 *adda_reg, u32 *adda_backup, 1154 u32 regnum) 1155{ 1156 struct rtl_priv *rtlpriv = rtl_priv(hw); 1157 u32 i; 1158 1159 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1160 "Reload ADDA power saving parameters !\n"); 1161 for (i = 0; i < regnum; i++) 1162 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]); 1163} 1164 1165static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw, 1166 u32 *macreg, u32 *macbackup) 1167{ 1168 struct rtl_priv *rtlpriv = rtl_priv(hw); 1169 u32 i; 1170 1171 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Reload MAC parameters !\n"); 1172 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 1173 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]); 1174 rtl_write_byte(rtlpriv, macreg[i], macbackup[i]); 1175} 1176 1177static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw) 1178{ 1179 struct rtl_priv *rtlpriv = rtl_priv(hw); 1180 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A standby mode!\n"); 1181 1182 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); 1183 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); 1184 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 1185} 1186 1187static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode) 1188{ 1189 struct rtl_priv *rtlpriv = rtl_priv(hw); 1190 u32 mode; 1191 1192 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1193 "BB Switch to %s mode!\n", pi_mode ? "PI" : "SI"); 1194 mode = pi_mode ? 0x01000100 : 0x01000000; 1195 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); 1196 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); 1197} 1198 1199static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8], 1200 u8 t, bool is2t) 1201{ 1202 struct rtl_priv *rtlpriv = rtl_priv(hw); 1203 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1204 u32 i; 1205 u8 patha_ok, pathb_ok; 1206 static u32 adda_reg[IQK_ADDA_REG_NUM] = { 1207 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74, 1208 0xe78, 0xe7c, 0xe80, 0xe84, 1209 0xe88, 0xe8c, 0xed0, 0xed4, 1210 0xed8, 0xedc, 0xee0, 0xeec 1211 }; 1212 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { 1213 0x522, 0x550, 0x551, 0x040 1214 }; 1215 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = { 1216 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE, 1217 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR, 1218 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE, 1219 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4, 1220 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1 1221 }; 1222 const u32 retrycount = 2; 1223 u32 bbvalue; 1224 1225 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 2.4G :Start!!!\n"); 1226 if (t == 0) { 1227 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); 1228 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); 1229 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", 1230 is2t ? "2T2R" : "1T1R"); 1231 1232 /* Save ADDA parameters, turn Path A ADDA on */ 1233 rtl92d_phy_save_adda_registers(hw, adda_reg, 1234 rtlphy->adda_backup, 1235 IQK_ADDA_REG_NUM); 1236 rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, 1237 rtlphy->iqk_mac_backup); 1238 rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, 1239 rtlphy->iqk_bb_backup, 1240 IQK_BB_REG_NUM); 1241 } 1242 rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); 1243 if (t == 0) 1244 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, 1245 RFPGA0_XA_HSSIPARAMETER1, BIT(8)); 1246 1247 /* Switch BB to PI mode to do IQ Calibration. */ 1248 if (!rtlphy->rfpi_enable) 1249 _rtl92d_phy_pimode_switch(hw, true); 1250 1251 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); 1252 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); 1253 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); 1254 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); 1255 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); 1256 if (is2t) { 1257 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 1258 0x00010000); 1259 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD, 1260 0x00010000); 1261 } 1262 /* MAC settings */ 1263 rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, 1264 rtlphy->iqk_mac_backup); 1265 /* Page B init */ 1266 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); 1267 if (is2t) 1268 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); 1269 /* IQ calibration setting */ 1270 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n"); 1271 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 1272 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); 1273 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); 1274 for (i = 0; i < retrycount; i++) { 1275 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t); 1276 if (patha_ok == 0x03) { 1277 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1278 "Path A IQK Success!!\n"); 1279 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 1280 0x3FF0000) >> 16; 1281 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 1282 0x3FF0000) >> 16; 1283 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & 1284 0x3FF0000) >> 16; 1285 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & 1286 0x3FF0000) >> 16; 1287 break; 1288 } else if (i == (retrycount - 1) && patha_ok == 0x01) { 1289 /* Tx IQK OK */ 1290 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1291 "Path A IQK Only Tx Success!!\n"); 1292 1293 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 1294 0x3FF0000) >> 16; 1295 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 1296 0x3FF0000) >> 16; 1297 } 1298 } 1299 if (0x00 == patha_ok) 1300 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK failed!!\n"); 1301 if (is2t) { 1302 _rtl92d_phy_patha_standby(hw); 1303 /* Turn Path B ADDA on */ 1304 rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); 1305 for (i = 0; i < retrycount; i++) { 1306 pathb_ok = _rtl92d_phy_pathb_iqk(hw); 1307 if (pathb_ok == 0x03) { 1308 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1309 "Path B IQK Success!!\n"); 1310 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, 1311 MASKDWORD) & 0x3FF0000) >> 16; 1312 result[t][5] = (rtl_get_bbreg(hw, 0xebc, 1313 MASKDWORD) & 0x3FF0000) >> 16; 1314 result[t][6] = (rtl_get_bbreg(hw, 0xec4, 1315 MASKDWORD) & 0x3FF0000) >> 16; 1316 result[t][7] = (rtl_get_bbreg(hw, 0xecc, 1317 MASKDWORD) & 0x3FF0000) >> 16; 1318 break; 1319 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { 1320 /* Tx IQK OK */ 1321 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1322 "Path B Only Tx IQK Success!!\n"); 1323 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, 1324 MASKDWORD) & 0x3FF0000) >> 16; 1325 result[t][5] = (rtl_get_bbreg(hw, 0xebc, 1326 MASKDWORD) & 0x3FF0000) >> 16; 1327 } 1328 } 1329 if (0x00 == pathb_ok) 1330 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1331 "Path B IQK failed!!\n"); 1332 } 1333 1334 /* Back to BB mode, load original value */ 1335 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1336 "IQK:Back to BB mode, load original value!\n"); 1337 1338 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); 1339 if (t != 0) { 1340 /* Switch back BB to SI mode after finish IQ Calibration. */ 1341 if (!rtlphy->rfpi_enable) 1342 _rtl92d_phy_pimode_switch(hw, false); 1343 /* Reload ADDA power saving parameters */ 1344 _rtl92d_phy_reload_adda_registers(hw, adda_reg, 1345 rtlphy->adda_backup, IQK_ADDA_REG_NUM); 1346 /* Reload MAC parameters */ 1347 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg, 1348 rtlphy->iqk_mac_backup); 1349 if (is2t) 1350 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, 1351 rtlphy->iqk_bb_backup, 1352 IQK_BB_REG_NUM); 1353 else 1354 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, 1355 rtlphy->iqk_bb_backup, 1356 IQK_BB_REG_NUM - 1); 1357 /* load 0xe30 IQC default value */ 1358 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); 1359 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); 1360 } 1361 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n"); 1362} 1363 1364static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw, 1365 long result[][8], u8 t) 1366{ 1367 struct rtl_priv *rtlpriv = rtl_priv(hw); 1368 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1369 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 1370 u8 patha_ok, pathb_ok; 1371 static u32 adda_reg[IQK_ADDA_REG_NUM] = { 1372 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74, 1373 0xe78, 0xe7c, 0xe80, 0xe84, 1374 0xe88, 0xe8c, 0xed0, 0xed4, 1375 0xed8, 0xedc, 0xee0, 0xeec 1376 }; 1377 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { 1378 0x522, 0x550, 0x551, 0x040 1379 }; 1380 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = { 1381 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE, 1382 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR, 1383 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE, 1384 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4, 1385 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1 1386 }; 1387 u32 bbvalue; 1388 bool is2t = IS_92D_SINGLEPHY(rtlhal->version); 1389 1390 /* Note: IQ calibration must be performed after loading 1391 * PHY_REG.txt , and radio_a, radio_b.txt */ 1392 1393 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 5G NORMAL:Start!!!\n"); 1394 mdelay(IQK_DELAY_TIME * 20); 1395 if (t == 0) { 1396 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); 1397 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); 1398 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", 1399 is2t ? "2T2R" : "1T1R"); 1400 /* Save ADDA parameters, turn Path A ADDA on */ 1401 rtl92d_phy_save_adda_registers(hw, adda_reg, 1402 rtlphy->adda_backup, 1403 IQK_ADDA_REG_NUM); 1404 rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, 1405 rtlphy->iqk_mac_backup); 1406 if (is2t) 1407 rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, 1408 rtlphy->iqk_bb_backup, 1409 IQK_BB_REG_NUM); 1410 else 1411 rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, 1412 rtlphy->iqk_bb_backup, 1413 IQK_BB_REG_NUM - 1); 1414 } 1415 rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); 1416 /* MAC settings */ 1417 rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, 1418 rtlphy->iqk_mac_backup); 1419 if (t == 0) 1420 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, 1421 RFPGA0_XA_HSSIPARAMETER1, BIT(8)); 1422 /* Switch BB to PI mode to do IQ Calibration. */ 1423 if (!rtlphy->rfpi_enable) 1424 _rtl92d_phy_pimode_switch(hw, true); 1425 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); 1426 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); 1427 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); 1428 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); 1429 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); 1430 1431 /* Page B init */ 1432 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); 1433 if (is2t) 1434 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); 1435 /* IQ calibration setting */ 1436 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n"); 1437 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 1438 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00); 1439 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); 1440 patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t); 1441 if (patha_ok == 0x03) { 1442 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Success!!\n"); 1443 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 1444 0x3FF0000) >> 16; 1445 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 1446 0x3FF0000) >> 16; 1447 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & 1448 0x3FF0000) >> 16; 1449 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & 1450 0x3FF0000) >> 16; 1451 } else if (patha_ok == 0x01) { /* Tx IQK OK */ 1452 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1453 "Path A IQK Only Tx Success!!\n"); 1454 1455 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 1456 0x3FF0000) >> 16; 1457 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 1458 0x3FF0000) >> 16; 1459 } else { 1460 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Fail!!\n"); 1461 } 1462 if (is2t) { 1463 /* _rtl92d_phy_patha_standby(hw); */ 1464 /* Turn Path B ADDA on */ 1465 rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); 1466 pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw); 1467 if (pathb_ok == 0x03) { 1468 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1469 "Path B IQK Success!!\n"); 1470 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & 1471 0x3FF0000) >> 16; 1472 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & 1473 0x3FF0000) >> 16; 1474 result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & 1475 0x3FF0000) >> 16; 1476 result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & 1477 0x3FF0000) >> 16; 1478 } else if (pathb_ok == 0x01) { /* Tx IQK OK */ 1479 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1480 "Path B Only Tx IQK Success!!\n"); 1481 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & 1482 0x3FF0000) >> 16; 1483 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & 1484 0x3FF0000) >> 16; 1485 } else { 1486 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1487 "Path B IQK failed!!\n"); 1488 } 1489 } 1490 1491 /* Back to BB mode, load original value */ 1492 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1493 "IQK:Back to BB mode, load original value!\n"); 1494 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); 1495 if (t != 0) { 1496 if (is2t) 1497 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, 1498 rtlphy->iqk_bb_backup, 1499 IQK_BB_REG_NUM); 1500 else 1501 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, 1502 rtlphy->iqk_bb_backup, 1503 IQK_BB_REG_NUM - 1); 1504 /* Reload MAC parameters */ 1505 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg, 1506 rtlphy->iqk_mac_backup); 1507 /* Switch back BB to SI mode after finish IQ Calibration. */ 1508 if (!rtlphy->rfpi_enable) 1509 _rtl92d_phy_pimode_switch(hw, false); 1510 /* Reload ADDA power saving parameters */ 1511 _rtl92d_phy_reload_adda_registers(hw, adda_reg, 1512 rtlphy->adda_backup, 1513 IQK_ADDA_REG_NUM); 1514 } 1515 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n"); 1516} 1517 1518static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw, 1519 long result[][8], u8 c1, u8 c2) 1520{ 1521 struct rtl_priv *rtlpriv = rtl_priv(hw); 1522 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 1523 u32 i, j, diff, sim_bitmap, bound; 1524 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */ 1525 bool bresult = true; 1526 bool is2t = IS_92D_SINGLEPHY(rtlhal->version); 1527 1528 if (is2t) 1529 bound = 8; 1530 else 1531 bound = 4; 1532 sim_bitmap = 0; 1533 for (i = 0; i < bound; i++) { 1534 diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - 1535 result[c2][i]) : (result[c2][i] - result[c1][i]); 1536 if (diff > MAX_TOLERANCE_92D) { 1537 if ((i == 2 || i == 6) && !sim_bitmap) { 1538 if (result[c1][i] + result[c1][i + 1] == 0) 1539 final_candidate[(i / 4)] = c2; 1540 else if (result[c2][i] + result[c2][i + 1] == 0) 1541 final_candidate[(i / 4)] = c1; 1542 else 1543 sim_bitmap = sim_bitmap | (1 << i); 1544 } else { 1545 sim_bitmap = sim_bitmap | (1 << i); 1546 } 1547 } 1548 } 1549 if (sim_bitmap == 0) { 1550 for (i = 0; i < (bound / 4); i++) { 1551 if (final_candidate[i] != 0xFF) { 1552 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 1553 result[3][j] = 1554 result[final_candidate[i]][j]; 1555 bresult = false; 1556 } 1557 } 1558 return bresult; 1559 } 1560 if (!(sim_bitmap & 0x0F)) { /* path A OK */ 1561 for (i = 0; i < 4; i++) 1562 result[3][i] = result[c1][i]; 1563 } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */ 1564 for (i = 0; i < 2; i++) 1565 result[3][i] = result[c1][i]; 1566 } 1567 if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */ 1568 for (i = 4; i < 8; i++) 1569 result[3][i] = result[c1][i]; 1570 } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */ 1571 for (i = 4; i < 6; i++) 1572 result[3][i] = result[c1][i]; 1573 } 1574 return false; 1575} 1576 1577static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw, 1578 bool iqk_ok, long result[][8], 1579 u8 final_candidate, bool txonly) 1580{ 1581 struct rtl_priv *rtlpriv = rtl_priv(hw); 1582 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 1583 u32 oldval_0, val_x, tx0_a, reg; 1584 long val_y, tx0_c; 1585 bool is2t = IS_92D_SINGLEPHY(rtlhal->version) || 1586 rtlhal->macphymode == DUALMAC_DUALPHY; 1587 1588 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1589 "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed"); 1590 if (final_candidate == 0xFF) { 1591 return; 1592 } else if (iqk_ok) { 1593 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 1594 MASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */ 1595 val_x = result[final_candidate][0]; 1596 if ((val_x & 0x00000200) != 0) 1597 val_x = val_x | 0xFFFFFC00; 1598 tx0_a = (val_x * oldval_0) >> 8; 1599 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1600 "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n", 1601 val_x, tx0_a, oldval_0); 1602 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); 1603 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), 1604 ((val_x * oldval_0 >> 7) & 0x1)); 1605 val_y = result[final_candidate][1]; 1606 if ((val_y & 0x00000200) != 0) 1607 val_y = val_y | 0xFFFFFC00; 1608 /* path B IQK result + 3 */ 1609 if (rtlhal->interfaceindex == 1 && 1610 rtlhal->current_bandtype == BAND_ON_5G) 1611 val_y += 3; 1612 tx0_c = (val_y * oldval_0) >> 8; 1613 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1614 "Y = 0x%lx, tx0_c = 0x%lx\n", 1615 val_y, tx0_c); 1616 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 1617 ((tx0_c & 0x3C0) >> 6)); 1618 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, 1619 (tx0_c & 0x3F)); 1620 if (is2t) 1621 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26), 1622 ((val_y * oldval_0 >> 7) & 0x1)); 1623 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n", 1624 rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 1625 MASKDWORD)); 1626 if (txonly) { 1627 RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n"); 1628 return; 1629 } 1630 reg = result[final_candidate][2]; 1631 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); 1632 reg = result[final_candidate][3] & 0x3F; 1633 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); 1634 reg = (result[final_candidate][3] >> 6) & 0xF; 1635 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); 1636 } 1637} 1638 1639static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw, 1640 bool iqk_ok, long result[][8], u8 final_candidate, bool txonly) 1641{ 1642 struct rtl_priv *rtlpriv = rtl_priv(hw); 1643 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 1644 u32 oldval_1, val_x, tx1_a, reg; 1645 long val_y, tx1_c; 1646 1647 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n", 1648 iqk_ok ? "Success" : "Failed"); 1649 if (final_candidate == 0xFF) { 1650 return; 1651 } else if (iqk_ok) { 1652 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 1653 MASKDWORD) >> 22) & 0x3FF; 1654 val_x = result[final_candidate][4]; 1655 if ((val_x & 0x00000200) != 0) 1656 val_x = val_x | 0xFFFFFC00; 1657 tx1_a = (val_x * oldval_1) >> 8; 1658 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n", 1659 val_x, tx1_a); 1660 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a); 1661 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), 1662 ((val_x * oldval_1 >> 7) & 0x1)); 1663 val_y = result[final_candidate][5]; 1664 if ((val_y & 0x00000200) != 0) 1665 val_y = val_y | 0xFFFFFC00; 1666 if (rtlhal->current_bandtype == BAND_ON_5G) 1667 val_y += 3; 1668 tx1_c = (val_y * oldval_1) >> 8; 1669 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n", 1670 val_y, tx1_c); 1671 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 1672 ((tx1_c & 0x3C0) >> 6)); 1673 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, 1674 (tx1_c & 0x3F)); 1675 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30), 1676 ((val_y * oldval_1 >> 7) & 0x1)); 1677 if (txonly) 1678 return; 1679 reg = result[final_candidate][6]; 1680 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); 1681 reg = result[final_candidate][7] & 0x3F; 1682 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); 1683 reg = (result[final_candidate][7] >> 6) & 0xF; 1684 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); 1685 } 1686} 1687 1688void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw) 1689{ 1690 struct rtl_priv *rtlpriv = rtl_priv(hw); 1691 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1692 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 1693 long result[4][8]; 1694 u8 i, final_candidate, indexforchannel; 1695 bool patha_ok, pathb_ok; 1696 long rege94, rege9c, regea4, regeac, regeb4; 1697 long regebc, regec4, regecc, regtmp = 0; 1698 bool is12simular, is13simular, is23simular; 1699 unsigned long flag = 0; 1700 1701 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1702 "IQK:Start!!!channel %d\n", rtlphy->current_channel); 1703 for (i = 0; i < 8; i++) { 1704 result[0][i] = 0; 1705 result[1][i] = 0; 1706 result[2][i] = 0; 1707 result[3][i] = 0; 1708 } 1709 final_candidate = 0xff; 1710 patha_ok = false; 1711 pathb_ok = false; 1712 is12simular = false; 1713 is23simular = false; 1714 is13simular = false; 1715 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1716 "IQK !!!currentband %d\n", rtlhal->current_bandtype); 1717 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 1718 for (i = 0; i < 3; i++) { 1719 if (rtlhal->current_bandtype == BAND_ON_5G) { 1720 _rtl92d_phy_iq_calibrate_5g_normal(hw, result, i); 1721 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) { 1722 if (IS_92D_SINGLEPHY(rtlhal->version)) 1723 _rtl92d_phy_iq_calibrate(hw, result, i, true); 1724 else 1725 _rtl92d_phy_iq_calibrate(hw, result, i, false); 1726 } 1727 if (i == 1) { 1728 is12simular = _rtl92d_phy_simularity_compare(hw, result, 1729 0, 1); 1730 if (is12simular) { 1731 final_candidate = 0; 1732 break; 1733 } 1734 } 1735 if (i == 2) { 1736 is13simular = _rtl92d_phy_simularity_compare(hw, result, 1737 0, 2); 1738 if (is13simular) { 1739 final_candidate = 0; 1740 break; 1741 } 1742 is23simular = _rtl92d_phy_simularity_compare(hw, result, 1743 1, 2); 1744 if (is23simular) { 1745 final_candidate = 1; 1746 } else { 1747 for (i = 0; i < 8; i++) 1748 regtmp += result[3][i]; 1749 1750 if (regtmp != 0) 1751 final_candidate = 3; 1752 else 1753 final_candidate = 0xFF; 1754 } 1755 } 1756 } 1757 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 1758 for (i = 0; i < 4; i++) { 1759 rege94 = result[i][0]; 1760 rege9c = result[i][1]; 1761 regea4 = result[i][2]; 1762 regeac = result[i][3]; 1763 regeb4 = result[i][4]; 1764 regebc = result[i][5]; 1765 regec4 = result[i][6]; 1766 regecc = result[i][7]; 1767 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1768 "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n", 1769 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, 1770 regecc); 1771 } 1772 if (final_candidate != 0xff) { 1773 rtlphy->reg_e94 = rege94 = result[final_candidate][0]; 1774 rtlphy->reg_e9c = rege9c = result[final_candidate][1]; 1775 regea4 = result[final_candidate][2]; 1776 regeac = result[final_candidate][3]; 1777 rtlphy->reg_eb4 = regeb4 = result[final_candidate][4]; 1778 rtlphy->reg_ebc = regebc = result[final_candidate][5]; 1779 regec4 = result[final_candidate][6]; 1780 regecc = result[final_candidate][7]; 1781 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1782 "IQK: final_candidate is %x\n", final_candidate); 1783 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1784 "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n", 1785 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, 1786 regecc); 1787 patha_ok = pathb_ok = true; 1788 } else { 1789 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */ 1790 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; /* Y default value */ 1791 } 1792 if ((rege94 != 0) /*&&(regea4 != 0) */) 1793 _rtl92d_phy_patha_fill_iqk_matrix(hw, patha_ok, result, 1794 final_candidate, (regea4 == 0)); 1795 if (IS_92D_SINGLEPHY(rtlhal->version)) { 1796 if ((regeb4 != 0) /*&&(regec4 != 0) */) 1797 _rtl92d_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result, 1798 final_candidate, (regec4 == 0)); 1799 } 1800 if (final_candidate != 0xFF) { 1801 indexforchannel = rtl92d_get_rightchnlplace_for_iqk( 1802 rtlphy->current_channel); 1803 1804 for (i = 0; i < IQK_MATRIX_REG_NUM; i++) 1805 rtlphy->iqk_matrix[indexforchannel]. 1806 value[0][i] = result[final_candidate][i]; 1807 rtlphy->iqk_matrix[indexforchannel].iqk_done = 1808 true; 1809 1810 rtl_dbg(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD, 1811 "IQK OK indexforchannel %d\n", indexforchannel); 1812 } 1813} 1814 1815void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel) 1816{ 1817 struct rtl_priv *rtlpriv = rtl_priv(hw); 1818 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1819 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 1820 u8 indexforchannel; 1821 1822 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "channel %d\n", channel); 1823 /*------Do IQK for normal chip and test chip 5G band------- */ 1824 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel); 1825 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "indexforchannel %d done %d\n", 1826 indexforchannel, 1827 rtlphy->iqk_matrix[indexforchannel].iqk_done); 1828 if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done && 1829 rtlphy->need_iqk) { 1830 /* Re Do IQK. */ 1831 rtl_dbg(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD, 1832 "Do IQK Matrix reg for channel:%d....\n", channel); 1833 rtl92d_phy_iq_calibrate(hw); 1834 } else { 1835 /* Just load the value. */ 1836 /* 2G band just load once. */ 1837 if (((!rtlhal->load_imrandiqk_setting_for2g) && 1838 indexforchannel == 0) || indexforchannel > 0) { 1839 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, 1840 "Just Read IQK Matrix reg for channel:%d....\n", 1841 channel); 1842 if (rtlphy->iqk_matrix[indexforchannel].value[0][0] != 0) 1843 _rtl92d_phy_patha_fill_iqk_matrix(hw, true, 1844 rtlphy->iqk_matrix[indexforchannel].value, 0, 1845 rtlphy->iqk_matrix[indexforchannel].value[0][2] == 0); 1846 if (IS_92D_SINGLEPHY(rtlhal->version)) { 1847 if ((rtlphy->iqk_matrix[ 1848 indexforchannel].value[0][4] != 0) 1849 /*&&(regec4 != 0) */) 1850 _rtl92d_phy_pathb_fill_iqk_matrix(hw, 1851 true, 1852 rtlphy->iqk_matrix[ 1853 indexforchannel].value, 0, 1854 (rtlphy->iqk_matrix[ 1855 indexforchannel].value[0][6] 1856 == 0)); 1857 } 1858 } 1859 } 1860 rtlphy->need_iqk = false; 1861 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); 1862} 1863 1864static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw, 1865 u8 channel) 1866{ 1867 struct rtl_priv *rtlpriv = rtl_priv(hw); 1868 u8 erfpath = rtlpriv->rtlhal.current_bandtype == 1869 BAND_ON_5G ? RF90_PATH_A : 1870 IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ? 1871 RF90_PATH_B : RF90_PATH_A; 1872 u32 u4tmp = 0, u4regvalue = 0; 1873 bool bneed_powerdown_radio = false; 1874 1875 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath); 1876 RTPRINT(rtlpriv, FINIT, INIT_IQK, "band type = %d\n", 1877 rtlpriv->rtlhal.current_bandtype); 1878 RTPRINT(rtlpriv, FINIT, INIT_IQK, "channel = %d\n", channel); 1879 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */ 1880 u4tmp = curveindex_5g[channel-1]; 1881 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1882 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); 1883 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY && 1884 rtlpriv->rtlhal.interfaceindex == 1) { 1885 bneed_powerdown_radio = 1886 rtl92d_phy_enable_anotherphy(hw, false); 1887 rtlpriv->rtlhal.during_mac1init_radioa = true; 1888 /* assume no this case */ 1889 if (bneed_powerdown_radio) 1890 rtl92d_phy_enable_rf_env(hw, erfpath, 1891 &u4regvalue); 1892 } 1893 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); 1894 if (bneed_powerdown_radio) 1895 rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); 1896 if (rtlpriv->rtlhal.during_mac1init_radioa) 1897 rtl92d_phy_powerdown_anotherphy(hw, false); 1898 } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) { 1899 u4tmp = curveindex_2g[channel-1]; 1900 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1901 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); 1902 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY && 1903 rtlpriv->rtlhal.interfaceindex == 0) { 1904 bneed_powerdown_radio = 1905 rtl92d_phy_enable_anotherphy(hw, true); 1906 rtlpriv->rtlhal.during_mac0init_radiob = true; 1907 if (bneed_powerdown_radio) 1908 rtl92d_phy_enable_rf_env(hw, erfpath, 1909 &u4regvalue); 1910 } 1911 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); 1912 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1913 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", 1914 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800)); 1915 if (bneed_powerdown_radio) 1916 rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); 1917 if (rtlpriv->rtlhal.during_mac0init_radiob) 1918 rtl92d_phy_powerdown_anotherphy(hw, true); 1919 } 1920 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); 1921} 1922 1923static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t) 1924{ 1925 struct rtl_priv *rtlpriv = rtl_priv(hw); 1926 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 1927 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1928 u8 tmpreg, index, rf_mode[2]; 1929 u8 path = is2t ? 2 : 1; 1930 u8 i; 1931 u32 u4tmp, offset; 1932 u32 curvecount_val[CV_CURVE_CNT * 2] = {0}; 1933 u16 timeout = 800, timecount = 0; 1934 1935 /* Check continuous TX and Packet TX */ 1936 tmpreg = rtl_read_byte(rtlpriv, 0xd03); 1937 /* if Deal with contisuous TX case, disable all continuous TX */ 1938 /* if Deal with Packet TX case, block all queues */ 1939 if ((tmpreg & 0x70) != 0) 1940 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); 1941 else 1942 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1943 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F); 1944 for (index = 0; index < path; index++) { 1945 /* 1. Read original RF mode */ 1946 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; 1947 rf_mode[index] = rtl_read_byte(rtlpriv, offset); 1948 /* 2. Set RF mode = standby mode */ 1949 rtl_set_rfreg(hw, (enum radio_path)index, RF_AC, 1950 RFREG_OFFSET_MASK, 0x010000); 1951 if (rtlpci->init_ready) { 1952 /* switch CV-curve control by LC-calibration */ 1953 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, 1954 BIT(17), 0x0); 1955 /* 4. Set LC calibration begin */ 1956 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW, 1957 0x08000, 0x01); 1958 } 1959 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6, 1960 RFREG_OFFSET_MASK); 1961 while ((!(u4tmp & BIT(11))) && timecount <= timeout) { 1962 mdelay(50); 1963 timecount += 50; 1964 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, 1965 RF_SYN_G6, RFREG_OFFSET_MASK); 1966 } 1967 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1968 "PHY_LCK finish delay for %d ms=2\n", timecount); 1969 rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK); 1970 if (index == 0 && rtlhal->interfaceindex == 0) { 1971 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1972 "path-A / 5G LCK\n"); 1973 } else { 1974 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1975 "path-B / 2.4G LCK\n"); 1976 } 1977 memset(curvecount_val, 0, sizeof(curvecount_val)); 1978 /* Set LC calibration off */ 1979 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW, 1980 0x08000, 0x0); 1981 RTPRINT(rtlpriv, FINIT, INIT_IQK, "set RF 0x18[15] = 0\n"); 1982 /* save Curve-counting number */ 1983 for (i = 0; i < CV_CURVE_CNT; i++) { 1984 u32 readval = 0, readval2 = 0; 1985 rtl_set_rfreg(hw, (enum radio_path)index, 0x3F, 1986 0x7f, i); 1987 1988 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D, 1989 RFREG_OFFSET_MASK, 0x0); 1990 readval = rtl_get_rfreg(hw, (enum radio_path)index, 1991 0x4F, RFREG_OFFSET_MASK); 1992 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5; 1993 /* reg 0x4f [4:0] */ 1994 /* reg 0x50 [19:10] */ 1995 readval2 = rtl_get_rfreg(hw, (enum radio_path)index, 1996 0x50, 0xffc00); 1997 curvecount_val[2 * i] = (((readval & 0x1F) << 10) | 1998 readval2); 1999 } 2000 if (index == 0 && rtlhal->interfaceindex == 0) 2001 rtl92d_phy_calc_curvindex(hw, targetchnl_5g, 2002 curvecount_val, 2003 true, curveindex_5g); 2004 else 2005 rtl92d_phy_calc_curvindex(hw, targetchnl_2g, 2006 curvecount_val, 2007 false, curveindex_2g); 2008 /* switch CV-curve control mode */ 2009 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, 2010 BIT(17), 0x1); 2011 } 2012 2013 /* Restore original situation */ 2014 for (index = 0; index < path; index++) { 2015 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; 2016 rtl_write_byte(rtlpriv, offset, 0x50); 2017 rtl_write_byte(rtlpriv, offset, rf_mode[index]); 2018 } 2019 if ((tmpreg & 0x70) != 0) 2020 rtl_write_byte(rtlpriv, 0xd03, tmpreg); 2021 else /*Deal with Packet TX case */ 2022 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 2023 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00); 2024 _rtl92d_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel); 2025} 2026 2027static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) 2028{ 2029 struct rtl_priv *rtlpriv = rtl_priv(hw); 2030 2031 RTPRINT(rtlpriv, FINIT, INIT_IQK, "cosa PHY_LCK ver=2\n"); 2032 _rtl92d_phy_lc_calibrate_sw(hw, is2t); 2033} 2034 2035void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) 2036{ 2037 struct rtl_priv *rtlpriv = rtl_priv(hw); 2038 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2039 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2040 u32 timeout = 2000, timecount = 0; 2041 2042 while (rtlpriv->mac80211.act_scanning && timecount < timeout) { 2043 udelay(50); 2044 timecount += 50; 2045 } 2046 2047 rtlphy->lck_inprogress = true; 2048 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2049 "LCK:Start!!! currentband %x delay %d ms\n", 2050 rtlhal->current_bandtype, timecount); 2051 2052 _rtl92d_phy_lc_calibrate(hw, is2t); 2053 2054 rtlphy->lck_inprogress = false; 2055 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LCK:Finish!!!\n"); 2056} 2057 2058static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, 2059 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid, 2060 u32 para1, u32 para2, u32 msdelay) 2061{ 2062 struct swchnlcmd *pcmd; 2063 2064 if (cmdtable == NULL) { 2065 WARN_ONCE(true, "rtl8192de: cmdtable cannot be NULL\n"); 2066 return false; 2067 } 2068 if (cmdtableidx >= cmdtablesz) 2069 return false; 2070 2071 pcmd = cmdtable + cmdtableidx; 2072 pcmd->cmdid = cmdid; 2073 pcmd->para1 = para1; 2074 pcmd->para2 = para2; 2075 pcmd->msdelay = msdelay; 2076 return true; 2077} 2078 2079static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, 2080 u8 channel, u8 *stage, u8 *step, 2081 u32 *delay) 2082{ 2083 struct rtl_priv *rtlpriv = rtl_priv(hw); 2084 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2085 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT]; 2086 u32 precommoncmdcnt; 2087 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT]; 2088 u32 postcommoncmdcnt; 2089 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT]; 2090 u32 rfdependcmdcnt; 2091 struct swchnlcmd *currentcmd = NULL; 2092 u8 rfpath; 2093 u8 num_total_rfpath = rtlphy->num_total_rfpath; 2094 2095 precommoncmdcnt = 0; 2096 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 2097 MAX_PRECMD_CNT, 2098 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); 2099 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 2100 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); 2101 postcommoncmdcnt = 0; 2102 _rtl92d_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++, 2103 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); 2104 rfdependcmdcnt = 0; 2105 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 2106 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG, 2107 RF_CHNLBW, channel, 0); 2108 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 2109 MAX_RFDEPENDCMD_CNT, CMDID_END, 2110 0, 0, 0); 2111 2112 do { 2113 switch (*stage) { 2114 case 0: 2115 currentcmd = &precommoncmd[*step]; 2116 break; 2117 case 1: 2118 currentcmd = &rfdependcmd[*step]; 2119 break; 2120 case 2: 2121 currentcmd = &postcommoncmd[*step]; 2122 break; 2123 } 2124 if (currentcmd->cmdid == CMDID_END) { 2125 if ((*stage) == 2) { 2126 return true; 2127 } else { 2128 (*stage)++; 2129 (*step) = 0; 2130 continue; 2131 } 2132 } 2133 switch (currentcmd->cmdid) { 2134 case CMDID_SET_TXPOWEROWER_LEVEL: 2135 rtl92d_phy_set_txpower_level(hw, channel); 2136 break; 2137 case CMDID_WRITEPORT_ULONG: 2138 rtl_write_dword(rtlpriv, currentcmd->para1, 2139 currentcmd->para2); 2140 break; 2141 case CMDID_WRITEPORT_USHORT: 2142 rtl_write_word(rtlpriv, currentcmd->para1, 2143 (u16)currentcmd->para2); 2144 break; 2145 case CMDID_WRITEPORT_UCHAR: 2146 rtl_write_byte(rtlpriv, currentcmd->para1, 2147 (u8)currentcmd->para2); 2148 break; 2149 case CMDID_RF_WRITEREG: 2150 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { 2151 rtlphy->rfreg_chnlval[rfpath] = 2152 ((rtlphy->rfreg_chnlval[rfpath] & 2153 0xffffff00) | currentcmd->para2); 2154 if (rtlpriv->rtlhal.current_bandtype == 2155 BAND_ON_5G) { 2156 if (currentcmd->para2 > 99) 2157 rtlphy->rfreg_chnlval[rfpath] = 2158 rtlphy->rfreg_chnlval 2159 [rfpath] | (BIT(18)); 2160 else 2161 rtlphy->rfreg_chnlval[rfpath] = 2162 rtlphy->rfreg_chnlval 2163 [rfpath] & (~BIT(18)); 2164 rtlphy->rfreg_chnlval[rfpath] |= 2165 (BIT(16) | BIT(8)); 2166 } else { 2167 rtlphy->rfreg_chnlval[rfpath] &= 2168 ~(BIT(8) | BIT(16) | BIT(18)); 2169 } 2170 rtl_set_rfreg(hw, (enum radio_path)rfpath, 2171 currentcmd->para1, 2172 RFREG_OFFSET_MASK, 2173 rtlphy->rfreg_chnlval[rfpath]); 2174 _rtl92d_phy_reload_imr_setting(hw, channel, 2175 rfpath); 2176 } 2177 _rtl92d_phy_switch_rf_setting(hw, channel); 2178 /* do IQK when all parameters are ready */ 2179 rtl92d_phy_reload_iqk_setting(hw, channel); 2180 break; 2181 default: 2182 pr_err("switch case %#x not processed\n", 2183 currentcmd->cmdid); 2184 break; 2185 } 2186 break; 2187 } while (true); 2188 (*delay) = currentcmd->msdelay; 2189 (*step)++; 2190 return false; 2191} 2192 2193u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw) 2194{ 2195 struct rtl_priv *rtlpriv = rtl_priv(hw); 2196 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2197 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2198 u32 delay; 2199 u32 timeout = 1000, timecount = 0; 2200 u8 channel = rtlphy->current_channel; 2201 u32 ret_value; 2202 2203 if (rtlphy->sw_chnl_inprogress) 2204 return 0; 2205 if (rtlphy->set_bwmode_inprogress) 2206 return 0; 2207 2208 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { 2209 rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD, 2210 "sw_chnl_inprogress false driver sleep or unload\n"); 2211 return 0; 2212 } 2213 while (rtlphy->lck_inprogress && timecount < timeout) { 2214 mdelay(50); 2215 timecount += 50; 2216 } 2217 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY && 2218 rtlhal->bandset == BAND_ON_BOTH) { 2219 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER, 2220 MASKDWORD); 2221 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0))) 2222 rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G); 2223 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0))) 2224 rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G); 2225 } 2226 switch (rtlhal->current_bandtype) { 2227 case BAND_ON_5G: 2228 /* Get first channel error when change between 2229 * 5G and 2.4G band. */ 2230 if (WARN_ONCE(channel <= 14, "rtl8192de: 5G but channel<=14\n")) 2231 return 0; 2232 break; 2233 case BAND_ON_2_4G: 2234 /* Get first channel error when change between 2235 * 5G and 2.4G band. */ 2236 if (WARN_ONCE(channel > 14, "rtl8192de: 2G but channel>14\n")) 2237 return 0; 2238 break; 2239 default: 2240 WARN_ONCE(true, "rtl8192de: Invalid WirelessMode(%#x)!!\n", 2241 rtlpriv->mac80211.mode); 2242 break; 2243 } 2244 rtlphy->sw_chnl_inprogress = true; 2245 if (channel == 0) 2246 channel = 1; 2247 rtlphy->sw_chnl_stage = 0; 2248 rtlphy->sw_chnl_step = 0; 2249 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, 2250 "switch to channel%d\n", rtlphy->current_channel); 2251 2252 do { 2253 if (!rtlphy->sw_chnl_inprogress) 2254 break; 2255 if (!_rtl92d_phy_sw_chnl_step_by_step(hw, 2256 rtlphy->current_channel, 2257 &rtlphy->sw_chnl_stage, &rtlphy->sw_chnl_step, &delay)) { 2258 if (delay > 0) 2259 mdelay(delay); 2260 else 2261 continue; 2262 } else { 2263 rtlphy->sw_chnl_inprogress = false; 2264 } 2265 break; 2266 } while (true); 2267 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 2268 rtlphy->sw_chnl_inprogress = false; 2269 return 1; 2270} 2271 2272static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw) 2273{ 2274 struct rtl_priv *rtlpriv = rtl_priv(hw); 2275 2276 /* a. SYS_CLKR 0x08[11] = 1 restore MAC clock */ 2277 /* b. SPS_CTRL 0x11[7:0] = 0x2b */ 2278 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) 2279 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 2280 /* c. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */ 2281 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 2282 /* RF_ON_EXCEP(d~g): */ 2283 /* d. APSD_CTRL 0x600[7:0] = 0x00 */ 2284 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); 2285 /* e. SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function again */ 2286 /* f. SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function*/ 2287 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 2288 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 2289 /* g. txpause 0x522[7:0] = 0x00 enable mac tx queue */ 2290 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 2291} 2292 2293static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw) 2294{ 2295 struct rtl_priv *rtlpriv = rtl_priv(hw); 2296 u32 u4btmp; 2297 u8 delay = 5; 2298 2299 /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */ 2300 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 2301 /* b. RF path 0 offset 0x00 = 0x00 disable RF */ 2302 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 2303 /* c. APSD_CTRL 0x600[7:0] = 0x40 */ 2304 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 2305 /* d. APSD_CTRL 0x600[7:0] = 0x00 2306 * APSD_CTRL 0x600[7:0] = 0x00 2307 * RF path 0 offset 0x00 = 0x00 2308 * APSD_CTRL 0x600[7:0] = 0x40 2309 * */ 2310 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); 2311 while (u4btmp != 0 && delay > 0) { 2312 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0); 2313 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 2314 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 2315 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); 2316 delay--; 2317 } 2318 if (delay == 0) { 2319 /* Jump out the LPS turn off sequence to RF_ON_EXCEP */ 2320 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); 2321 2322 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 2323 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 2324 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 2325 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 2326 "Fail !!! Switch RF timeout\n"); 2327 return; 2328 } 2329 /* e. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */ 2330 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 2331 /* f. SPS_CTRL 0x11[7:0] = 0x22 */ 2332 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) 2333 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); 2334 /* g. SYS_CLKR 0x08[11] = 0 gated MAC clock */ 2335} 2336 2337bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw, 2338 enum rf_pwrstate rfpwr_state) 2339{ 2340 2341 bool bresult = true; 2342 struct rtl_priv *rtlpriv = rtl_priv(hw); 2343 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2344 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2345 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2346 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2347 u8 i, queue_id; 2348 struct rtl8192_tx_ring *ring = NULL; 2349 2350 if (rfpwr_state == ppsc->rfpwr_state) 2351 return false; 2352 switch (rfpwr_state) { 2353 case ERFON: 2354 if ((ppsc->rfpwr_state == ERFOFF) && 2355 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 2356 bool rtstatus; 2357 u32 initializecount = 0; 2358 do { 2359 initializecount++; 2360 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 2361 "IPS Set eRf nic enable\n"); 2362 rtstatus = rtl_ps_enable_nic(hw); 2363 } while (!rtstatus && (initializecount < 10)); 2364 2365 RT_CLEAR_PS_LEVEL(ppsc, 2366 RT_RF_OFF_LEVL_HALT_NIC); 2367 } else { 2368 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 2369 "awake, slept:%d ms state_inap:%x\n", 2370 jiffies_to_msecs(jiffies - 2371 ppsc->last_sleep_jiffies), 2372 rtlpriv->psc.state_inap); 2373 ppsc->last_awake_jiffies = jiffies; 2374 _rtl92d_phy_set_rfon(hw); 2375 } 2376 2377 if (mac->link_state == MAC80211_LINKED) 2378 rtlpriv->cfg->ops->led_control(hw, 2379 LED_CTL_LINK); 2380 else 2381 rtlpriv->cfg->ops->led_control(hw, 2382 LED_CTL_NO_LINK); 2383 break; 2384 case ERFOFF: 2385 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) { 2386 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 2387 "IPS Set eRf nic disable\n"); 2388 rtl_ps_disable_nic(hw); 2389 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2390 } else { 2391 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 2392 rtlpriv->cfg->ops->led_control(hw, 2393 LED_CTL_NO_LINK); 2394 else 2395 rtlpriv->cfg->ops->led_control(hw, 2396 LED_CTL_POWER_OFF); 2397 } 2398 break; 2399 case ERFSLEEP: 2400 if (ppsc->rfpwr_state == ERFOFF) 2401 return false; 2402 2403 for (queue_id = 0, i = 0; 2404 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 2405 ring = &pcipriv->dev.tx_ring[queue_id]; 2406 if (skb_queue_len(&ring->queue) == 0 || 2407 queue_id == BEACON_QUEUE) { 2408 queue_id++; 2409 continue; 2410 } else if (rtlpci->pdev->current_state != PCI_D0) { 2411 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 2412 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", 2413 i + 1, queue_id); 2414 break; 2415 } else { 2416 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 2417 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n", 2418 i + 1, queue_id, 2419 skb_queue_len(&ring->queue)); 2420 udelay(10); 2421 i++; 2422 } 2423 2424 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 2425 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 2426 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n", 2427 MAX_DOZE_WAITING_TIMES_9x, queue_id, 2428 skb_queue_len(&ring->queue)); 2429 break; 2430 } 2431 } 2432 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 2433 "Set rfsleep awakened:%d ms\n", 2434 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies)); 2435 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 2436 "sleep awakened:%d ms state_inap:%x\n", 2437 jiffies_to_msecs(jiffies - 2438 ppsc->last_awake_jiffies), 2439 rtlpriv->psc.state_inap); 2440 ppsc->last_sleep_jiffies = jiffies; 2441 _rtl92d_phy_set_rfsleep(hw); 2442 break; 2443 default: 2444 pr_err("switch case %#x not processed\n", 2445 rfpwr_state); 2446 bresult = false; 2447 break; 2448 } 2449 if (bresult) 2450 ppsc->rfpwr_state = rfpwr_state; 2451 return bresult; 2452} 2453 2454void rtl92d_phy_set_poweron(struct ieee80211_hw *hw) 2455{ 2456 struct rtl_priv *rtlpriv = rtl_priv(hw); 2457 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2458 unsigned long flags; 2459 u8 value8; 2460 u16 i; 2461 u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1); 2462 2463 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ 2464 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 2465 value8 = rtl_read_byte(rtlpriv, mac_reg); 2466 value8 |= BIT(1); 2467 rtl_write_byte(rtlpriv, mac_reg, value8); 2468 } else { 2469 value8 = rtl_read_byte(rtlpriv, mac_reg); 2470 value8 &= (~BIT(1)); 2471 rtl_write_byte(rtlpriv, mac_reg, value8); 2472 } 2473 2474 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) { 2475 value8 = rtl_read_byte(rtlpriv, REG_MAC0); 2476 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON); 2477 } else { 2478 spin_lock_irqsave(&globalmutex_power, flags); 2479 if (rtlhal->interfaceindex == 0) { 2480 value8 = rtl_read_byte(rtlpriv, REG_MAC0); 2481 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON); 2482 } else { 2483 value8 = rtl_read_byte(rtlpriv, REG_MAC1); 2484 rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON); 2485 } 2486 value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); 2487 spin_unlock_irqrestore(&globalmutex_power, flags); 2488 for (i = 0; i < 200; i++) { 2489 if ((value8 & BIT(7)) == 0) { 2490 break; 2491 } else { 2492 udelay(500); 2493 spin_lock_irqsave(&globalmutex_power, flags); 2494 value8 = rtl_read_byte(rtlpriv, 2495 REG_POWER_OFF_IN_PROCESS); 2496 spin_unlock_irqrestore(&globalmutex_power, 2497 flags); 2498 } 2499 } 2500 if (i == 200) 2501 WARN_ONCE(true, "rtl8192de: Another mac power off over time\n"); 2502 } 2503} 2504 2505void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw) 2506{ 2507 struct rtl_priv *rtlpriv = rtl_priv(hw); 2508 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2509 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2510 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2511 u8 rfpath, i; 2512 2513 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n"); 2514 /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */ 2515 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 2516 /* r_select_5G for path_A/B,0x878 */ 2517 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0); 2518 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0); 2519 if (rtlhal->macphymode != DUALMAC_DUALPHY) { 2520 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0); 2521 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0); 2522 } 2523 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */ 2524 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0); 2525 /* fc_area 0xd2c */ 2526 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0); 2527 /* 5G LAN ON */ 2528 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa); 2529 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */ 2530 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, 2531 0x40000100); 2532 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, 2533 0x40000100); 2534 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 2535 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 2536 BIT(10) | BIT(6) | BIT(5), 2537 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) | 2538 (rtlefuse->eeprom_c9 & BIT(1)) | 2539 ((rtlefuse->eeprom_cc & BIT(1)) << 4)); 2540 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 2541 BIT(10) | BIT(6) | BIT(5), 2542 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) | 2543 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | 2544 ((rtlefuse->eeprom_cc & BIT(0)) << 5)); 2545 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0); 2546 } else { 2547 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 2548 BIT(26) | BIT(22) | BIT(21) | BIT(10) | 2549 BIT(6) | BIT(5), 2550 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) | 2551 (rtlefuse->eeprom_c9 & BIT(1)) | 2552 ((rtlefuse->eeprom_cc & BIT(1)) << 4) | 2553 ((rtlefuse->eeprom_c9 & BIT(7)) << 9) | 2554 ((rtlefuse->eeprom_c9 & BIT(5)) << 12) | 2555 ((rtlefuse->eeprom_cc & BIT(3)) << 18)); 2556 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 2557 BIT(10) | BIT(6) | BIT(5), 2558 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) | 2559 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | 2560 ((rtlefuse->eeprom_cc & BIT(0)) << 5)); 2561 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 2562 BIT(10) | BIT(6) | BIT(5), 2563 ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) | 2564 ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) | 2565 ((rtlefuse->eeprom_cc & BIT(2)) << 3)); 2566 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, 2567 BIT(31) | BIT(15), 0); 2568 } 2569 /* 1.5V_LDO */ 2570 } else { 2571 /* r_select_5G for path_A/B */ 2572 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1); 2573 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1); 2574 if (rtlhal->macphymode != DUALMAC_DUALPHY) { 2575 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1); 2576 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1); 2577 } 2578 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */ 2579 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1); 2580 /* fc_area */ 2581 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1); 2582 /* 5G LAN ON */ 2583 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0); 2584 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */ 2585 if (rtlefuse->internal_pa_5g[0]) 2586 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, 2587 0x2d4000b5); 2588 else 2589 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, 2590 0x20000080); 2591 if (rtlefuse->internal_pa_5g[1]) 2592 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, 2593 0x2d4000b5); 2594 else 2595 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, 2596 0x20000080); 2597 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 2598 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 2599 BIT(10) | BIT(6) | BIT(5), 2600 (rtlefuse->eeprom_cc & BIT(5))); 2601 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 2602 ((rtlefuse->eeprom_cc & BIT(4)) >> 4)); 2603 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 2604 (rtlefuse->eeprom_cc & BIT(4)) >> 4); 2605 } else { 2606 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 2607 BIT(26) | BIT(22) | BIT(21) | BIT(10) | 2608 BIT(6) | BIT(5), 2609 (rtlefuse->eeprom_cc & BIT(5)) | 2610 ((rtlefuse->eeprom_cc & BIT(7)) << 14)); 2611 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 2612 ((rtlefuse->eeprom_cc & BIT(4)) >> 4)); 2613 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), 2614 ((rtlefuse->eeprom_cc & BIT(6)) >> 6)); 2615 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, 2616 BIT(31) | BIT(15), 2617 ((rtlefuse->eeprom_cc & BIT(4)) >> 4) | 2618 ((rtlefuse->eeprom_cc & BIT(6)) << 10)); 2619 } 2620 } 2621 /* update IQK related settings */ 2622 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); 2623 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); 2624 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 0x00); 2625 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) | 2626 BIT(26) | BIT(24), 0x00); 2627 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 0x00); 2628 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00); 2629 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00); 2630 2631 /* Update RF */ 2632 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; 2633 rfpath++) { 2634 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 2635 /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ 2636 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) | 2637 BIT(18), 0); 2638 /* RF0x0b[16:14] =3b'111 */ 2639 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, 2640 0x1c000, 0x07); 2641 } else { 2642 /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ 2643 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | 2644 BIT(16) | BIT(18), 2645 (BIT(16) | BIT(8)) >> 8); 2646 } 2647 } 2648 /* Update for all band. */ 2649 /* DMDP */ 2650 if (rtlphy->rf_type == RF_1T1R) { 2651 /* Use antenna 0,0xc04,0xd04 */ 2652 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11); 2653 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1); 2654 2655 /* enable ad/da clock1 for dual-phy reg0x888 */ 2656 if (rtlhal->interfaceindex == 0) { 2657 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | 2658 BIT(13), 0x3); 2659 } else { 2660 rtl92d_phy_enable_anotherphy(hw, false); 2661 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2662 "MAC1 use DBI to update 0x888\n"); 2663 /* 0x888 */ 2664 rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN, 2665 rtl92de_read_dword_dbi(hw, 2666 RFPGA0_ADDALLOCKEN, 2667 BIT(3)) | BIT(12) | BIT(13), 2668 BIT(3)); 2669 rtl92d_phy_powerdown_anotherphy(hw, false); 2670 } 2671 } else { 2672 /* Single PHY */ 2673 /* Use antenna 0 & 1,0xc04,0xd04 */ 2674 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33); 2675 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3); 2676 /* disable ad/da clock1,0x888 */ 2677 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0); 2678 } 2679 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; 2680 rfpath++) { 2681 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath, 2682 RF_CHNLBW, RFREG_OFFSET_MASK); 2683 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C, 2684 RFREG_OFFSET_MASK); 2685 } 2686 for (i = 0; i < 2; i++) 2687 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n", 2688 rtlphy->rfreg_chnlval[i]); 2689 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<==\n"); 2690 2691} 2692 2693bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw) 2694{ 2695 struct rtl_priv *rtlpriv = rtl_priv(hw); 2696 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2697 u8 u1btmp; 2698 unsigned long flags; 2699 2700 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) { 2701 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); 2702 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON)); 2703 return true; 2704 } 2705 spin_lock_irqsave(&globalmutex_power, flags); 2706 if (rtlhal->interfaceindex == 0) { 2707 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); 2708 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON)); 2709 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1); 2710 u1btmp &= MAC1_ON; 2711 } else { 2712 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1); 2713 rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON)); 2714 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); 2715 u1btmp &= MAC0_ON; 2716 } 2717 if (u1btmp) { 2718 spin_unlock_irqrestore(&globalmutex_power, flags); 2719 return false; 2720 } 2721 u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); 2722 u1btmp |= BIT(7); 2723 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp); 2724 spin_unlock_irqrestore(&globalmutex_power, flags); 2725 return true; 2726}
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