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phy_common.c

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linux-6.19.14/drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c C 
   1// SPDX-License-Identifier: GPL-2.0
   2/* Copyright(c) 2009-2012  Realtek Corporation.*/
   3
   4#include "../wifi.h"
   5#include "../rtl8192ce/reg.h"
   6#include "../rtl8192ce/def.h"
   7#include "dm_common.h"
   8#include "fw_common.h"
   9#include "phy_common.h"
  10#include <linux/export.h>
  11
  12u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
  13{
  14	struct rtl_priv *rtlpriv = rtl_priv(hw);
  15	u32 returnvalue, originalvalue, bitshift;
  16
  17	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
  18		regaddr, bitmask);
  19	originalvalue = rtl_read_dword(rtlpriv, regaddr);
  20	bitshift = calculate_bit_shift(bitmask);
  21	returnvalue = (originalvalue & bitmask) >> bitshift;
  22
  23	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
  24		"BBR MASK=0x%x Addr[0x%x]=0x%x\n",
  25		bitmask, regaddr, originalvalue);
  26
  27	return returnvalue;
  28}
  29EXPORT_SYMBOL(rtl92c_phy_query_bb_reg);
  30
  31void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
  32			   u32 regaddr, u32 bitmask, u32 data)
  33{
  34	struct rtl_priv *rtlpriv = rtl_priv(hw);
  35	u32 originalvalue, bitshift;
  36
  37	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
  38		"regaddr(%#x), bitmask(%#x), data(%#x)\n",
  39		regaddr, bitmask, data);
  40
  41	if (bitmask != MASKDWORD) {
  42		originalvalue = rtl_read_dword(rtlpriv, regaddr);
  43		bitshift = calculate_bit_shift(bitmask);
  44		data = ((originalvalue & (~bitmask)) | (data << bitshift));
  45	}
  46
  47	rtl_write_dword(rtlpriv, regaddr, data);
  48
  49	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
  50		"regaddr(%#x), bitmask(%#x), data(%#x)\n",
  51		regaddr, bitmask, data);
  52}
  53EXPORT_SYMBOL(rtl92c_phy_set_bb_reg);
  54
  55u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
  56				  enum radio_path rfpath, u32 offset)
  57{
  58	WARN_ONCE(true, "rtl8192c-common: _rtl92c_phy_fw_rf_serial_read deprecated!\n");
  59	return 0;
  60}
  61EXPORT_SYMBOL(_rtl92c_phy_fw_rf_serial_read);
  62
  63void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
  64				    enum radio_path rfpath, u32 offset,
  65				    u32 data)
  66{
  67	WARN_ONCE(true, "rtl8192c-common: _rtl92c_phy_fw_rf_serial_write deprecated!\n");
  68}
  69EXPORT_SYMBOL(_rtl92c_phy_fw_rf_serial_write);
  70
  71u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
  72			       enum radio_path rfpath, u32 offset)
  73{
  74	struct rtl_priv *rtlpriv = rtl_priv(hw);
  75	struct rtl_phy *rtlphy = &(rtlpriv->phy);
  76	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
  77	u32 newoffset;
  78	u32 tmplong, tmplong2;
  79	u8 rfpi_enable = 0;
  80	u32 retvalue;
  81
  82	offset &= 0x3f;
  83	newoffset = offset;
  84	if (RT_CANNOT_IO(hw)) {
  85		pr_err("return all one\n");
  86		return 0xFFFFFFFF;
  87	}
  88	tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
  89	if (rfpath == RF90_PATH_A)
  90		tmplong2 = tmplong;
  91	else
  92		tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
  93	tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
  94	    (newoffset << 23) | BLSSIREADEDGE;
  95	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
  96		      tmplong & (~BLSSIREADEDGE));
  97	mdelay(1);
  98	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
  99	mdelay(1);
 100	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
 101		      tmplong | BLSSIREADEDGE);
 102	mdelay(1);
 103	if (rfpath == RF90_PATH_A)
 104		rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
 105						 BIT(8));
 106	else if (rfpath == RF90_PATH_B)
 107		rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
 108						 BIT(8));
 109	if (rfpi_enable)
 110		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
 111					 BLSSIREADBACKDATA);
 112	else
 113		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
 114					 BLSSIREADBACKDATA);
 115	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
 116		rfpath, pphyreg->rf_rb,
 117		retvalue);
 118	return retvalue;
 119}
 120EXPORT_SYMBOL(_rtl92c_phy_rf_serial_read);
 121
 122void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
 123				 enum radio_path rfpath, u32 offset,
 124				 u32 data)
 125{
 126	u32 data_and_addr;
 127	u32 newoffset;
 128	struct rtl_priv *rtlpriv = rtl_priv(hw);
 129	struct rtl_phy *rtlphy = &(rtlpriv->phy);
 130	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 131
 132	if (RT_CANNOT_IO(hw)) {
 133		pr_err("stop\n");
 134		return;
 135	}
 136	offset &= 0x3f;
 137	newoffset = offset;
 138	data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
 139	rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
 140	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
 141		rfpath, pphyreg->rf3wire_offset,
 142		data_and_addr);
 143}
 144EXPORT_SYMBOL(_rtl92c_phy_rf_serial_write);
 145
 146static void _rtl92c_phy_bb_config_1t(struct ieee80211_hw *hw)
 147{
 148	rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
 149	rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022);
 150	rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45);
 151	rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
 152	rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1);
 153	rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2);
 154	rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2);
 155	rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2);
 156	rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2);
 157	rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2);
 158}
 159
 160bool rtl92c_phy_rf_config(struct ieee80211_hw *hw)
 161{
 162	struct rtl_priv *rtlpriv = rtl_priv(hw);
 163
 164	return rtlpriv->cfg->ops->phy_rf6052_config(hw);
 165}
 166EXPORT_SYMBOL(rtl92c_phy_rf_config);
 167
 168bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
 169{
 170	struct rtl_priv *rtlpriv = rtl_priv(hw);
 171	struct rtl_phy *rtlphy = &(rtlpriv->phy);
 172	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 173	bool rtstatus;
 174
 175	rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
 176						 BASEBAND_CONFIG_PHY_REG);
 177	if (!rtstatus) {
 178		pr_err("Write BB Reg Fail!!\n");
 179		return false;
 180	}
 181	if (rtlphy->rf_type == RF_1T2R) {
 182		_rtl92c_phy_bb_config_1t(hw);
 183		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
 184	}
 185	if (rtlefuse->autoload_failflag == false) {
 186		rtlphy->pwrgroup_cnt = 0;
 187		rtstatus = rtlpriv->cfg->ops->config_bb_with_pgheaderfile(hw,
 188						   BASEBAND_CONFIG_PHY_REG);
 189	}
 190	if (!rtstatus) {
 191		pr_err("BB_PG Reg Fail!!\n");
 192		return false;
 193	}
 194	rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
 195						 BASEBAND_CONFIG_AGC_TAB);
 196	if (!rtstatus) {
 197		pr_err("AGC Table Fail\n");
 198		return false;
 199	}
 200	rtlphy->cck_high_power =
 201		(bool)(rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, 0x200));
 202
 203	return true;
 204}
 205
 206EXPORT_SYMBOL(_rtl92c_phy_bb8192c_config_parafile);
 207
 208void _rtl92c_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
 209					    u32 regaddr, u32 bitmask,
 210					    u32 data)
 211{
 212	struct rtl_priv *rtlpriv = rtl_priv(hw);
 213	struct rtl_phy *rtlphy = &(rtlpriv->phy);
 214
 215	if (regaddr == RTXAGC_A_RATE18_06) {
 216		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
 217		    data;
 218		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 219			"MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
 220			rtlphy->pwrgroup_cnt,
 221			rtlphy->mcs_txpwrlevel_origoffset
 222			[rtlphy->pwrgroup_cnt][0]);
 223	}
 224	if (regaddr == RTXAGC_A_RATE54_24) {
 225		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
 226		    data;
 227		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 228			"MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
 229			rtlphy->pwrgroup_cnt,
 230			rtlphy->mcs_txpwrlevel_origoffset
 231			[rtlphy->pwrgroup_cnt][1]);
 232	}
 233	if (regaddr == RTXAGC_A_CCK1_MCS32) {
 234		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
 235		    data;
 236		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 237			"MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
 238			rtlphy->pwrgroup_cnt,
 239			rtlphy->mcs_txpwrlevel_origoffset
 240			[rtlphy->pwrgroup_cnt][6]);
 241	}
 242	if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
 243		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] =
 244		    data;
 245		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 246			"MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
 247			rtlphy->pwrgroup_cnt,
 248			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 249							    pwrgroup_cnt][7]);
 250	}
 251	if (regaddr == RTXAGC_A_MCS03_MCS00) {
 252		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
 253		    data;
 254		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 255			"MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
 256			rtlphy->pwrgroup_cnt,
 257			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 258							    pwrgroup_cnt][2]);
 259	}
 260	if (regaddr == RTXAGC_A_MCS07_MCS04) {
 261		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
 262		    data;
 263		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 264			"MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
 265			rtlphy->pwrgroup_cnt,
 266			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 267							    pwrgroup_cnt][3]);
 268	}
 269	if (regaddr == RTXAGC_A_MCS11_MCS08) {
 270		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
 271		    data;
 272		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 273			"MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
 274			rtlphy->pwrgroup_cnt,
 275			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 276							    pwrgroup_cnt][4]);
 277	}
 278	if (regaddr == RTXAGC_A_MCS15_MCS12) {
 279		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
 280		    data;
 281		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 282			"MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
 283			rtlphy->pwrgroup_cnt,
 284			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 285							    pwrgroup_cnt][5]);
 286	}
 287	if (regaddr == RTXAGC_B_RATE18_06) {
 288		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] =
 289		    data;
 290		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 291			"MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
 292			rtlphy->pwrgroup_cnt,
 293			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 294							    pwrgroup_cnt][8]);
 295	}
 296	if (regaddr == RTXAGC_B_RATE54_24) {
 297		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] =
 298		    data;
 299		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 300			"MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
 301			rtlphy->pwrgroup_cnt,
 302			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 303							    pwrgroup_cnt][9]);
 304	}
 305	if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
 306		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] =
 307		    data;
 308		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 309			"MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
 310			rtlphy->pwrgroup_cnt,
 311			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 312							    pwrgroup_cnt][14]);
 313	}
 314	if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
 315		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] =
 316		    data;
 317		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 318			"MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
 319			rtlphy->pwrgroup_cnt,
 320			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 321							    pwrgroup_cnt][15]);
 322	}
 323	if (regaddr == RTXAGC_B_MCS03_MCS00) {
 324		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] =
 325		    data;
 326		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 327			"MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
 328			rtlphy->pwrgroup_cnt,
 329			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 330							    pwrgroup_cnt][10]);
 331	}
 332	if (regaddr == RTXAGC_B_MCS07_MCS04) {
 333		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] =
 334		    data;
 335		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 336			"MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
 337			rtlphy->pwrgroup_cnt,
 338			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 339							    pwrgroup_cnt][11]);
 340	}
 341	if (regaddr == RTXAGC_B_MCS11_MCS08) {
 342		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] =
 343		    data;
 344		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 345			"MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
 346			rtlphy->pwrgroup_cnt,
 347			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 348							    pwrgroup_cnt][12]);
 349	}
 350	if (regaddr == RTXAGC_B_MCS15_MCS12) {
 351		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] =
 352		    data;
 353		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 354			"MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
 355			rtlphy->pwrgroup_cnt,
 356			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 357							    pwrgroup_cnt][13]);
 358
 359		rtlphy->pwrgroup_cnt++;
 360	}
 361}
 362EXPORT_SYMBOL(_rtl92c_store_pwrindex_diffrate_offset);
 363
 364void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
 365{
 366	struct rtl_priv *rtlpriv = rtl_priv(hw);
 367	struct rtl_phy *rtlphy = &(rtlpriv->phy);
 368
 369	rtlphy->default_initialgain[0] =
 370	    (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
 371	rtlphy->default_initialgain[1] =
 372	    (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
 373	rtlphy->default_initialgain[2] =
 374	    (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
 375	rtlphy->default_initialgain[3] =
 376	    (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
 377
 378	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 379		"Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
 380		rtlphy->default_initialgain[0],
 381		rtlphy->default_initialgain[1],
 382		rtlphy->default_initialgain[2],
 383		rtlphy->default_initialgain[3]);
 384
 385	rtlphy->framesync = (u8)rtl_get_bbreg(hw,
 386					       ROFDM0_RXDETECTOR3, MASKBYTE0);
 387	rtlphy->framesync_c34 = rtl_get_bbreg(hw,
 388					      ROFDM0_RXDETECTOR2, MASKDWORD);
 389
 390	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 391		"Default framesync (0x%x) = 0x%x\n",
 392		ROFDM0_RXDETECTOR3, rtlphy->framesync);
 393}
 394
 395void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
 396{
 397	struct rtl_priv *rtlpriv = rtl_priv(hw);
 398	struct rtl_phy *rtlphy = &(rtlpriv->phy);
 399
 400	rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 401	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 402	rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 403	rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 404
 405	rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 406	rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 407	rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 408	rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 409
 410	rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
 411	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
 412
 413	rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
 414	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
 415
 416	rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
 417	    RFPGA0_XA_LSSIPARAMETER;
 418	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
 419	    RFPGA0_XB_LSSIPARAMETER;
 420
 421	rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
 422	rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
 423	rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
 424	rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
 425
 426	rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 427	rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 428	rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 429	rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 430
 431	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
 432	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
 433
 434	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
 435	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
 436
 437	rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 438	rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 439	rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 440	rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 441
 442	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
 443	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
 444	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
 445	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
 446
 447	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
 448	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
 449	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
 450	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
 451
 452	rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
 453	rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
 454	rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;
 455	rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
 456
 457	rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
 458	rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
 459	rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
 460	rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
 461
 462	rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
 463	rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
 464	rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
 465	rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
 466
 467	rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
 468	rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
 469	rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
 470	rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
 471
 472	rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
 473	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
 474	rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
 475	rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
 476
 477	rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
 478	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
 479
 480}
 481EXPORT_SYMBOL(_rtl92c_phy_init_bb_rf_register_definition);
 482
 483void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
 484{
 485	struct rtl_priv *rtlpriv = rtl_priv(hw);
 486	struct rtl_phy *rtlphy = &(rtlpriv->phy);
 487	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 488	u8 txpwr_level;
 489	long txpwr_dbm;
 490
 491	txpwr_level = rtlphy->cur_cck_txpwridx;
 492	txpwr_dbm = _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B,
 493						 txpwr_level);
 494	txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
 495	    rtlefuse->legacy_ht_txpowerdiff;
 496	if (_rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
 497					 txpwr_level) > txpwr_dbm)
 498		txpwr_dbm =
 499		    _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
 500						 txpwr_level);
 501	txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
 502	if (_rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
 503					 txpwr_level) > txpwr_dbm)
 504		txpwr_dbm =
 505		    _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
 506						 txpwr_level);
 507	*powerlevel = txpwr_dbm;
 508}
 509
 510static void _rtl92c_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
 511				      u8 *cckpowerlevel, u8 *ofdmpowerlevel)
 512{
 513	struct rtl_priv *rtlpriv = rtl_priv(hw);
 514	struct rtl_phy *rtlphy = &(rtlpriv->phy);
 515	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 516	u8 index = (channel - 1);
 517
 518	cckpowerlevel[RF90_PATH_A] =
 519	    rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
 520	cckpowerlevel[RF90_PATH_B] =
 521	    rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
 522	if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) {
 523		ofdmpowerlevel[RF90_PATH_A] =
 524		    rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
 525		ofdmpowerlevel[RF90_PATH_B] =
 526		    rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
 527	} else if (get_rf_type(rtlphy) == RF_2T2R) {
 528		ofdmpowerlevel[RF90_PATH_A] =
 529		    rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
 530		ofdmpowerlevel[RF90_PATH_B] =
 531		    rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
 532	}
 533}
 534
 535static void _rtl92c_ccxpower_index_check(struct ieee80211_hw *hw,
 536					 u8 channel, u8 *cckpowerlevel,
 537					 u8 *ofdmpowerlevel)
 538{
 539	struct rtl_priv *rtlpriv = rtl_priv(hw);
 540	struct rtl_phy *rtlphy = &(rtlpriv->phy);
 541
 542	rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
 543	rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
 544}
 545
 546void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
 547{
 548	struct rtl_priv *rtlpriv = rtl_priv(hw);
 549	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 550	u8 cckpowerlevel[2], ofdmpowerlevel[2];
 551
 552	if (!rtlefuse->txpwr_fromeprom)
 553		return;
 554	_rtl92c_get_txpower_index(hw, channel,
 555				  &cckpowerlevel[0], &ofdmpowerlevel[0]);
 556	_rtl92c_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
 557				     &ofdmpowerlevel[0]);
 558	rtlpriv->cfg->ops->phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
 559	rtlpriv->cfg->ops->phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0],
 560						       channel);
 561}
 562EXPORT_SYMBOL(rtl92c_phy_set_txpower_level);
 563
 564bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
 565{
 566	struct rtl_priv *rtlpriv = rtl_priv(hw);
 567	struct rtl_phy *rtlphy = &(rtlpriv->phy);
 568	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 569	u8 idx;
 570	u8 rf_path;
 571	u8 ccktxpwridx = _rtl92c_phy_dbm_to_txpwr_idx(hw, WIRELESS_MODE_B,
 572						      power_indbm);
 573	u8 ofdmtxpwridx = _rtl92c_phy_dbm_to_txpwr_idx(hw, WIRELESS_MODE_N_24G,
 574						       power_indbm);
 575	if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
 576		ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
 577	else
 578		ofdmtxpwridx = 0;
 579	rtl_dbg(rtlpriv, COMP_TXAGC, DBG_TRACE,
 580		"%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
 581		power_indbm, ccktxpwridx, ofdmtxpwridx);
 582	for (idx = 0; idx < 14; idx++) {
 583		for (rf_path = 0; rf_path < 2; rf_path++) {
 584			rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
 585			rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] =
 586			    ofdmtxpwridx;
 587			rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] =
 588			    ofdmtxpwridx;
 589		}
 590	}
 591	rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
 592	return true;
 593}
 594EXPORT_SYMBOL(rtl92c_phy_update_txpower_dbm);
 595
 596u8 _rtl92c_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw,
 597				enum wireless_mode wirelessmode,
 598				long power_indbm)
 599{
 600	u8 txpwridx;
 601	long offset;
 602
 603	switch (wirelessmode) {
 604	case WIRELESS_MODE_B:
 605		offset = -7;
 606		break;
 607	case WIRELESS_MODE_G:
 608	case WIRELESS_MODE_N_24G:
 609		offset = -8;
 610		break;
 611	default:
 612		offset = -8;
 613		break;
 614	}
 615
 616	if ((power_indbm - offset) > 0)
 617		txpwridx = (u8)((power_indbm - offset) * 2);
 618	else
 619		txpwridx = 0;
 620
 621	if (txpwridx > MAX_TXPWR_IDX_NMODE_92S)
 622		txpwridx = MAX_TXPWR_IDX_NMODE_92S;
 623
 624	return txpwridx;
 625}
 626EXPORT_SYMBOL(_rtl92c_phy_dbm_to_txpwr_idx);
 627
 628long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
 629				  enum wireless_mode wirelessmode,
 630				  u8 txpwridx)
 631{
 632	long offset;
 633	long pwrout_dbm;
 634
 635	switch (wirelessmode) {
 636	case WIRELESS_MODE_B:
 637		offset = -7;
 638		break;
 639	case WIRELESS_MODE_G:
 640	case WIRELESS_MODE_N_24G:
 641		offset = -8;
 642		break;
 643	default:
 644		offset = -8;
 645		break;
 646	}
 647	pwrout_dbm = txpwridx / 2 + offset;
 648	return pwrout_dbm;
 649}
 650EXPORT_SYMBOL(_rtl92c_phy_txpwr_idx_to_dbm);
 651
 652void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
 653			    enum nl80211_channel_type ch_type)
 654{
 655	struct rtl_priv *rtlpriv = rtl_priv(hw);
 656	struct rtl_phy *rtlphy = &(rtlpriv->phy);
 657	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 658	u8 tmp_bw = rtlphy->current_chan_bw;
 659
 660	if (rtlphy->set_bwmode_inprogress)
 661		return;
 662	rtlphy->set_bwmode_inprogress = true;
 663	if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
 664		rtlpriv->cfg->ops->phy_set_bw_mode_callback(hw);
 665	} else {
 666		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
 667			"false driver sleep or unload\n");
 668		rtlphy->set_bwmode_inprogress = false;
 669		rtlphy->current_chan_bw = tmp_bw;
 670	}
 671}
 672EXPORT_SYMBOL(rtl92c_phy_set_bw_mode);
 673
 674void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw)
 675{
 676	struct rtl_priv *rtlpriv = rtl_priv(hw);
 677	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 678	struct rtl_phy *rtlphy = &(rtlpriv->phy);
 679	u32 delay;
 680
 681	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
 682		"switch to channel%d\n", rtlphy->current_channel);
 683	if (is_hal_stop(rtlhal))
 684		return;
 685	do {
 686		if (!rtlphy->sw_chnl_inprogress)
 687			break;
 688		if (!_rtl92c_phy_sw_chnl_step_by_step
 689		    (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
 690		     &rtlphy->sw_chnl_step, &delay)) {
 691			if (delay > 0)
 692				mdelay(delay);
 693			else
 694				continue;
 695		} else {
 696			rtlphy->sw_chnl_inprogress = false;
 697		}
 698		break;
 699	} while (true);
 700	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
 701}
 702EXPORT_SYMBOL(rtl92c_phy_sw_chnl_callback);
 703
 704u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw)
 705{
 706	struct rtl_priv *rtlpriv = rtl_priv(hw);
 707	struct rtl_phy *rtlphy = &(rtlpriv->phy);
 708	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 709
 710	if (rtlphy->sw_chnl_inprogress)
 711		return 0;
 712	if (rtlphy->set_bwmode_inprogress)
 713		return 0;
 714	WARN_ONCE((rtlphy->current_channel > 14),
 715		  "rtl8192c-common: WIRELESS_MODE_G but channel>14");
 716	rtlphy->sw_chnl_inprogress = true;
 717	rtlphy->sw_chnl_stage = 0;
 718	rtlphy->sw_chnl_step = 0;
 719	if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
 720		rtl92c_phy_sw_chnl_callback(hw);
 721		rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
 722			"sw_chnl_inprogress false schedule workitem\n");
 723		rtlphy->sw_chnl_inprogress = false;
 724	} else {
 725		rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
 726			"sw_chnl_inprogress false driver sleep or unload\n");
 727		rtlphy->sw_chnl_inprogress = false;
 728	}
 729	return 1;
 730}
 731EXPORT_SYMBOL(rtl92c_phy_sw_chnl);
 732
 733static void _rtl92c_phy_sw_rf_seting(struct ieee80211_hw *hw, u8 channel)
 734{
 735	struct rtl_priv *rtlpriv = rtl_priv(hw);
 736	struct rtl_phy *rtlphy = &(rtlpriv->phy);
 737	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 738
 739	if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) {
 740		if (channel == 6 &&
 741		    rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
 742			rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1,
 743				      MASKDWORD, 0x00255);
 744		} else {
 745			u32 backuprf0x1A =
 746			  (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1,
 747					     RFREG_OFFSET_MASK);
 748			rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD,
 749				      backuprf0x1A);
 750		}
 751	}
 752}
 753
 754static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
 755					     u32 cmdtableidx, u32 cmdtablesz,
 756					     enum swchnlcmd_id cmdid,
 757					     u32 para1, u32 para2, u32 msdelay)
 758{
 759	struct swchnlcmd *pcmd;
 760
 761	if (cmdtable == NULL) {
 762		WARN_ONCE(true, "rtl8192c-common: cmdtable cannot be NULL.\n");
 763		return false;
 764	}
 765
 766	if (cmdtableidx >= cmdtablesz)
 767		return false;
 768
 769	pcmd = cmdtable + cmdtableidx;
 770	pcmd->cmdid = cmdid;
 771	pcmd->para1 = para1;
 772	pcmd->para2 = para2;
 773	pcmd->msdelay = msdelay;
 774	return true;
 775}
 776
 777bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
 778				      u8 channel, u8 *stage, u8 *step,
 779				      u32 *delay)
 780{
 781	struct rtl_priv *rtlpriv = rtl_priv(hw);
 782	struct rtl_phy *rtlphy = &(rtlpriv->phy);
 783	struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
 784	u32 precommoncmdcnt;
 785	struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
 786	u32 postcommoncmdcnt;
 787	struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
 788	u32 rfdependcmdcnt;
 789	struct swchnlcmd *currentcmd = NULL;
 790	u8 rfpath;
 791	u8 num_total_rfpath = rtlphy->num_total_rfpath;
 792
 793	precommoncmdcnt = 0;
 794	_rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
 795					 MAX_PRECMD_CNT,
 796					 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
 797	_rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
 798					 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
 799
 800	postcommoncmdcnt = 0;
 801
 802	_rtl92c_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
 803					 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
 804
 805	rfdependcmdcnt = 0;
 806
 807	WARN_ONCE((channel < 1 || channel > 14),
 808		  "rtl8192c-common: illegal channel for Zebra: %d\n", channel);
 809
 810	_rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
 811					 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
 812					 RF_CHNLBW, channel, 10);
 813
 814	_rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
 815					 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
 816					 0);
 817
 818	do {
 819		switch (*stage) {
 820		case 0:
 821			currentcmd = &precommoncmd[*step];
 822			break;
 823		case 1:
 824			currentcmd = &rfdependcmd[*step];
 825			break;
 826		case 2:
 827			currentcmd = &postcommoncmd[*step];
 828			break;
 829		default:
 830			pr_err("Invalid 'stage' = %d, Check it!\n",
 831			       *stage);
 832			return true;
 833		}
 834
 835		if (currentcmd->cmdid == CMDID_END) {
 836			if ((*stage) == 2) {
 837				return true;
 838			} else {
 839				(*stage)++;
 840				(*step) = 0;
 841				continue;
 842			}
 843		}
 844
 845		switch (currentcmd->cmdid) {
 846		case CMDID_SET_TXPOWEROWER_LEVEL:
 847			rtl92c_phy_set_txpower_level(hw, channel);
 848			break;
 849		case CMDID_WRITEPORT_ULONG:
 850			rtl_write_dword(rtlpriv, currentcmd->para1,
 851					currentcmd->para2);
 852			break;
 853		case CMDID_WRITEPORT_USHORT:
 854			rtl_write_word(rtlpriv, currentcmd->para1,
 855				       (u16) currentcmd->para2);
 856			break;
 857		case CMDID_WRITEPORT_UCHAR:
 858			rtl_write_byte(rtlpriv, currentcmd->para1,
 859				       (u8)currentcmd->para2);
 860			break;
 861		case CMDID_RF_WRITEREG:
 862			for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
 863				rtlphy->rfreg_chnlval[rfpath] =
 864				    ((rtlphy->rfreg_chnlval[rfpath] &
 865				      0xfffffc00) | currentcmd->para2);
 866
 867				rtl_set_rfreg(hw, (enum radio_path)rfpath,
 868					      currentcmd->para1,
 869					      RFREG_OFFSET_MASK,
 870					      rtlphy->rfreg_chnlval[rfpath]);
 871			}
 872			_rtl92c_phy_sw_rf_seting(hw, channel);
 873			break;
 874		default:
 875			rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
 876				"switch case %#x not processed\n",
 877				currentcmd->cmdid);
 878			break;
 879		}
 880
 881		break;
 882	} while (true);
 883
 884	(*delay) = currentcmd->msdelay;
 885	(*step)++;
 886	return false;
 887}
 888
 889bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw, u32 rfpath)
 890{
 891	return true;
 892}
 893EXPORT_SYMBOL(rtl8192_phy_check_is_legal_rfpath);
 894
 895static u8 _rtl92c_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
 896{
 897	u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
 898	u8 result = 0x00;
 899
 900	rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
 901	rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
 902	rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
 903	rtl_set_bbreg(hw, 0xe3c, MASKDWORD,
 904		      config_pathb ? 0x28160202 : 0x28160502);
 905
 906	if (config_pathb) {
 907		rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
 908		rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
 909		rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
 910		rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202);
 911	}
 912
 913	rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1);
 914	rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
 915	rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
 916
 917	mdelay(IQK_DELAY_TIME);
 918
 919	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
 920	reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
 921	reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
 922	reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
 923
 924	if (!(reg_eac & BIT(28)) &&
 925	    (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
 926	    (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
 927		result |= 0x01;
 928	else
 929		return result;
 930
 931	if (!(reg_eac & BIT(27)) &&
 932	    (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
 933	    (((reg_eac & 0x03FF0000) >> 16) != 0x36))
 934		result |= 0x02;
 935	return result;
 936}
 937
 938static u8 _rtl92c_phy_path_b_iqk(struct ieee80211_hw *hw)
 939{
 940	u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
 941	u8 result = 0x00;
 942
 943	rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
 944	rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
 945	mdelay(IQK_DELAY_TIME);
 946	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
 947	reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
 948	reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
 949	reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
 950	reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
 951
 952	if (!(reg_eac & BIT(31)) &&
 953	    (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
 954	    (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
 955		result |= 0x01;
 956	else
 957		return result;
 958	if (!(reg_eac & BIT(30)) &&
 959	    (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
 960	    (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
 961		result |= 0x02;
 962	return result;
 963}
 964
 965static void _rtl92c_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
 966					       bool b_iqk_ok, long result[][8],
 967					       u8 final_candidate, bool btxonly)
 968{
 969	u32 oldval_0, x, tx0_a, reg;
 970	long y, tx0_c;
 971
 972	if (final_candidate == 0xFF) {
 973		return;
 974	} else if (b_iqk_ok) {
 975		oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
 976					  MASKDWORD) >> 22) & 0x3FF;
 977		x = result[final_candidate][0];
 978		if ((x & 0x00000200) != 0)
 979			x = x | 0xFFFFFC00;
 980		tx0_a = (x * oldval_0) >> 8;
 981		rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
 982		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
 983			      ((x * oldval_0 >> 7) & 0x1));
 984		y = result[final_candidate][1];
 985		if ((y & 0x00000200) != 0)
 986			y = y | 0xFFFFFC00;
 987		tx0_c = (y * oldval_0) >> 8;
 988		rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
 989			      ((tx0_c & 0x3C0) >> 6));
 990		rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
 991			      (tx0_c & 0x3F));
 992		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
 993			      ((y * oldval_0 >> 7) & 0x1));
 994		if (btxonly)
 995			return;
 996		reg = result[final_candidate][2];
 997		rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
 998		reg = result[final_candidate][3] & 0x3F;
 999		rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
1000		reg = (result[final_candidate][3] >> 6) & 0xF;
1001		rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
1002	}
1003}
1004
1005static void _rtl92c_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
1006					       bool b_iqk_ok, long result[][8],
1007					       u8 final_candidate, bool btxonly)
1008{
1009	u32 oldval_1, x, tx1_a, reg;
1010	long y, tx1_c;
1011
1012	if (final_candidate == 0xFF) {
1013		return;
1014	} else if (b_iqk_ok) {
1015		oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
1016					  MASKDWORD) >> 22) & 0x3FF;
1017		x = result[final_candidate][4];
1018		if ((x & 0x00000200) != 0)
1019			x = x | 0xFFFFFC00;
1020		tx1_a = (x * oldval_1) >> 8;
1021		rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
1022		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27),
1023			      ((x * oldval_1 >> 7) & 0x1));
1024		y = result[final_candidate][5];
1025		if ((y & 0x00000200) != 0)
1026			y = y | 0xFFFFFC00;
1027		tx1_c = (y * oldval_1) >> 8;
1028		rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
1029			      ((tx1_c & 0x3C0) >> 6));
1030		rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
1031			      (tx1_c & 0x3F));
1032		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25),
1033			      ((y * oldval_1 >> 7) & 0x1));
1034		if (btxonly)
1035			return;
1036		reg = result[final_candidate][6];
1037		rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
1038		reg = result[final_candidate][7] & 0x3F;
1039		rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
1040		reg = (result[final_candidate][7] >> 6) & 0xF;
1041		rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
1042	}
1043}
1044
1045static void _rtl92c_phy_save_adda_registers(struct ieee80211_hw *hw,
1046					    u32 *addareg, u32 *addabackup,
1047					    u32 registernum)
1048{
1049	u32 i;
1050
1051	for (i = 0; i < registernum; i++)
1052		addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1053}
1054
1055static void _rtl92c_phy_save_mac_registers(struct ieee80211_hw *hw,
1056					   u32 *macreg, u32 *macbackup)
1057{
1058	struct rtl_priv *rtlpriv = rtl_priv(hw);
1059	u32 i;
1060
1061	for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1062		macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1063	macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1064}
1065
1066static void _rtl92c_phy_reload_adda_registers(struct ieee80211_hw *hw,
1067					      u32 *addareg, u32 *addabackup,
1068					      u32 regiesternum)
1069{
1070	u32 i;
1071
1072	for (i = 0; i < regiesternum; i++)
1073		rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
1074}
1075
1076static void _rtl92c_phy_reload_mac_registers(struct ieee80211_hw *hw,
1077					     u32 *macreg, u32 *macbackup)
1078{
1079	struct rtl_priv *rtlpriv = rtl_priv(hw);
1080	u32 i;
1081
1082	for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1083		rtl_write_byte(rtlpriv, macreg[i], (u8)macbackup[i]);
1084	rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1085}
1086
1087static void _rtl92c_phy_path_adda_on(struct ieee80211_hw *hw,
1088				     u32 *addareg, bool is_patha_on, bool is2t)
1089{
1090	u32 pathon;
1091	u32 i;
1092
1093	pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1094	if (!is2t) {
1095		pathon = 0x0bdb25a0;
1096		rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1097	} else {
1098		rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
1099	}
1100
1101	for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1102		rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon);
1103}
1104
1105static void _rtl92c_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1106						u32 *macreg, u32 *macbackup)
1107{
1108	struct rtl_priv *rtlpriv = rtl_priv(hw);
1109	u32 i = 0;
1110
1111	rtl_write_byte(rtlpriv, macreg[i], 0x3F);
1112
1113	for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1114		rtl_write_byte(rtlpriv, macreg[i],
1115			       (u8)(macbackup[i] & (~BIT(3))));
1116	rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] & (~BIT(5))));
1117}
1118
1119static void _rtl92c_phy_path_a_standby(struct ieee80211_hw *hw)
1120{
1121	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1122	rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1123	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1124}
1125
1126static void _rtl92c_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1127{
1128	u32 mode;
1129
1130	mode = pi_mode ? 0x01000100 : 0x01000000;
1131	rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1132	rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1133}
1134
1135static bool _rtl92c_phy_simularity_compare(struct ieee80211_hw *hw,
1136					   long result[][8], u8 c1, u8 c2)
1137{
1138	u32 i, j, diff, simularity_bitmap, bound;
1139	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1140
1141	u8 final_candidate[2] = { 0xFF, 0xFF };
1142	bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version);
1143
1144	if (is2t)
1145		bound = 8;
1146	else
1147		bound = 4;
1148
1149	simularity_bitmap = 0;
1150
1151	for (i = 0; i < bound; i++) {
1152		diff = (result[c1][i] > result[c2][i]) ?
1153		    (result[c1][i] - result[c2][i]) :
1154		    (result[c2][i] - result[c1][i]);
1155
1156		if (diff > MAX_TOLERANCE) {
1157			if ((i == 2 || i == 6) && !simularity_bitmap) {
1158				if (result[c1][i] + result[c1][i + 1] == 0)
1159					final_candidate[(i / 4)] = c2;
1160				else if (result[c2][i] + result[c2][i + 1] == 0)
1161					final_candidate[(i / 4)] = c1;
1162				else
1163					simularity_bitmap = simularity_bitmap |
1164					    (1 << i);
1165			} else
1166				simularity_bitmap =
1167				    simularity_bitmap | (1 << i);
1168		}
1169	}
1170
1171	if (simularity_bitmap == 0) {
1172		for (i = 0; i < (bound / 4); i++) {
1173			if (final_candidate[i] != 0xFF) {
1174				for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1175					result[3][j] =
1176					    result[final_candidate[i]][j];
1177				bresult = false;
1178			}
1179		}
1180		return bresult;
1181	} else if (!(simularity_bitmap & 0x0F)) {
1182		for (i = 0; i < 4; i++)
1183			result[3][i] = result[c1][i];
1184		return false;
1185	} else if (!(simularity_bitmap & 0xF0) && is2t) {
1186		for (i = 4; i < 8; i++)
1187			result[3][i] = result[c1][i];
1188		return false;
1189	} else {
1190		return false;
1191	}
1192}
1193
1194static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw,
1195				     long result[][8], u8 t, bool is2t)
1196{
1197	struct rtl_priv *rtlpriv = rtl_priv(hw);
1198	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1199	u32 i;
1200	u8 patha_ok, pathb_ok;
1201	u32 adda_reg[IQK_ADDA_REG_NUM] = {
1202		0x85c, 0xe6c, 0xe70, 0xe74,
1203		0xe78, 0xe7c, 0xe80, 0xe84,
1204		0xe88, 0xe8c, 0xed0, 0xed4,
1205		0xed8, 0xedc, 0xee0, 0xeec
1206	};
1207	u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1208		0x522, 0x550, 0x551, 0x040
1209	};
1210	const u32 retrycount = 2;
1211
1212	if (t == 0) {
1213		rtl_get_bbreg(hw, 0x800, MASKDWORD);
1214
1215		_rtl92c_phy_save_adda_registers(hw, adda_reg,
1216						rtlphy->adda_backup, 16);
1217		_rtl92c_phy_save_mac_registers(hw, iqk_mac_reg,
1218					       rtlphy->iqk_mac_backup);
1219	}
1220	_rtl92c_phy_path_adda_on(hw, adda_reg, true, is2t);
1221	if (t == 0) {
1222		rtlphy->rfpi_enable =
1223		   (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
1224				     BIT(8));
1225	}
1226
1227	if (!rtlphy->rfpi_enable)
1228		_rtl92c_phy_pi_mode_switch(hw, true);
1229	if (t == 0) {
1230		rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
1231		rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
1232		rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD);
1233	}
1234	rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1235	rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1236	rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1237	if (is2t) {
1238		rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1239		rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1240	}
1241	_rtl92c_phy_mac_setting_calibration(hw, iqk_mac_reg,
1242					    rtlphy->iqk_mac_backup);
1243	rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000);
1244	if (is2t)
1245		rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000);
1246	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1247	rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1248	rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1249	for (i = 0; i < retrycount; i++) {
1250		patha_ok = _rtl92c_phy_path_a_iqk(hw, is2t);
1251		if (patha_ok == 0x03) {
1252			result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1253					0x3FF0000) >> 16;
1254			result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1255					0x3FF0000) >> 16;
1256			result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1257					0x3FF0000) >> 16;
1258			result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1259					0x3FF0000) >> 16;
1260			break;
1261		} else if (i == (retrycount - 1) && patha_ok == 0x01)
1262
1263			result[t][0] = (rtl_get_bbreg(hw, 0xe94,
1264						      MASKDWORD) & 0x3FF0000) >>
1265			    16;
1266		result[t][1] =
1267		    (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
1268
1269	}
1270
1271	if (is2t) {
1272		_rtl92c_phy_path_a_standby(hw);
1273		_rtl92c_phy_path_adda_on(hw, adda_reg, false, is2t);
1274		for (i = 0; i < retrycount; i++) {
1275			pathb_ok = _rtl92c_phy_path_b_iqk(hw);
1276			if (pathb_ok == 0x03) {
1277				result[t][4] = (rtl_get_bbreg(hw,
1278							      0xeb4,
1279							      MASKDWORD) &
1280						0x3FF0000) >> 16;
1281				result[t][5] =
1282				    (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1283				     0x3FF0000) >> 16;
1284				result[t][6] =
1285				    (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1286				     0x3FF0000) >> 16;
1287				result[t][7] =
1288				    (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1289				     0x3FF0000) >> 16;
1290				break;
1291			} else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1292				result[t][4] = (rtl_get_bbreg(hw,
1293							      0xeb4,
1294							      MASKDWORD) &
1295						0x3FF0000) >> 16;
1296			}
1297			result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1298					0x3FF0000) >> 16;
1299		}
1300	}
1301	rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04);
1302	rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874);
1303	rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08);
1304	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1305	rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1306	if (is2t)
1307		rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1308	if (t != 0) {
1309		if (!rtlphy->rfpi_enable)
1310			_rtl92c_phy_pi_mode_switch(hw, false);
1311		_rtl92c_phy_reload_adda_registers(hw, adda_reg,
1312						  rtlphy->adda_backup, 16);
1313		_rtl92c_phy_reload_mac_registers(hw, iqk_mac_reg,
1314						 rtlphy->iqk_mac_backup);
1315	}
1316}
1317
1318static void _rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw,
1319				     s8 delta, bool is2t)
1320{
1321}
1322
1323static void _rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1324					  bool bmain, bool is2t)
1325{
1326	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1327
1328	if (is_hal_stop(rtlhal)) {
1329		rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
1330		rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1331	}
1332	if (is2t) {
1333		if (bmain)
1334			rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1335				      BIT(5) | BIT(6), 0x1);
1336		else
1337			rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1338				      BIT(5) | BIT(6), 0x2);
1339	} else {
1340		if (bmain)
1341			rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2);
1342		else
1343			rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
1344	}
1345}
1346
1347#undef IQK_ADDA_REG_NUM
1348#undef IQK_DELAY_TIME
1349
1350void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
1351{
1352	struct rtl_priv *rtlpriv = rtl_priv(hw);
1353	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1354	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1355
1356	long result[4][8];
1357	u8 i, final_candidate;
1358	bool b_patha_ok, b_pathb_ok;
1359	long reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc, reg_ec4,
1360	    reg_tmp = 0;
1361	bool is12simular, is13simular, is23simular;
1362	u32 iqk_bb_reg[10] = {
1363		ROFDM0_XARXIQIMBALANCE,
1364		ROFDM0_XBRXIQIMBALANCE,
1365		ROFDM0_ECCATHRESHOLD,
1366		ROFDM0_AGCRSSITABLE,
1367		ROFDM0_XATXIQIMBALANCE,
1368		ROFDM0_XBTXIQIMBALANCE,
1369		ROFDM0_XCTXIQIMBALANCE,
1370		ROFDM0_XCTXAFE,
1371		ROFDM0_XDTXAFE,
1372		ROFDM0_RXIQEXTANTA
1373	};
1374
1375	if (b_recovery) {
1376		_rtl92c_phy_reload_adda_registers(hw,
1377						  iqk_bb_reg,
1378						  rtlphy->iqk_bb_backup, 10);
1379		return;
1380	}
1381	for (i = 0; i < 8; i++) {
1382		result[0][i] = 0;
1383		result[1][i] = 0;
1384		result[2][i] = 0;
1385		result[3][i] = 0;
1386	}
1387	final_candidate = 0xff;
1388	b_patha_ok = false;
1389	b_pathb_ok = false;
1390	is12simular = false;
1391	is23simular = false;
1392	is13simular = false;
1393	for (i = 0; i < 3; i++) {
1394		if (IS_92C_SERIAL(rtlhal->version))
1395			_rtl92c_phy_iq_calibrate(hw, result, i, true);
1396		else
1397			_rtl92c_phy_iq_calibrate(hw, result, i, false);
1398		if (i == 1) {
1399			is12simular = _rtl92c_phy_simularity_compare(hw,
1400								     result, 0,
1401								     1);
1402			if (is12simular) {
1403				final_candidate = 0;
1404				break;
1405			}
1406		}
1407		if (i == 2) {
1408			is13simular = _rtl92c_phy_simularity_compare(hw,
1409								     result, 0,
1410								     2);
1411			if (is13simular) {
1412				final_candidate = 0;
1413				break;
1414			}
1415			is23simular = _rtl92c_phy_simularity_compare(hw,
1416								     result, 1,
1417								     2);
1418			if (is23simular)
1419				final_candidate = 1;
1420			else {
1421				for (i = 0; i < 8; i++)
1422					reg_tmp += result[3][i];
1423
1424				if (reg_tmp != 0)
1425					final_candidate = 3;
1426				else
1427					final_candidate = 0xFF;
1428			}
1429		}
1430	}
1431	for (i = 0; i < 4; i++) {
1432		reg_e94 = result[i][0];
1433		reg_e9c = result[i][1];
1434		reg_ea4 = result[i][2];
1435		reg_eb4 = result[i][4];
1436		reg_ebc = result[i][5];
1437		reg_ec4 = result[i][6];
1438	}
1439	if (final_candidate != 0xff) {
1440		rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
1441		rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
1442		reg_ea4 = result[final_candidate][2];
1443		rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
1444		rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
1445		reg_ec4 = result[final_candidate][6];
1446		b_patha_ok = true;
1447		b_pathb_ok = true;
1448	} else {
1449		rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
1450		rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
1451	}
1452	if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
1453		_rtl92c_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
1454						   final_candidate,
1455						   (reg_ea4 == 0));
1456	if (IS_92C_SERIAL(rtlhal->version)) {
1457		if (reg_eb4 != 0) /*&&(reg_ec4 != 0) */
1458			_rtl92c_phy_path_b_fill_iqk_matrix(hw, b_pathb_ok,
1459							   result,
1460							   final_candidate,
1461							   (reg_ec4 == 0));
1462	}
1463	_rtl92c_phy_save_adda_registers(hw, iqk_bb_reg,
1464					rtlphy->iqk_bb_backup, 10);
1465}
1466EXPORT_SYMBOL(rtl92c_phy_iq_calibrate);
1467
1468void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw)
1469{
1470	struct rtl_priv *rtlpriv = rtl_priv(hw);
1471	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1472
1473	if (IS_92C_SERIAL(rtlhal->version))
1474		rtlpriv->cfg->ops->phy_lc_calibrate(hw, true);
1475	else
1476		rtlpriv->cfg->ops->phy_lc_calibrate(hw, false);
1477}
1478EXPORT_SYMBOL(rtl92c_phy_lc_calibrate);
1479
1480void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta)
1481{
1482	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1483
1484	if (IS_92C_SERIAL(rtlhal->version))
1485		_rtl92c_phy_ap_calibrate(hw, delta, true);
1486	else
1487		_rtl92c_phy_ap_calibrate(hw, delta, false);
1488}
1489EXPORT_SYMBOL(rtl92c_phy_ap_calibrate);
1490
1491void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
1492{
1493	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1494
1495	if (IS_92C_SERIAL(rtlhal->version))
1496		_rtl92c_phy_set_rfpath_switch(hw, bmain, true);
1497	else
1498		_rtl92c_phy_set_rfpath_switch(hw, bmain, false);
1499}
1500EXPORT_SYMBOL(rtl92c_phy_set_rfpath_switch);
1501
1502bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1503{
1504	struct rtl_priv *rtlpriv = rtl_priv(hw);
1505	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1506	bool postprocessing = false;
1507
1508	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1509		"-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1510		iotype, rtlphy->set_io_inprogress);
1511	do {
1512		switch (iotype) {
1513		case IO_CMD_RESUME_DM_BY_SCAN:
1514			rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1515				"[IO CMD] Resume DM after scan.\n");
1516			postprocessing = true;
1517			break;
1518		case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1519			rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1520				"[IO CMD] Pause DM before scan.\n");
1521			postprocessing = true;
1522			break;
1523		default:
1524			rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1525				"switch case %#x not processed\n", iotype);
1526			break;
1527		}
1528	} while (false);
1529	if (postprocessing && !rtlphy->set_io_inprogress) {
1530		rtlphy->set_io_inprogress = true;
1531		rtlphy->current_io_type = iotype;
1532	} else {
1533		return false;
1534	}
1535	rtl92c_phy_set_io(hw);
1536	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
1537	return true;
1538}
1539EXPORT_SYMBOL(rtl92c_phy_set_io_cmd);
1540
1541void rtl92c_phy_set_io(struct ieee80211_hw *hw)
1542{
1543	struct rtl_priv *rtlpriv = rtl_priv(hw);
1544	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1545	struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
1546
1547	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1548		"--->Cmd(%#x), set_io_inprogress(%d)\n",
1549		rtlphy->current_io_type, rtlphy->set_io_inprogress);
1550	switch (rtlphy->current_io_type) {
1551	case IO_CMD_RESUME_DM_BY_SCAN:
1552		dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
1553		rtl92c_dm_write_dig(hw);
1554		rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1555		break;
1556	case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1557		rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
1558		dm_digtable->cur_igvalue = 0x17;
1559		rtl92c_dm_write_dig(hw);
1560		break;
1561	default:
1562		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1563			"switch case %#x not processed\n",
1564			rtlphy->current_io_type);
1565		break;
1566	}
1567	rtlphy->set_io_inprogress = false;
1568	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1569		"(%#x)\n", rtlphy->current_io_type);
1570}
1571EXPORT_SYMBOL(rtl92c_phy_set_io);
1572
1573void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw)
1574{
1575	struct rtl_priv *rtlpriv = rtl_priv(hw);
1576
1577	rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
1578	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1579	rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1580	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1581	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1582	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1583}
1584EXPORT_SYMBOL(rtl92ce_phy_set_rf_on);
1585
1586void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw)
1587{
1588	u32 u4b_tmp;
1589	u8 delay = 5;
1590	struct rtl_priv *rtlpriv = rtl_priv(hw);
1591
1592	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1593	rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1594	rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1595	u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1596	while (u4b_tmp != 0 && delay > 0) {
1597		rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
1598		rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1599		rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1600		u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1601		delay--;
1602	}
1603	if (delay == 0) {
1604		rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1605		rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1606		rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1607		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1608		rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
1609			"Switch RF timeout !!!.\n");
1610		return;
1611	}
1612	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1613	rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
1614}
1615EXPORT_SYMBOL(_rtl92c_phy_set_rf_sleep);
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