rtl8xxxu.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
   4 *
   5 * Register definitions taken from original Realtek rtl8723au driver
   6 */
   7
   8#include <linux/average.h>
   9#include <linux/usb.h>
  10#include <net/mac80211.h>
  11
  12#define RTL8XXXU_DEBUG_REG_WRITE	0x01
  13#define RTL8XXXU_DEBUG_REG_READ		0x02
  14#define RTL8XXXU_DEBUG_RFREG_WRITE	0x04
  15#define RTL8XXXU_DEBUG_RFREG_READ	0x08
  16#define RTL8XXXU_DEBUG_CHANNEL		0x10
  17#define RTL8XXXU_DEBUG_TX		0x20
  18#define RTL8XXXU_DEBUG_TX_DUMP		0x40
  19#define RTL8XXXU_DEBUG_RX		0x80
  20#define RTL8XXXU_DEBUG_RX_DUMP		0x100
  21#define RTL8XXXU_DEBUG_USB		0x200
  22#define RTL8XXXU_DEBUG_KEY		0x400
  23#define RTL8XXXU_DEBUG_H2C		0x800
  24#define RTL8XXXU_DEBUG_ACTION		0x1000
  25#define RTL8XXXU_DEBUG_EFUSE		0x2000
  26#define RTL8XXXU_DEBUG_INTERRUPT	0x4000
  27
  28#define RTW_USB_CONTROL_MSG_TIMEOUT	500
  29#define RTL8XXXU_MAX_REG_POLL		500
  30#define	USB_INTR_CONTENT_LENGTH		56
  31
  32#define RTL8XXXU_OUT_ENDPOINTS		6
  33
  34#define REALTEK_USB_READ		0xc0
  35#define REALTEK_USB_WRITE		0x40
  36#define REALTEK_USB_CMD_REQ		0x05
  37#define REALTEK_USB_CMD_IDX		0x00
  38
  39#define TX_TOTAL_PAGE_NUM		0xf8
  40#define TX_TOTAL_PAGE_NUM_8188F		0xf7
  41#define TX_TOTAL_PAGE_NUM_8188E		0xa9
  42#define TX_TOTAL_PAGE_NUM_8192E		0xf3
  43#define TX_TOTAL_PAGE_NUM_8723B		0xf7
  44#define TX_TOTAL_PAGE_NUM_8192F		0xf7
  45/* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */
  46#define TX_PAGE_NUM_PUBQ		0xe7
  47#define TX_PAGE_NUM_HI_PQ		0x0c
  48#define TX_PAGE_NUM_LO_PQ		0x02
  49#define TX_PAGE_NUM_NORM_PQ		0x02
  50
  51#define TX_PAGE_NUM_PUBQ_8188F		0xe5
  52#define TX_PAGE_NUM_HI_PQ_8188F		0x0c
  53#define TX_PAGE_NUM_LO_PQ_8188F		0x02
  54#define TX_PAGE_NUM_NORM_PQ_8188F	0x02
  55
  56#define TX_PAGE_NUM_PUBQ_8188E		0x47
  57#define TX_PAGE_NUM_HI_PQ_8188E		0x29
  58#define TX_PAGE_NUM_LO_PQ_8188E		0x1c
  59#define TX_PAGE_NUM_NORM_PQ_8188E	0x1c
  60
  61#define TX_PAGE_NUM_PUBQ_8192E		0xe7
  62#define TX_PAGE_NUM_HI_PQ_8192E		0x08
  63#define TX_PAGE_NUM_LO_PQ_8192E		0x0c
  64#define TX_PAGE_NUM_NORM_PQ_8192E	0x00
  65
  66#define TX_PAGE_NUM_PUBQ_8723B		0xe7
  67#define TX_PAGE_NUM_HI_PQ_8723B		0x0c
  68#define TX_PAGE_NUM_LO_PQ_8723B		0x02
  69#define TX_PAGE_NUM_NORM_PQ_8723B	0x02
  70
  71#define TX_PAGE_NUM_PUBQ_8192F		0xde
  72#define TX_PAGE_NUM_HI_PQ_8192F		0x08
  73#define TX_PAGE_NUM_LO_PQ_8192F		0x08
  74#define TX_PAGE_NUM_NORM_PQ_8192F	0x08
  75
  76#define RTL_FW_PAGE_SIZE		4096
  77#define RTL8XXXU_FIRMWARE_POLL_MAX	1000
  78
  79#define RTL8723A_CHANNEL_GROUPS		3
  80#define RTL8723A_MAX_RF_PATHS		2
  81#define RTL8723B_CHANNEL_GROUPS		6
  82#define RTL8723B_TX_COUNT		4
  83#define RTL8723B_MAX_RF_PATHS		4
  84#define RTL8XXXU_MAX_CHANNEL_GROUPS	6
  85#define RF6052_MAX_TX_PWR		0x3f
  86
  87#define EFUSE_MAP_LEN			512
  88#define EFUSE_MAX_SECTION_8723A		64
  89#define EFUSE_REAL_CONTENT_LEN_8723A	512
  90#define EFUSE_BT_MAP_LEN_8723A		1024
  91#define EFUSE_MAX_WORD_UNIT		4
  92#define EFUSE_UNDEFINED			0xff
  93
  94enum rtl8xxxu_rtl_chip {
  95	RTL8192S = 0x81920,
  96	RTL8191S = 0x81910,
  97	RTL8192C = 0x8192c,
  98	RTL8191C = 0x8191c,
  99	RTL8188C = 0x8188c,
 100	RTL8188R = 0x81889,
 101	RTL8192D = 0x8192d,
 102	RTL8723A = 0x8723a,
 103	RTL8188E = 0x8188e,
 104	RTL8812  = 0x88120,
 105	RTL8821  = 0x88210,
 106	RTL8192E = 0x8192e,
 107	RTL8191E = 0x8191e,
 108	RTL8723B = 0x8723b,
 109	RTL8814A = 0x8814a,
 110	RTL8881A = 0x8881a,
 111	RTL8821B = 0x8821b,
 112	RTL8822B = 0x8822b,
 113	RTL8703B = 0x8703b,
 114	RTL8195A = 0x8195a,
 115	RTL8188F = 0x8188f,
 116	RTL8710B = 0x8710b,
 117	RTL8192F = 0x8192f,
 118};
 119
 120enum rtl8xxxu_rx_type {
 121	RX_TYPE_DATA_PKT = 0,
 122	RX_TYPE_C2H = 1,
 123	RX_TYPE_ERROR = -1
 124};
 125
 126enum rtl8xxxu_rx_desc_enc {
 127	RX_DESC_ENC_NONE	= 0,
 128	RX_DESC_ENC_WEP40	= 1,
 129	RX_DESC_ENC_TKIP_WO_MIC	= 2,
 130	RX_DESC_ENC_TKIP_MIC	= 3,
 131	RX_DESC_ENC_AES		= 4,
 132	RX_DESC_ENC_WEP104	= 5,
 133};
 134
 135struct rtl8xxxu_rxdesc16 {
 136#ifdef __LITTLE_ENDIAN
 137	u32 pktlen:14;
 138	u32 crc32:1;
 139	u32 icverr:1;
 140	u32 drvinfo_sz:4;
 141	u32 security:3;
 142	u32 qos:1;
 143	u32 shift:2;
 144	u32 phy_stats:1;
 145	u32 swdec:1;
 146	u32 ls:1;
 147	u32 fs:1;
 148	u32 eor:1;
 149	u32 own:1;
 150
 151	u32 macid:5;
 152	u32 tid:4;
 153	u32 hwrsvd:4;
 154	u32 amsdu:1;
 155	u32 paggr:1;
 156	u32 faggr:1;
 157	u32 a1fit:4;
 158	u32 a2fit:4;
 159	u32 pam:1;
 160	u32 pwr:1;
 161	u32 md:1;
 162	u32 mf:1;
 163	u32 type:2;
 164	u32 mc:1;
 165	u32 bc:1;
 166
 167	u32 seq:12;
 168	u32 frag:4;
 169	u32 pkt_cnt:8;
 170	u32 reserved:6;
 171	u32 nextind:1;
 172	u32 reserved0:1;
 173
 174	u32 rxmcs:6;
 175	u32 rxht:1;
 176	u32 gf:1;
 177	u32 splcp:1;
 178	u32 bw:1;
 179	u32 htc:1;
 180	u32 eosp:1;
 181	u32 bssidfit:2;
 182	u32 rpt_sel:2;		/* 8188e */
 183	u32 reserved1:14;
 184	u32 unicastwake:1;
 185	u32 magicwake:1;
 186
 187	u32 pattern0match:1;
 188	u32 pattern1match:1;
 189	u32 pattern2match:1;
 190	u32 pattern3match:1;
 191	u32 pattern4match:1;
 192	u32 pattern5match:1;
 193	u32 pattern6match:1;
 194	u32 pattern7match:1;
 195	u32 pattern8match:1;
 196	u32 pattern9match:1;
 197	u32 patternamatch:1;
 198	u32 patternbmatch:1;
 199	u32 patterncmatch:1;
 200	u32 reserved2:19;
 201#else
 202	u32 own:1;
 203	u32 eor:1;
 204	u32 fs:1;
 205	u32 ls:1;
 206	u32 swdec:1;
 207	u32 phy_stats:1;
 208	u32 shift:2;
 209	u32 qos:1;
 210	u32 security:3;
 211	u32 drvinfo_sz:4;
 212	u32 icverr:1;
 213	u32 crc32:1;
 214	u32 pktlen:14;
 215
 216	u32 bc:1;
 217	u32 mc:1;
 218	u32 type:2;
 219	u32 mf:1;
 220	u32 md:1;
 221	u32 pwr:1;
 222	u32 pam:1;
 223	u32 a2fit:4;
 224	u32 a1fit:4;
 225	u32 faggr:1;
 226	u32 paggr:1;
 227	u32 amsdu:1;
 228	u32 hwrsvd:4;
 229	u32 tid:4;
 230	u32 macid:5;
 231
 232	u32 reserved0:1;
 233	u32 nextind:1;
 234	u32 reserved:6;
 235	u32 pkt_cnt:8;
 236	u32 frag:4;
 237	u32 seq:12;
 238
 239	u32 magicwake:1;
 240	u32 unicastwake:1;
 241	u32 reserved1:14;
 242	u32 rpt_sel:2;		/* 8188e */
 243	u32 bssidfit:2;
 244	u32 eosp:1;
 245	u32 htc:1;
 246	u32 bw:1;
 247	u32 splcp:1;
 248	u32 gf:1;
 249	u32 rxht:1;
 250	u32 rxmcs:6;
 251
 252	u32 reserved2:19;
 253	u32 patterncmatch:1;
 254	u32 patternbmatch:1;
 255	u32 patternamatch:1;
 256	u32 pattern9match:1;
 257	u32 pattern8match:1;
 258	u32 pattern7match:1;
 259	u32 pattern6match:1;
 260	u32 pattern5match:1;
 261	u32 pattern4match:1;
 262	u32 pattern3match:1;
 263	u32 pattern2match:1;
 264	u32 pattern1match:1;
 265	u32 pattern0match:1;
 266#endif
 267	u32 tsfl;
 268#if 0
 269	u32 bassn:12;
 270	u32 bavld:1;
 271	u32 reserved3:19;
 272#endif
 273};
 274
 275struct rtl8xxxu_rxdesc24 {
 276#ifdef __LITTLE_ENDIAN
 277	u32 pktlen:14;
 278	u32 crc32:1;
 279	u32 icverr:1;
 280	u32 drvinfo_sz:4;
 281	u32 security:3;
 282	u32 qos:1;
 283	u32 shift:2;
 284	u32 phy_stats:1;
 285	u32 swdec:1;
 286	u32 ls:1;
 287	u32 fs:1;
 288	u32 eor:1;
 289	u32 own:1;
 290
 291	u32 macid:7;
 292	u32 dummy1_0:1;
 293	u32 tid:4;
 294	u32 dummy1_1:1;
 295	u32 amsdu:1;
 296	u32 rxid_match:1;
 297	u32 paggr:1;
 298	u32 a1fit:4;	/* 16 */
 299	u32 chkerr:1;
 300	u32 ipver:1;
 301	u32 tcpudp:1;
 302	u32 chkvld:1;
 303	u32 pam:1;
 304	u32 pwr:1;
 305	u32 more_data:1;
 306	u32 more_frag:1;
 307	u32 type:2;
 308	u32 mc:1;
 309	u32 bc:1;
 310
 311	u32 seq:12;
 312	u32 frag:4;
 313	u32 rx_is_qos:1;	/* 16 */
 314	u32 dummy2_0:1;
 315	u32 wlanhd_iv_len:6;
 316	u32 dummy2_1:4;
 317	u32 rpt_sel:1;
 318	u32 dummy2_2:3;
 319
 320	u32 rxmcs:7;
 321	u32 dummy3_0:3;
 322	u32 htc:1;
 323	u32 eosp:1;
 324	u32 bssidfit:2;
 325	u32 dummy3_1:2;
 326	u32 usb_agg_pktnum:8;	/* 16 */
 327	u32 dummy3_2:5;
 328	u32 pattern_match:1;
 329	u32 unicast_match:1;
 330	u32 magic_match:1;
 331
 332	u32 splcp:1;
 333	u32 ldcp:1;
 334	u32 stbc:1;
 335	u32 dummy4_0:1;
 336	u32 bw:2;
 337	u32 dummy4_1:26;
 338#else
 339	u32 own:1;
 340	u32 eor:1;
 341	u32 fs:1;
 342	u32 ls:1;
 343	u32 swdec:1;
 344	u32 phy_stats:1;
 345	u32 shift:2;
 346	u32 qos:1;
 347	u32 security:3;
 348	u32 drvinfo_sz:4;
 349	u32 icverr:1;
 350	u32 crc32:1;
 351	u32 pktlen:14;
 352
 353	u32 bc:1;
 354	u32 mc:1;
 355	u32 type:2;
 356	u32 mf:1;
 357	u32 md:1;
 358	u32 pwr:1;
 359	u32 pam:1;
 360	u32 a2fit:4;
 361	u32 a1fit:4;
 362	u32 faggr:1;
 363	u32 paggr:1;
 364	u32 amsdu:1;
 365	u32 hwrsvd:4;
 366	u32 tid:4;
 367	u32 macid:5;
 368
 369	u32 dummy2_2:3;
 370	u32 rpt_sel:1;
 371	u32 dummy2_1:4;
 372	u32 wlanhd_iv_len:6;
 373	u32 dummy2_0:1;
 374	u32 rx_is_qos:1;
 375	u32 frag:4;		/* 16 */
 376	u32 seq:12;
 377
 378	u32 magic_match:1;
 379	u32 unicast_match:1;
 380	u32 pattern_match:1;
 381	u32 dummy3_2:5;
 382	u32 usb_agg_pktnum:8;
 383	u32 dummy3_1:2;		/* 16 */
 384	u32 bssidfit:2;
 385	u32 eosp:1;
 386	u32 htc:1;
 387	u32 dummy3_0:3;
 388	u32 rxmcs:7;
 389
 390	u32 dumm4_1:26;
 391	u32 bw:2;
 392	u32 dummy4_0:1;
 393	u32 stbc:1;
 394	u32 ldcp:1;
 395	u32 splcp:1;
 396#endif
 397	u32 tsfl;
 398};
 399
 400struct rtl8xxxu_txdesc32 {
 401	__le16 pkt_size;
 402	u8 pkt_offset;
 403	u8 txdw0;
 404	__le32 txdw1;
 405	__le32 txdw2;
 406	__le32 txdw3;
 407	__le32 txdw4;
 408	__le32 txdw5;
 409	__le32 txdw6;
 410	__le16 csum;
 411	__le16 txdw7;
 412};
 413
 414struct rtl8xxxu_txdesc40 {
 415	__le16 pkt_size;
 416	u8 pkt_offset;
 417	u8 txdw0;
 418	__le32 txdw1;
 419	__le32 txdw2;
 420	__le32 txdw3;
 421	__le32 txdw4;
 422	__le32 txdw5;
 423	__le32 txdw6;
 424	__le16 csum;
 425	__le16 txdw7;
 426	__le32 txdw8;
 427	__le32 txdw9;
 428};
 429
 430/*  CCK Rates, TxHT = 0 */
 431#define DESC_RATE_1M			0x00
 432#define DESC_RATE_2M			0x01
 433#define DESC_RATE_5_5M			0x02
 434#define DESC_RATE_11M			0x03
 435
 436/*  OFDM Rates, TxHT = 0 */
 437#define DESC_RATE_6M			0x04
 438#define DESC_RATE_9M			0x05
 439#define DESC_RATE_12M			0x06
 440#define DESC_RATE_18M			0x07
 441#define DESC_RATE_24M			0x08
 442#define DESC_RATE_36M			0x09
 443#define DESC_RATE_48M			0x0a
 444#define DESC_RATE_54M			0x0b
 445
 446/*  MCS Rates, TxHT = 1 */
 447#define DESC_RATE_MCS0			0x0c
 448#define DESC_RATE_MCS1			0x0d
 449#define DESC_RATE_MCS2			0x0e
 450#define DESC_RATE_MCS3			0x0f
 451#define DESC_RATE_MCS4			0x10
 452#define DESC_RATE_MCS5			0x11
 453#define DESC_RATE_MCS6			0x12
 454#define DESC_RATE_MCS7			0x13
 455#define DESC_RATE_MCS8			0x14
 456#define DESC_RATE_MCS9			0x15
 457#define DESC_RATE_MCS10			0x16
 458#define DESC_RATE_MCS11			0x17
 459#define DESC_RATE_MCS12			0x18
 460#define DESC_RATE_MCS13			0x19
 461#define DESC_RATE_MCS14			0x1a
 462#define DESC_RATE_MCS15			0x1b
 463#define DESC_RATE_MCS15_SG		0x1c
 464#define DESC_RATE_MCS32			0x20
 465
 466#define TXDESC_OFFSET_SZ		0
 467#define TXDESC_OFFSET_SHT		16
 468#if 0
 469#define TXDESC_BMC			BIT(24)
 470#define TXDESC_LSG			BIT(26)
 471#define TXDESC_FSG			BIT(27)
 472#define TXDESC_OWN			BIT(31)
 473#else
 474#define TXDESC_BROADMULTICAST		BIT(0)
 475#define TXDESC_HTC			BIT(1)
 476#define TXDESC_LAST_SEGMENT		BIT(2)
 477#define TXDESC_FIRST_SEGMENT		BIT(3)
 478#define TXDESC_LINIP			BIT(4)
 479#define TXDESC_NO_ACM			BIT(5)
 480#define TXDESC_GF			BIT(6)
 481#define TXDESC_OWN			BIT(7)
 482#endif
 483
 484/* Word 1 */
 485/*
 486 * Bits 0-7 differ dependent on chip generation. For 8723au bits 5/6 are
 487 * aggregation enable and break respectively. For 8723bu, bits 0-7 are macid.
 488 */
 489#define TXDESC_PKT_OFFSET_SZ		0
 490#define TXDESC32_AGG_ENABLE		BIT(5)
 491#define TXDESC32_AGG_BREAK		BIT(6)
 492#define TXDESC40_MACID_SHIFT		0
 493#define TXDESC40_MACID_MASK		0x00f0
 494#define TXDESC_QUEUE_SHIFT		8
 495#define TXDESC_QUEUE_MASK		0x1f00
 496#define TXDESC_QUEUE_BK			0x2
 497#define TXDESC_QUEUE_BE			0x0
 498#define TXDESC_QUEUE_VI			0x5
 499#define TXDESC_QUEUE_VO			0x7
 500#define TXDESC_QUEUE_BEACON		0x10
 501#define TXDESC_QUEUE_HIGH		0x11
 502#define TXDESC_QUEUE_MGNT		0x12
 503#define TXDESC_QUEUE_CMD		0x13
 504#define TXDESC_QUEUE_MAX		(TXDESC_QUEUE_CMD + 1)
 505#define TXDESC40_RDG_NAV_EXT		BIT(13)
 506#define TXDESC40_LSIG_TXOP_ENABLE	BIT(14)
 507#define TXDESC40_PIFS			BIT(15)
 508
 509#define DESC_RATE_ID_SHIFT		16
 510#define DESC_RATE_ID_MASK		0xf
 511#define TXDESC_NAVUSEHDR		BIT(20)
 512#define TXDESC_EN_DESC_ID		BIT(21)
 513#define TXDESC_SEC_RC4			0x00400000
 514#define TXDESC_SEC_AES			0x00c00000
 515#define TXDESC_PKT_OFFSET_SHIFT		26
 516#define TXDESC_AGG_EN			BIT(29)
 517#define TXDESC_HWPC			BIT(31)
 518
 519/* Word 2 */
 520#define TXDESC40_PAID_SHIFT		0
 521#define TXDESC40_PAID_MASK		0x1ff
 522#define TXDESC40_CCA_RTS_SHIFT		10
 523#define TXDESC40_CCA_RTS_MASK		0xc00
 524#define TXDESC40_AGG_ENABLE		BIT(12)
 525#define TXDESC40_RDG_ENABLE		BIT(13)
 526#define TXDESC40_AGG_BREAK		BIT(16)
 527#define TXDESC40_MORE_FRAG		BIT(17)
 528#define TXDESC40_RAW			BIT(18)
 529#define TXDESC32_ACK_REPORT		BIT(19)
 530#define TXDESC40_SPE_RPT		BIT(19)
 531#define TXDESC_AMPDU_DENSITY_SHIFT	20
 532#define TXDESC40_BT_INT			BIT(23)
 533#define TXDESC40_GID_SHIFT		24
 534#define TXDESC_ANTENNA_SELECT_A		BIT(24)
 535#define TXDESC_ANTENNA_SELECT_B		BIT(25)
 536
 537/* Word 3 */
 538#define TXDESC40_USE_DRIVER_RATE	BIT(8)
 539#define TXDESC40_CTS_SELF_ENABLE	BIT(11)
 540#define TXDESC40_RTS_CTS_ENABLE		BIT(12)
 541#define TXDESC40_HW_RTS_ENABLE		BIT(13)
 542#define TXDESC32_SEQ_SHIFT		16
 543#define TXDESC32_SEQ_MASK		0x0fff0000
 544
 545/* Word 4 */
 546#define TXDESC32_RTS_RATE_SHIFT		0
 547#define TXDESC32_RTS_RATE_MASK		0x3f
 548#define TXDESC32_QOS			BIT(6)
 549#define TXDESC32_HW_SEQ_ENABLE		BIT(7)
 550#define TXDESC32_USE_DRIVER_RATE	BIT(8)
 551#define TXDESC_DISABLE_DATA_FB		BIT(10)
 552#define TXDESC32_CTS_SELF_ENABLE	BIT(11)
 553#define TXDESC32_RTS_CTS_ENABLE		BIT(12)
 554#define TXDESC32_HW_RTS_ENABLE		BIT(13)
 555#define TXDESC32_PT_STAGE_MASK		GENMASK(17, 15)
 556#define TXDESC_PRIME_CH_OFF_LOWER	BIT(20)
 557#define TXDESC_PRIME_CH_OFF_UPPER	BIT(21)
 558#define TXDESC32_SHORT_PREAMBLE		BIT(24)
 559#define TXDESC_DATA_BW			BIT(25)
 560#define TXDESC_RTS_DATA_BW		BIT(27)
 561#define TXDESC_RTS_PRIME_CH_OFF_LOWER	BIT(28)
 562#define TXDESC_RTS_PRIME_CH_OFF_UPPER	BIT(29)
 563#define TXDESC40_DATA_RATE_FB_SHIFT	8
 564#define TXDESC40_DATA_RATE_FB_MASK	0x00001f00
 565#define TXDESC40_RETRY_LIMIT_ENABLE	BIT(17)
 566#define TXDESC40_RETRY_LIMIT_SHIFT	18
 567#define TXDESC40_RETRY_LIMIT_MASK	0x00fc0000
 568#define TXDESC40_RTS_RATE_SHIFT		24
 569#define TXDESC40_RTS_RATE_MASK		0x3f000000
 570
 571/* Word 5 */
 572#define TXDESC40_SHORT_PREAMBLE		BIT(4)
 573#define TXDESC32_SHORT_GI		BIT(6)
 574#define TXDESC_CCX_TAG			BIT(7)
 575#define TXDESC32_RETRY_LIMIT_ENABLE	BIT(17)
 576#define TXDESC32_RETRY_LIMIT_SHIFT	18
 577#define TXDESC32_RETRY_LIMIT_MASK	0x00fc0000
 578
 579/* Word 6 */
 580#define TXDESC_MAX_AGG_SHIFT		11
 581#define TXDESC_USB_TX_AGG_SHIT		24
 582
 583/* Word 7 */
 584#define TXDESC_ANTENNA_SELECT_C		BIT(29)
 585
 586/* Word 8 */
 587#define TXDESC40_HW_SEQ_ENABLE		BIT(15)
 588
 589/* Word 9 */
 590#define TXDESC40_SEQ_SHIFT		12
 591#define TXDESC40_SEQ_MASK		0x00fff000
 592
 593struct phy_rx_agc_info {
 594#ifdef __LITTLE_ENDIAN
 595	u8	gain:7, trsw:1;
 596#else
 597	u8	trsw:1, gain:7;
 598#endif
 599};
 600
 601#define CCK_AGC_RPT_LNA_IDX_MASK	GENMASK(7, 5)
 602#define CCK_AGC_RPT_VGA_IDX_MASK	GENMASK(4, 0)
 603
 604struct rtl8723au_phy_stats {
 605	struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS];
 606	u8	ch_corr[RTL8723A_MAX_RF_PATHS];
 607	u8	cck_sig_qual_ofdm_pwdb_all;
 608	u8	cck_agc_rpt_ofdm_cfosho_a;
 609	u8	cck_rpt_b_ofdm_cfosho_b;
 610	u8	reserved_1;
 611	u8	noise_power_db_msb;
 612	s8	path_cfotail[RTL8723A_MAX_RF_PATHS];
 613	u8	pcts_mask[RTL8723A_MAX_RF_PATHS];
 614	s8	stream_rxevm[RTL8723A_MAX_RF_PATHS];
 615	u8	path_rxsnr[RTL8723A_MAX_RF_PATHS];
 616	u8	noise_power_db_lsb;
 617	u8	reserved_2[3];
 618	u8	stream_csi[RTL8723A_MAX_RF_PATHS];
 619	u8	stream_target_csi[RTL8723A_MAX_RF_PATHS];
 620	s8	sig_evm;
 621	u8	reserved_3;
 622
 623#ifdef __LITTLE_ENDIAN
 624	u8	antsel_rx_keep_2:1;	/* ex_intf_flg:1; */
 625	u8	sgi_en:1;
 626	u8	rxsc:2;
 627	u8	idle_long:1;
 628	u8	r_ant_train_en:1;
 629	u8	antenna_select_b:1;
 630	u8	antenna_select:1;
 631#else	/*  _BIG_ENDIAN_ */
 632	u8	antenna_select:1;
 633	u8	antenna_select_b:1;
 634	u8	r_ant_train_en:1;
 635	u8	idle_long:1;
 636	u8	rxsc:2;
 637	u8	sgi_en:1;
 638	u8	antsel_rx_keep_2:1;	/* ex_intf_flg:1; */
 639#endif
 640};
 641
 642struct jaguar2_phy_stats_type0 {
 643	/* DW0 */
 644	u8		page_num;
 645	u8		pwdb;
 646#ifdef __LITTLE_ENDIAN
 647	u8		gain: 6;
 648	u8		rsvd_0: 1;
 649	u8		trsw: 1;
 650#else
 651	u8		trsw: 1;
 652	u8		rsvd_0: 1;
 653	u8		gain: 6;
 654#endif
 655	u8		rsvd_1;
 656
 657	/* DW1 */
 658	u8		rsvd_2;
 659#ifdef __LITTLE_ENDIAN
 660	u8		rxsc: 4;
 661	u8		agc_table: 4;
 662#else
 663	u8		agc_table: 4;
 664	u8		rxsc: 4;
 665#endif
 666	u8		channel;
 667	u8		band;
 668
 669	/* DW2 */
 670	u16		length;
 671#ifdef __LITTLE_ENDIAN
 672	u8		antidx_a: 3;
 673	u8		antidx_b: 3;
 674	u8		rsvd_3: 2;
 675	u8		antidx_c: 3;
 676	u8		antidx_d: 3;
 677	u8		rsvd_4:2;
 678#else
 679	u8		rsvd_3: 2;
 680	u8		antidx_b: 3;
 681	u8		antidx_a: 3;
 682	u8		rsvd_4:2;
 683	u8		antidx_d: 3;
 684	u8		antidx_c: 3;
 685#endif
 686
 687	/* DW3 */
 688	u8		signal_quality;
 689#ifdef __LITTLE_ENDIAN
 690	u8		vga:5;
 691	u8		lna_l:3;
 692	u8		bb_power:6;
 693	u8		rsvd_9:1;
 694	u8		lna_h:1;
 695#else
 696	u8		lna_l:3;
 697	u8		vga:5;
 698	u8		lna_h:1;
 699	u8		rsvd_9:1;
 700	u8		bb_power:6;
 701#endif
 702	u8		rsvd_5;
 703
 704	/* DW4 */
 705	u32		rsvd_6;
 706
 707	/* DW5 */
 708	u32		rsvd_7;
 709
 710	/* DW6 */
 711	u32		rsvd_8;
 712} __packed;
 713
 714struct jaguar2_phy_stats_type1 {
 715	/* DW0 and DW1 */
 716	u8		page_num;
 717	u8		pwdb[4];
 718#ifdef __LITTLE_ENDIAN
 719	u8		l_rxsc: 4;
 720	u8		ht_rxsc: 4;
 721#else
 722	u8		ht_rxsc: 4;
 723	u8		l_rxsc: 4;
 724#endif
 725	u8		channel;
 726#ifdef __LITTLE_ENDIAN
 727	u8		band: 2;
 728	u8		rsvd_0: 1;
 729	u8		hw_antsw_occu: 1;
 730	u8		gnt_bt: 1;
 731	u8		ldpc: 1;
 732	u8		stbc: 1;
 733	u8		beamformed: 1;
 734#else
 735	u8		beamformed: 1;
 736	u8		stbc: 1;
 737	u8		ldpc: 1;
 738	u8		gnt_bt: 1;
 739	u8		hw_antsw_occu: 1;
 740	u8		rsvd_0: 1;
 741	u8		band: 2;
 742#endif
 743
 744	/* DW2 */
 745	u16		lsig_length;
 746#ifdef __LITTLE_ENDIAN
 747	u8		antidx_a: 3;
 748	u8		antidx_b: 3;
 749	u8		rsvd_1: 2;
 750	u8		antidx_c: 3;
 751	u8		antidx_d: 3;
 752	u8		rsvd_2: 2;
 753#else
 754	u8		rsvd_1: 2;
 755	u8		antidx_b: 3;
 756	u8		antidx_a: 3;
 757	u8		rsvd_2: 2;
 758	u8		antidx_d: 3;
 759	u8		antidx_c: 3;
 760#endif
 761
 762	/* DW3 */
 763	u8		paid;
 764#ifdef __LITTLE_ENDIAN
 765	u8		paid_msb: 1;
 766	u8		gid: 6;
 767	u8		rsvd_3: 1;
 768#else
 769	u8		rsvd_3: 1;
 770	u8		gid: 6;
 771	u8		paid_msb: 1;
 772#endif
 773	u8		intf_pos;
 774#ifdef __LITTLE_ENDIAN
 775	u8		intf_pos_msb: 1;
 776	u8		rsvd_4: 2;
 777	u8		nb_intf_flag: 1;
 778	u8		rf_mode: 2;
 779	u8		rsvd_5: 2;
 780#else
 781	u8		rsvd_5: 2;
 782	u8		rf_mode: 2;
 783	u8		nb_intf_flag: 1;
 784	u8		rsvd_4: 2;
 785	u8		intf_pos_msb: 1;
 786#endif
 787
 788	/* DW4 */
 789	s8		rxevm[4];			/* s(8,1) */
 790
 791	/* DW5 */
 792	s8		cfo_tail[4];			/* s(8,7) */
 793
 794	/* DW6 */
 795	s8		rxsnr[4];			/* s(8,1) */
 796} __packed;
 797
 798struct jaguar2_phy_stats_type2 {
 799	/* DW0 ane DW1 */
 800	u8		page_num;
 801	u8		pwdb[4];
 802#ifdef __LITTLE_ENDIAN
 803	u8		l_rxsc: 4;
 804	u8		ht_rxsc: 4;
 805#else
 806	u8		ht_rxsc: 4;
 807	u8		l_rxsc: 4;
 808#endif
 809	u8		channel;
 810#ifdef __LITTLE_ENDIAN
 811	u8		band: 2;
 812	u8		rsvd_0: 1;
 813	u8		hw_antsw_occu: 1;
 814	u8		gnt_bt: 1;
 815	u8		ldpc: 1;
 816	u8		stbc: 1;
 817	u8		beamformed: 1;
 818#else
 819	u8		beamformed: 1;
 820	u8		stbc: 1;
 821	u8		ldpc: 1;
 822	u8		gnt_bt: 1;
 823	u8		hw_antsw_occu: 1;
 824	u8		rsvd_0: 1;
 825	u8		band: 2;
 826#endif
 827
 828	/* DW2 */
 829#ifdef __LITTLE_ENDIAN
 830	u8		shift_l_map: 6;
 831	u8		rsvd_1: 2;
 832#else
 833	u8		rsvd_1: 2;
 834	u8		shift_l_map: 6;
 835#endif
 836	u8		cnt_pw2cca;
 837#ifdef __LITTLE_ENDIAN
 838	u8		agc_table_a: 4;
 839	u8		agc_table_b: 4;
 840	u8		agc_table_c: 4;
 841	u8		agc_table_d: 4;
 842#else
 843	u8		agc_table_b: 4;
 844	u8		agc_table_a: 4;
 845	u8		agc_table_d: 4;
 846	u8		agc_table_c: 4;
 847#endif
 848
 849	/* DW3 ~ DW6*/
 850	u8		cnt_cca2agc_rdy;
 851#ifdef __LITTLE_ENDIAN
 852	u8		gain_a: 6;
 853	u8		rsvd_2: 1;
 854	u8		trsw_a: 1;
 855	u8		gain_b: 6;
 856	u8		rsvd_3: 1;
 857	u8		trsw_b: 1;
 858	u8		gain_c: 6;
 859	u8		rsvd_4: 1;
 860	u8		trsw_c: 1;
 861	u8		gain_d: 6;
 862	u8		rsvd_5: 1;
 863	u8		trsw_d: 1;
 864	u8		aagc_step_a: 2;
 865	u8		aagc_step_b: 2;
 866	u8		aagc_step_c: 2;
 867	u8		aagc_step_d: 2;
 868#else
 869	u8		trsw_a: 1;
 870	u8		rsvd_2: 1;
 871	u8		gain_a: 6;
 872	u8		trsw_b: 1;
 873	u8		rsvd_3: 1;
 874	u8		gain_b: 6;
 875	u8		trsw_c: 1;
 876	u8		rsvd_4: 1;
 877	u8		gain_c: 6;
 878	u8		trsw_d: 1;
 879	u8		rsvd_5: 1;
 880	u8		gain_d: 6;
 881	u8		aagc_step_d: 2;
 882	u8		aagc_step_c: 2;
 883	u8		aagc_step_b: 2;
 884	u8		aagc_step_a: 2;
 885#endif
 886	u8		ht_aagc_gain[4];
 887	u8		dagc_gain[4];
 888#ifdef __LITTLE_ENDIAN
 889	u8		counter: 6;
 890	u8		rsvd_6: 2;
 891	u8		syn_count: 5;
 892	u8		rsvd_7:3;
 893#else
 894	u8		rsvd_6: 2;
 895	u8		counter: 6;
 896	u8		rsvd_7:3;
 897	u8		syn_count: 5;
 898#endif
 899} __packed;
 900
 901/*
 902 * Regs to backup
 903 */
 904#define RTL8XXXU_ADDA_REGS		16
 905#define RTL8XXXU_MAC_REGS		4
 906#define RTL8XXXU_BB_REGS		9
 907
 908struct rtl8xxxu_firmware_header {
 909	__le16	signature;		/*  92C0: test chip; 92C,
 910					    88C0: test chip;
 911					    88C1: MP A-cut;
 912					    92C1: MP A-cut */
 913	u8	category;		/*  AP/NIC and USB/PCI */
 914	u8	function;
 915
 916	__le16	major_version;		/*  FW Version */
 917	u8	minor_version;		/*  FW Subversion, default 0x00 */
 918	u8	reserved1;
 919
 920	u8	month;			/*  Release time Month field */
 921	u8	date;			/*  Release time Date field */
 922	u8	hour;			/*  Release time Hour field */
 923	u8	minute;			/*  Release time Minute field */
 924
 925	__le16	ramcodesize;		/*  Size of RAM code */
 926	u16	reserved2;
 927
 928	__le32	svn_idx;		/*  SVN entry index */
 929	u32	reserved3;
 930
 931	u32	reserved4;
 932	u32	reserved5;
 933
 934	u8	data[];
 935};
 936
 937/*
 938 * 8723au/8192cu/8188ru required base power index offset tables.
 939 */
 940struct rtl8xxxu_power_base {
 941	u32 reg_0e00;
 942	u32 reg_0e04;
 943	u32 reg_0e08;
 944	u32 reg_086c;
 945
 946	u32 reg_0e10;
 947	u32 reg_0e14;
 948	u32 reg_0e18;
 949	u32 reg_0e1c;
 950
 951	u32 reg_0830;
 952	u32 reg_0834;
 953	u32 reg_0838;
 954	u32 reg_086c_2;
 955
 956	u32 reg_083c;
 957	u32 reg_0848;
 958	u32 reg_084c;
 959	u32 reg_0868;
 960};
 961
 962/*
 963 * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14
 964 */
 965struct rtl8723au_idx {
 966#ifdef __LITTLE_ENDIAN
 967	int	a:4;
 968	int	b:4;
 969#else
 970	int	b:4;
 971	int	a:4;
 972#endif
 973} __attribute__((packed));
 974
 975struct rtl8723au_efuse {
 976	__le16 rtl_id;
 977	u8 res0[0xe];
 978	u8 cck_tx_power_index_A[3];	/* 0x10 */
 979	u8 cck_tx_power_index_B[3];
 980	u8 ht40_1s_tx_power_index_A[3];	/* 0x16 */
 981	u8 ht40_1s_tx_power_index_B[3];
 982	/*
 983	 * The following entries are half-bytes split as:
 984	 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
 985	 */
 986	struct rtl8723au_idx ht20_tx_power_index_diff[3];
 987	struct rtl8723au_idx ofdm_tx_power_index_diff[3];
 988	struct rtl8723au_idx ht40_max_power_offset[3];
 989	struct rtl8723au_idx ht20_max_power_offset[3];
 990	u8 channel_plan;		/* 0x28 */
 991	u8 tssi_a;
 992	u8 thermal_meter;
 993	u8 rf_regulatory;
 994	u8 rf_option_2;
 995	u8 rf_option_3;
 996	u8 rf_option_4;
 997	u8 res7;
 998	u8 version			/* 0x30 */;
 999	u8 customer_id_major;
1000	u8 customer_id_minor;
1001	u8 xtal_k;
1002	u8 chipset;			/* 0x34 */
1003	u8 res8[0x82];
1004	u8 vid;				/* 0xb7 */
1005	u8 res9;
1006	u8 pid;				/* 0xb9 */
1007	u8 res10[0x0c];
1008	u8 mac_addr[ETH_ALEN];		/* 0xc6 */
1009	u8 res11[2];
1010	u8 vendor_name[7];
1011	u8 res12[2];
1012	u8 device_name[0x29];		/* 0xd7 */
1013};
1014
1015struct rtl8192cu_efuse {
1016	__le16 rtl_id;
1017	__le16 hpon;
1018	u8 res0[2];
1019	__le16 clk;
1020	__le16 testr;
1021	__le16 vid;
1022	__le16 did;
1023	__le16 svid;
1024	__le16 smid;						/* 0x10 */
1025	u8 res1[4];
1026	u8 mac_addr[ETH_ALEN];					/* 0x16 */
1027	u8 res2[2];
1028	u8 vendor_name[7];
1029	u8 res3[3];
1030	u8 device_name[0x14];					/* 0x28 */
1031	u8 res4[0x1e];						/* 0x3c */
1032	u8 cck_tx_power_index_A[3];				/* 0x5a */
1033	u8 cck_tx_power_index_B[3];
1034	u8 ht40_1s_tx_power_index_A[3];				/* 0x60 */
1035	u8 ht40_1s_tx_power_index_B[3];
1036	/*
1037	 * The following entries are half-bytes split as:
1038	 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
1039	 */
1040	struct rtl8723au_idx ht40_2s_tx_power_index_diff[3];
1041	struct rtl8723au_idx ht20_tx_power_index_diff[3];	/* 0x69 */
1042	struct rtl8723au_idx ofdm_tx_power_index_diff[3];
1043	struct rtl8723au_idx ht40_max_power_offset[3];		/* 0x6f */
1044	struct rtl8723au_idx ht20_max_power_offset[3];
1045	u8 channel_plan;					/* 0x75 */
1046	u8 tssi_a;
1047	u8 tssi_b;
1048	u8 thermal_meter;	/* xtal_k */			/* 0x78 */
1049	u8 rf_regulatory;
1050	u8 rf_option_2;
1051	u8 rf_option_3;
1052	u8 rf_option_4;
1053	u8 res5[1];						/* 0x7d */
1054	u8 version;
1055	u8 customer_id;
1056};
1057
1058struct rtl8723bu_pwr_idx {
1059#ifdef __LITTLE_ENDIAN
1060	int	ht20:4;
1061	int	ht40:4;
1062	int	ofdm:4;
1063	int	cck:4;
1064#else
1065	int	cck:4;
1066	int	ofdm:4;
1067	int	ht40:4;
1068	int	ht20:4;
1069#endif
1070} __attribute__((packed));
1071
1072struct rtl8723bu_efuse_tx_power {
1073	u8 cck_base[6];
1074	u8 ht40_base[5];
1075	struct rtl8723au_idx ht20_ofdm_1s_diff;
1076	struct rtl8723bu_pwr_idx pwr_diff[3];
1077	u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */
1078};
1079
1080struct rtl8723bu_efuse {
1081	__le16 rtl_id;
1082	u8 res0[0x0e];
1083	struct rtl8723bu_efuse_tx_power tx_power_index_A;	/* 0x10 */
1084	struct rtl8723bu_efuse_tx_power tx_power_index_B;	/* 0x3a */
1085	struct rtl8723bu_efuse_tx_power tx_power_index_C;	/* 0x64 */
1086	struct rtl8723bu_efuse_tx_power tx_power_index_D;	/* 0x8e */
1087	u8 channel_plan;		/* 0xb8 */
1088	u8 xtal_k;
1089	u8 thermal_meter;
1090	u8 iqk_lck;
1091	u8 pa_type;			/* 0xbc */
1092	u8 lna_type_2g;			/* 0xbd */
1093	u8 res2[3];
1094	u8 rf_board_option;
1095	u8 rf_feature_option;
1096	u8 rf_bt_setting;
1097	u8 eeprom_version;
1098	u8 eeprom_customer_id;
1099	u8 res3[2];
1100	u8 tx_pwr_calibrate_rate;
1101	u8 rf_antenna_option;		/* 0xc9 */
1102	u8 rfe_option;
1103	u8 res4[9];
1104	u8 usb_optional_function;
1105	u8 res5[0x1e];
1106	u8 res6[2];
1107	u8 serial[0x0b];		/* 0xf5 */
1108	u8 vid;				/* 0x100 */
1109	u8 res7;
1110	u8 pid;
1111	u8 res8[4];
1112	u8 mac_addr[ETH_ALEN];		/* 0x107 */
1113	u8 res9[2];
1114	u8 vendor_name[0x07];
1115	u8 res10[2];
1116	u8 device_name[0x14];
1117	u8 res11[0xcf];
1118	u8 package_type;		/* 0x1fb */
1119	u8 res12[0x4];
1120};
1121
1122struct rtl8192eu_efuse_tx_power {
1123	u8 cck_base[6];
1124	u8 ht40_base[5];
1125	struct rtl8723au_idx ht20_ofdm_1s_diff;
1126	struct rtl8723bu_pwr_idx pwr_diff[3];
1127	u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */
1128};
1129
1130struct rtl8192eu_efuse {
1131	__le16 rtl_id;
1132	u8 res0[0x0e];
1133	struct rtl8192eu_efuse_tx_power tx_power_index_A;	/* 0x10 */
1134	struct rtl8192eu_efuse_tx_power tx_power_index_B;	/* 0x3a */
1135	u8 res2[0x54];
1136	u8 channel_plan;		/* 0xb8 */
1137	u8 xtal_k;
1138	u8 thermal_meter;
1139	u8 iqk_lck;
1140	u8 pa_type;			/* 0xbc */
1141	u8 lna_type_2g;			/* 0xbd */
1142	u8 res3[1];
1143	u8 lna_type_5g;			/* 0xbf */
1144	u8 res4[1];
1145	u8 rf_board_option;
1146	u8 rf_feature_option;
1147	u8 rf_bt_setting;
1148	u8 eeprom_version;
1149	u8 eeprom_customer_id;
1150	u8 res5[3];
1151	u8 rf_antenna_option;		/* 0xc9 */
1152	u8 res6[6];
1153	u8 vid;				/* 0xd0 */
1154	u8 res7[1];
1155	u8 pid;				/* 0xd2 */
1156	u8 res8[1];
1157	u8 usb_optional_function;
1158	u8 res9[2];
1159	u8 mac_addr[ETH_ALEN];		/* 0xd7 */
1160	u8 device_info[80];
1161	u8 res11[3];
1162	u8 unknown[0x0d];		/* 0x130 */
1163	u8 res12[0xc3];
1164};
1165
1166struct rtl8188fu_efuse_tx_power {
1167	u8 cck_base[6];
1168	u8 ht40_base[5];
1169	/* a: ofdm; b: ht20 */
1170	struct rtl8723au_idx ht20_ofdm_1s_diff;
1171};
1172
1173struct rtl8188fu_efuse {
1174	__le16 rtl_id;
1175	u8 res0[0x0e];
1176	struct rtl8188fu_efuse_tx_power tx_power_index_A;	/* 0x10 */
1177	u8 res1[0x9c];			/* 0x1c */
1178	u8 channel_plan;		/* 0xb8 */
1179	u8 xtal_k;
1180	u8 thermal_meter;
1181	u8 iqk_lck;
1182	u8 res2[5];
1183	u8 rf_board_option;
1184	u8 rf_feature_option;
1185	u8 rf_bt_setting;
1186	u8 eeprom_version;
1187	u8 eeprom_customer_id;
1188	u8 res3[2];
1189	u8 kfree_thermal_k_on;
1190	u8 rf_antenna_option;		/* 0xc9 */
1191	u8 rfe_option;
1192	u8 country_code;
1193	u8 res4[4];
1194	u8 vid;				/* 0xd0 */
1195	u8 res5[1];
1196	u8 pid;				/* 0xd2 */
1197	u8 res6[1];
1198	u8 usb_optional_function;
1199	u8 res7[2];
1200	u8 mac_addr[ETH_ALEN];		/* 0xd7 */
1201	u8 res8[2];
1202	u8 vendor_name[7];
1203	u8 res9[2];
1204	u8 device_name[7];		/* 0xe8 */
1205	u8 res10[0x41];
1206	u8 unknown[0x0d];		/* 0x130 */
1207	u8 res11[0xc3];
1208};
1209
1210struct rtl8188eu_efuse {
1211	__le16 rtl_id;
1212	u8 res0[0x0e];
1213	struct rtl8192eu_efuse_tx_power tx_power_index_A;	/* 0x10 */
1214	u8 res1[0x7e];			/* 0x3a */
1215	u8 channel_plan;		/* 0xb8 */
1216	u8 xtal_k;
1217	u8 thermal_meter;
1218	u8 iqk_lck;
1219	u8 res2[5];
1220	u8 rf_board_option;
1221	u8 rf_feature_option;
1222	u8 rf_bt_setting;
1223	u8 eeprom_version;
1224	u8 eeprom_customer_id;
1225	u8 res3[3];
1226	u8 rf_antenna_option;		/* 0xc9 */
1227	u8 res4[6];
1228	u8 vid;				/* 0xd0 */
1229	u8 res5[1];
1230	u8 pid;				/* 0xd2 */
1231	u8 res6[1];
1232	u8 usb_optional_function;
1233	u8 res7[2];
1234	u8 mac_addr[ETH_ALEN];		/* 0xd7 */
1235	u8 res8[2];
1236	u8 vendor_name[7];
1237	u8 res9[2];
1238	u8 device_name[0x0b];		/* 0xe8 */
1239	u8 res10[2];
1240	u8 serial[0x0b];		/* 0xf5 */
1241	u8 res11[0x30];
1242	u8 unknown[0x0d];		/* 0x130 */
1243	u8 res12[0xc3];
1244} __packed;
1245
1246struct rtl8710bu_efuse {
1247	__le16 rtl_id;
1248	u8 res0[0x1e];
1249	struct rtl8188fu_efuse_tx_power tx_power_index_A;	/* 0x20 */
1250	u8 res1[0x9c];			/* 0x2c */
1251	u8 channel_plan;		/* 0xc8 */
1252	u8 xtal_k;			/* 0xc9 */
1253	u8 thermal_meter;		/* 0xca */
1254	u8 res2[0x4f];
1255	u8 mac_addr[ETH_ALEN];		/* 0x11a */
1256	u8 res3[0x11];
1257	u8 rf_board_option;		/* 0x131 */
1258	u8 res4[2];
1259	u8 eeprom_version;		/* 0x134 */
1260	u8 eeprom_customer_id;		/* 0x135 */
1261	u8 res5[5];
1262	u8 country_code;		/* 0x13b */
1263	u8 res6[0x84];
1264	u8 vid[2];			/* 0x1c0 */
1265	u8 pid[2];			/* 0x1c2 */
1266	u8 res7[0x3c];
1267} __packed;
1268
1269struct rtl8192fu_efuse {
1270	__le16 rtl_id;
1271	u8 res0[0x0e];
1272	struct rtl8192eu_efuse_tx_power tx_power_index_A;	/* 0x10 */
1273	struct rtl8192eu_efuse_tx_power tx_power_index_B;	/* 0x3a */
1274	u8 res2[0x54];
1275	u8 channel_plan;		/* 0xb8 */
1276	u8 xtal_k;			/* 0xb9 */
1277	u8 thermal_meter;		/* 0xba */
1278	u8 iqk_lck;			/* 0xbb */
1279	u8 pa_type;			/* 0xbc */
1280	u8 lna_type_2g;			/* 0xbd */
1281	u8 res3[1];
1282	u8 lna_type_5g;			/* 0xbf */
1283	u8 res4[1];
1284	u8 rf_board_option;		/* 0xc1 */
1285	u8 rf_feature_option;		/* 0xc2 */
1286	u8 rf_bt_setting;		/* 0xc3 */
1287	u8 eeprom_version;		/* 0xc4 */
1288	u8 eeprom_customer_id;		/* 0xc5 */
1289	u8 res5[3];
1290	u8 rf_antenna_option;		/* 0xc9 */
1291	u8 rfe_option;			/* 0xca */
1292	u8 country_code;		/* 0xcb */
1293	u8 res6[52];
1294	u8 vid[2];			/* 0x100 */
1295	u8 pid[2];			/* 0x102 */
1296	u8 usb_optional_function;	/* 0x104 */
1297	u8 res7[2];
1298	u8 mac_addr[ETH_ALEN];		/* 0x107 */
1299	u8 device_info[80];		/* 0x10d */
1300	u8 res9[163];
1301} __packed;
1302
1303struct rtl8xxxu_reg8val {
1304	u16 reg;
1305	u8 val;
1306};
1307
1308struct rtl8xxxu_reg32val {
1309	u16 reg;
1310	u32 val;
1311};
1312
1313struct rtl8xxxu_rfregval {
1314	u8 reg;
1315	u32 val;
1316};
1317
1318enum rtl8xxxu_rfpath {
1319	RF_A = 0,
1320	RF_B = 1,
1321};
1322
1323struct rtl8xxxu_rfregs {
1324	u16 hssiparm1;
1325	u16 hssiparm2;
1326	u16 lssiparm;
1327	u16 hspiread;
1328	u16 lssiread;
1329	u16 rf_sw_ctrl;
1330};
1331
1332#define H2C_MAX_MBOX			4
1333#define H2C_EXT				BIT(7)
1334#define  H2C_JOIN_BSS_DISCONNECT	0
1335#define  H2C_JOIN_BSS_CONNECT		1
1336
1337#define H2C_MACID_ROLE_STA		1
1338#define H2C_MACID_ROLE_AP		2
1339
1340/*
1341 * H2C (firmware) commands differ between the older generation chips
1342 * 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu,
1343 * 8192[de]u, 8192eu, and 8812.
1344 */
1345enum h2c_cmd_8723a {
1346	H2C_SET_POWER_MODE = 1,
1347	H2C_JOIN_BSS_REPORT = 2,
1348	H2C_SET_RSSI = 5,
1349	H2C_SET_RATE_MASK = (6 | H2C_EXT),
1350};
1351
1352enum h2c_cmd_8723b {
1353	/*
1354	 * Common Class: 000
1355	 */
1356	H2C_8723B_RSVD_PAGE = 0x00,
1357	H2C_8723B_MEDIA_STATUS_RPT = 0x01,
1358	H2C_8723B_SCAN_ENABLE = 0x02,
1359	H2C_8723B_KEEP_ALIVE = 0x03,
1360	H2C_8723B_DISCON_DECISION = 0x04,
1361	H2C_8723B_PSD_OFFLOAD = 0x05,
1362	H2C_8723B_AP_OFFLOAD = 0x08,
1363	H2C_8723B_BCN_RSVDPAGE = 0x09,
1364	H2C_8723B_PROBERSP_RSVDPAGE = 0x0A,
1365	H2C_8723B_FCS_RSVDPAGE = 0x10,
1366	H2C_8723B_FCS_INFO = 0x11,
1367	H2C_8723B_AP_WOW_GPIO_CTRL = 0x13,
1368
1369	/*
1370	 * PoweSave Class: 001
1371	 */
1372	H2C_8723B_SET_PWR_MODE = 0x20,
1373	H2C_8723B_PS_TUNING_PARA = 0x21,
1374	H2C_8723B_PS_TUNING_PARA2 = 0x22,
1375	H2C_8723B_P2P_LPS_PARAM = 0x23,
1376	H2C_8723B_P2P_PS_OFFLOAD = 0x24,
1377	H2C_8723B_PS_SCAN_ENABLE = 0x25,
1378	H2C_8723B_SAP_PS_ = 0x26,
1379	H2C_8723B_INACTIVE_PS_ = 0x27,
1380	H2C_8723B_FWLPS_IN_IPS_ = 0x28,
1381
1382	/*
1383	 * Dynamic Mechanism Class: 010
1384	 */
1385	H2C_8723B_MACID_CFG_RAID = 0x40,
1386	H2C_8723B_TXBF = 0x41,
1387	H2C_8723B_RSSI_SETTING = 0x42,
1388	H2C_8723B_AP_REQ_TXRPT = 0x43,
1389	H2C_8723B_INIT_RATE_COLLECT = 0x44,
1390
1391	/*
1392	 * BT Class: 011
1393	 */
1394	H2C_8723B_B_TYPE_TDMA = 0x60,
1395	H2C_8723B_BT_INFO = 0x61,
1396	H2C_8723B_FORCE_BT_TXPWR = 0x62,
1397	H2C_8723B_BT_IGNORE_WLANACT = 0x63,
1398	H2C_8723B_DAC_SWING_VALUE = 0x64,
1399	H2C_8723B_ANT_SEL_RSV = 0x65,
1400	H2C_8723B_WL_OPMODE = 0x66,
1401	H2C_8723B_BT_MP_OPER = 0x67,
1402	H2C_8723B_BT_CONTROL = 0x68,
1403	H2C_8723B_BT_WIFI_CTRL = 0x69,
1404	H2C_8723B_BT_FW_PATCH = 0x6a,
1405	H2C_8723B_BT_WLAN_CALIBRATION = 0x6d,
1406	H2C_8723B_BT_GRANT = 0x6e,
1407
1408	/*
1409	 * WOWLAN Class: 100
1410	 */
1411	H2C_8723B_WOWLAN = 0x80,
1412	H2C_8723B_REMOTE_WAKE_CTRL = 0x81,
1413	H2C_8723B_AOAC_GLOBAL_INFO = 0x82,
1414	H2C_8723B_AOAC_RSVD_PAGE = 0x83,
1415	H2C_8723B_AOAC_RSVD_PAGE2 = 0x84,
1416	H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85,
1417	H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86,
1418	H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87,
1419
1420	H2C_8723B_RESET_TSF = 0xC0,
1421};
1422
1423
1424struct h2c_cmd {
1425	union {
1426		struct {
1427			u8 cmd;
1428			u8 data[7];
1429		} __packed cmd;
1430		struct {
1431			__le32 data;
1432			__le16 ext;
1433		} __packed raw;
1434		struct {
1435			__le32 data;
1436			__le32 ext;
1437		} __packed raw_wide;
1438		struct {
1439			u8 cmd;
1440			u8 data;
1441		} __packed joinbss;
1442		struct {
1443			u8 cmd;
1444			__le16 mask_hi;
1445			u8 arg;
1446			__le16 mask_lo;
1447		} __packed ramask;
1448		struct {
1449			u8 cmd;
1450			u8 parm;
1451			u8 macid;
1452			u8 macid_end;
1453		} __packed media_status_rpt;
1454		struct {
1455			u8 cmd;
1456			u8 macid;
1457			/*
1458			 * [0:4] - RAID
1459			 * [7]   - SGI
1460			 */
1461			u8 data1;
1462			/*
1463			 * [0:1] - Bandwidth
1464			 * [3]   - No Update
1465			 * [4:5] - VHT enable
1466			 * [6]   - DISPT
1467			 * [7]   - DISRA
1468			 */
1469			u8 data2;
1470			u8 ramask0;
1471			u8 ramask1;
1472			u8 ramask2;
1473			u8 ramask3;
1474		} __packed b_macid_cfg;
1475		struct {
1476			u8 cmd;
1477			u8 data1;
1478			u8 data2;
1479			u8 data3;
1480			u8 data4;
1481			u8 data5;
1482		} __packed b_type_dma;
1483		struct {
1484			u8 cmd;
1485			u8 data;
1486		} __packed bt_info;
1487		struct {
1488			u8 cmd;
1489			u8 operreq;
1490			u8 opcode;
1491			u8 data;
1492			u8 addr;
1493		} __packed bt_mp_oper;
1494		struct {
1495			u8 cmd;
1496			u8 data;
1497		} __packed bt_wlan_calibration;
1498		struct {
1499			u8 cmd;
1500			u8 data;
1501		} __packed ignore_wlan;
1502		struct {
1503			u8 cmd;
1504			u8 ant_inverse;
1505			u8 int_switch_type;
1506		} __packed ant_sel_rsv;
1507		struct {
1508			u8 cmd;
1509			u8 data;
1510		} __packed bt_grant;
1511		struct {
1512			u8 cmd;
1513			u8 macid;
1514			u8 unknown0;
1515			u8 rssi;
1516			/*
1517			 * [0]   - is_rx
1518			 * [1]   - stbc_en
1519			 * [2]   - noisy_decision
1520			 * [6]   - bf_en
1521			 */
1522			u8 data;
1523			/*
1524			 * [0:6] - ra_th_offset
1525			 * [7]   - ra_offset_direction
1526			 */
1527			u8 ra_th_offset;
1528			u8 unknown1;
1529			u8 unknown2;
1530		} __packed rssi_report;
1531	};
1532};
1533
1534enum c2h_evt_8723b {
1535	C2H_8723B_DEBUG = 0,
1536	C2H_8723B_TSF = 1,
1537	C2H_8723B_AP_RPT_RSP = 2,
1538	C2H_8723B_CCX_TX_RPT = 3,
1539	C2H_8723B_BT_RSSI = 4,
1540	C2H_8723B_BT_OP_MODE = 5,
1541	C2H_8723B_EXT_RA_RPT = 6,
1542	C2H_8723B_BT_INFO = 9,
1543	C2H_8723B_HW_INFO_EXCH = 0x0a,
1544	C2H_8723B_BT_MP_INFO = 0x0b,
1545	C2H_8723B_RA_REPORT = 0x0c,
1546	C2H_8723B_FW_DEBUG = 0xff,
1547};
1548
1549enum bt_info_src_8723b {
1550	BT_INFO_SRC_8723B_WIFI_FW = 0x0,
1551        BT_INFO_SRC_8723B_BT_RSP = 0x1,
1552        BT_INFO_SRC_8723B_BT_ACTIVE_SEND = 0x2,
1553};
1554
1555enum bt_mp_oper_opcode_8723b {
1556	BT_MP_OP_GET_BT_VERSION	= 0x00,
1557	BT_MP_OP_RESET = 0x01,
1558	BT_MP_OP_TEST_CTRL = 0x02,
1559	BT_MP_OP_SET_BT_MODE = 0x03,
1560	BT_MP_OP_SET_CHNL_TX_GAIN = 0x04,
1561	BT_MP_OP_SET_PKT_TYPE_LEN = 0x05,
1562	BT_MP_OP_SET_PKT_CNT_L_PL_TYPE = 0x06,
1563	BT_MP_OP_SET_PKT_CNT_H_PKT_INTV = 0x07,
1564	BT_MP_OP_SET_PKT_HEADER = 0x08,
1565	BT_MP_OP_SET_WHITENCOEFF = 0x09,
1566	BT_MP_OP_SET_BD_ADDR_L = 0x0a,
1567	BT_MP_OP_SET_BD_ADDR_H = 0x0b,
1568	BT_MP_OP_WRITE_REG_ADDR = 0x0c,
1569	BT_MP_OP_WRITE_REG_VALUE = 0x0d,
1570	BT_MP_OP_GET_BT_STATUS = 0x0e,
1571	BT_MP_OP_GET_BD_ADDR_L = 0x0f,
1572	BT_MP_OP_GET_BD_ADDR_H = 0x10,
1573	BT_MP_OP_READ_REG = 0x11,
1574	BT_MP_OP_SET_TARGET_BD_ADDR_L = 0x12,
1575	BT_MP_OP_SET_TARGET_BD_ADDR_H = 0x13,
1576	BT_MP_OP_SET_TX_POWER_CALIBRATION = 0x14,
1577	BT_MP_OP_GET_RX_PKT_CNT_L = 0x15,
1578	BT_MP_OP_GET_RX_PKT_CNT_H = 0x16,
1579	BT_MP_OP_GET_RX_ERROR_BITS_L = 0x17,
1580	BT_MP_OP_GET_RX_ERROR_BITS_H = 0x18,
1581	BT_MP_OP_GET_RSSI = 0x19,
1582	BT_MP_OP_GET_CFO_HDR_QUALITY_L = 0x1a,
1583	BT_MP_OP_GET_CFO_HDR_QUALITY_H = 0x1b,
1584	BT_MP_OP_GET_TARGET_BD_ADDR_L = 0x1c,
1585	BT_MP_OP_GET_TARGET_BD_ADDR_H = 0x1d,
1586	BT_MP_OP_GET_AFH_MAP_L = 0x1e,
1587	BT_MP_OP_GET_AFH_MAP_M = 0x1f,
1588	BT_MP_OP_GET_AFH_MAP_H = 0x20,
1589	BT_MP_OP_GET_AFH_STATUS = 0x21,
1590	BT_MP_OP_SET_TRACKING_INTERVAL = 0x22,
1591	BT_MP_OP_SET_THERMAL_METER = 0x23,
1592	BT_MP_OP_ENABLE_CFO_TRACKING = 0x24,
1593};
1594
1595enum rtl8xxxu_bw_mode {
1596	RTL8XXXU_CHANNEL_WIDTH_20 = 0,
1597	RTL8XXXU_CHANNEL_WIDTH_40 = 1,
1598	RTL8XXXU_CHANNEL_WIDTH_80 = 2,
1599	RTL8XXXU_CHANNEL_WIDTH_160 = 3,
1600	RTL8XXXU_CHANNEL_WIDTH_80_80 = 4,
1601	RTL8XXXU_CHANNEL_WIDTH_MAX = 5,
1602};
1603
1604struct rtl8723bu_c2h {
1605	u8 id;
1606	u8 seq;
1607	union {
1608		struct {
1609			u8 payload[0];
1610		} __packed raw;
1611		struct {
1612			u8 ext_id;
1613			u8 status:4;
1614			u8 retlen:4;
1615			u8 opcode_ver:4;
1616			u8 req_num:4;
1617			u8 payload[2];
1618		} __packed bt_mp_info;
1619		struct {
1620			u8 response_source:4;
1621			u8 dummy0_0:4;
1622
1623			u8 bt_info;
1624
1625			u8 retry_count:4;
1626			u8 dummy2_0:1;
1627			u8 bt_page:1;
1628			u8 tx_rx_mask:1;
1629			u8 dummy2_2:1;
1630
1631			u8 rssi;
1632
1633			u8 basic_rate:1;
1634			u8 bt_has_reset:1;
1635			u8 dummy4_1:1;
1636			u8 ignore_wlan:1;
1637			u8 auto_report:1;
1638			u8 dummy4_2:3;
1639
1640			u8 a4;
1641			u8 a5;
1642		} __packed bt_info;
1643		struct {
1644			u8 rate:7;
1645			u8 sgi:1;
1646			u8 macid;
1647			u8 ldpc:1;
1648			u8 txbf:1;
1649			u8 noisy_state:1;
1650			u8 dummy2_0:5;
1651			u8 dummy3_0;
1652			u8 dummy4_0;
1653			u8 dummy5_0;
1654			u8 bw;
1655		} __packed ra_report;
1656	};
1657} __packed;
1658
1659struct rtl8xxxu_fileops;
1660
1661/*mlme related.*/
1662enum wireless_mode {
1663	WIRELESS_MODE_UNKNOWN = 0,
1664	/* Sub-Element */
1665	WIRELESS_MODE_B = BIT(0),
1666	WIRELESS_MODE_G = BIT(1),
1667	WIRELESS_MODE_A = BIT(2),
1668	WIRELESS_MODE_N_24G = BIT(3),
1669	WIRELESS_MODE_N_5G = BIT(4),
1670	WIRELESS_AUTO = BIT(5),
1671	WIRELESS_MODE_AC = BIT(6),
1672	WIRELESS_MODE_MAX = 0x7F,
1673};
1674
1675/* from rtlwifi/wifi.h */
1676enum ratr_table_mode_new {
1677	RATEID_IDX_BGN_40M_2SS = 0,
1678	RATEID_IDX_BGN_40M_1SS = 1,
1679	RATEID_IDX_BGN_20M_2SS_BN = 2,
1680	RATEID_IDX_BGN_20M_1SS_BN = 3,
1681	RATEID_IDX_GN_N2SS = 4,
1682	RATEID_IDX_GN_N1SS = 5,
1683	RATEID_IDX_BG = 6,
1684	RATEID_IDX_G = 7,
1685	RATEID_IDX_B = 8,
1686	RATEID_IDX_VHT_2SS = 9,
1687	RATEID_IDX_VHT_1SS = 10,
1688	RATEID_IDX_MIX1 = 11,
1689	RATEID_IDX_MIX2 = 12,
1690	RATEID_IDX_VHT_3SS = 13,
1691	RATEID_IDX_BGN_3SS = 14,
1692};
1693
1694#define BT_INFO_8723B_1ANT_B_FTP		BIT(7)
1695#define BT_INFO_8723B_1ANT_B_A2DP		BIT(6)
1696#define BT_INFO_8723B_1ANT_B_HID		BIT(5)
1697#define BT_INFO_8723B_1ANT_B_SCO_BUSY		BIT(4)
1698#define BT_INFO_8723B_1ANT_B_ACL_BUSY		BIT(3)
1699#define BT_INFO_8723B_1ANT_B_INQ_PAGE		BIT(2)
1700#define BT_INFO_8723B_1ANT_B_SCO_ESCO		BIT(1)
1701#define BT_INFO_8723B_1ANT_B_CONNECTION	BIT(0)
1702
1703enum _BT_8723B_1ANT_STATUS {
1704	BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE      = 0x0,
1705	BT_8723B_1ANT_STATUS_CONNECTED_IDLE          = 0x1,
1706	BT_8723B_1ANT_STATUS_INQ_PAGE                = 0x2,
1707	BT_8723B_1ANT_STATUS_ACL_BUSY                = 0x3,
1708	BT_8723B_1ANT_STATUS_SCO_BUSY                = 0x4,
1709	BT_8723B_1ANT_STATUS_ACL_SCO_BUSY            = 0x5,
1710	BT_8723B_1ANT_STATUS_MAX
1711};
1712
1713struct rtl8xxxu_btcoex {
1714	u8      bt_status;
1715	bool	bt_busy;
1716	bool	has_sco;
1717	bool	has_a2dp;
1718	bool    has_hid;
1719	bool    has_pan;
1720	bool	hid_only;
1721	bool	a2dp_only;
1722	bool    c2h_bt_inquiry;
1723};
1724
1725#define RTL8XXXU_RATR_STA_INIT 0
1726#define RTL8XXXU_RATR_STA_HIGH 1
1727#define RTL8XXXU_RATR_STA_MID  2
1728#define RTL8XXXU_RATR_STA_LOW  3
1729
1730#define RTL8XXXU_NOISE_FLOOR_MIN	-100
1731#define RTL8XXXU_SNR_THRESH_HIGH	50
1732#define RTL8XXXU_SNR_THRESH_LOW	20
1733
1734struct rtl8xxxu_ra_report {
1735	struct rate_info txrate;
1736	u32 bit_rate;
1737	u8 desc_rate;
1738};
1739
1740struct rtl8xxxu_ra_info {
1741	u8 rate_id;
1742	u32 rate_mask;
1743	u32 ra_use_rate;
1744	u8 rate_sgi;
1745	u8 rssi_sta_ra;		/* Percentage */
1746	u8 pre_rssi_sta_ra;
1747	u8 sgi_enable;
1748	u8 decision_rate;
1749	u8 pre_rate;
1750	u8 highest_rate;
1751	u8 lowest_rate;
1752	u32 nsc_up;
1753	u32 nsc_down;
1754	u32 total;
1755	u16 retry[5];
1756	u16 drop;
1757	u16 rpt_time;
1758	u16 pre_min_rpt_time;
1759	u8 dynamic_tx_rpt_timing_counter;
1760	u8 ra_waiting_counter;
1761	u8 ra_pending_counter;
1762	u8 ra_drop_after_down;
1763	u8 pt_try_state;	/* 0 trying state, 1 for decision state */
1764	u8 pt_stage;		/* 0~6 */
1765	u8 pt_stop_count;	/* Stop PT counter */
1766	u8 pt_pre_rate;		/* if rate change do PT */
1767	u8 pt_pre_rssi;		/* if RSSI change 5% do PT */
1768	u8 pt_mode_ss;		/* decide which rate should do PT */
1769	u8 ra_stage;		/* StageRA, decide how many times RA will be done between PT */
1770	u8 pt_smooth_factor;
1771};
1772
1773#define CFO_TH_XTAL_HIGH	20 /* kHz */
1774#define CFO_TH_XTAL_LOW	10 /* kHz */
1775#define CFO_TH_ATC		80 /* kHz */
1776
1777struct rtl8xxxu_cfo_tracking {
1778	bool adjust;
1779	bool atc_status;
1780	int cfo_tail[2];
1781	u8 crystal_cap;
1782	u32 packet_count;
1783	u32 packet_count_pre;
1784};
1785
1786#define RTL8XXXU_HW_LED_CONTROL	2
1787#define RTL8XXXU_MAX_MAC_ID_NUM	128
1788#define RTL8XXXU_BC_MC_MACID	0
1789#define RTL8XXXU_BC_MC_MACID1	1
1790#define RTL8XXXU_MAX_SEC_CAM_NUM	64
1791
1792struct rtl8xxxu_priv {
1793	struct ieee80211_hw *hw;
1794	struct usb_device *udev;
1795	struct rtl8xxxu_fileops *fops;
1796
1797	spinlock_t tx_urb_lock;
1798	struct list_head tx_urb_free_list;
1799	int tx_urb_free_count;
1800	bool tx_stopped;
1801
1802	spinlock_t rx_urb_lock;
1803	struct list_head rx_urb_pending_list;
1804	int rx_urb_pending_count;
1805	bool shutdown;
1806	struct work_struct rx_urb_wq;
1807
1808	u8 mac_addr[ETH_ALEN];
1809	char chip_name[8];
1810	char chip_vendor[8];
1811	u8 cck_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS];
1812	u8 cck_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS];
1813	u8 ht40_1s_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS];
1814	u8 ht40_1s_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS];
1815	/*
1816	 * The following entries are half-bytes split as:
1817	 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
1818	 */
1819	struct rtl8723au_idx ht40_2s_tx_power_index_diff[
1820		RTL8723A_CHANNEL_GROUPS];
1821	struct rtl8723au_idx ht20_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS];
1822	struct rtl8723au_idx ofdm_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS];
1823	struct rtl8723au_idx ht40_max_power_offset[RTL8723A_CHANNEL_GROUPS];
1824	struct rtl8723au_idx ht20_max_power_offset[RTL8723A_CHANNEL_GROUPS];
1825	/*
1826	 * Newer generation chips only keep power diffs per TX count,
1827	 * not per channel group.
1828	 */
1829	struct rtl8723au_idx ofdm_tx_power_diff[RTL8723B_TX_COUNT];
1830	struct rtl8723au_idx ht20_tx_power_diff[RTL8723B_TX_COUNT];
1831	struct rtl8723au_idx ht40_tx_power_diff[RTL8723B_TX_COUNT];
1832	struct rtl8xxxu_power_base *power_base;
1833	u8 package_type;
1834	u32 chip_cut:4;
1835	u32 rom_rev:4;
1836	u32 is_multi_func:1;
1837	u32 has_wifi:1;
1838	u32 has_bluetooth:1;
1839	u32 enable_bluetooth:1;
1840	u32 has_gps:1;
1841	u32 hi_pa:1;
1842	u32 vendor_umc:1;
1843	u32 vendor_smic:1;
1844	u32 has_polarity_ctrl:1;
1845	u32 has_eeprom:1;
1846	u32 boot_eeprom:1;
1847	u32 usb_interrupts:1;
1848	u32 ep_tx_high_queue:1;
1849	u32 ep_tx_normal_queue:1;
1850	u32 ep_tx_low_queue:1;
1851	u32 rx_buf_aggregation:1;
1852	u32 cck_agc_report_type:1;
1853	u32 cck_new_agc:1;
1854	u8 default_crystal_cap;
1855	u8 rfe_type;
1856	unsigned int pipe_interrupt;
1857	unsigned int pipe_in;
1858	unsigned int pipe_out[TXDESC_QUEUE_MAX];
1859	u8 out_ep[RTL8XXXU_OUT_ENDPOINTS];
1860	u8 ep_tx_count;
1861	u8 rf_paths;
1862	u8 rx_paths;
1863	u8 tx_paths;
1864	u32 rege94;
1865	u32 rege9c;
1866	u32 regeb4;
1867	u32 regebc;
1868	u32 regrcr;
1869	int next_mbox;
1870	int nr_out_eps;
1871
1872	/* Ensure no added or deleted stas while iterating */
1873	struct mutex sta_mutex;
1874	struct mutex h2c_mutex;
1875	/* Protect the indirect register accesses of RTL8710BU. */
1876	struct mutex syson_indirect_access_mutex;
1877
1878	struct usb_anchor rx_anchor;
1879	struct usb_anchor tx_anchor;
1880	struct usb_anchor int_anchor;
1881	struct rtl8xxxu_firmware_header *fw_data;
1882	size_t fw_size;
1883	struct mutex usb_buf_mutex;
1884	union {
1885		__le32 val32;
1886		__le16 val16;
1887		u8 val8;
1888	} usb_buf;
1889	union {
1890		u8 raw[EFUSE_MAP_LEN];
1891		struct rtl8723au_efuse efuse8723;
1892		struct rtl8723bu_efuse efuse8723bu;
1893		struct rtl8192cu_efuse efuse8192;
1894		struct rtl8192eu_efuse efuse8192eu;
1895		struct rtl8188fu_efuse efuse8188fu;
1896		struct rtl8188eu_efuse efuse8188eu;
1897		struct rtl8710bu_efuse efuse8710bu;
1898		struct rtl8192fu_efuse efuse8192fu;
1899	} efuse_wifi;
1900	u32 adda_backup[RTL8XXXU_ADDA_REGS];
1901	u32 mac_backup[RTL8XXXU_MAC_REGS];
1902	u32 bb_backup[RTL8XXXU_BB_REGS];
1903	u32 bb_recovery_backup[RTL8XXXU_BB_REGS];
1904	enum rtl8xxxu_rtl_chip rtl_chip;
1905	u8 pi_enabled:1;
1906	u8 no_pape:1;
1907	u8 int_buf[USB_INTR_CONTENT_LENGTH];
1908	DECLARE_BITMAP(tx_aggr_started, IEEE80211_NUM_TIDS);
1909	DECLARE_BITMAP(tid_tx_operational, IEEE80211_NUM_TIDS);
1910
1911	struct ieee80211_vif *vifs[2];
1912	struct delayed_work ra_watchdog;
1913	struct work_struct c2hcmd_work;
1914	struct sk_buff_head c2hcmd_queue;
1915	struct delayed_work update_beacon_work;
1916	struct rtl8xxxu_btcoex bt_coex;
1917	struct rtl8xxxu_ra_report ra_report;
1918	struct rtl8xxxu_cfo_tracking cfo_tracking;
1919	struct rtl8xxxu_ra_info ra_info;
1920
1921	bool led_registered;
1922	char led_name[32];
1923	struct led_classdev led_cdev;
1924	DECLARE_BITMAP(mac_id_map, RTL8XXXU_MAX_MAC_ID_NUM);
1925	DECLARE_BITMAP(cam_map, RTL8XXXU_MAX_SEC_CAM_NUM);
1926};
1927
1928DECLARE_EWMA(rssi, 10, 16);
1929
1930struct rtl8xxxu_sta_info {
1931	struct ieee80211_sta *sta;
1932	struct ieee80211_vif *vif;
1933
1934	u8 macid;
1935	struct ewma_rssi avg_rssi;
1936	u8 rssi_level;
1937};
1938
1939struct rtl8xxxu_vif {
1940	int port_num;
1941	u8 hw_key_idx;
1942};
1943
1944struct rtl8xxxu_rx_urb {
1945	struct urb urb;
1946	struct ieee80211_hw *hw;
1947	struct list_head list;
1948};
1949
1950struct rtl8xxxu_tx_urb {
1951	struct urb urb;
1952	struct ieee80211_hw *hw;
1953	struct list_head list;
1954};
1955
1956struct rtl8xxxu_fileops {
1957	int (*identify_chip) (struct rtl8xxxu_priv *priv);
1958	int (*read_efuse) (struct rtl8xxxu_priv *priv);
1959	int (*parse_efuse) (struct rtl8xxxu_priv *priv);
1960	int (*load_firmware) (struct rtl8xxxu_priv *priv);
1961	int (*power_on) (struct rtl8xxxu_priv *priv);
1962	void (*power_off) (struct rtl8xxxu_priv *priv);
1963	void (*reset_8051) (struct rtl8xxxu_priv *priv);
1964	int (*llt_init) (struct rtl8xxxu_priv *priv);
1965	void (*init_phy_bb) (struct rtl8xxxu_priv *priv);
1966	int (*init_phy_rf) (struct rtl8xxxu_priv *priv);
1967	void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv);
1968	void (*phy_lc_calibrate) (struct rtl8xxxu_priv *priv);
1969	void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv);
1970	void (*config_channel) (struct ieee80211_hw *hw);
1971	int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb);
1972	void (*parse_phystats) (struct rtl8xxxu_priv *priv,
1973				struct ieee80211_rx_status *rx_status,
1974				struct rtl8723au_phy_stats *phy_stats,
1975				u32 rxmcs, struct ieee80211_hdr *hdr,
1976				bool crc_icv_err);
1977	void (*init_aggregation) (struct rtl8xxxu_priv *priv);
1978	void (*init_statistics) (struct rtl8xxxu_priv *priv);
1979	void (*init_burst) (struct rtl8xxxu_priv *priv);
1980	void (*enable_rf) (struct rtl8xxxu_priv *priv);
1981	void (*disable_rf) (struct rtl8xxxu_priv *priv);
1982	void (*usb_quirks) (struct rtl8xxxu_priv *priv);
1983	void (*set_tx_power) (struct rtl8xxxu_priv *priv, int channel,
1984			      bool ht40);
1985	void (*update_rate_mask) (struct rtl8xxxu_priv *priv,
1986				  u32 ramask, u8 rateid, int sgi, int txbw_40mhz,
1987				  u8 macid);
1988	void (*report_connect) (struct rtl8xxxu_priv *priv,
1989				u8 macid, u8 role, bool connect);
1990	void (*report_rssi) (struct rtl8xxxu_priv *priv, u8 macid, u8 rssi);
1991	void (*fill_txdesc) (struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
1992			     struct ieee80211_tx_info *tx_info,
1993			     struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
1994			     bool short_preamble, bool ampdu_enable,
1995			     u32 rts_rate, u8 macid);
1996	void (*set_crystal_cap) (struct rtl8xxxu_priv *priv, u8 crystal_cap);
1997	s8 (*cck_rssi) (struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats);
1998	int (*led_classdev_brightness_set) (struct led_classdev *led_cdev,
1999					    enum led_brightness brightness);
2000	int writeN_block_size;
2001	int rx_agg_buf_size;
2002	char tx_desc_size;
2003	char rx_desc_size;
2004	u8 has_s0s1:1;
2005	u8 has_tx_report:1;
2006	u8 gen2_thermal_meter:1;
2007	u8 needs_full_init:1;
2008	u8 init_reg_rxfltmap:1;
2009	u8 init_reg_pkt_life_time:1;
2010	u8 init_reg_hmtfr:1;
2011	u8 supports_concurrent:1;
2012	u8 ampdu_max_time;
2013	u8 ustime_tsf_edca;
2014	u16 max_aggr_num;
2015	u8 supports_ap:1;
2016	u16 max_macid_num;
2017	u16 max_sec_cam_num;
2018	u32 adda_1t_init;
2019	u32 adda_1t_path_on;
2020	u32 adda_2t_path_on_a;
2021	u32 adda_2t_path_on_b;
2022	u16 trxff_boundary;
2023	u8 pbp_rx;
2024	u8 pbp_tx;
2025	const struct rtl8xxxu_reg8val *mactable;
2026	u8 total_page_num;
2027	u8 page_num_hi;
2028	u8 page_num_lo;
2029	u8 page_num_norm;
2030	u8 last_llt_entry;
2031};
2032
2033extern int rtl8xxxu_debug;
2034
2035extern const u32 rtl8xxxu_iqk_phy_iq_bb_reg[];
2036u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr);
2037u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr);
2038u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr);
2039int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val);
2040int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val);
2041int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val);
2042int rtl8xxxu_write8_set(struct rtl8xxxu_priv *priv, u16 addr, u8 bits);
2043int rtl8xxxu_write8_clear(struct rtl8xxxu_priv *priv, u16 addr, u8 bits);
2044int rtl8xxxu_write16_set(struct rtl8xxxu_priv *priv, u16 addr, u16 bits);
2045int rtl8xxxu_write16_clear(struct rtl8xxxu_priv *priv, u16 addr, u16 bits);
2046int rtl8xxxu_write32_set(struct rtl8xxxu_priv *priv, u16 addr, u32 bits);
2047int rtl8xxxu_write32_clear(struct rtl8xxxu_priv *priv, u16 addr, u32 bits);
2048int rtl8xxxu_write32_mask(struct rtl8xxxu_priv *priv, u16 addr,
2049			  u32 mask, u32 val);
2050
2051u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
2052			enum rtl8xxxu_rfpath path, u8 reg);
2053int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
2054			 enum rtl8xxxu_rfpath path, u8 reg, u32 data);
2055int rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv *priv,
2056			      enum rtl8xxxu_rfpath path, u8 reg,
2057			      u32 mask, u32 val);
2058void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2059			u32 *backup, int count);
2060void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2061			   u32 *backup, int count);
2062void rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv,
2063			    const u32 *reg, u32 *backup);
2064void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
2065			       const u32 *reg, u32 *backup);
2066void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
2067			   bool path_a_on);
2068void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
2069			      const u32 *regs, u32 *backup);
2070void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok,
2071				int result[][8], int candidate, bool tx_only);
2072void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok,
2073				int result[][8], int candidate, bool tx_only);
2074int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2075			 const struct rtl8xxxu_rfregval *table,
2076			 enum rtl8xxxu_rfpath path);
2077int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2078			   const struct rtl8xxxu_reg32val *array);
2079int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name);
2080void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv);
2081void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor);
2082void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor);
2083void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv);
2084int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv);
2085int rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data);
2086int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv);
2087void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv);
2088int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv);
2089void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start);
2090void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv);
2091void rtl8188f_phy_lc_calibrate(struct rtl8xxxu_priv *priv);
2092int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv);
2093int rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv,
2094			  struct h2c_cmd *h2c, int len);
2095int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv);
2096void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv);
2097int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv);
2098void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv);
2099void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv);
2100void rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv,
2101				int channel, bool ht40);
2102void rtl8188f_channel_to_group(int channel, int *group, int *cck_group);
2103void rtl8188f_set_tx_power(struct rtl8xxxu_priv *priv,
2104			   int channel, bool ht40);
2105void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw);
2106void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw);
2107void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv);
2108void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv);
2109void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
2110			       u32 ramask, u8 rateid, int sgi, int txbw_40mhz, u8 macid);
2111void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
2112				    u32 ramask, u8 rateid, int sgi, int txbw_40mhz, u8 macid);
2113void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
2114				  u8 macid, u8 role, bool connect);
2115void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
2116				  u8 macid, u8 role, bool connect);
2117void rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi);
2118void rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi);
2119void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv);
2120void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv);
2121void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv);
2122void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv);
2123void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv);
2124int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb);
2125int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb);
2126void rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv *priv,
2127				 struct ieee80211_rx_status *rx_status,
2128				 struct rtl8723au_phy_stats *phy_stats,
2129				 u32 rxmcs, struct ieee80211_hdr *hdr,
2130				 bool crc_icv_err);
2131void jaguar2_rx_parse_phystats(struct rtl8xxxu_priv *priv,
2132			       struct ieee80211_rx_status *rx_status,
2133			       struct rtl8723au_phy_stats *phy_stats,
2134			       u32 rxmcs, struct ieee80211_hdr *hdr,
2135			       bool crc_icv_err);
2136int rtl8xxxu_gen2_channel_to_group(int channel);
2137bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
2138				 int result[][8], int c1, int c2);
2139bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv,
2140				      int result[][8], int c1, int c2);
2141void rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
2142			     struct ieee80211_tx_info *tx_info,
2143			     struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
2144			     bool short_preamble, bool ampdu_enable,
2145			     u32 rts_rate, u8 macid);
2146void rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
2147			     struct ieee80211_tx_info *tx_info,
2148			     struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi,
2149			     bool short_preamble, bool ampdu_enable,
2150			     u32 rts_rate, u8 macid);
2151void rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
2152			     struct ieee80211_tx_info *tx_info,
2153			     struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi,
2154			     bool short_preamble, bool ampdu_enable,
2155			     u32 rts_rate, u8 macid);
2156void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
2157			   u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5);
2158void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv);
2159void rtl8723a_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap);
2160void rtl8188f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap);
2161s8 rtl8723a_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats);
2162void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt,
2163			       u8 rate, u8 sgi, u8 bw);
2164void rtl8188e_ra_info_init_all(struct rtl8xxxu_ra_info *ra);
2165void rtl8188e_handle_ra_tx_report2(struct rtl8xxxu_priv *priv, struct sk_buff *skb);
2166
2167extern struct rtl8xxxu_fileops rtl8192fu_fops;
2168extern struct rtl8xxxu_fileops rtl8710bu_fops;
2169extern struct rtl8xxxu_fileops rtl8188fu_fops;
2170extern struct rtl8xxxu_fileops rtl8188eu_fops;
2171extern struct rtl8xxxu_fileops rtl8192cu_fops;
2172extern struct rtl8xxxu_fileops rtl8192eu_fops;
2173extern struct rtl8xxxu_fileops rtl8723au_fops;
2174extern struct rtl8xxxu_fileops rtl8723bu_fops;