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core.c
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linux-6.19.14/drivers/net/wireless/realtek/rtl8xxxu/core.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * RTL8XXXU mac80211 USB driver 4 * 5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 6 * 7 * Portions, notably calibration code: 8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 9 * 10 * This driver was written as a replacement for the vendor provided 11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in 12 * their programming interface, I have started adding support for 13 * additional 8xxx chips like the 8192cu, 8188cus, etc. 14 */ 15 16#include <linux/firmware.h> 17#include "regs.h" 18#include "rtl8xxxu.h" 19 20#define DRIVER_NAME "rtl8xxxu" 21 22int rtl8xxxu_debug; 23static bool rtl8xxxu_dma_aggregation; 24static int rtl8xxxu_dma_agg_timeout = -1; 25static int rtl8xxxu_dma_agg_pages = -1; 26 27MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@gmail.com>"); 28MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver"); 29MODULE_LICENSE("GPL"); 30MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin"); 31MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin"); 32MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin"); 33MODULE_FIRMWARE("rtlwifi/rtl8188eufw.bin"); 34MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin"); 35MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin"); 36MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin"); 37MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin"); 38MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin"); 39MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin"); 40MODULE_FIRMWARE("rtlwifi/rtl8188fufw.bin"); 41MODULE_FIRMWARE("rtlwifi/rtl8710bufw_SMIC.bin"); 42MODULE_FIRMWARE("rtlwifi/rtl8710bufw_UMC.bin"); 43MODULE_FIRMWARE("rtlwifi/rtl8192fufw.bin"); 44 45module_param_named(debug, rtl8xxxu_debug, int, 0600); 46MODULE_PARM_DESC(debug, "Set debug mask"); 47module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600); 48MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation"); 49module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600); 50MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)"); 51module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600); 52MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)"); 53 54#define USB_VENDOR_ID_REALTEK 0x0bda 55#define RTL8XXXU_RX_URBS 32 56#define RTL8XXXU_RX_URB_PENDING_WATER 8 57#define RTL8XXXU_TX_URBS 64 58#define RTL8XXXU_TX_URB_LOW_WATER 25 59#define RTL8XXXU_TX_URB_HIGH_WATER 32 60 61static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, 62 struct rtl8xxxu_rx_urb *rx_urb); 63 64static struct ieee80211_rate rtl8xxxu_rates[] = { 65 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 }, 66 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 }, 67 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 }, 68 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 }, 69 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 }, 70 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 }, 71 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 }, 72 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 }, 73 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 }, 74 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 }, 75 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 }, 76 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 }, 77}; 78 79static struct ieee80211_channel rtl8xxxu_channels_2g[] = { 80 { .band = NL80211_BAND_2GHZ, .center_freq = 2412, 81 .hw_value = 1, .max_power = 30 }, 82 { .band = NL80211_BAND_2GHZ, .center_freq = 2417, 83 .hw_value = 2, .max_power = 30 }, 84 { .band = NL80211_BAND_2GHZ, .center_freq = 2422, 85 .hw_value = 3, .max_power = 30 }, 86 { .band = NL80211_BAND_2GHZ, .center_freq = 2427, 87 .hw_value = 4, .max_power = 30 }, 88 { .band = NL80211_BAND_2GHZ, .center_freq = 2432, 89 .hw_value = 5, .max_power = 30 }, 90 { .band = NL80211_BAND_2GHZ, .center_freq = 2437, 91 .hw_value = 6, .max_power = 30 }, 92 { .band = NL80211_BAND_2GHZ, .center_freq = 2442, 93 .hw_value = 7, .max_power = 30 }, 94 { .band = NL80211_BAND_2GHZ, .center_freq = 2447, 95 .hw_value = 8, .max_power = 30 }, 96 { .band = NL80211_BAND_2GHZ, .center_freq = 2452, 97 .hw_value = 9, .max_power = 30 }, 98 { .band = NL80211_BAND_2GHZ, .center_freq = 2457, 99 .hw_value = 10, .max_power = 30 }, 100 { .band = NL80211_BAND_2GHZ, .center_freq = 2462, 101 .hw_value = 11, .max_power = 30 }, 102 { .band = NL80211_BAND_2GHZ, .center_freq = 2467, 103 .hw_value = 12, .max_power = 30 }, 104 { .band = NL80211_BAND_2GHZ, .center_freq = 2472, 105 .hw_value = 13, .max_power = 30 }, 106 { .band = NL80211_BAND_2GHZ, .center_freq = 2484, 107 .hw_value = 14, .max_power = 30 } 108}; 109 110static struct ieee80211_supported_band rtl8xxxu_supported_band = { 111 .channels = rtl8xxxu_channels_2g, 112 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g), 113 .bitrates = rtl8xxxu_rates, 114 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates), 115}; 116 117static const struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = { 118 {0x800, 0x80040000}, {0x804, 0x00000003}, 119 {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, 120 {0x810, 0x10001331}, {0x814, 0x020c3d10}, 121 {0x818, 0x02200385}, {0x81c, 0x00000000}, 122 {0x820, 0x01000100}, {0x824, 0x00390004}, 123 {0x828, 0x00000000}, {0x82c, 0x00000000}, 124 {0x830, 0x00000000}, {0x834, 0x00000000}, 125 {0x838, 0x00000000}, {0x83c, 0x00000000}, 126 {0x840, 0x00010000}, {0x844, 0x00000000}, 127 {0x848, 0x00000000}, {0x84c, 0x00000000}, 128 {0x850, 0x00000000}, {0x854, 0x00000000}, 129 {0x858, 0x569a569a}, {0x85c, 0x001b25a4}, 130 {0x860, 0x66f60110}, {0x864, 0x061f0130}, 131 {0x868, 0x00000000}, {0x86c, 0x32323200}, 132 {0x870, 0x07000760}, {0x874, 0x22004000}, 133 {0x878, 0x00000808}, {0x87c, 0x00000000}, 134 {0x880, 0xc0083070}, {0x884, 0x000004d5}, 135 {0x888, 0x00000000}, {0x88c, 0xccc000c0}, 136 {0x890, 0x00000800}, {0x894, 0xfffffffe}, 137 {0x898, 0x40302010}, {0x89c, 0x00706050}, 138 {0x900, 0x00000000}, {0x904, 0x00000023}, 139 {0x908, 0x00000000}, {0x90c, 0x81121111}, 140 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, 141 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, 142 {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, 143 {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, 144 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, 145 {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, 146 {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, 147 {0xa78, 0x00000900}, 148 {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, 149 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, 150 {0xc10, 0x08800000}, {0xc14, 0x40000100}, 151 {0xc18, 0x08800000}, {0xc1c, 0x40000100}, 152 {0xc20, 0x00000000}, {0xc24, 0x00000000}, 153 {0xc28, 0x00000000}, {0xc2c, 0x00000000}, 154 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af}, 155 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, 156 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, 157 {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, 158 {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, 159 {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, 160 {0xc60, 0x00000000}, {0xc64, 0x7112848b}, 161 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, 162 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db}, 163 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, 164 {0xc80, 0x40000100}, {0xc84, 0x20f60000}, 165 {0xc88, 0x40000100}, {0xc8c, 0x20200000}, 166 {0xc90, 0x00121820}, {0xc94, 0x00000000}, 167 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, 168 {0xca0, 0x00000000}, {0xca4, 0x00000080}, 169 {0xca8, 0x00000000}, {0xcac, 0x00000000}, 170 {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, 171 {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, 172 {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, 173 {0xcc8, 0x00000000}, {0xccc, 0x00000000}, 174 {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, 175 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, 176 {0xce0, 0x00222222}, {0xce4, 0x00000000}, 177 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, 178 {0xd00, 0x00080740}, {0xd04, 0x00020401}, 179 {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, 180 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, 181 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, 182 {0xd30, 0x00000000}, {0xd34, 0x80608000}, 183 {0xd38, 0x00000000}, {0xd3c, 0x00027293}, 184 {0xd40, 0x00000000}, {0xd44, 0x00000000}, 185 {0xd48, 0x00000000}, {0xd4c, 0x00000000}, 186 {0xd50, 0x6437140a}, {0xd54, 0x00000000}, 187 {0xd58, 0x00000000}, {0xd5c, 0x30032064}, 188 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, 189 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, 190 {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, 191 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, 192 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, 193 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, 194 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, 195 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, 196 {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, 197 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, 198 {0xe44, 0x01004800}, {0xe48, 0xfb000000}, 199 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, 200 {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, 201 {0xe5c, 0x28160d05}, {0xe60, 0x00000008}, 202 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0}, 203 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0}, 204 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0}, 205 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0}, 206 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0}, 207 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0}, 208 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0}, 209 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0}, 210 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 211 {0xf00, 0x00000300}, 212 {0xffff, 0xffffffff}, 213}; 214 215static const struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = { 216 {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, 217 {0x800, 0x80040002}, {0x804, 0x00000003}, 218 {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, 219 {0x810, 0x10000330}, {0x814, 0x020c3d10}, 220 {0x818, 0x02200385}, {0x81c, 0x00000000}, 221 {0x820, 0x01000100}, {0x824, 0x00390004}, 222 {0x828, 0x01000100}, {0x82c, 0x00390004}, 223 {0x830, 0x27272727}, {0x834, 0x27272727}, 224 {0x838, 0x27272727}, {0x83c, 0x27272727}, 225 {0x840, 0x00010000}, {0x844, 0x00010000}, 226 {0x848, 0x27272727}, {0x84c, 0x27272727}, 227 {0x850, 0x00000000}, {0x854, 0x00000000}, 228 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4}, 229 {0x860, 0x66e60230}, {0x864, 0x061f0130}, 230 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27}, 231 {0x870, 0x07000700}, {0x874, 0x22184000}, 232 {0x878, 0x08080808}, {0x87c, 0x00000000}, 233 {0x880, 0xc0083070}, {0x884, 0x000004d5}, 234 {0x888, 0x00000000}, {0x88c, 0xcc0000c0}, 235 {0x890, 0x00000800}, {0x894, 0xfffffffe}, 236 {0x898, 0x40302010}, {0x89c, 0x00706050}, 237 {0x900, 0x00000000}, {0x904, 0x00000023}, 238 {0x908, 0x00000000}, {0x90c, 0x81121313}, 239 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, 240 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, 241 {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, 242 {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, 243 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, 244 {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, 245 {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, 246 {0xc00, 0x48071d40}, {0xc04, 0x03a05633}, 247 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, 248 {0xc10, 0x08800000}, {0xc14, 0x40000100}, 249 {0xc18, 0x08800000}, {0xc1c, 0x40000100}, 250 {0xc20, 0x00000000}, {0xc24, 0x00000000}, 251 {0xc28, 0x00000000}, {0xc2c, 0x00000000}, 252 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf}, 253 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, 254 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, 255 {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, 256 {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, 257 {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, 258 {0xc60, 0x00000000}, {0xc64, 0x5116848b}, 259 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, 260 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b}, 261 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612}, 262 {0xc80, 0x40000100}, {0xc84, 0x20f60000}, 263 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000}, 264 {0xc90, 0x00121820}, {0xc94, 0x00000000}, 265 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, 266 {0xca0, 0x00000000}, {0xca4, 0x00000080}, 267 {0xca8, 0x00000000}, {0xcac, 0x00000000}, 268 {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, 269 {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, 270 {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, 271 {0xcc8, 0x00000000}, {0xccc, 0x00000000}, 272 {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, 273 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, 274 {0xce0, 0x00222222}, {0xce4, 0x00000000}, 275 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, 276 {0xd00, 0x00080740}, {0xd04, 0x00020403}, 277 {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, 278 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, 279 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, 280 {0xd30, 0x00000000}, {0xd34, 0x80608000}, 281 {0xd38, 0x00000000}, {0xd3c, 0x00027293}, 282 {0xd40, 0x00000000}, {0xd44, 0x00000000}, 283 {0xd48, 0x00000000}, {0xd4c, 0x00000000}, 284 {0xd50, 0x6437140a}, {0xd54, 0x00000000}, 285 {0xd58, 0x00000000}, {0xd5c, 0x30032064}, 286 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, 287 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, 288 {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, 289 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, 290 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, 291 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, 292 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, 293 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, 294 {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, 295 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, 296 {0xe44, 0x01004800}, {0xe48, 0xfb000000}, 297 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, 298 {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, 299 {0xe5c, 0x28160d05}, {0xe60, 0x00000010}, 300 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4}, 301 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4}, 302 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4}, 303 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4}, 304 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4}, 305 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4}, 306 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4}, 307 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4}, 308 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 309 {0xf00, 0x00000300}, 310 {0xffff, 0xffffffff}, 311}; 312 313static const struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = { 314 {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, 315 {0x040, 0x000c0004}, {0x800, 0x80040000}, 316 {0x804, 0x00000001}, {0x808, 0x0000fc00}, 317 {0x80c, 0x0000000a}, {0x810, 0x10005388}, 318 {0x814, 0x020c3d10}, {0x818, 0x02200385}, 319 {0x81c, 0x00000000}, {0x820, 0x01000100}, 320 {0x824, 0x00390204}, {0x828, 0x00000000}, 321 {0x82c, 0x00000000}, {0x830, 0x00000000}, 322 {0x834, 0x00000000}, {0x838, 0x00000000}, 323 {0x83c, 0x00000000}, {0x840, 0x00010000}, 324 {0x844, 0x00000000}, {0x848, 0x00000000}, 325 {0x84c, 0x00000000}, {0x850, 0x00000000}, 326 {0x854, 0x00000000}, {0x858, 0x569a569a}, 327 {0x85c, 0x001b25a4}, {0x860, 0x66e60230}, 328 {0x864, 0x061f0130}, {0x868, 0x00000000}, 329 {0x86c, 0x20202000}, {0x870, 0x03000300}, 330 {0x874, 0x22004000}, {0x878, 0x00000808}, 331 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070}, 332 {0x884, 0x000004d5}, {0x888, 0x00000000}, 333 {0x88c, 0xccc000c0}, {0x890, 0x00000800}, 334 {0x894, 0xfffffffe}, {0x898, 0x40302010}, 335 {0x89c, 0x00706050}, {0x900, 0x00000000}, 336 {0x904, 0x00000023}, {0x908, 0x00000000}, 337 {0x90c, 0x81121111}, {0xa00, 0x00d047c8}, 338 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300}, 339 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78}, 340 {0xa14, 0x11144028}, {0xa18, 0x00881117}, 341 {0xa1c, 0x89140f00}, {0xa20, 0x15160000}, 342 {0xa24, 0x070b0f12}, {0xa28, 0x00000104}, 343 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00}, 344 {0xa74, 0x00000007}, {0xc00, 0x48071d40}, 345 {0xc04, 0x03a05611}, {0xc08, 0x000000e4}, 346 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000}, 347 {0xc14, 0x40000100}, {0xc18, 0x08800000}, 348 {0xc1c, 0x40000100}, {0xc20, 0x00000000}, 349 {0xc24, 0x00000000}, {0xc28, 0x00000000}, 350 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44}, 351 {0xc34, 0x469652cf}, {0xc38, 0x49795994}, 352 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f}, 353 {0xc44, 0x000100b7}, {0xc48, 0xec020107}, 354 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e}, 355 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f}, 356 {0xc5c, 0x433c0094}, {0xc60, 0x00000000}, 357 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff}, 358 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d}, 359 {0xc74, 0x018610db}, {0xc78, 0x0000001f}, 360 {0xc7c, 0x00b91612}, {0xc80, 0x24000090}, 361 {0xc84, 0x20f60000}, {0xc88, 0x24000090}, 362 {0xc8c, 0x20200000}, {0xc90, 0x00121820}, 363 {0xc94, 0x00000000}, {0xc98, 0x00121820}, 364 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000}, 365 {0xca4, 0x00000080}, {0xca8, 0x00000000}, 366 {0xcac, 0x00000000}, {0xcb0, 0x00000000}, 367 {0xcb4, 0x00000000}, {0xcb8, 0x00000000}, 368 {0xcbc, 0x28000000}, {0xcc0, 0x00000000}, 369 {0xcc4, 0x00000000}, {0xcc8, 0x00000000}, 370 {0xccc, 0x00000000}, {0xcd0, 0x00000000}, 371 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427}, 372 {0xcdc, 0x00766932}, {0xce0, 0x00222222}, 373 {0xce4, 0x00000000}, {0xce8, 0x37644302}, 374 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740}, 375 {0xd04, 0x00020401}, {0xd08, 0x0000907f}, 376 {0xd0c, 0x20010201}, {0xd10, 0xa0633333}, 377 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b}, 378 {0xd2c, 0xcc979975}, {0xd30, 0x00000000}, 379 {0xd34, 0x80608000}, {0xd38, 0x00000000}, 380 {0xd3c, 0x00027293}, {0xd40, 0x00000000}, 381 {0xd44, 0x00000000}, {0xd48, 0x00000000}, 382 {0xd4c, 0x00000000}, {0xd50, 0x6437140a}, 383 {0xd54, 0x00000000}, {0xd58, 0x00000000}, 384 {0xd5c, 0x30032064}, {0xd60, 0x4653de68}, 385 {0xd64, 0x04518a3c}, {0xd68, 0x00002101}, 386 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e}, 387 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24}, 388 {0xe00, 0x24242424}, {0xe04, 0x24242424}, 389 {0xe08, 0x03902024}, {0xe10, 0x24242424}, 390 {0xe14, 0x24242424}, {0xe18, 0x24242424}, 391 {0xe1c, 0x24242424}, {0xe28, 0x00000000}, 392 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f}, 393 {0xe38, 0x02140102}, {0xe3c, 0x681604c2}, 394 {0xe40, 0x01007c00}, {0xe44, 0x01004800}, 395 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1}, 396 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f}, 397 {0xe58, 0x02140102}, {0xe5c, 0x28160d05}, 398 {0xe60, 0x00000008}, {0xe68, 0x001b25a4}, 399 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0}, 400 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0}, 401 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0}, 402 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0}, 403 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0}, 404 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0}, 405 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0}, 406 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448}, 407 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 408 {0xf00, 0x00000300}, 409 {0xffff, 0xffffffff}, 410}; 411 412static const struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = { 413 {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, 414 {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, 415 {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, 416 {0xc78, 0x7a060001}, {0xc78, 0x79070001}, 417 {0xc78, 0x78080001}, {0xc78, 0x77090001}, 418 {0xc78, 0x760a0001}, {0xc78, 0x750b0001}, 419 {0xc78, 0x740c0001}, {0xc78, 0x730d0001}, 420 {0xc78, 0x720e0001}, {0xc78, 0x710f0001}, 421 {0xc78, 0x70100001}, {0xc78, 0x6f110001}, 422 {0xc78, 0x6e120001}, {0xc78, 0x6d130001}, 423 {0xc78, 0x6c140001}, {0xc78, 0x6b150001}, 424 {0xc78, 0x6a160001}, {0xc78, 0x69170001}, 425 {0xc78, 0x68180001}, {0xc78, 0x67190001}, 426 {0xc78, 0x661a0001}, {0xc78, 0x651b0001}, 427 {0xc78, 0x641c0001}, {0xc78, 0x631d0001}, 428 {0xc78, 0x621e0001}, {0xc78, 0x611f0001}, 429 {0xc78, 0x60200001}, {0xc78, 0x49210001}, 430 {0xc78, 0x48220001}, {0xc78, 0x47230001}, 431 {0xc78, 0x46240001}, {0xc78, 0x45250001}, 432 {0xc78, 0x44260001}, {0xc78, 0x43270001}, 433 {0xc78, 0x42280001}, {0xc78, 0x41290001}, 434 {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, 435 {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, 436 {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, 437 {0xc78, 0x21300001}, {0xc78, 0x20310001}, 438 {0xc78, 0x06320001}, {0xc78, 0x05330001}, 439 {0xc78, 0x04340001}, {0xc78, 0x03350001}, 440 {0xc78, 0x02360001}, {0xc78, 0x01370001}, 441 {0xc78, 0x00380001}, {0xc78, 0x00390001}, 442 {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, 443 {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, 444 {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, 445 {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, 446 {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, 447 {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, 448 {0xc78, 0x7a460001}, {0xc78, 0x79470001}, 449 {0xc78, 0x78480001}, {0xc78, 0x77490001}, 450 {0xc78, 0x764a0001}, {0xc78, 0x754b0001}, 451 {0xc78, 0x744c0001}, {0xc78, 0x734d0001}, 452 {0xc78, 0x724e0001}, {0xc78, 0x714f0001}, 453 {0xc78, 0x70500001}, {0xc78, 0x6f510001}, 454 {0xc78, 0x6e520001}, {0xc78, 0x6d530001}, 455 {0xc78, 0x6c540001}, {0xc78, 0x6b550001}, 456 {0xc78, 0x6a560001}, {0xc78, 0x69570001}, 457 {0xc78, 0x68580001}, {0xc78, 0x67590001}, 458 {0xc78, 0x665a0001}, {0xc78, 0x655b0001}, 459 {0xc78, 0x645c0001}, {0xc78, 0x635d0001}, 460 {0xc78, 0x625e0001}, {0xc78, 0x615f0001}, 461 {0xc78, 0x60600001}, {0xc78, 0x49610001}, 462 {0xc78, 0x48620001}, {0xc78, 0x47630001}, 463 {0xc78, 0x46640001}, {0xc78, 0x45650001}, 464 {0xc78, 0x44660001}, {0xc78, 0x43670001}, 465 {0xc78, 0x42680001}, {0xc78, 0x41690001}, 466 {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, 467 {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, 468 {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, 469 {0xc78, 0x21700001}, {0xc78, 0x20710001}, 470 {0xc78, 0x06720001}, {0xc78, 0x05730001}, 471 {0xc78, 0x04740001}, {0xc78, 0x03750001}, 472 {0xc78, 0x02760001}, {0xc78, 0x01770001}, 473 {0xc78, 0x00780001}, {0xc78, 0x00790001}, 474 {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, 475 {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, 476 {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, 477 {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, 478 {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, 479 {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, 480 {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, 481 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, 482 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, 483 {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, 484 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, 485 {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, 486 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, 487 {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, 488 {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, 489 {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, 490 {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, 491 {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, 492 {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, 493 {0xffff, 0xffffffff} 494}; 495 496static const struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = { 497 {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, 498 {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, 499 {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, 500 {0xc78, 0x7b060001}, {0xc78, 0x7b070001}, 501 {0xc78, 0x7b080001}, {0xc78, 0x7a090001}, 502 {0xc78, 0x790a0001}, {0xc78, 0x780b0001}, 503 {0xc78, 0x770c0001}, {0xc78, 0x760d0001}, 504 {0xc78, 0x750e0001}, {0xc78, 0x740f0001}, 505 {0xc78, 0x73100001}, {0xc78, 0x72110001}, 506 {0xc78, 0x71120001}, {0xc78, 0x70130001}, 507 {0xc78, 0x6f140001}, {0xc78, 0x6e150001}, 508 {0xc78, 0x6d160001}, {0xc78, 0x6c170001}, 509 {0xc78, 0x6b180001}, {0xc78, 0x6a190001}, 510 {0xc78, 0x691a0001}, {0xc78, 0x681b0001}, 511 {0xc78, 0x671c0001}, {0xc78, 0x661d0001}, 512 {0xc78, 0x651e0001}, {0xc78, 0x641f0001}, 513 {0xc78, 0x63200001}, {0xc78, 0x62210001}, 514 {0xc78, 0x61220001}, {0xc78, 0x60230001}, 515 {0xc78, 0x46240001}, {0xc78, 0x45250001}, 516 {0xc78, 0x44260001}, {0xc78, 0x43270001}, 517 {0xc78, 0x42280001}, {0xc78, 0x41290001}, 518 {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, 519 {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, 520 {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, 521 {0xc78, 0x21300001}, {0xc78, 0x20310001}, 522 {0xc78, 0x06320001}, {0xc78, 0x05330001}, 523 {0xc78, 0x04340001}, {0xc78, 0x03350001}, 524 {0xc78, 0x02360001}, {0xc78, 0x01370001}, 525 {0xc78, 0x00380001}, {0xc78, 0x00390001}, 526 {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, 527 {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, 528 {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, 529 {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, 530 {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, 531 {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, 532 {0xc78, 0x7b460001}, {0xc78, 0x7b470001}, 533 {0xc78, 0x7b480001}, {0xc78, 0x7a490001}, 534 {0xc78, 0x794a0001}, {0xc78, 0x784b0001}, 535 {0xc78, 0x774c0001}, {0xc78, 0x764d0001}, 536 {0xc78, 0x754e0001}, {0xc78, 0x744f0001}, 537 {0xc78, 0x73500001}, {0xc78, 0x72510001}, 538 {0xc78, 0x71520001}, {0xc78, 0x70530001}, 539 {0xc78, 0x6f540001}, {0xc78, 0x6e550001}, 540 {0xc78, 0x6d560001}, {0xc78, 0x6c570001}, 541 {0xc78, 0x6b580001}, {0xc78, 0x6a590001}, 542 {0xc78, 0x695a0001}, {0xc78, 0x685b0001}, 543 {0xc78, 0x675c0001}, {0xc78, 0x665d0001}, 544 {0xc78, 0x655e0001}, {0xc78, 0x645f0001}, 545 {0xc78, 0x63600001}, {0xc78, 0x62610001}, 546 {0xc78, 0x61620001}, {0xc78, 0x60630001}, 547 {0xc78, 0x46640001}, {0xc78, 0x45650001}, 548 {0xc78, 0x44660001}, {0xc78, 0x43670001}, 549 {0xc78, 0x42680001}, {0xc78, 0x41690001}, 550 {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, 551 {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, 552 {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, 553 {0xc78, 0x21700001}, {0xc78, 0x20710001}, 554 {0xc78, 0x06720001}, {0xc78, 0x05730001}, 555 {0xc78, 0x04740001}, {0xc78, 0x03750001}, 556 {0xc78, 0x02760001}, {0xc78, 0x01770001}, 557 {0xc78, 0x00780001}, {0xc78, 0x00790001}, 558 {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, 559 {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, 560 {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, 561 {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, 562 {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, 563 {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, 564 {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, 565 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, 566 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, 567 {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, 568 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, 569 {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, 570 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, 571 {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, 572 {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, 573 {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, 574 {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, 575 {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, 576 {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, 577 {0xffff, 0xffffffff} 578}; 579 580static const struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = { 581 { /* RF_A */ 582 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1, 583 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2, 584 .lssiparm = REG_FPGA0_XA_LSSI_PARM, 585 .hspiread = REG_HSPI_XA_READBACK, 586 .lssiread = REG_FPGA0_XA_LSSI_READBACK, 587 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL, 588 }, 589 { /* RF_B */ 590 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1, 591 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2, 592 .lssiparm = REG_FPGA0_XB_LSSI_PARM, 593 .hspiread = REG_HSPI_XB_READBACK, 594 .lssiread = REG_FPGA0_XB_LSSI_READBACK, 595 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL, 596 }, 597}; 598 599const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = { 600 REG_OFDM0_XA_RX_IQ_IMBALANCE, 601 REG_OFDM0_XB_RX_IQ_IMBALANCE, 602 REG_OFDM0_ENERGY_CCA_THRES, 603 REG_OFDM0_AGC_RSSI_TABLE, 604 REG_OFDM0_XA_TX_IQ_IMBALANCE, 605 REG_OFDM0_XB_TX_IQ_IMBALANCE, 606 REG_OFDM0_XC_TX_AFE, 607 REG_OFDM0_XD_TX_AFE, 608 REG_OFDM0_RX_IQ_EXT_ANTA 609}; 610 611u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr) 612{ 613 struct usb_device *udev = priv->udev; 614 int len; 615 u8 data; 616 617 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 618 addr |= 0x8000; 619 620 mutex_lock(&priv->usb_buf_mutex); 621 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 622 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 623 addr, 0, &priv->usb_buf.val8, sizeof(u8), 624 RTW_USB_CONTROL_MSG_TIMEOUT); 625 data = priv->usb_buf.val8; 626 mutex_unlock(&priv->usb_buf_mutex); 627 628 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 629 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n", 630 __func__, addr, data, len); 631 return data; 632} 633 634u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr) 635{ 636 struct usb_device *udev = priv->udev; 637 int len; 638 u16 data; 639 640 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 641 addr |= 0x8000; 642 643 mutex_lock(&priv->usb_buf_mutex); 644 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 645 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 646 addr, 0, &priv->usb_buf.val16, sizeof(u16), 647 RTW_USB_CONTROL_MSG_TIMEOUT); 648 data = le16_to_cpu(priv->usb_buf.val16); 649 mutex_unlock(&priv->usb_buf_mutex); 650 651 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 652 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n", 653 __func__, addr, data, len); 654 return data; 655} 656 657u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr) 658{ 659 struct usb_device *udev = priv->udev; 660 int len; 661 u32 data; 662 663 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 664 addr |= 0x8000; 665 666 mutex_lock(&priv->usb_buf_mutex); 667 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 668 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 669 addr, 0, &priv->usb_buf.val32, sizeof(u32), 670 RTW_USB_CONTROL_MSG_TIMEOUT); 671 data = le32_to_cpu(priv->usb_buf.val32); 672 mutex_unlock(&priv->usb_buf_mutex); 673 674 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 675 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n", 676 __func__, addr, data, len); 677 return data; 678} 679 680int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val) 681{ 682 struct usb_device *udev = priv->udev; 683 int ret; 684 685 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 686 addr |= 0x8000; 687 688 mutex_lock(&priv->usb_buf_mutex); 689 priv->usb_buf.val8 = val; 690 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 691 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 692 addr, 0, &priv->usb_buf.val8, sizeof(u8), 693 RTW_USB_CONTROL_MSG_TIMEOUT); 694 695 mutex_unlock(&priv->usb_buf_mutex); 696 697 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 698 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n", 699 __func__, addr, val); 700 return ret; 701} 702 703int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val) 704{ 705 struct usb_device *udev = priv->udev; 706 int ret; 707 708 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 709 addr |= 0x8000; 710 711 mutex_lock(&priv->usb_buf_mutex); 712 priv->usb_buf.val16 = cpu_to_le16(val); 713 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 714 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 715 addr, 0, &priv->usb_buf.val16, sizeof(u16), 716 RTW_USB_CONTROL_MSG_TIMEOUT); 717 mutex_unlock(&priv->usb_buf_mutex); 718 719 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 720 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n", 721 __func__, addr, val); 722 return ret; 723} 724 725int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val) 726{ 727 struct usb_device *udev = priv->udev; 728 int ret; 729 730 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 731 addr |= 0x8000; 732 733 mutex_lock(&priv->usb_buf_mutex); 734 priv->usb_buf.val32 = cpu_to_le32(val); 735 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 736 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 737 addr, 0, &priv->usb_buf.val32, sizeof(u32), 738 RTW_USB_CONTROL_MSG_TIMEOUT); 739 mutex_unlock(&priv->usb_buf_mutex); 740 741 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 742 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n", 743 __func__, addr, val); 744 return ret; 745} 746 747int rtl8xxxu_write8_set(struct rtl8xxxu_priv *priv, u16 addr, u8 bits) 748{ 749 u8 val8; 750 751 val8 = rtl8xxxu_read8(priv, addr); 752 val8 |= bits; 753 return rtl8xxxu_write8(priv, addr, val8); 754} 755 756int rtl8xxxu_write8_clear(struct rtl8xxxu_priv *priv, u16 addr, u8 bits) 757{ 758 u8 val8; 759 760 val8 = rtl8xxxu_read8(priv, addr); 761 val8 &= ~bits; 762 return rtl8xxxu_write8(priv, addr, val8); 763} 764 765int rtl8xxxu_write16_set(struct rtl8xxxu_priv *priv, u16 addr, u16 bits) 766{ 767 u16 val16; 768 769 val16 = rtl8xxxu_read16(priv, addr); 770 val16 |= bits; 771 return rtl8xxxu_write16(priv, addr, val16); 772} 773 774int rtl8xxxu_write16_clear(struct rtl8xxxu_priv *priv, u16 addr, u16 bits) 775{ 776 u16 val16; 777 778 val16 = rtl8xxxu_read16(priv, addr); 779 val16 &= ~bits; 780 return rtl8xxxu_write16(priv, addr, val16); 781} 782 783int rtl8xxxu_write32_set(struct rtl8xxxu_priv *priv, u16 addr, u32 bits) 784{ 785 u32 val32; 786 787 val32 = rtl8xxxu_read32(priv, addr); 788 val32 |= bits; 789 return rtl8xxxu_write32(priv, addr, val32); 790} 791 792int rtl8xxxu_write32_clear(struct rtl8xxxu_priv *priv, u16 addr, u32 bits) 793{ 794 u32 val32; 795 796 val32 = rtl8xxxu_read32(priv, addr); 797 val32 &= ~bits; 798 return rtl8xxxu_write32(priv, addr, val32); 799} 800 801int rtl8xxxu_write32_mask(struct rtl8xxxu_priv *priv, u16 addr, 802 u32 mask, u32 val) 803{ 804 u32 orig, new, shift; 805 806 shift = __ffs(mask); 807 808 orig = rtl8xxxu_read32(priv, addr); 809 new = (orig & ~mask) | ((val << shift) & mask); 810 return rtl8xxxu_write32(priv, addr, new); 811} 812 813int rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv *priv, 814 enum rtl8xxxu_rfpath path, u8 reg, 815 u32 mask, u32 val) 816{ 817 u32 orig, new, shift; 818 819 shift = __ffs(mask); 820 821 orig = rtl8xxxu_read_rfreg(priv, path, reg); 822 new = (orig & ~mask) | ((val << shift) & mask); 823 return rtl8xxxu_write_rfreg(priv, path, reg, new); 824} 825 826static int 827rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len) 828{ 829 struct usb_device *udev = priv->udev; 830 int blocksize = priv->fops->writeN_block_size; 831 int ret, i, count, remainder; 832 833 count = len / blocksize; 834 remainder = len % blocksize; 835 836 for (i = 0; i < count; i++) { 837 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 838 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 839 addr, 0, buf, blocksize, 840 RTW_USB_CONTROL_MSG_TIMEOUT); 841 if (ret != blocksize) 842 goto write_error; 843 844 addr += blocksize; 845 buf += blocksize; 846 } 847 848 if (remainder) { 849 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 850 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 851 addr, 0, buf, remainder, 852 RTW_USB_CONTROL_MSG_TIMEOUT); 853 if (ret != remainder) 854 goto write_error; 855 } 856 857 return len; 858 859write_error: 860 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 861 dev_info(&udev->dev, 862 "%s: Failed to write block at addr: %04x size: %04x\n", 863 __func__, addr, blocksize); 864 return -EAGAIN; 865} 866 867u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, 868 enum rtl8xxxu_rfpath path, u8 reg) 869{ 870 u32 hssia, val32, retval; 871 872 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); 873 if (path != RF_A) 874 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2); 875 else 876 val32 = hssia; 877 878 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK; 879 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT); 880 val32 |= FPGA0_HSSI_PARM2_EDGE_READ; 881 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ; 882 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); 883 884 udelay(10); 885 886 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32); 887 udelay(100); 888 889 hssia |= FPGA0_HSSI_PARM2_EDGE_READ; 890 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); 891 udelay(10); 892 893 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1); 894 if (val32 & FPGA0_HSSI_PARM1_PI) 895 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread); 896 else 897 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread); 898 899 retval &= 0xfffff; 900 901 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ) 902 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", 903 __func__, reg, retval); 904 return retval; 905} 906 907/* 908 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can 909 * have write issues in high temperature conditions. We may have to 910 * retry writing them. 911 */ 912int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, 913 enum rtl8xxxu_rfpath path, u8 reg, u32 data) 914{ 915 int ret, retval; 916 u32 dataaddr, val32; 917 918 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE) 919 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", 920 __func__, reg, data); 921 922 data &= FPGA0_LSSI_PARM_DATA_MASK; 923 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data; 924 925 if (priv->rtl_chip == RTL8192E) { 926 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 927 val32 &= ~0x20000; 928 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 929 } 930 931 /* Use XB for path B */ 932 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr); 933 if (ret != sizeof(dataaddr)) 934 retval = -EIO; 935 else 936 retval = 0; 937 938 udelay(1); 939 940 if (priv->rtl_chip == RTL8192E) { 941 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 942 val32 |= 0x20000; 943 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 944 } 945 946 return retval; 947} 948 949static int 950rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len) 951{ 952 struct device *dev = &priv->udev->dev; 953 int mbox_nr, retry, retval = 0; 954 int mbox_reg, mbox_ext_reg; 955 u8 val8; 956 957 mutex_lock(&priv->h2c_mutex); 958 959 mbox_nr = priv->next_mbox; 960 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); 961 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2); 962 963 /* 964 * MBOX ready? 965 */ 966 retry = 100; 967 do { 968 val8 = rtl8xxxu_read8(priv, REG_HMTFR); 969 if (!(val8 & BIT(mbox_nr))) 970 break; 971 } while (retry--); 972 973 if (!retry) { 974 dev_info(dev, "%s: Mailbox busy\n", __func__); 975 retval = -EBUSY; 976 goto error; 977 } 978 979 /* 980 * Need to swap as it's being swapped again by rtl8xxxu_write16/32() 981 */ 982 if (len > sizeof(u32)) { 983 rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext)); 984 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 985 dev_info(dev, "H2C_EXT %04x\n", 986 le16_to_cpu(h2c->raw.ext)); 987 } 988 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); 989 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 990 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); 991 992 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; 993 994error: 995 mutex_unlock(&priv->h2c_mutex); 996 return retval; 997} 998 999int 1000rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len) 1001{ 1002 struct device *dev = &priv->udev->dev; 1003 int mbox_nr, retry, retval = 0; 1004 int mbox_reg, mbox_ext_reg; 1005 u8 val8; 1006 1007 mutex_lock(&priv->h2c_mutex); 1008 1009 mbox_nr = priv->next_mbox; 1010 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); 1011 mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4); 1012 1013 /* 1014 * MBOX ready? 1015 */ 1016 retry = 100; 1017 do { 1018 val8 = rtl8xxxu_read8(priv, REG_HMTFR); 1019 if (!(val8 & BIT(mbox_nr))) 1020 break; 1021 } while (retry--); 1022 1023 if (!retry) { 1024 dev_info(dev, "%s: Mailbox busy\n", __func__); 1025 retval = -EBUSY; 1026 goto error; 1027 } 1028 1029 /* 1030 * Need to swap as it's being swapped again by rtl8xxxu_write16/32() 1031 */ 1032 if (len > sizeof(u32)) { 1033 rtl8xxxu_write32(priv, mbox_ext_reg, 1034 le32_to_cpu(h2c->raw_wide.ext)); 1035 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 1036 dev_info(dev, "H2C_EXT %08x\n", 1037 le32_to_cpu(h2c->raw_wide.ext)); 1038 } 1039 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); 1040 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 1041 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); 1042 1043 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; 1044 1045error: 1046 mutex_unlock(&priv->h2c_mutex); 1047 return retval; 1048} 1049 1050void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv) 1051{ 1052 u8 val8; 1053 u32 val32; 1054 1055 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); 1056 val8 |= BIT(0) | BIT(3); 1057 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8); 1058 1059 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); 1060 val32 &= ~(BIT(4) | BIT(5)); 1061 val32 |= BIT(3); 1062 if (priv->rf_paths == 2) { 1063 val32 &= ~(BIT(20) | BIT(21)); 1064 val32 |= BIT(19); 1065 } 1066 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); 1067 1068 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1069 val32 &= ~OFDM_RF_PATH_TX_MASK; 1070 if (priv->tx_paths == 2) 1071 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B; 1072 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C) 1073 val32 |= OFDM_RF_PATH_TX_B; 1074 else 1075 val32 |= OFDM_RF_PATH_TX_A; 1076 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1077 1078 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1079 val32 &= ~FPGA_RF_MODE_JAPAN; 1080 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1081 1082 if (priv->rf_paths == 2) 1083 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0); 1084 else 1085 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0); 1086 1087 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95); 1088 if (priv->rf_paths == 2) 1089 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95); 1090 1091 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 1092} 1093 1094void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv) 1095{ 1096 u8 sps0; 1097 u32 val32; 1098 1099 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); 1100 1101 /* RF RX code for preamble power saving */ 1102 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); 1103 val32 &= ~(BIT(3) | BIT(4) | BIT(5)); 1104 if (priv->rf_paths == 2) 1105 val32 &= ~(BIT(19) | BIT(20) | BIT(21)); 1106 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); 1107 1108 /* Disable TX for four paths */ 1109 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1110 val32 &= ~OFDM_RF_PATH_TX_MASK; 1111 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1112 1113 /* Enable power saving */ 1114 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1115 val32 |= FPGA_RF_MODE_JAPAN; 1116 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1117 1118 /* AFE control register to power down bits [30:22] */ 1119 if (priv->rf_paths == 2) 1120 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0); 1121 else 1122 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0); 1123 1124 /* Power down RF module */ 1125 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); 1126 if (priv->rf_paths == 2) 1127 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0); 1128 1129 sps0 &= ~(BIT(0) | BIT(3)); 1130 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0); 1131} 1132 1133static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv) 1134{ 1135 u8 val8; 1136 1137 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2); 1138 val8 &= ~BIT(6); 1139 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8); 1140 1141 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64); 1142 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2); 1143 val8 &= ~BIT(0); 1144 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8); 1145} 1146 1147static void rtl8xxxu_start_tx_beacon(struct rtl8xxxu_priv *priv) 1148{ 1149 u8 val8; 1150 1151 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2); 1152 val8 |= EN_BCNQ_DL >> 16; 1153 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8); 1154 1155 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x80); 1156 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2); 1157 val8 &= 0xF0; 1158 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8); 1159} 1160 1161 1162/* 1163 * The rtl8723a has 3 channel groups for its efuse settings. It only 1164 * supports the 2.4GHz band, so channels 1 - 14: 1165 * group 0: channels 1 - 3 1166 * group 1: channels 4 - 9 1167 * group 2: channels 10 - 14 1168 * 1169 * Note: We index from 0 in the code 1170 */ 1171static int rtl8xxxu_gen1_channel_to_group(int channel) 1172{ 1173 int group; 1174 1175 if (channel < 4) 1176 group = 0; 1177 else if (channel < 10) 1178 group = 1; 1179 else 1180 group = 2; 1181 1182 return group; 1183} 1184 1185/* 1186 * Valid for rtl8723bu and rtl8192eu 1187 */ 1188int rtl8xxxu_gen2_channel_to_group(int channel) 1189{ 1190 int group; 1191 1192 if (channel < 3) 1193 group = 0; 1194 else if (channel < 6) 1195 group = 1; 1196 else if (channel < 9) 1197 group = 2; 1198 else if (channel < 12) 1199 group = 3; 1200 else 1201 group = 4; 1202 1203 return group; 1204} 1205 1206void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw) 1207{ 1208 struct rtl8xxxu_priv *priv = hw->priv; 1209 u32 val32, rsr; 1210 u8 val8, opmode; 1211 bool ht = true; 1212 int sec_ch_above, channel; 1213 int i; 1214 1215 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE); 1216 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 1217 channel = hw->conf.chandef.chan->hw_value; 1218 1219 switch (hw->conf.chandef.width) { 1220 case NL80211_CHAN_WIDTH_20_NOHT: 1221 ht = false; 1222 fallthrough; 1223 case NL80211_CHAN_WIDTH_20: 1224 opmode |= BW_OPMODE_20MHZ; 1225 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); 1226 1227 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1228 val32 &= ~FPGA_RF_MODE; 1229 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1230 1231 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1232 val32 &= ~FPGA_RF_MODE; 1233 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1234 1235 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); 1236 val32 |= FPGA0_ANALOG2_20MHZ; 1237 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); 1238 break; 1239 case NL80211_CHAN_WIDTH_40: 1240 if (hw->conf.chandef.center_freq1 > 1241 hw->conf.chandef.chan->center_freq) { 1242 sec_ch_above = 1; 1243 channel += 2; 1244 } else { 1245 sec_ch_above = 0; 1246 channel -= 2; 1247 } 1248 1249 opmode &= ~BW_OPMODE_20MHZ; 1250 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); 1251 rsr &= ~RSR_RSC_BANDWIDTH_40M; 1252 if (!sec_ch_above) 1253 rsr |= RSR_RSC_UPPER_SUB_CHANNEL; 1254 else 1255 rsr |= RSR_RSC_LOWER_SUB_CHANNEL; 1256 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr); 1257 1258 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1259 val32 |= FPGA_RF_MODE; 1260 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1261 1262 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1263 val32 |= FPGA_RF_MODE; 1264 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1265 1266 /* 1267 * Set Control channel to upper or lower. These settings 1268 * are required only for 40MHz 1269 */ 1270 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 1271 val32 &= ~CCK0_SIDEBAND; 1272 if (!sec_ch_above) 1273 val32 |= CCK0_SIDEBAND; 1274 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 1275 1276 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 1277 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ 1278 if (sec_ch_above) 1279 val32 |= OFDM_LSTF_PRIME_CH_LOW; 1280 else 1281 val32 |= OFDM_LSTF_PRIME_CH_HIGH; 1282 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 1283 1284 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); 1285 val32 &= ~FPGA0_ANALOG2_20MHZ; 1286 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); 1287 1288 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 1289 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); 1290 if (sec_ch_above) 1291 val32 |= FPGA0_PS_UPPER_CHANNEL; 1292 else 1293 val32 |= FPGA0_PS_LOWER_CHANNEL; 1294 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 1295 break; 1296 1297 default: 1298 break; 1299 } 1300 1301 for (i = RF_A; i < priv->rf_paths; i++) { 1302 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1303 val32 &= ~MODE_AG_CHANNEL_MASK; 1304 val32 |= channel; 1305 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1306 } 1307 1308 if (ht) 1309 val8 = 0x0e; 1310 else 1311 val8 = 0x0a; 1312 1313 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); 1314 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); 1315 1316 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); 1317 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); 1318 1319 for (i = RF_A; i < priv->rf_paths; i++) { 1320 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1321 val32 &= ~MODE_AG_BW_MASK; 1322 if (hw->conf.chandef.width != NL80211_CHAN_WIDTH_40) 1323 val32 |= MODE_AG_CHANNEL_20MHZ; 1324 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1325 } 1326} 1327 1328void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw) 1329{ 1330 struct rtl8xxxu_priv *priv = hw->priv; 1331 u32 val32; 1332 u8 val8, subchannel; 1333 u16 rf_mode_bw; 1334 bool ht = true; 1335 int sec_ch_above, channel; 1336 int i; 1337 1338 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL); 1339 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK; 1340 channel = hw->conf.chandef.chan->hw_value; 1341 1342/* Hack */ 1343 subchannel = 0; 1344 1345 switch (hw->conf.chandef.width) { 1346 case NL80211_CHAN_WIDTH_20_NOHT: 1347 ht = false; 1348 fallthrough; 1349 case NL80211_CHAN_WIDTH_20: 1350 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20; 1351 subchannel = 0; 1352 1353 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1354 val32 &= ~FPGA_RF_MODE; 1355 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1356 1357 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1358 val32 &= ~FPGA_RF_MODE; 1359 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1360 1361 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); 1362 val32 &= ~(BIT(30) | BIT(31)); 1363 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); 1364 1365 break; 1366 case NL80211_CHAN_WIDTH_40: 1367 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40; 1368 1369 if (hw->conf.chandef.center_freq1 > 1370 hw->conf.chandef.chan->center_freq) { 1371 sec_ch_above = 1; 1372 channel += 2; 1373 subchannel = 2; 1374 } else { 1375 sec_ch_above = 0; 1376 channel -= 2; 1377 subchannel = 1; 1378 } 1379 1380 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1381 val32 |= FPGA_RF_MODE; 1382 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1383 1384 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1385 val32 |= FPGA_RF_MODE; 1386 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1387 1388 /* 1389 * Set Control channel to upper or lower. These settings 1390 * are required only for 40MHz 1391 */ 1392 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 1393 val32 &= ~CCK0_SIDEBAND; 1394 if (!sec_ch_above) 1395 val32 |= CCK0_SIDEBAND; 1396 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 1397 1398 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 1399 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ 1400 if (sec_ch_above) 1401 val32 |= OFDM_LSTF_PRIME_CH_LOW; 1402 else 1403 val32 |= OFDM_LSTF_PRIME_CH_HIGH; 1404 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 1405 1406 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 1407 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); 1408 if (sec_ch_above) 1409 val32 |= FPGA0_PS_UPPER_CHANNEL; 1410 else 1411 val32 |= FPGA0_PS_LOWER_CHANNEL; 1412 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 1413 break; 1414 case NL80211_CHAN_WIDTH_80: 1415 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80; 1416 break; 1417 default: 1418 break; 1419 } 1420 1421 for (i = RF_A; i < priv->rf_paths; i++) { 1422 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1423 val32 &= ~MODE_AG_CHANNEL_MASK; 1424 val32 |= channel; 1425 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1426 } 1427 1428 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw); 1429 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel); 1430 1431 if (ht) 1432 val8 = 0x0e; 1433 else 1434 val8 = 0x0a; 1435 1436 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); 1437 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); 1438 1439 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); 1440 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); 1441 1442 for (i = RF_A; i < priv->rf_paths; i++) { 1443 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1444 val32 &= ~MODE_AG_BW_MASK; 1445 switch(hw->conf.chandef.width) { 1446 case NL80211_CHAN_WIDTH_80: 1447 val32 |= MODE_AG_BW_80MHZ_8723B; 1448 break; 1449 case NL80211_CHAN_WIDTH_40: 1450 val32 |= MODE_AG_BW_40MHZ_8723B; 1451 break; 1452 default: 1453 val32 |= MODE_AG_BW_20MHZ_8723B; 1454 break; 1455 } 1456 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1457 } 1458} 1459 1460void 1461rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) 1462{ 1463 struct rtl8xxxu_power_base *power_base = priv->power_base; 1464 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS]; 1465 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS]; 1466 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b; 1467 u8 val8, base; 1468 int group, i; 1469 1470 group = rtl8xxxu_gen1_channel_to_group(channel); 1471 1472 cck[0] = priv->cck_tx_power_index_A[group]; 1473 cck[1] = priv->cck_tx_power_index_B[group]; 1474 1475 if (priv->hi_pa) { 1476 if (cck[0] > 0x20) 1477 cck[0] = 0x20; 1478 if (cck[1] > 0x20) 1479 cck[1] = 0x20; 1480 } 1481 1482 ofdm[0] = priv->ht40_1s_tx_power_index_A[group]; 1483 ofdm[1] = priv->ht40_1s_tx_power_index_B[group]; 1484 1485 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a; 1486 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b; 1487 1488 mcsbase[0] = ofdm[0]; 1489 mcsbase[1] = ofdm[1]; 1490 if (!ht40) { 1491 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a; 1492 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b; 1493 } 1494 1495 if (priv->tx_paths > 1) { 1496 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a) 1497 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a; 1498 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b) 1499 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b; 1500 } 1501 1502 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) 1503 dev_info(&priv->udev->dev, 1504 "%s: Setting TX power CCK A: %02x, " 1505 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n", 1506 __func__, cck[0], cck[1], ofdm[0], ofdm[1]); 1507 1508 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) { 1509 if (cck[i] > RF6052_MAX_TX_PWR) 1510 cck[i] = RF6052_MAX_TX_PWR; 1511 if (ofdm[i] > RF6052_MAX_TX_PWR) 1512 ofdm[i] = RF6052_MAX_TX_PWR; 1513 } 1514 1515 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); 1516 val32 &= 0xffff00ff; 1517 val32 |= (cck[0] << 8); 1518 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); 1519 1520 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 1521 val32 &= 0xff; 1522 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24)); 1523 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 1524 1525 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 1526 val32 &= 0xffffff00; 1527 val32 |= cck[1]; 1528 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 1529 1530 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); 1531 val32 &= 0xff; 1532 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24)); 1533 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); 1534 1535 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 | 1536 ofdmbase[0] << 16 | ofdmbase[0] << 24; 1537 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 | 1538 ofdmbase[1] << 16 | ofdmbase[1] << 24; 1539 1540 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, 1541 ofdm_a + power_base->reg_0e00); 1542 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, 1543 ofdm_b + power_base->reg_0830); 1544 1545 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, 1546 ofdm_a + power_base->reg_0e04); 1547 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, 1548 ofdm_b + power_base->reg_0834); 1549 1550 mcs_a = mcsbase[0] | mcsbase[0] << 8 | 1551 mcsbase[0] << 16 | mcsbase[0] << 24; 1552 mcs_b = mcsbase[1] | mcsbase[1] << 8 | 1553 mcsbase[1] << 16 | mcsbase[1] << 24; 1554 1555 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, 1556 mcs_a + power_base->reg_0e10); 1557 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, 1558 mcs_b + power_base->reg_083c); 1559 1560 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, 1561 mcs_a + power_base->reg_0e14); 1562 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, 1563 mcs_b + power_base->reg_0848); 1564 1565 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, 1566 mcs_a + power_base->reg_0e18); 1567 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, 1568 mcs_b + power_base->reg_084c); 1569 1570 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, 1571 mcs_a + power_base->reg_0e1c); 1572 val8 = u32_get_bits(mcs_a + power_base->reg_0e1c, 0xff000000); 1573 for (i = 0; i < 3; i++) { 1574 base = i != 2 ? 8 : 6; 1575 val8 = max_t(int, val8 - base, 0); 1576 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8); 1577 } 1578 1579 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, 1580 mcs_b + power_base->reg_0868); 1581 val8 = u32_get_bits(mcs_b + power_base->reg_0868, 0xff000000); 1582 for (i = 0; i < 3; i++) { 1583 base = i != 2 ? 8 : 6; 1584 val8 = max_t(int, val8 - base, 0); 1585 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8); 1586 } 1587} 1588 1589static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv, 1590 enum nl80211_iftype linktype, int port_num) 1591{ 1592 u8 val8, type; 1593 1594 switch (linktype) { 1595 case NL80211_IFTYPE_UNSPECIFIED: 1596 type = MSR_LINKTYPE_NONE; 1597 break; 1598 case NL80211_IFTYPE_ADHOC: 1599 type = MSR_LINKTYPE_ADHOC; 1600 break; 1601 case NL80211_IFTYPE_STATION: 1602 type = MSR_LINKTYPE_STATION; 1603 break; 1604 case NL80211_IFTYPE_AP: 1605 type = MSR_LINKTYPE_AP; 1606 break; 1607 default: 1608 return; 1609 } 1610 1611 switch (port_num) { 1612 case 0: 1613 val8 = rtl8xxxu_read8(priv, REG_MSR) & 0x0c; 1614 val8 |= type; 1615 break; 1616 case 1: 1617 val8 = rtl8xxxu_read8(priv, REG_MSR) & 0x03; 1618 val8 |= type << 2; 1619 break; 1620 default: 1621 return; 1622 } 1623 1624 rtl8xxxu_write8(priv, REG_MSR, val8); 1625} 1626 1627static void 1628rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry) 1629{ 1630 u16 val16; 1631 1632 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) & 1633 RETRY_LIMIT_SHORT_MASK) | 1634 ((long_retry << RETRY_LIMIT_LONG_SHIFT) & 1635 RETRY_LIMIT_LONG_MASK); 1636 1637 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); 1638} 1639 1640static void 1641rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm) 1642{ 1643 u16 val16; 1644 1645 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) | 1646 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK); 1647 1648 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16); 1649} 1650 1651static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv) 1652{ 1653 struct device *dev = &priv->udev->dev; 1654 char cut = 'A' + priv->chip_cut; 1655 1656 dev_info(dev, 1657 "RTL%s rev %c (%s) romver %d, %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n", 1658 priv->chip_name, cut, priv->chip_vendor, priv->rom_rev, 1659 priv->tx_paths, priv->rx_paths, priv->ep_tx_count, 1660 priv->has_wifi, priv->has_bluetooth, priv->has_gps, 1661 priv->hi_pa); 1662 1663 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr); 1664} 1665 1666void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor) 1667{ 1668 if (vendor) { 1669 strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor)); 1670 priv->vendor_umc = 1; 1671 } else { 1672 strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor)); 1673 } 1674} 1675 1676void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor) 1677{ 1678 switch (vendor) { 1679 case SYS_CFG_VENDOR_ID_TSMC: 1680 strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor)); 1681 break; 1682 case SYS_CFG_VENDOR_ID_SMIC: 1683 strscpy(priv->chip_vendor, "SMIC", sizeof(priv->chip_vendor)); 1684 priv->vendor_smic = 1; 1685 break; 1686 case SYS_CFG_VENDOR_ID_UMC: 1687 strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor)); 1688 priv->vendor_umc = 1; 1689 break; 1690 default: 1691 strscpy(priv->chip_vendor, "unknown", sizeof(priv->chip_vendor)); 1692 } 1693} 1694 1695void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv) 1696{ 1697 u16 val16; 1698 1699 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX); 1700 1701 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) { 1702 priv->ep_tx_high_queue = 1; 1703 priv->ep_tx_count++; 1704 } 1705 1706 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) { 1707 priv->ep_tx_normal_queue = 1; 1708 priv->ep_tx_count++; 1709 } 1710 1711 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) { 1712 priv->ep_tx_low_queue = 1; 1713 priv->ep_tx_count++; 1714 } 1715} 1716 1717int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv) 1718{ 1719 struct device *dev = &priv->udev->dev; 1720 1721 switch (priv->nr_out_eps) { 1722 case 6: 1723 case 5: 1724 case 4: 1725 case 3: 1726 priv->ep_tx_low_queue = 1; 1727 priv->ep_tx_count++; 1728 fallthrough; 1729 case 2: 1730 priv->ep_tx_normal_queue = 1; 1731 priv->ep_tx_count++; 1732 fallthrough; 1733 case 1: 1734 priv->ep_tx_high_queue = 1; 1735 priv->ep_tx_count++; 1736 break; 1737 default: 1738 dev_info(dev, "Unsupported USB TX end-points\n"); 1739 return -ENOTSUPP; 1740 } 1741 1742 return 0; 1743} 1744 1745int 1746rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data) 1747{ 1748 int i; 1749 u8 val8; 1750 u32 val32; 1751 1752 /* Write Address */ 1753 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff); 1754 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2); 1755 val8 &= 0xfc; 1756 val8 |= (offset >> 8) & 0x03; 1757 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8); 1758 1759 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3); 1760 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f); 1761 1762 /* Poll for data read */ 1763 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1764 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) { 1765 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1766 if (val32 & BIT(31)) 1767 break; 1768 } 1769 1770 if (i == RTL8XXXU_MAX_REG_POLL) 1771 return -EIO; 1772 1773 udelay(50); 1774 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1775 1776 *data = val32 & 0xff; 1777 return 0; 1778} 1779 1780int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv) 1781{ 1782 struct device *dev = &priv->udev->dev; 1783 int i, ret = 0; 1784 u8 val8, word_mask, header, extheader; 1785 u16 val16, efuse_addr, offset; 1786 u32 val32; 1787 1788 val16 = rtl8xxxu_read16(priv, REG_9346CR); 1789 if (val16 & EEPROM_ENABLE) 1790 priv->has_eeprom = 1; 1791 if (val16 & EEPROM_BOOT) 1792 priv->boot_eeprom = 1; 1793 1794 if (priv->is_multi_func) { 1795 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST); 1796 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT; 1797 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32); 1798 } 1799 1800 dev_dbg(dev, "Booting from %s\n", 1801 priv->boot_eeprom ? "EEPROM" : "EFUSE"); 1802 1803 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE); 1804 1805 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */ 1806 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL); 1807 if (!(val16 & SYS_ISO_PWC_EV12V)) { 1808 val16 |= SYS_ISO_PWC_EV12V; 1809 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16); 1810 } 1811 /* Reset: 0x0000[28], default valid */ 1812 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1813 if (!(val16 & SYS_FUNC_ELDR)) { 1814 val16 |= SYS_FUNC_ELDR; 1815 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 1816 } 1817 1818 /* 1819 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid 1820 */ 1821 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); 1822 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) { 1823 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M); 1824 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16); 1825 } 1826 1827 /* Default value is 0xff */ 1828 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN); 1829 1830 efuse_addr = 0; 1831 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) { 1832 u16 map_addr; 1833 1834 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header); 1835 if (ret || header == 0xff) 1836 goto exit; 1837 1838 if ((header & 0x1f) == 0x0f) { /* extended header */ 1839 offset = (header & 0xe0) >> 5; 1840 1841 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, 1842 &extheader); 1843 if (ret) 1844 goto exit; 1845 /* All words disabled */ 1846 if ((extheader & 0x0f) == 0x0f) 1847 continue; 1848 1849 offset |= ((extheader & 0xf0) >> 1); 1850 word_mask = extheader & 0x0f; 1851 } else { 1852 offset = (header >> 4) & 0x0f; 1853 word_mask = header & 0x0f; 1854 } 1855 1856 /* Get word enable value from PG header */ 1857 1858 /* We have 8 bits to indicate validity */ 1859 map_addr = offset * 8; 1860 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { 1861 /* Check word enable condition in the section */ 1862 if (word_mask & BIT(i)) { 1863 map_addr += 2; 1864 continue; 1865 } 1866 1867 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); 1868 if (ret) 1869 goto exit; 1870 if (map_addr >= EFUSE_MAP_LEN - 1) { 1871 dev_warn(dev, "%s: Illegal map_addr (%04x), " 1872 "efuse corrupt!\n", 1873 __func__, map_addr); 1874 ret = -EINVAL; 1875 goto exit; 1876 } 1877 priv->efuse_wifi.raw[map_addr++] = val8; 1878 1879 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); 1880 if (ret) 1881 goto exit; 1882 priv->efuse_wifi.raw[map_addr++] = val8; 1883 } 1884 } 1885 1886exit: 1887 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE); 1888 1889 return ret; 1890} 1891 1892static void rtl8xxxu_dump_efuse(struct rtl8xxxu_priv *priv) 1893{ 1894 dev_info(&priv->udev->dev, 1895 "Dumping efuse for RTL%s (0x%02x bytes):\n", 1896 priv->chip_name, EFUSE_MAP_LEN); 1897 1898 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 1899 priv->efuse_wifi.raw, EFUSE_MAP_LEN, true); 1900} 1901 1902static ssize_t read_file_efuse(struct file *file, char __user *user_buf, 1903 size_t count, loff_t *ppos) 1904{ 1905 struct rtl8xxxu_priv *priv = file_inode(file)->i_private; 1906 1907 return simple_read_from_buffer(user_buf, count, ppos, 1908 priv->efuse_wifi.raw, EFUSE_MAP_LEN); 1909} 1910 1911static const struct debugfs_short_fops fops_efuse = { 1912 .read = read_file_efuse, 1913}; 1914 1915static void rtl8xxxu_debugfs_init(struct rtl8xxxu_priv *priv) 1916{ 1917 struct dentry *phydir; 1918 1919 phydir = debugfs_create_dir("rtl8xxxu", priv->hw->wiphy->debugfsdir); 1920 debugfs_create_file("efuse", 0400, phydir, priv, &fops_efuse); 1921} 1922 1923void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv) 1924{ 1925 u8 val8; 1926 u16 sys_func; 1927 1928 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 1929 val8 &= ~BIT(0); 1930 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 1931 1932 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1933 sys_func &= ~SYS_FUNC_CPU_ENABLE; 1934 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 1935 1936 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 1937 val8 |= BIT(0); 1938 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 1939 1940 sys_func |= SYS_FUNC_CPU_ENABLE; 1941 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 1942} 1943 1944static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv) 1945{ 1946 struct device *dev = &priv->udev->dev; 1947 u16 reg_mcu_fw_dl; 1948 int ret = 0, i; 1949 u32 val32; 1950 1951 if (priv->rtl_chip == RTL8710B) 1952 reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B; 1953 else 1954 reg_mcu_fw_dl = REG_MCU_FW_DL; 1955 1956 /* Poll checksum report */ 1957 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { 1958 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); 1959 if (val32 & MCU_FW_DL_CSUM_REPORT) 1960 break; 1961 } 1962 1963 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { 1964 dev_warn(dev, "Firmware checksum poll timed out\n"); 1965 ret = -EAGAIN; 1966 goto exit; 1967 } 1968 1969 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); 1970 val32 |= MCU_FW_DL_READY; 1971 val32 &= ~MCU_WINT_INIT_READY; 1972 rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32); 1973 1974 /* 1975 * Reset the 8051 in order for the firmware to start running, 1976 * otherwise it won't come up on the 8192eu 1977 */ 1978 priv->fops->reset_8051(priv); 1979 1980 /* Wait for firmware to become ready */ 1981 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { 1982 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); 1983 if (val32 & MCU_WINT_INIT_READY) 1984 break; 1985 1986 udelay(100); 1987 } 1988 1989 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { 1990 dev_warn(dev, "Firmware failed to start\n"); 1991 ret = -EAGAIN; 1992 goto exit; 1993 } 1994 1995 /* 1996 * Init H2C command 1997 */ 1998 if (priv->fops->init_reg_hmtfr) 1999 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f); 2000exit: 2001 return ret; 2002} 2003 2004static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv) 2005{ 2006 int pages, remainder, i, ret; 2007 u16 reg_fw_start_address; 2008 u16 reg_mcu_fw_dl; 2009 u8 val8; 2010 u16 val16; 2011 u32 val32; 2012 u8 *fwptr; 2013 2014 if (priv->rtl_chip == RTL8192F) 2015 reg_fw_start_address = REG_FW_START_ADDRESS_8192F; 2016 else 2017 reg_fw_start_address = REG_FW_START_ADDRESS; 2018 2019 if (priv->rtl_chip == RTL8710B) { 2020 reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B; 2021 } else { 2022 reg_mcu_fw_dl = REG_MCU_FW_DL; 2023 2024 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1); 2025 val8 |= 4; 2026 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8); 2027 2028 /* 8051 enable */ 2029 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2030 val16 |= SYS_FUNC_CPU_ENABLE; 2031 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2032 } 2033 2034 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl); 2035 if (val8 & MCU_FW_RAM_SEL) { 2036 dev_info(&priv->udev->dev, 2037 "Firmware is already running, resetting the MCU.\n"); 2038 rtl8xxxu_write8(priv, reg_mcu_fw_dl, 0x00); 2039 priv->fops->reset_8051(priv); 2040 } 2041 2042 /* MCU firmware download enable */ 2043 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl); 2044 val8 |= MCU_FW_DL_ENABLE; 2045 rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8); 2046 2047 /* 8051 reset */ 2048 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); 2049 val32 &= ~BIT(19); 2050 rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32); 2051 2052 if (priv->rtl_chip == RTL8710B) { 2053 /* We must set 0x8090[8]=1 before download FW. */ 2054 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 1); 2055 val8 |= BIT(0); 2056 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 1, val8); 2057 } 2058 2059 /* Reset firmware download checksum */ 2060 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl); 2061 val8 |= MCU_FW_DL_CSUM_REPORT; 2062 rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8); 2063 2064 pages = priv->fw_size / RTL_FW_PAGE_SIZE; 2065 remainder = priv->fw_size % RTL_FW_PAGE_SIZE; 2066 2067 fwptr = priv->fw_data->data; 2068 2069 for (i = 0; i < pages; i++) { 2070 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8; 2071 val8 |= i; 2072 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8); 2073 2074 ret = rtl8xxxu_writeN(priv, reg_fw_start_address, 2075 fwptr, RTL_FW_PAGE_SIZE); 2076 if (ret != RTL_FW_PAGE_SIZE) { 2077 ret = -EAGAIN; 2078 goto fw_abort; 2079 } 2080 2081 fwptr += RTL_FW_PAGE_SIZE; 2082 } 2083 2084 if (remainder) { 2085 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8; 2086 val8 |= i; 2087 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8); 2088 ret = rtl8xxxu_writeN(priv, reg_fw_start_address, 2089 fwptr, remainder); 2090 if (ret != remainder) { 2091 ret = -EAGAIN; 2092 goto fw_abort; 2093 } 2094 } 2095 2096 ret = 0; 2097fw_abort: 2098 /* MCU firmware download disable */ 2099 val16 = rtl8xxxu_read16(priv, reg_mcu_fw_dl); 2100 val16 &= ~MCU_FW_DL_ENABLE; 2101 rtl8xxxu_write16(priv, reg_mcu_fw_dl, val16); 2102 2103 return ret; 2104} 2105 2106int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name) 2107{ 2108 struct device *dev = &priv->udev->dev; 2109 const struct firmware *fw; 2110 int ret = 0; 2111 u16 signature; 2112 2113 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name); 2114 if (request_firmware(&fw, fw_name, &priv->udev->dev)) { 2115 dev_warn(dev, "request_firmware(%s) failed\n", fw_name); 2116 ret = -EAGAIN; 2117 goto exit; 2118 } 2119 if (!fw) { 2120 dev_warn(dev, "Firmware data not available\n"); 2121 ret = -EINVAL; 2122 goto exit; 2123 } 2124 2125 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL); 2126 if (!priv->fw_data) { 2127 ret = -ENOMEM; 2128 goto exit; 2129 } 2130 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header); 2131 2132 signature = le16_to_cpu(priv->fw_data->signature); 2133 switch (signature & 0xfff0) { 2134 case 0x92e0: 2135 case 0x92c0: 2136 case 0x88e0: 2137 case 0x88c0: 2138 case 0x5300: 2139 case 0x2300: 2140 case 0x88f0: 2141 case 0x10b0: 2142 case 0x92f0: 2143 break; 2144 default: 2145 ret = -EINVAL; 2146 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n", 2147 __func__, signature); 2148 } 2149 2150 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n", 2151 le16_to_cpu(priv->fw_data->major_version), 2152 priv->fw_data->minor_version, signature); 2153 2154exit: 2155 release_firmware(fw); 2156 return ret; 2157} 2158 2159void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv) 2160{ 2161 u16 val16; 2162 int i = 100; 2163 2164 /* Inform 8051 to perform reset */ 2165 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20); 2166 2167 for (i = 100; i > 0; i--) { 2168 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2169 2170 if (!(val16 & SYS_FUNC_CPU_ENABLE)) { 2171 dev_dbg(&priv->udev->dev, 2172 "%s: Firmware self reset success!\n", __func__); 2173 break; 2174 } 2175 udelay(50); 2176 } 2177 2178 if (!i) { 2179 /* Force firmware reset */ 2180 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2181 val16 &= ~SYS_FUNC_CPU_ENABLE; 2182 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2183 } 2184} 2185 2186static int 2187rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv) 2188{ 2189 const struct rtl8xxxu_reg8val *array = priv->fops->mactable; 2190 int i, ret; 2191 u16 reg; 2192 u8 val; 2193 2194 for (i = 0; ; i++) { 2195 reg = array[i].reg; 2196 val = array[i].val; 2197 2198 if (reg == 0xffff && val == 0xff) 2199 break; 2200 2201 ret = rtl8xxxu_write8(priv, reg, val); 2202 if (ret != 1) { 2203 dev_warn(&priv->udev->dev, 2204 "Failed to initialize MAC " 2205 "(reg: %04x, val %02x)\n", reg, val); 2206 return -EAGAIN; 2207 } 2208 } 2209 2210 switch (priv->rtl_chip) { 2211 case RTL8188C: 2212 case RTL8188R: 2213 case RTL8191C: 2214 case RTL8192C: 2215 case RTL8723A: 2216 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a); 2217 break; 2218 case RTL8188E: 2219 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0707); 2220 break; 2221 default: 2222 break; 2223 } 2224 2225 return 0; 2226} 2227 2228int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, 2229 const struct rtl8xxxu_reg32val *array) 2230{ 2231 int i, ret; 2232 u16 reg; 2233 u32 val; 2234 2235 for (i = 0; ; i++) { 2236 reg = array[i].reg; 2237 val = array[i].val; 2238 2239 if (reg == 0xffff && val == 0xffffffff) 2240 break; 2241 2242 ret = rtl8xxxu_write32(priv, reg, val); 2243 if (ret != sizeof(val)) { 2244 dev_warn(&priv->udev->dev, 2245 "Failed to initialize PHY\n"); 2246 return -EAGAIN; 2247 } 2248 udelay(1); 2249 } 2250 2251 return 0; 2252} 2253 2254void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv) 2255{ 2256 u8 val8, ldoa15, ldov12d, lpldo, ldohci12; 2257 u16 val16; 2258 u32 val32; 2259 2260 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); 2261 udelay(2); 2262 val8 |= AFE_PLL_320_ENABLE; 2263 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); 2264 udelay(2); 2265 2266 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff); 2267 udelay(2); 2268 2269 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2270 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB; 2271 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2272 2273 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); 2274 val32 &= ~AFE_XTAL_RF_GATE; 2275 if (priv->has_bluetooth) 2276 val32 &= ~AFE_XTAL_BT_GATE; 2277 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); 2278 2279 /* 6. 0x1f[7:0] = 0x07 */ 2280 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; 2281 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); 2282 2283 if (priv->hi_pa) 2284 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table); 2285 else if (priv->tx_paths == 2) 2286 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table); 2287 else 2288 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table); 2289 2290 if (priv->rtl_chip == RTL8188R && priv->hi_pa && 2291 priv->vendor_umc && priv->chip_cut == 1) 2292 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50); 2293 2294 if (priv->hi_pa) 2295 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table); 2296 else 2297 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table); 2298 2299 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF; 2300 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT); 2301 ldohci12 = 0x57; 2302 lpldo = 1; 2303 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15; 2304 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32); 2305} 2306 2307/* 2308 * Most of this is black magic retrieved from the old rtl8723au driver 2309 */ 2310static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv) 2311{ 2312 u32 val32; 2313 2314 priv->fops->init_phy_bb(priv); 2315 2316 if (priv->tx_paths == 1 && priv->rx_paths == 2) { 2317 /* 2318 * For 1T2R boards, patch the registers. 2319 * 2320 * It looks like 8191/2 1T2R boards use path B for TX 2321 */ 2322 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO); 2323 val32 &= ~(BIT(0) | BIT(1)); 2324 val32 |= BIT(1); 2325 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32); 2326 2327 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO); 2328 val32 &= ~0x300033; 2329 val32 |= 0x200022; 2330 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32); 2331 2332 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); 2333 val32 &= ~CCK0_AFE_RX_MASK; 2334 val32 &= 0x00ffffff; 2335 val32 |= 0x40000000; 2336 val32 |= CCK0_AFE_RX_ANT_B; 2337 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); 2338 2339 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 2340 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); 2341 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B | 2342 OFDM_RF_PATH_TX_B); 2343 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 2344 2345 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1); 2346 val32 &= ~(BIT(4) | BIT(5)); 2347 val32 |= BIT(4); 2348 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32); 2349 2350 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON); 2351 val32 &= ~(BIT(27) | BIT(26)); 2352 val32 |= BIT(27); 2353 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32); 2354 2355 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON); 2356 val32 &= ~(BIT(27) | BIT(26)); 2357 val32 |= BIT(27); 2358 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32); 2359 2360 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON); 2361 val32 &= ~(BIT(27) | BIT(26)); 2362 val32 |= BIT(27); 2363 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32); 2364 2365 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON); 2366 val32 &= ~(BIT(27) | BIT(26)); 2367 val32 |= BIT(27); 2368 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32); 2369 2370 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX); 2371 val32 &= ~(BIT(27) | BIT(26)); 2372 val32 |= BIT(27); 2373 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32); 2374 } 2375 2376 if (priv->fops->set_crystal_cap) 2377 priv->fops->set_crystal_cap(priv, priv->default_crystal_cap); 2378 2379 if (priv->rtl_chip == RTL8192E) 2380 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb); 2381 2382 return 0; 2383} 2384 2385static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv, 2386 const struct rtl8xxxu_rfregval *array, 2387 enum rtl8xxxu_rfpath path) 2388{ 2389 int i, ret; 2390 u8 reg; 2391 u32 val; 2392 2393 for (i = 0; ; i++) { 2394 reg = array[i].reg; 2395 val = array[i].val; 2396 2397 if (reg == 0xff && val == 0xffffffff) 2398 break; 2399 2400 switch (reg) { 2401 case 0xfe: 2402 msleep(50); 2403 continue; 2404 case 0xfd: 2405 mdelay(5); 2406 continue; 2407 case 0xfc: 2408 mdelay(1); 2409 continue; 2410 case 0xfb: 2411 udelay(50); 2412 continue; 2413 case 0xfa: 2414 udelay(5); 2415 continue; 2416 case 0xf9: 2417 udelay(1); 2418 continue; 2419 } 2420 2421 ret = rtl8xxxu_write_rfreg(priv, path, reg, val); 2422 if (ret) { 2423 dev_warn(&priv->udev->dev, 2424 "Failed to initialize RF\n"); 2425 return -EAGAIN; 2426 } 2427 udelay(1); 2428 } 2429 2430 return 0; 2431} 2432 2433int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, 2434 const struct rtl8xxxu_rfregval *table, 2435 enum rtl8xxxu_rfpath path) 2436{ 2437 u32 val32; 2438 u16 val16, rfsi_rfenv; 2439 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2; 2440 2441 switch (path) { 2442 case RF_A: 2443 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL; 2444 reg_int_oe = REG_FPGA0_XA_RF_INT_OE; 2445 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2; 2446 break; 2447 case RF_B: 2448 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL; 2449 reg_int_oe = REG_FPGA0_XB_RF_INT_OE; 2450 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2; 2451 break; 2452 default: 2453 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n", 2454 __func__, path + 'A'); 2455 return -EINVAL; 2456 } 2457 /* For path B, use XB */ 2458 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl); 2459 rfsi_rfenv &= FPGA0_RF_RFENV; 2460 2461 /* 2462 * These two we might be able to optimize into one 2463 */ 2464 val32 = rtl8xxxu_read32(priv, reg_int_oe); 2465 val32 |= BIT(20); /* 0x10 << 16 */ 2466 rtl8xxxu_write32(priv, reg_int_oe, val32); 2467 udelay(1); 2468 2469 val32 = rtl8xxxu_read32(priv, reg_int_oe); 2470 val32 |= BIT(4); 2471 rtl8xxxu_write32(priv, reg_int_oe, val32); 2472 udelay(1); 2473 2474 /* 2475 * These two we might be able to optimize into one 2476 */ 2477 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); 2478 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN; 2479 rtl8xxxu_write32(priv, reg_hssi_parm2, val32); 2480 udelay(1); 2481 2482 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); 2483 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN; 2484 rtl8xxxu_write32(priv, reg_hssi_parm2, val32); 2485 udelay(1); 2486 2487 rtl8xxxu_init_rf_regs(priv, table, path); 2488 2489 /* For path B, use XB */ 2490 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl); 2491 val16 &= ~FPGA0_RF_RFENV; 2492 val16 |= rfsi_rfenv; 2493 rtl8xxxu_write16(priv, reg_sw_ctrl, val16); 2494 2495 return 0; 2496} 2497 2498static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data) 2499{ 2500 int ret = -EBUSY; 2501 int count = 0; 2502 u32 value; 2503 2504 value = LLT_OP_WRITE | address << 8 | data; 2505 2506 rtl8xxxu_write32(priv, REG_LLT_INIT, value); 2507 2508 do { 2509 value = rtl8xxxu_read32(priv, REG_LLT_INIT); 2510 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) { 2511 ret = 0; 2512 break; 2513 } 2514 } while (count++ < 20); 2515 2516 return ret; 2517} 2518 2519int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv) 2520{ 2521 int ret; 2522 int i, last_entry; 2523 u8 last_tx_page; 2524 2525 last_tx_page = priv->fops->total_page_num; 2526 2527 if (priv->fops->last_llt_entry) 2528 last_entry = priv->fops->last_llt_entry; 2529 else 2530 last_entry = 255; 2531 2532 for (i = 0; i < last_tx_page; i++) { 2533 ret = rtl8xxxu_llt_write(priv, i, i + 1); 2534 if (ret) 2535 goto exit; 2536 } 2537 2538 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff); 2539 if (ret) 2540 goto exit; 2541 2542 /* Mark remaining pages as a ring buffer */ 2543 for (i = last_tx_page + 1; i < last_entry; i++) { 2544 ret = rtl8xxxu_llt_write(priv, i, (i + 1)); 2545 if (ret) 2546 goto exit; 2547 } 2548 2549 /* Let last entry point to the start entry of ring buffer */ 2550 ret = rtl8xxxu_llt_write(priv, last_entry, last_tx_page + 1); 2551 if (ret) 2552 goto exit; 2553 2554exit: 2555 return ret; 2556} 2557 2558int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv) 2559{ 2560 u32 val32; 2561 int ret = 0; 2562 int i; 2563 2564 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); 2565 val32 |= AUTO_LLT_INIT_LLT; 2566 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32); 2567 2568 for (i = 500; i; i--) { 2569 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); 2570 if (!(val32 & AUTO_LLT_INIT_LLT)) 2571 break; 2572 usleep_range(2, 4); 2573 } 2574 2575 if (!i) { 2576 ret = -EBUSY; 2577 dev_warn(&priv->udev->dev, "LLT table init failed\n"); 2578 } 2579 2580 return ret; 2581} 2582 2583static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv) 2584{ 2585 u16 val16, hi, lo; 2586 u16 hiq, mgq, bkq, beq, viq, voq; 2587 int hip, mgp, bkp, bep, vip, vop; 2588 int ret = 0; 2589 u32 val32; 2590 2591 switch (priv->ep_tx_count) { 2592 case 1: 2593 if (priv->ep_tx_high_queue) { 2594 hi = TRXDMA_QUEUE_HIGH; 2595 } else if (priv->ep_tx_low_queue) { 2596 hi = TRXDMA_QUEUE_LOW; 2597 } else if (priv->ep_tx_normal_queue) { 2598 hi = TRXDMA_QUEUE_NORMAL; 2599 } else { 2600 hi = 0; 2601 ret = -EINVAL; 2602 } 2603 2604 hiq = hi; 2605 mgq = hi; 2606 bkq = hi; 2607 beq = hi; 2608 viq = hi; 2609 voq = hi; 2610 2611 hip = 0; 2612 mgp = 0; 2613 bkp = 0; 2614 bep = 0; 2615 vip = 0; 2616 vop = 0; 2617 break; 2618 case 2: 2619 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) { 2620 hi = TRXDMA_QUEUE_HIGH; 2621 lo = TRXDMA_QUEUE_LOW; 2622 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) { 2623 hi = TRXDMA_QUEUE_NORMAL; 2624 lo = TRXDMA_QUEUE_LOW; 2625 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) { 2626 hi = TRXDMA_QUEUE_HIGH; 2627 lo = TRXDMA_QUEUE_NORMAL; 2628 } else { 2629 ret = -EINVAL; 2630 hi = 0; 2631 lo = 0; 2632 } 2633 2634 hiq = hi; 2635 mgq = hi; 2636 bkq = lo; 2637 beq = lo; 2638 viq = hi; 2639 voq = hi; 2640 2641 hip = 0; 2642 mgp = 0; 2643 bkp = 1; 2644 bep = 1; 2645 vip = 0; 2646 vop = 0; 2647 break; 2648 case 3: 2649 beq = TRXDMA_QUEUE_LOW; 2650 bkq = TRXDMA_QUEUE_LOW; 2651 viq = TRXDMA_QUEUE_NORMAL; 2652 voq = TRXDMA_QUEUE_HIGH; 2653 mgq = TRXDMA_QUEUE_HIGH; 2654 hiq = TRXDMA_QUEUE_HIGH; 2655 2656 hip = hiq ^ 3; 2657 mgp = mgq ^ 3; 2658 bkp = bkq ^ 3; 2659 bep = beq ^ 3; 2660 vip = viq ^ 3; 2661 vop = viq ^ 3; 2662 break; 2663 default: 2664 ret = -EINVAL; 2665 } 2666 2667 /* 2668 * None of the vendor drivers are configuring the beacon 2669 * queue here .... why? 2670 */ 2671 if (!ret) { 2672 /* Only RTL8192F seems to do it like this. */ 2673 if (priv->rtl_chip == RTL8192F) { 2674 val32 = rtl8xxxu_read32(priv, REG_TRXDMA_CTRL); 2675 val32 &= 0x7; 2676 val32 |= (voq << TRXDMA_CTRL_VOQ_SHIFT_8192F) | 2677 (viq << TRXDMA_CTRL_VIQ_SHIFT_8192F) | 2678 (beq << TRXDMA_CTRL_BEQ_SHIFT_8192F) | 2679 (bkq << TRXDMA_CTRL_BKQ_SHIFT_8192F) | 2680 (mgq << TRXDMA_CTRL_MGQ_SHIFT_8192F) | 2681 (hiq << TRXDMA_CTRL_HIQ_SHIFT_8192F); 2682 rtl8xxxu_write32(priv, REG_TRXDMA_CTRL, val32); 2683 } else { 2684 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL); 2685 val16 &= 0x7; 2686 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) | 2687 (viq << TRXDMA_CTRL_VIQ_SHIFT) | 2688 (beq << TRXDMA_CTRL_BEQ_SHIFT) | 2689 (bkq << TRXDMA_CTRL_BKQ_SHIFT) | 2690 (mgq << TRXDMA_CTRL_MGQ_SHIFT) | 2691 (hiq << TRXDMA_CTRL_HIQ_SHIFT); 2692 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16); 2693 } 2694 2695 priv->pipe_out[TXDESC_QUEUE_VO] = 2696 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]); 2697 priv->pipe_out[TXDESC_QUEUE_VI] = 2698 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]); 2699 priv->pipe_out[TXDESC_QUEUE_BE] = 2700 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]); 2701 priv->pipe_out[TXDESC_QUEUE_BK] = 2702 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]); 2703 priv->pipe_out[TXDESC_QUEUE_BEACON] = 2704 usb_sndbulkpipe(priv->udev, priv->out_ep[0]); 2705 priv->pipe_out[TXDESC_QUEUE_MGNT] = 2706 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]); 2707 priv->pipe_out[TXDESC_QUEUE_HIGH] = 2708 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]); 2709 priv->pipe_out[TXDESC_QUEUE_CMD] = 2710 usb_sndbulkpipe(priv->udev, priv->out_ep[0]); 2711 } 2712 2713 return ret; 2714} 2715 2716void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok, 2717 int result[][8], int candidate, bool tx_only) 2718{ 2719 u32 oldval, x, tx0_a, reg; 2720 int y, tx0_c; 2721 u32 val32; 2722 2723 if (!iqk_ok) 2724 return; 2725 2726 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2727 oldval = val32 >> 22; 2728 2729 x = result[candidate][0]; 2730 if ((x & 0x00000200) != 0) 2731 x = x | 0xfffffc00; 2732 tx0_a = (x * oldval) >> 8; 2733 2734 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2735 val32 &= ~0x3ff; 2736 val32 |= tx0_a; 2737 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); 2738 2739 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2740 val32 &= ~BIT(31); 2741 if ((x * oldval >> 7) & 0x1) 2742 val32 |= BIT(31); 2743 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2744 2745 y = result[candidate][1]; 2746 if ((y & 0x00000200) != 0) 2747 y = y | 0xfffffc00; 2748 tx0_c = (y * oldval) >> 8; 2749 2750 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE); 2751 val32 &= ~0xf0000000; 2752 val32 |= (((tx0_c & 0x3c0) >> 6) << 28); 2753 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32); 2754 2755 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2756 val32 &= ~0x003f0000; 2757 val32 |= ((tx0_c & 0x3f) << 16); 2758 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); 2759 2760 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2761 val32 &= ~BIT(29); 2762 if ((y * oldval >> 7) & 0x1) 2763 val32 |= BIT(29); 2764 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2765 2766 if (tx_only) { 2767 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); 2768 return; 2769 } 2770 2771 reg = result[candidate][2]; 2772 2773 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); 2774 val32 &= ~0x3ff; 2775 val32 |= (reg & 0x3ff); 2776 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); 2777 2778 reg = result[candidate][3] & 0x3F; 2779 2780 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); 2781 val32 &= ~0xfc00; 2782 val32 |= ((reg << 10) & 0xfc00); 2783 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); 2784 2785 reg = (result[candidate][3] >> 6) & 0xF; 2786 2787 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA); 2788 val32 &= ~0xf0000000; 2789 val32 |= (reg << 28); 2790 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32); 2791} 2792 2793void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, 2794 int result[][8], int candidate, bool tx_only) 2795{ 2796 u32 oldval, x, tx1_a, reg; 2797 int y, tx1_c; 2798 u32 val32; 2799 2800 if (!iqk_ok) 2801 return; 2802 2803 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2804 oldval = val32 >> 22; 2805 2806 x = result[candidate][4]; 2807 if ((x & 0x00000200) != 0) 2808 x = x | 0xfffffc00; 2809 tx1_a = (x * oldval) >> 8; 2810 2811 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2812 val32 &= ~0x3ff; 2813 val32 |= tx1_a; 2814 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); 2815 2816 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2817 val32 &= ~BIT(27); 2818 if ((x * oldval >> 7) & 0x1) 2819 val32 |= BIT(27); 2820 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2821 2822 y = result[candidate][5]; 2823 if ((y & 0x00000200) != 0) 2824 y = y | 0xfffffc00; 2825 tx1_c = (y * oldval) >> 8; 2826 2827 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE); 2828 val32 &= ~0xf0000000; 2829 val32 |= (((tx1_c & 0x3c0) >> 6) << 28); 2830 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32); 2831 2832 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2833 val32 &= ~0x003f0000; 2834 val32 |= ((tx1_c & 0x3f) << 16); 2835 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); 2836 2837 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2838 val32 &= ~BIT(25); 2839 if ((y * oldval >> 7) & 0x1) 2840 val32 |= BIT(25); 2841 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2842 2843 if (tx_only) { 2844 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); 2845 return; 2846 } 2847 2848 reg = result[candidate][6]; 2849 2850 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); 2851 val32 &= ~0x3ff; 2852 val32 |= (reg & 0x3ff); 2853 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); 2854 2855 reg = result[candidate][7] & 0x3f; 2856 2857 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); 2858 val32 &= ~0xfc00; 2859 val32 |= ((reg << 10) & 0xfc00); 2860 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); 2861 2862 reg = (result[candidate][7] >> 6) & 0xf; 2863 2864 if (priv->rtl_chip == RTL8192F) { 2865 rtl8xxxu_write32_mask(priv, REG_RXIQB_EXT, 0x000000f0, reg); 2866 } else { 2867 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_RSSI_TABLE); 2868 val32 &= ~0x0000f000; 2869 val32 |= (reg << 12); 2870 rtl8xxxu_write32(priv, REG_OFDM0_AGC_RSSI_TABLE, val32); 2871 } 2872} 2873 2874#define MAX_TOLERANCE 5 2875 2876bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv, 2877 int result[][8], int c1, int c2) 2878{ 2879 u32 i, j, diff, simubitmap, bound = 0; 2880 int candidate[2] = {-1, -1}; /* for path A and path B */ 2881 bool retval = true; 2882 2883 if (priv->tx_paths > 1) 2884 bound = 8; 2885 else 2886 bound = 4; 2887 2888 simubitmap = 0; 2889 2890 for (i = 0; i < bound; i++) { 2891 diff = (result[c1][i] > result[c2][i]) ? 2892 (result[c1][i] - result[c2][i]) : 2893 (result[c2][i] - result[c1][i]); 2894 if (diff > MAX_TOLERANCE) { 2895 if ((i == 2 || i == 6) && !simubitmap) { 2896 if (result[c1][i] + result[c1][i + 1] == 0) 2897 candidate[(i / 4)] = c2; 2898 else if (result[c2][i] + result[c2][i + 1] == 0) 2899 candidate[(i / 4)] = c1; 2900 else 2901 simubitmap = simubitmap | (1 << i); 2902 } else { 2903 simubitmap = simubitmap | (1 << i); 2904 } 2905 } 2906 } 2907 2908 if (simubitmap == 0) { 2909 for (i = 0; i < (bound / 4); i++) { 2910 if (candidate[i] >= 0) { 2911 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 2912 result[3][j] = result[candidate[i]][j]; 2913 retval = false; 2914 } 2915 } 2916 return retval; 2917 } else if (!(simubitmap & 0x0f)) { 2918 /* path A OK */ 2919 for (i = 0; i < 4; i++) 2920 result[3][i] = result[c1][i]; 2921 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) { 2922 /* path B OK */ 2923 for (i = 4; i < 8; i++) 2924 result[3][i] = result[c1][i]; 2925 } 2926 2927 return false; 2928} 2929 2930bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, 2931 int result[][8], int c1, int c2) 2932{ 2933 u32 i, j, diff, simubitmap, bound = 0; 2934 int candidate[2] = {-1, -1}; /* for path A and path B */ 2935 int tmp1, tmp2; 2936 bool retval = true; 2937 2938 if (priv->tx_paths > 1) 2939 bound = 8; 2940 else 2941 bound = 4; 2942 2943 simubitmap = 0; 2944 2945 for (i = 0; i < bound; i++) { 2946 if (i & 1) { 2947 if ((result[c1][i] & 0x00000200)) 2948 tmp1 = result[c1][i] | 0xfffffc00; 2949 else 2950 tmp1 = result[c1][i]; 2951 2952 if ((result[c2][i]& 0x00000200)) 2953 tmp2 = result[c2][i] | 0xfffffc00; 2954 else 2955 tmp2 = result[c2][i]; 2956 } else { 2957 tmp1 = result[c1][i]; 2958 tmp2 = result[c2][i]; 2959 } 2960 2961 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); 2962 2963 if (diff > MAX_TOLERANCE) { 2964 if ((i == 2 || i == 6) && !simubitmap) { 2965 if (result[c1][i] + result[c1][i + 1] == 0) 2966 candidate[(i / 4)] = c2; 2967 else if (result[c2][i] + result[c2][i + 1] == 0) 2968 candidate[(i / 4)] = c1; 2969 else 2970 simubitmap = simubitmap | (1 << i); 2971 } else { 2972 simubitmap = simubitmap | (1 << i); 2973 } 2974 } 2975 } 2976 2977 if (simubitmap == 0) { 2978 for (i = 0; i < (bound / 4); i++) { 2979 if (candidate[i] >= 0) { 2980 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 2981 result[3][j] = result[candidate[i]][j]; 2982 retval = false; 2983 } 2984 } 2985 return retval; 2986 } else { 2987 if (!(simubitmap & 0x03)) { 2988 /* path A TX OK */ 2989 for (i = 0; i < 2; i++) 2990 result[3][i] = result[c1][i]; 2991 } 2992 2993 if (!(simubitmap & 0x0c)) { 2994 /* path A RX OK */ 2995 for (i = 2; i < 4; i++) 2996 result[3][i] = result[c1][i]; 2997 } 2998 2999 if (!(simubitmap & 0x30) && priv->tx_paths > 1) { 3000 /* path B TX OK */ 3001 for (i = 4; i < 6; i++) 3002 result[3][i] = result[c1][i]; 3003 } 3004 3005 if (!(simubitmap & 0xc0) && priv->tx_paths > 1) { 3006 /* path B RX OK */ 3007 for (i = 6; i < 8; i++) 3008 result[3][i] = result[c1][i]; 3009 } 3010 } 3011 3012 return false; 3013} 3014 3015void 3016rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup) 3017{ 3018 int i; 3019 3020 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) 3021 backup[i] = rtl8xxxu_read8(priv, reg[i]); 3022 3023 backup[i] = rtl8xxxu_read32(priv, reg[i]); 3024} 3025 3026void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, 3027 const u32 *reg, u32 *backup) 3028{ 3029 int i; 3030 3031 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) 3032 rtl8xxxu_write8(priv, reg[i], backup[i]); 3033 3034 rtl8xxxu_write32(priv, reg[i], backup[i]); 3035} 3036 3037void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 3038 u32 *backup, int count) 3039{ 3040 int i; 3041 3042 for (i = 0; i < count; i++) 3043 backup[i] = rtl8xxxu_read32(priv, regs[i]); 3044} 3045 3046void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 3047 u32 *backup, int count) 3048{ 3049 int i; 3050 3051 for (i = 0; i < count; i++) 3052 rtl8xxxu_write32(priv, regs[i], backup[i]); 3053} 3054 3055 3056void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, 3057 bool path_a_on) 3058{ 3059 u32 path_on; 3060 int i; 3061 3062 if (priv->tx_paths == 1) { 3063 path_on = priv->fops->adda_1t_path_on; 3064 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init); 3065 } else { 3066 path_on = path_a_on ? priv->fops->adda_2t_path_on_a : 3067 priv->fops->adda_2t_path_on_b; 3068 3069 rtl8xxxu_write32(priv, regs[0], path_on); 3070 } 3071 3072 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++) 3073 rtl8xxxu_write32(priv, regs[i], path_on); 3074} 3075 3076void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, 3077 const u32 *regs, u32 *backup) 3078{ 3079 int i = 0; 3080 3081 rtl8xxxu_write8(priv, regs[i], 0x3f); 3082 3083 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++) 3084 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3))); 3085 3086 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5))); 3087} 3088 3089static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv) 3090{ 3091 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32; 3092 int result = 0; 3093 3094 /* path-A IQK setting */ 3095 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f); 3096 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f); 3097 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102); 3098 3099 val32 = (priv->rf_paths > 1) ? 0x28160202 : 3100 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */ 3101 0x28160502; 3102 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32); 3103 3104 /* path-B IQK setting */ 3105 if (priv->rf_paths > 1) { 3106 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22); 3107 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22); 3108 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102); 3109 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202); 3110 } 3111 3112 /* LO calibration setting */ 3113 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1); 3114 3115 /* One shot, path A LOK & IQK */ 3116 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 3117 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 3118 3119 mdelay(1); 3120 3121 /* Check failed */ 3122 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 3123 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 3124 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 3125 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); 3126 3127 if (!(reg_eac & BIT(28)) && 3128 ((reg_e94 & 0x03ff0000) != 0x01420000) && 3129 ((reg_e9c & 0x03ff0000) != 0x00420000)) 3130 result |= 0x01; 3131 else /* If TX not OK, ignore RX */ 3132 goto out; 3133 3134 /* If TX is OK, check whether RX is OK */ 3135 if (!(reg_eac & BIT(27)) && 3136 ((reg_ea4 & 0x03ff0000) != 0x01320000) && 3137 ((reg_eac & 0x03ff0000) != 0x00360000)) 3138 result |= 0x02; 3139 else 3140 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", 3141 __func__); 3142out: 3143 return result; 3144} 3145 3146static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv) 3147{ 3148 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc; 3149 int result = 0; 3150 3151 /* One shot, path B LOK & IQK */ 3152 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002); 3153 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000); 3154 3155 mdelay(1); 3156 3157 /* Check failed */ 3158 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 3159 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3160 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3161 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); 3162 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); 3163 3164 if (!(reg_eac & BIT(31)) && 3165 ((reg_eb4 & 0x03ff0000) != 0x01420000) && 3166 ((reg_ebc & 0x03ff0000) != 0x00420000)) 3167 result |= 0x01; 3168 else 3169 goto out; 3170 3171 if (!(reg_eac & BIT(30)) && 3172 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) && 3173 (((reg_ecc & 0x03ff0000) >> 16) != 0x36)) 3174 result |= 0x02; 3175 else 3176 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", 3177 __func__); 3178out: 3179 return result; 3180} 3181 3182static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, 3183 int result[][8], int t) 3184{ 3185 struct device *dev = &priv->udev->dev; 3186 u32 i, val32; 3187 int path_a_ok, path_b_ok; 3188 int retry = 2; 3189 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { 3190 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, 3191 REG_RX_WAIT_CCA, REG_TX_CCK_RFON, 3192 REG_TX_CCK_BBON, REG_TX_OFDM_RFON, 3193 REG_TX_OFDM_BBON, REG_TX_TO_RX, 3194 REG_TX_TO_TX, REG_RX_CCK, 3195 REG_RX_OFDM, REG_RX_WAIT_RIFS, 3196 REG_RX_TO_RX, REG_STANDBY, 3197 REG_SLEEP, REG_PMPD_ANAEN 3198 }; 3199 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { 3200 REG_TXPAUSE, REG_BEACON_CTRL, 3201 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG 3202 }; 3203 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { 3204 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, 3205 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, 3206 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, 3207 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE 3208 }; 3209 3210 /* 3211 * Note: IQ calibration must be performed after loading 3212 * PHY_REG.txt , and radio_a, radio_b.txt 3213 */ 3214 3215 if (t == 0) { 3216 /* Save ADDA parameters, turn Path A ADDA on */ 3217 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, 3218 RTL8XXXU_ADDA_REGS); 3219 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 3220 rtl8xxxu_save_regs(priv, iqk_bb_regs, 3221 priv->bb_backup, RTL8XXXU_BB_REGS); 3222 } 3223 3224 rtl8xxxu_path_adda_on(priv, adda_regs, true); 3225 3226 if (t == 0) { 3227 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); 3228 if (val32 & FPGA0_HSSI_PARM1_PI) 3229 priv->pi_enabled = 1; 3230 } 3231 3232 if (!priv->pi_enabled) { 3233 /* Switch BB to PI mode to do IQ Calibration. */ 3234 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); 3235 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100); 3236 } 3237 3238 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 3239 val32 &= ~FPGA_RF_MODE_CCK; 3240 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 3241 3242 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); 3243 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); 3244 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); 3245 3246 if (!priv->no_pape) { 3247 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); 3248 val32 |= (FPGA0_RF_PAPE | 3249 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); 3250 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); 3251 } 3252 3253 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); 3254 val32 &= ~BIT(10); 3255 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); 3256 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); 3257 val32 &= ~BIT(10); 3258 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); 3259 3260 if (priv->tx_paths > 1) { 3261 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); 3262 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000); 3263 } 3264 3265 /* MAC settings */ 3266 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); 3267 3268 /* Page B init */ 3269 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000); 3270 3271 if (priv->tx_paths > 1) 3272 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000); 3273 3274 /* IQ calibration setting */ 3275 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 3276 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 3277 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 3278 3279 for (i = 0; i < retry; i++) { 3280 path_a_ok = rtl8xxxu_iqk_path_a(priv); 3281 if (path_a_ok == 0x03) { 3282 val32 = rtl8xxxu_read32(priv, 3283 REG_TX_POWER_BEFORE_IQK_A); 3284 result[t][0] = (val32 >> 16) & 0x3ff; 3285 val32 = rtl8xxxu_read32(priv, 3286 REG_TX_POWER_AFTER_IQK_A); 3287 result[t][1] = (val32 >> 16) & 0x3ff; 3288 val32 = rtl8xxxu_read32(priv, 3289 REG_RX_POWER_BEFORE_IQK_A_2); 3290 result[t][2] = (val32 >> 16) & 0x3ff; 3291 val32 = rtl8xxxu_read32(priv, 3292 REG_RX_POWER_AFTER_IQK_A_2); 3293 result[t][3] = (val32 >> 16) & 0x3ff; 3294 break; 3295 } else if (i == (retry - 1) && path_a_ok == 0x01) { 3296 /* TX IQK OK */ 3297 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n", 3298 __func__); 3299 3300 val32 = rtl8xxxu_read32(priv, 3301 REG_TX_POWER_BEFORE_IQK_A); 3302 result[t][0] = (val32 >> 16) & 0x3ff; 3303 val32 = rtl8xxxu_read32(priv, 3304 REG_TX_POWER_AFTER_IQK_A); 3305 result[t][1] = (val32 >> 16) & 0x3ff; 3306 } 3307 } 3308 3309 if (!path_a_ok) 3310 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__); 3311 3312 if (priv->tx_paths > 1) { 3313 /* 3314 * Path A into standby 3315 */ 3316 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0); 3317 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); 3318 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 3319 3320 /* Turn Path B ADDA on */ 3321 rtl8xxxu_path_adda_on(priv, adda_regs, false); 3322 3323 for (i = 0; i < retry; i++) { 3324 path_b_ok = rtl8xxxu_iqk_path_b(priv); 3325 if (path_b_ok == 0x03) { 3326 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3327 result[t][4] = (val32 >> 16) & 0x3ff; 3328 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3329 result[t][5] = (val32 >> 16) & 0x3ff; 3330 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); 3331 result[t][6] = (val32 >> 16) & 0x3ff; 3332 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); 3333 result[t][7] = (val32 >> 16) & 0x3ff; 3334 break; 3335 } else if (i == (retry - 1) && path_b_ok == 0x01) { 3336 /* TX IQK OK */ 3337 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3338 result[t][4] = (val32 >> 16) & 0x3ff; 3339 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3340 result[t][5] = (val32 >> 16) & 0x3ff; 3341 } 3342 } 3343 3344 if (!path_b_ok) 3345 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); 3346 } 3347 3348 /* Back to BB mode, load original value */ 3349 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0); 3350 3351 if (t) { 3352 if (!priv->pi_enabled) { 3353 /* 3354 * Switch back BB to SI mode after finishing 3355 * IQ Calibration 3356 */ 3357 val32 = 0x01000000; 3358 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); 3359 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); 3360 } 3361 3362 /* Reload ADDA power saving parameters */ 3363 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, 3364 RTL8XXXU_ADDA_REGS); 3365 3366 /* Reload MAC parameters */ 3367 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 3368 3369 /* Reload BB parameters */ 3370 rtl8xxxu_restore_regs(priv, iqk_bb_regs, 3371 priv->bb_backup, RTL8XXXU_BB_REGS); 3372 3373 /* Restore RX initial gain */ 3374 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3); 3375 3376 if (priv->tx_paths > 1) { 3377 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 3378 0x00032ed3); 3379 } 3380 3381 /* Load 0xe30 IQC default value */ 3382 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); 3383 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); 3384 } 3385} 3386 3387void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start) 3388{ 3389 struct h2c_cmd h2c; 3390 3391 memset(&h2c, 0, sizeof(struct h2c_cmd)); 3392 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION; 3393 h2c.bt_wlan_calibration.data = start; 3394 3395 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration)); 3396} 3397 3398void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv) 3399{ 3400 struct device *dev = &priv->udev->dev; 3401 int result[4][8]; /* last is final result */ 3402 int i, candidate; 3403 bool path_a_ok, path_b_ok; 3404 u32 reg_e94, reg_e9c, reg_ea4, reg_eac; 3405 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; 3406 s32 reg_tmp = 0; 3407 bool simu; 3408 3409 memset(result, 0, sizeof(result)); 3410 candidate = -1; 3411 3412 path_a_ok = false; 3413 path_b_ok = false; 3414 3415 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 3416 3417 for (i = 0; i < 3; i++) { 3418 rtl8xxxu_phy_iqcalibrate(priv, result, i); 3419 3420 if (i == 1) { 3421 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1); 3422 if (simu) { 3423 candidate = 0; 3424 break; 3425 } 3426 } 3427 3428 if (i == 2) { 3429 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2); 3430 if (simu) { 3431 candidate = 0; 3432 break; 3433 } 3434 3435 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2); 3436 if (simu) { 3437 candidate = 1; 3438 } else { 3439 for (i = 0; i < 8; i++) 3440 reg_tmp += result[3][i]; 3441 3442 if (reg_tmp) 3443 candidate = 3; 3444 else 3445 candidate = -1; 3446 } 3447 } 3448 } 3449 3450 for (i = 0; i < 4; i++) { 3451 reg_e94 = result[i][0]; 3452 reg_e9c = result[i][1]; 3453 reg_ea4 = result[i][2]; 3454 reg_eac = result[i][3]; 3455 reg_eb4 = result[i][4]; 3456 reg_ebc = result[i][5]; 3457 reg_ec4 = result[i][6]; 3458 reg_ecc = result[i][7]; 3459 } 3460 3461 if (candidate >= 0) { 3462 reg_e94 = result[candidate][0]; 3463 priv->rege94 = reg_e94; 3464 reg_e9c = result[candidate][1]; 3465 priv->rege9c = reg_e9c; 3466 reg_ea4 = result[candidate][2]; 3467 reg_eac = result[candidate][3]; 3468 reg_eb4 = result[candidate][4]; 3469 priv->regeb4 = reg_eb4; 3470 reg_ebc = result[candidate][5]; 3471 priv->regebc = reg_ebc; 3472 reg_ec4 = result[candidate][6]; 3473 reg_ecc = result[candidate][7]; 3474 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); 3475 dev_dbg(dev, 3476 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", 3477 __func__, reg_e94, reg_e9c, 3478 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); 3479 path_a_ok = true; 3480 path_b_ok = true; 3481 } else { 3482 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; 3483 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; 3484 } 3485 3486 if (reg_e94 && candidate >= 0) 3487 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, 3488 candidate, (reg_ea4 == 0)); 3489 3490 if (priv->tx_paths > 1 && reg_eb4) 3491 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, 3492 candidate, (reg_ec4 == 0)); 3493 3494 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, 3495 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); 3496} 3497 3498void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv) 3499{ 3500 u32 val32; 3501 u32 rf_amode, rf_bmode = 0, lstf; 3502 3503 /* Check continuous TX and Packet TX */ 3504 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 3505 3506 if (lstf & OFDM_LSTF_MASK) { 3507 /* Disable all continuous TX */ 3508 val32 = lstf & ~OFDM_LSTF_MASK; 3509 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 3510 3511 /* Read original RF mode Path A */ 3512 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC); 3513 3514 /* Set RF mode to standby Path A */ 3515 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 3516 (rf_amode & 0x8ffff) | 0x10000); 3517 3518 /* Path-B */ 3519 if (priv->tx_paths > 1) { 3520 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B, 3521 RF6052_REG_AC); 3522 3523 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 3524 (rf_bmode & 0x8ffff) | 0x10000); 3525 } 3526 } else { 3527 /* Deal with Packet TX case */ 3528 /* block all queues */ 3529 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3530 } 3531 3532 /* Start LC calibration */ 3533 if (priv->fops->has_s0s1) 3534 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0); 3535 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); 3536 val32 |= 0x08000; 3537 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); 3538 3539 msleep(100); 3540 3541 if (priv->fops->has_s0s1) 3542 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0); 3543 3544 /* Restore original parameters */ 3545 if (lstf & OFDM_LSTF_MASK) { 3546 /* Path-A */ 3547 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); 3548 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode); 3549 3550 /* Path-B */ 3551 if (priv->tx_paths > 1) 3552 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 3553 rf_bmode); 3554 } else /* Deal with Packet TX case */ 3555 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 3556} 3557 3558static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv, int port_num) 3559{ 3560 int i; 3561 u16 reg; 3562 3563 switch (port_num) { 3564 case 0: 3565 reg = REG_MACID; 3566 break; 3567 case 1: 3568 reg = REG_MACID1; 3569 break; 3570 default: 3571 WARN_ONCE(1, "%s: invalid port_num\n", __func__); 3572 return -EINVAL; 3573 } 3574 3575 for (i = 0; i < ETH_ALEN; i++) 3576 rtl8xxxu_write8(priv, reg + i, priv->vifs[port_num]->addr[i]); 3577 3578 return 0; 3579} 3580 3581static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid, int port_num) 3582{ 3583 int i; 3584 u16 reg; 3585 3586 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid); 3587 3588 switch (port_num) { 3589 case 0: 3590 reg = REG_BSSID; 3591 break; 3592 case 1: 3593 reg = REG_BSSID1; 3594 break; 3595 default: 3596 WARN_ONCE(1, "%s: invalid port_num\n", __func__); 3597 return -EINVAL; 3598 } 3599 3600 for (i = 0; i < ETH_ALEN; i++) 3601 rtl8xxxu_write8(priv, reg + i, bssid[i]); 3602 3603 return 0; 3604} 3605 3606static void 3607rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor) 3608{ 3609 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 }; 3610 u8 max_agg = 0xf; 3611 int i; 3612 3613 ampdu_factor = 1 << (ampdu_factor + 2); 3614 if (ampdu_factor > max_agg) 3615 ampdu_factor = max_agg; 3616 3617 for (i = 0; i < 4; i++) { 3618 if ((vals[i] & 0xf0) > (ampdu_factor << 4)) 3619 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4); 3620 3621 if ((vals[i] & 0x0f) > ampdu_factor) 3622 vals[i] = (vals[i] & 0xf0) | ampdu_factor; 3623 3624 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]); 3625 } 3626} 3627 3628static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density) 3629{ 3630 u8 val8; 3631 3632 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE); 3633 val8 &= 0xf8; 3634 val8 |= density; 3635 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8); 3636} 3637 3638int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv) 3639{ 3640 u8 val8; 3641 u8 val32; 3642 int count, ret = 0; 3643 3644 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3645 3646 /* 3647 * Poll - wait for RX packet to complete 3648 */ 3649 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 3650 val32 = rtl8xxxu_read32(priv, 0x5f8); 3651 if (!val32) 3652 break; 3653 udelay(10); 3654 } 3655 3656 if (!count) { 3657 dev_warn(&priv->udev->dev, 3658 "%s: RX poll timed out (0x05f8)\n", __func__); 3659 ret = -EBUSY; 3660 goto exit; 3661 } 3662 3663 /* Disable CCK and OFDM, clock gated */ 3664 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 3665 val8 &= ~SYS_FUNC_BBRSTB; 3666 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 3667 3668 udelay(2); 3669 3670 /* Reset baseband */ 3671 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 3672 val8 &= ~SYS_FUNC_BB_GLB_RSTN; 3673 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 3674 3675 /* Reset MAC TRX */ 3676 val8 = rtl8xxxu_read8(priv, REG_CR); 3677 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE; 3678 rtl8xxxu_write8(priv, REG_CR, val8); 3679 3680 /* Reset MAC TRX */ 3681 val8 = rtl8xxxu_read8(priv, REG_CR + 1); 3682 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */ 3683 rtl8xxxu_write8(priv, REG_CR + 1, val8); 3684 3685 /* Respond TX OK to scheduler */ 3686 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); 3687 val8 |= DUAL_TSF_TX_OK; 3688 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); 3689 3690exit: 3691 return ret; 3692} 3693 3694void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv) 3695{ 3696 u8 val8; 3697 3698 /* Clear suspend enable and power down enable*/ 3699 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3700 val8 &= ~(BIT(3) | BIT(7)); 3701 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3702 3703 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ 3704 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); 3705 val8 &= ~BIT(0); 3706 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); 3707 3708 /* 0x04[12:11] = 11 enable WL suspend*/ 3709 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3710 val8 &= ~(BIT(3) | BIT(4)); 3711 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3712} 3713 3714int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv) 3715{ 3716 struct device *dev = &priv->udev->dev; 3717 u32 val32; 3718 int retry, retval; 3719 3720 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3721 3722 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); 3723 val32 |= RXPKT_NUM_RW_RELEASE_EN; 3724 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32); 3725 3726 retry = 100; 3727 retval = -EBUSY; 3728 3729 do { 3730 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); 3731 if (val32 & RXPKT_NUM_RXDMA_IDLE) { 3732 retval = 0; 3733 break; 3734 } 3735 } while (retry--); 3736 3737 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0); 3738 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000); 3739 mdelay(2); 3740 3741 if (!retry) 3742 dev_warn(dev, "Failed to flush FIFO\n"); 3743 3744 return retval; 3745} 3746 3747void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv) 3748{ 3749 /* Fix USB interface interference issue */ 3750 rtl8xxxu_write8(priv, 0xfe40, 0xe0); 3751 rtl8xxxu_write8(priv, 0xfe41, 0x8d); 3752 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3753 /* 3754 * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits 3755 * 8 and 5, for which I have found no documentation. 3756 */ 3757 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320); 3758 3759 /* 3760 * Solve too many protocol error on USB bus. 3761 * Can't do this for 8188/8192 UMC A cut parts 3762 */ 3763 if (!(!priv->chip_cut && priv->vendor_umc)) { 3764 rtl8xxxu_write8(priv, 0xfe40, 0xe6); 3765 rtl8xxxu_write8(priv, 0xfe41, 0x94); 3766 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3767 3768 rtl8xxxu_write8(priv, 0xfe40, 0xe0); 3769 rtl8xxxu_write8(priv, 0xfe41, 0x19); 3770 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3771 3772 rtl8xxxu_write8(priv, 0xfe40, 0xe5); 3773 rtl8xxxu_write8(priv, 0xfe41, 0x91); 3774 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3775 3776 rtl8xxxu_write8(priv, 0xfe40, 0xe2); 3777 rtl8xxxu_write8(priv, 0xfe41, 0x81); 3778 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3779 } 3780} 3781 3782void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv) 3783{ 3784 u32 val32; 3785 3786 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); 3787 val32 |= TXDMA_OFFSET_DROP_DATA_EN; 3788 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); 3789} 3790 3791void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, 3792 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5) 3793{ 3794 struct h2c_cmd h2c; 3795 3796 memset(&h2c, 0, sizeof(struct h2c_cmd)); 3797 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA; 3798 h2c.b_type_dma.data1 = arg1; 3799 h2c.b_type_dma.data2 = arg2; 3800 h2c.b_type_dma.data3 = arg3; 3801 h2c.b_type_dma.data4 = arg4; 3802 h2c.b_type_dma.data5 = arg5; 3803 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma)); 3804} 3805 3806void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv) 3807{ 3808 u32 val32; 3809 3810 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); 3811 val32 &= ~(BIT(22) | BIT(23)); 3812 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); 3813} 3814 3815static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv) 3816{ 3817 struct rtl8xxxu_fileops *fops = priv->fops; 3818 u32 hq, lq, nq, eq, pubq; 3819 u32 val32; 3820 3821 hq = 0; 3822 lq = 0; 3823 nq = 0; 3824 eq = 0; 3825 pubq = 0; 3826 3827 if (priv->ep_tx_high_queue) 3828 hq = fops->page_num_hi; 3829 if (priv->ep_tx_low_queue) 3830 lq = fops->page_num_lo; 3831 if (priv->ep_tx_normal_queue) 3832 nq = fops->page_num_norm; 3833 3834 val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT); 3835 rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32); 3836 3837 pubq = fops->total_page_num - hq - lq - nq - 1; 3838 3839 val32 = RQPN_LOAD; 3840 val32 |= (hq << RQPN_HI_PQ_SHIFT); 3841 val32 |= (lq << RQPN_LO_PQ_SHIFT); 3842 val32 |= (pubq << RQPN_PUB_PQ_SHIFT); 3843 3844 rtl8xxxu_write32(priv, REG_RQPN, val32); 3845} 3846 3847void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv) 3848{ 3849 u8 val8; 3850 3851 /* 3852 * For USB high speed set 512B packets 3853 */ 3854 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B); 3855 u8p_replace_bits(&val8, 1, RXDMA_PRO_DMA_BURST_SIZE); 3856 u8p_replace_bits(&val8, 3, RXDMA_PRO_DMA_BURST_CNT); 3857 val8 |= RXDMA_PRO_DMA_MODE; 3858 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8); 3859 3860 /* 3861 * Enable single packet AMPDU 3862 */ 3863 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B); 3864 val8 |= HT_SINGLE_AMPDU_ENABLE; 3865 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8); 3866 3867 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, priv->fops->max_aggr_num); 3868 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 3869 priv->fops->ampdu_max_time); 3870 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff); 3871 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18); 3872 rtl8xxxu_write8(priv, REG_PIFS, 0x00); 3873 if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B || 3874 priv->rtl_chip == RTL8192F) { 3875 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, FWHW_TXQ_CTRL_AMPDU_RETRY); 3876 rtl8xxxu_write32(priv, REG_FAST_EDCA_CTRL, 0x03086666); 3877 } 3878 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, priv->fops->ustime_tsf_edca); 3879 rtl8xxxu_write8(priv, REG_USTIME_EDCA, priv->fops->ustime_tsf_edca); 3880 3881 /* to prevent mac is reseted by bus. */ 3882 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); 3883 val8 |= RSV_CTRL_WLOCK_1C | RSV_CTRL_DIS_PRST; 3884 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); 3885} 3886 3887static u8 rtl8xxxu_acquire_macid(struct rtl8xxxu_priv *priv) 3888{ 3889 u8 macid; 3890 3891 macid = find_first_zero_bit(priv->mac_id_map, RTL8XXXU_MAX_MAC_ID_NUM); 3892 if (macid < RTL8XXXU_MAX_MAC_ID_NUM) 3893 set_bit(macid, priv->mac_id_map); 3894 3895 return macid; 3896} 3897 3898static void rtl8xxxu_release_macid(struct rtl8xxxu_priv *priv, u8 macid) 3899{ 3900 clear_bit(macid, priv->mac_id_map); 3901} 3902 3903static inline u8 rtl8xxxu_get_macid(struct rtl8xxxu_priv *priv, 3904 struct ieee80211_sta *sta) 3905{ 3906 struct rtl8xxxu_sta_info *sta_info; 3907 3908 if (!sta) 3909 return 0; 3910 3911 sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; 3912 if (!sta_info) 3913 return 0; 3914 3915 return sta_info->macid; 3916} 3917 3918static int rtl8xxxu_init_device(struct ieee80211_hw *hw) 3919{ 3920 struct rtl8xxxu_priv *priv = hw->priv; 3921 struct device *dev = &priv->udev->dev; 3922 struct rtl8xxxu_fileops *fops = priv->fops; 3923 bool macpower; 3924 int ret; 3925 u8 val8; 3926 u16 val16; 3927 u32 val32; 3928 3929 /* Check if MAC is already powered on */ 3930 val8 = rtl8xxxu_read8(priv, REG_CR); 3931 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); 3932 3933 /* 3934 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not 3935 * initialized. First MAC returns 0xea, second MAC returns 0x00 3936 */ 3937 if (val8 == 0xea || !(val16 & SYS_CLK_MAC_CLK_ENABLE)) 3938 macpower = false; 3939 else 3940 macpower = true; 3941 3942 if (fops->needs_full_init) 3943 macpower = false; 3944 3945 ret = fops->power_on(priv); 3946 if (ret < 0) { 3947 dev_warn(dev, "%s: Failed power on\n", __func__); 3948 goto exit; 3949 } 3950 3951 if (!macpower) 3952 rtl8xxxu_init_queue_reserved_page(priv); 3953 3954 ret = rtl8xxxu_init_queue_priority(priv); 3955 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret); 3956 if (ret) 3957 goto exit; 3958 3959 /* 3960 * Set RX page boundary 3961 */ 3962 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, fops->trxff_boundary); 3963 3964 for (int retry = 5; retry >= 0 ; retry--) { 3965 ret = rtl8xxxu_download_firmware(priv); 3966 dev_dbg(dev, "%s: download_firmware %i\n", __func__, ret); 3967 if (ret != -EAGAIN) 3968 break; 3969 if (retry) 3970 dev_dbg(dev, "%s: retry firmware download\n", __func__); 3971 } 3972 if (ret) 3973 goto exit; 3974 ret = rtl8xxxu_start_firmware(priv); 3975 dev_dbg(dev, "%s: start_firmware %i\n", __func__, ret); 3976 if (ret) 3977 goto exit; 3978 3979 if (fops->phy_init_antenna_selection) 3980 fops->phy_init_antenna_selection(priv); 3981 3982 ret = rtl8xxxu_init_mac(priv); 3983 3984 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret); 3985 if (ret) 3986 goto exit; 3987 3988 ret = rtl8xxxu_init_phy_bb(priv); 3989 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret); 3990 if (ret) 3991 goto exit; 3992 3993 ret = fops->init_phy_rf(priv); 3994 if (ret) 3995 goto exit; 3996 3997 /* Mac APLL Setting */ 3998 if (priv->rtl_chip == RTL8192F) 3999 rtl8xxxu_write16_set(priv, REG_AFE_CTRL4, BIT(4) | BIT(15)); 4000 4001 /* RFSW Control - clear bit 14 ?? */ 4002 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E && 4003 priv->rtl_chip != RTL8188E && priv->rtl_chip != RTL8710B && 4004 priv->rtl_chip != RTL8192F) 4005 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003); 4006 4007 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW | 4008 FPGA0_RF_ANTSWB | 4009 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT); 4010 if (!priv->no_pape) { 4011 val32 |= (FPGA0_RF_PAPE | 4012 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); 4013 } 4014 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); 4015 4016 /* 0x860[6:5]= 00 - why? - this sets antenna B */ 4017 if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188E && 4018 priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F) 4019 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210); 4020 4021 if (!macpower) { 4022 /* 4023 * Set TX buffer boundary 4024 */ 4025 val8 = fops->total_page_num + 1; 4026 4027 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8); 4028 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8); 4029 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8); 4030 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8); 4031 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8); 4032 } 4033 4034 /* 4035 * The vendor drivers set PBP for all devices, except 8192e. 4036 * There is no explanation for this in any of the sources. 4037 */ 4038 val8 = (fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) | 4039 (fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT); 4040 if (priv->rtl_chip != RTL8192E) 4041 rtl8xxxu_write8(priv, REG_PBP, val8); 4042 4043 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower); 4044 if (!macpower) { 4045 ret = fops->llt_init(priv); 4046 if (ret) { 4047 dev_warn(dev, "%s: LLT table init failed\n", __func__); 4048 goto exit; 4049 } 4050 4051 /* 4052 * Chip specific quirks 4053 */ 4054 fops->usb_quirks(priv); 4055 4056 /* 4057 * Enable TX report and TX report timer for 8723bu/8188eu/... 4058 */ 4059 if (fops->has_tx_report) { 4060 /* 4061 * The RTL8188EU has two types of TX reports: 4062 * rpt_sel=1: 4063 * One report for one frame. We can use this for frames 4064 * with IEEE80211_TX_CTL_REQ_TX_STATUS. 4065 * rpt_sel=2: 4066 * One report for many frames transmitted over a period 4067 * of time. (This is what REG_TX_REPORT_TIME is for.) The 4068 * report includes the number of frames transmitted 4069 * successfully, and the number of unsuccessful 4070 * transmissions. We use this for software rate control. 4071 * 4072 * Bit 0 of REG_TX_REPORT_CTRL is required for both types. 4073 * Bit 1 (TX_REPORT_CTRL_TIMER_ENABLE) is required for 4074 * type 2. 4075 */ 4076 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); 4077 if (priv->rtl_chip == RTL8188E) 4078 val8 |= BIT(0); 4079 val8 |= TX_REPORT_CTRL_TIMER_ENABLE; 4080 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); 4081 /* Set MAX RPT MACID */ 4082 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02); 4083 /* TX report Timer. Unit: 32us */ 4084 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0); 4085 4086 /* tmp ps ? */ 4087 val8 = rtl8xxxu_read8(priv, 0xa3); 4088 val8 &= 0xf8; 4089 rtl8xxxu_write8(priv, 0xa3, val8); 4090 } 4091 4092 if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F) 4093 rtl8xxxu_write8(priv, REG_EARLY_MODE_CONTROL_8710B, 0); 4094 } 4095 4096 /* 4097 * Unit in 8 bytes. 4098 * Get Rx PHY status in order to report RSSI and others. 4099 */ 4100 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4); 4101 4102 if (priv->rtl_chip == RTL8192E) { 4103 rtl8xxxu_write32(priv, REG_HIMR0, 0x00); 4104 rtl8xxxu_write32(priv, REG_HIMR1, 0x00); 4105 } else if (priv->rtl_chip == RTL8188F) { 4106 rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff); 4107 rtl8xxxu_write32(priv, REG_HISR1, 0xffffffff); 4108 } else if (priv->rtl_chip == RTL8188E) { 4109 rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff); 4110 val32 = IMR0_PSTIMEOUT | IMR0_TBDER | IMR0_CPWM | IMR0_CPWM2; 4111 rtl8xxxu_write32(priv, REG_HIMR0, val32); 4112 val32 = IMR1_TXERR | IMR1_RXERR | IMR1_TXFOVW | IMR1_RXFOVW; 4113 rtl8xxxu_write32(priv, REG_HIMR1, val32); 4114 val8 = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION); 4115 val8 |= USB_SPEC_INT_BULK_SELECT; 4116 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, val8); 4117 } else if (priv->rtl_chip == RTL8710B) { 4118 rtl8xxxu_write32(priv, REG_HIMR0_8710B, 0); 4119 } else if (priv->rtl_chip != RTL8192F) { 4120 /* 4121 * Enable all interrupts - not obvious USB needs to do this 4122 */ 4123 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff); 4124 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff); 4125 } 4126 4127 /* 4128 * Configure initial WMAC settings 4129 */ 4130 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST | 4131 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL | 4132 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC; 4133 rtl8xxxu_write32(priv, REG_RCR, val32); 4134 priv->regrcr = val32; 4135 4136 if (fops->init_reg_rxfltmap) { 4137 /* Accept all data frames */ 4138 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); 4139 4140 /* 4141 * Since ADF is removed from RCR, ps-poll will not be indicate to driver, 4142 * RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. 4143 */ 4144 rtl8xxxu_write16(priv, REG_RXFLTMAP1, 0x400); 4145 4146 /* Accept all management frames */ 4147 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); 4148 } else { 4149 /* 4150 * Accept all multicast 4151 */ 4152 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff); 4153 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff); 4154 } 4155 4156 /* 4157 * Init adaptive controls 4158 */ 4159 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4160 val32 &= ~RESPONSE_RATE_BITMAP_ALL; 4161 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M; 4162 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4163 4164 /* CCK = 0x0a, OFDM = 0x10 */ 4165 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10); 4166 rtl8xxxu_set_retry(priv, 0x30, 0x30); 4167 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10); 4168 4169 /* 4170 * Init EDCA 4171 */ 4172 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a); 4173 4174 /* Set CCK SIFS */ 4175 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a); 4176 4177 /* Set OFDM SIFS */ 4178 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a); 4179 4180 /* TXOP */ 4181 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b); 4182 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f); 4183 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324); 4184 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226); 4185 4186 /* Set data auto rate fallback retry count */ 4187 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000); 4188 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404); 4189 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201); 4190 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605); 4191 4192 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL); 4193 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY; 4194 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8); 4195 4196 /* Set ACK timeout */ 4197 rtl8xxxu_write8(priv, REG_ACKTO, 0x40); 4198 4199 /* 4200 * Initialize beacon parameters 4201 */ 4202 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8); 4203 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16); 4204 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404); 4205 if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8710B && 4206 priv->rtl_chip != RTL8192F) 4207 /* Firmware will control REG_DRVERLYINT when power saving is enable, */ 4208 /* so don't set this register on STA mode. */ 4209 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME); 4210 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME); 4211 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F); 4212 4213 /* 4214 * Initialize burst parameters 4215 */ 4216 if (priv->fops->init_burst) 4217 priv->fops->init_burst(priv); 4218 4219 if (fops->init_aggregation) 4220 fops->init_aggregation(priv); 4221 4222 if (fops->init_reg_pkt_life_time) { 4223 rtl8xxxu_write16(priv, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ 4224 rtl8xxxu_write16(priv, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ 4225 } 4226 4227 /* 4228 * Enable CCK and OFDM block 4229 */ 4230 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 4231 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM); 4232 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 4233 4234 /* 4235 * Invalidate all CAM entries - bit 30 is undocumented 4236 */ 4237 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30)); 4238 4239 /* 4240 * Start out with default power levels for channel 6, 20MHz 4241 */ 4242 fops->set_tx_power(priv, 1, false); 4243 4244 /* Let the 8051 take control of antenna setting */ 4245 if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188F && 4246 priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192C) { 4247 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); 4248 val8 |= LEDCFG2_DPDT_SELECT; 4249 rtl8xxxu_write8(priv, REG_LEDCFG2, val8); 4250 } 4251 4252 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff); 4253 4254 /* Disable BAR - not sure if this has any effect on USB */ 4255 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff); 4256 4257 if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8188E && 4258 priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F) 4259 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0); 4260 4261 if (fops->init_statistics) 4262 fops->init_statistics(priv); 4263 4264 if (priv->rtl_chip == RTL8192E) { 4265 /* 4266 * 0x4c6[3] 1: RTS BW = Data BW 4267 * 0: RTS BW depends on CCA / secondary CCA result. 4268 */ 4269 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL); 4270 val8 &= ~BIT(3); 4271 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8); 4272 /* 4273 * Reset USB mode switch setting 4274 */ 4275 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00); 4276 } else if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8188E || 4277 priv->rtl_chip == RTL8192F) { 4278 /* 4279 * Init GPIO settings for 8188f, 8188e, 8192f 4280 */ 4281 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); 4282 val8 &= ~GPIO_MUXCFG_IO_SEL_ENBT; 4283 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); 4284 } 4285 4286 if (priv->rtl_chip == RTL8188F) 4287 /* CCK PD */ 4288 rtl8xxxu_write8(priv, REG_CCK_PD_THRESH, CCK_PD_TYPE1_LV1_TH); 4289 4290 fops->phy_lc_calibrate(priv); 4291 4292 fops->phy_iq_calibrate(priv); 4293 4294 /* 4295 * This should enable thermal meter 4296 */ 4297 if (fops->gen2_thermal_meter) { 4298 if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B) { 4299 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B); 4300 val32 |= 0x30000; 4301 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B, val32); 4302 } else { 4303 rtl8xxxu_write_rfreg(priv, 4304 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8); 4305 } 4306 } else { 4307 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60); 4308 } 4309 4310 /* Set NAV_UPPER to 30000us */ 4311 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT); 4312 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8); 4313 4314 if (priv->rtl_chip == RTL8723A) { 4315 /* 4316 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, 4317 * but we need to find root cause. 4318 * This is 8723au only. 4319 */ 4320 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 4321 if ((val32 & 0xff000000) != 0x83000000) { 4322 val32 |= FPGA_RF_MODE_CCK; 4323 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 4324 } 4325 } else if (priv->rtl_chip == RTL8192E || priv->rtl_chip == RTL8188E) { 4326 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00); 4327 } 4328 4329 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL); 4330 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK; 4331 /* ack for xmit mgmt frames. */ 4332 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32); 4333 4334 if (priv->rtl_chip == RTL8192E) { 4335 /* 4336 * Fix LDPC rx hang issue. 4337 */ 4338 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC); 4339 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75); 4340 val32 &= 0xfff00fff; 4341 val32 |= 0x0007e000; 4342 rtl8xxxu_write32(priv, REG_AFE_MISC, val32); 4343 4344 /* 4345 * 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting 4346 * should be equal or CCK RSSI report may be incorrect 4347 */ 4348 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); 4349 priv->cck_agc_report_type = 4350 u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR); 4351 4352 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_HSSI_PARM2); 4353 if (priv->cck_agc_report_type != 4354 u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR)) { 4355 if (priv->cck_agc_report_type) 4356 val32 |= FPGA0_HSSI_PARM2_CCK_HIGH_PWR; 4357 else 4358 val32 &= ~FPGA0_HSSI_PARM2_CCK_HIGH_PWR; 4359 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM2, val32); 4360 } 4361 4362 val32 = rtl8xxxu_read32(priv, REG_AGC_RPT); 4363 if (priv->cck_agc_report_type) 4364 val32 |= AGC_RPT_CCK; 4365 else 4366 val32 &= ~AGC_RPT_CCK; 4367 rtl8xxxu_write32(priv, REG_AGC_RPT, val32); 4368 } 4369 4370 if (priv->rtl_chip == RTL8710B) { 4371 /* 4372 * 0x76D[5:4] is Port0,Port1 Enable Bit. 4373 * This is only for 8710B, 2b'00 for MP and 2b'11 for Normal Driver 4374 */ 4375 val8 = rtl8xxxu_read8(priv, REG_PORT_CONTROL_8710B); 4376 val8 |= BIT(5) | BIT(4); 4377 rtl8xxxu_write8(priv, REG_PORT_CONTROL_8710B, val8); 4378 4379 /* Set 0x5c[8] and [2:0] = 1, LDO mode */ 4380 val32 = rtl8xxxu_read32(priv, REG_WL_RF_PSS_8710B); 4381 val32 |= 0x107; 4382 rtl8xxxu_write32(priv, REG_WL_RF_PSS_8710B, val32); 4383 } 4384 4385 val32 = rtl8xxxu_read32(priv, 0xa9c); 4386 priv->cck_new_agc = u32_get_bits(val32, BIT(17)); 4387 4388 /* Initialise the center frequency offset tracking */ 4389 if (priv->fops->set_crystal_cap) { 4390 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); 4391 priv->cfo_tracking.atc_status = val32 & CFO_TRACKING_ATC_STATUS; 4392 priv->cfo_tracking.adjust = true; 4393 priv->cfo_tracking.crystal_cap = priv->default_crystal_cap; 4394 } 4395 4396 if (priv->rtl_chip == RTL8188E) 4397 rtl8188e_ra_info_init_all(&priv->ra_info); 4398 4399 set_bit(RTL8XXXU_BC_MC_MACID, priv->mac_id_map); 4400 set_bit(RTL8XXXU_BC_MC_MACID1, priv->mac_id_map); 4401 4402exit: 4403 return ret; 4404} 4405 4406static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv, 4407 struct ieee80211_key_conf *key, const u8 *mac) 4408{ 4409 u32 cmd, val32, addr, ctrl; 4410 int j, i, tmp_debug; 4411 4412 tmp_debug = rtl8xxxu_debug; 4413 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY) 4414 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE; 4415 4416 /* 4417 * This is a bit of a hack - the lower bits of the cipher 4418 * suite selector happens to match the cipher index in the CAM 4419 */ 4420 addr = key->hw_key_idx << CAM_CMD_KEY_SHIFT; 4421 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID; 4422 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 4423 ctrl |= BIT(6); 4424 4425 for (j = 5; j >= 0; j--) { 4426 switch (j) { 4427 case 0: 4428 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24); 4429 break; 4430 case 1: 4431 val32 = mac[2] | (mac[3] << 8) | 4432 (mac[4] << 16) | (mac[5] << 24); 4433 break; 4434 default: 4435 i = (j - 2) << 2; 4436 val32 = key->key[i] | (key->key[i + 1] << 8) | 4437 key->key[i + 2] << 16 | key->key[i + 3] << 24; 4438 break; 4439 } 4440 4441 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32); 4442 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j); 4443 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd); 4444 udelay(100); 4445 } 4446 4447 rtl8xxxu_debug = tmp_debug; 4448} 4449 4450static 4451int rtl8xxxu_get_antenna(struct ieee80211_hw *hw, int radio_idx, u32 *tx_ant, 4452 u32 *rx_ant) 4453{ 4454 struct rtl8xxxu_priv *priv = hw->priv; 4455 4456 *tx_ant = BIT(priv->tx_paths) - 1; 4457 *rx_ant = BIT(priv->rx_paths) - 1; 4458 4459 return 0; 4460} 4461 4462static int rtl8xxxu_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, 4463 bool set) 4464{ 4465 struct rtl8xxxu_priv *priv = hw->priv; 4466 4467 schedule_delayed_work(&priv->update_beacon_work, 0); 4468 4469 return 0; 4470} 4471 4472static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw, 4473 struct ieee80211_vif *vif, const u8 *mac) 4474{ 4475 struct rtl8xxxu_priv *priv = hw->priv; 4476 u8 val8; 4477 4478 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4479 val8 |= BEACON_DISABLE_TSF_UPDATE; 4480 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4481} 4482 4483static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw, 4484 struct ieee80211_vif *vif) 4485{ 4486 struct rtl8xxxu_priv *priv = hw->priv; 4487 u8 val8; 4488 4489 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4490 val8 &= ~BEACON_DISABLE_TSF_UPDATE; 4491 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4492} 4493 4494void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, 4495 u32 ramask, u8 rateid, int sgi, int txbw_40mhz, 4496 u8 macid) 4497{ 4498 struct h2c_cmd h2c; 4499 4500 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4501 4502 h2c.ramask.cmd = H2C_SET_RATE_MASK; 4503 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff); 4504 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16); 4505 4506 h2c.ramask.arg = 0x80; 4507 if (sgi) 4508 h2c.ramask.arg |= 0x20; 4509 4510 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n", 4511 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask)); 4512 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask)); 4513} 4514 4515void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, 4516 u32 ramask, u8 rateid, int sgi, int txbw_40mhz, 4517 u8 macid) 4518{ 4519 struct h2c_cmd h2c; 4520 u8 bw; 4521 4522 if (txbw_40mhz) 4523 bw = RTL8XXXU_CHANNEL_WIDTH_40; 4524 else 4525 bw = RTL8XXXU_CHANNEL_WIDTH_20; 4526 4527 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4528 4529 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID; 4530 h2c.b_macid_cfg.ramask0 = ramask & 0xff; 4531 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff; 4532 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff; 4533 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff; 4534 h2c.b_macid_cfg.macid = macid; 4535 4536 h2c.b_macid_cfg.data1 = rateid; 4537 if (sgi) 4538 h2c.b_macid_cfg.data1 |= BIT(7); 4539 4540 h2c.b_macid_cfg.data2 = bw; 4541 4542 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, rateid %02x, sgi %d, size %zi\n", 4543 __func__, ramask, rateid, sgi, sizeof(h2c.b_macid_cfg)); 4544 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg)); 4545} 4546 4547void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv, 4548 u8 macid, u8 role, bool connect) 4549{ 4550 struct h2c_cmd h2c; 4551 4552 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4553 4554 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT; 4555 4556 if (connect) 4557 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT; 4558 else 4559 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT; 4560 4561 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss)); 4562} 4563 4564void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, 4565 u8 macid, u8 role, bool connect) 4566{ 4567 /* 4568 * The firmware turns on the rate control when it knows it's 4569 * connected to a network. 4570 */ 4571 struct h2c_cmd h2c; 4572 4573 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4574 4575 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT; 4576 if (connect) 4577 h2c.media_status_rpt.parm |= BIT(0); 4578 else 4579 h2c.media_status_rpt.parm &= ~BIT(0); 4580 4581 h2c.media_status_rpt.parm |= ((role << 4) & 0xf0); 4582 h2c.media_status_rpt.macid = macid; 4583 4584 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt)); 4585} 4586 4587void rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi) 4588{ 4589 struct h2c_cmd h2c; 4590 const int h2c_size = 4; 4591 4592 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4593 4594 h2c.rssi_report.cmd = H2C_SET_RSSI; 4595 h2c.rssi_report.macid = macid; 4596 h2c.rssi_report.rssi = rssi; 4597 4598 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, h2c_size); 4599} 4600 4601void rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi) 4602{ 4603 struct h2c_cmd h2c; 4604 int h2c_size = sizeof(h2c.rssi_report); 4605 4606 if (priv->rtl_chip == RTL8723B) 4607 h2c_size = 4; 4608 4609 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4610 4611 h2c.rssi_report.cmd = H2C_8723B_RSSI_SETTING; 4612 h2c.rssi_report.macid = macid; 4613 h2c.rssi_report.rssi = rssi; 4614 4615 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, h2c_size); 4616} 4617 4618void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv) 4619{ 4620 u8 agg_ctrl, usb_spec, page_thresh, timeout; 4621 4622 usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION); 4623 usb_spec &= ~USB_SPEC_USB_AGG_ENABLE; 4624 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec); 4625 4626 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); 4627 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; 4628 4629 if (!rtl8xxxu_dma_aggregation) { 4630 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 4631 return; 4632 } 4633 4634 agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN; 4635 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 4636 4637 /* 4638 * The number of packets we can take looks to be buffer size / 512 4639 * which matches the 512 byte rounding we have to do when de-muxing 4640 * the packets. 4641 * 4642 * Sample numbers from the vendor driver: 4643 * USB High-Speed mode values: 4644 * RxAggBlockCount = 8 : 512 byte unit 4645 * RxAggBlockTimeout = 6 4646 * RxAggPageCount = 48 : 128 byte unit 4647 * RxAggPageTimeout = 4 or 6 (absolute time 34ms/(2^6)) 4648 */ 4649 4650 page_thresh = (priv->fops->rx_agg_buf_size / 512); 4651 if (rtl8xxxu_dma_agg_pages >= 0) { 4652 if (rtl8xxxu_dma_agg_pages <= page_thresh) 4653 timeout = page_thresh; 4654 else if (rtl8xxxu_dma_agg_pages <= 6) 4655 dev_err(&priv->udev->dev, 4656 "%s: dma_agg_pages=%i too small, minimum is 6\n", 4657 __func__, rtl8xxxu_dma_agg_pages); 4658 else 4659 dev_err(&priv->udev->dev, 4660 "%s: dma_agg_pages=%i larger than limit %i\n", 4661 __func__, rtl8xxxu_dma_agg_pages, page_thresh); 4662 } 4663 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh); 4664 /* 4665 * REG_RXDMA_AGG_PG_TH + 1 seems to be the timeout register on 4666 * gen2 chips and rtl8188eu. The rtl8723au seems unhappy if we 4667 * don't set it, so better set both. 4668 */ 4669 timeout = 4; 4670 4671 if (rtl8xxxu_dma_agg_timeout >= 0) { 4672 if (rtl8xxxu_dma_agg_timeout <= 127) 4673 timeout = rtl8xxxu_dma_agg_timeout; 4674 else 4675 dev_err(&priv->udev->dev, 4676 "%s: Invalid dma_agg_timeout: %i\n", 4677 __func__, rtl8xxxu_dma_agg_timeout); 4678 } 4679 4680 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout); 4681 rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout); 4682 priv->rx_buf_aggregation = 1; 4683} 4684 4685static const struct ieee80211_rate rtl8xxxu_legacy_ratetable[] = { 4686 {.bitrate = 10, .hw_value = 0x00,}, 4687 {.bitrate = 20, .hw_value = 0x01,}, 4688 {.bitrate = 55, .hw_value = 0x02,}, 4689 {.bitrate = 110, .hw_value = 0x03,}, 4690 {.bitrate = 60, .hw_value = 0x04,}, 4691 {.bitrate = 90, .hw_value = 0x05,}, 4692 {.bitrate = 120, .hw_value = 0x06,}, 4693 {.bitrate = 180, .hw_value = 0x07,}, 4694 {.bitrate = 240, .hw_value = 0x08,}, 4695 {.bitrate = 360, .hw_value = 0x09,}, 4696 {.bitrate = 480, .hw_value = 0x0a,}, 4697 {.bitrate = 540, .hw_value = 0x0b,}, 4698}; 4699 4700static void rtl8xxxu_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss) 4701{ 4702 if (rate <= DESC_RATE_54M) 4703 return; 4704 4705 if (rate >= DESC_RATE_MCS0 && rate <= DESC_RATE_MCS15) { 4706 if (rate < DESC_RATE_MCS8) 4707 *nss = 1; 4708 else 4709 *nss = 2; 4710 *mcs = rate - DESC_RATE_MCS0; 4711 } 4712} 4713 4714static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg) 4715{ 4716 struct ieee80211_hw *hw = priv->hw; 4717 u32 val32; 4718 u8 rate_idx = 0; 4719 4720 rate_cfg &= RESPONSE_RATE_BITMAP_ALL; 4721 4722 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4723 if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) 4724 val32 &= RESPONSE_RATE_RRSR_INIT_5G; 4725 else 4726 val32 &= RESPONSE_RATE_RRSR_INIT_2G; 4727 val32 |= rate_cfg; 4728 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4729 4730 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg); 4731 4732 if (rate_cfg) 4733 rate_idx = __fls(rate_cfg); 4734 4735 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx); 4736} 4737 4738static u16 4739rtl8xxxu_wireless_mode(struct ieee80211_hw *hw, struct ieee80211_sta *sta) 4740{ 4741 u16 network_type = WIRELESS_MODE_UNKNOWN; 4742 4743 if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) { 4744 if (sta->deflink.vht_cap.vht_supported) 4745 network_type = WIRELESS_MODE_AC; 4746 else if (sta->deflink.ht_cap.ht_supported) 4747 network_type = WIRELESS_MODE_N_5G; 4748 4749 network_type |= WIRELESS_MODE_A; 4750 } else { 4751 if (sta->deflink.vht_cap.vht_supported) 4752 network_type = WIRELESS_MODE_AC; 4753 else if (sta->deflink.ht_cap.ht_supported) 4754 network_type = WIRELESS_MODE_N_24G; 4755 4756 if (sta->deflink.supp_rates[0] <= 0xf) 4757 network_type |= WIRELESS_MODE_B; 4758 else if (sta->deflink.supp_rates[0] & 0xf) 4759 network_type |= (WIRELESS_MODE_B | WIRELESS_MODE_G); 4760 else 4761 network_type |= WIRELESS_MODE_G; 4762 } 4763 4764 return network_type; 4765} 4766 4767static void rtl8xxxu_set_aifs(struct rtl8xxxu_priv *priv, u8 slot_time) 4768{ 4769 u32 reg_edca_param[IEEE80211_NUM_ACS] = { 4770 [IEEE80211_AC_VO] = REG_EDCA_VO_PARAM, 4771 [IEEE80211_AC_VI] = REG_EDCA_VI_PARAM, 4772 [IEEE80211_AC_BE] = REG_EDCA_BE_PARAM, 4773 [IEEE80211_AC_BK] = REG_EDCA_BK_PARAM, 4774 }; 4775 u32 val32; 4776 u16 wireless_mode = 0; 4777 u8 aifs, aifsn, sifs; 4778 int i; 4779 4780 for (i = 0; i < ARRAY_SIZE(priv->vifs); i++) { 4781 struct ieee80211_sta *sta; 4782 4783 if (!priv->vifs[i]) 4784 continue; 4785 4786 rcu_read_lock(); 4787 sta = ieee80211_find_sta(priv->vifs[i], priv->vifs[i]->bss_conf.bssid); 4788 if (sta) 4789 wireless_mode = rtl8xxxu_wireless_mode(priv->hw, sta); 4790 rcu_read_unlock(); 4791 4792 if (wireless_mode) 4793 break; 4794 } 4795 4796 if (priv->hw->conf.chandef.chan->band == NL80211_BAND_5GHZ || 4797 (wireless_mode & WIRELESS_MODE_N_24G)) 4798 sifs = 16; 4799 else 4800 sifs = 10; 4801 4802 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 4803 val32 = rtl8xxxu_read32(priv, reg_edca_param[i]); 4804 4805 /* It was set in conf_tx. */ 4806 aifsn = val32 & 0xff; 4807 4808 /* aifsn not set yet or already fixed */ 4809 if (aifsn < 2 || aifsn > 15) 4810 continue; 4811 4812 aifs = aifsn * slot_time + sifs; 4813 4814 val32 &= ~0xff; 4815 val32 |= aifs; 4816 rtl8xxxu_write32(priv, reg_edca_param[i], val32); 4817 } 4818} 4819 4820void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt, 4821 u8 rate, u8 sgi, u8 bw) 4822{ 4823 u8 mcs, nss; 4824 4825 rarpt->txrate.flags = 0; 4826 4827 if (rate <= DESC_RATE_54M) { 4828 rarpt->txrate.legacy = rtl8xxxu_legacy_ratetable[rate].bitrate; 4829 } else { 4830 rtl8xxxu_desc_to_mcsrate(rate, &mcs, &nss); 4831 rarpt->txrate.flags |= RATE_INFO_FLAGS_MCS; 4832 4833 rarpt->txrate.mcs = mcs; 4834 rarpt->txrate.nss = nss; 4835 4836 if (sgi) 4837 rarpt->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 4838 4839 rarpt->txrate.bw = bw; 4840 } 4841 4842 rarpt->bit_rate = cfg80211_calculate_bitrate(&rarpt->txrate); 4843 rarpt->desc_rate = rate; 4844} 4845 4846static void 4847rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 4848 struct ieee80211_bss_conf *bss_conf, u64 changed) 4849{ 4850 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; 4851 struct rtl8xxxu_priv *priv = hw->priv; 4852 struct device *dev = &priv->udev->dev; 4853 struct rtl8xxxu_sta_info *sta_info; 4854 struct ieee80211_sta *sta; 4855 struct rtl8xxxu_ra_report *rarpt; 4856 u8 val8, macid; 4857 u32 val32; 4858 4859 rarpt = &priv->ra_report; 4860 4861 if (changed & BSS_CHANGED_ASSOC) { 4862 dev_dbg(dev, "Changed ASSOC: %i!\n", vif->cfg.assoc); 4863 4864 rtl8xxxu_set_linktype(priv, vif->type, rtlvif->port_num); 4865 4866 if (vif->cfg.assoc) { 4867 u32 ramask; 4868 int sgi = 0; 4869 u8 highest_rate; 4870 u8 bw; 4871 4872 rcu_read_lock(); 4873 sta = ieee80211_find_sta(vif, bss_conf->bssid); 4874 if (!sta) { 4875 dev_info(dev, "%s: ASSOC no sta found\n", 4876 __func__); 4877 rcu_read_unlock(); 4878 goto error; 4879 } 4880 macid = rtl8xxxu_get_macid(priv, sta); 4881 4882 if (sta->deflink.ht_cap.ht_supported) 4883 dev_info(dev, "%s: HT supported\n", __func__); 4884 if (sta->deflink.vht_cap.vht_supported) 4885 dev_info(dev, "%s: VHT supported\n", __func__); 4886 4887 /* TODO: Set bits 28-31 for rate adaptive id */ 4888 ramask = (sta->deflink.supp_rates[0] & 0xfff) | 4889 sta->deflink.ht_cap.mcs.rx_mask[0] << 12 | 4890 sta->deflink.ht_cap.mcs.rx_mask[1] << 20; 4891 if (sta->deflink.ht_cap.cap & 4892 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) 4893 sgi = 1; 4894 4895 highest_rate = fls(ramask) - 1; 4896 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) 4897 bw = RATE_INFO_BW_40; 4898 else 4899 bw = RATE_INFO_BW_20; 4900 4901 sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; 4902 sta_info->rssi_level = RTL8XXXU_RATR_STA_INIT; 4903 rcu_read_unlock(); 4904 4905 rtl8xxxu_update_ra_report(rarpt, highest_rate, sgi, bw); 4906 4907 priv->fops->update_rate_mask(priv, ramask, 0, sgi, 4908 bw == RATE_INFO_BW_40, macid); 4909 4910 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff); 4911 4912 if (rtlvif->port_num == 0) 4913 rtl8xxxu_stop_tx_beacon(priv); 4914 4915 /* joinbss sequence */ 4916 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT, 4917 0xc000 | vif->cfg.aid); 4918 4919 priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, true); 4920 } else { 4921 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4922 val8 |= BEACON_DISABLE_TSF_UPDATE; 4923 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4924 4925 priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, false); 4926 } 4927 } 4928 4929 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 4930 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n", 4931 bss_conf->use_short_preamble); 4932 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4933 if (bss_conf->use_short_preamble) 4934 val32 |= RSR_ACK_SHORT_PREAMBLE; 4935 else 4936 val32 &= ~RSR_ACK_SHORT_PREAMBLE; 4937 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4938 } 4939 4940 if (changed & BSS_CHANGED_ERP_SLOT) { 4941 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n", 4942 bss_conf->use_short_slot); 4943 4944 if (bss_conf->use_short_slot) 4945 val8 = 9; 4946 else 4947 val8 = 20; 4948 rtl8xxxu_write8(priv, REG_SLOT, val8); 4949 4950 rtl8xxxu_set_aifs(priv, val8); 4951 } 4952 4953 if (changed & BSS_CHANGED_BSSID) { 4954 dev_dbg(dev, "Changed BSSID!\n"); 4955 rtl8xxxu_set_bssid(priv, bss_conf->bssid, rtlvif->port_num); 4956 } 4957 4958 if (changed & BSS_CHANGED_BASIC_RATES) { 4959 dev_dbg(dev, "Changed BASIC_RATES!\n"); 4960 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates); 4961 } 4962 4963 if (changed & BSS_CHANGED_BEACON_ENABLED) { 4964 if (bss_conf->enable_beacon) { 4965 rtl8xxxu_start_tx_beacon(priv); 4966 schedule_delayed_work(&priv->update_beacon_work, 0); 4967 } else { 4968 rtl8xxxu_stop_tx_beacon(priv); 4969 } 4970 } 4971 4972 if (changed & BSS_CHANGED_BEACON) 4973 schedule_delayed_work(&priv->update_beacon_work, 0); 4974 4975error: 4976 return; 4977} 4978 4979static int rtl8xxxu_start_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 4980 struct ieee80211_bss_conf *link_conf) 4981{ 4982 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; 4983 struct rtl8xxxu_priv *priv = hw->priv; 4984 struct device *dev = &priv->udev->dev; 4985 4986 dev_dbg(dev, "Start AP mode\n"); 4987 rtl8xxxu_set_bssid(priv, vif->bss_conf.bssid, rtlvif->port_num); 4988 rtl8xxxu_write16(priv, REG_BCN_INTERVAL, vif->bss_conf.beacon_int); 4989 priv->fops->report_connect(priv, RTL8XXXU_BC_MC_MACID, 0, true); 4990 4991 return 0; 4992} 4993 4994static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue) 4995{ 4996 u32 rtlqueue; 4997 4998 switch (queue) { 4999 case IEEE80211_AC_VO: 5000 rtlqueue = TXDESC_QUEUE_VO; 5001 break; 5002 case IEEE80211_AC_VI: 5003 rtlqueue = TXDESC_QUEUE_VI; 5004 break; 5005 case IEEE80211_AC_BE: 5006 rtlqueue = TXDESC_QUEUE_BE; 5007 break; 5008 case IEEE80211_AC_BK: 5009 rtlqueue = TXDESC_QUEUE_BK; 5010 break; 5011 default: 5012 rtlqueue = TXDESC_QUEUE_BE; 5013 } 5014 5015 return rtlqueue; 5016} 5017 5018static u32 rtl8xxxu_queue_select(struct ieee80211_hdr *hdr, struct sk_buff *skb) 5019{ 5020 u32 queue; 5021 5022 if (unlikely(ieee80211_is_beacon(hdr->frame_control))) 5023 queue = TXDESC_QUEUE_BEACON; 5024 else if (ieee80211_is_mgmt(hdr->frame_control)) 5025 queue = TXDESC_QUEUE_MGNT; 5026 else 5027 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb)); 5028 5029 return queue; 5030} 5031 5032/* 5033 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor 5034 * format. The descriptor checksum is still only calculated over the 5035 * initial 32 bytes of the descriptor! 5036 */ 5037static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc) 5038{ 5039 __le16 *ptr = (__le16 *)tx_desc; 5040 u16 csum = 0; 5041 int i; 5042 5043 /* 5044 * Clear csum field before calculation, as the csum field is 5045 * in the middle of the struct. 5046 */ 5047 tx_desc->csum = cpu_to_le16(0); 5048 5049 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++) 5050 csum = csum ^ le16_to_cpu(ptr[i]); 5051 5052 tx_desc->csum |= cpu_to_le16(csum); 5053} 5054 5055static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv) 5056{ 5057 struct rtl8xxxu_tx_urb *tx_urb, *tmp; 5058 unsigned long flags; 5059 5060 spin_lock_irqsave(&priv->tx_urb_lock, flags); 5061 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) { 5062 list_del(&tx_urb->list); 5063 priv->tx_urb_free_count--; 5064 usb_free_urb(&tx_urb->urb); 5065 } 5066 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 5067} 5068 5069static struct rtl8xxxu_tx_urb * 5070rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv) 5071{ 5072 struct rtl8xxxu_tx_urb *tx_urb; 5073 unsigned long flags; 5074 5075 spin_lock_irqsave(&priv->tx_urb_lock, flags); 5076 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list, 5077 struct rtl8xxxu_tx_urb, list); 5078 if (tx_urb) { 5079 list_del(&tx_urb->list); 5080 priv->tx_urb_free_count--; 5081 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER && 5082 !priv->tx_stopped) { 5083 priv->tx_stopped = true; 5084 ieee80211_stop_queues(priv->hw); 5085 } 5086 } 5087 5088 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 5089 5090 return tx_urb; 5091} 5092 5093static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv, 5094 struct rtl8xxxu_tx_urb *tx_urb) 5095{ 5096 unsigned long flags; 5097 5098 INIT_LIST_HEAD(&tx_urb->list); 5099 5100 spin_lock_irqsave(&priv->tx_urb_lock, flags); 5101 5102 list_add(&tx_urb->list, &priv->tx_urb_free_list); 5103 priv->tx_urb_free_count++; 5104 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER && 5105 priv->tx_stopped) { 5106 priv->tx_stopped = false; 5107 ieee80211_wake_queues(priv->hw); 5108 } 5109 5110 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 5111} 5112 5113static void rtl8xxxu_tx_complete(struct urb *urb) 5114{ 5115 struct sk_buff *skb = (struct sk_buff *)urb->context; 5116 struct ieee80211_tx_info *tx_info; 5117 struct ieee80211_hw *hw; 5118 struct rtl8xxxu_priv *priv; 5119 struct rtl8xxxu_tx_urb *tx_urb = 5120 container_of(urb, struct rtl8xxxu_tx_urb, urb); 5121 5122 tx_info = IEEE80211_SKB_CB(skb); 5123 hw = tx_info->rate_driver_data[0]; 5124 priv = hw->priv; 5125 5126 skb_pull(skb, priv->fops->tx_desc_size); 5127 5128 ieee80211_tx_info_clear_status(tx_info); 5129 tx_info->status.rates[0].idx = -1; 5130 tx_info->status.rates[0].count = 0; 5131 5132 if (!urb->status) 5133 tx_info->flags |= IEEE80211_TX_STAT_ACK; 5134 5135 ieee80211_tx_status_irqsafe(hw, skb); 5136 5137 rtl8xxxu_free_tx_urb(priv, tx_urb); 5138} 5139 5140static void rtl8xxxu_dump_action(struct device *dev, 5141 struct ieee80211_hdr *hdr) 5142{ 5143 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr; 5144 u16 cap, timeout; 5145 5146 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION)) 5147 return; 5148 5149 switch (mgmt->u.action.u.addba_resp.action_code) { 5150 case WLAN_ACTION_ADDBA_RESP: 5151 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab); 5152 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout); 5153 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: " 5154 "timeout %i, tid %02x, buf_size %02x, policy %02x, " 5155 "status %02x\n", 5156 timeout, 5157 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, 5158 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, 5159 (cap >> 1) & 0x1, 5160 le16_to_cpu(mgmt->u.action.u.addba_resp.status)); 5161 break; 5162 case WLAN_ACTION_ADDBA_REQ: 5163 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab); 5164 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout); 5165 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: " 5166 "timeout %i, tid %02x, buf_size %02x, policy %02x\n", 5167 timeout, 5168 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, 5169 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, 5170 (cap >> 1) & 0x1); 5171 break; 5172 default: 5173 dev_info(dev, "action frame %02x\n", 5174 mgmt->u.action.u.addba_resp.action_code); 5175 break; 5176 } 5177} 5178 5179/* 5180 * Fill in v1 (gen1) specific TX descriptor bits. 5181 * This format is used on 8188cu/8192cu/8723au 5182 */ 5183void 5184rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 5185 struct ieee80211_tx_info *tx_info, 5186 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 5187 bool short_preamble, bool ampdu_enable, u32 rts_rate, 5188 u8 macid) 5189{ 5190 struct rtl8xxxu_priv *priv = hw->priv; 5191 struct device *dev = &priv->udev->dev; 5192 u8 *qc = ieee80211_get_qos_ctl(hdr); 5193 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 5194 u32 rate = 0; 5195 u16 seq_number; 5196 5197 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) 5198 dev_info(dev, "%s: TX rate: %d, pkt size %u\n", 5199 __func__, rate, le16_to_cpu(tx_desc->pkt_size)); 5200 5201 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 5202 5203 tx_desc->txdw5 = cpu_to_le32(rate); 5204 5205 if (ieee80211_is_data(hdr->frame_control)) 5206 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00); 5207 5208 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT); 5209 5210 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational)) 5211 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE); 5212 else 5213 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK); 5214 5215 if (ieee80211_is_mgmt(hdr->frame_control)) { 5216 tx_desc->txdw5 = cpu_to_le32(rate); 5217 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); 5218 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT); 5219 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE); 5220 } 5221 5222 if (ieee80211_is_data_qos(hdr->frame_control)) { 5223 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS); 5224 5225 if (conf_is_ht40(&hw->conf)) { 5226 tx_desc->txdw4 |= cpu_to_le32(TXDESC_DATA_BW); 5227 5228 if (conf_is_ht40_minus(&hw->conf)) 5229 tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_UPPER); 5230 else 5231 tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_LOWER); 5232 } 5233 } 5234 5235 if (short_preamble) 5236 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE); 5237 5238 if (sgi) 5239 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI); 5240 5241 /* 5242 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled 5243 */ 5244 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT); 5245 if (ampdu_enable || tx_info->control.use_rts) { 5246 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE); 5247 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 5248 } else if (tx_info->control.use_cts_prot) { 5249 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE); 5250 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 5251 } 5252} 5253 5254/* 5255 * Fill in v2 (gen2) specific TX descriptor bits. 5256 * This format is used on 8192eu/8723bu 5257 */ 5258void 5259rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 5260 struct ieee80211_tx_info *tx_info, 5261 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 5262 bool short_preamble, bool ampdu_enable, u32 rts_rate, 5263 u8 macid) 5264{ 5265 struct rtl8xxxu_priv *priv = hw->priv; 5266 struct device *dev = &priv->udev->dev; 5267 struct rtl8xxxu_txdesc40 *tx_desc40; 5268 u8 *qc = ieee80211_get_qos_ctl(hdr); 5269 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 5270 u32 rate = 0; 5271 u16 seq_number; 5272 5273 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32; 5274 5275 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) 5276 dev_info(dev, "%s: TX rate: %d, pkt size %u\n", 5277 __func__, rate, le16_to_cpu(tx_desc40->pkt_size)); 5278 5279 tx_desc40->txdw1 |= cpu_to_le32(macid << TXDESC40_MACID_SHIFT); 5280 5281 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 5282 5283 tx_desc40->txdw4 = cpu_to_le32(rate); 5284 if (ieee80211_is_data(hdr->frame_control)) { 5285 tx_desc40->txdw4 |= cpu_to_le32(0x1f << 5286 TXDESC40_DATA_RATE_FB_SHIFT); 5287 } 5288 5289 tx_desc40->txdw9 = cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT); 5290 5291 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational)) 5292 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE); 5293 else 5294 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK); 5295 5296 if (ieee80211_is_mgmt(hdr->frame_control)) { 5297 tx_desc40->txdw4 = cpu_to_le32(rate); 5298 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_USE_DRIVER_RATE); 5299 tx_desc40->txdw4 |= 5300 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT); 5301 tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE); 5302 } 5303 5304 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) 5305 tx_desc40->txdw8 |= cpu_to_le32(TXDESC40_HW_SEQ_ENABLE); 5306 5307 if (short_preamble) 5308 tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE); 5309 5310 tx_desc40->txdw4 |= cpu_to_le32(rts_rate << TXDESC40_RTS_RATE_SHIFT); 5311 5312 /* 5313 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled 5314 */ 5315 if (ampdu_enable || tx_info->control.use_rts) { 5316 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE); 5317 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE); 5318 } else if (tx_info->control.use_cts_prot) { 5319 /* 5320 * For some reason the vendor driver doesn't set 5321 * TXDESC40_HW_RTS_ENABLE for CTS to SELF 5322 */ 5323 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_CTS_SELF_ENABLE); 5324 } 5325} 5326 5327/* 5328 * Fill in v3 (gen1) specific TX descriptor bits. 5329 * This format is a hybrid between the v1 and v2 formats, only seen 5330 * on 8188eu devices so far. 5331 */ 5332void 5333rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 5334 struct ieee80211_tx_info *tx_info, 5335 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 5336 bool short_preamble, bool ampdu_enable, u32 rts_rate, 5337 u8 macid) 5338{ 5339 struct rtl8xxxu_priv *priv = hw->priv; 5340 struct device *dev = &priv->udev->dev; 5341 struct rtl8xxxu_ra_info *ra = &priv->ra_info; 5342 u8 *qc = ieee80211_get_qos_ctl(hdr); 5343 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 5344 u32 rate = 0; 5345 u16 seq_number; 5346 5347 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 5348 5349 if (ieee80211_is_data(hdr->frame_control)) { 5350 rate = ra->decision_rate; 5351 tx_desc->txdw5 = cpu_to_le32(rate); 5352 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); 5353 tx_desc->txdw4 |= le32_encode_bits(ra->pt_stage, TXDESC32_PT_STAGE_MASK); 5354 /* Data/RTS rate FB limit */ 5355 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00); 5356 } 5357 5358 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) 5359 dev_info(dev, "%s: TX rate: %d, pkt size %d\n", 5360 __func__, rate, le16_to_cpu(tx_desc->pkt_size)); 5361 5362 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT); 5363 5364 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational)) 5365 tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE); 5366 else 5367 tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK); 5368 5369 if (ieee80211_is_mgmt(hdr->frame_control)) { 5370 tx_desc->txdw5 = cpu_to_le32(rate); 5371 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); 5372 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT); 5373 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE); 5374 } 5375 5376 if (ieee80211_is_data_qos(hdr->frame_control)) { 5377 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS); 5378 5379 if (conf_is_ht40(&hw->conf)) { 5380 tx_desc->txdw4 |= cpu_to_le32(TXDESC_DATA_BW); 5381 5382 if (conf_is_ht40_minus(&hw->conf)) 5383 tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_UPPER); 5384 else 5385 tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_LOWER); 5386 } 5387 } 5388 5389 if (short_preamble) 5390 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE); 5391 5392 if (sgi && ra->rate_sgi) 5393 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI); 5394 5395 /* 5396 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled 5397 */ 5398 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT); 5399 if (ampdu_enable || tx_info->control.use_rts) { 5400 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE); 5401 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 5402 } else if (tx_info->control.use_cts_prot) { 5403 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE); 5404 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 5405 } 5406 5407 tx_desc->txdw2 |= cpu_to_le32(TXDESC_ANTENNA_SELECT_A | 5408 TXDESC_ANTENNA_SELECT_B); 5409 tx_desc->txdw7 |= cpu_to_le16(TXDESC_ANTENNA_SELECT_C >> 16); 5410} 5411 5412static void rtl8xxxu_tx(struct ieee80211_hw *hw, 5413 struct ieee80211_tx_control *control, 5414 struct sk_buff *skb) 5415{ 5416 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 5417 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 5418 struct rtl8xxxu_priv *priv = hw->priv; 5419 struct rtl8xxxu_txdesc32 *tx_desc; 5420 struct rtl8xxxu_tx_urb *tx_urb; 5421 struct ieee80211_sta *sta = NULL; 5422 struct ieee80211_vif *vif = tx_info->control.vif; 5423 struct rtl8xxxu_vif *rtlvif = vif ? (struct rtl8xxxu_vif *)vif->drv_priv : NULL; 5424 struct device *dev = &priv->udev->dev; 5425 u32 queue, rts_rate; 5426 u16 pktlen = skb->len; 5427 int tx_desc_size = priv->fops->tx_desc_size; 5428 u8 macid; 5429 int ret; 5430 bool ampdu_enable, sgi = false, short_preamble = false, bmc = false; 5431 5432 if (skb_headroom(skb) < tx_desc_size) { 5433 dev_warn(dev, 5434 "%s: Not enough headroom (%i) for tx descriptor\n", 5435 __func__, skb_headroom(skb)); 5436 goto error; 5437 } 5438 5439 if (unlikely(skb->len > (65535 - tx_desc_size))) { 5440 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n", 5441 __func__, skb->len); 5442 goto error; 5443 } 5444 5445 tx_urb = rtl8xxxu_alloc_tx_urb(priv); 5446 if (!tx_urb) { 5447 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__); 5448 goto error; 5449 } 5450 5451 if (ieee80211_is_action(hdr->frame_control)) 5452 rtl8xxxu_dump_action(dev, hdr); 5453 5454 tx_info->rate_driver_data[0] = hw; 5455 5456 if (control && control->sta) 5457 sta = control->sta; 5458 5459 queue = rtl8xxxu_queue_select(hdr, skb); 5460 5461 tx_desc = skb_push(skb, tx_desc_size); 5462 5463 memset(tx_desc, 0, tx_desc_size); 5464 tx_desc->pkt_size = cpu_to_le16(pktlen); 5465 tx_desc->pkt_offset = tx_desc_size; 5466 5467 /* These bits mean different things to the RTL8192F. */ 5468 if (priv->rtl_chip != RTL8192F) 5469 tx_desc->txdw0 = 5470 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT; 5471 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) || 5472 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) { 5473 tx_desc->txdw0 |= TXDESC_BROADMULTICAST; 5474 bmc = true; 5475 } 5476 5477 5478 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT); 5479 macid = rtl8xxxu_get_macid(priv, sta); 5480 5481 if (tx_info->control.hw_key) { 5482 switch (tx_info->control.hw_key->cipher) { 5483 case WLAN_CIPHER_SUITE_WEP40: 5484 case WLAN_CIPHER_SUITE_WEP104: 5485 case WLAN_CIPHER_SUITE_TKIP: 5486 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4); 5487 break; 5488 case WLAN_CIPHER_SUITE_CCMP: 5489 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES); 5490 break; 5491 default: 5492 break; 5493 } 5494 if (bmc && rtlvif && rtlvif->hw_key_idx != 0xff) { 5495 tx_desc->txdw1 |= cpu_to_le32(TXDESC_EN_DESC_ID); 5496 macid = rtlvif->hw_key_idx; 5497 } 5498 } 5499 5500 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */ 5501 ampdu_enable = false; 5502 if (ieee80211_is_data_qos(hdr->frame_control) && sta) { 5503 if (sta->deflink.ht_cap.ht_supported) { 5504 u32 ampdu, val32; 5505 u8 *qc = ieee80211_get_qos_ctl(hdr); 5506 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 5507 5508 ampdu = (u32)sta->deflink.ht_cap.ampdu_density; 5509 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT; 5510 tx_desc->txdw2 |= cpu_to_le32(val32); 5511 5512 ampdu_enable = true; 5513 5514 if (!test_bit(tid, priv->tx_aggr_started) && 5515 !(skb->protocol == cpu_to_be16(ETH_P_PAE))) 5516 if (!ieee80211_start_tx_ba_session(sta, tid, 0)) 5517 set_bit(tid, priv->tx_aggr_started); 5518 } 5519 } 5520 5521 if (ieee80211_is_data_qos(hdr->frame_control) && 5522 sta && sta->deflink.ht_cap.cap & 5523 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) 5524 sgi = true; 5525 5526 if (sta && vif && vif->bss_conf.use_short_preamble) 5527 short_preamble = true; 5528 5529 if (skb->len > hw->wiphy->rts_threshold) 5530 tx_info->control.use_rts = true; 5531 5532 if (sta && vif && vif->bss_conf.use_cts_prot) 5533 tx_info->control.use_cts_prot = true; 5534 5535 if (ampdu_enable || tx_info->control.use_rts || 5536 tx_info->control.use_cts_prot) 5537 rts_rate = DESC_RATE_24M; 5538 else 5539 rts_rate = 0; 5540 5541 priv->fops->fill_txdesc(hw, hdr, tx_info, tx_desc, sgi, short_preamble, 5542 ampdu_enable, rts_rate, macid); 5543 5544 rtl8xxxu_calc_tx_desc_csum(tx_desc); 5545 5546 /* avoid zero checksum make tx hang */ 5547 if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F) 5548 tx_desc->csum = ~tx_desc->csum; 5549 5550 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue], 5551 skb->data, skb->len, rtl8xxxu_tx_complete, skb); 5552 5553 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor); 5554 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC); 5555 if (ret) { 5556 usb_unanchor_urb(&tx_urb->urb); 5557 rtl8xxxu_free_tx_urb(priv, tx_urb); 5558 goto error; 5559 } 5560 return; 5561error: 5562 dev_kfree_skb(skb); 5563} 5564 5565static void rtl8xxxu_send_beacon_frame(struct ieee80211_hw *hw, 5566 struct ieee80211_vif *vif) 5567{ 5568 struct rtl8xxxu_priv *priv = hw->priv; 5569 struct sk_buff *skb = ieee80211_beacon_get(hw, vif, 0); 5570 struct device *dev = &priv->udev->dev; 5571 int retry; 5572 u8 val8; 5573 5574 /* BCN_VALID, write 1 to clear, cleared by SW */ 5575 val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2); 5576 val8 |= BIT_BCN_VALID >> 16; 5577 rtl8xxxu_write8(priv, REG_TDECTRL + 2, val8); 5578 5579 /* SW_BCN_SEL - Port0 */ 5580 val8 = rtl8xxxu_read8(priv, REG_DWBCN1_CTRL_8723B + 2); 5581 val8 &= ~(BIT_SW_BCN_SEL >> 16); 5582 rtl8xxxu_write8(priv, REG_DWBCN1_CTRL_8723B + 2, val8); 5583 5584 if (skb) 5585 rtl8xxxu_tx(hw, NULL, skb); 5586 5587 retry = 100; 5588 do { 5589 val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2); 5590 if (val8 & (BIT_BCN_VALID >> 16)) 5591 break; 5592 usleep_range(10, 20); 5593 } while (--retry); 5594 5595 if (!retry) 5596 dev_err(dev, "%s: Failed to read beacon valid bit\n", __func__); 5597} 5598 5599static void rtl8xxxu_update_beacon_work_callback(struct work_struct *work) 5600{ 5601 struct rtl8xxxu_priv *priv = 5602 container_of(work, struct rtl8xxxu_priv, update_beacon_work.work); 5603 struct ieee80211_hw *hw = priv->hw; 5604 struct ieee80211_vif *vif = priv->vifs[0]; 5605 5606 if (!vif) { 5607 WARN_ONCE(true, "no vif to update beacon\n"); 5608 return; 5609 } 5610 5611 if (vif->bss_conf.csa_active) { 5612 if (ieee80211_beacon_cntdwn_is_complete(vif, 0)) { 5613 ieee80211_csa_finish(vif, 0); 5614 return; 5615 } 5616 schedule_delayed_work(&priv->update_beacon_work, 5617 msecs_to_jiffies(vif->bss_conf.beacon_int)); 5618 } 5619 rtl8xxxu_send_beacon_frame(hw, vif); 5620} 5621 5622static inline bool rtl8xxxu_is_packet_match_bssid(struct rtl8xxxu_priv *priv, 5623 struct ieee80211_hdr *hdr, 5624 int port_num) 5625{ 5626 return priv->vifs[port_num] && 5627 priv->vifs[port_num]->type == NL80211_IFTYPE_STATION && 5628 priv->vifs[port_num]->cfg.assoc && 5629 ether_addr_equal(priv->vifs[port_num]->bss_conf.bssid, hdr->addr2); 5630} 5631 5632static inline bool rtl8xxxu_is_sta_sta(struct rtl8xxxu_priv *priv) 5633{ 5634 return (priv->vifs[0] && priv->vifs[0]->cfg.assoc && 5635 priv->vifs[0]->type == NL80211_IFTYPE_STATION) && 5636 (priv->vifs[1] && priv->vifs[1]->cfg.assoc && 5637 priv->vifs[1]->type == NL80211_IFTYPE_STATION); 5638} 5639 5640void rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv *priv, 5641 struct ieee80211_rx_status *rx_status, 5642 struct rtl8723au_phy_stats *phy_stats, 5643 u32 rxmcs, struct ieee80211_hdr *hdr, 5644 bool crc_icv_err) 5645{ 5646 if (phy_stats->sgi_en) 5647 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 5648 5649 if (rxmcs < DESC_RATE_6M) { 5650 /* 5651 * Handle PHY stats for CCK rates 5652 */ 5653 rx_status->signal = priv->fops->cck_rssi(priv, phy_stats); 5654 } else { 5655 bool parse_cfo = priv->fops->set_crystal_cap && 5656 !crc_icv_err && 5657 !ieee80211_is_ctl(hdr->frame_control) && 5658 !rtl8xxxu_is_sta_sta(priv) && 5659 (rtl8xxxu_is_packet_match_bssid(priv, hdr, 0) || 5660 rtl8xxxu_is_packet_match_bssid(priv, hdr, 1)); 5661 5662 if (parse_cfo) { 5663 priv->cfo_tracking.cfo_tail[0] = phy_stats->path_cfotail[0]; 5664 priv->cfo_tracking.cfo_tail[1] = phy_stats->path_cfotail[1]; 5665 5666 priv->cfo_tracking.packet_count++; 5667 } 5668 5669 rx_status->signal = 5670 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110; 5671 } 5672} 5673 5674static void jaguar2_rx_parse_phystats_type0(struct rtl8xxxu_priv *priv, 5675 struct ieee80211_rx_status *rx_status, 5676 struct jaguar2_phy_stats_type0 *phy_stats0, 5677 u32 rxmcs, struct ieee80211_hdr *hdr, 5678 bool crc_icv_err) 5679{ 5680 s8 rx_power = phy_stats0->pwdb - 110; 5681 5682 if (!priv->cck_new_agc) 5683 rx_power = priv->fops->cck_rssi(priv, (struct rtl8723au_phy_stats *)phy_stats0); 5684 5685 rx_status->signal = rx_power; 5686} 5687 5688static void jaguar2_rx_parse_phystats_type1(struct rtl8xxxu_priv *priv, 5689 struct ieee80211_rx_status *rx_status, 5690 struct jaguar2_phy_stats_type1 *phy_stats1, 5691 u32 rxmcs, struct ieee80211_hdr *hdr, 5692 bool crc_icv_err) 5693{ 5694 bool parse_cfo = priv->fops->set_crystal_cap && 5695 !crc_icv_err && 5696 !ieee80211_is_ctl(hdr->frame_control) && 5697 !rtl8xxxu_is_sta_sta(priv) && 5698 (rtl8xxxu_is_packet_match_bssid(priv, hdr, 0) || 5699 rtl8xxxu_is_packet_match_bssid(priv, hdr, 1)); 5700 u8 pwdb_max = 0, rxsc; 5701 int rx_path; 5702 5703 if (parse_cfo) { 5704 /* Only path-A and path-B have CFO tail and short CFO */ 5705 priv->cfo_tracking.cfo_tail[RF_A] = phy_stats1->cfo_tail[RF_A]; 5706 priv->cfo_tracking.cfo_tail[RF_B] = phy_stats1->cfo_tail[RF_B]; 5707 5708 priv->cfo_tracking.packet_count++; 5709 } 5710 5711 for (rx_path = 0; rx_path < priv->rx_paths; rx_path++) 5712 pwdb_max = max(pwdb_max, phy_stats1->pwdb[rx_path]); 5713 5714 rx_status->signal = pwdb_max - 110; 5715 5716 if (rxmcs >= DESC_RATE_6M && rxmcs <= DESC_RATE_54M) 5717 rxsc = phy_stats1->l_rxsc; 5718 else 5719 rxsc = phy_stats1->ht_rxsc; 5720 5721 if (phy_stats1->rf_mode == 0 || rxsc == 1 || rxsc == 2) 5722 rx_status->bw = RATE_INFO_BW_20; 5723 else 5724 rx_status->bw = RATE_INFO_BW_40; 5725} 5726 5727static void jaguar2_rx_parse_phystats_type2(struct rtl8xxxu_priv *priv, 5728 struct ieee80211_rx_status *rx_status, 5729 struct jaguar2_phy_stats_type2 *phy_stats2, 5730 u32 rxmcs, struct ieee80211_hdr *hdr, 5731 bool crc_icv_err) 5732{ 5733 u8 pwdb_max = 0; 5734 int rx_path; 5735 5736 for (rx_path = 0; rx_path < priv->rx_paths; rx_path++) 5737 pwdb_max = max(pwdb_max, phy_stats2->pwdb[rx_path]); 5738 5739 rx_status->signal = pwdb_max - 110; 5740} 5741 5742void jaguar2_rx_parse_phystats(struct rtl8xxxu_priv *priv, 5743 struct ieee80211_rx_status *rx_status, 5744 struct rtl8723au_phy_stats *phy_stats, 5745 u32 rxmcs, struct ieee80211_hdr *hdr, 5746 bool crc_icv_err) 5747{ 5748 struct jaguar2_phy_stats_type0 *phy_stats0 = (struct jaguar2_phy_stats_type0 *)phy_stats; 5749 struct jaguar2_phy_stats_type1 *phy_stats1 = (struct jaguar2_phy_stats_type1 *)phy_stats; 5750 struct jaguar2_phy_stats_type2 *phy_stats2 = (struct jaguar2_phy_stats_type2 *)phy_stats; 5751 5752 switch (phy_stats0->page_num) { 5753 case 0: 5754 /* CCK */ 5755 jaguar2_rx_parse_phystats_type0(priv, rx_status, phy_stats0, 5756 rxmcs, hdr, crc_icv_err); 5757 break; 5758 case 1: 5759 /* OFDM */ 5760 jaguar2_rx_parse_phystats_type1(priv, rx_status, phy_stats1, 5761 rxmcs, hdr, crc_icv_err); 5762 break; 5763 case 2: 5764 /* Also OFDM but different (how?) */ 5765 jaguar2_rx_parse_phystats_type2(priv, rx_status, phy_stats2, 5766 rxmcs, hdr, crc_icv_err); 5767 break; 5768 default: 5769 return; 5770 } 5771} 5772 5773static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv) 5774{ 5775 struct rtl8xxxu_rx_urb *rx_urb, *tmp; 5776 unsigned long flags; 5777 5778 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5779 5780 list_for_each_entry_safe(rx_urb, tmp, 5781 &priv->rx_urb_pending_list, list) { 5782 list_del(&rx_urb->list); 5783 priv->rx_urb_pending_count--; 5784 usb_free_urb(&rx_urb->urb); 5785 } 5786 5787 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5788} 5789 5790static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv, 5791 struct rtl8xxxu_rx_urb *rx_urb) 5792{ 5793 struct sk_buff *skb; 5794 unsigned long flags; 5795 int pending = 0; 5796 5797 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5798 5799 if (!priv->shutdown) { 5800 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list); 5801 priv->rx_urb_pending_count++; 5802 pending = priv->rx_urb_pending_count; 5803 } else { 5804 skb = (struct sk_buff *)rx_urb->urb.context; 5805 dev_kfree_skb_irq(skb); 5806 usb_free_urb(&rx_urb->urb); 5807 } 5808 5809 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5810 5811 if (pending > RTL8XXXU_RX_URB_PENDING_WATER) 5812 schedule_work(&priv->rx_urb_wq); 5813} 5814 5815static void rtl8xxxu_rx_urb_work(struct work_struct *work) 5816{ 5817 struct rtl8xxxu_priv *priv; 5818 struct rtl8xxxu_rx_urb *rx_urb, *tmp; 5819 struct list_head local; 5820 struct sk_buff *skb; 5821 unsigned long flags; 5822 int ret; 5823 5824 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq); 5825 INIT_LIST_HEAD(&local); 5826 5827 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5828 5829 list_splice_init(&priv->rx_urb_pending_list, &local); 5830 priv->rx_urb_pending_count = 0; 5831 5832 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5833 5834 list_for_each_entry_safe(rx_urb, tmp, &local, list) { 5835 list_del_init(&rx_urb->list); 5836 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); 5837 /* 5838 * If out of memory or temporary error, put it back on the 5839 * queue and try again. Otherwise the device is dead/gone 5840 * and we should drop it. 5841 */ 5842 switch (ret) { 5843 case 0: 5844 break; 5845 case -ENOMEM: 5846 case -EAGAIN: 5847 rtl8xxxu_queue_rx_urb(priv, rx_urb); 5848 break; 5849 default: 5850 dev_warn(&priv->udev->dev, 5851 "failed to requeue urb with error %i\n", ret); 5852 skb = (struct sk_buff *)rx_urb->urb.context; 5853 dev_kfree_skb(skb); 5854 usb_free_urb(&rx_urb->urb); 5855 } 5856 } 5857} 5858 5859/* 5860 * The RTL8723BU/RTL8192EU vendor driver use coexistence table type 5861 * 0-7 to represent writing different combinations of register values 5862 * to REG_BT_COEX_TABLEs. It's for different kinds of coexistence use 5863 * cases which Realtek doesn't provide detail for these settings. Keep 5864 * this aligned with vendor driver for easier maintenance. 5865 */ 5866static 5867void rtl8723bu_set_coex_with_type(struct rtl8xxxu_priv *priv, u8 type) 5868{ 5869 switch (type) { 5870 case 0: 5871 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); 5872 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555); 5873 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5874 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5875 break; 5876 case 1: 5877 case 3: 5878 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); 5879 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a); 5880 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5881 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5882 break; 5883 case 2: 5884 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); 5885 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a); 5886 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5887 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5888 break; 5889 case 4: 5890 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); 5891 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaa5a5a); 5892 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5893 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5894 break; 5895 case 5: 5896 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); 5897 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaa5a5a5a); 5898 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5899 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5900 break; 5901 case 6: 5902 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); 5903 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa); 5904 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5905 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5906 break; 5907 case 7: 5908 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0xaaaaaaaa); 5909 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa); 5910 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5911 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5912 break; 5913 default: 5914 break; 5915 } 5916} 5917 5918static 5919void rtl8723bu_update_bt_link_info(struct rtl8xxxu_priv *priv, u8 bt_info) 5920{ 5921 struct rtl8xxxu_btcoex *btcoex = &priv->bt_coex; 5922 5923 if (bt_info & BT_INFO_8723B_1ANT_B_INQ_PAGE) 5924 btcoex->c2h_bt_inquiry = true; 5925 else 5926 btcoex->c2h_bt_inquiry = false; 5927 5928 if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) { 5929 btcoex->bt_status = BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE; 5930 btcoex->has_sco = false; 5931 btcoex->has_hid = false; 5932 btcoex->has_pan = false; 5933 btcoex->has_a2dp = false; 5934 } else { 5935 if ((bt_info & 0x1f) == BT_INFO_8723B_1ANT_B_CONNECTION) 5936 btcoex->bt_status = BT_8723B_1ANT_STATUS_CONNECTED_IDLE; 5937 else if ((bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) || 5938 (bt_info & BT_INFO_8723B_1ANT_B_SCO_BUSY)) 5939 btcoex->bt_status = BT_8723B_1ANT_STATUS_SCO_BUSY; 5940 else if (bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY) 5941 btcoex->bt_status = BT_8723B_1ANT_STATUS_ACL_BUSY; 5942 else 5943 btcoex->bt_status = BT_8723B_1ANT_STATUS_MAX; 5944 5945 if (bt_info & BT_INFO_8723B_1ANT_B_FTP) 5946 btcoex->has_pan = true; 5947 else 5948 btcoex->has_pan = false; 5949 5950 if (bt_info & BT_INFO_8723B_1ANT_B_A2DP) 5951 btcoex->has_a2dp = true; 5952 else 5953 btcoex->has_a2dp = false; 5954 5955 if (bt_info & BT_INFO_8723B_1ANT_B_HID) 5956 btcoex->has_hid = true; 5957 else 5958 btcoex->has_hid = false; 5959 5960 if (bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) 5961 btcoex->has_sco = true; 5962 else 5963 btcoex->has_sco = false; 5964 } 5965 5966 if (!btcoex->has_a2dp && !btcoex->has_sco && 5967 !btcoex->has_pan && btcoex->has_hid) 5968 btcoex->hid_only = true; 5969 else 5970 btcoex->hid_only = false; 5971 5972 if (!btcoex->has_sco && !btcoex->has_pan && 5973 !btcoex->has_hid && btcoex->has_a2dp) 5974 btcoex->has_a2dp = true; 5975 else 5976 btcoex->has_a2dp = false; 5977 5978 if (btcoex->bt_status == BT_8723B_1ANT_STATUS_SCO_BUSY || 5979 btcoex->bt_status == BT_8723B_1ANT_STATUS_ACL_BUSY) 5980 btcoex->bt_busy = true; 5981 else 5982 btcoex->bt_busy = false; 5983} 5984 5985static inline bool rtl8xxxu_is_assoc(struct rtl8xxxu_priv *priv) 5986{ 5987 return (priv->vifs[0] && priv->vifs[0]->cfg.assoc) || 5988 (priv->vifs[1] && priv->vifs[1]->cfg.assoc); 5989} 5990 5991static 5992void rtl8723bu_handle_bt_inquiry(struct rtl8xxxu_priv *priv) 5993{ 5994 struct rtl8xxxu_btcoex *btcoex; 5995 5996 btcoex = &priv->bt_coex; 5997 5998 if (!rtl8xxxu_is_assoc(priv)) { 5999 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 6000 rtl8723bu_set_coex_with_type(priv, 0); 6001 } else if (btcoex->has_sco || btcoex->has_hid || btcoex->has_a2dp) { 6002 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 0x3, 0x11, 0x11); 6003 rtl8723bu_set_coex_with_type(priv, 4); 6004 } else if (btcoex->has_pan) { 6005 rtl8723bu_set_ps_tdma(priv, 0x61, 0x3f, 0x3, 0x11, 0x11); 6006 rtl8723bu_set_coex_with_type(priv, 4); 6007 } else { 6008 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 6009 rtl8723bu_set_coex_with_type(priv, 7); 6010 } 6011} 6012 6013static 6014void rtl8723bu_handle_bt_info(struct rtl8xxxu_priv *priv) 6015{ 6016 struct rtl8xxxu_btcoex *btcoex; 6017 6018 btcoex = &priv->bt_coex; 6019 6020 if (rtl8xxxu_is_assoc(priv)) { 6021 u32 val32 = 0; 6022 u32 high_prio_tx = 0, high_prio_rx = 0; 6023 6024 val32 = rtl8xxxu_read32(priv, 0x770); 6025 high_prio_tx = val32 & 0x0000ffff; 6026 high_prio_rx = (val32 & 0xffff0000) >> 16; 6027 6028 if (btcoex->bt_busy) { 6029 if (btcoex->hid_only) { 6030 rtl8723bu_set_ps_tdma(priv, 0x61, 0x20, 6031 0x3, 0x11, 0x11); 6032 rtl8723bu_set_coex_with_type(priv, 5); 6033 } else if (btcoex->a2dp_only) { 6034 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 6035 0x3, 0x11, 0x11); 6036 rtl8723bu_set_coex_with_type(priv, 4); 6037 } else if ((btcoex->has_a2dp && btcoex->has_pan) || 6038 (btcoex->has_hid && btcoex->has_a2dp && 6039 btcoex->has_pan)) { 6040 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21, 6041 0x3, 0x10, 0x10); 6042 rtl8723bu_set_coex_with_type(priv, 4); 6043 } else if (btcoex->has_hid && btcoex->has_a2dp) { 6044 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21, 6045 0x3, 0x10, 0x10); 6046 rtl8723bu_set_coex_with_type(priv, 3); 6047 } else { 6048 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 6049 0x3, 0x11, 0x11); 6050 rtl8723bu_set_coex_with_type(priv, 4); 6051 } 6052 } else { 6053 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 6054 if (high_prio_tx + high_prio_rx <= 60) 6055 rtl8723bu_set_coex_with_type(priv, 2); 6056 else 6057 rtl8723bu_set_coex_with_type(priv, 7); 6058 } 6059 } else { 6060 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 6061 rtl8723bu_set_coex_with_type(priv, 0); 6062 } 6063} 6064 6065static void rtl8xxxu_c2hcmd_callback(struct work_struct *work) 6066{ 6067 struct rtl8xxxu_priv *priv; 6068 struct rtl8723bu_c2h *c2h; 6069 struct sk_buff *skb = NULL; 6070 u8 bt_info = 0; 6071 struct rtl8xxxu_btcoex *btcoex; 6072 struct rtl8xxxu_ra_report *rarpt; 6073 u8 bw; 6074 6075 priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work); 6076 btcoex = &priv->bt_coex; 6077 rarpt = &priv->ra_report; 6078 6079 while (!skb_queue_empty(&priv->c2hcmd_queue)) { 6080 skb = skb_dequeue(&priv->c2hcmd_queue); 6081 6082 c2h = (struct rtl8723bu_c2h *)skb->data; 6083 6084 switch (c2h->id) { 6085 case C2H_8723B_BT_INFO: 6086 bt_info = c2h->bt_info.bt_info; 6087 6088 rtl8723bu_update_bt_link_info(priv, bt_info); 6089 if (btcoex->c2h_bt_inquiry) { 6090 rtl8723bu_handle_bt_inquiry(priv); 6091 break; 6092 } 6093 rtl8723bu_handle_bt_info(priv); 6094 break; 6095 case C2H_8723B_RA_REPORT: 6096 bw = rarpt->txrate.bw; 6097 6098 if (skb->len >= offsetofend(typeof(*c2h), ra_report.bw)) { 6099 if (c2h->ra_report.bw == RTL8XXXU_CHANNEL_WIDTH_40) 6100 bw = RATE_INFO_BW_40; 6101 else 6102 bw = RATE_INFO_BW_20; 6103 } 6104 6105 rtl8xxxu_update_ra_report(rarpt, c2h->ra_report.rate, 6106 c2h->ra_report.sgi, bw); 6107 break; 6108 default: 6109 break; 6110 } 6111 6112 dev_kfree_skb(skb); 6113 } 6114} 6115 6116static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv, 6117 struct sk_buff *skb) 6118{ 6119 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data; 6120 struct device *dev = &priv->udev->dev; 6121 int len; 6122 6123 len = skb->len - 2; 6124 6125 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n", 6126 c2h->id, c2h->seq, len, c2h->bt_info.response_source); 6127 6128 switch(c2h->id) { 6129 case C2H_8723B_BT_INFO: 6130 if (c2h->bt_info.response_source > 6131 BT_INFO_SRC_8723B_BT_ACTIVE_SEND) 6132 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n"); 6133 else 6134 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n"); 6135 6136 if (c2h->bt_info.bt_has_reset) 6137 dev_dbg(dev, "BT has been reset\n"); 6138 if (c2h->bt_info.tx_rx_mask) 6139 dev_dbg(dev, "BT TRx mask\n"); 6140 6141 break; 6142 case C2H_8723B_BT_MP_INFO: 6143 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n", 6144 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status); 6145 break; 6146 case C2H_8723B_RA_REPORT: 6147 dev_dbg(dev, 6148 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n", 6149 c2h->ra_report.rate, c2h->ra_report.sgi, 6150 c2h->ra_report.macid, c2h->ra_report.noisy_state); 6151 break; 6152 default: 6153 dev_info(dev, "Unhandled C2H event %02x seq %02x\n", 6154 c2h->id, c2h->seq); 6155 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE, 6156 16, 1, c2h->raw.payload, len, false); 6157 break; 6158 } 6159 6160 skb_queue_tail(&priv->c2hcmd_queue, skb); 6161 6162 schedule_work(&priv->c2hcmd_work); 6163} 6164 6165static void rtl8188e_c2hcmd_callback(struct work_struct *work) 6166{ 6167 struct rtl8xxxu_priv *priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work); 6168 struct device *dev = &priv->udev->dev; 6169 struct sk_buff *skb = NULL; 6170 struct rtl8xxxu_rxdesc16 *rx_desc; 6171 6172 while (!skb_queue_empty(&priv->c2hcmd_queue)) { 6173 skb = skb_dequeue(&priv->c2hcmd_queue); 6174 6175 rx_desc = (struct rtl8xxxu_rxdesc16 *)(skb->data - sizeof(struct rtl8xxxu_rxdesc16)); 6176 6177 switch (rx_desc->rpt_sel) { 6178 case 1: 6179 dev_dbg(dev, "C2H TX report type 1\n"); 6180 6181 break; 6182 case 2: 6183 dev_dbg(dev, "C2H TX report type 2\n"); 6184 6185 rtl8188e_handle_ra_tx_report2(priv, skb); 6186 6187 break; 6188 case 3: 6189 dev_dbg(dev, "C2H USB interrupt report\n"); 6190 6191 break; 6192 default: 6193 dev_warn(dev, "%s: rpt_sel should not be %d\n", 6194 __func__, rx_desc->rpt_sel); 6195 6196 break; 6197 } 6198 6199 dev_kfree_skb(skb); 6200 } 6201} 6202 6203#define rtl8xxxu_iterate_vifs_atomic(priv, iterator, data) \ 6204 ieee80211_iterate_active_interfaces_atomic((priv)->hw, \ 6205 IEEE80211_IFACE_ITER_NORMAL, iterator, data) 6206 6207struct rtl8xxxu_rx_update_rssi_data { 6208 struct rtl8xxxu_priv *priv; 6209 struct ieee80211_hdr *hdr; 6210 struct ieee80211_rx_status *rx_status; 6211 u8 *bssid; 6212}; 6213 6214static void rtl8xxxu_rx_update_rssi_iter(void *data, u8 *mac, 6215 struct ieee80211_vif *vif) 6216{ 6217 struct rtl8xxxu_rx_update_rssi_data *iter_data = data; 6218 struct ieee80211_sta *sta; 6219 struct ieee80211_hdr *hdr = iter_data->hdr; 6220 struct rtl8xxxu_priv *priv = iter_data->priv; 6221 struct rtl8xxxu_sta_info *sta_info; 6222 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 6223 u8 *bssid = iter_data->bssid; 6224 6225 if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) 6226 return; 6227 6228 if (!(ether_addr_equal(vif->addr, hdr->addr1) || 6229 ieee80211_is_beacon(hdr->frame_control))) 6230 return; 6231 6232 sta = ieee80211_find_sta_by_ifaddr(priv->hw, hdr->addr2, 6233 vif->addr); 6234 if (!sta) 6235 return; 6236 6237 sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; 6238 ewma_rssi_add(&sta_info->avg_rssi, -rx_status->signal); 6239} 6240 6241static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 6242{ 6243 __le16 fc = hdr->frame_control; 6244 u8 *bssid; 6245 6246 if (ieee80211_has_tods(fc)) 6247 bssid = hdr->addr1; 6248 else if (ieee80211_has_fromds(fc)) 6249 bssid = hdr->addr2; 6250 else 6251 bssid = hdr->addr3; 6252 6253 return bssid; 6254} 6255 6256static void rtl8xxxu_rx_update_rssi(struct rtl8xxxu_priv *priv, 6257 struct ieee80211_rx_status *rx_status, 6258 struct ieee80211_hdr *hdr) 6259{ 6260 struct rtl8xxxu_rx_update_rssi_data data = {}; 6261 6262 if (ieee80211_is_ctl(hdr->frame_control)) 6263 return; 6264 6265 data.priv = priv; 6266 data.hdr = hdr; 6267 data.rx_status = rx_status; 6268 data.bssid = get_hdr_bssid(hdr); 6269 6270 rtl8xxxu_iterate_vifs_atomic(priv, rtl8xxxu_rx_update_rssi_iter, &data); 6271} 6272 6273int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb) 6274{ 6275 struct ieee80211_hw *hw = priv->hw; 6276 struct ieee80211_rx_status *rx_status; 6277 struct rtl8xxxu_rxdesc16 *rx_desc; 6278 struct rtl8723au_phy_stats *phy_stats; 6279 struct sk_buff *next_skb = NULL; 6280 __le32 *_rx_desc_le; 6281 u32 *_rx_desc; 6282 int drvinfo_sz, desc_shift; 6283 int i, pkt_cnt, pkt_len, urb_len, pkt_offset; 6284 6285 urb_len = skb->len; 6286 pkt_cnt = 0; 6287 6288 if (urb_len < sizeof(struct rtl8xxxu_rxdesc16)) { 6289 kfree_skb(skb); 6290 return RX_TYPE_ERROR; 6291 } 6292 6293 do { 6294 rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data; 6295 _rx_desc_le = (__le32 *)skb->data; 6296 _rx_desc = (u32 *)skb->data; 6297 6298 for (i = 0; 6299 i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++) 6300 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); 6301 6302 /* 6303 * Only read pkt_cnt from the header if we're parsing the 6304 * first packet 6305 */ 6306 if (!pkt_cnt) 6307 pkt_cnt = rx_desc->pkt_cnt; 6308 pkt_len = rx_desc->pktlen; 6309 6310 drvinfo_sz = rx_desc->drvinfo_sz * 8; 6311 desc_shift = rx_desc->shift; 6312 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift + 6313 sizeof(struct rtl8xxxu_rxdesc16), 128); 6314 6315 /* 6316 * Only clone the skb if there's enough data at the end to 6317 * at least cover the rx descriptor 6318 */ 6319 if (pkt_cnt > 1 && 6320 urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc16))) 6321 next_skb = skb_clone(skb, GFP_ATOMIC); 6322 6323 rx_status = IEEE80211_SKB_RXCB(skb); 6324 memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); 6325 6326 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16)); 6327 6328 if (rx_desc->rpt_sel) { 6329 skb_queue_tail(&priv->c2hcmd_queue, skb); 6330 schedule_work(&priv->c2hcmd_work); 6331 } else { 6332 struct ieee80211_hdr *hdr; 6333 6334 phy_stats = (struct rtl8723au_phy_stats *)skb->data; 6335 6336 skb_pull(skb, drvinfo_sz + desc_shift); 6337 6338 skb_trim(skb, pkt_len); 6339 6340 hdr = (struct ieee80211_hdr *)skb->data; 6341 if (rx_desc->phy_stats) { 6342 priv->fops->parse_phystats( 6343 priv, rx_status, phy_stats, 6344 rx_desc->rxmcs, 6345 hdr, 6346 rx_desc->crc32 || rx_desc->icverr); 6347 if (!rx_desc->crc32 && !rx_desc->icverr) 6348 rtl8xxxu_rx_update_rssi(priv, 6349 rx_status, 6350 hdr); 6351 } else { 6352 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 6353 } 6354 6355 rx_status->mactime = rx_desc->tsfl; 6356 rx_status->flag |= RX_FLAG_MACTIME_START; 6357 6358 if (!rx_desc->swdec && 6359 rx_desc->security != RX_DESC_ENC_NONE) 6360 rx_status->flag |= RX_FLAG_DECRYPTED; 6361 if (rx_desc->crc32) 6362 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 6363 if (rx_desc->bw) 6364 rx_status->bw = RATE_INFO_BW_40; 6365 6366 if (rx_desc->rxht) { 6367 rx_status->encoding = RX_ENC_HT; 6368 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; 6369 } else { 6370 rx_status->rate_idx = rx_desc->rxmcs; 6371 } 6372 6373 rx_status->freq = hw->conf.chandef.chan->center_freq; 6374 rx_status->band = hw->conf.chandef.chan->band; 6375 6376 ieee80211_rx_irqsafe(hw, skb); 6377 } 6378 6379 skb = next_skb; 6380 if (skb) 6381 skb_pull(next_skb, pkt_offset); 6382 6383 pkt_cnt--; 6384 urb_len -= pkt_offset; 6385 next_skb = NULL; 6386 } while (skb && pkt_cnt > 0 && 6387 urb_len >= sizeof(struct rtl8xxxu_rxdesc16)); 6388 6389 return RX_TYPE_DATA_PKT; 6390} 6391 6392int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb) 6393{ 6394 struct ieee80211_hw *hw = priv->hw; 6395 struct ieee80211_rx_status *rx_status; 6396 struct rtl8xxxu_rxdesc24 *rx_desc; 6397 struct rtl8723au_phy_stats *phy_stats; 6398 struct sk_buff *next_skb = NULL; 6399 __le32 *_rx_desc_le; 6400 u32 *_rx_desc; 6401 int drvinfo_sz, desc_shift; 6402 int i, pkt_len, urb_len, pkt_offset; 6403 6404 urb_len = skb->len; 6405 6406 if (urb_len < sizeof(struct rtl8xxxu_rxdesc24)) { 6407 kfree_skb(skb); 6408 return RX_TYPE_ERROR; 6409 } 6410 6411 do { 6412 rx_desc = (struct rtl8xxxu_rxdesc24 *)skb->data; 6413 _rx_desc_le = (__le32 *)skb->data; 6414 _rx_desc = (u32 *)skb->data; 6415 6416 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++) 6417 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); 6418 6419 pkt_len = rx_desc->pktlen; 6420 6421 drvinfo_sz = rx_desc->drvinfo_sz * 8; 6422 desc_shift = rx_desc->shift; 6423 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift + 6424 sizeof(struct rtl8xxxu_rxdesc24), 8); 6425 6426 /* 6427 * Only clone the skb if there's enough data at the end to 6428 * at least cover the rx descriptor 6429 */ 6430 if (urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc24))) 6431 next_skb = skb_clone(skb, GFP_ATOMIC); 6432 6433 rx_status = IEEE80211_SKB_RXCB(skb); 6434 memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); 6435 6436 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24)); 6437 6438 phy_stats = (struct rtl8723au_phy_stats *)skb->data; 6439 6440 skb_pull(skb, drvinfo_sz + desc_shift); 6441 6442 skb_trim(skb, pkt_len); 6443 6444 if (rx_desc->rpt_sel) { 6445 struct device *dev = &priv->udev->dev; 6446 dev_dbg(dev, "%s: C2H packet\n", __func__); 6447 rtl8723bu_handle_c2h(priv, skb); 6448 } else { 6449 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 6450 6451 if (rx_desc->phy_stats) { 6452 priv->fops->parse_phystats(priv, rx_status, phy_stats, 6453 rx_desc->rxmcs, hdr, 6454 rx_desc->crc32 || rx_desc->icverr); 6455 if (!rx_desc->crc32 && !rx_desc->icverr) 6456 rtl8xxxu_rx_update_rssi(priv, 6457 rx_status, 6458 hdr); 6459 } else { 6460 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 6461 } 6462 6463 rx_status->mactime = rx_desc->tsfl; 6464 rx_status->flag |= RX_FLAG_MACTIME_START; 6465 6466 if (!rx_desc->swdec && 6467 rx_desc->security != RX_DESC_ENC_NONE) 6468 rx_status->flag |= RX_FLAG_DECRYPTED; 6469 if (rx_desc->crc32) 6470 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 6471 if (rx_desc->bw) 6472 rx_status->bw = RATE_INFO_BW_40; 6473 6474 if (rx_desc->rxmcs >= DESC_RATE_MCS0) { 6475 rx_status->encoding = RX_ENC_HT; 6476 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; 6477 } else { 6478 rx_status->rate_idx = rx_desc->rxmcs; 6479 } 6480 6481 rx_status->freq = hw->conf.chandef.chan->center_freq; 6482 rx_status->band = hw->conf.chandef.chan->band; 6483 6484 ieee80211_rx_irqsafe(hw, skb); 6485 } 6486 6487 skb = next_skb; 6488 if (skb) 6489 skb_pull(next_skb, pkt_offset); 6490 6491 urb_len -= pkt_offset; 6492 next_skb = NULL; 6493 } while (skb && urb_len >= sizeof(struct rtl8xxxu_rxdesc24)); 6494 6495 return RX_TYPE_DATA_PKT; 6496} 6497 6498static void rtl8xxxu_rx_complete(struct urb *urb) 6499{ 6500 struct rtl8xxxu_rx_urb *rx_urb = 6501 container_of(urb, struct rtl8xxxu_rx_urb, urb); 6502 struct ieee80211_hw *hw = rx_urb->hw; 6503 struct rtl8xxxu_priv *priv = hw->priv; 6504 struct sk_buff *skb = (struct sk_buff *)urb->context; 6505 struct device *dev = &priv->udev->dev; 6506 6507 skb_put(skb, urb->actual_length); 6508 6509 if (urb->status == 0) { 6510 priv->fops->parse_rx_desc(priv, skb); 6511 6512 skb = NULL; 6513 rx_urb->urb.context = NULL; 6514 rtl8xxxu_queue_rx_urb(priv, rx_urb); 6515 } else { 6516 dev_dbg(dev, "%s: status %i\n", __func__, urb->status); 6517 goto cleanup; 6518 } 6519 return; 6520 6521cleanup: 6522 usb_free_urb(urb); 6523 dev_kfree_skb(skb); 6524} 6525 6526static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, 6527 struct rtl8xxxu_rx_urb *rx_urb) 6528{ 6529 struct rtl8xxxu_fileops *fops = priv->fops; 6530 struct sk_buff *skb; 6531 int skb_size; 6532 int ret, rx_desc_sz; 6533 6534 rx_desc_sz = fops->rx_desc_size; 6535 6536 if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) { 6537 skb_size = fops->rx_agg_buf_size; 6538 skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats)); 6539 } else { 6540 skb_size = IEEE80211_MAX_FRAME_LEN + rx_desc_sz; 6541 } 6542 6543 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL); 6544 if (!skb) 6545 return -ENOMEM; 6546 6547 memset(skb->data, 0, rx_desc_sz); 6548 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data, 6549 skb_size, rtl8xxxu_rx_complete, skb); 6550 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor); 6551 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC); 6552 if (ret) 6553 usb_unanchor_urb(&rx_urb->urb); 6554 return ret; 6555} 6556 6557static void rtl8xxxu_int_complete(struct urb *urb) 6558{ 6559 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context; 6560 struct device *dev = &priv->udev->dev; 6561 int ret; 6562 6563 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_INTERRUPT) 6564 dev_dbg(dev, "%s: status %i\n", __func__, urb->status); 6565 if (urb->status == 0) { 6566 usb_anchor_urb(urb, &priv->int_anchor); 6567 ret = usb_submit_urb(urb, GFP_ATOMIC); 6568 if (ret) 6569 usb_unanchor_urb(urb); 6570 } else { 6571 dev_dbg(dev, "%s: Error %i\n", __func__, urb->status); 6572 } 6573} 6574 6575 6576static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw) 6577{ 6578 struct rtl8xxxu_priv *priv = hw->priv; 6579 struct urb *urb; 6580 u32 val32; 6581 int ret; 6582 6583 urb = usb_alloc_urb(0, GFP_KERNEL); 6584 if (!urb) 6585 return -ENOMEM; 6586 6587 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt, 6588 priv->int_buf, USB_INTR_CONTENT_LENGTH, 6589 rtl8xxxu_int_complete, priv, 1); 6590 usb_anchor_urb(urb, &priv->int_anchor); 6591 ret = usb_submit_urb(urb, GFP_KERNEL); 6592 if (ret) { 6593 usb_unanchor_urb(urb); 6594 goto error; 6595 } 6596 6597 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR); 6598 val32 |= USB_HIMR_CPWM; 6599 rtl8xxxu_write32(priv, REG_USB_HIMR, val32); 6600 6601error: 6602 usb_free_urb(urb); 6603 return ret; 6604} 6605 6606static void rtl8xxxu_switch_ports(struct rtl8xxxu_priv *priv) 6607{ 6608 u8 macid[ETH_ALEN], bssid[ETH_ALEN], macid_1[ETH_ALEN], bssid_1[ETH_ALEN]; 6609 u8 msr, bcn_ctrl, bcn_ctrl_1, atimwnd[2], atimwnd_1[2]; 6610 struct rtl8xxxu_vif *rtlvif; 6611 u8 tsftr[8], tsftr_1[8]; 6612 int i; 6613 6614 msr = rtl8xxxu_read8(priv, REG_MSR); 6615 bcn_ctrl = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 6616 bcn_ctrl_1 = rtl8xxxu_read8(priv, REG_BEACON_CTRL_1); 6617 6618 for (i = 0; i < ARRAY_SIZE(atimwnd); i++) 6619 atimwnd[i] = rtl8xxxu_read8(priv, REG_ATIMWND + i); 6620 for (i = 0; i < ARRAY_SIZE(atimwnd_1); i++) 6621 atimwnd_1[i] = rtl8xxxu_read8(priv, REG_ATIMWND_1 + i); 6622 6623 for (i = 0; i < ARRAY_SIZE(tsftr); i++) 6624 tsftr[i] = rtl8xxxu_read8(priv, REG_TSFTR + i); 6625 for (i = 0; i < ARRAY_SIZE(tsftr); i++) 6626 tsftr_1[i] = rtl8xxxu_read8(priv, REG_TSFTR1 + i); 6627 6628 for (i = 0; i < ARRAY_SIZE(macid); i++) 6629 macid[i] = rtl8xxxu_read8(priv, REG_MACID + i); 6630 6631 for (i = 0; i < ARRAY_SIZE(bssid); i++) 6632 bssid[i] = rtl8xxxu_read8(priv, REG_BSSID + i); 6633 6634 for (i = 0; i < ARRAY_SIZE(macid_1); i++) 6635 macid_1[i] = rtl8xxxu_read8(priv, REG_MACID1 + i); 6636 6637 for (i = 0; i < ARRAY_SIZE(bssid_1); i++) 6638 bssid_1[i] = rtl8xxxu_read8(priv, REG_BSSID1 + i); 6639 6640 /* disable bcn function, disable update TSF */ 6641 rtl8xxxu_write8(priv, REG_BEACON_CTRL, (bcn_ctrl & 6642 (~BEACON_FUNCTION_ENABLE)) | BEACON_DISABLE_TSF_UPDATE); 6643 rtl8xxxu_write8(priv, REG_BEACON_CTRL_1, (bcn_ctrl_1 & 6644 (~BEACON_FUNCTION_ENABLE)) | BEACON_DISABLE_TSF_UPDATE); 6645 6646 /* switch msr */ 6647 msr = (msr & 0xf0) | ((msr & 0x03) << 2) | ((msr & 0x0c) >> 2); 6648 rtl8xxxu_write8(priv, REG_MSR, msr); 6649 6650 /* write port0 */ 6651 rtl8xxxu_write8(priv, REG_BEACON_CTRL, bcn_ctrl_1 & ~BEACON_FUNCTION_ENABLE); 6652 for (i = 0; i < ARRAY_SIZE(atimwnd_1); i++) 6653 rtl8xxxu_write8(priv, REG_ATIMWND + i, atimwnd_1[i]); 6654 for (i = 0; i < ARRAY_SIZE(tsftr_1); i++) 6655 rtl8xxxu_write8(priv, REG_TSFTR + i, tsftr_1[i]); 6656 for (i = 0; i < ARRAY_SIZE(macid_1); i++) 6657 rtl8xxxu_write8(priv, REG_MACID + i, macid_1[i]); 6658 for (i = 0; i < ARRAY_SIZE(bssid_1); i++) 6659 rtl8xxxu_write8(priv, REG_BSSID + i, bssid_1[i]); 6660 6661 /* write port1 */ 6662 rtl8xxxu_write8(priv, REG_BEACON_CTRL_1, bcn_ctrl & ~BEACON_FUNCTION_ENABLE); 6663 for (i = 0; i < ARRAY_SIZE(atimwnd); i++) 6664 rtl8xxxu_write8(priv, REG_ATIMWND_1 + i, atimwnd[i]); 6665 for (i = 0; i < ARRAY_SIZE(tsftr); i++) 6666 rtl8xxxu_write8(priv, REG_TSFTR1 + i, tsftr[i]); 6667 for (i = 0; i < ARRAY_SIZE(macid); i++) 6668 rtl8xxxu_write8(priv, REG_MACID1 + i, macid[i]); 6669 for (i = 0; i < ARRAY_SIZE(bssid); i++) 6670 rtl8xxxu_write8(priv, REG_BSSID1 + i, bssid[i]); 6671 6672 /* write bcn ctl */ 6673 rtl8xxxu_write8(priv, REG_BEACON_CTRL, bcn_ctrl_1); 6674 rtl8xxxu_write8(priv, REG_BEACON_CTRL_1, bcn_ctrl); 6675 swap(priv->vifs[0], priv->vifs[1]); 6676 6677 /* priv->vifs[0] is NULL here, based on how this function is currently 6678 * called from rtl8xxxu_add_interface(). 6679 * When this function will be used in the future for a different 6680 * scenario, please check whether vifs[0] or vifs[1] can be NULL and if 6681 * necessary add code to set port_num = 1. 6682 */ 6683 rtlvif = (struct rtl8xxxu_vif *)priv->vifs[1]->drv_priv; 6684 rtlvif->port_num = 1; 6685} 6686 6687static int rtl8xxxu_add_interface(struct ieee80211_hw *hw, 6688 struct ieee80211_vif *vif) 6689{ 6690 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; 6691 struct rtl8xxxu_priv *priv = hw->priv; 6692 int port_num; 6693 u8 val8; 6694 6695 if (!priv->vifs[0]) 6696 port_num = 0; 6697 else if (!priv->vifs[1]) 6698 port_num = 1; 6699 else 6700 return -EOPNOTSUPP; 6701 6702 switch (vif->type) { 6703 case NL80211_IFTYPE_STATION: 6704 if (port_num == 0) { 6705 rtl8xxxu_stop_tx_beacon(priv); 6706 6707 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 6708 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE | 6709 BEACON_DISABLE_TSF_UPDATE; 6710 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 6711 } 6712 break; 6713 case NL80211_IFTYPE_AP: 6714 if (port_num == 1) { 6715 rtl8xxxu_switch_ports(priv); 6716 port_num = 0; 6717 } 6718 6719 rtl8xxxu_write8(priv, REG_BEACON_CTRL, 6720 BEACON_DISABLE_TSF_UPDATE | BEACON_CTRL_MBSSID); 6721 rtl8xxxu_write8(priv, REG_ATIMWND, 0x0c); /* 12ms */ 6722 rtl8xxxu_write16(priv, REG_TSFTR_SYN_OFFSET, 0x7fff); /* ~32ms */ 6723 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, DUAL_TSF_RESET_TSF0); 6724 6725 /* enable BCN0 function */ 6726 rtl8xxxu_write8(priv, REG_BEACON_CTRL, 6727 BEACON_DISABLE_TSF_UPDATE | 6728 BEACON_FUNCTION_ENABLE | BEACON_CTRL_MBSSID | 6729 BEACON_CTRL_TX_BEACON_RPT); 6730 6731 /* select BCN on port 0 */ 6732 val8 = rtl8xxxu_read8(priv, REG_CCK_CHECK); 6733 val8 &= ~BIT_BCN_PORT_SEL; 6734 rtl8xxxu_write8(priv, REG_CCK_CHECK, val8); 6735 break; 6736 default: 6737 return -EOPNOTSUPP; 6738 } 6739 6740 priv->vifs[port_num] = vif; 6741 rtlvif->port_num = port_num; 6742 rtlvif->hw_key_idx = 0xff; 6743 6744 rtl8xxxu_set_linktype(priv, vif->type, port_num); 6745 ether_addr_copy(priv->mac_addr, vif->addr); 6746 rtl8xxxu_set_mac(priv, port_num); 6747 6748 return 0; 6749} 6750 6751static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw, 6752 struct ieee80211_vif *vif) 6753{ 6754 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; 6755 struct rtl8xxxu_priv *priv = hw->priv; 6756 6757 dev_dbg(&priv->udev->dev, "%s\n", __func__); 6758 6759 priv->vifs[rtlvif->port_num] = NULL; 6760} 6761 6762static int rtl8xxxu_config(struct ieee80211_hw *hw, int radio_idx, u32 changed) 6763{ 6764 struct rtl8xxxu_priv *priv = hw->priv; 6765 struct device *dev = &priv->udev->dev; 6766 int ret = 0, channel; 6767 bool ht40; 6768 6769 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) 6770 dev_info(dev, 6771 "%s: channel: %i (changed %08x chandef.width %02x)\n", 6772 __func__, hw->conf.chandef.chan->hw_value, 6773 changed, hw->conf.chandef.width); 6774 6775 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 6776 switch (hw->conf.chandef.width) { 6777 case NL80211_CHAN_WIDTH_20_NOHT: 6778 case NL80211_CHAN_WIDTH_20: 6779 ht40 = false; 6780 break; 6781 case NL80211_CHAN_WIDTH_40: 6782 ht40 = true; 6783 break; 6784 default: 6785 ret = -ENOTSUPP; 6786 goto exit; 6787 } 6788 6789 channel = hw->conf.chandef.chan->hw_value; 6790 6791 priv->fops->set_tx_power(priv, channel, ht40); 6792 6793 priv->fops->config_channel(hw); 6794 } 6795 6796exit: 6797 return ret; 6798} 6799 6800static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw, 6801 struct ieee80211_vif *vif, 6802 unsigned int link_id, u16 queue, 6803 const struct ieee80211_tx_queue_params *param) 6804{ 6805 struct rtl8xxxu_priv *priv = hw->priv; 6806 struct device *dev = &priv->udev->dev; 6807 u32 val32; 6808 u8 aifs, acm_ctrl, acm_bit; 6809 6810 aifs = param->aifs; 6811 6812 val32 = aifs | 6813 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT | 6814 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT | 6815 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT; 6816 6817 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL); 6818 dev_dbg(dev, 6819 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n", 6820 __func__, queue, val32, param->acm, acm_ctrl); 6821 6822 switch (queue) { 6823 case IEEE80211_AC_VO: 6824 acm_bit = ACM_HW_CTRL_VO; 6825 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32); 6826 break; 6827 case IEEE80211_AC_VI: 6828 acm_bit = ACM_HW_CTRL_VI; 6829 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32); 6830 break; 6831 case IEEE80211_AC_BE: 6832 acm_bit = ACM_HW_CTRL_BE; 6833 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32); 6834 break; 6835 case IEEE80211_AC_BK: 6836 acm_bit = ACM_HW_CTRL_BK; 6837 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32); 6838 break; 6839 default: 6840 acm_bit = 0; 6841 break; 6842 } 6843 6844 if (param->acm) 6845 acm_ctrl |= acm_bit; 6846 else 6847 acm_ctrl &= ~acm_bit; 6848 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl); 6849 6850 return 0; 6851} 6852 6853static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw, 6854 unsigned int changed_flags, 6855 unsigned int *total_flags, u64 multicast) 6856{ 6857 struct rtl8xxxu_priv *priv = hw->priv; 6858 u32 rcr = priv->regrcr; 6859 6860 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n", 6861 __func__, changed_flags, *total_flags); 6862 6863 /* 6864 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR) 6865 */ 6866 6867 if (*total_flags & FIF_FCSFAIL) 6868 rcr |= RCR_ACCEPT_CRC32; 6869 else 6870 rcr &= ~RCR_ACCEPT_CRC32; 6871 6872 /* 6873 * FIF_PLCPFAIL not supported? 6874 */ 6875 6876 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) 6877 rcr &= ~(RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH); 6878 else 6879 rcr |= RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH; 6880 6881 if (priv->vifs[0] && priv->vifs[0]->type == NL80211_IFTYPE_AP) 6882 rcr &= ~(RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON); 6883 6884 if (*total_flags & FIF_CONTROL) 6885 rcr |= RCR_ACCEPT_CTRL_FRAME; 6886 else 6887 rcr &= ~RCR_ACCEPT_CTRL_FRAME; 6888 6889 if (*total_flags & FIF_OTHER_BSS) 6890 rcr |= RCR_ACCEPT_AP; 6891 else 6892 rcr &= ~RCR_ACCEPT_AP; 6893 6894 if (*total_flags & FIF_PSPOLL) 6895 rcr |= RCR_ACCEPT_PM; 6896 else 6897 rcr &= ~RCR_ACCEPT_PM; 6898 6899 /* 6900 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted 6901 */ 6902 6903 rtl8xxxu_write32(priv, REG_RCR, rcr); 6904 priv->regrcr = rcr; 6905 6906 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC | 6907 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL | 6908 FIF_PROBE_REQ); 6909} 6910 6911static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, int radio_idx, 6912 u32 rts) 6913{ 6914 if (rts > 2347 && rts != (u32)-1) 6915 return -EINVAL; 6916 6917 return 0; 6918} 6919 6920static int rtl8xxxu_get_free_sec_cam(struct ieee80211_hw *hw) 6921{ 6922 struct rtl8xxxu_priv *priv = hw->priv; 6923 6924 return find_first_zero_bit(priv->cam_map, priv->fops->max_sec_cam_num); 6925} 6926 6927static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 6928 struct ieee80211_vif *vif, 6929 struct ieee80211_sta *sta, 6930 struct ieee80211_key_conf *key) 6931{ 6932 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; 6933 struct rtl8xxxu_priv *priv = hw->priv; 6934 struct device *dev = &priv->udev->dev; 6935 u8 mac_addr[ETH_ALEN]; 6936 u8 val8; 6937 u16 val16; 6938 u32 val32; 6939 int retval = -EOPNOTSUPP; 6940 6941 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n", 6942 __func__, cmd, key->cipher, key->keyidx); 6943 6944 if (key->keyidx > 3) 6945 return -EOPNOTSUPP; 6946 6947 switch (key->cipher) { 6948 case WLAN_CIPHER_SUITE_WEP40: 6949 case WLAN_CIPHER_SUITE_WEP104: 6950 6951 break; 6952 case WLAN_CIPHER_SUITE_CCMP: 6953 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 6954 break; 6955 case WLAN_CIPHER_SUITE_TKIP: 6956 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 6957 break; 6958 default: 6959 return -EOPNOTSUPP; 6960 } 6961 6962 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { 6963 dev_dbg(dev, "%s: pairwise key\n", __func__); 6964 ether_addr_copy(mac_addr, sta->addr); 6965 } else { 6966 dev_dbg(dev, "%s: group key\n", __func__); 6967 ether_addr_copy(mac_addr, vif->bss_conf.bssid); 6968 } 6969 6970 val16 = rtl8xxxu_read16(priv, REG_CR); 6971 val16 |= CR_SECURITY_ENABLE; 6972 rtl8xxxu_write16(priv, REG_CR, val16); 6973 6974 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY | 6975 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY; 6976 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY; 6977 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8); 6978 6979 switch (cmd) { 6980 case SET_KEY: 6981 6982 retval = rtl8xxxu_get_free_sec_cam(hw); 6983 if (retval < 0) 6984 return -EOPNOTSUPP; 6985 6986 key->hw_key_idx = retval; 6987 6988 if (vif->type == NL80211_IFTYPE_AP && !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 6989 rtlvif->hw_key_idx = key->hw_key_idx; 6990 6991 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 6992 rtl8xxxu_cam_write(priv, key, mac_addr); 6993 set_bit(key->hw_key_idx, priv->cam_map); 6994 retval = 0; 6995 break; 6996 case DISABLE_KEY: 6997 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000); 6998 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE | 6999 key->hw_key_idx << CAM_CMD_KEY_SHIFT; 7000 rtl8xxxu_write32(priv, REG_CAM_CMD, val32); 7001 rtlvif->hw_key_idx = 0xff; 7002 clear_bit(key->hw_key_idx, priv->cam_map); 7003 retval = 0; 7004 break; 7005 default: 7006 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd); 7007 } 7008 7009 return retval; 7010} 7011 7012static int 7013rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 7014 struct ieee80211_ampdu_params *params) 7015{ 7016 struct rtl8xxxu_priv *priv = hw->priv; 7017 struct device *dev = &priv->udev->dev; 7018 u8 ampdu_factor, ampdu_density; 7019 struct ieee80211_sta *sta = params->sta; 7020 u16 tid = params->tid; 7021 enum ieee80211_ampdu_mlme_action action = params->action; 7022 7023 switch (action) { 7024 case IEEE80211_AMPDU_TX_START: 7025 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__); 7026 ampdu_factor = sta->deflink.ht_cap.ampdu_factor; 7027 ampdu_density = sta->deflink.ht_cap.ampdu_density; 7028 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor); 7029 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density); 7030 dev_dbg(dev, 7031 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n", 7032 ampdu_factor, ampdu_density); 7033 return IEEE80211_AMPDU_TX_START_IMMEDIATE; 7034 case IEEE80211_AMPDU_TX_STOP_CONT: 7035 case IEEE80211_AMPDU_TX_STOP_FLUSH: 7036 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 7037 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP\n", __func__); 7038 rtl8xxxu_set_ampdu_factor(priv, 0); 7039 rtl8xxxu_set_ampdu_min_space(priv, 0); 7040 clear_bit(tid, priv->tx_aggr_started); 7041 clear_bit(tid, priv->tid_tx_operational); 7042 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 7043 break; 7044 case IEEE80211_AMPDU_TX_OPERATIONAL: 7045 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_OPERATIONAL\n", __func__); 7046 set_bit(tid, priv->tid_tx_operational); 7047 break; 7048 case IEEE80211_AMPDU_RX_START: 7049 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__); 7050 break; 7051 case IEEE80211_AMPDU_RX_STOP: 7052 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__); 7053 break; 7054 default: 7055 break; 7056 } 7057 return 0; 7058} 7059 7060static void 7061rtl8xxxu_sta_statistics(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 7062 struct ieee80211_sta *sta, struct station_info *sinfo) 7063{ 7064 struct rtl8xxxu_priv *priv = hw->priv; 7065 7066 sinfo->txrate = priv->ra_report.txrate; 7067 sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE); 7068} 7069 7070static u8 rtl8xxxu_signal_to_snr(int signal) 7071{ 7072 if (signal < RTL8XXXU_NOISE_FLOOR_MIN) 7073 signal = RTL8XXXU_NOISE_FLOOR_MIN; 7074 else if (signal > 0) 7075 signal = 0; 7076 return (u8)(signal - RTL8XXXU_NOISE_FLOOR_MIN); 7077} 7078 7079static void rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv *priv, 7080 int signal, struct ieee80211_sta *sta, 7081 bool force) 7082{ 7083 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; 7084 struct ieee80211_hw *hw = priv->hw; 7085 u16 wireless_mode; 7086 u8 rssi_level, ratr_idx; 7087 u8 txbw_40mhz; 7088 u8 snr, snr_thresh_high, snr_thresh_low; 7089 u8 go_up_gap = 5; 7090 u8 macid = rtl8xxxu_get_macid(priv, sta); 7091 7092 rssi_level = sta_info->rssi_level; 7093 snr = rtl8xxxu_signal_to_snr(signal); 7094 snr_thresh_high = RTL8XXXU_SNR_THRESH_HIGH; 7095 snr_thresh_low = RTL8XXXU_SNR_THRESH_LOW; 7096 txbw_40mhz = (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) ? 1 : 0; 7097 7098 switch (rssi_level) { 7099 case RTL8XXXU_RATR_STA_MID: 7100 snr_thresh_high += go_up_gap; 7101 break; 7102 case RTL8XXXU_RATR_STA_LOW: 7103 snr_thresh_high += go_up_gap; 7104 snr_thresh_low += go_up_gap; 7105 break; 7106 default: 7107 break; 7108 } 7109 7110 if (snr > snr_thresh_high) 7111 rssi_level = RTL8XXXU_RATR_STA_HIGH; 7112 else if (snr > snr_thresh_low) 7113 rssi_level = RTL8XXXU_RATR_STA_MID; 7114 else 7115 rssi_level = RTL8XXXU_RATR_STA_LOW; 7116 7117 if (rssi_level != sta_info->rssi_level || force) { 7118 int sgi = 0; 7119 u32 rate_bitmap = 0; 7120 7121 rate_bitmap = (sta->deflink.supp_rates[0] & 0xfff) | 7122 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12) | 7123 (sta->deflink.ht_cap.mcs.rx_mask[1] << 20); 7124 if (sta->deflink.ht_cap.cap & 7125 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) 7126 sgi = 1; 7127 7128 wireless_mode = rtl8xxxu_wireless_mode(hw, sta); 7129 switch (wireless_mode) { 7130 case WIRELESS_MODE_B: 7131 ratr_idx = RATEID_IDX_B; 7132 if (rate_bitmap & 0x0000000c) 7133 rate_bitmap &= 0x0000000d; 7134 else 7135 rate_bitmap &= 0x0000000f; 7136 break; 7137 case WIRELESS_MODE_A: 7138 case WIRELESS_MODE_G: 7139 ratr_idx = RATEID_IDX_G; 7140 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) 7141 rate_bitmap &= 0x00000f00; 7142 else 7143 rate_bitmap &= 0x00000ff0; 7144 break; 7145 case (WIRELESS_MODE_B | WIRELESS_MODE_G): 7146 ratr_idx = RATEID_IDX_BG; 7147 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) 7148 rate_bitmap &= 0x00000f00; 7149 else if (rssi_level == RTL8XXXU_RATR_STA_MID) 7150 rate_bitmap &= 0x00000ff0; 7151 else 7152 rate_bitmap &= 0x00000ff5; 7153 break; 7154 case WIRELESS_MODE_N_24G: 7155 case WIRELESS_MODE_N_5G: 7156 case (WIRELESS_MODE_G | WIRELESS_MODE_N_24G): 7157 case (WIRELESS_MODE_A | WIRELESS_MODE_N_5G): 7158 if (priv->tx_paths == 2 && priv->rx_paths == 2) 7159 ratr_idx = RATEID_IDX_GN_N2SS; 7160 else 7161 ratr_idx = RATEID_IDX_GN_N1SS; 7162 break; 7163 case (WIRELESS_MODE_B | WIRELESS_MODE_G | WIRELESS_MODE_N_24G): 7164 case (WIRELESS_MODE_B | WIRELESS_MODE_N_24G): 7165 if (txbw_40mhz) { 7166 if (priv->tx_paths == 2 && priv->rx_paths == 2) 7167 ratr_idx = RATEID_IDX_BGN_40M_2SS; 7168 else 7169 ratr_idx = RATEID_IDX_BGN_40M_1SS; 7170 } else { 7171 if (priv->tx_paths == 2 && priv->rx_paths == 2) 7172 ratr_idx = RATEID_IDX_BGN_20M_2SS_BN; 7173 else 7174 ratr_idx = RATEID_IDX_BGN_20M_1SS_BN; 7175 } 7176 7177 if (priv->tx_paths == 2 && priv->rx_paths == 2) { 7178 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) { 7179 rate_bitmap &= 0x0f8f0000; 7180 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) { 7181 rate_bitmap &= 0x0f8ff000; 7182 } else { 7183 if (txbw_40mhz) 7184 rate_bitmap &= 0x0f8ff015; 7185 else 7186 rate_bitmap &= 0x0f8ff005; 7187 } 7188 } else { 7189 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) { 7190 rate_bitmap &= 0x000f0000; 7191 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) { 7192 rate_bitmap &= 0x000ff000; 7193 } else { 7194 if (txbw_40mhz) 7195 rate_bitmap &= 0x000ff015; 7196 else 7197 rate_bitmap &= 0x000ff005; 7198 } 7199 } 7200 break; 7201 default: 7202 ratr_idx = RATEID_IDX_BGN_40M_2SS; 7203 rate_bitmap &= 0x0fffffff; 7204 break; 7205 } 7206 7207 sta_info->rssi_level = rssi_level; 7208 priv->fops->update_rate_mask(priv, rate_bitmap, ratr_idx, sgi, txbw_40mhz, macid); 7209 } 7210} 7211 7212static void rtl8xxxu_set_atc_status(struct rtl8xxxu_priv *priv, bool atc_status) 7213{ 7214 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; 7215 u32 val32; 7216 7217 if (atc_status == cfo->atc_status) 7218 return; 7219 7220 cfo->atc_status = atc_status; 7221 7222 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); 7223 if (atc_status) 7224 val32 |= CFO_TRACKING_ATC_STATUS; 7225 else 7226 val32 &= ~CFO_TRACKING_ATC_STATUS; 7227 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); 7228} 7229 7230/* Central frequency offset correction */ 7231static void rtl8xxxu_track_cfo(struct rtl8xxxu_priv *priv) 7232{ 7233 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; 7234 int cfo_khz_a, cfo_khz_b, cfo_average; 7235 int crystal_cap; 7236 7237 if (!rtl8xxxu_is_assoc(priv)) { 7238 /* Reset */ 7239 cfo->adjust = true; 7240 7241 if (cfo->crystal_cap > priv->default_crystal_cap) 7242 priv->fops->set_crystal_cap(priv, cfo->crystal_cap - 1); 7243 else if (cfo->crystal_cap < priv->default_crystal_cap) 7244 priv->fops->set_crystal_cap(priv, cfo->crystal_cap + 1); 7245 7246 rtl8xxxu_set_atc_status(priv, true); 7247 7248 return; 7249 } 7250 7251 if (cfo->packet_count == cfo->packet_count_pre) 7252 /* No new information. */ 7253 return; 7254 7255 cfo->packet_count_pre = cfo->packet_count; 7256 7257 /* CFO_tail[1:0] is S(8,7), (num_subcarrier>>7) x 312.5K = CFO value(K Hz) */ 7258 cfo_khz_a = (int)((cfo->cfo_tail[0] * 3125) / 10) >> 7; 7259 cfo_khz_b = (int)((cfo->cfo_tail[1] * 3125) / 10) >> 7; 7260 7261 if (priv->tx_paths == 1) 7262 cfo_average = cfo_khz_a; 7263 else 7264 cfo_average = (cfo_khz_a + cfo_khz_b) / 2; 7265 7266 dev_dbg(&priv->udev->dev, "cfo_average: %d\n", cfo_average); 7267 7268 if (cfo->adjust) { 7269 if (abs(cfo_average) < CFO_TH_XTAL_LOW) 7270 cfo->adjust = false; 7271 } else { 7272 if (abs(cfo_average) > CFO_TH_XTAL_HIGH) 7273 cfo->adjust = true; 7274 } 7275 7276 /* 7277 * TODO: We should return here only if bluetooth is enabled. 7278 * See the vendor drivers for how to determine that. 7279 */ 7280 if (priv->has_bluetooth) 7281 return; 7282 7283 if (!cfo->adjust) 7284 return; 7285 7286 crystal_cap = cfo->crystal_cap; 7287 7288 if (cfo_average > CFO_TH_XTAL_LOW) 7289 crystal_cap++; 7290 else if (cfo_average < -CFO_TH_XTAL_LOW) 7291 crystal_cap--; 7292 7293 crystal_cap = clamp(crystal_cap, 0, 0x3f); 7294 7295 priv->fops->set_crystal_cap(priv, crystal_cap); 7296 7297 rtl8xxxu_set_atc_status(priv, abs(cfo_average) >= CFO_TH_ATC); 7298} 7299 7300static void rtl8xxxu_ra_iter(void *data, struct ieee80211_sta *sta) 7301{ 7302 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; 7303 struct rtl8xxxu_priv *priv = data; 7304 int signal = -ewma_rssi_read(&sta_info->avg_rssi); 7305 7306 priv->fops->report_rssi(priv, rtl8xxxu_get_macid(priv, sta), 7307 rtl8xxxu_signal_to_snr(signal)); 7308 rtl8xxxu_refresh_rate_mask(priv, signal, sta, false); 7309} 7310 7311struct rtl8xxxu_stas_entry { 7312 struct list_head list; 7313 struct ieee80211_sta *sta; 7314}; 7315 7316struct rtl8xxxu_iter_stas_data { 7317 struct rtl8xxxu_priv *priv; 7318 struct list_head list; 7319}; 7320 7321static void rtl8xxxu_collect_sta_iter(void *data, struct ieee80211_sta *sta) 7322{ 7323 struct rtl8xxxu_iter_stas_data *iter_stas = data; 7324 struct rtl8xxxu_stas_entry *stas_entry; 7325 7326 stas_entry = kmalloc(sizeof(*stas_entry), GFP_ATOMIC); 7327 if (!stas_entry) 7328 return; 7329 7330 stas_entry->sta = sta; 7331 list_add_tail(&stas_entry->list, &iter_stas->list); 7332} 7333 7334static void rtl8xxxu_watchdog_callback(struct work_struct *work) 7335{ 7336 7337 struct rtl8xxxu_iter_stas_data iter_data; 7338 struct rtl8xxxu_stas_entry *sta_entry, *tmp; 7339 struct rtl8xxxu_priv *priv; 7340 7341 priv = container_of(work, struct rtl8xxxu_priv, ra_watchdog.work); 7342 iter_data.priv = priv; 7343 INIT_LIST_HEAD(&iter_data.list); 7344 7345 mutex_lock(&priv->sta_mutex); 7346 ieee80211_iterate_stations_atomic(priv->hw, rtl8xxxu_collect_sta_iter, 7347 &iter_data); 7348 list_for_each_entry_safe(sta_entry, tmp, &iter_data.list, list) { 7349 list_del_init(&sta_entry->list); 7350 rtl8xxxu_ra_iter(priv, sta_entry->sta); 7351 kfree(sta_entry); 7352 } 7353 mutex_unlock(&priv->sta_mutex); 7354 7355 if (priv->fops->set_crystal_cap) 7356 rtl8xxxu_track_cfo(priv); 7357 7358 schedule_delayed_work(&priv->ra_watchdog, 2 * HZ); 7359} 7360 7361static int rtl8xxxu_start(struct ieee80211_hw *hw) 7362{ 7363 struct rtl8xxxu_priv *priv = hw->priv; 7364 struct rtl8xxxu_rx_urb *rx_urb; 7365 struct rtl8xxxu_tx_urb *tx_urb; 7366 struct sk_buff *skb; 7367 unsigned long flags; 7368 int ret, i; 7369 7370 ret = 0; 7371 7372 init_usb_anchor(&priv->rx_anchor); 7373 init_usb_anchor(&priv->tx_anchor); 7374 init_usb_anchor(&priv->int_anchor); 7375 7376 priv->fops->enable_rf(priv); 7377 if (priv->usb_interrupts) { 7378 ret = rtl8xxxu_submit_int_urb(hw); 7379 if (ret) 7380 goto exit; 7381 } 7382 7383 for (i = 0; i < RTL8XXXU_TX_URBS; i++) { 7384 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL); 7385 if (!tx_urb) { 7386 if (!i) 7387 ret = -ENOMEM; 7388 7389 goto error_out; 7390 } 7391 usb_init_urb(&tx_urb->urb); 7392 INIT_LIST_HEAD(&tx_urb->list); 7393 tx_urb->hw = hw; 7394 list_add(&tx_urb->list, &priv->tx_urb_free_list); 7395 priv->tx_urb_free_count++; 7396 } 7397 7398 priv->tx_stopped = false; 7399 7400 spin_lock_irqsave(&priv->rx_urb_lock, flags); 7401 priv->shutdown = false; 7402 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 7403 7404 for (i = 0; i < RTL8XXXU_RX_URBS; i++) { 7405 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL); 7406 if (!rx_urb) { 7407 if (!i) 7408 ret = -ENOMEM; 7409 7410 goto error_out; 7411 } 7412 usb_init_urb(&rx_urb->urb); 7413 INIT_LIST_HEAD(&rx_urb->list); 7414 rx_urb->hw = hw; 7415 7416 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); 7417 if (ret) { 7418 if (ret != -ENOMEM) { 7419 skb = (struct sk_buff *)rx_urb->urb.context; 7420 dev_kfree_skb(skb); 7421 } 7422 rtl8xxxu_queue_rx_urb(priv, rx_urb); 7423 } 7424 } 7425 7426 schedule_delayed_work(&priv->ra_watchdog, 2 * HZ); 7427exit: 7428 /* 7429 * Accept all data and mgmt frames 7430 */ 7431 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); 7432 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); 7433 7434 rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, 7435 OFDM0_X_AGC_CORE1_IGI_MASK, 0x1e); 7436 7437 return ret; 7438 7439error_out: 7440 rtl8xxxu_free_tx_resources(priv); 7441 /* 7442 * Disable all data and mgmt frames 7443 */ 7444 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); 7445 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); 7446 7447 return ret; 7448} 7449 7450static void rtl8xxxu_stop(struct ieee80211_hw *hw, bool suspend) 7451{ 7452 struct rtl8xxxu_priv *priv = hw->priv; 7453 unsigned long flags; 7454 7455 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 7456 7457 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); 7458 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); 7459 7460 spin_lock_irqsave(&priv->rx_urb_lock, flags); 7461 priv->shutdown = true; 7462 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 7463 7464 usb_kill_anchored_urbs(&priv->rx_anchor); 7465 usb_kill_anchored_urbs(&priv->tx_anchor); 7466 if (priv->usb_interrupts) 7467 usb_kill_anchored_urbs(&priv->int_anchor); 7468 7469 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 7470 7471 priv->fops->disable_rf(priv); 7472 7473 /* 7474 * Disable interrupts 7475 */ 7476 if (priv->usb_interrupts) 7477 rtl8xxxu_write32(priv, REG_USB_HIMR, 0); 7478 7479 cancel_work_sync(&priv->c2hcmd_work); 7480 cancel_delayed_work_sync(&priv->ra_watchdog); 7481 cancel_delayed_work_sync(&priv->update_beacon_work); 7482 7483 rtl8xxxu_free_rx_resources(priv); 7484 rtl8xxxu_free_tx_resources(priv); 7485} 7486 7487static int rtl8xxxu_sta_add(struct ieee80211_hw *hw, 7488 struct ieee80211_vif *vif, 7489 struct ieee80211_sta *sta) 7490{ 7491 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; 7492 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; 7493 struct rtl8xxxu_priv *priv = hw->priv; 7494 7495 mutex_lock(&priv->sta_mutex); 7496 ewma_rssi_init(&sta_info->avg_rssi); 7497 if (vif->type == NL80211_IFTYPE_AP) { 7498 sta_info->rssi_level = RTL8XXXU_RATR_STA_INIT; 7499 sta_info->macid = rtl8xxxu_acquire_macid(priv); 7500 if (sta_info->macid >= RTL8XXXU_MAX_MAC_ID_NUM) { 7501 mutex_unlock(&priv->sta_mutex); 7502 return -ENOSPC; 7503 } 7504 7505 rtl8xxxu_refresh_rate_mask(priv, 0, sta, true); 7506 priv->fops->report_connect(priv, sta_info->macid, H2C_MACID_ROLE_STA, true); 7507 } else { 7508 switch (rtlvif->port_num) { 7509 case 0: 7510 sta_info->macid = RTL8XXXU_BC_MC_MACID; 7511 break; 7512 case 1: 7513 sta_info->macid = RTL8XXXU_BC_MC_MACID1; 7514 break; 7515 default: 7516 break; 7517 } 7518 } 7519 mutex_unlock(&priv->sta_mutex); 7520 7521 return 0; 7522} 7523 7524static int rtl8xxxu_sta_remove(struct ieee80211_hw *hw, 7525 struct ieee80211_vif *vif, 7526 struct ieee80211_sta *sta) 7527{ 7528 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; 7529 struct rtl8xxxu_priv *priv = hw->priv; 7530 7531 mutex_lock(&priv->sta_mutex); 7532 if (vif->type == NL80211_IFTYPE_AP) 7533 rtl8xxxu_release_macid(priv, sta_info->macid); 7534 mutex_unlock(&priv->sta_mutex); 7535 7536 return 0; 7537} 7538 7539static const struct ieee80211_ops rtl8xxxu_ops = { 7540 .add_chanctx = ieee80211_emulate_add_chanctx, 7541 .remove_chanctx = ieee80211_emulate_remove_chanctx, 7542 .change_chanctx = ieee80211_emulate_change_chanctx, 7543 .switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx, 7544 .tx = rtl8xxxu_tx, 7545 .wake_tx_queue = ieee80211_handle_wake_tx_queue, 7546 .add_interface = rtl8xxxu_add_interface, 7547 .remove_interface = rtl8xxxu_remove_interface, 7548 .config = rtl8xxxu_config, 7549 .conf_tx = rtl8xxxu_conf_tx, 7550 .bss_info_changed = rtl8xxxu_bss_info_changed, 7551 .start_ap = rtl8xxxu_start_ap, 7552 .configure_filter = rtl8xxxu_configure_filter, 7553 .set_rts_threshold = rtl8xxxu_set_rts_threshold, 7554 .start = rtl8xxxu_start, 7555 .stop = rtl8xxxu_stop, 7556 .sw_scan_start = rtl8xxxu_sw_scan_start, 7557 .sw_scan_complete = rtl8xxxu_sw_scan_complete, 7558 .set_key = rtl8xxxu_set_key, 7559 .ampdu_action = rtl8xxxu_ampdu_action, 7560 .sta_statistics = rtl8xxxu_sta_statistics, 7561 .get_antenna = rtl8xxxu_get_antenna, 7562 .set_tim = rtl8xxxu_set_tim, 7563 .sta_add = rtl8xxxu_sta_add, 7564 .sta_remove = rtl8xxxu_sta_remove, 7565}; 7566 7567static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv, 7568 struct usb_interface *interface) 7569{ 7570 struct usb_interface_descriptor *interface_desc; 7571 struct usb_host_interface *host_interface; 7572 struct usb_endpoint_descriptor *endpoint; 7573 struct device *dev = &priv->udev->dev; 7574 int i, j = 0, endpoints; 7575 u8 dir, xtype, num; 7576 int ret = 0; 7577 7578 host_interface = interface->cur_altsetting; 7579 interface_desc = &host_interface->desc; 7580 endpoints = interface_desc->bNumEndpoints; 7581 7582 for (i = 0; i < endpoints; i++) { 7583 endpoint = &host_interface->endpoint[i].desc; 7584 7585 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK; 7586 num = usb_endpoint_num(endpoint); 7587 xtype = usb_endpoint_type(endpoint); 7588 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 7589 dev_dbg(dev, 7590 "%s: endpoint: dir %02x, # %02x, type %02x\n", 7591 __func__, dir, num, xtype); 7592 if (usb_endpoint_dir_in(endpoint) && 7593 usb_endpoint_xfer_bulk(endpoint)) { 7594 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 7595 dev_dbg(dev, "%s: in endpoint num %i\n", 7596 __func__, num); 7597 7598 if (priv->pipe_in) { 7599 dev_warn(dev, 7600 "%s: Too many IN pipes\n", __func__); 7601 ret = -EINVAL; 7602 goto exit; 7603 } 7604 7605 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num); 7606 } 7607 7608 if (usb_endpoint_dir_in(endpoint) && 7609 usb_endpoint_xfer_int(endpoint)) { 7610 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 7611 dev_dbg(dev, "%s: interrupt endpoint num %i\n", 7612 __func__, num); 7613 7614 if (priv->pipe_interrupt) { 7615 dev_warn(dev, "%s: Too many INTERRUPT pipes\n", 7616 __func__); 7617 ret = -EINVAL; 7618 goto exit; 7619 } 7620 7621 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num); 7622 } 7623 7624 if (usb_endpoint_dir_out(endpoint) && 7625 usb_endpoint_xfer_bulk(endpoint)) { 7626 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 7627 dev_dbg(dev, "%s: out endpoint num %i\n", 7628 __func__, num); 7629 if (j >= RTL8XXXU_OUT_ENDPOINTS) { 7630 dev_warn(dev, 7631 "%s: Too many OUT pipes\n", __func__); 7632 ret = -EINVAL; 7633 goto exit; 7634 } 7635 priv->out_ep[j++] = num; 7636 } 7637 } 7638exit: 7639 priv->nr_out_eps = j; 7640 return ret; 7641} 7642 7643static void rtl8xxxu_init_led(struct rtl8xxxu_priv *priv) 7644{ 7645 struct led_classdev *led = &priv->led_cdev; 7646 7647 if (!priv->fops->led_classdev_brightness_set) 7648 return; 7649 7650 led->brightness_set_blocking = priv->fops->led_classdev_brightness_set; 7651 7652 snprintf(priv->led_name, sizeof(priv->led_name), 7653 "rtl8xxxu-usb%s", dev_name(&priv->udev->dev)); 7654 led->name = priv->led_name; 7655 led->max_brightness = RTL8XXXU_HW_LED_CONTROL; 7656 7657 if (led_classdev_register(&priv->udev->dev, led)) 7658 return; 7659 7660 priv->led_registered = true; 7661 7662 led->brightness = led->max_brightness; 7663 priv->fops->led_classdev_brightness_set(led, led->brightness); 7664} 7665 7666static void rtl8xxxu_deinit_led(struct rtl8xxxu_priv *priv) 7667{ 7668 struct led_classdev *led = &priv->led_cdev; 7669 7670 if (!priv->led_registered) 7671 return; 7672 7673 priv->fops->led_classdev_brightness_set(led, LED_OFF); 7674 led_classdev_unregister(led); 7675} 7676 7677static const struct ieee80211_iface_limit rtl8xxxu_limits[] = { 7678 { .max = 2, .types = BIT(NL80211_IFTYPE_STATION), }, 7679 { .max = 1, .types = BIT(NL80211_IFTYPE_AP), }, 7680}; 7681 7682static const struct ieee80211_iface_combination rtl8xxxu_combinations[] = { 7683 { 7684 .limits = rtl8xxxu_limits, 7685 .n_limits = ARRAY_SIZE(rtl8xxxu_limits), 7686 .max_interfaces = 2, 7687 .num_different_channels = 1, 7688 }, 7689}; 7690 7691static int rtl8xxxu_probe(struct usb_interface *interface, 7692 const struct usb_device_id *id) 7693{ 7694 struct rtl8xxxu_priv *priv; 7695 struct ieee80211_hw *hw; 7696 struct usb_device *udev; 7697 struct ieee80211_supported_band *sband; 7698 int ret; 7699 int untested = 1; 7700 7701 udev = usb_get_dev(interface_to_usbdev(interface)); 7702 7703 switch (id->idVendor) { 7704 case USB_VENDOR_ID_REALTEK: 7705 switch(id->idProduct) { 7706 case 0x1724: 7707 case 0x8176: 7708 case 0x8178: 7709 case 0x817f: 7710 case 0x818b: 7711 case 0xf179: 7712 case 0x8179: 7713 case 0xb711: 7714 case 0xf192: 7715 case 0x2005: 7716 untested = 0; 7717 break; 7718 } 7719 break; 7720 case 0x7392: 7721 if (id->idProduct == 0x7811 || id->idProduct == 0xa611 || id->idProduct == 0xb811) 7722 untested = 0; 7723 break; 7724 case 0x050d: 7725 if (id->idProduct == 0x1004) 7726 untested = 0; 7727 break; 7728 case 0x20f4: 7729 if (id->idProduct == 0x648b) 7730 untested = 0; 7731 break; 7732 case 0x2001: 7733 if (id->idProduct == 0x3308) 7734 untested = 0; 7735 break; 7736 case 0x2357: 7737 if (id->idProduct == 0x0109 || id->idProduct == 0x010c || 7738 id->idProduct == 0x0135) 7739 untested = 0; 7740 break; 7741 case 0x0b05: 7742 if (id->idProduct == 0x18f1) 7743 untested = 0; 7744 break; 7745 default: 7746 break; 7747 } 7748 7749 if (untested) { 7750 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE; 7751 dev_info(&udev->dev, 7752 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n", 7753 id->idVendor, id->idProduct); 7754 dev_info(&udev->dev, 7755 "Please report results to Jes.Sorensen@gmail.com\n"); 7756 } 7757 7758 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops); 7759 if (!hw) { 7760 ret = -ENOMEM; 7761 goto err_put_dev; 7762 } 7763 7764 priv = hw->priv; 7765 priv->hw = hw; 7766 priv->udev = udev; 7767 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info; 7768 mutex_init(&priv->usb_buf_mutex); 7769 mutex_init(&priv->syson_indirect_access_mutex); 7770 mutex_init(&priv->h2c_mutex); 7771 mutex_init(&priv->sta_mutex); 7772 INIT_LIST_HEAD(&priv->tx_urb_free_list); 7773 spin_lock_init(&priv->tx_urb_lock); 7774 INIT_LIST_HEAD(&priv->rx_urb_pending_list); 7775 spin_lock_init(&priv->rx_urb_lock); 7776 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work); 7777 INIT_DELAYED_WORK(&priv->ra_watchdog, rtl8xxxu_watchdog_callback); 7778 INIT_DELAYED_WORK(&priv->update_beacon_work, rtl8xxxu_update_beacon_work_callback); 7779 skb_queue_head_init(&priv->c2hcmd_queue); 7780 7781 usb_set_intfdata(interface, hw); 7782 7783 ret = rtl8xxxu_parse_usb(priv, interface); 7784 if (ret) 7785 goto err_set_intfdata; 7786 7787 ret = priv->fops->identify_chip(priv); 7788 if (ret) { 7789 dev_err(&udev->dev, "Fatal - failed to identify chip\n"); 7790 goto err_set_intfdata; 7791 } 7792 7793 hw->wiphy->available_antennas_tx = BIT(priv->tx_paths) - 1; 7794 hw->wiphy->available_antennas_rx = BIT(priv->rx_paths) - 1; 7795 7796 if (priv->rtl_chip == RTL8188E) 7797 INIT_WORK(&priv->c2hcmd_work, rtl8188e_c2hcmd_callback); 7798 else 7799 INIT_WORK(&priv->c2hcmd_work, rtl8xxxu_c2hcmd_callback); 7800 7801 ret = priv->fops->read_efuse(priv); 7802 if (ret) { 7803 dev_err(&udev->dev, "Fatal - failed to read EFuse\n"); 7804 goto err_set_intfdata; 7805 } 7806 7807 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) 7808 rtl8xxxu_dump_efuse(priv); 7809 7810 ret = priv->fops->parse_efuse(priv); 7811 if (ret) { 7812 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n"); 7813 goto err_set_intfdata; 7814 } 7815 7816 rtl8xxxu_print_chipinfo(priv); 7817 7818 ret = priv->fops->load_firmware(priv); 7819 if (ret) { 7820 dev_err(&udev->dev, "Fatal - failed to load firmware\n"); 7821 goto err_set_intfdata; 7822 } 7823 7824 ret = rtl8xxxu_init_device(hw); 7825 if (ret) 7826 goto err_set_intfdata; 7827 7828 hw->vif_data_size = sizeof(struct rtl8xxxu_vif); 7829 hw->sta_data_size = sizeof(struct rtl8xxxu_sta_info); 7830 7831 hw->wiphy->max_scan_ssids = 1; 7832 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; 7833 if (priv->fops->max_macid_num) 7834 hw->wiphy->max_ap_assoc_sta = priv->fops->max_macid_num - 1; 7835 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 7836 if (priv->fops->supports_ap) 7837 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP); 7838 hw->queues = 4; 7839 7840 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 7841 7842 if (priv->fops->supports_concurrent) { 7843 hw->wiphy->iface_combinations = rtl8xxxu_combinations; 7844 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtl8xxxu_combinations); 7845 } 7846 7847 sband = &rtl8xxxu_supported_band; 7848 sband->ht_cap.ht_supported = true; 7849 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 7850 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; 7851 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 | 7852 IEEE80211_HT_CAP_SUP_WIDTH_20_40; 7853 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs)); 7854 sband->ht_cap.mcs.rx_mask[0] = 0xff; 7855 sband->ht_cap.mcs.rx_mask[4] = 0x01; 7856 if (priv->rf_paths > 1) { 7857 sband->ht_cap.mcs.rx_mask[1] = 0xff; 7858 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40; 7859 } 7860 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 7861 7862 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 7863 7864 hw->wiphy->rts_threshold = 2347; 7865 7866 SET_IEEE80211_DEV(priv->hw, &interface->dev); 7867 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr); 7868 7869 hw->extra_tx_headroom = priv->fops->tx_desc_size; 7870 ieee80211_hw_set(hw, SIGNAL_DBM); 7871 7872 /* 7873 * The firmware handles rate control, except for RTL8188EU, 7874 * where we handle the rate control in the driver. 7875 */ 7876 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 7877 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 7878 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 7879 ieee80211_hw_set(hw, MFP_CAPABLE); 7880 7881 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); 7882 7883 ret = ieee80211_register_hw(priv->hw); 7884 if (ret) { 7885 dev_err(&udev->dev, "%s: Failed to register: %i\n", 7886 __func__, ret); 7887 goto err_set_intfdata; 7888 } 7889 7890 rtl8xxxu_init_led(priv); 7891 rtl8xxxu_debugfs_init(priv); 7892 7893 return 0; 7894 7895err_set_intfdata: 7896 usb_set_intfdata(interface, NULL); 7897 7898 kfree(priv->fw_data); 7899 mutex_destroy(&priv->usb_buf_mutex); 7900 mutex_destroy(&priv->syson_indirect_access_mutex); 7901 mutex_destroy(&priv->h2c_mutex); 7902 7903 ieee80211_free_hw(hw); 7904err_put_dev: 7905 usb_put_dev(udev); 7906 7907 return ret; 7908} 7909 7910static void rtl8xxxu_disconnect(struct usb_interface *interface) 7911{ 7912 struct rtl8xxxu_priv *priv; 7913 struct ieee80211_hw *hw; 7914 7915 hw = usb_get_intfdata(interface); 7916 priv = hw->priv; 7917 7918 rtl8xxxu_deinit_led(priv); 7919 7920 ieee80211_unregister_hw(hw); 7921 7922 priv->fops->power_off(priv); 7923 7924 usb_set_intfdata(interface, NULL); 7925 7926 dev_info(&priv->udev->dev, "disconnecting\n"); 7927 7928 kfree(priv->fw_data); 7929 mutex_destroy(&priv->usb_buf_mutex); 7930 mutex_destroy(&priv->syson_indirect_access_mutex); 7931 mutex_destroy(&priv->h2c_mutex); 7932 7933 if (priv->udev->state != USB_STATE_NOTATTACHED) { 7934 dev_info(&priv->udev->dev, 7935 "Device still attached, trying to reset\n"); 7936 usb_reset_device(priv->udev); 7937 } 7938 usb_put_dev(priv->udev); 7939 ieee80211_free_hw(hw); 7940} 7941 7942static const struct usb_device_id dev_table[] = { 7943{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff), 7944 .driver_info = (unsigned long)&rtl8723au_fops}, 7945{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff), 7946 .driver_info = (unsigned long)&rtl8723au_fops}, 7947{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff), 7948 .driver_info = (unsigned long)&rtl8723au_fops}, 7949{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff), 7950 .driver_info = (unsigned long)&rtl8192eu_fops}, 7951/* TP-Link TL-WN822N v4 */ 7952{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0108, 0xff, 0xff, 0xff), 7953 .driver_info = (unsigned long)&rtl8192eu_fops}, 7954/* D-Link DWA-131 rev E1, tested by David Patiño */ 7955{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3319, 0xff, 0xff, 0xff), 7956 .driver_info = (unsigned long)&rtl8192eu_fops}, 7957/* Tested by Myckel Habets */ 7958{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0109, 0xff, 0xff, 0xff), 7959 .driver_info = (unsigned long)&rtl8192eu_fops}, 7960{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff), 7961 .driver_info = (unsigned long)&rtl8723bu_fops}, 7962{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xa611, 0xff, 0xff, 0xff), 7963 .driver_info = (unsigned long)&rtl8723bu_fops}, 7964/* RTL8188FU */ 7965{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf179, 0xff, 0xff, 0xff), 7966 .driver_info = (unsigned long)&rtl8188fu_fops}, 7967{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8179, 0xff, 0xff, 0xff), 7968 .driver_info = (unsigned long)&rtl8188eu_fops}, 7969/* Tested by Hans de Goede - rtl8188etv */ 7970{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0179, 0xff, 0xff, 0xff), 7971 .driver_info = (unsigned long)&rtl8188eu_fops}, 7972/* Sitecom rtl8188eus */ 7973{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0076, 0xff, 0xff, 0xff), 7974 .driver_info = (unsigned long)&rtl8188eu_fops}, 7975/* D-Link USB-GO-N150 */ 7976{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3311, 0xff, 0xff, 0xff), 7977 .driver_info = (unsigned long)&rtl8188eu_fops}, 7978/* D-Link DWA-125 REV D1 */ 7979{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330f, 0xff, 0xff, 0xff), 7980 .driver_info = (unsigned long)&rtl8188eu_fops}, 7981/* D-Link DWA-123 REV D1 */ 7982{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3310, 0xff, 0xff, 0xff), 7983 .driver_info = (unsigned long)&rtl8188eu_fops}, 7984/* D-Link DWA-121 rev B1 */ 7985{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x331b, 0xff, 0xff, 0xff), 7986 .driver_info = (unsigned long)&rtl8188eu_fops}, 7987/* Abocom - Abocom */ 7988{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8179, 0xff, 0xff, 0xff), 7989 .driver_info = (unsigned long)&rtl8188eu_fops}, 7990/* Elecom WDC-150SU2M */ 7991{USB_DEVICE_AND_INTERFACE_INFO(0x056e, 0x4008, 0xff, 0xff, 0xff), 7992 .driver_info = (unsigned long)&rtl8188eu_fops}, 7993/* TP-Link TL-WN722N v2 */ 7994{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x010c, 0xff, 0xff, 0xff), 7995 .driver_info = (unsigned long)&rtl8188eu_fops}, 7996/* TP-Link TL-WN727N v5.21 */ 7997{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0111, 0xff, 0xff, 0xff), 7998 .driver_info = (unsigned long)&rtl8188eu_fops}, 7999/* MERCUSYS MW150US v2 */ 8000{USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0102, 0xff, 0xff, 0xff), 8001 .driver_info = (unsigned long)&rtl8188eu_fops}, 8002/* ASUS USB-N10 Nano B1 */ 8003{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f0, 0xff, 0xff, 0xff), 8004 .driver_info = (unsigned long)&rtl8188eu_fops}, 8005 /* Edimax EW-7811Un V2 */ 8006{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb811, 0xff, 0xff, 0xff), 8007 .driver_info = (unsigned long)&rtl8188eu_fops}, 8008/* Rosewill USB-N150 Nano */ 8009{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xffef, 0xff, 0xff, 0xff), 8010 .driver_info = (unsigned long)&rtl8188eu_fops}, 8011/* RTL8710BU aka RTL8188GU (not to be confused with RTL8188GTVU) */ 8012{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb711, 0xff, 0xff, 0xff), 8013 .driver_info = (unsigned long)&rtl8710bu_fops}, 8014/* TOTOLINK N150UA V5 / N150UA-B */ 8015{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2005, 0xff, 0xff, 0xff), 8016 .driver_info = (unsigned long)&rtl8710bu_fops}, 8017/* Comfast CF-826F */ 8018{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf192, 0xff, 0xff, 0xff), 8019 .driver_info = (unsigned long)&rtl8192fu_fops}, 8020/* Asus USB-N13 rev C1 */ 8021{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f1, 0xff, 0xff, 0xff), 8022 .driver_info = (unsigned long)&rtl8192fu_fops}, 8023/* EDIMAX EW-7722UTn V3 */ 8024{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb722, 0xff, 0xff, 0xff), 8025 .driver_info = (unsigned long)&rtl8192fu_fops}, 8026{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x318b, 0xff, 0xff, 0xff), 8027 .driver_info = (unsigned long)&rtl8192fu_fops}, 8028/* TP-Link TL-WN823N V2 */ 8029{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0135, 0xff, 0xff, 0xff), 8030 .driver_info = (unsigned long)&rtl8192fu_fops}, 8031/* D-Link AN3U rev. A1 */ 8032{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3328, 0xff, 0xff, 0xff), 8033 .driver_info = (unsigned long)&rtl8192fu_fops}, 8034#ifdef CONFIG_RTL8XXXU_UNTESTED 8035/* Still supported by rtlwifi */ 8036{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff), 8037 .driver_info = (unsigned long)&rtl8192cu_fops}, 8038{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff), 8039 .driver_info = (unsigned long)&rtl8192cu_fops}, 8040{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff), 8041 .driver_info = (unsigned long)&rtl8192cu_fops}, 8042{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x819a, 0xff, 0xff, 0xff), 8043 .driver_info = (unsigned long)&rtl8192cu_fops}, 8044{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8754, 0xff, 0xff, 0xff), 8045 .driver_info = (unsigned long)&rtl8192cu_fops}, 8046{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817c, 0xff, 0xff, 0xff), 8047 .driver_info = (unsigned long)&rtl8192cu_fops}, 8048/* Tested by Larry Finger */ 8049{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff), 8050 .driver_info = (unsigned long)&rtl8192cu_fops}, 8051/* Tested by Andrea Merello */ 8052{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff), 8053 .driver_info = (unsigned long)&rtl8192cu_fops}, 8054/* Tested by Jocelyn Mayer */ 8055{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff), 8056 .driver_info = (unsigned long)&rtl8192cu_fops}, 8057/* Tested by Stefano Bravi */ 8058{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff), 8059 .driver_info = (unsigned long)&rtl8192cu_fops}, 8060/* Currently untested 8188 series devices */ 8061{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x018a, 0xff, 0xff, 0xff), 8062 .driver_info = (unsigned long)&rtl8192cu_fops}, 8063{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff), 8064 .driver_info = (unsigned long)&rtl8192cu_fops}, 8065{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff), 8066 .driver_info = (unsigned long)&rtl8192cu_fops}, 8067{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff), 8068 .driver_info = (unsigned long)&rtl8192cu_fops}, 8069{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff), 8070 .driver_info = (unsigned long)&rtl8192cu_fops}, 8071{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff), 8072 .driver_info = (unsigned long)&rtl8192cu_fops}, 8073{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff), 8074 .driver_info = (unsigned long)&rtl8192cu_fops}, 8075{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff), 8076 .driver_info = (unsigned long)&rtl8192cu_fops}, 8077{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8186, 0xff, 0xff, 0xff), 8078 .driver_info = (unsigned long)&rtl8192cu_fops}, 8079{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff), 8080 .driver_info = (unsigned long)&rtl8192cu_fops}, 8081{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff), 8082 .driver_info = (unsigned long)&rtl8192cu_fops}, 8083{USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff), 8084 .driver_info = (unsigned long)&rtl8192cu_fops}, 8085{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff), 8086 .driver_info = (unsigned long)&rtl8192cu_fops}, 8087{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff), 8088 .driver_info = (unsigned long)&rtl8192cu_fops}, 8089{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x11f2, 0xff, 0xff, 0xff), 8090 .driver_info = (unsigned long)&rtl8192cu_fops}, 8091{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff), 8092 .driver_info = (unsigned long)&rtl8192cu_fops}, 8093{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff), 8094 .driver_info = (unsigned long)&rtl8192cu_fops}, 8095{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff), 8096 .driver_info = (unsigned long)&rtl8192cu_fops}, 8097{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9043, 0xff, 0xff, 0xff), 8098 .driver_info = (unsigned long)&rtl8192cu_fops}, 8099{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff), 8100 .driver_info = (unsigned long)&rtl8192cu_fops}, 8101{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff), 8102 .driver_info = (unsigned long)&rtl8192cu_fops}, 8103{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff), 8104 .driver_info = (unsigned long)&rtl8192cu_fops}, 8105{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff), 8106 .driver_info = (unsigned long)&rtl8192cu_fops}, 8107{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff), 8108 .driver_info = (unsigned long)&rtl8192cu_fops}, 8109{USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff), 8110 .driver_info = (unsigned long)&rtl8192cu_fops}, 8111{USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff), 8112 .driver_info = (unsigned long)&rtl8192cu_fops}, 8113{USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff), 8114 .driver_info = (unsigned long)&rtl8192cu_fops}, 8115{USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3358, 0xff, 0xff, 0xff), 8116 .driver_info = (unsigned long)&rtl8192cu_fops}, 8117{USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3359, 0xff, 0xff, 0xff), 8118 .driver_info = (unsigned long)&rtl8192cu_fops}, 8119{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff), 8120 .driver_info = (unsigned long)&rtl8192cu_fops}, 8121{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff), 8122 .driver_info = (unsigned long)&rtl8192cu_fops}, 8123{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff), 8124 .driver_info = (unsigned long)&rtl8192cu_fops}, 8125{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff), 8126 .driver_info = (unsigned long)&rtl8192cu_fops}, 8127{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff), 8128 .driver_info = (unsigned long)&rtl8192cu_fops}, 8129{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff), 8130 .driver_info = (unsigned long)&rtl8192cu_fops}, 8131{USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff), 8132 .driver_info = (unsigned long)&rtl8192cu_fops}, 8133{USB_DEVICE_AND_INTERFACE_INFO(0x9846, 0x9041, 0xff, 0xff, 0xff), 8134 .driver_info = (unsigned long)&rtl8192cu_fops}, 8135{USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff), 8136 .driver_info = (unsigned long)&rtl8192cu_fops}, 8137{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff), 8138 .driver_info = (unsigned long)&rtl8192cu_fops}, 8139{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff), 8140 .driver_info = (unsigned long)&rtl8192cu_fops}, 8141{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff), 8142 .driver_info = (unsigned long)&rtl8192cu_fops}, 8143{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff), 8144 .driver_info = (unsigned long)&rtl8192cu_fops}, 8145{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff), 8146 .driver_info = (unsigned long)&rtl8192cu_fops}, 8147{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff), 8148 .driver_info = (unsigned long)&rtl8192cu_fops}, 8149{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff), 8150 .driver_info = (unsigned long)&rtl8192cu_fops}, 8151/* Currently untested 8192 series devices */ 8152{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff), 8153 .driver_info = (unsigned long)&rtl8192cu_fops}, 8154{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff), 8155 .driver_info = (unsigned long)&rtl8192cu_fops}, 8156{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff), 8157 .driver_info = (unsigned long)&rtl8192cu_fops}, 8158{USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff), 8159 .driver_info = (unsigned long)&rtl8192cu_fops}, 8160{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff), 8161 .driver_info = (unsigned long)&rtl8192cu_fops}, 8162{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff), 8163 .driver_info = (unsigned long)&rtl8192cu_fops}, 8164{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff), 8165 .driver_info = (unsigned long)&rtl8192cu_fops}, 8166{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff), 8167 .driver_info = (unsigned long)&rtl8192cu_fops}, 8168{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff), 8169 .driver_info = (unsigned long)&rtl8192cu_fops}, 8170{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0077, 0xff, 0xff, 0xff), 8171 .driver_info = (unsigned long)&rtl8192cu_fops}, 8172{USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff), 8173 .driver_info = (unsigned long)&rtl8192cu_fops}, 8174{USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff), 8175 .driver_info = (unsigned long)&rtl8192cu_fops}, 8176{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff), 8177 .driver_info = (unsigned long)&rtl8192cu_fops}, 8178{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff), 8179 .driver_info = (unsigned long)&rtl8192cu_fops}, 8180{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff), 8181 .driver_info = (unsigned long)&rtl8192cu_fops}, 8182{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff), 8183 .driver_info = (unsigned long)&rtl8192cu_fops}, 8184{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff), 8185 .driver_info = (unsigned long)&rtl8192cu_fops}, 8186{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff), 8187 .driver_info = (unsigned long)&rtl8192cu_fops}, 8188{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff), 8189 .driver_info = (unsigned long)&rtl8192cu_fops}, 8190{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff), 8191 .driver_info = (unsigned long)&rtl8192cu_fops}, 8192{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff), 8193 .driver_info = (unsigned long)&rtl8192cu_fops}, 8194{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330d, 0xff, 0xff, 0xff), 8195 .driver_info = (unsigned long)&rtl8192cu_fops}, 8196{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff), 8197 .driver_info = (unsigned long)&rtl8192cu_fops}, 8198{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff), 8199 .driver_info = (unsigned long)&rtl8192cu_fops}, 8200{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff), 8201 .driver_info = (unsigned long)&rtl8192cu_fops}, 8202{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff), 8203 .driver_info = (unsigned long)&rtl8192cu_fops}, 8204{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff), 8205 .driver_info = (unsigned long)&rtl8192cu_fops}, 8206/* found in rtl8192eu vendor driver */ 8207{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0107, 0xff, 0xff, 0xff), 8208 .driver_info = (unsigned long)&rtl8192eu_fops}, 8209{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab33, 0xff, 0xff, 0xff), 8210 .driver_info = (unsigned long)&rtl8192eu_fops}, 8211{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818c, 0xff, 0xff, 0xff), 8212 .driver_info = (unsigned long)&rtl8192eu_fops}, 8213/* D-Link DWA-131 rev C1 */ 8214{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3312, 0xff, 0xff, 0xff), 8215 .driver_info = (unsigned long)&rtl8192eu_fops}, 8216/* TP-Link TL-WN8200ND V2 */ 8217{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0126, 0xff, 0xff, 0xff), 8218 .driver_info = (unsigned long)&rtl8192eu_fops}, 8219/* Mercusys MW300UM */ 8220{USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0100, 0xff, 0xff, 0xff), 8221 .driver_info = (unsigned long)&rtl8192eu_fops}, 8222/* Mercusys MW300UH */ 8223{USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0104, 0xff, 0xff, 0xff), 8224 .driver_info = (unsigned long)&rtl8192eu_fops}, 8225#endif 8226{ } 8227}; 8228 8229static struct usb_driver rtl8xxxu_driver = { 8230 .name = DRIVER_NAME, 8231 .probe = rtl8xxxu_probe, 8232 .disconnect = rtl8xxxu_disconnect, 8233 .id_table = dev_table, 8234 .no_dynamic_id = 1, 8235 .disable_hub_initiated_lpm = 1, 8236}; 8237 8238MODULE_DEVICE_TABLE(usb, dev_table); 8239 8240module_usb_driver(rtl8xxxu_driver);
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