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8188f.c
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linux-6.19.14/drivers/net/wireless/realtek/rtl8xxxu/8188f.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * RTL8XXXU mac80211 USB driver - 8188f specific subdriver 4 * 5 * Copyright (c) 2022 Bitterblue Smith <rtl8821cerfe2@gmail.com> 6 * 7 * Portions copied from existing rtl8xxxu code: 8 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 9 * 10 * Portions, notably calibration code: 11 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 12 */ 13 14#include "regs.h" 15#include "rtl8xxxu.h" 16 17static const struct rtl8xxxu_reg8val rtl8188f_mac_init_table[] = { 18 {0x024, 0xDF}, {0x025, 0x07}, {0x02B, 0x1C}, {0x283, 0x20}, 19 {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00}, 20 {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, 21 {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04}, 22 {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D}, 23 {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, 24 {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0}, 25 {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00}, 26 {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0}, 27 {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x44}, 28 {0x461, 0x44}, {0x4BC, 0xC0}, {0x4C8, 0xFF}, {0x4C9, 0x08}, 29 {0x4CC, 0xFF}, {0x4CD, 0xFF}, {0x4CE, 0x01}, {0x500, 0x26}, 30 {0x501, 0xA2}, {0x502, 0x2F}, {0x503, 0x00}, {0x504, 0x28}, 31 {0x505, 0xA3}, {0x506, 0x5E}, {0x507, 0x00}, {0x508, 0x2B}, 32 {0x509, 0xA4}, {0x50A, 0x5E}, {0x50B, 0x00}, {0x50C, 0x4F}, 33 {0x50D, 0xA4}, {0x50E, 0x00}, {0x50F, 0x00}, {0x512, 0x1C}, 34 {0x514, 0x0A}, {0x516, 0x0A}, {0x525, 0x4F}, {0x550, 0x10}, 35 {0x551, 0x10}, {0x559, 0x02}, {0x55C, 0x28}, {0x55D, 0xFF}, 36 {0x605, 0x30}, {0x608, 0x0E}, {0x609, 0x2A}, {0x620, 0xFF}, 37 {0x621, 0xFF}, {0x622, 0xFF}, {0x623, 0xFF}, {0x624, 0xFF}, 38 {0x625, 0xFF}, {0x626, 0xFF}, {0x627, 0xFF}, {0x638, 0x28}, 39 {0x63C, 0x0A}, {0x63D, 0x0A}, {0x63E, 0x0E}, {0x63F, 0x0E}, 40 {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xC8}, 41 {0x66E, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65}, 42 {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70A, 0x65}, 43 {0x70B, 0x87}, 44 {0xffff, 0xff}, 45}; 46 47static const struct rtl8xxxu_reg32val rtl8188fu_phy_init_table[] = { 48 {0x800, 0x80045700}, {0x804, 0x00000001}, 49 {0x808, 0x0000FC00}, {0x80C, 0x0000000A}, 50 {0x810, 0x10001331}, {0x814, 0x020C3D10}, 51 {0x818, 0x00200385}, {0x81C, 0x00000000}, 52 {0x820, 0x01000100}, {0x824, 0x00390204}, 53 {0x828, 0x00000000}, {0x82C, 0x00000000}, 54 {0x830, 0x00000000}, {0x834, 0x00000000}, 55 {0x838, 0x00000000}, {0x83C, 0x00000000}, 56 {0x840, 0x00010000}, {0x844, 0x00000000}, 57 {0x848, 0x00000000}, {0x84C, 0x00000000}, 58 {0x850, 0x00030000}, {0x854, 0x00000000}, 59 {0x858, 0x569A569A}, {0x85C, 0x569A569A}, 60 {0x860, 0x00000130}, {0x864, 0x00000000}, 61 {0x868, 0x00000000}, {0x86C, 0x27272700}, 62 {0x870, 0x00000000}, {0x874, 0x25004000}, 63 {0x878, 0x00000808}, {0x87C, 0x004F0201}, 64 {0x880, 0xB0000B1E}, {0x884, 0x00000007}, 65 {0x888, 0x00000000}, {0x88C, 0xCCC000C0}, 66 {0x890, 0x00000800}, {0x894, 0xFFFFFFFE}, 67 {0x898, 0x40302010}, {0x89C, 0x00706050}, 68 {0x900, 0x00000000}, {0x904, 0x00000023}, 69 {0x908, 0x00000000}, {0x90C, 0x81121111}, 70 {0x910, 0x00000002}, {0x914, 0x00000201}, 71 {0x948, 0x99000000}, {0x94C, 0x00000010}, 72 {0x950, 0x20003000}, {0x954, 0x4A880000}, 73 {0x958, 0x4BC5D87A}, {0x95C, 0x04EB9B79}, 74 {0x96C, 0x00000003}, {0xA00, 0x00D047C8}, 75 {0xA04, 0x80FF800C}, {0xA08, 0x8C898300}, 76 {0xA0C, 0x2E7F120F}, {0xA10, 0x9500BB78}, 77 {0xA14, 0x1114D028}, {0xA18, 0x00881117}, 78 {0xA1C, 0x89140F00}, {0xA20, 0xD1D80000}, 79 {0xA24, 0x5A7DA0BD}, {0xA28, 0x0000223B}, 80 {0xA2C, 0x00D30000}, {0xA70, 0x101FBF00}, 81 {0xA74, 0x00000007}, {0xA78, 0x00000900}, 82 {0xA7C, 0x225B0606}, {0xA80, 0x218075B1}, 83 {0xA84, 0x00120000}, {0xA88, 0x040C0000}, 84 {0xA8C, 0x12345678}, {0xA90, 0xABCDEF00}, 85 {0xA94, 0x001B1B89}, {0xA98, 0x05100000}, 86 {0xA9C, 0x3F000000}, {0xAA0, 0x00000000}, 87 {0xB2C, 0x00000000}, {0xC00, 0x48071D40}, 88 {0xC04, 0x03A05611}, {0xC08, 0x000000E4}, 89 {0xC0C, 0x6C6C6C6C}, {0xC10, 0x18800000}, 90 {0xC14, 0x40000100}, {0xC18, 0x08800000}, 91 {0xC1C, 0x40000100}, {0xC20, 0x00000000}, 92 {0xC24, 0x00000000}, {0xC28, 0x00000000}, 93 {0xC2C, 0x00000000}, {0xC30, 0x69E9CC4A}, 94 {0xC34, 0x31000040}, {0xC38, 0x21688080}, 95 {0xC3C, 0x00001714}, {0xC40, 0x1F78403F}, 96 {0xC44, 0x00010036}, {0xC48, 0xEC020107}, 97 {0xC4C, 0x007F037F}, {0xC50, 0x69553420}, 98 {0xC54, 0x43BC0094}, {0xC58, 0x00013169}, 99 {0xC5C, 0x00250492}, {0xC60, 0x00000000}, 100 {0xC64, 0x7112848B}, {0xC68, 0x47C07BFF}, 101 {0xC6C, 0x00000036}, {0xC70, 0x2C7F000D}, 102 {0xC74, 0x020600DB}, {0xC78, 0x0000001F}, 103 {0xC7C, 0x00B91612}, {0xC80, 0x390000E4}, 104 {0xC84, 0x11F60000}, 105 {0xC88, 0x40000100}, {0xC8C, 0x20200000}, 106 {0xC90, 0x00091521}, {0xC94, 0x00000000}, 107 {0xC98, 0x00121820}, {0xC9C, 0x00007F7F}, 108 {0xCA0, 0x00000000}, {0xCA4, 0x000300A0}, 109 {0xCA8, 0x00000000}, {0xCAC, 0x00000000}, 110 {0xCB0, 0x00000000}, {0xCB4, 0x00000000}, 111 {0xCB8, 0x00000000}, {0xCBC, 0x28000000}, 112 {0xCC0, 0x00000000}, {0xCC4, 0x00000000}, 113 {0xCC8, 0x00000000}, {0xCCC, 0x00000000}, 114 {0xCD0, 0x00000000}, {0xCD4, 0x00000000}, 115 {0xCD8, 0x64B22427}, {0xCDC, 0x00766932}, 116 {0xCE0, 0x00222222}, {0xCE4, 0x10000000}, 117 {0xCE8, 0x37644302}, {0xCEC, 0x2F97D40C}, 118 {0xD00, 0x04030740}, {0xD04, 0x40020401}, 119 {0xD08, 0x0000907F}, {0xD0C, 0x20010201}, 120 {0xD10, 0xA0633333}, {0xD14, 0x3333BC53}, 121 {0xD18, 0x7A8F5B6F}, {0xD2C, 0xCB979975}, 122 {0xD30, 0x00000000}, {0xD34, 0x80608000}, 123 {0xD38, 0x98000000}, {0xD3C, 0x40127353}, 124 {0xD40, 0x00000000}, {0xD44, 0x00000000}, 125 {0xD48, 0x00000000}, {0xD4C, 0x00000000}, 126 {0xD50, 0x6437140A}, {0xD54, 0x00000000}, 127 {0xD58, 0x00000282}, {0xD5C, 0x30032064}, 128 {0xD60, 0x4653DE68}, {0xD64, 0x04518A3C}, 129 {0xD68, 0x00002101}, {0xD6C, 0x2A201C16}, 130 {0xD70, 0x1812362E}, {0xD74, 0x322C2220}, 131 {0xD78, 0x000E3C24}, {0xE00, 0x2D2D2D2D}, 132 {0xE04, 0x2D2D2D2D}, {0xE08, 0x0390272D}, 133 {0xE10, 0x2D2D2D2D}, {0xE14, 0x2D2D2D2D}, 134 {0xE18, 0x2D2D2D2D}, {0xE1C, 0x2D2D2D2D}, 135 {0xE28, 0x00000000}, {0xE30, 0x1000DC1F}, 136 {0xE34, 0x10008C1F}, {0xE38, 0x02140102}, 137 {0xE3C, 0x681604C2}, {0xE40, 0x01007C00}, 138 {0xE44, 0x01004800}, {0xE48, 0xFB000000}, 139 {0xE4C, 0x000028D1}, {0xE50, 0x1000DC1F}, 140 {0xE54, 0x10008C1F}, {0xE58, 0x02140102}, 141 {0xE5C, 0x28160D05}, {0xE60, 0x00000008}, 142 {0xE60, 0x021400A0}, {0xE64, 0x281600A0}, 143 {0xE6C, 0x01C00010}, {0xE70, 0x01C00010}, 144 {0xE74, 0x02000010}, {0xE78, 0x02000010}, 145 {0xE7C, 0x02000010}, {0xE80, 0x02000010}, 146 {0xE84, 0x01C00010}, {0xE88, 0x02000010}, 147 {0xE8C, 0x01C00010}, {0xED0, 0x01C00010}, 148 {0xED4, 0x01C00010}, {0xED8, 0x01C00010}, 149 {0xEDC, 0x00000010}, {0xEE0, 0x00000010}, 150 {0xEEC, 0x03C00010}, {0xF14, 0x00000003}, 151 {0xF4C, 0x00000000}, {0xF00, 0x00000300}, 152 {0xffff, 0xffffffff}, 153}; 154 155static const struct rtl8xxxu_reg32val rtl8188f_agc_table[] = { 156 {0xC78, 0xFC000001}, {0xC78, 0xFB010001}, 157 {0xC78, 0xFA020001}, {0xC78, 0xF9030001}, 158 {0xC78, 0xF8040001}, {0xC78, 0xF7050001}, 159 {0xC78, 0xF6060001}, {0xC78, 0xF5070001}, 160 {0xC78, 0xF4080001}, {0xC78, 0xF3090001}, 161 {0xC78, 0xF20A0001}, {0xC78, 0xF10B0001}, 162 {0xC78, 0xF00C0001}, {0xC78, 0xEF0D0001}, 163 {0xC78, 0xEE0E0001}, {0xC78, 0xED0F0001}, 164 {0xC78, 0xEC100001}, {0xC78, 0xEB110001}, 165 {0xC78, 0xEA120001}, {0xC78, 0xE9130001}, 166 {0xC78, 0xE8140001}, {0xC78, 0xE7150001}, 167 {0xC78, 0xE6160001}, {0xC78, 0xE5170001}, 168 {0xC78, 0xE4180001}, {0xC78, 0xE3190001}, 169 {0xC78, 0xE21A0001}, {0xC78, 0xE11B0001}, 170 {0xC78, 0xE01C0001}, {0xC78, 0xC21D0001}, 171 {0xC78, 0xC11E0001}, {0xC78, 0xC01F0001}, 172 {0xC78, 0xA5200001}, {0xC78, 0xA4210001}, 173 {0xC78, 0xA3220001}, {0xC78, 0xA2230001}, 174 {0xC78, 0xA1240001}, {0xC78, 0xA0250001}, 175 {0xC78, 0x65260001}, {0xC78, 0x64270001}, 176 {0xC78, 0x63280001}, {0xC78, 0x62290001}, 177 {0xC78, 0x612A0001}, {0xC78, 0x442B0001}, 178 {0xC78, 0x432C0001}, {0xC78, 0x422D0001}, 179 {0xC78, 0x412E0001}, {0xC78, 0x402F0001}, 180 {0xC78, 0x21300001}, {0xC78, 0x20310001}, 181 {0xC78, 0x05320001}, {0xC78, 0x04330001}, 182 {0xC78, 0x03340001}, {0xC78, 0x02350001}, 183 {0xC78, 0x01360001}, {0xC78, 0x00370001}, 184 {0xC78, 0x00380001}, {0xC78, 0x00390001}, 185 {0xC78, 0x003A0001}, {0xC78, 0x003B0001}, 186 {0xC78, 0x003C0001}, {0xC78, 0x003D0001}, 187 {0xC78, 0x003E0001}, {0xC78, 0x003F0001}, 188 {0xC50, 0x69553422}, {0xC50, 0x69553420}, 189 {0xffff, 0xffffffff} 190}; 191 192static const struct rtl8xxxu_rfregval rtl8188fu_radioa_init_table[] = { 193 {0x00, 0x00030000}, {0x08, 0x00008400}, 194 {0x18, 0x00000407}, {0x19, 0x00000012}, 195 {0x1B, 0x00001C6C}, 196 {0x1E, 0x00080009}, {0x1F, 0x00000880}, 197 {0x2F, 0x0001A060}, {0x3F, 0x00028000}, 198 {0x42, 0x000060C0}, {0x57, 0x000D0000}, 199 {0x58, 0x000C0160}, {0x67, 0x00001552}, 200 {0x83, 0x00000000}, {0xB0, 0x000FF9F0}, 201 {0xB1, 0x00022218}, {0xB2, 0x00034C00}, 202 {0xB4, 0x0004484B}, {0xB5, 0x0000112A}, 203 {0xB6, 0x0000053E}, {0xB7, 0x00010408}, 204 {0xB8, 0x00010200}, {0xB9, 0x00080001}, 205 {0xBA, 0x00040001}, {0xBB, 0x00000400}, 206 {0xBF, 0x000C0000}, {0xC2, 0x00002400}, 207 {0xC3, 0x00000009}, {0xC4, 0x00040C91}, 208 {0xC5, 0x00099999}, {0xC6, 0x000000A3}, 209 {0xC7, 0x0008F820}, {0xC8, 0x00076C06}, 210 {0xC9, 0x00000000}, {0xCA, 0x00080000}, 211 {0xDF, 0x00000180}, {0xEF, 0x000001A0}, 212 {0x51, 0x000E8333}, {0x52, 0x000FAC2C}, 213 {0x53, 0x00000103}, {0x56, 0x000517F0}, 214 {0x35, 0x00000099}, {0x35, 0x00000199}, 215 {0x35, 0x00000299}, {0x36, 0x00000064}, 216 {0x36, 0x00008064}, {0x36, 0x00010064}, 217 {0x36, 0x00018064}, {0x18, 0x00000C07}, 218 {0x5A, 0x00048000}, {0x19, 0x000739D0}, 219 {0x34, 0x0000ADD6}, {0x34, 0x00009DD3}, 220 {0x34, 0x00008CF4}, {0x34, 0x00007CF1}, 221 {0x34, 0x00006CEE}, {0x34, 0x00005CEB}, 222 {0x34, 0x00004CCE}, {0x34, 0x00003CCB}, 223 {0x34, 0x00002CC8}, {0x34, 0x00001C4B}, 224 {0x34, 0x00000C48}, 225 {0x00, 0x00030159}, {0x84, 0x00048000}, 226 {0x86, 0x0000002A}, {0x87, 0x00000025}, 227 {0x8E, 0x00065540}, {0x8F, 0x00088000}, 228 {0xEF, 0x000020A0}, {0x3B, 0x000F0F00}, 229 {0x3B, 0x000E0B00}, {0x3B, 0x000D0900}, 230 {0x3B, 0x000C0700}, {0x3B, 0x000B0600}, 231 {0x3B, 0x000A0400}, {0x3B, 0x00090200}, 232 {0x3B, 0x00080000}, {0x3B, 0x0007BF00}, 233 {0x3B, 0x00060B00}, {0x3B, 0x0005C900}, 234 {0x3B, 0x00040700}, {0x3B, 0x00030600}, 235 {0x3B, 0x0002D500}, {0x3B, 0x00010200}, 236 {0x3B, 0x0000E000}, {0xEF, 0x000000A0}, 237 {0xEF, 0x00000010}, {0x3B, 0x0000C0A8}, 238 {0x3B, 0x00010400}, {0xEF, 0x00000000}, 239 {0xEF, 0x00080000}, {0x30, 0x00010000}, 240 {0x31, 0x0000000F}, {0x32, 0x00007EFE}, 241 {0xEF, 0x00000000}, {0x00, 0x00010159}, 242 {0x18, 0x0000FC07}, {0xFE, 0x00000000}, 243 {0xFE, 0x00000000}, {0x1F, 0x00080003}, 244 {0xFE, 0x00000000}, {0xFE, 0x00000000}, 245 {0x1E, 0x00000001}, {0x1F, 0x00080000}, 246 {0x00, 0x00033D95}, 247 {0xff, 0xffffffff} 248}; 249 250static const struct rtl8xxxu_rfregval rtl8188fu_cut_b_radioa_init_table[] = { 251 {0x00, 0x00030000}, {0x08, 0x00008400}, 252 {0x18, 0x00000407}, {0x19, 0x00000012}, 253 {0x1B, 0x00001C6C}, 254 {0x1E, 0x00080009}, {0x1F, 0x00000880}, 255 {0x2F, 0x0001A060}, {0x3F, 0x00028000}, 256 {0x42, 0x000060C0}, {0x57, 0x000D0000}, 257 {0x58, 0x000C0160}, {0x67, 0x00001552}, 258 {0x83, 0x00000000}, {0xB0, 0x000FF9F0}, 259 {0xB1, 0x00022218}, {0xB2, 0x00034C00}, 260 {0xB4, 0x0004484B}, {0xB5, 0x0000112A}, 261 {0xB6, 0x0000053E}, {0xB7, 0x00010408}, 262 {0xB8, 0x00010200}, {0xB9, 0x00080001}, 263 {0xBA, 0x00040001}, {0xBB, 0x00000400}, 264 {0xBF, 0x000C0000}, {0xC2, 0x00002400}, 265 {0xC3, 0x00000009}, {0xC4, 0x00040C91}, 266 {0xC5, 0x00099999}, {0xC6, 0x000000A3}, 267 {0xC7, 0x0008F820}, {0xC8, 0x00076C06}, 268 {0xC9, 0x00000000}, {0xCA, 0x00080000}, 269 {0xDF, 0x00000180}, {0xEF, 0x000001A0}, 270 {0x51, 0x000E8231}, {0x52, 0x000FAC2C}, 271 {0x53, 0x00000141}, {0x56, 0x000517F0}, 272 {0x35, 0x00000090}, {0x35, 0x00000190}, 273 {0x35, 0x00000290}, {0x36, 0x00001064}, 274 {0x36, 0x00009064}, {0x36, 0x00011064}, 275 {0x36, 0x00019064}, {0x18, 0x00000C07}, 276 {0x5A, 0x00048000}, {0x19, 0x000739D0}, 277 {0x34, 0x0000ADD2}, {0x34, 0x00009DD0}, 278 {0x34, 0x00008CF3}, {0x34, 0x00007CF0}, 279 {0x34, 0x00006CED}, {0x34, 0x00005CD2}, 280 {0x34, 0x00004CCF}, {0x34, 0x00003CCC}, 281 {0x34, 0x00002CC9}, {0x34, 0x00001C4C}, 282 {0x34, 0x00000C49}, 283 {0x00, 0x00030159}, {0x84, 0x00048000}, 284 {0x86, 0x0000002A}, {0x87, 0x00000025}, 285 {0x8E, 0x00065540}, {0x8F, 0x00088000}, 286 {0xEF, 0x000020A0}, {0x3B, 0x000F0F00}, 287 {0x3B, 0x000E0B00}, {0x3B, 0x000D0900}, 288 {0x3B, 0x000C0700}, {0x3B, 0x000B0600}, 289 {0x3B, 0x000A0400}, {0x3B, 0x00090200}, 290 {0x3B, 0x00080000}, {0x3B, 0x0007BF00}, 291 {0x3B, 0x00060B00}, {0x3B, 0x0005C900}, 292 {0x3B, 0x00040700}, {0x3B, 0x00030600}, 293 {0x3B, 0x0002D500}, {0x3B, 0x00010200}, 294 {0x3B, 0x0000E000}, {0xEF, 0x000000A0}, 295 {0xEF, 0x00000010}, {0x3B, 0x0000C0A8}, 296 {0x3B, 0x00010400}, {0xEF, 0x00000000}, 297 {0xEF, 0x00080000}, {0x30, 0x00010000}, 298 {0x31, 0x0000000F}, {0x32, 0x00007EFE}, 299 {0xEF, 0x00000000}, {0x00, 0x00010159}, 300 {0x18, 0x0000FC07}, {0xFE, 0x00000000}, 301 {0xFE, 0x00000000}, {0x1F, 0x00080003}, 302 {0xFE, 0x00000000}, {0xFE, 0x00000000}, 303 {0x1E, 0x00000001}, {0x1F, 0x00080000}, 304 {0x00, 0x00033D95}, 305 {0xff, 0xffffffff} 306}; 307 308static int rtl8188fu_identify_chip(struct rtl8xxxu_priv *priv) 309{ 310 struct device *dev = &priv->udev->dev; 311 u32 sys_cfg, vendor; 312 int ret = 0; 313 314 strscpy(priv->chip_name, "8188FU", sizeof(priv->chip_name)); 315 priv->rtl_chip = RTL8188F; 316 priv->rf_paths = 1; 317 priv->rx_paths = 1; 318 priv->tx_paths = 1; 319 priv->has_wifi = 1; 320 321 sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); 322 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); 323 if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { 324 dev_info(dev, "Unsupported test chip\n"); 325 ret = -ENOTSUPP; 326 goto out; 327 } 328 329 vendor = sys_cfg & SYS_CFG_VENDOR_EXT_MASK; 330 rtl8xxxu_identify_vendor_2bits(priv, vendor); 331 332 ret = rtl8xxxu_config_endpoints_no_sie(priv); 333 334out: 335 return ret; 336} 337 338void rtl8188f_channel_to_group(int channel, int *group, int *cck_group) 339{ 340 if (channel < 3) 341 *group = 0; 342 else if (channel < 6) 343 *group = 1; 344 else if (channel < 9) 345 *group = 2; 346 else if (channel < 12) 347 *group = 3; 348 else 349 *group = 4; 350 351 if (channel == 14) 352 *cck_group = 5; 353 else 354 *cck_group = *group; 355} 356 357void 358rtl8188f_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) 359{ 360 u32 val32, ofdm, mcs; 361 u8 cck, ofdmbase, mcsbase; 362 int group, cck_group; 363 364 rtl8188f_channel_to_group(channel, &group, &cck_group); 365 366 cck = priv->cck_tx_power_index_A[cck_group]; 367 368 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); 369 val32 &= 0xffff00ff; 370 val32 |= (cck << 8); 371 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); 372 373 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 374 val32 &= 0xff; 375 val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); 376 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 377 378 ofdmbase = priv->ht40_1s_tx_power_index_A[group]; 379 ofdmbase += priv->ofdm_tx_power_diff[0].a; 380 ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; 381 382 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); 383 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); 384 385 mcsbase = priv->ht40_1s_tx_power_index_A[group]; 386 if (ht40) 387 /* This diff is always 0 - not used in 8188FU. */ 388 mcsbase += priv->ht40_tx_power_diff[0].a; 389 else 390 mcsbase += priv->ht20_tx_power_diff[0].a; 391 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; 392 393 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); 394 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); 395 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs); 396 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs); 397} 398 399/* A workaround to eliminate the 2400MHz, 2440MHz, 2480MHz spur of 8188F. */ 400static void rtl8188f_spur_calibration(struct rtl8xxxu_priv *priv, u8 channel) 401{ 402 static const u32 frequencies[14 + 1] = { 403 [5] = 0xFCCD, 404 [6] = 0xFC4D, 405 [7] = 0xFFCD, 406 [8] = 0xFF4D, 407 [11] = 0xFDCD, 408 [13] = 0xFCCD, 409 [14] = 0xFF9A 410 }; 411 412 static const u32 reg_d40[14 + 1] = { 413 [5] = 0x06000000, 414 [6] = 0x00000600, 415 [13] = 0x06000000 416 }; 417 418 static const u32 reg_d44[14 + 1] = { 419 [11] = 0x04000000 420 }; 421 422 static const u32 reg_d4c[14 + 1] = { 423 [7] = 0x06000000, 424 [8] = 0x00000380, 425 [14] = 0x00180000 426 }; 427 428 const u8 threshold = 0x16; 429 bool do_notch, hw_ctrl, sw_ctrl, hw_ctrl_s1 = 0, sw_ctrl_s1 = 0; 430 u32 val32, initial_gain, reg948; 431 432 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); 433 val32 |= GENMASK(28, 24); 434 rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); 435 436 /* enable notch filter */ 437 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); 438 val32 |= BIT(9); 439 rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); 440 441 if (channel <= 14 && frequencies[channel] > 0) { 442 reg948 = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); 443 hw_ctrl = reg948 & BIT(6); 444 sw_ctrl = !hw_ctrl; 445 446 if (hw_ctrl) { 447 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); 448 val32 &= GENMASK(5, 3); 449 hw_ctrl_s1 = val32 == BIT(3); 450 } else if (sw_ctrl) { 451 sw_ctrl_s1 = !(reg948 & BIT(9)); 452 } 453 454 if (hw_ctrl_s1 || sw_ctrl_s1) { 455 initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 456 457 /* Disable CCK block */ 458 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 459 val32 &= ~FPGA_RF_MODE_CCK; 460 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 461 462 val32 = initial_gain & ~OFDM0_X_AGC_CORE1_IGI_MASK; 463 val32 |= 0x30; 464 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); 465 466 /* disable 3-wire */ 467 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); 468 469 /* Setup PSD */ 470 rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, frequencies[channel]); 471 472 /* Start PSD */ 473 rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, 0x400000 | frequencies[channel]); 474 475 msleep(30); 476 477 do_notch = rtl8xxxu_read32(priv, REG_FPGA0_PSD_REPORT) >= threshold; 478 479 /* turn off PSD */ 480 rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, frequencies[channel]); 481 482 /* enable 3-wire */ 483 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccc000c0); 484 485 /* Enable CCK block */ 486 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 487 val32 |= FPGA_RF_MODE_CCK; 488 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 489 490 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, initial_gain); 491 492 if (do_notch) { 493 rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK1, reg_d40[channel]); 494 rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK2, reg_d44[channel]); 495 rtl8xxxu_write32(priv, 0xd48, 0x0); 496 rtl8xxxu_write32(priv, 0xd4c, reg_d4c[channel]); 497 498 /* enable CSI mask */ 499 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); 500 val32 |= BIT(28); 501 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); 502 503 return; 504 } 505 } 506 } 507 508 /* disable CSI mask function */ 509 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); 510 val32 &= ~BIT(28); 511 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); 512} 513 514static void rtl8188fu_config_channel(struct ieee80211_hw *hw) 515{ 516 struct rtl8xxxu_priv *priv = hw->priv; 517 u32 val32; 518 u8 channel, subchannel; 519 bool sec_ch_above; 520 521 channel = (u8)hw->conf.chandef.chan->hw_value; 522 523 /* Set channel */ 524 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); 525 val32 &= ~MODE_AG_CHANNEL_MASK; 526 val32 |= channel; 527 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); 528 529 /* Spur calibration */ 530 rtl8188f_spur_calibration(priv, channel); 531 532 /* Set bandwidth mode */ 533 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 534 val32 &= ~FPGA_RF_MODE; 535 val32 |= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40; 536 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 537 538 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 539 val32 &= ~FPGA_RF_MODE; 540 val32 |= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40; 541 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 542 543 /* RXADC CLK */ 544 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 545 val32 |= GENMASK(10, 8); 546 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 547 548 /* TXDAC CLK */ 549 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 550 val32 |= BIT(14) | BIT(12); 551 val32 &= ~BIT(13); 552 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 553 554 /* small BW */ 555 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); 556 val32 &= ~GENMASK(31, 30); 557 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); 558 559 /* adc buffer clk */ 560 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); 561 val32 &= ~BIT(29); 562 val32 |= BIT(28); 563 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); 564 565 /* adc buffer clk */ 566 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_AFE); 567 val32 &= ~BIT(29); 568 val32 |= BIT(28); 569 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_AFE, val32); 570 571 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); 572 val32 &= ~BIT(19); 573 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); 574 575 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); 576 val32 &= ~GENMASK(23, 20); 577 val32 |= BIT(21); 578 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || 579 hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) 580 val32 |= BIT(20); 581 else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 582 val32 |= BIT(22); 583 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); 584 585 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) { 586 if (hw->conf.chandef.center_freq1 > 587 hw->conf.chandef.chan->center_freq) { 588 sec_ch_above = 1; 589 channel += 2; 590 } else { 591 sec_ch_above = 0; 592 channel -= 2; 593 } 594 595 /* Set Control channel to upper or lower. */ 596 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 597 val32 &= ~CCK0_SIDEBAND; 598 if (!sec_ch_above) 599 val32 |= CCK0_SIDEBAND; 600 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 601 602 val32 = rtl8xxxu_read32(priv, REG_DATA_SUBCHANNEL); 603 val32 &= ~GENMASK(3, 0); 604 if (sec_ch_above) 605 subchannel = 2; 606 else 607 subchannel = 1; 608 val32 |= subchannel; 609 rtl8xxxu_write32(priv, REG_DATA_SUBCHANNEL, val32); 610 611 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 612 val32 &= ~RSR_RSC_BANDWIDTH_40M; 613 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 614 } 615 616 /* RF TRX_BW */ 617 val32 = channel; 618 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || 619 hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) 620 val32 |= MODE_AG_BW_20MHZ_8723B; 621 else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 622 val32 |= MODE_AG_BW_40MHZ_8723B; 623 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); 624 625 /* FILTER BW&RC Corner (ACPR) */ 626 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || 627 hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) 628 val32 = 0x00065; 629 else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 630 val32 = 0x00025; 631 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RXG_MIX_SWBW, val32); 632 633 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || 634 hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) 635 val32 = 0x0; 636 else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 637 val32 = 0x01000; 638 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RX_BB2, val32); 639 640 /* RC Corner */ 641 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00140); 642 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RX_G2, 0x01c6c); 643} 644 645static void rtl8188fu_init_aggregation(struct rtl8xxxu_priv *priv) 646{ 647 u8 agg_ctrl, rxdma_mode, usb_tx_agg_desc_num = 6; 648 u32 agg_rx, val32; 649 650 /* TX aggregation */ 651 val32 = rtl8xxxu_read32(priv, REG_DWBCN0_CTRL_8188F); 652 val32 &= ~(0xf << 4); 653 val32 |= usb_tx_agg_desc_num << 4; 654 rtl8xxxu_write32(priv, REG_DWBCN0_CTRL_8188F, val32); 655 rtl8xxxu_write8(priv, REG_DWBCN1_CTRL_8723B, usb_tx_agg_desc_num << 1); 656 657 /* RX aggregation */ 658 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); 659 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; 660 661 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); 662 agg_rx &= ~RXDMA_USB_AGG_ENABLE; 663 agg_rx &= ~0xFF0F; /* reset agg size and timeout */ 664 665 rxdma_mode = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B); 666 rxdma_mode &= ~BIT(1); 667 668 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 669 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); 670 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, rxdma_mode); 671} 672 673static void rtl8188fu_init_statistics(struct rtl8xxxu_priv *priv) 674{ 675 u32 val32; 676 677 /* Time duration for NHM unit: 4us, 0xc350=200ms */ 678 rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0xc350); 679 rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff); 680 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff50); 681 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); 682 683 /* TH8 */ 684 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 685 val32 |= 0xff; 686 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 687 688 /* Enable CCK */ 689 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); 690 val32 &= ~(BIT(8) | BIT(9) | BIT(10)); 691 val32 |= BIT(8); 692 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); 693 694 /* Max power amongst all RX antennas */ 695 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); 696 val32 |= BIT(7); 697 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); 698} 699 700#define TX_POWER_INDEX_MAX 0x3F 701#define TX_POWER_INDEX_DEFAULT_CCK 0x22 702#define TX_POWER_INDEX_DEFAULT_HT40 0x27 703 704static int rtl8188fu_parse_efuse(struct rtl8xxxu_priv *priv) 705{ 706 struct rtl8188fu_efuse *efuse = &priv->efuse_wifi.efuse8188fu; 707 int i; 708 709 if (efuse->rtl_id != cpu_to_le16(0x8129)) 710 return -EINVAL; 711 712 ether_addr_copy(priv->mac_addr, efuse->mac_addr); 713 714 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, 715 sizeof(efuse->tx_power_index_A.cck_base)); 716 717 memcpy(priv->ht40_1s_tx_power_index_A, 718 efuse->tx_power_index_A.ht40_base, 719 sizeof(efuse->tx_power_index_A.ht40_base)); 720 721 for (i = 0; i < ARRAY_SIZE(priv->cck_tx_power_index_A); i++) { 722 if (priv->cck_tx_power_index_A[i] > TX_POWER_INDEX_MAX) 723 priv->cck_tx_power_index_A[i] = TX_POWER_INDEX_DEFAULT_CCK; 724 } 725 726 for (i = 0; i < ARRAY_SIZE(priv->ht40_1s_tx_power_index_A); i++) { 727 if (priv->ht40_1s_tx_power_index_A[i] > TX_POWER_INDEX_MAX) 728 priv->ht40_1s_tx_power_index_A[i] = TX_POWER_INDEX_DEFAULT_HT40; 729 } 730 731 priv->ofdm_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.a; 732 priv->ht20_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; 733 734 priv->default_crystal_cap = efuse->xtal_k & 0x3f; 735 736 return 0; 737} 738 739static int rtl8188fu_load_firmware(struct rtl8xxxu_priv *priv) 740{ 741 const char *fw_name; 742 int ret; 743 744 fw_name = "rtlwifi/rtl8188fufw.bin"; 745 746 ret = rtl8xxxu_load_firmware(priv, fw_name); 747 748 return ret; 749} 750 751static void rtl8188fu_init_phy_bb(struct rtl8xxxu_priv *priv) 752{ 753 u8 val8; 754 u16 val16; 755 756 /* Enable BB and RF */ 757 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 758 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; 759 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 760 761 /* 762 * Per vendor driver, run power sequence before init of RF 763 */ 764 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; 765 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); 766 767 usleep_range(10, 20); 768 769 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780); 770 771 val8 = SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_USBA | SYS_FUNC_USBD; 772 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 773 774 rtl8xxxu_init_phy_regs(priv, rtl8188fu_phy_init_table); 775 rtl8xxxu_init_phy_regs(priv, rtl8188f_agc_table); 776} 777 778static int rtl8188fu_init_phy_rf(struct rtl8xxxu_priv *priv) 779{ 780 int ret; 781 782 if (priv->chip_cut == 1) 783 ret = rtl8xxxu_init_phy_rf(priv, rtl8188fu_cut_b_radioa_init_table, RF_A); 784 else 785 ret = rtl8xxxu_init_phy_rf(priv, rtl8188fu_radioa_init_table, RF_A); 786 787 return ret; 788} 789 790void rtl8188f_phy_lc_calibrate(struct rtl8xxxu_priv *priv) 791{ 792 u32 val32; 793 u32 rf_amode, lstf; 794 int i; 795 796 /* Check continuous TX and Packet TX */ 797 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 798 799 if (lstf & OFDM_LSTF_MASK) { 800 /* Disable all continuous TX */ 801 val32 = lstf & ~OFDM_LSTF_MASK; 802 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 803 } else { 804 /* Deal with Packet TX case */ 805 /* block all queues */ 806 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 807 } 808 809 /* Read original RF mode Path A */ 810 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); 811 812 /* Start LC calibration */ 813 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, rf_amode | 0x08000); 814 815 for (i = 0; i < 100; i++) { 816 if ((rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG) & 0x08000) == 0) 817 break; 818 msleep(10); 819 } 820 821 if (i == 100) 822 dev_warn(&priv->udev->dev, "LC calibration timed out.\n"); 823 824 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, rf_amode); 825 826 /* Restore original parameters */ 827 if (lstf & OFDM_LSTF_MASK) 828 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); 829 else /* Deal with Packet TX case */ 830 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 831} 832 833static int rtl8188fu_iqk_path_a(struct rtl8xxxu_priv *priv, u32 *lok_result) 834{ 835 u32 reg_eac, reg_e94, reg_e9c, val32; 836 int result = 0; 837 838 /* 839 * Leave IQK mode 840 */ 841 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 842 val32 &= 0x000000ff; 843 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 844 845 /* 846 * Enable path A PA in TX IQK mode 847 */ 848 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 849 val32 |= 0x80000; 850 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 851 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); 852 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); 853 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07ff7); 854 855 /* PA,PAD gain adjust */ 856 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x980); 857 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x5102a); 858 859 /* enter IQK mode */ 860 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 861 val32 &= 0x000000ff; 862 val32 |= 0x80800000; 863 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 864 865 /* path-A IQK setting */ 866 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); 867 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); 868 869 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ff); 870 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); 871 872 /* LO calibration setting */ 873 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); 874 875 /* One shot, path A LOK & IQK */ 876 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 877 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 878 879 mdelay(25); 880 881 /* 882 * Leave IQK mode 883 */ 884 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 885 val32 &= 0x000000ff; 886 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 887 888 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); 889 890 /* save LOK result */ 891 *lok_result = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC); 892 893 /* Check failed */ 894 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 895 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 896 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 897 898 if (!(reg_eac & BIT(28)) && 899 ((reg_e94 & 0x03ff0000) != 0x01420000) && 900 ((reg_e9c & 0x03ff0000) != 0x00420000)) 901 result |= 0x01; 902 903 return result; 904} 905 906static int rtl8188fu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result) 907{ 908 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; 909 int result = 0; 910 911 /* 912 * Leave IQK mode 913 */ 914 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 915 val32 &= 0x000000ff; 916 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 917 918 /* 919 * Enable path A PA in TX IQK mode 920 */ 921 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 922 val32 |= 0x80000; 923 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 924 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); 925 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); 926 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); 927 928 /* PA,PAD gain adjust */ 929 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x980); 930 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x5102a); 931 932 /* 933 * Enter IQK mode 934 */ 935 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 936 val32 &= 0x000000ff; 937 val32 |= 0x80800000; 938 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 939 940 /* 941 * Tx IQK setting 942 */ 943 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 944 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 945 946 /* path-A IQK setting */ 947 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1c); 948 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x30008c1c); 949 950 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160fff); 951 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); 952 953 /* LO calibration setting */ 954 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); 955 956 /* One shot, path A LOK & IQK */ 957 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 958 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 959 960 mdelay(25); 961 962 /* 963 * Leave IQK mode 964 */ 965 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 966 val32 &= 0x000000ff; 967 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 968 969 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); 970 971 /* Check failed */ 972 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 973 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 974 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 975 976 if (!(reg_eac & BIT(28)) && 977 ((reg_e94 & 0x03ff0000) != 0x01420000) && 978 ((reg_e9c & 0x03ff0000) != 0x00420000)) 979 result |= 0x01; 980 else /* If TX not OK, ignore RX */ 981 goto out; 982 983 val32 = 0x80007c00 | (reg_e94 & 0x3ff0000) | 984 ((reg_e9c & 0x3ff0000) >> 16); 985 rtl8xxxu_write32(priv, REG_TX_IQK, val32); 986 987 /* 988 * Modify RX IQK mode table 989 */ 990 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 991 val32 &= 0x000000ff; 992 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 993 994 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 995 val32 |= 0x80000; 996 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 997 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); 998 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); 999 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); 1000 1001 /* 1002 * PA, PAD setting 1003 */ 1004 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x980); 1005 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x51000); 1006 1007 /* 1008 * Enter IQK mode 1009 */ 1010 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1011 val32 &= 0x000000ff; 1012 val32 |= 0x80800000; 1013 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1014 1015 /* 1016 * RX IQK setting 1017 */ 1018 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 1019 1020 /* path-A IQK setting */ 1021 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x30008c1c); 1022 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1c); 1023 1024 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160000); 1025 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281613ff); 1026 1027 /* LO calibration setting */ 1028 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); 1029 1030 /* One shot, path A LOK & IQK */ 1031 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 1032 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 1033 1034 mdelay(25); 1035 1036 /* 1037 * Leave IQK mode 1038 */ 1039 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1040 val32 &= 0x000000ff; 1041 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1042 1043 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); 1044 1045 /* reload LOK value */ 1046 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC, lok_result); 1047 1048 /* Check failed */ 1049 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 1050 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); 1051 1052 if (!(reg_eac & BIT(27)) && 1053 ((reg_ea4 & 0x03ff0000) != 0x01320000) && 1054 ((reg_eac & 0x03ff0000) != 0x00360000)) 1055 result |= 0x02; 1056 1057out: 1058 return result; 1059} 1060 1061static void rtl8188fu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, 1062 int result[][8], int t) 1063{ 1064 struct device *dev = &priv->udev->dev; 1065 u32 i, val32, rx_initial_gain, lok_result; 1066 u32 path_sel_bb, path_sel_rf; 1067 int path_a_ok; 1068 int retry = 2; 1069 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { 1070 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, 1071 REG_RX_WAIT_CCA, REG_TX_CCK_RFON, 1072 REG_TX_CCK_BBON, REG_TX_OFDM_RFON, 1073 REG_TX_OFDM_BBON, REG_TX_TO_RX, 1074 REG_TX_TO_TX, REG_RX_CCK, 1075 REG_RX_OFDM, REG_RX_WAIT_RIFS, 1076 REG_RX_TO_RX, REG_STANDBY, 1077 REG_SLEEP, REG_PMPD_ANAEN 1078 }; 1079 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { 1080 REG_TXPAUSE, REG_BEACON_CTRL, 1081 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG 1082 }; 1083 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { 1084 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, 1085 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, 1086 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, 1087 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE 1088 }; 1089 1090 /* 1091 * Note: IQ calibration must be performed after loading 1092 * PHY_REG.txt , and radio_a, radio_b.txt 1093 */ 1094 1095 rx_initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 1096 1097 if (t == 0) { 1098 /* Save ADDA parameters, turn Path A ADDA on */ 1099 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, 1100 RTL8XXXU_ADDA_REGS); 1101 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 1102 rtl8xxxu_save_regs(priv, iqk_bb_regs, 1103 priv->bb_backup, RTL8XXXU_BB_REGS); 1104 } 1105 1106 rtl8xxxu_path_adda_on(priv, adda_regs, true); 1107 1108 if (t == 0) { 1109 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); 1110 priv->pi_enabled = u32_get_bits(val32, FPGA0_HSSI_PARM1_PI); 1111 } 1112 1113 /* save RF path */ 1114 path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); 1115 path_sel_rf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_S0S1); 1116 1117 /* BB setting */ 1118 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); 1119 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); 1120 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x25204000); 1121 1122 /* MAC settings */ 1123 val32 = rtl8xxxu_read32(priv, REG_TX_PTCL_CTRL); 1124 val32 |= 0x00ff0000; 1125 rtl8xxxu_write32(priv, REG_TX_PTCL_CTRL, val32); 1126 1127 /* IQ calibration setting */ 1128 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1129 val32 &= 0xff; 1130 val32 |= 0x80800000; 1131 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1132 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 1133 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 1134 1135 for (i = 0; i < retry; i++) { 1136 path_a_ok = rtl8188fu_iqk_path_a(priv, &lok_result); 1137 if (path_a_ok == 0x01) { 1138 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1139 val32 &= 0xff; 1140 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1141 1142 val32 = rtl8xxxu_read32(priv, 1143 REG_TX_POWER_BEFORE_IQK_A); 1144 result[t][0] = (val32 >> 16) & 0x3ff; 1145 1146 val32 = rtl8xxxu_read32(priv, 1147 REG_TX_POWER_AFTER_IQK_A); 1148 result[t][1] = (val32 >> 16) & 0x3ff; 1149 break; 1150 } 1151 } 1152 1153 for (i = 0; i < retry; i++) { 1154 path_a_ok = rtl8188fu_rx_iqk_path_a(priv, lok_result); 1155 if (path_a_ok == 0x03) { 1156 val32 = rtl8xxxu_read32(priv, 1157 REG_RX_POWER_BEFORE_IQK_A_2); 1158 result[t][2] = (val32 >> 16) & 0x3ff; 1159 1160 val32 = rtl8xxxu_read32(priv, 1161 REG_RX_POWER_AFTER_IQK_A_2); 1162 result[t][3] = (val32 >> 16) & 0x3ff; 1163 break; 1164 } 1165 } 1166 1167 if (!path_a_ok) 1168 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__); 1169 1170 /* Back to BB mode, load original value */ 1171 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1172 val32 &= 0xff; 1173 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1174 1175 if (t == 0) 1176 return; 1177 1178 if (!priv->pi_enabled) { 1179 /* 1180 * Switch back BB to SI mode after finishing 1181 * IQ Calibration 1182 */ 1183 val32 = 0x01000000; 1184 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); 1185 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); 1186 } 1187 1188 /* Reload ADDA power saving parameters */ 1189 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, 1190 RTL8XXXU_ADDA_REGS); 1191 1192 /* Reload MAC parameters */ 1193 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 1194 1195 /* Reload BB parameters */ 1196 rtl8xxxu_restore_regs(priv, iqk_bb_regs, 1197 priv->bb_backup, RTL8XXXU_BB_REGS); 1198 1199 /* Reload RF path */ 1200 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); 1201 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, path_sel_rf); 1202 1203 /* Restore RX initial gain */ 1204 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 1205 val32 &= 0xffffff00; 1206 val32 |= 0x50; 1207 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); 1208 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 1209 val32 &= 0xffffff00; 1210 val32 |= rx_initial_gain & 0xff; 1211 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); 1212 1213 /* Load 0xe30 IQC default value */ 1214 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); 1215 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); 1216} 1217 1218static void rtl8188fu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) 1219{ 1220 struct device *dev = &priv->udev->dev; 1221 int result[4][8]; /* last is final result */ 1222 int i, candidate; 1223 bool path_a_ok; 1224 u32 reg_e94, reg_e9c, reg_ea4, reg_eac; 1225 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; 1226 s32 reg_tmp = 0; 1227 bool simu; 1228 u32 path_sel_bb, path_sel_rf; 1229 1230 /* Save RF path */ 1231 path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); 1232 path_sel_rf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_S0S1); 1233 1234 memset(result, 0, sizeof(result)); 1235 candidate = -1; 1236 1237 path_a_ok = false; 1238 1239 for (i = 0; i < 3; i++) { 1240 rtl8188fu_phy_iqcalibrate(priv, result, i); 1241 1242 if (i == 1) { 1243 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 1); 1244 if (simu) { 1245 candidate = 0; 1246 break; 1247 } 1248 } 1249 1250 if (i == 2) { 1251 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 2); 1252 if (simu) { 1253 candidate = 0; 1254 break; 1255 } 1256 1257 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 1, 2); 1258 if (simu) { 1259 candidate = 1; 1260 } else { 1261 for (i = 0; i < 8; i++) 1262 reg_tmp += result[3][i]; 1263 1264 if (reg_tmp) 1265 candidate = 3; 1266 else 1267 candidate = -1; 1268 } 1269 } 1270 } 1271 1272 for (i = 0; i < 4; i++) { 1273 reg_e94 = result[i][0]; 1274 reg_e9c = result[i][1]; 1275 reg_ea4 = result[i][2]; 1276 reg_eac = result[i][3]; 1277 reg_eb4 = result[i][4]; 1278 reg_ebc = result[i][5]; 1279 reg_ec4 = result[i][6]; 1280 reg_ecc = result[i][7]; 1281 } 1282 1283 if (candidate >= 0) { 1284 reg_e94 = result[candidate][0]; 1285 priv->rege94 = reg_e94; 1286 reg_e9c = result[candidate][1]; 1287 priv->rege9c = reg_e9c; 1288 reg_ea4 = result[candidate][2]; 1289 reg_eac = result[candidate][3]; 1290 reg_eb4 = result[candidate][4]; 1291 priv->regeb4 = reg_eb4; 1292 reg_ebc = result[candidate][5]; 1293 priv->regebc = reg_ebc; 1294 reg_ec4 = result[candidate][6]; 1295 reg_ecc = result[candidate][7]; 1296 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); 1297 dev_dbg(dev, 1298 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", 1299 __func__, reg_e94, reg_e9c, 1300 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); 1301 path_a_ok = true; 1302 } else { 1303 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; 1304 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; 1305 } 1306 1307 if (reg_e94 && candidate >= 0) 1308 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, 1309 candidate, (reg_ea4 == 0)); 1310 1311 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, 1312 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); 1313 1314 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); 1315 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, path_sel_rf); 1316} 1317 1318static void rtl8188f_disabled_to_emu(struct rtl8xxxu_priv *priv) 1319{ 1320 u16 val8; 1321 1322 /* 0x04[12:11] = 2b'01enable WL suspend */ 1323 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1324 val8 &= ~((APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND) >> 8); 1325 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1326 1327 /* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode */ 1328 val8 = rtl8xxxu_read8(priv, 0xc4); 1329 val8 &= ~BIT(4); 1330 rtl8xxxu_write8(priv, 0xc4, val8); 1331} 1332 1333static int rtl8188f_emu_to_active(struct rtl8xxxu_priv *priv) 1334{ 1335 u8 val8; 1336 u32 val32; 1337 int count, ret = 0; 1338 1339 /* Disable SW LPS */ 1340 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1341 val8 &= ~(APS_FSMCO_SW_LPS >> 8); 1342 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1343 1344 /* wait till 0x04[17] = 1 power ready */ 1345 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1346 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1347 if (val32 & BIT(17)) 1348 break; 1349 1350 udelay(10); 1351 } 1352 1353 if (!count) { 1354 ret = -EBUSY; 1355 goto exit; 1356 } 1357 1358 /* Disable HWPDN */ 1359 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1360 val8 &= ~(APS_FSMCO_HW_POWERDOWN >> 8); 1361 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1362 1363 /* Disable WL suspend */ 1364 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1365 val8 &= ~(APS_FSMCO_HW_SUSPEND >> 8); 1366 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1367 1368 /* set, then poll until 0 */ 1369 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1370 val8 |= APS_FSMCO_MAC_ENABLE >> 8; 1371 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1372 1373 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1374 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1375 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { 1376 ret = 0; 1377 break; 1378 } 1379 udelay(10); 1380 } 1381 1382 if (!count) { 1383 ret = -EBUSY; 1384 goto exit; 1385 } 1386 1387 /* 0x27<=35 to reduce RF noise */ 1388 val8 = rtl8xxxu_write8(priv, 0x27, 0x35); 1389exit: 1390 return ret; 1391} 1392 1393static int rtl8188fu_active_to_emu(struct rtl8xxxu_priv *priv) 1394{ 1395 u8 val8; 1396 u32 val32; 1397 int count, ret = 0; 1398 1399 /* Turn off RF */ 1400 rtl8xxxu_write8(priv, REG_RF_CTRL, 0); 1401 1402 /* 0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ 1403 val8 = rtl8xxxu_read8(priv, 0x4e); 1404 val8 &= ~BIT(7); 1405 rtl8xxxu_write8(priv, 0x4e, val8); 1406 1407 /* 0x27 <= 34, xtal_qsel = 0 to xtal bring up */ 1408 rtl8xxxu_write8(priv, 0x27, 0x34); 1409 1410 /* 0x04[9] = 1 turn off MAC by HW state machine */ 1411 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1412 val8 |= APS_FSMCO_MAC_OFF >> 8; 1413 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1414 1415 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1416 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1417 if ((val32 & APS_FSMCO_MAC_OFF) == 0) { 1418 ret = 0; 1419 break; 1420 } 1421 udelay(10); 1422 } 1423 1424 if (!count) { 1425 ret = -EBUSY; 1426 goto exit; 1427 } 1428 1429exit: 1430 return ret; 1431} 1432 1433static int rtl8188fu_emu_to_disabled(struct rtl8xxxu_priv *priv) 1434{ 1435 u8 val8; 1436 1437 /* 0x04[12:11] = 2b'01 enable WL suspend */ 1438 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1439 val8 &= ~((APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND) >> 8); 1440 val8 |= APS_FSMCO_HW_SUSPEND >> 8; 1441 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1442 1443 /* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode */ 1444 val8 = rtl8xxxu_read8(priv, 0xc4); 1445 val8 |= BIT(4); 1446 rtl8xxxu_write8(priv, 0xc4, val8); 1447 1448 return 0; 1449} 1450 1451static int rtl8188fu_active_to_lps(struct rtl8xxxu_priv *priv) 1452{ 1453 struct device *dev = &priv->udev->dev; 1454 u8 val8; 1455 u16 val16; 1456 u32 val32; 1457 int retry, retval; 1458 1459 /* set RPWM IMR */ 1460 val8 = rtl8xxxu_read8(priv, REG_FTIMR + 1); 1461 val8 |= IMR0_CPWM >> 8; 1462 rtl8xxxu_write8(priv, REG_FTIMR + 1, val8); 1463 1464 /* Tx Pause */ 1465 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 1466 1467 retry = 100; 1468 retval = -EBUSY; 1469 1470 /* 1471 * Poll 32 bit wide REG_SCH_TX_CMD for 0x00000000 to ensure no TX is pending. 1472 */ 1473 do { 1474 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); 1475 if (!val32) { 1476 retval = 0; 1477 break; 1478 } 1479 } while (retry--); 1480 1481 if (!retry) { 1482 dev_warn(dev, "Failed to flush TX queue\n"); 1483 retval = -EBUSY; 1484 goto out; 1485 } 1486 1487 /* Disable CCK and OFDM, clock gated */ 1488 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 1489 val8 &= ~SYS_FUNC_BBRSTB; 1490 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 1491 1492 udelay(2); 1493 1494 /* Whole BB is reset */ 1495 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 1496 val8 &= ~SYS_FUNC_BB_GLB_RSTN; 1497 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 1498 1499 /* Reset MAC TRX */ 1500 val16 = rtl8xxxu_read16(priv, REG_CR); 1501 val16 |= 0x3f; 1502 val16 &= ~(CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | CR_SECURITY_ENABLE); 1503 rtl8xxxu_write16(priv, REG_CR, val16); 1504 1505 /* Respond TxOK to scheduler */ 1506 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); 1507 val8 |= DUAL_TSF_TX_OK; 1508 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); 1509 1510out: 1511 return retval; 1512} 1513 1514static int rtl8188fu_power_on(struct rtl8xxxu_priv *priv) 1515{ 1516 u16 val16; 1517 int ret; 1518 1519 rtl8188f_disabled_to_emu(priv); 1520 1521 ret = rtl8188f_emu_to_active(priv); 1522 if (ret) 1523 goto exit; 1524 1525 rtl8xxxu_write8(priv, REG_CR, 0); 1526 1527 val16 = rtl8xxxu_read16(priv, REG_CR); 1528 1529 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | 1530 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | 1531 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | 1532 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); 1533 rtl8xxxu_write16(priv, REG_CR, val16); 1534 1535exit: 1536 return ret; 1537} 1538 1539static void rtl8188fu_power_off(struct rtl8xxxu_priv *priv) 1540{ 1541 u8 val8; 1542 u16 val16; 1543 1544 rtl8xxxu_flush_fifo(priv); 1545 1546 val16 = rtl8xxxu_read16(priv, REG_GPIO_MUXCFG); 1547 val16 &= ~BIT(12); 1548 rtl8xxxu_write16(priv, REG_GPIO_MUXCFG, val16); 1549 1550 rtl8xxxu_write32(priv, REG_HISR0, 0xFFFFFFFF); 1551 rtl8xxxu_write32(priv, REG_HISR1, 0xFFFFFFFF); 1552 1553 /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */ 1554 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); 1555 val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; 1556 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); 1557 1558 /* Turn off RF */ 1559 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); 1560 1561 /* Reset Firmware if running in RAM */ 1562 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) 1563 rtl8xxxu_firmware_self_reset(priv); 1564 1565 rtl8188fu_active_to_lps(priv); 1566 1567 /* Reset MCU */ 1568 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1569 val16 &= ~SYS_FUNC_CPU_ENABLE; 1570 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 1571 1572 /* Reset MCU ready status */ 1573 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); 1574 1575 rtl8188fu_active_to_emu(priv); 1576 rtl8188fu_emu_to_disabled(priv); 1577} 1578 1579#define PPG_BB_GAIN_2G_TXA_OFFSET_8188F 0xee 1580#define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0f 1581 1582static void rtl8188f_enable_rf(struct rtl8xxxu_priv *priv) 1583{ 1584 u32 val32; 1585 u8 pg_pwrtrim = 0xff, val8; 1586 s8 bb_gain; 1587 1588 /* Somehow this is not found in the efuse we read earlier. */ 1589 rtl8xxxu_read_efuse8(priv, PPG_BB_GAIN_2G_TXA_OFFSET_8188F, &pg_pwrtrim); 1590 1591 if (pg_pwrtrim != 0xff) { 1592 bb_gain = pg_pwrtrim & PPG_BB_GAIN_2G_TX_OFFSET_MASK; 1593 1594 if (bb_gain == PPG_BB_GAIN_2G_TX_OFFSET_MASK) 1595 bb_gain = 0; 1596 else if (bb_gain & 1) 1597 bb_gain = bb_gain >> 1; 1598 else 1599 bb_gain = -(bb_gain >> 1); 1600 1601 val8 = abs(bb_gain); 1602 if (bb_gain > 0) 1603 val8 |= BIT(5); 1604 1605 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55); 1606 val32 &= ~0xfc000; 1607 val32 |= val8 << 14; 1608 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, val32); 1609 } 1610 1611 rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); 1612 1613 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1614 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); 1615 val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_TX_A; 1616 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1617 1618 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 1619} 1620 1621static void rtl8188f_disable_rf(struct rtl8xxxu_priv *priv) 1622{ 1623 u32 val32; 1624 1625 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1626 val32 &= ~OFDM_RF_PATH_TX_MASK; 1627 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1628 1629 /* Power down RF module */ 1630 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); 1631} 1632 1633static void rtl8188f_usb_quirks(struct rtl8xxxu_priv *priv) 1634{ 1635 u16 val16; 1636 u32 val32; 1637 1638 val16 = rtl8xxxu_read16(priv, REG_CR); 1639 val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE); 1640 rtl8xxxu_write16(priv, REG_CR, val16); 1641 1642 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); 1643 val32 |= TXDMA_OFFSET_DROP_DATA_EN; 1644 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); 1645} 1646 1647#define XTAL1 GENMASK(22, 17) 1648#define XTAL0 GENMASK(16, 11) 1649 1650void rtl8188f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap) 1651{ 1652 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; 1653 u32 val32; 1654 1655 if (crystal_cap == cfo->crystal_cap) 1656 return; 1657 1658 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); 1659 1660 dev_dbg(&priv->udev->dev, 1661 "%s: Adjusting crystal cap from 0x%x (actually 0x%lx 0x%lx) to 0x%x\n", 1662 __func__, 1663 cfo->crystal_cap, 1664 FIELD_GET(XTAL1, val32), 1665 FIELD_GET(XTAL0, val32), 1666 crystal_cap); 1667 1668 val32 &= ~(XTAL1 | XTAL0); 1669 val32 |= FIELD_PREP(XTAL1, crystal_cap) | 1670 FIELD_PREP(XTAL0, crystal_cap); 1671 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); 1672 1673 cfo->crystal_cap = crystal_cap; 1674} 1675 1676static s8 rtl8188f_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) 1677{ 1678 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; 1679 s8 rx_pwr_all = 0x00; 1680 u8 vga_idx, lna_idx; 1681 1682 lna_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK); 1683 vga_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK); 1684 1685 switch (lna_idx) { 1686 case 7: 1687 if (vga_idx <= 27) 1688 rx_pwr_all = -100 + 2 * (27 - vga_idx); 1689 else 1690 rx_pwr_all = -100; 1691 break; 1692 case 5: 1693 rx_pwr_all = -74 + 2 * (21 - vga_idx); 1694 break; 1695 case 3: 1696 rx_pwr_all = -60 + 2 * (20 - vga_idx); 1697 break; 1698 case 1: 1699 rx_pwr_all = -44 + 2 * (19 - vga_idx); 1700 break; 1701 default: 1702 break; 1703 } 1704 1705 return rx_pwr_all; 1706} 1707 1708struct rtl8xxxu_fileops rtl8188fu_fops = { 1709 .identify_chip = rtl8188fu_identify_chip, 1710 .parse_efuse = rtl8188fu_parse_efuse, 1711 .load_firmware = rtl8188fu_load_firmware, 1712 .power_on = rtl8188fu_power_on, 1713 .power_off = rtl8188fu_power_off, 1714 .read_efuse = rtl8xxxu_read_efuse, 1715 .reset_8051 = rtl8xxxu_reset_8051, 1716 .llt_init = rtl8xxxu_auto_llt_table, 1717 .init_phy_bb = rtl8188fu_init_phy_bb, 1718 .init_phy_rf = rtl8188fu_init_phy_rf, 1719 .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection, 1720 .phy_lc_calibrate = rtl8188f_phy_lc_calibrate, 1721 .phy_iq_calibrate = rtl8188fu_phy_iq_calibrate, 1722 .config_channel = rtl8188fu_config_channel, 1723 .parse_rx_desc = rtl8xxxu_parse_rxdesc24, 1724 .parse_phystats = rtl8723au_rx_parse_phystats, 1725 .init_aggregation = rtl8188fu_init_aggregation, 1726 .init_statistics = rtl8188fu_init_statistics, 1727 .init_burst = rtl8xxxu_init_burst, 1728 .enable_rf = rtl8188f_enable_rf, 1729 .disable_rf = rtl8188f_disable_rf, 1730 .usb_quirks = rtl8188f_usb_quirks, 1731 .set_tx_power = rtl8188f_set_tx_power, 1732 .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, 1733 .report_connect = rtl8xxxu_gen2_report_connect, 1734 .report_rssi = rtl8xxxu_gen2_report_rssi, 1735 .fill_txdesc = rtl8xxxu_fill_txdesc_v2, 1736 .set_crystal_cap = rtl8188f_set_crystal_cap, 1737 .cck_rssi = rtl8188f_cck_rssi, 1738 .writeN_block_size = 128, 1739 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), 1740 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), 1741 .has_s0s1 = 1, 1742 .has_tx_report = 1, 1743 .gen2_thermal_meter = 1, 1744 .needs_full_init = 1, 1745 .init_reg_rxfltmap = 1, 1746 .init_reg_pkt_life_time = 1, 1747 .init_reg_hmtfr = 1, 1748 .ampdu_max_time = 0x70, 1749 .ustime_tsf_edca = 0x28, 1750 .max_aggr_num = 0x0c14, 1751 .supports_ap = 1, 1752 .max_macid_num = 16, 1753 .max_sec_cam_num = 16, 1754 .supports_concurrent = 1, 1755 .adda_1t_init = 0x03c00014, 1756 .adda_1t_path_on = 0x03c00014, 1757 .trxff_boundary = 0x3f7f, 1758 .pbp_rx = PBP_PAGE_SIZE_256, 1759 .pbp_tx = PBP_PAGE_SIZE_256, 1760 .mactable = rtl8188f_mac_init_table, 1761 .total_page_num = TX_TOTAL_PAGE_NUM_8188F, 1762 .page_num_hi = TX_PAGE_NUM_HI_PQ_8188F, 1763 .page_num_lo = TX_PAGE_NUM_LO_PQ_8188F, 1764 .page_num_norm = TX_PAGE_NUM_NORM_PQ_8188F, 1765};
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