rt2800lib.c

    1// SPDX-License-Identifier: GPL-2.0-or-later
    2/*
    3	Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
    4	Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
    5	Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
    6	Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
    7
    8	Based on the original rt2800pci.c and rt2800usb.c.
    9	  Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   10	  Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   11	  Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   12	  Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
   13	  Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
   14	  Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
   15	  <http://rt2x00.serialmonkey.com>
   16
   17 */
   18
   19/*
   20	Module: rt2800lib
   21	Abstract: rt2800 generic device routines.
   22 */
   23
   24#include <linux/crc-ccitt.h>
   25#include <linux/kernel.h>
   26#include <linux/module.h>
   27#include <linux/nvmem-consumer.h>
   28#include <linux/slab.h>
   29
   30#include "rt2x00.h"
   31#include "rt2800lib.h"
   32#include "rt2800.h"
   33
   34static unsigned int modparam_watchdog = RT2800_WATCHDOG_DMA_BUSY;
   35module_param_named(watchdog, modparam_watchdog, uint, 0444);
   36MODULE_PARM_DESC(watchdog, "Enable watchdog to recover tx/rx hangs.\n"
   37		 "\t\t(0=disabled, 1=hang watchdog, 2=DMA watchdog(default), 3=both)");
   38
   39/*
   40 * Register access.
   41 * All access to the CSR registers will go through the methods
   42 * rt2800_register_read and rt2800_register_write.
   43 * BBP and RF register require indirect register access,
   44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
   45 * These indirect registers work with busy bits,
   46 * and we will try maximal REGISTER_BUSY_COUNT times to access
   47 * the register while taking a REGISTER_BUSY_DELAY us delay
   48 * between each attampt. When the busy bit is still set at that time,
   49 * the access attempt is considered to have failed,
   50 * and we will print an error.
   51 * The _lock versions must be used if you already hold the csr_mutex
   52 */
   53#define WAIT_FOR_BBP(__dev, __reg) \
   54	rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
   55#define WAIT_FOR_RFCSR(__dev, __reg) \
   56	rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
   57#define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
   58	rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \
   59			    (__reg))
   60#define WAIT_FOR_RF(__dev, __reg) \
   61	rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
   62#define WAIT_FOR_MCU(__dev, __reg) \
   63	rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
   64			    H2M_MAILBOX_CSR_OWNER, (__reg))
   65
   66static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
   67{
   68	/* check for rt2872 on SoC */
   69	if (!rt2x00_is_soc(rt2x00dev) ||
   70	    !rt2x00_rt(rt2x00dev, RT2872))
   71		return false;
   72
   73	/* we know for sure that these rf chipsets are used on rt305x boards */
   74	if (rt2x00_rf(rt2x00dev, RF3020) ||
   75	    rt2x00_rf(rt2x00dev, RF3021) ||
   76	    rt2x00_rf(rt2x00dev, RF3022))
   77		return true;
   78
   79	rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
   80	return false;
   81}
   82
   83static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
   84			     const unsigned int word, const u8 value)
   85{
   86	u32 reg;
   87
   88	mutex_lock(&rt2x00dev->csr_mutex);
   89
   90	/*
   91	 * Wait until the BBP becomes available, afterwards we
   92	 * can safely write the new data into the register.
   93	 */
   94	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
   95		reg = 0;
   96		rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
   97		rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
   98		rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
   99		rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  100		rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  101
  102		rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  103	}
  104
  105	mutex_unlock(&rt2x00dev->csr_mutex);
  106}
  107
  108static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word)
  109{
  110	u32 reg;
  111	u8 value;
  112
  113	mutex_lock(&rt2x00dev->csr_mutex);
  114
  115	/*
  116	 * Wait until the BBP becomes available, afterwards we
  117	 * can safely write the read request into the register.
  118	 * After the data has been written, we wait until hardware
  119	 * returns the correct value, if at any time the register
  120	 * doesn't become available in time, reg will be 0xffffffff
  121	 * which means we return 0xff to the caller.
  122	 */
  123	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  124		reg = 0;
  125		rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  126		rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  127		rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
  128		rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  129
  130		rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  131
  132		WAIT_FOR_BBP(rt2x00dev, &reg);
  133	}
  134
  135	value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
  136
  137	mutex_unlock(&rt2x00dev->csr_mutex);
  138
  139	return value;
  140}
  141
  142static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
  143			       const unsigned int word, const u8 value)
  144{
  145	u32 reg;
  146
  147	mutex_lock(&rt2x00dev->csr_mutex);
  148
  149	/*
  150	 * Wait until the RFCSR becomes available, afterwards we
  151	 * can safely write the new data into the register.
  152	 */
  153	switch (rt2x00dev->chip.rt) {
  154	case RT6352:
  155		if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
  156			reg = 0;
  157			rt2x00_set_field32(&reg, RF_CSR_CFG_DATA_MT7620, value);
  158			rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
  159					   word);
  160			rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 1);
  161			rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
  162
  163			rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
  164		}
  165		break;
  166
  167	default:
  168		if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
  169			reg = 0;
  170			rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
  171			rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
  172			rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
  173			rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
  174
  175			rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
  176		}
  177		break;
  178	}
  179
  180	mutex_unlock(&rt2x00dev->csr_mutex);
  181}
  182
  183static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
  184				    const unsigned int reg, const u8 value)
  185{
  186	rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
  187}
  188
  189static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
  190				       const unsigned int reg, const u8 value)
  191{
  192	rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
  193	rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
  194}
  195
  196static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
  197				     const unsigned int reg, const u8 value)
  198{
  199	rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
  200	rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
  201}
  202
  203static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
  204				  const u8 reg, const u8 value)
  205{
  206	rt2800_bbp_write(rt2x00dev, 158, reg);
  207	rt2800_bbp_write(rt2x00dev, 159, value);
  208}
  209
  210static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg)
  211{
  212	rt2800_bbp_write(rt2x00dev, 158, reg);
  213	return rt2800_bbp_read(rt2x00dev, 159);
  214}
  215
  216static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
  217				  const u8 reg, const u8 value)
  218{
  219	rt2800_bbp_write(rt2x00dev, 195, reg);
  220	rt2800_bbp_write(rt2x00dev, 196, value);
  221}
  222
  223static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
  224			    const unsigned int word)
  225{
  226	u32 reg;
  227	u8 value;
  228
  229	mutex_lock(&rt2x00dev->csr_mutex);
  230
  231	/*
  232	 * Wait until the RFCSR becomes available, afterwards we
  233	 * can safely write the read request into the register.
  234	 * After the data has been written, we wait until hardware
  235	 * returns the correct value, if at any time the register
  236	 * doesn't become available in time, reg will be 0xffffffff
  237	 * which means we return 0xff to the caller.
  238	 */
  239	switch (rt2x00dev->chip.rt) {
  240	case RT6352:
  241		if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
  242			reg = 0;
  243			rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
  244					   word);
  245			rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 0);
  246			rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
  247
  248			rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
  249
  250			WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg);
  251		}
  252
  253		value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
  254		break;
  255
  256	default:
  257		if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
  258			reg = 0;
  259			rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
  260			rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
  261			rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
  262
  263			rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
  264
  265			WAIT_FOR_RFCSR(rt2x00dev, &reg);
  266		}
  267
  268		value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
  269		break;
  270	}
  271
  272	mutex_unlock(&rt2x00dev->csr_mutex);
  273
  274	return value;
  275}
  276
  277static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
  278				 const unsigned int reg)
  279{
  280	return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)));
  281}
  282
  283static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
  284			    const unsigned int word, const u32 value)
  285{
  286	u32 reg;
  287
  288	mutex_lock(&rt2x00dev->csr_mutex);
  289
  290	/*
  291	 * Wait until the RF becomes available, afterwards we
  292	 * can safely write the new data into the register.
  293	 */
  294	if (WAIT_FOR_RF(rt2x00dev, &reg)) {
  295		reg = 0;
  296		rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
  297		rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
  298		rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
  299		rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
  300
  301		rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
  302		rt2x00_rf_write(rt2x00dev, word, value);
  303	}
  304
  305	mutex_unlock(&rt2x00dev->csr_mutex);
  306}
  307
  308static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
  309	[EEPROM_CHIP_ID]		= 0x0000,
  310	[EEPROM_VERSION]		= 0x0001,
  311	[EEPROM_MAC_ADDR_0]		= 0x0002,
  312	[EEPROM_MAC_ADDR_1]		= 0x0003,
  313	[EEPROM_MAC_ADDR_2]		= 0x0004,
  314	[EEPROM_NIC_CONF0]		= 0x001a,
  315	[EEPROM_NIC_CONF1]		= 0x001b,
  316	[EEPROM_FREQ]			= 0x001d,
  317	[EEPROM_LED_AG_CONF]		= 0x001e,
  318	[EEPROM_LED_ACT_CONF]		= 0x001f,
  319	[EEPROM_LED_POLARITY]		= 0x0020,
  320	[EEPROM_NIC_CONF2]		= 0x0021,
  321	[EEPROM_LNA]			= 0x0022,
  322	[EEPROM_RSSI_BG]		= 0x0023,
  323	[EEPROM_RSSI_BG2]		= 0x0024,
  324	[EEPROM_TXMIXER_GAIN_BG]	= 0x0024, /* overlaps with RSSI_BG2 */
  325	[EEPROM_RSSI_A]			= 0x0025,
  326	[EEPROM_RSSI_A2]		= 0x0026,
  327	[EEPROM_TXMIXER_GAIN_A]		= 0x0026, /* overlaps with RSSI_A2 */
  328	[EEPROM_EIRP_MAX_TX_POWER]	= 0x0027,
  329	[EEPROM_TXPOWER_DELTA]		= 0x0028,
  330	[EEPROM_TXPOWER_BG1]		= 0x0029,
  331	[EEPROM_TXPOWER_BG2]		= 0x0030,
  332	[EEPROM_TSSI_BOUND_BG1]		= 0x0037,
  333	[EEPROM_TSSI_BOUND_BG2]		= 0x0038,
  334	[EEPROM_TSSI_BOUND_BG3]		= 0x0039,
  335	[EEPROM_TSSI_BOUND_BG4]		= 0x003a,
  336	[EEPROM_TSSI_BOUND_BG5]		= 0x003b,
  337	[EEPROM_TXPOWER_A1]		= 0x003c,
  338	[EEPROM_TXPOWER_A2]		= 0x0053,
  339	[EEPROM_TXPOWER_INIT]		= 0x0068,
  340	[EEPROM_TSSI_BOUND_A1]		= 0x006a,
  341	[EEPROM_TSSI_BOUND_A2]		= 0x006b,
  342	[EEPROM_TSSI_BOUND_A3]		= 0x006c,
  343	[EEPROM_TSSI_BOUND_A4]		= 0x006d,
  344	[EEPROM_TSSI_BOUND_A5]		= 0x006e,
  345	[EEPROM_TXPOWER_BYRATE]		= 0x006f,
  346	[EEPROM_BBP_START]		= 0x0078,
  347};
  348
  349static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
  350	[EEPROM_CHIP_ID]		= 0x0000,
  351	[EEPROM_VERSION]		= 0x0001,
  352	[EEPROM_MAC_ADDR_0]		= 0x0002,
  353	[EEPROM_MAC_ADDR_1]		= 0x0003,
  354	[EEPROM_MAC_ADDR_2]		= 0x0004,
  355	[EEPROM_NIC_CONF0]		= 0x001a,
  356	[EEPROM_NIC_CONF1]		= 0x001b,
  357	[EEPROM_NIC_CONF2]		= 0x001c,
  358	[EEPROM_EIRP_MAX_TX_POWER]	= 0x0020,
  359	[EEPROM_FREQ]			= 0x0022,
  360	[EEPROM_LED_AG_CONF]		= 0x0023,
  361	[EEPROM_LED_ACT_CONF]		= 0x0024,
  362	[EEPROM_LED_POLARITY]		= 0x0025,
  363	[EEPROM_LNA]			= 0x0026,
  364	[EEPROM_EXT_LNA2]		= 0x0027,
  365	[EEPROM_RSSI_BG]		= 0x0028,
  366	[EEPROM_RSSI_BG2]		= 0x0029,
  367	[EEPROM_RSSI_A]			= 0x002a,
  368	[EEPROM_RSSI_A2]		= 0x002b,
  369	[EEPROM_TXPOWER_BG1]		= 0x0030,
  370	[EEPROM_TXPOWER_BG2]		= 0x0037,
  371	[EEPROM_EXT_TXPOWER_BG3]	= 0x003e,
  372	[EEPROM_TSSI_BOUND_BG1]		= 0x0045,
  373	[EEPROM_TSSI_BOUND_BG2]		= 0x0046,
  374	[EEPROM_TSSI_BOUND_BG3]		= 0x0047,
  375	[EEPROM_TSSI_BOUND_BG4]		= 0x0048,
  376	[EEPROM_TSSI_BOUND_BG5]		= 0x0049,
  377	[EEPROM_TXPOWER_A1]		= 0x004b,
  378	[EEPROM_TXPOWER_A2]		= 0x0065,
  379	[EEPROM_EXT_TXPOWER_A3]		= 0x007f,
  380	[EEPROM_TSSI_BOUND_A1]		= 0x009a,
  381	[EEPROM_TSSI_BOUND_A2]		= 0x009b,
  382	[EEPROM_TSSI_BOUND_A3]		= 0x009c,
  383	[EEPROM_TSSI_BOUND_A4]		= 0x009d,
  384	[EEPROM_TSSI_BOUND_A5]		= 0x009e,
  385	[EEPROM_TXPOWER_BYRATE]		= 0x00a0,
  386};
  387
  388static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
  389					     const enum rt2800_eeprom_word word)
  390{
  391	const unsigned int *map;
  392	unsigned int index;
  393
  394	if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
  395		      "%s: invalid EEPROM word %d\n",
  396		      wiphy_name(rt2x00dev->hw->wiphy), word))
  397		return 0;
  398
  399	if (rt2x00_rt(rt2x00dev, RT3593) ||
  400	    rt2x00_rt(rt2x00dev, RT3883))
  401		map = rt2800_eeprom_map_ext;
  402	else
  403		map = rt2800_eeprom_map;
  404
  405	index = map[word];
  406
  407	/* Index 0 is valid only for EEPROM_CHIP_ID.
  408	 * Otherwise it means that the offset of the
  409	 * given word is not initialized in the map,
  410	 * or that the field is not usable on the
  411	 * actual chipset.
  412	 */
  413	WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
  414		  "%s: invalid access of EEPROM word %d\n",
  415		  wiphy_name(rt2x00dev->hw->wiphy), word);
  416
  417	return index;
  418}
  419
  420static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
  421				const enum rt2800_eeprom_word word)
  422{
  423	unsigned int index;
  424
  425	index = rt2800_eeprom_word_index(rt2x00dev, word);
  426	return rt2x00_eeprom_addr(rt2x00dev, index);
  427}
  428
  429static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
  430			      const enum rt2800_eeprom_word word)
  431{
  432	unsigned int index;
  433
  434	index = rt2800_eeprom_word_index(rt2x00dev, word);
  435	return rt2x00_eeprom_read(rt2x00dev, index);
  436}
  437
  438static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
  439				const enum rt2800_eeprom_word word, u16 data)
  440{
  441	unsigned int index;
  442
  443	index = rt2800_eeprom_word_index(rt2x00dev, word);
  444	rt2x00_eeprom_write(rt2x00dev, index, data);
  445}
  446
  447static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
  448					 const enum rt2800_eeprom_word array,
  449					 unsigned int offset)
  450{
  451	unsigned int index;
  452
  453	index = rt2800_eeprom_word_index(rt2x00dev, array);
  454	return rt2x00_eeprom_read(rt2x00dev, index + offset);
  455}
  456
  457static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
  458{
  459	u32 reg;
  460	int i, count;
  461
  462	reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
  463	rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
  464	rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
  465	rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
  466	rt2x00_set_field32(&reg, WLAN_EN, 1);
  467	rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
  468
  469	udelay(REGISTER_BUSY_DELAY);
  470
  471	count = 0;
  472	do {
  473		/*
  474		 * Check PLL_LD & XTAL_RDY.
  475		 */
  476		for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  477			reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
  478			if (rt2x00_get_field32(reg, PLL_LD) &&
  479			    rt2x00_get_field32(reg, XTAL_RDY))
  480				break;
  481			udelay(REGISTER_BUSY_DELAY);
  482		}
  483
  484		if (i >= REGISTER_BUSY_COUNT) {
  485
  486			if (count >= 10)
  487				return -EIO;
  488
  489			rt2800_register_write(rt2x00dev, 0x58, 0x018);
  490			udelay(REGISTER_BUSY_DELAY);
  491			rt2800_register_write(rt2x00dev, 0x58, 0x418);
  492			udelay(REGISTER_BUSY_DELAY);
  493			rt2800_register_write(rt2x00dev, 0x58, 0x618);
  494			udelay(REGISTER_BUSY_DELAY);
  495			count++;
  496		} else {
  497			count = 0;
  498		}
  499
  500		reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
  501		rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
  502		rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
  503		rt2x00_set_field32(&reg, WLAN_RESET, 1);
  504		rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
  505		udelay(10);
  506		rt2x00_set_field32(&reg, WLAN_RESET, 0);
  507		rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
  508		udelay(10);
  509		rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
  510	} while (count != 0);
  511
  512	return 0;
  513}
  514
  515void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
  516			const u8 command, const u8 token,
  517			const u8 arg0, const u8 arg1)
  518{
  519	u32 reg;
  520
  521	/*
  522	 * SOC devices don't support MCU requests.
  523	 */
  524	if (rt2x00_is_soc(rt2x00dev))
  525		return;
  526
  527	mutex_lock(&rt2x00dev->csr_mutex);
  528
  529	/*
  530	 * Wait until the MCU becomes available, afterwards we
  531	 * can safely write the new data into the register.
  532	 */
  533	if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
  534		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
  535		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
  536		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
  537		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
  538		rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
  539
  540		reg = 0;
  541		rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
  542		rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
  543	}
  544
  545	mutex_unlock(&rt2x00dev->csr_mutex);
  546}
  547EXPORT_SYMBOL_GPL(rt2800_mcu_request);
  548
  549int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
  550{
  551	unsigned int i = 0;
  552	u32 reg;
  553
  554	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  555		reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
  556		if (reg && reg != ~0)
  557			return 0;
  558		msleep(1);
  559	}
  560
  561	rt2x00_err(rt2x00dev, "Unstable hardware\n");
  562	return -EBUSY;
  563}
  564EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
  565
  566int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
  567{
  568	unsigned int i;
  569	u32 reg;
  570
  571	/*
  572	 * Some devices are really slow to respond here. Wait a whole second
  573	 * before timing out.
  574	 */
  575	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  576		reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
  577		if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
  578		    !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
  579			return 0;
  580
  581		msleep(10);
  582	}
  583
  584	rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
  585	return -EACCES;
  586}
  587EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
  588
  589void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
  590{
  591	u32 reg;
  592
  593	reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
  594	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
  595	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
  596	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
  597	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
  598	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
  599	rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
  600}
  601EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
  602
  603void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
  604			       unsigned short *txwi_size,
  605			       unsigned short *rxwi_size)
  606{
  607	switch (rt2x00dev->chip.rt) {
  608	case RT3593:
  609	case RT3883:
  610		*txwi_size = TXWI_DESC_SIZE_4WORDS;
  611		*rxwi_size = RXWI_DESC_SIZE_5WORDS;
  612		break;
  613
  614	case RT5592:
  615	case RT6352:
  616		*txwi_size = TXWI_DESC_SIZE_5WORDS;
  617		*rxwi_size = RXWI_DESC_SIZE_6WORDS;
  618		break;
  619
  620	default:
  621		*txwi_size = TXWI_DESC_SIZE_4WORDS;
  622		*rxwi_size = RXWI_DESC_SIZE_4WORDS;
  623		break;
  624	}
  625}
  626EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
  627
  628static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
  629{
  630	u16 fw_crc;
  631	u16 crc;
  632
  633	/*
  634	 * The last 2 bytes in the firmware array are the crc checksum itself,
  635	 * this means that we should never pass those 2 bytes to the crc
  636	 * algorithm.
  637	 */
  638	fw_crc = (data[len - 2] << 8 | data[len - 1]);
  639
  640	/*
  641	 * Use the crc ccitt algorithm.
  642	 * This will return the same value as the legacy driver which
  643	 * used bit ordering reversion on both the firmware bytes
  644	 * before input input as well as on the final output.
  645	 * Obviously using crc ccitt directly is much more efficient.
  646	 */
  647	crc = crc_ccitt(~0, data, len - 2);
  648
  649	/*
  650	 * There is a small difference between the crc-itu-t + bitrev and
  651	 * the crc-ccitt crc calculation. In the latter method the 2 bytes
  652	 * will be swapped, use swab16 to convert the crc to the correct
  653	 * value.
  654	 */
  655	crc = swab16(crc);
  656
  657	return fw_crc == crc;
  658}
  659
  660int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
  661			  const u8 *data, const size_t len)
  662{
  663	size_t offset = 0;
  664	size_t fw_len;
  665	bool multiple;
  666
  667	/*
  668	 * PCI(e) & SOC devices require firmware with a length
  669	 * of 8kb. USB devices require firmware files with a length
  670	 * of 4kb. Certain USB chipsets however require different firmware,
  671	 * which Ralink only provides attached to the original firmware
  672	 * file. Thus for USB devices, firmware files have a length
  673	 * which is a multiple of 4kb. The firmware for rt3290 chip also
  674	 * have a length which is a multiple of 4kb.
  675	 */
  676	if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
  677		fw_len = 4096;
  678	else
  679		fw_len = 8192;
  680
  681	multiple = true;
  682	/*
  683	 * Validate the firmware length
  684	 */
  685	if (len != fw_len && (!multiple || (len % fw_len) != 0))
  686		return FW_BAD_LENGTH;
  687
  688	/*
  689	 * Check if the chipset requires one of the upper parts
  690	 * of the firmware.
  691	 */
  692	if (rt2x00_is_usb(rt2x00dev) &&
  693	    !rt2x00_rt(rt2x00dev, RT2860) &&
  694	    !rt2x00_rt(rt2x00dev, RT2872) &&
  695	    !rt2x00_rt(rt2x00dev, RT3070) &&
  696	    ((len / fw_len) == 1))
  697		return FW_BAD_VERSION;
  698
  699	/*
  700	 * 8kb firmware files must be checked as if it were
  701	 * 2 separate firmware files.
  702	 */
  703	while (offset < len) {
  704		if (!rt2800_check_firmware_crc(data + offset, fw_len))
  705			return FW_BAD_CRC;
  706
  707		offset += fw_len;
  708	}
  709
  710	return FW_OK;
  711}
  712EXPORT_SYMBOL_GPL(rt2800_check_firmware);
  713
  714int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
  715			 const u8 *data, const size_t len)
  716{
  717	unsigned int i;
  718	u32 reg;
  719	int retval;
  720
  721	if (rt2x00_rt(rt2x00dev, RT3290)) {
  722		retval = rt2800_enable_wlan_rt3290(rt2x00dev);
  723		if (retval)
  724			return -EBUSY;
  725	}
  726
  727	/*
  728	 * If driver doesn't wake up firmware here,
  729	 * rt2800_load_firmware will hang forever when interface is up again.
  730	 */
  731	rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
  732
  733	/*
  734	 * Wait for stable hardware.
  735	 */
  736	if (rt2800_wait_csr_ready(rt2x00dev))
  737		return -EBUSY;
  738
  739	if (rt2x00_is_pci(rt2x00dev)) {
  740		if (rt2x00_rt(rt2x00dev, RT3290) ||
  741		    rt2x00_rt(rt2x00dev, RT3572) ||
  742		    rt2x00_rt(rt2x00dev, RT5390) ||
  743		    rt2x00_rt(rt2x00dev, RT5392)) {
  744			reg = rt2800_register_read(rt2x00dev, AUX_CTRL);
  745			rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
  746			rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
  747			rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
  748		}
  749		rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
  750	}
  751
  752	rt2800_disable_wpdma(rt2x00dev);
  753
  754	/*
  755	 * Write firmware to the device.
  756	 */
  757	rt2800_drv_write_firmware(rt2x00dev, data, len);
  758
  759	/*
  760	 * Wait for device to stabilize.
  761	 */
  762	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  763		reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL);
  764		if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
  765			break;
  766		msleep(1);
  767	}
  768
  769	if (i == REGISTER_BUSY_COUNT) {
  770		rt2x00_err(rt2x00dev, "PBF system register not ready\n");
  771		return -EBUSY;
  772	}
  773
  774	/*
  775	 * Disable DMA, will be reenabled later when enabling
  776	 * the radio.
  777	 */
  778	rt2800_disable_wpdma(rt2x00dev);
  779
  780	/*
  781	 * Initialize firmware.
  782	 */
  783	rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
  784	rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
  785	if (rt2x00_is_usb(rt2x00dev)) {
  786		rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
  787		rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
  788	}
  789	msleep(1);
  790
  791	return 0;
  792}
  793EXPORT_SYMBOL_GPL(rt2800_load_firmware);
  794
  795void rt2800_write_tx_data(struct queue_entry *entry,
  796			  struct txentry_desc *txdesc)
  797{
  798	__le32 *txwi = rt2800_drv_get_txwi(entry);
  799	u32 word;
  800	int i;
  801
  802	/*
  803	 * Initialize TX Info descriptor
  804	 */
  805	word = rt2x00_desc_read(txwi, 0);
  806	rt2x00_set_field32(&word, TXWI_W0_FRAG,
  807			   test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
  808	rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
  809			   test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
  810	rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
  811	rt2x00_set_field32(&word, TXWI_W0_TS,
  812			   test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
  813	rt2x00_set_field32(&word, TXWI_W0_AMPDU,
  814			   test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
  815	rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
  816			   txdesc->u.ht.mpdu_density);
  817	rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
  818	rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
  819	rt2x00_set_field32(&word, TXWI_W0_BW,
  820			   test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
  821	rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
  822			   test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
  823	rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
  824	rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
  825	rt2x00_desc_write(txwi, 0, word);
  826
  827	word = rt2x00_desc_read(txwi, 1);
  828	rt2x00_set_field32(&word, TXWI_W1_ACK,
  829			   test_bit(ENTRY_TXD_ACK, &txdesc->flags));
  830	rt2x00_set_field32(&word, TXWI_W1_NSEQ,
  831			   test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
  832	rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
  833	rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
  834			   test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
  835			   txdesc->key_idx : txdesc->u.ht.wcid);
  836	rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
  837			   txdesc->length);
  838	rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
  839	rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
  840	rt2x00_desc_write(txwi, 1, word);
  841
  842	/*
  843	 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
  844	 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
  845	 * When TXD_W3_WIV is set to 1 it will use the IV data
  846	 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
  847	 * crypto entry in the registers should be used to encrypt the frame.
  848	 *
  849	 * Nulify all remaining words as well, we don't know how to program them.
  850	 */
  851	for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
  852		_rt2x00_desc_write(txwi, i, 0);
  853}
  854EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
  855
  856static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
  857{
  858	s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
  859	s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
  860	s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
  861	s8 base_val = rt2x00_rt(rt2x00dev, RT6352) ? -2 : -12;
  862	u16 eeprom;
  863	u8 offset0;
  864	u8 offset1;
  865	u8 offset2;
  866
  867	if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
  868		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
  869		offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
  870		offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
  871		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
  872		offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
  873	} else {
  874		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
  875		offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
  876		offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
  877		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
  878		offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
  879	}
  880
  881	/*
  882	 * Convert the value from the descriptor into the RSSI value
  883	 * If the value in the descriptor is 0, it is considered invalid
  884	 * and the default (extremely low) rssi value is assumed
  885	 */
  886	rssi0 = (rssi0) ? (base_val - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
  887	rssi1 = (rssi1) ? (base_val - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
  888	rssi2 = (rssi2) ? (base_val - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
  889
  890	/*
  891	 * mac80211 only accepts a single RSSI value. Calculating the
  892	 * average doesn't deliver a fair answer either since -60:-60 would
  893	 * be considered equally good as -50:-70 while the second is the one
  894	 * which gives less energy...
  895	 */
  896	rssi0 = max(rssi0, rssi1);
  897	return (int)max(rssi0, rssi2);
  898}
  899
  900void rt2800_process_rxwi(struct queue_entry *entry,
  901			 struct rxdone_entry_desc *rxdesc)
  902{
  903	__le32 *rxwi = (__le32 *) entry->skb->data;
  904	u32 word;
  905
  906	word = rt2x00_desc_read(rxwi, 0);
  907
  908	rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
  909	rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
  910
  911	word = rt2x00_desc_read(rxwi, 1);
  912
  913	if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
  914		rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI;
  915
  916	if (rt2x00_get_field32(word, RXWI_W1_BW))
  917		rxdesc->bw = RATE_INFO_BW_40;
  918
  919	/*
  920	 * Detect RX rate, always use MCS as signal type.
  921	 */
  922	rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
  923	rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
  924	rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
  925
  926	/*
  927	 * Mask of 0x8 bit to remove the short preamble flag.
  928	 */
  929	if (rxdesc->rate_mode == RATE_MODE_CCK)
  930		rxdesc->signal &= ~0x8;
  931
  932	word = rt2x00_desc_read(rxwi, 2);
  933
  934	/*
  935	 * Convert descriptor AGC value to RSSI value.
  936	 */
  937	rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
  938	/*
  939	 * Remove RXWI descriptor from start of the buffer.
  940	 */
  941	skb_pull(entry->skb, entry->queue->winfo_size);
  942}
  943EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
  944
  945static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc,
  946				    u32 status, enum nl80211_band band)
  947{
  948	u8 flags = 0;
  949	u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
  950
  951	switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) {
  952	case RATE_MODE_HT_GREENFIELD:
  953		flags |= IEEE80211_TX_RC_GREEN_FIELD;
  954		fallthrough;
  955	case RATE_MODE_HT_MIX:
  956		flags |= IEEE80211_TX_RC_MCS;
  957		break;
  958	case RATE_MODE_OFDM:
  959		if (band == NL80211_BAND_2GHZ)
  960			idx += 4;
  961		break;
  962	case RATE_MODE_CCK:
  963		if (idx >= 8)
  964			idx -= 8;
  965		break;
  966	}
  967
  968	if (rt2x00_get_field32(status, TX_STA_FIFO_BW))
  969		flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
  970
  971	if (rt2x00_get_field32(status, TX_STA_FIFO_SGI))
  972		flags |= IEEE80211_TX_RC_SHORT_GI;
  973
  974	skbdesc->tx_rate_idx = idx;
  975	skbdesc->tx_rate_flags = flags;
  976}
  977
  978static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
  979{
  980	__le32 *txwi;
  981	u32 word;
  982	int wcid, ack, pid;
  983	int tx_wcid, tx_ack, tx_pid, is_agg;
  984
  985	/*
  986	 * This frames has returned with an IO error,
  987	 * so the status report is not intended for this
  988	 * frame.
  989	 */
  990	if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags))
  991		return false;
  992
  993	wcid	= rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
  994	ack	= rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
  995	pid	= rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
  996	is_agg	= rt2x00_get_field32(reg, TX_STA_FIFO_TX_AGGRE);
  997
  998	/*
  999	 * Validate if this TX status report is intended for
 1000	 * this entry by comparing the WCID/ACK/PID fields.
 1001	 */
 1002	txwi = rt2800_drv_get_txwi(entry);
 1003
 1004	word = rt2x00_desc_read(txwi, 1);
 1005	tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
 1006	tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
 1007	tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
 1008
 1009	if (wcid != tx_wcid || ack != tx_ack || (!is_agg && pid != tx_pid)) {
 1010		rt2x00_dbg(entry->queue->rt2x00dev,
 1011			   "TX status report missed for queue %d entry %d\n",
 1012			   entry->queue->qid, entry->entry_idx);
 1013		return false;
 1014	}
 1015
 1016	return true;
 1017}
 1018
 1019void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi,
 1020			 bool match)
 1021{
 1022	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 1023	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 1024	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 1025	struct txdone_entry_desc txdesc;
 1026	u32 word;
 1027	u16 mcs, real_mcs;
 1028	int aggr, ampdu, wcid, ack_req;
 1029
 1030	/*
 1031	 * Obtain the status about this packet.
 1032	 */
 1033	txdesc.flags = 0;
 1034	word = rt2x00_desc_read(txwi, 0);
 1035
 1036	mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 1037	ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 1038
 1039	real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 1040	aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 1041	wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
 1042	ack_req	= rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED);
 1043
 1044	/*
 1045	 * If a frame was meant to be sent as a single non-aggregated MPDU
 1046	 * but ended up in an aggregate the used tx rate doesn't correlate
 1047	 * with the one specified in the TXWI as the whole aggregate is sent
 1048	 * with the same rate.
 1049	 *
 1050	 * For example: two frames are sent to rt2x00, the first one sets
 1051	 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 1052	 * and requests MCS15. If the hw aggregates both frames into one
 1053	 * AMDPU the tx status for both frames will contain MCS7 although
 1054	 * the frame was sent successfully.
 1055	 *
 1056	 * Hence, replace the requested rate with the real tx rate to not
 1057	 * confuse the rate control algortihm by providing clearly wrong
 1058	 * data.
 1059	 *
 1060	 * FIXME: if we do not find matching entry, we tell that frame was
 1061	 * posted without any retries. We need to find a way to fix that
 1062	 * and provide retry count.
 1063	 */
 1064	if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) {
 1065		rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band);
 1066		mcs = real_mcs;
 1067	}
 1068
 1069	if (aggr == 1 || ampdu == 1)
 1070		__set_bit(TXDONE_AMPDU, &txdesc.flags);
 1071
 1072	if (!ack_req)
 1073		__set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags);
 1074
 1075	/*
 1076	 * Ralink has a retry mechanism using a global fallback
 1077	 * table. We setup this fallback table to try the immediate
 1078	 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 1079	 * always contains the MCS used for the last transmission, be
 1080	 * it successful or not.
 1081	 */
 1082	if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 1083		/*
 1084		 * Transmission succeeded. The number of retries is
 1085		 * mcs - real_mcs
 1086		 */
 1087		__set_bit(TXDONE_SUCCESS, &txdesc.flags);
 1088		txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 1089	} else {
 1090		/*
 1091		 * Transmission failed. The number of retries is
 1092		 * always 7 in this case (for a total number of 8
 1093		 * frames sent).
 1094		 */
 1095		__set_bit(TXDONE_FAILURE, &txdesc.flags);
 1096		txdesc.retry = rt2x00dev->long_retry;
 1097	}
 1098
 1099	/*
 1100	 * the frame was retried at least once
 1101	 * -> hw used fallback rates
 1102	 */
 1103	if (txdesc.retry)
 1104		__set_bit(TXDONE_FALLBACK, &txdesc.flags);
 1105
 1106	if (!match) {
 1107		/* RCU assures non-null sta will not be freed by mac80211. */
 1108		rcu_read_lock();
 1109		if (likely(wcid >= WCID_START && wcid <= WCID_END))
 1110			skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START];
 1111		else
 1112			skbdesc->sta = NULL;
 1113		rt2x00lib_txdone_nomatch(entry, &txdesc);
 1114		rcu_read_unlock();
 1115	} else {
 1116		rt2x00lib_txdone(entry, &txdesc);
 1117	}
 1118}
 1119EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 1120
 1121void rt2800_txdone(struct rt2x00_dev *rt2x00dev, unsigned int quota)
 1122{
 1123	struct data_queue *queue;
 1124	struct queue_entry *entry;
 1125	u32 reg;
 1126	u8 qid;
 1127	bool match;
 1128
 1129	while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, &reg)) {
 1130		/*
 1131		 * TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus qid is
 1132		 * guaranteed to be one of the TX QIDs .
 1133		 */
 1134		qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
 1135		queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
 1136
 1137		if (unlikely(rt2x00queue_empty(queue))) {
 1138			rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n",
 1139				   qid);
 1140			break;
 1141		}
 1142
 1143		entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 1144
 1145		if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
 1146			     !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))) {
 1147			rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n",
 1148				    entry->entry_idx, qid);
 1149			break;
 1150		}
 1151
 1152		match = rt2800_txdone_entry_check(entry, reg);
 1153		rt2800_txdone_entry(entry, reg, rt2800_drv_get_txwi(entry), match);
 1154	}
 1155}
 1156EXPORT_SYMBOL_GPL(rt2800_txdone);
 1157
 1158static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev,
 1159						 struct queue_entry *entry)
 1160{
 1161	bool ret;
 1162	unsigned long tout;
 1163
 1164	if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
 1165		return false;
 1166
 1167	if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags))
 1168		tout = msecs_to_jiffies(50);
 1169	else
 1170		tout = msecs_to_jiffies(2000);
 1171
 1172	ret = time_after(jiffies, entry->last_action + tout);
 1173	if (unlikely(ret))
 1174		rt2x00_dbg(entry->queue->rt2x00dev,
 1175			   "TX status timeout for entry %d in queue %d\n",
 1176			   entry->entry_idx, entry->queue->qid);
 1177	return ret;
 1178}
 1179
 1180bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev)
 1181{
 1182	struct data_queue *queue;
 1183	struct queue_entry *entry;
 1184
 1185	tx_queue_for_each(rt2x00dev, queue) {
 1186		entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 1187		if (rt2800_entry_txstatus_timeout(rt2x00dev, entry))
 1188			return true;
 1189	}
 1190
 1191	return false;
 1192}
 1193EXPORT_SYMBOL_GPL(rt2800_txstatus_timeout);
 1194
 1195/*
 1196 * test if there is an entry in any TX queue for which DMA is done
 1197 * but the TX status has not been returned yet
 1198 */
 1199bool rt2800_txstatus_pending(struct rt2x00_dev *rt2x00dev)
 1200{
 1201	struct data_queue *queue;
 1202
 1203	tx_queue_for_each(rt2x00dev, queue) {
 1204		if (rt2x00queue_get_entry(queue, Q_INDEX_DMA_DONE) !=
 1205		    rt2x00queue_get_entry(queue, Q_INDEX_DONE))
 1206			return true;
 1207	}
 1208	return false;
 1209}
 1210EXPORT_SYMBOL_GPL(rt2800_txstatus_pending);
 1211
 1212void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev)
 1213{
 1214	struct data_queue *queue;
 1215	struct queue_entry *entry;
 1216
 1217	/*
 1218	 * Process any trailing TX status reports for IO failures,
 1219	 * we loop until we find the first non-IO error entry. This
 1220	 * can either be a frame which is free, is being uploaded,
 1221	 * or has completed the upload but didn't have an entry
 1222	 * in the TX_STAT_FIFO register yet.
 1223	 */
 1224	tx_queue_for_each(rt2x00dev, queue) {
 1225		while (!rt2x00queue_empty(queue)) {
 1226			entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 1227
 1228			if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
 1229			    !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
 1230				break;
 1231
 1232			if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) ||
 1233			    rt2800_entry_txstatus_timeout(rt2x00dev, entry))
 1234				rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
 1235			else
 1236				break;
 1237		}
 1238	}
 1239}
 1240EXPORT_SYMBOL_GPL(rt2800_txdone_nostatus);
 1241
 1242static bool rt2800_check_hung(struct data_queue *queue)
 1243{
 1244	unsigned int cur_idx = rt2800_drv_get_dma_done(queue);
 1245
 1246	if (queue->wd_idx != cur_idx) {
 1247		queue->wd_idx = cur_idx;
 1248		queue->wd_count = 0;
 1249	} else
 1250		queue->wd_count++;
 1251
 1252	return queue->wd_count > 16;
 1253}
 1254
 1255static void rt2800_update_survey(struct rt2x00_dev *rt2x00dev)
 1256{
 1257	struct ieee80211_channel *chan = rt2x00dev->hw->conf.chandef.chan;
 1258	struct rt2x00_chan_survey *chan_survey =
 1259		   &rt2x00dev->chan_survey[chan->hw_value];
 1260
 1261	chan_survey->time_idle += rt2800_register_read(rt2x00dev, CH_IDLE_STA);
 1262	chan_survey->time_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA);
 1263	chan_survey->time_ext_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
 1264}
 1265
 1266static bool rt2800_watchdog_hung(struct rt2x00_dev *rt2x00dev)
 1267{
 1268	struct data_queue *queue;
 1269	bool hung_tx = false;
 1270	bool hung_rx = false;
 1271
 1272	rt2800_update_survey(rt2x00dev);
 1273
 1274	queue_for_each(rt2x00dev, queue) {
 1275		switch (queue->qid) {
 1276		case QID_AC_VO:
 1277		case QID_AC_VI:
 1278		case QID_AC_BE:
 1279		case QID_AC_BK:
 1280		case QID_MGMT:
 1281			if (rt2x00queue_empty(queue))
 1282				continue;
 1283			hung_tx = hung_tx || rt2800_check_hung(queue);
 1284			break;
 1285		case QID_RX:
 1286			/* For station mode we should reactive at least
 1287			 * beacons. TODO: need to find good way detect
 1288			 * RX hung for AP mode.
 1289			 */
 1290			if (rt2x00dev->intf_sta_count == 0)
 1291				continue;
 1292			hung_rx = hung_rx || rt2800_check_hung(queue);
 1293			break;
 1294		default:
 1295			break;
 1296		}
 1297	}
 1298
 1299	if (!hung_tx && !hung_rx)
 1300		return false;
 1301
 1302	if (hung_tx)
 1303		rt2x00_warn(rt2x00dev, "Watchdog TX hung detected\n");
 1304
 1305	if (hung_rx)
 1306		rt2x00_warn(rt2x00dev, "Watchdog RX hung detected\n");
 1307
 1308	queue_for_each(rt2x00dev, queue)
 1309		queue->wd_count = 0;
 1310
 1311	return true;
 1312}
 1313
 1314static bool rt2800_watchdog_dma_busy(struct rt2x00_dev *rt2x00dev)
 1315{
 1316	bool busy_rx, busy_tx;
 1317	u32 reg_cfg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
 1318	u32 reg_int = rt2800_register_read(rt2x00dev, INT_SOURCE_CSR);
 1319
 1320	if (rt2x00_get_field32(reg_cfg, WPDMA_GLO_CFG_RX_DMA_BUSY) &&
 1321	    rt2x00_get_field32(reg_int, INT_SOURCE_CSR_RX_COHERENT))
 1322		rt2x00dev->rxdma_busy++;
 1323	else
 1324		rt2x00dev->rxdma_busy = 0;
 1325
 1326	if (rt2x00_get_field32(reg_cfg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 1327	    rt2x00_get_field32(reg_int, INT_SOURCE_CSR_TX_COHERENT))
 1328		rt2x00dev->txdma_busy++;
 1329	else
 1330		rt2x00dev->txdma_busy = 0;
 1331
 1332	busy_rx = rt2x00dev->rxdma_busy > 30;
 1333	busy_tx = rt2x00dev->txdma_busy > 30;
 1334
 1335	if (!busy_rx && !busy_tx)
 1336		return false;
 1337
 1338	if (busy_rx)
 1339		rt2x00_warn(rt2x00dev, "Watchdog RX DMA busy detected\n");
 1340
 1341	if (busy_tx)
 1342		rt2x00_warn(rt2x00dev, "Watchdog TX DMA busy detected\n");
 1343
 1344	rt2x00dev->rxdma_busy = 0;
 1345	rt2x00dev->txdma_busy = 0;
 1346
 1347	return true;
 1348}
 1349
 1350void rt2800_watchdog(struct rt2x00_dev *rt2x00dev)
 1351{
 1352	bool reset = false;
 1353
 1354	if (test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags))
 1355		return;
 1356
 1357	if (rt2x00dev->link.watchdog & RT2800_WATCHDOG_DMA_BUSY)
 1358		reset = rt2800_watchdog_dma_busy(rt2x00dev);
 1359
 1360	if (rt2x00dev->link.watchdog & RT2800_WATCHDOG_HANG)
 1361		reset = rt2800_watchdog_hung(rt2x00dev) || reset;
 1362
 1363	if (reset)
 1364		ieee80211_restart_hw(rt2x00dev->hw);
 1365}
 1366EXPORT_SYMBOL_GPL(rt2800_watchdog);
 1367
 1368static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
 1369					  unsigned int index)
 1370{
 1371	return HW_BEACON_BASE(index);
 1372}
 1373
 1374static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
 1375					  unsigned int index)
 1376{
 1377	return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
 1378}
 1379
 1380static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
 1381{
 1382	struct data_queue *queue = rt2x00dev->bcn;
 1383	struct queue_entry *entry;
 1384	int i, bcn_num = 0;
 1385	u64 off, reg = 0;
 1386	u32 bssid_dw1;
 1387
 1388	/*
 1389	 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
 1390	 */
 1391	for (i = 0; i < queue->limit; i++) {
 1392		entry = &queue->entries[i];
 1393		if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
 1394			continue;
 1395		off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
 1396		reg |= off << (8 * bcn_num);
 1397		bcn_num++;
 1398	}
 1399
 1400	rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
 1401	rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
 1402
 1403	/*
 1404	 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
 1405	 */
 1406	bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1);
 1407	rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
 1408			   bcn_num > 0 ? bcn_num - 1 : 0);
 1409	rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
 1410}
 1411
 1412void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 1413{
 1414	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 1415	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 1416	unsigned int beacon_base;
 1417	unsigned int padding_len;
 1418	u32 orig_reg, reg;
 1419	const int txwi_desc_size = entry->queue->winfo_size;
 1420
 1421	/*
 1422	 * Disable beaconing while we are reloading the beacon data,
 1423	 * otherwise we might be sending out invalid data.
 1424	 */
 1425	reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
 1426	orig_reg = reg;
 1427	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 1428	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 1429
 1430	/*
 1431	 * Add space for the TXWI in front of the skb.
 1432	 */
 1433	memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
 1434
 1435	/*
 1436	 * Register descriptor details in skb frame descriptor.
 1437	 */
 1438	skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 1439	skbdesc->desc = entry->skb->data;
 1440	skbdesc->desc_len = txwi_desc_size;
 1441
 1442	/*
 1443	 * Add the TXWI for the beacon to the skb.
 1444	 */
 1445	rt2800_write_tx_data(entry, txdesc);
 1446
 1447	/*
 1448	 * Dump beacon to userspace through debugfs.
 1449	 */
 1450	rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
 1451
 1452	/*
 1453	 * Write entire beacon with TXWI and padding to register.
 1454	 */
 1455	padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 1456	if (padding_len && skb_pad(entry->skb, padding_len)) {
 1457		rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
 1458		/* skb freed by skb_pad() on failure */
 1459		entry->skb = NULL;
 1460		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
 1461		return;
 1462	}
 1463
 1464	beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
 1465
 1466	rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
 1467				   entry->skb->len + padding_len);
 1468	__set_bit(ENTRY_BCN_ENABLED, &entry->flags);
 1469
 1470	/*
 1471	 * Change global beacons settings.
 1472	 */
 1473	rt2800_update_beacons_setup(rt2x00dev);
 1474
 1475	/*
 1476	 * Restore beaconing state.
 1477	 */
 1478	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
 1479
 1480	/*
 1481	 * Clean up beacon skb.
 1482	 */
 1483	dev_kfree_skb_any(entry->skb);
 1484	entry->skb = NULL;
 1485}
 1486EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 1487
 1488static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
 1489						unsigned int index)
 1490{
 1491	int i;
 1492	const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
 1493	unsigned int beacon_base;
 1494
 1495	beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
 1496
 1497	/*
 1498	 * For the Beacon base registers we only need to clear
 1499	 * the whole TXWI which (when set to 0) will invalidate
 1500	 * the entire beacon.
 1501	 */
 1502	for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
 1503		rt2800_register_write(rt2x00dev, beacon_base + i, 0);
 1504}
 1505
 1506void rt2800_clear_beacon(struct queue_entry *entry)
 1507{
 1508	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 1509	u32 orig_reg, reg;
 1510
 1511	/*
 1512	 * Disable beaconing while we are reloading the beacon data,
 1513	 * otherwise we might be sending out invalid data.
 1514	 */
 1515	orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
 1516	reg = orig_reg;
 1517	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 1518	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 1519
 1520	/*
 1521	 * Clear beacon.
 1522	 */
 1523	rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
 1524	__clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
 1525
 1526	/*
 1527	 * Change global beacons settings.
 1528	 */
 1529	rt2800_update_beacons_setup(rt2x00dev);
 1530	/*
 1531	 * Restore beaconing state.
 1532	 */
 1533	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
 1534}
 1535EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
 1536
 1537#ifdef CONFIG_RT2X00_LIB_DEBUGFS
 1538const struct rt2x00debug rt2800_rt2x00debug = {
 1539	.owner	= THIS_MODULE,
 1540	.csr	= {
 1541		.read		= rt2800_register_read,
 1542		.write		= rt2800_register_write,
 1543		.flags		= RT2X00DEBUGFS_OFFSET,
 1544		.word_base	= CSR_REG_BASE,
 1545		.word_size	= sizeof(u32),
 1546		.word_count	= CSR_REG_SIZE / sizeof(u32),
 1547	},
 1548	.eeprom	= {
 1549		/* NOTE: The local EEPROM access functions can't
 1550		 * be used here, use the generic versions instead.
 1551		 */
 1552		.read		= rt2x00_eeprom_read,
 1553		.write		= rt2x00_eeprom_write,
 1554		.word_base	= EEPROM_BASE,
 1555		.word_size	= sizeof(u16),
 1556		.word_count	= EEPROM_SIZE / sizeof(u16),
 1557	},
 1558	.bbp	= {
 1559		.read		= rt2800_bbp_read,
 1560		.write		= rt2800_bbp_write,
 1561		.word_base	= BBP_BASE,
 1562		.word_size	= sizeof(u8),
 1563		.word_count	= BBP_SIZE / sizeof(u8),
 1564	},
 1565	.rf	= {
 1566		.read		= rt2x00_rf_read,
 1567		.write		= rt2800_rf_write,
 1568		.word_base	= RF_BASE,
 1569		.word_size	= sizeof(u32),
 1570		.word_count	= RF_SIZE / sizeof(u32),
 1571	},
 1572	.rfcsr	= {
 1573		.read		= rt2800_rfcsr_read,
 1574		.write		= rt2800_rfcsr_write,
 1575		.word_base	= RFCSR_BASE,
 1576		.word_size	= sizeof(u8),
 1577		.word_count	= RFCSR_SIZE / sizeof(u8),
 1578	},
 1579};
 1580EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 1581#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 1582
 1583int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 1584{
 1585	u32 reg;
 1586
 1587	if (rt2x00_rt(rt2x00dev, RT3290)) {
 1588		reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
 1589		return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
 1590	} else {
 1591		reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
 1592		return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
 1593	}
 1594}
 1595EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 1596
 1597#ifdef CONFIG_RT2X00_LIB_LEDS
 1598static void rt2800_brightness_set(struct led_classdev *led_cdev,
 1599				  enum led_brightness brightness)
 1600{
 1601	struct rt2x00_led *led =
 1602	    container_of(led_cdev, struct rt2x00_led, led_dev);
 1603	unsigned int enabled = brightness != LED_OFF;
 1604	unsigned int bg_mode =
 1605	    (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
 1606	unsigned int polarity =
 1607		rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 1608				   EEPROM_FREQ_LED_POLARITY);
 1609	unsigned int ledmode =
 1610		rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 1611				   EEPROM_FREQ_LED_MODE);
 1612	u32 reg;
 1613
 1614	/* Check for SoC (SOC devices don't support MCU requests) */
 1615	if (rt2x00_is_soc(led->rt2x00dev)) {
 1616		reg = rt2800_register_read(led->rt2x00dev, LED_CFG);
 1617
 1618		/* Set LED Polarity */
 1619		rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
 1620
 1621		/* Set LED Mode */
 1622		if (led->type == LED_TYPE_RADIO) {
 1623			rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
 1624					   enabled ? 3 : 0);
 1625		} else if (led->type == LED_TYPE_ASSOC) {
 1626			rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
 1627					   enabled ? 3 : 0);
 1628		} else if (led->type == LED_TYPE_QUALITY) {
 1629			rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
 1630					   enabled ? 3 : 0);
 1631		}
 1632
 1633		rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 1634
 1635	} else {
 1636		if (led->type == LED_TYPE_RADIO) {
 1637			rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 1638					      enabled ? 0x20 : 0);
 1639		} else if (led->type == LED_TYPE_ASSOC) {
 1640			rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 1641					      enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 1642		} else if (led->type == LED_TYPE_QUALITY) {
 1643			/*
 1644			 * The brightness is divided into 6 levels (0 - 5),
 1645			 * The specs tell us the following levels:
 1646			 *	0, 1 ,3, 7, 15, 31
 1647			 * to determine the level in a simple way we can simply
 1648			 * work with bitshifting:
 1649			 *	(1 << level) - 1
 1650			 */
 1651			rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 1652					      (1 << brightness / (LED_FULL / 6)) - 1,
 1653					      polarity);
 1654		}
 1655	}
 1656}
 1657
 1658static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 1659		     struct rt2x00_led *led, enum led_type type)
 1660{
 1661	led->rt2x00dev = rt2x00dev;
 1662	led->type = type;
 1663	led->led_dev.brightness_set = rt2800_brightness_set;
 1664	led->flags = LED_INITIALIZED;
 1665}
 1666#endif /* CONFIG_RT2X00_LIB_LEDS */
 1667
 1668/*
 1669 * Configuration handlers.
 1670 */
 1671static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
 1672			       const u8 *address,
 1673			       int wcid)
 1674{
 1675	struct mac_wcid_entry wcid_entry;
 1676	u32 offset;
 1677
 1678	offset = MAC_WCID_ENTRY(wcid);
 1679
 1680	memset(&wcid_entry, 0xff, sizeof(wcid_entry));
 1681	if (address)
 1682		memcpy(wcid_entry.mac, address, ETH_ALEN);
 1683
 1684	rt2800_register_multiwrite(rt2x00dev, offset,
 1685				      &wcid_entry, sizeof(wcid_entry));
 1686}
 1687
 1688static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
 1689{
 1690	u32 offset;
 1691	offset = MAC_WCID_ATTR_ENTRY(wcid);
 1692	rt2800_register_write(rt2x00dev, offset, 0);
 1693}
 1694
 1695static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
 1696					   int wcid, u32 bssidx)
 1697{
 1698	u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
 1699	u32 reg;
 1700
 1701	/*
 1702	 * The BSS Idx numbers is split in a main value of 3 bits,
 1703	 * and a extended field for adding one additional bit to the value.
 1704	 */
 1705	reg = rt2800_register_read(rt2x00dev, offset);
 1706	rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
 1707	rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
 1708			   (bssidx & 0x8) >> 3);
 1709	rt2800_register_write(rt2x00dev, offset, reg);
 1710}
 1711
 1712static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
 1713					   struct rt2x00lib_crypto *crypto,
 1714					   struct ieee80211_key_conf *key)
 1715{
 1716	struct mac_iveiv_entry iveiv_entry;
 1717	u32 offset;
 1718	u32 reg;
 1719
 1720	offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 1721
 1722	if (crypto->cmd == SET_KEY) {
 1723		reg = rt2800_register_read(rt2x00dev, offset);
 1724		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 1725				   !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 1726		/*
 1727		 * Both the cipher as the BSS Idx numbers are split in a main
 1728		 * value of 3 bits, and a extended field for adding one additional
 1729		 * bit to the value.
 1730		 */
 1731		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 1732				   (crypto->cipher & 0x7));
 1733		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
 1734				   (crypto->cipher & 0x8) >> 3);
 1735		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 1736		rt2800_register_write(rt2x00dev, offset, reg);
 1737	} else {
 1738		/* Delete the cipher without touching the bssidx */
 1739		reg = rt2800_register_read(rt2x00dev, offset);
 1740		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
 1741		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
 1742		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
 1743		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
 1744		rt2800_register_write(rt2x00dev, offset, reg);
 1745	}
 1746
 1747	if (test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags))
 1748		return;
 1749
 1750	offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 1751
 1752	memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 1753	if ((crypto->cipher == CIPHER_TKIP) ||
 1754	    (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 1755	    (crypto->cipher == CIPHER_AES))
 1756		iveiv_entry.iv[3] |= 0x20;
 1757	iveiv_entry.iv[3] |= key->keyidx << 6;
 1758	rt2800_register_multiwrite(rt2x00dev, offset,
 1759				   &iveiv_entry, sizeof(iveiv_entry));
 1760}
 1761
 1762int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
 1763			     struct rt2x00lib_crypto *crypto,
 1764			     struct ieee80211_key_conf *key)
 1765{
 1766	struct hw_key_entry key_entry;
 1767	struct rt2x00_field32 field;
 1768	u32 offset;
 1769	u32 reg;
 1770
 1771	if (crypto->cmd == SET_KEY) {
 1772		key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 1773
 1774		memcpy(key_entry.key, crypto->key,
 1775		       sizeof(key_entry.key));
 1776		memcpy(key_entry.tx_mic, crypto->tx_mic,
 1777		       sizeof(key_entry.tx_mic));
 1778		memcpy(key_entry.rx_mic, crypto->rx_mic,
 1779		       sizeof(key_entry.rx_mic));
 1780
 1781		offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 1782		rt2800_register_multiwrite(rt2x00dev, offset,
 1783					      &key_entry, sizeof(key_entry));
 1784	}
 1785
 1786	/*
 1787	 * The cipher types are stored over multiple registers
 1788	 * starting with SHARED_KEY_MODE_BASE each word will have
 1789	 * 32 bits and contains the cipher types for 2 bssidx each.
 1790	 * Using the correct defines correctly will cause overhead,
 1791	 * so just calculate the correct offset.
 1792	 */
 1793	field.bit_offset = 4 * (key->hw_key_idx % 8);
 1794	field.bit_mask = 0x7 << field.bit_offset;
 1795
 1796	offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 1797
 1798	reg = rt2800_register_read(rt2x00dev, offset);
 1799	rt2x00_set_field32(&reg, field,
 1800			   (crypto->cmd == SET_KEY) * crypto->cipher);
 1801	rt2800_register_write(rt2x00dev, offset, reg);
 1802
 1803	/*
 1804	 * Update WCID information
 1805	 */
 1806	rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
 1807	rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
 1808				       crypto->bssidx);
 1809	rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
 1810
 1811	return 0;
 1812}
 1813EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
 1814
 1815int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 1816			       struct rt2x00lib_crypto *crypto,
 1817			       struct ieee80211_key_conf *key)
 1818{
 1819	struct hw_key_entry key_entry;
 1820	u32 offset;
 1821
 1822	if (crypto->cmd == SET_KEY) {
 1823		/*
 1824		 * Allow key configuration only for STAs that are
 1825		 * known by the hw.
 1826		 */
 1827		if (crypto->wcid > WCID_END)
 1828			return -ENOSPC;
 1829		key->hw_key_idx = crypto->wcid;
 1830
 1831		memcpy(key_entry.key, crypto->key,
 1832		       sizeof(key_entry.key));
 1833		memcpy(key_entry.tx_mic, crypto->tx_mic,
 1834		       sizeof(key_entry.tx_mic));
 1835		memcpy(key_entry.rx_mic, crypto->rx_mic,
 1836		       sizeof(key_entry.rx_mic));
 1837
 1838		offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 1839		rt2800_register_multiwrite(rt2x00dev, offset,
 1840					      &key_entry, sizeof(key_entry));
 1841	}
 1842
 1843	/*
 1844	 * Update WCID information
 1845	 */
 1846	rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
 1847
 1848	return 0;
 1849}
 1850EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
 1851
 1852static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev)
 1853{
 1854	u8 i, max_psdu;
 1855	u32 reg;
 1856	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 1857
 1858	for (i = 0; i < 3; i++)
 1859		if (drv_data->ampdu_factor_cnt[i] > 0)
 1860			break;
 1861
 1862	max_psdu = min(drv_data->max_psdu, i);
 1863
 1864	reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
 1865	rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, max_psdu);
 1866	rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
 1867}
 1868
 1869int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
 1870		   struct ieee80211_sta *sta)
 1871{
 1872	struct rt2x00_dev *rt2x00dev = hw->priv;
 1873	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 1874	struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
 1875	int wcid;
 1876
 1877	/*
 1878	 * Limit global maximum TX AMPDU length to smallest value of all
 1879	 * connected stations. In AP mode this can be suboptimal, but we
 1880	 * do not have a choice if some connected STA is not capable to
 1881	 * receive the same amount of data like the others.
 1882	 */
 1883	if (sta->deflink.ht_cap.ht_supported) {
 1884		drv_data->ampdu_factor_cnt[sta->deflink.ht_cap.ampdu_factor & 3]++;
 1885		rt2800_set_max_psdu_len(rt2x00dev);
 1886	}
 1887
 1888	/*
 1889	 * Search for the first free WCID entry and return the corresponding
 1890	 * index.
 1891	 */
 1892	wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START;
 1893
 1894	/*
 1895	 * Store selected wcid even if it is invalid so that we can
 1896	 * later decide if the STA is uploaded into the hw.
 1897	 */
 1898	sta_priv->wcid = wcid;
 1899
 1900	/*
 1901	 * No space left in the device, however, we can still communicate
 1902	 * with the STA -> No error.
 1903	 */
 1904	if (wcid > WCID_END)
 1905		return 0;
 1906
 1907	__set_bit(wcid - WCID_START, drv_data->sta_ids);
 1908	drv_data->wcid_to_sta[wcid - WCID_START] = sta;
 1909
 1910	/*
 1911	 * Clean up WCID attributes and write STA address to the device.
 1912	 */
 1913	rt2800_delete_wcid_attr(rt2x00dev, wcid);
 1914	rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
 1915	rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
 1916				       rt2x00lib_get_bssidx(rt2x00dev, vif));
 1917	return 0;
 1918}
 1919EXPORT_SYMBOL_GPL(rt2800_sta_add);
 1920
 1921int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
 1922		      struct ieee80211_sta *sta)
 1923{
 1924	struct rt2x00_dev *rt2x00dev = hw->priv;
 1925	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 1926	struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
 1927	int wcid = sta_priv->wcid;
 1928
 1929	if (sta->deflink.ht_cap.ht_supported) {
 1930		drv_data->ampdu_factor_cnt[sta->deflink.ht_cap.ampdu_factor & 3]--;
 1931		rt2800_set_max_psdu_len(rt2x00dev);
 1932	}
 1933
 1934	if (wcid > WCID_END)
 1935		return 0;
 1936	/*
 1937	 * Remove WCID entry, no need to clean the attributes as they will
 1938	 * get renewed when the WCID is reused.
 1939	 */
 1940	rt2800_config_wcid(rt2x00dev, NULL, wcid);
 1941	drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
 1942	__clear_bit(wcid - WCID_START, drv_data->sta_ids);
 1943
 1944	return 0;
 1945}
 1946EXPORT_SYMBOL_GPL(rt2800_sta_remove);
 1947
 1948void rt2800_pre_reset_hw(struct rt2x00_dev *rt2x00dev)
 1949{
 1950	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 1951	struct data_queue *queue = rt2x00dev->bcn;
 1952	struct queue_entry *entry;
 1953	int i, wcid;
 1954
 1955	for (wcid = WCID_START; wcid < WCID_END; wcid++) {
 1956		drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
 1957		__clear_bit(wcid - WCID_START, drv_data->sta_ids);
 1958	}
 1959
 1960	for (i = 0; i < queue->limit; i++) {
 1961		entry = &queue->entries[i];
 1962		clear_bit(ENTRY_BCN_ASSIGNED, &entry->flags);
 1963	}
 1964}
 1965EXPORT_SYMBOL_GPL(rt2800_pre_reset_hw);
 1966
 1967void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
 1968			  const unsigned int filter_flags)
 1969{
 1970	u32 reg;
 1971
 1972	/*
 1973	 * Start configuration steps.
 1974	 * Note that the version error will always be dropped
 1975	 * and broadcast frames will always be accepted since
 1976	 * there is no filter for it at this time.
 1977	 */
 1978	reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG);
 1979	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 1980			   !(filter_flags & FIF_FCSFAIL));
 1981	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 1982			   !(filter_flags & FIF_PLCPFAIL));
 1983	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 1984			   !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
 1985	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 1986	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 1987	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 1988			   !(filter_flags & FIF_ALLMULTI));
 1989	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 1990	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 1991	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 1992			   !(filter_flags & FIF_CONTROL));
 1993	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 1994			   !(filter_flags & FIF_CONTROL));
 1995	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 1996			   !(filter_flags & FIF_CONTROL));
 1997	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 1998			   !(filter_flags & FIF_CONTROL));
 1999	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 2000			   !(filter_flags & FIF_CONTROL));
 2001	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 2002			   !(filter_flags & FIF_PSPOLL));
 2003	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
 2004	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
 2005			   !(filter_flags & FIF_CONTROL));
 2006	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 2007			   !(filter_flags & FIF_CONTROL));
 2008	rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 2009}
 2010EXPORT_SYMBOL_GPL(rt2800_config_filter);
 2011
 2012void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
 2013			struct rt2x00intf_conf *conf, const unsigned int flags)
 2014{
 2015	u32 reg;
 2016	bool update_bssid = false;
 2017
 2018	if (flags & CONFIG_UPDATE_TYPE) {
 2019		/*
 2020		 * Enable synchronisation.
 2021		 */
 2022		reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
 2023		rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 2024		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 2025
 2026		if (conf->sync == TSF_SYNC_AP_NONE) {
 2027			/*
 2028			 * Tune beacon queue transmit parameters for AP mode
 2029			 */
 2030			reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
 2031			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
 2032			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
 2033			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
 2034			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
 2035			rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
 2036		} else {
 2037			reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
 2038			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
 2039			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
 2040			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
 2041			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
 2042			rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
 2043		}
 2044	}
 2045
 2046	if (flags & CONFIG_UPDATE_MAC) {
 2047		if (flags & CONFIG_UPDATE_TYPE &&
 2048		    conf->sync == TSF_SYNC_AP_NONE) {
 2049			/*
 2050			 * The BSSID register has to be set to our own mac
 2051			 * address in AP mode.
 2052			 */
 2053			memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
 2054			update_bssid = true;
 2055		}
 2056
 2057		if (!is_zero_ether_addr((const u8 *)conf->mac)) {
 2058			reg = le32_to_cpu(conf->mac[1]);
 2059			rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 2060			conf->mac[1] = cpu_to_le32(reg);
 2061		}
 2062
 2063		rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 2064					      conf->mac, sizeof(conf->mac));
 2065	}
 2066
 2067	if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
 2068		if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
 2069			reg = le32_to_cpu(conf->bssid[1]);
 2070			rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
 2071			rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 2072			conf->bssid[1] = cpu_to_le32(reg);
 2073		}
 2074
 2075		rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 2076					      conf->bssid, sizeof(conf->bssid));
 2077	}
 2078}
 2079EXPORT_SYMBOL_GPL(rt2800_config_intf);
 2080
 2081static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
 2082				    struct rt2x00lib_erp *erp)
 2083{
 2084	bool any_sta_nongf = !!(erp->ht_opmode &
 2085				IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
 2086	u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
 2087	u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
 2088	u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
 2089	u32 reg;
 2090
 2091	/* default protection rate for HT20: OFDM 24M */
 2092	mm20_rate = gf20_rate = 0x4004;
 2093
 2094	/* default protection rate for HT40: duplicate OFDM 24M */
 2095	mm40_rate = gf40_rate = 0x4084;
 2096
 2097	switch (protection) {
 2098	case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
 2099		/*
 2100		 * All STAs in this BSS are HT20/40 but there might be
 2101		 * STAs not supporting greenfield mode.
 2102		 * => Disable protection for HT transmissions.
 2103		 */
 2104		mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
 2105
 2106		break;
 2107	case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
 2108		/*
 2109		 * All STAs in this BSS are HT20 or HT20/40 but there
 2110		 * might be STAs not supporting greenfield mode.
 2111		 * => Protect all HT40 transmissions.
 2112		 */
 2113		mm20_mode = gf20_mode = 0;
 2114		mm40_mode = gf40_mode = 1;
 2115
 2116		break;
 2117	case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
 2118		/*
 2119		 * Nonmember protection:
 2120		 * According to 802.11n we _should_ protect all
 2121		 * HT transmissions (but we don't have to).
 2122		 *
 2123		 * But if cts_protection is enabled we _shall_ protect
 2124		 * all HT transmissions using a CCK rate.
 2125		 *
 2126		 * And if any station is non GF we _shall_ protect
 2127		 * GF transmissions.
 2128		 *
 2129		 * We decide to protect everything
 2130		 * -> fall through to mixed mode.
 2131		 */
 2132	case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
 2133		/*
 2134		 * Legacy STAs are present
 2135		 * => Protect all HT transmissions.
 2136		 */
 2137		mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1;
 2138
 2139		/*
 2140		 * If erp protection is needed we have to protect HT
 2141		 * transmissions with CCK 11M long preamble.
 2142		 */
 2143		if (erp->cts_protection) {
 2144			/* don't duplicate RTS/CTS in CCK mode */
 2145			mm20_rate = mm40_rate = 0x0003;
 2146			gf20_rate = gf40_rate = 0x0003;
 2147		}
 2148		break;
 2149	}
 2150
 2151	/* check for STAs not supporting greenfield mode */
 2152	if (any_sta_nongf)
 2153		gf20_mode = gf40_mode = 1;
 2154
 2155	/* Update HT protection config */
 2156	reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
 2157	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
 2158	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
 2159	rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
 2160
 2161	reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
 2162	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
 2163	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
 2164	rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
 2165
 2166	reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
 2167	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
 2168	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
 2169	rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
 2170
 2171	reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
 2172	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
 2173	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
 2174	rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
 2175}
 2176
 2177void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
 2178		       u32 changed)
 2179{
 2180	u32 reg;
 2181
 2182	if (changed & BSS_CHANGED_ERP_PREAMBLE) {
 2183		reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
 2184		rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 2185				   !!erp->short_preamble);
 2186		rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 2187	}
 2188
 2189	if (changed & BSS_CHANGED_ERP_CTS_PROT) {
 2190		reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
 2191		rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 2192				   erp->cts_protection ? 2 : 0);
 2193		rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 2194	}
 2195
 2196	if (changed & BSS_CHANGED_BASIC_RATES) {
 2197		rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 2198				      0xff0 | erp->basic_rates);
 2199		rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 2200	}
 2201
 2202	if (changed & BSS_CHANGED_ERP_SLOT) {
 2203		reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
 2204		rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
 2205				   erp->slot_time);
 2206		rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 2207
 2208		reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
 2209		rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 2210		rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 2211	}
 2212
 2213	if (changed & BSS_CHANGED_BEACON_INT) {
 2214		reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
 2215		rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 2216				   erp->beacon_int * 16);
 2217		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 2218	}
 2219
 2220	if (changed & BSS_CHANGED_HT)
 2221		rt2800_config_ht_opmode(rt2x00dev, erp);
 2222}
 2223EXPORT_SYMBOL_GPL(rt2800_config_erp);
 2224
 2225static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev,
 2226				    const struct rt2x00_field32 mask)
 2227{
 2228	unsigned int i;
 2229	u32 reg;
 2230
 2231	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 2232		reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
 2233		if (!rt2x00_get_field32(reg, mask))
 2234			return 0;
 2235
 2236		udelay(REGISTER_BUSY_DELAY);
 2237	}
 2238
 2239	rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
 2240	return -EACCES;
 2241}
 2242
 2243static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
 2244{
 2245	unsigned int i;
 2246	u8 value;
 2247
 2248	/*
 2249	 * BBP was enabled after firmware was loaded,
 2250	 * but we need to reactivate it now.
 2251	 */
 2252	rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 2253	rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 2254	msleep(1);
 2255
 2256	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 2257		value = rt2800_bbp_read(rt2x00dev, 0);
 2258		if ((value != 0xff) && (value != 0x00))
 2259			return 0;
 2260		udelay(REGISTER_BUSY_DELAY);
 2261	}
 2262
 2263	rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
 2264	return -EACCES;
 2265}
 2266
 2267static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
 2268{
 2269	u32 reg;
 2270	u16 eeprom;
 2271	u8 led_ctrl, led_g_mode, led_r_mode;
 2272
 2273	reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
 2274	if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
 2275		rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
 2276		rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
 2277	} else {
 2278		rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
 2279		rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
 2280	}
 2281	rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
 2282
 2283	reg = rt2800_register_read(rt2x00dev, LED_CFG);
 2284	led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
 2285	led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
 2286	if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
 2287	    led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
 2288		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
 2289		led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
 2290		if (led_ctrl == 0 || led_ctrl > 0x40) {
 2291			rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
 2292			rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
 2293			rt2800_register_write(rt2x00dev, LED_CFG, reg);
 2294		} else {
 2295			rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
 2296					   (led_g_mode << 2) | led_r_mode, 1);
 2297		}
 2298	}
 2299}
 2300
 2301static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
 2302				     enum antenna ant)
 2303{
 2304	u32 reg;
 2305	u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
 2306	u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
 2307
 2308	if (rt2x00_is_pci(rt2x00dev)) {
 2309		reg = rt2800_register_read(rt2x00dev, E2PROM_CSR);
 2310		rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
 2311		rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
 2312	} else if (rt2x00_is_usb(rt2x00dev))
 2313		rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
 2314				   eesk_pin, 0);
 2315
 2316	reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
 2317	rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
 2318	rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
 2319	rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
 2320}
 2321
 2322void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
 2323{
 2324	u8 r1;
 2325	u8 r3;
 2326	u16 eeprom;
 2327
 2328	r1 = rt2800_bbp_read(rt2x00dev, 1);
 2329	r3 = rt2800_bbp_read(rt2x00dev, 3);
 2330
 2331	if (rt2x00_rt(rt2x00dev, RT3572) &&
 2332	    rt2x00_has_cap_bt_coexist(rt2x00dev))
 2333		rt2800_config_3572bt_ant(rt2x00dev);
 2334
 2335	/*
 2336	 * Configure the TX antenna.
 2337	 */
 2338	switch (ant->tx_chain_num) {
 2339	case 1:
 2340		rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 2341		break;
 2342	case 2:
 2343		if (rt2x00_rt(rt2x00dev, RT3572) &&
 2344		    rt2x00_has_cap_bt_coexist(rt2x00dev))
 2345			rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
 2346		else
 2347			rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 2348		break;
 2349	case 3:
 2350		rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 2351		break;
 2352	}
 2353
 2354	/*
 2355	 * Configure the RX antenna.
 2356	 */
 2357	switch (ant->rx_chain_num) {
 2358	case 1:
 2359		if (rt2x00_rt(rt2x00dev, RT3070) ||
 2360		    rt2x00_rt(rt2x00dev, RT3090) ||
 2361		    rt2x00_rt(rt2x00dev, RT3352) ||
 2362		    rt2x00_rt(rt2x00dev, RT3390)) {
 2363			eeprom = rt2800_eeprom_read(rt2x00dev,
 2364						    EEPROM_NIC_CONF1);
 2365			if (rt2x00_get_field16(eeprom,
 2366						EEPROM_NIC_CONF1_ANT_DIVERSITY))
 2367				rt2800_set_ant_diversity(rt2x00dev,
 2368						rt2x00dev->default_ant.rx);
 2369		}
 2370		rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 2371		break;
 2372	case 2:
 2373		if (rt2x00_rt(rt2x00dev, RT3572) &&
 2374		    rt2x00_has_cap_bt_coexist(rt2x00dev)) {
 2375			rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
 2376			rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
 2377				rt2x00dev->curr_band == NL80211_BAND_5GHZ);
 2378			rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
 2379		} else {
 2380			rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 2381		}
 2382		break;
 2383	case 3:
 2384		rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 2385		break;
 2386	}
 2387
 2388	rt2800_bbp_write(rt2x00dev, 3, r3);
 2389	rt2800_bbp_write(rt2x00dev, 1, r1);
 2390
 2391	if (rt2x00_rt(rt2x00dev, RT3593) ||
 2392	    rt2x00_rt(rt2x00dev, RT3883)) {
 2393		if (ant->rx_chain_num == 1)
 2394			rt2800_bbp_write(rt2x00dev, 86, 0x00);
 2395		else
 2396			rt2800_bbp_write(rt2x00dev, 86, 0x46);
 2397	}
 2398}
 2399EXPORT_SYMBOL_GPL(rt2800_config_ant);
 2400
 2401static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 2402				   struct rt2x00lib_conf *libconf)
 2403{
 2404	u16 eeprom;
 2405	short lna_gain;
 2406
 2407	if (libconf->rf.channel <= 14) {
 2408		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
 2409		lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 2410	} else if (libconf->rf.channel <= 64) {
 2411		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
 2412		lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 2413	} else if (libconf->rf.channel <= 128) {
 2414		if (rt2x00_rt(rt2x00dev, RT3593) ||
 2415		    rt2x00_rt(rt2x00dev, RT3883)) {
 2416			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
 2417			lna_gain = rt2x00_get_field16(eeprom,
 2418						      EEPROM_EXT_LNA2_A1);
 2419		} else {
 2420			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
 2421			lna_gain = rt2x00_get_field16(eeprom,
 2422						      EEPROM_RSSI_BG2_LNA_A1);
 2423		}
 2424	} else {
 2425		if (rt2x00_rt(rt2x00dev, RT3593) ||
 2426		    rt2x00_rt(rt2x00dev, RT3883)) {
 2427			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
 2428			lna_gain = rt2x00_get_field16(eeprom,
 2429						      EEPROM_EXT_LNA2_A2);
 2430		} else {
 2431			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
 2432			lna_gain = rt2x00_get_field16(eeprom,
 2433						      EEPROM_RSSI_A2_LNA_A2);
 2434		}
 2435	}
 2436
 2437	rt2x00dev->lna_gain = lna_gain;
 2438}
 2439
 2440static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev)
 2441{
 2442	return clk_get_rate(rt2x00dev->clk) == 20000000;
 2443}
 2444
 2445#define FREQ_OFFSET_BOUND	0x5f
 2446
 2447static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev)
 2448{
 2449	u8 freq_offset, prev_freq_offset;
 2450	u8 rfcsr, prev_rfcsr;
 2451
 2452	freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
 2453	freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
 2454
 2455	rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
 2456	prev_rfcsr = rfcsr;
 2457
 2458	rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
 2459	if (rfcsr == prev_rfcsr)
 2460		return;
 2461
 2462	if (rt2x00_is_usb(rt2x00dev)) {
 2463		rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
 2464				   freq_offset, prev_rfcsr);
 2465		return;
 2466	}
 2467
 2468	prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
 2469	while (prev_freq_offset != freq_offset) {
 2470		if (prev_freq_offset < freq_offset)
 2471			prev_freq_offset++;
 2472		else
 2473			prev_freq_offset--;
 2474
 2475		rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
 2476		rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
 2477
 2478		usleep_range(1000, 1500);
 2479	}
 2480}
 2481
 2482static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
 2483					 struct ieee80211_conf *conf,
 2484					 struct rf_channel *rf,
 2485					 struct channel_info *info)
 2486{
 2487	rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 2488
 2489	if (rt2x00dev->default_ant.tx_chain_num == 1)
 2490		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 2491
 2492	if (rt2x00dev->default_ant.rx_chain_num == 1) {
 2493		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 2494		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 2495	} else if (rt2x00dev->default_ant.rx_chain_num == 2)
 2496		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 2497
 2498	if (rf->channel > 14) {
 2499		/*
 2500		 * When TX power is below 0, we should increase it by 7 to
 2501		 * make it a positive value (Minimum value is -7).
 2502		 * However this means that values between 0 and 7 have
 2503		 * double meaning, and we should set a 7DBm boost flag.
 2504		 */
 2505		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 2506				   (info->default_power1 >= 0));
 2507
 2508		if (info->default_power1 < 0)
 2509			info->default_power1 += 7;
 2510
 2511		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
 2512
 2513		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 2514				   (info->default_power2 >= 0));
 2515
 2516		if (info->default_power2 < 0)
 2517			info->default_power2 += 7;
 2518
 2519		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
 2520	} else {
 2521		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
 2522		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
 2523	}
 2524
 2525	rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 2526
 2527	rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 2528	rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 2529	rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 2530	rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 2531
 2532	udelay(200);
 2533
 2534	rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 2535	rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 2536	rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 2537	rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 2538
 2539	udelay(200);
 2540
 2541	rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 2542	rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 2543	rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 2544	rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 2545}
 2546
 2547static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
 2548					 struct ieee80211_conf *conf,
 2549					 struct rf_channel *rf,
 2550					 struct channel_info *info)
 2551{
 2552	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 2553	u8 rfcsr, calib_tx, calib_rx;
 2554
 2555	rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
 2556
 2557	rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
 2558	rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
 2559	rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
 2560
 2561	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
 2562	rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
 2563	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
 2564
 2565	rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
 2566	rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
 2567	rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
 2568
 2569	rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
 2570	rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
 2571	rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
 2572
 2573	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
 2574	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
 2575	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
 2576			  rt2x00dev->default_ant.rx_chain_num <= 1);
 2577	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
 2578			  rt2x00dev->default_ant.rx_chain_num <= 2);
 2579	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
 2580	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
 2581			  rt2x00dev->default_ant.tx_chain_num <= 1);
 2582	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
 2583			  rt2x00dev->default_ant.tx_chain_num <= 2);
 2584	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
 2585
 2586	rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
 2587	rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 2588	rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 2589
 2590	if (rt2x00_rt(rt2x00dev, RT3390)) {
 2591		calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
 2592		calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
 2593	} else {
 2594		if (conf_is_ht40(conf)) {
 2595			calib_tx = drv_data->calibration_bw40;
 2596			calib_rx = drv_data->calibration_bw40;
 2597		} else {
 2598			calib_tx = drv_data->calibration_bw20;
 2599			calib_rx = drv_data->calibration_bw20;
 2600		}
 2601	}
 2602
 2603	rfcsr = rt2800_rfcsr_read(rt2x00dev, 24);
 2604	rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
 2605	rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
 2606
 2607	rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
 2608	rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
 2609	rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
 2610
 2611	rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
 2612	rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 2613	rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
 2614
 2615	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
 2616	rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
 2617	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
 2618
 2619	usleep_range(1000, 1500);
 2620
 2621	rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
 2622	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
 2623}
 2624
 2625static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
 2626					 struct ieee80211_conf *conf,
 2627					 struct rf_channel *rf,
 2628					 struct channel_info *info)
 2629{
 2630	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 2631	u8 rfcsr;
 2632	u32 reg;
 2633
 2634	if (rf->channel <= 14) {
 2635		rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
 2636		rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
 2637	} else {
 2638		rt2800_bbp_write(rt2x00dev, 25, 0x09);
 2639		rt2800_bbp_write(rt2x00dev, 26, 0xff);
 2640	}
 2641
 2642	rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
 2643	rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
 2644
 2645	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
 2646	rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
 2647	if (rf->channel <= 14)
 2648		rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
 2649	else
 2650		rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
 2651	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
 2652
 2653	rfcsr = rt2800_rfcsr_read(rt2x00dev, 5);
 2654	if (rf->channel <= 14)
 2655		rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
 2656	else
 2657		rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
 2658	rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
 2659
 2660	rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
 2661	if (rf->channel <= 14) {
 2662		rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
 2663		rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 2664				  info->default_power1);
 2665	} else {
 2666		rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
 2667		rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 2668				(info->default_power1 & 0x3) |
 2669				((info->default_power1 & 0xC) << 1));
 2670	}
 2671	rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
 2672
 2673	rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
 2674	if (rf->channel <= 14) {
 2675		rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
 2676		rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
 2677				  info->default_power2);
 2678	} else {
 2679		rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
 2680		rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
 2681				(info->default_power2 & 0x3) |
 2682				((info->default_power2 & 0xC) << 1));
 2683	}
 2684	rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
 2685
 2686	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
 2687	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
 2688	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
 2689	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
 2690	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
 2691	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
 2692	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
 2693	if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
 2694		if (rf->channel <= 14) {
 2695			rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
 2696			rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
 2697		}
 2698		rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
 2699		rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
 2700	} else {
 2701		switch (rt2x00dev->default_ant.tx_chain_num) {
 2702		case 1:
 2703			rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
 2704			fallthrough;
 2705		case 2:
 2706			rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
 2707			break;
 2708		}
 2709
 2710		switch (rt2x00dev->default_ant.rx_chain_num) {
 2711		case 1:
 2712			rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
 2713			fallthrough;
 2714		case 2:
 2715			rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
 2716			break;
 2717		}
 2718	}
 2719	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
 2720
 2721	rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
 2722	rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 2723	rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 2724
 2725	if (conf_is_ht40(conf)) {
 2726		rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
 2727		rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
 2728	} else {
 2729		rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
 2730		rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
 2731	}
 2732
 2733	if (rf->channel <= 14) {
 2734		rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
 2735		rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
 2736		rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
 2737		rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
 2738		rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
 2739		rfcsr = 0x4c;
 2740		rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
 2741				  drv_data->txmixer_gain_24g);
 2742		rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
 2743		rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
 2744		rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
 2745		rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
 2746		rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
 2747		rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
 2748		rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
 2749		rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
 2750	} else {
 2751		rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
 2752		rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
 2753		rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
 2754		rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
 2755		rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
 2756		rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
 2757		rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
 2758		rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
 2759		rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
 2760		rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
 2761		rfcsr = 0x7a;
 2762		rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
 2763				  drv_data->txmixer_gain_5g);
 2764		rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
 2765		rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
 2766		if (rf->channel <= 64) {
 2767			rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
 2768			rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
 2769			rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
 2770		} else if (rf->channel <= 128) {
 2771			rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
 2772			rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
 2773			rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
 2774		} else {
 2775			rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
 2776			rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
 2777			rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
 2778		}
 2779		rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
 2780		rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
 2781		rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
 2782	}
 2783
 2784	reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
 2785	rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
 2786	if (rf->channel <= 14)
 2787		rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
 2788	else
 2789		rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
 2790	rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
 2791
 2792	rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
 2793	rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 2794	rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
 2795}
 2796
 2797static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
 2798					 struct ieee80211_conf *conf,
 2799					 struct rf_channel *rf,
 2800					 struct channel_info *info)
 2801{
 2802	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 2803	u8 txrx_agc_fc;
 2804	u8 txrx_h20m;
 2805	u8 rfcsr;
 2806	u8 bbp;
 2807	const bool txbf_enabled = false; /* TODO */
 2808
 2809	/* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
 2810	bbp = rt2800_bbp_read(rt2x00dev, 109);
 2811	rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
 2812	rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
 2813	rt2800_bbp_write(rt2x00dev, 109, bbp);
 2814
 2815	bbp = rt2800_bbp_read(rt2x00dev, 110);
 2816	rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
 2817	rt2800_bbp_write(rt2x00dev, 110, bbp);
 2818
 2819	if (rf->channel <= 14) {
 2820		/* Restore BBP 25 & 26 for 2.4 GHz */
 2821		rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
 2822		rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
 2823	} else {
 2824		/* Hard code BBP 25 & 26 for 5GHz */
 2825
 2826		/* Enable IQ Phase correction */
 2827		rt2800_bbp_write(rt2x00dev, 25, 0x09);
 2828		/* Setup IQ Phase correction value */
 2829		rt2800_bbp_write(rt2x00dev, 26, 0xff);
 2830	}
 2831
 2832	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
 2833	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
 2834
 2835	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
 2836	rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
 2837	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
 2838
 2839	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
 2840	rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
 2841	if (rf->channel <= 14)
 2842		rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
 2843	else
 2844		rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
 2845	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
 2846
 2847	rfcsr = rt2800_rfcsr_read(rt2x00dev, 53);
 2848	if (rf->channel <= 14) {
 2849		rfcsr = 0;
 2850		rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
 2851				  info->default_power1 & 0x1f);
 2852	} else {
 2853		if (rt2x00_is_usb(rt2x00dev))
 2854			rfcsr = 0x40;
 2855
 2856		rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
 2857				  ((info->default_power1 & 0x18) << 1) |
 2858				  (info->default_power1 & 7));
 2859	}
 2860	rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
 2861
 2862	rfcsr = rt2800_rfcsr_read(rt2x00dev, 55);
 2863	if (rf->channel <= 14) {
 2864		rfcsr = 0;
 2865		rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
 2866				  info->default_power2 & 0x1f);
 2867	} else {
 2868		if (rt2x00_is_usb(rt2x00dev))
 2869			rfcsr = 0x40;
 2870
 2871		rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
 2872				  ((info->default_power2 & 0x18) << 1) |
 2873				  (info->default_power2 & 7));
 2874	}
 2875	rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
 2876
 2877	rfcsr = rt2800_rfcsr_read(rt2x00dev, 54);
 2878	if (rf->channel <= 14) {
 2879		rfcsr = 0;
 2880		rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
 2881				  info->default_power3 & 0x1f);
 2882	} else {
 2883		if (rt2x00_is_usb(rt2x00dev))
 2884			rfcsr = 0x40;
 2885
 2886		rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
 2887				  ((info->default_power3 & 0x18) << 1) |
 2888				  (info->default_power3 & 7));
 2889	}
 2890	rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
 2891
 2892	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
 2893	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
 2894	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
 2895	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
 2896	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
 2897	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
 2898	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
 2899	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
 2900	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
 2901
 2902	switch (rt2x00dev->default_ant.tx_chain_num) {
 2903	case 3:
 2904		rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
 2905		fallthrough;
 2906	case 2:
 2907		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
 2908		fallthrough;
 2909	case 1:
 2910		rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
 2911		break;
 2912	}
 2913
 2914	switch (rt2x00dev->default_ant.rx_chain_num) {
 2915	case 3:
 2916		rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
 2917		fallthrough;
 2918	case 2:
 2919		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
 2920		fallthrough;
 2921	case 1:
 2922		rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
 2923		break;
 2924	}
 2925	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
 2926
 2927	rt2800_freq_cal_mode1(rt2x00dev);
 2928
 2929	if (conf_is_ht40(conf)) {
 2930		txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
 2931						RFCSR24_TX_AGC_FC);
 2932		txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
 2933					      RFCSR24_TX_H20M);
 2934	} else {
 2935		txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
 2936						RFCSR24_TX_AGC_FC);
 2937		txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
 2938					      RFCSR24_TX_H20M);
 2939	}
 2940
 2941	/* NOTE: the reference driver does not writes the new value
 2942	 * back to RFCSR 32
 2943	 */
 2944	rfcsr = rt2800_rfcsr_read(rt2x00dev, 32);
 2945	rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
 2946
 2947	if (rf->channel <= 14)
 2948		rfcsr = 0xa0;
 2949	else
 2950		rfcsr = 0x80;
 2951	rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
 2952
 2953	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
 2954	rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
 2955	rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
 2956	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
 2957
 2958	/* Band selection */
 2959	rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
 2960	if (rf->channel <= 14)
 2961		rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
 2962	else
 2963		rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
 2964	rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
 2965
 2966	rfcsr = rt2800_rfcsr_read(rt2x00dev, 34);
 2967	if (rf->channel <= 14)
 2968		rfcsr = 0x3c;
 2969	else
 2970		rfcsr = 0x20;
 2971	rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
 2972
 2973	rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
 2974	if (rf->channel <= 14)
 2975		rfcsr = 0x1a;
 2976	else
 2977		rfcsr = 0x12;
 2978	rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
 2979
 2980	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
 2981	if (rf->channel >= 1 && rf->channel <= 14)
 2982		rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
 2983	else if (rf->channel >= 36 && rf->channel <= 64)
 2984		rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
 2985	else if (rf->channel >= 100 && rf->channel <= 128)
 2986		rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
 2987	else
 2988		rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
 2989	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
 2990
 2991	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
 2992	rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
 2993	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
 2994
 2995	rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
 2996
 2997	if (rf->channel <= 14) {
 2998		rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
 2999		rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
 3000	} else {
 3001		rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
 3002		rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
 3003	}
 3004
 3005	rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
 3006	rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
 3007	rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
 3008
 3009	rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
 3010	if (rf->channel <= 14) {
 3011		rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
 3012		rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
 3013	} else {
 3014		rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
 3015		rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
 3016	}
 3017	rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
 3018
 3019	rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
 3020	if (rf->channel <= 14)
 3021		rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
 3022	else
 3023		rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
 3024
 3025	if (txbf_enabled)
 3026		rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
 3027
 3028	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
 3029
 3030	rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
 3031	rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
 3032	rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
 3033
 3034	rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
 3035	if (rf->channel <= 14)
 3036		rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
 3037	else
 3038		rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
 3039	rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
 3040
 3041	if (rf->channel <= 14) {
 3042		rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
 3043		rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
 3044	} else {
 3045		rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
 3046		rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
 3047	}
 3048
 3049	/* Initiate VCO calibration */
 3050	rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
 3051	if (rf->channel <= 14) {
 3052		rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
 3053	} else {
 3054		rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
 3055		rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
 3056		rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
 3057		rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
 3058		rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
 3059		rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
 3060	}
 3061	rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
 3062
 3063	if (rf->channel >= 1 && rf->channel <= 14) {
 3064		rfcsr = 0x23;
 3065		if (txbf_enabled)
 3066			rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
 3067		rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
 3068
 3069		rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
 3070	} else if (rf->channel >= 36 && rf->channel <= 64) {
 3071		rfcsr = 0x36;
 3072		if (txbf_enabled)
 3073			rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
 3074		rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
 3075
 3076		rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
 3077	} else if (rf->channel >= 100 && rf->channel <= 128) {
 3078		rfcsr = 0x32;
 3079		if (txbf_enabled)
 3080			rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
 3081		rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
 3082
 3083		rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
 3084	} else {
 3085		rfcsr = 0x30;
 3086		if (txbf_enabled)
 3087			rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
 3088		rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
 3089
 3090		rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
 3091	}
 3092}
 3093
 3094static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev,
 3095					 struct ieee80211_conf *conf,
 3096					 struct rf_channel *rf,
 3097					 struct channel_info *info)
 3098{
 3099	u8 rfcsr;
 3100	u8 bbp;
 3101	u8 pwr1, pwr2, pwr3;
 3102
 3103	const bool txbf_enabled = false; /* TODO */
 3104
 3105	/* TODO: add band selection */
 3106
 3107	if (rf->channel <= 14)
 3108		rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
 3109	else if (rf->channel < 132)
 3110		rt2800_rfcsr_write(rt2x00dev, 6, 0x80);
 3111	else
 3112		rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
 3113
 3114	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
 3115	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
 3116
 3117	if (rf->channel <= 14)
 3118		rt2800_rfcsr_write(rt2x00dev, 11, 0x46);
 3119	else
 3120		rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
 3121
 3122	if (rf->channel <= 14)
 3123		rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
 3124	else
 3125		rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
 3126
 3127	rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
 3128
 3129	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
 3130	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
 3131	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
 3132	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
 3133	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
 3134	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
 3135	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
 3136	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
 3137	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
 3138
 3139	switch (rt2x00dev->default_ant.tx_chain_num) {
 3140	case 3:
 3141		rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
 3142		fallthrough;
 3143	case 2:
 3144		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
 3145		fallthrough;
 3146	case 1:
 3147		rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
 3148		break;
 3149	}
 3150
 3151	switch (rt2x00dev->default_ant.rx_chain_num) {
 3152	case 3:
 3153		rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
 3154		fallthrough;
 3155	case 2:
 3156		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
 3157		fallthrough;
 3158	case 1:
 3159		rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
 3160		break;
 3161	}
 3162	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
 3163
 3164	rt2800_freq_cal_mode1(rt2x00dev);
 3165
 3166	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
 3167	if (!conf_is_ht40(conf))
 3168		rfcsr &= ~(0x06);
 3169	else
 3170		rfcsr |= 0x06;
 3171	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
 3172
 3173	if (rf->channel <= 14)
 3174		rt2800_rfcsr_write(rt2x00dev, 31, 0xa0);
 3175	else
 3176		rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
 3177
 3178	if (conf_is_ht40(conf))
 3179		rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
 3180	else
 3181		rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
 3182
 3183	if (rf->channel <= 14)
 3184		rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
 3185	else
 3186		rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
 3187
 3188	/* loopback RF_BS */
 3189	rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
 3190	if (rf->channel <= 14)
 3191		rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
 3192	else
 3193		rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
 3194	rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
 3195
 3196	if (rf->channel <= 14)
 3197		rfcsr = 0x23;
 3198	else if (rf->channel < 100)
 3199		rfcsr = 0x36;
 3200	else if (rf->channel < 132)
 3201		rfcsr = 0x32;
 3202	else
 3203		rfcsr = 0x30;
 3204
 3205	if (txbf_enabled)
 3206		rfcsr |= 0x40;
 3207
 3208	rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
 3209
 3210	if (rf->channel <= 14)
 3211		rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
 3212	else
 3213		rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
 3214
 3215	if (rf->channel <= 14)
 3216		rfcsr = 0xbb;
 3217	else if (rf->channel < 100)
 3218		rfcsr = 0xeb;
 3219	else if (rf->channel < 132)
 3220		rfcsr = 0xb3;
 3221	else
 3222		rfcsr = 0x9b;
 3223	rt2800_rfcsr_write(rt2x00dev, 45, rfcsr);
 3224
 3225	if (rf->channel <= 14)
 3226		rfcsr = 0x8e;
 3227	else
 3228		rfcsr = 0x8a;
 3229
 3230	if (txbf_enabled)
 3231		rfcsr |= 0x20;
 3232
 3233	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
 3234
 3235	rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
 3236
 3237	rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
 3238	if (rf->channel <= 14)
 3239		rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
 3240	else
 3241		rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
 3242
 3243	rfcsr = rt2800_rfcsr_read(rt2x00dev, 52);
 3244	if (rf->channel <= 14)
 3245		rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
 3246	else
 3247		rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
 3248
 3249	if (rf->channel <= 14) {
 3250		pwr1 = info->default_power1 & 0x1f;
 3251		pwr2 = info->default_power2 & 0x1f;
 3252		pwr3 = info->default_power3 & 0x1f;
 3253	} else {
 3254		pwr1 = 0x48 | ((info->default_power1 & 0x18) << 1) |
 3255			(info->default_power1 & 0x7);
 3256		pwr2 = 0x48 | ((info->default_power2 & 0x18) << 1) |
 3257			(info->default_power2 & 0x7);
 3258		pwr3 = 0x48 | ((info->default_power3 & 0x18) << 1) |
 3259			(info->default_power3 & 0x7);
 3260	}
 3261
 3262	rt2800_rfcsr_write(rt2x00dev, 53, pwr1);
 3263	rt2800_rfcsr_write(rt2x00dev, 54, pwr2);
 3264	rt2800_rfcsr_write(rt2x00dev, 55, pwr3);
 3265
 3266	rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n",
 3267		   rf->channel, pwr1, pwr2, pwr3);
 3268
 3269	bbp = (info->default_power1 >> 5) |
 3270	      ((info->default_power2 & 0xe0) >> 1);
 3271	rt2800_bbp_write(rt2x00dev, 109, bbp);
 3272
 3273	bbp = rt2800_bbp_read(rt2x00dev, 110);
 3274	bbp &= 0x0f;
 3275	bbp |= (info->default_power3 & 0xe0) >> 1;
 3276	rt2800_bbp_write(rt2x00dev, 110, bbp);
 3277
 3278	rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
 3279	if (rf->channel <= 14)
 3280		rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
 3281	else
 3282		rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
 3283
 3284	/* Enable RF tuning */
 3285	rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
 3286	rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
 3287	rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
 3288
 3289	udelay(2000);
 3290
 3291	bbp = rt2800_bbp_read(rt2x00dev, 49);
 3292	/* clear update flag */
 3293	rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe);
 3294	rt2800_bbp_write(rt2x00dev, 49, bbp);
 3295
 3296	/* TODO: add calibration for TxBF */
 3297}
 3298
 3299#define POWER_BOUND		0x27
 3300#define POWER_BOUND_5G		0x2b
 3301
 3302static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
 3303					 struct ieee80211_conf *conf,
 3304					 struct rf_channel *rf,
 3305					 struct channel_info *info)
 3306{
 3307	u8 rfcsr;
 3308
 3309	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
 3310	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
 3311	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
 3312	rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
 3313	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
 3314
 3315	rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
 3316	if (info->default_power1 > POWER_BOUND)
 3317		rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
 3318	else
 3319		rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
 3320	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
 3321
 3322	rt2800_freq_cal_mode1(rt2x00dev);
 3323
 3324	if (rf->channel <= 14) {
 3325		if (rf->channel == 6)
 3326			rt2800_bbp_write(rt2x00dev, 68, 0x0c);
 3327		else
 3328			rt2800_bbp_write(rt2x00dev, 68, 0x0b);
 3329
 3330		if (rf->channel >= 1 && rf->channel <= 6)
 3331			rt2800_bbp_write(rt2x00dev, 59, 0x0f);
 3332		else if (rf->channel >= 7 && rf->channel <= 11)
 3333			rt2800_bbp_write(rt2x00dev, 59, 0x0e);
 3334		else if (rf->channel >= 12 && rf->channel <= 14)
 3335			rt2800_bbp_write(rt2x00dev, 59, 0x0d);
 3336	}
 3337}
 3338
 3339static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
 3340					 struct ieee80211_conf *conf,
 3341					 struct rf_channel *rf,
 3342					 struct channel_info *info)
 3343{
 3344	u8 rfcsr;
 3345
 3346	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
 3347	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
 3348
 3349	rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
 3350	rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
 3351	rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
 3352
 3353	if (info->default_power1 > POWER_BOUND)
 3354		rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
 3355	else
 3356		rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
 3357
 3358	if (info->default_power2 > POWER_BOUND)
 3359		rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
 3360	else
 3361		rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
 3362
 3363	rt2800_freq_cal_mode1(rt2x00dev);
 3364
 3365	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
 3366	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
 3367	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
 3368
 3369	if ( rt2x00dev->default_ant.tx_chain_num == 2 )
 3370		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
 3371	else
 3372		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
 3373
 3374	if ( rt2x00dev->default_ant.rx_chain_num == 2 )
 3375		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
 3376	else
 3377		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
 3378
 3379	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
 3380	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
 3381
 3382	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
 3383
 3384	rt2800_rfcsr_write(rt2x00dev, 31, 80);
 3385}
 3386
 3387static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
 3388					 struct ieee80211_conf *conf,
 3389					 struct rf_channel *rf,
 3390					 struct channel_info *info)
 3391{
 3392	u8 rfcsr;
 3393	int idx = rf->channel-1;
 3394
 3395	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
 3396	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
 3397	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
 3398	rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
 3399	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
 3400
 3401	rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
 3402	if (info->default_power1 > POWER_BOUND)
 3403		rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
 3404	else
 3405		rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
 3406	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
 3407
 3408	if (rt2x00_rt(rt2x00dev, RT5392)) {
 3409		rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
 3410		if (info->default_power2 > POWER_BOUND)
 3411			rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
 3412		else
 3413			rt2x00_set_field8(&rfcsr, RFCSR50_TX,
 3414					  info->default_power2);
 3415		rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
 3416	}
 3417
 3418	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
 3419	if (rt2x00_rt(rt2x00dev, RT5392)) {
 3420		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
 3421		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
 3422	}
 3423	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
 3424	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
 3425	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
 3426	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
 3427	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
 3428
 3429	rt2800_freq_cal_mode1(rt2x00dev);
 3430
 3431	if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
 3432		if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
 3433			/* r55/r59 value array of channel 1~14 */
 3434			static const u8 r55_bt_rev[] = {0x83, 0x83,
 3435				0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
 3436				0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
 3437			static const u8 r59_bt_rev[] = {0x0e, 0x0e,
 3438				0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
 3439				0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
 3440
 3441			rt2800_rfcsr_write(rt2x00dev, 55,
 3442					   r55_bt_rev[idx]);
 3443			rt2800_rfcsr_write(rt2x00dev, 59,
 3444					   r59_bt_rev[idx]);
 3445		} else {
 3446			static const u8 r59_bt[] = {0x8b, 0x8b, 0x8b,
 3447				0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
 3448				0x88, 0x88, 0x86, 0x85, 0x84};
 3449
 3450			rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
 3451		}
 3452	} else {
 3453		if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
 3454			static const u8 r55_nonbt_rev[] = {0x23, 0x23,
 3455				0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
 3456				0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
 3457			static const u8 r59_nonbt_rev[] = {0x07, 0x07,
 3458				0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
 3459				0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
 3460
 3461			rt2800_rfcsr_write(rt2x00dev, 55,
 3462					   r55_nonbt_rev[idx]);
 3463			rt2800_rfcsr_write(rt2x00dev, 59,
 3464					   r59_nonbt_rev[idx]);
 3465		} else if (rt2x00_rt(rt2x00dev, RT5390) ||
 3466			   rt2x00_rt(rt2x00dev, RT5392) ||
 3467			   rt2x00_rt(rt2x00dev, RT6352)) {
 3468			static const u8 r59_non_bt[] = {0x8f, 0x8f,
 3469				0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
 3470				0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
 3471
 3472			rt2800_rfcsr_write(rt2x00dev, 59,
 3473					   r59_non_bt[idx]);
 3474		} else if (rt2x00_rt(rt2x00dev, RT5350)) {
 3475			static const u8 r59_non_bt[] = {0x0b, 0x0b,
 3476				0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a,
 3477				0x0a, 0x09, 0x08, 0x07, 0x07, 0x06};
 3478
 3479			rt2800_rfcsr_write(rt2x00dev, 59,
 3480					   r59_non_bt[idx]);
 3481		}
 3482	}
 3483}
 3484
 3485static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
 3486					 struct ieee80211_conf *conf,
 3487					 struct rf_channel *rf,
 3488					 struct channel_info *info)
 3489{
 3490	u8 rfcsr, ep_reg;
 3491	u32 reg;
 3492	int power_bound;
 3493
 3494	/* TODO */
 3495	const bool is_11b = false;
 3496	const bool is_type_ep = false;
 3497
 3498	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
 3499	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
 3500			   (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
 3501	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
 3502
 3503	/* Order of values on rf_channel entry: N, K, mod, R */
 3504	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
 3505
 3506	rfcsr = rt2800_rfcsr_read(rt2x00dev,  9);
 3507	rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
 3508	rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
 3509	rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
 3510	rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
 3511
 3512	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
 3513	rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
 3514	rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
 3515	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
 3516
 3517	if (rf->channel <= 14) {
 3518		rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
 3519		/* FIXME: RF11 owerwrite ? */
 3520		rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
 3521		rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
 3522		rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
 3523		rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
 3524		rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
 3525		rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
 3526		rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
 3527		rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
 3528		rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
 3529		rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
 3530		rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
 3531		rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
 3532		rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
 3533		rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
 3534		rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
 3535		rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
 3536		rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
 3537		rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
 3538		rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
 3539		rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
 3540		rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
 3541		rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
 3542		rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
 3543		rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
 3544		rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
 3545		rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
 3546		rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
 3547		rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
 3548
 3549		/* TODO RF27 <- tssi */
 3550
 3551		rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
 3552		rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 3553		rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
 3554
 3555		if (is_11b) {
 3556			/* CCK */
 3557			rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
 3558			rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
 3559			if (is_type_ep)
 3560				rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
 3561			else
 3562				rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
 3563		} else {
 3564			/* OFDM */
 3565			if (is_type_ep)
 3566				rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
 3567			else
 3568				rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
 3569		}
 3570
 3571		power_bound = POWER_BOUND;
 3572		ep_reg = 0x2;
 3573	} else {
 3574		rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
 3575		/* FIMXE: RF11 overwrite */
 3576		rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
 3577		rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
 3578		rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
 3579		rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
 3580		rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
 3581		rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
 3582		rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
 3583		rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
 3584		rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
 3585		rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
 3586		rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
 3587		rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
 3588		rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
 3589		rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
 3590
 3591		/* TODO RF27 <- tssi */
 3592
 3593		if (rf->channel >= 36 && rf->channel <= 64) {
 3594
 3595			rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
 3596			rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
 3597			rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
 3598			rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
 3599			if (rf->channel <= 50)
 3600				rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
 3601			else if (rf->channel >= 52)
 3602				rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
 3603			rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
 3604			rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
 3605			rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
 3606			rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
 3607			rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
 3608			rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
 3609			rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
 3610			if (rf->channel <= 50) {
 3611				rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
 3612				rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
 3613			} else if (rf->channel >= 52) {
 3614				rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
 3615				rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
 3616			}
 3617
 3618			rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
 3619			rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
 3620			rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
 3621
 3622		} else if (rf->channel >= 100 && rf->channel <= 165) {
 3623
 3624			rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
 3625			rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
 3626			rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
 3627			if (rf->channel <= 153) {
 3628				rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
 3629				rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
 3630			} else if (rf->channel >= 155) {
 3631				rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
 3632				rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
 3633			}
 3634			if (rf->channel <= 138) {
 3635				rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
 3636				rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
 3637				rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
 3638				rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
 3639			} else if (rf->channel >= 140) {
 3640				rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
 3641				rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
 3642				rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
 3643				rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
 3644			}
 3645			if (rf->channel <= 124)
 3646				rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
 3647			else if (rf->channel >= 126)
 3648				rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
 3649			if (rf->channel <= 138)
 3650				rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
 3651			else if (rf->channel >= 140)
 3652				rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
 3653			rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
 3654			if (rf->channel <= 138)
 3655				rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
 3656			else if (rf->channel >= 140)
 3657				rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
 3658			if (rf->channel <= 128)
 3659				rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
 3660			else if (rf->channel >= 130)
 3661				rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
 3662			if (rf->channel <= 116)
 3663				rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
 3664			else if (rf->channel >= 118)
 3665				rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
 3666			if (rf->channel <= 138)
 3667				rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
 3668			else if (rf->channel >= 140)
 3669				rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
 3670			if (rf->channel <= 116)
 3671				rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
 3672			else if (rf->channel >= 118)
 3673				rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
 3674		}
 3675
 3676		power_bound = POWER_BOUND_5G;
 3677		ep_reg = 0x3;
 3678	}
 3679
 3680	rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
 3681	if (info->default_power1 > power_bound)
 3682		rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
 3683	else
 3684		rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
 3685	if (is_type_ep)
 3686		rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
 3687	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
 3688
 3689	rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
 3690	if (info->default_power2 > power_bound)
 3691		rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
 3692	else
 3693		rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
 3694	if (is_type_ep)
 3695		rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
 3696	rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
 3697
 3698	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
 3699	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
 3700	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
 3701
 3702	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
 3703			  rt2x00dev->default_ant.tx_chain_num >= 1);
 3704	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
 3705			  rt2x00dev->default_ant.tx_chain_num == 2);
 3706	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
 3707
 3708	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
 3709			  rt2x00dev->default_ant.rx_chain_num >= 1);
 3710	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
 3711			  rt2x00dev->default_ant.rx_chain_num == 2);
 3712	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
 3713
 3714	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
 3715	rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
 3716
 3717	if (conf_is_ht40(conf))
 3718		rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
 3719	else
 3720		rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
 3721
 3722	if (!is_11b) {
 3723		rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
 3724		rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
 3725	}
 3726
 3727	/* TODO proper frequency adjustment */
 3728	rt2800_freq_cal_mode1(rt2x00dev);
 3729
 3730	/* TODO merge with others */
 3731	rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
 3732	rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
 3733	rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
 3734
 3735	/* BBP settings */
 3736	rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 3737	rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 3738	rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 3739
 3740	rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
 3741	rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
 3742	rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
 3743	rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
 3744
 3745	/* GLRT band configuration */
 3746	rt2800_bbp_write(rt2x00dev, 195, 128);
 3747	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
 3748	rt2800_bbp_write(rt2x00dev, 195, 129);
 3749	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
 3750	rt2800_bbp_write(rt2x00dev, 195, 130);
 3751	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
 3752	rt2800_bbp_write(rt2x00dev, 195, 131);
 3753	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
 3754	rt2800_bbp_write(rt2x00dev, 195, 133);
 3755	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
 3756	rt2800_bbp_write(rt2x00dev, 195, 124);
 3757	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
 3758}
 3759
 3760static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
 3761					 struct ieee80211_conf *conf,
 3762					 struct rf_channel *rf,
 3763					 struct channel_info *info)
 3764{
 3765	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 3766	u8 rx_agc_fc, tx_agc_fc;
 3767	u8 rfcsr;
 3768
 3769	/* Frequeny plan setting */
 3770	/* Rdiv setting (set 0x03 if Xtal==20)
 3771	 * R13[1:0]
 3772	 */
 3773	rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
 3774	rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620,
 3775			  rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0);
 3776	rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
 3777
 3778	/* N setting
 3779	 * R20[7:0] in rf->rf1
 3780	 * R21[0] always 0
 3781	 */
 3782	rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
 3783	rfcsr = (rf->rf1 & 0x00ff);
 3784	rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
 3785
 3786	rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
 3787	rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0);
 3788	rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
 3789
 3790	/* K setting (always 0)
 3791	 * R16[3:0] (RF PLL freq selection)
 3792	 */
 3793	rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
 3794	rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0);
 3795	rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
 3796
 3797	/* D setting (always 0)
 3798	 * R22[2:0] (D=15, R22[2:0]=<111>)
 3799	 */
 3800	rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
 3801	rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0);
 3802	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
 3803
 3804	/* Ksd setting
 3805	 * Ksd: R17<7:0> in rf->rf2
 3806	 *      R18<7:0> in rf->rf3
 3807	 *      R19<1:0> in rf->rf4
 3808	 */
 3809	rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
 3810	rfcsr = rf->rf2;
 3811	rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
 3812
 3813	rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
 3814	rfcsr = rf->rf3;
 3815	rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
 3816
 3817	rfcsr = rt2800_rfcsr_read(rt2x00dev, 19);
 3818	rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
 3819	rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
 3820
 3821	/* Default: XO=20MHz , SDM mode */
 3822	rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
 3823	rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
 3824	rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
 3825
 3826	rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
 3827	rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
 3828	rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
 3829
 3830	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
 3831	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
 3832			  rt2x00dev->default_ant.tx_chain_num != 1);
 3833	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
 3834
 3835	rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
 3836	rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620,
 3837			  rt2x00dev->default_ant.tx_chain_num != 1);
 3838	rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620,
 3839			  rt2x00dev->default_ant.rx_chain_num != 1);
 3840	rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
 3841
 3842	rfcsr = rt2800_rfcsr_read(rt2x00dev, 42);
 3843	rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620,
 3844			  rt2x00dev->default_ant.tx_chain_num != 1);
 3845	rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
 3846
 3847	/* RF for DC Cal BW */
 3848	if (conf_is_ht40(conf)) {
 3849		rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
 3850		rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
 3851		rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
 3852		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
 3853		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
 3854	} else {
 3855		rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
 3856		rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
 3857		rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
 3858		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
 3859		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
 3860	}
 3861
 3862	if (conf_is_ht40(conf)) {
 3863		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
 3864		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
 3865	} else {
 3866		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
 3867		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
 3868	}
 3869
 3870	rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
 3871	rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
 3872			  conf_is_ht40(conf) && (rf->channel == 11));
 3873	rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
 3874
 3875	if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
 3876		if (conf_is_ht40(conf)) {
 3877			rx_agc_fc = drv_data->rx_calibration_bw40;
 3878			tx_agc_fc = drv_data->tx_calibration_bw40;
 3879		} else {
 3880			rx_agc_fc = drv_data->rx_calibration_bw20;
 3881			tx_agc_fc = drv_data->tx_calibration_bw20;
 3882		}
 3883		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
 3884		rfcsr &= (~0x3F);
 3885		rfcsr |= rx_agc_fc;
 3886		rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
 3887		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
 3888		rfcsr &= (~0x3F);
 3889		rfcsr |= rx_agc_fc;
 3890		rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
 3891		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6);
 3892		rfcsr &= (~0x3F);
 3893		rfcsr |= rx_agc_fc;
 3894		rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
 3895		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7);
 3896		rfcsr &= (~0x3F);
 3897		rfcsr |= rx_agc_fc;
 3898		rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
 3899
 3900		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
 3901		rfcsr &= (~0x3F);
 3902		rfcsr |= tx_agc_fc;
 3903		rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
 3904		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
 3905		rfcsr &= (~0x3F);
 3906		rfcsr |= tx_agc_fc;
 3907		rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
 3908		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58);
 3909		rfcsr &= (~0x3F);
 3910		rfcsr |= tx_agc_fc;
 3911		rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
 3912		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59);
 3913		rfcsr &= (~0x3F);
 3914		rfcsr |= tx_agc_fc;
 3915		rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
 3916	}
 3917}
 3918
 3919static void rt2800_config_alc_rt6352(struct rt2x00_dev *rt2x00dev,
 3920				     struct ieee80211_channel *chan,
 3921				     int power_level)
 3922{
 3923	int cur_channel = rt2x00dev->rf_channel;
 3924	u16 eeprom, chan_power, rate_power, target_power;
 3925	u16 tx_power[2];
 3926	s8 *power_group[2];
 3927	u32 mac_sys_ctrl;
 3928	u32 cnt, reg;
 3929	u8 bbp;
 3930
 3931	if (WARN_ON(cur_channel < 1 || cur_channel > 14))
 3932		return;
 3933
 3934	/* get per chain power, 2 chains in total, unit is 0.5dBm */
 3935	power_level = (power_level - 3) * 2;
 3936
 3937	/* We can't get the accurate TX power. Based on some tests, the real
 3938	 * TX power is approximately equal to channel_power + (max)rate_power.
 3939	 * Usually max rate_power is the gain of the OFDM 6M rate. The antenna
 3940	 * gain and externel PA gain are not included as we are unable to
 3941	 * obtain these values.
 3942	 */
 3943	rate_power = rt2800_eeprom_read_from_array(rt2x00dev,
 3944						   EEPROM_TXPOWER_BYRATE, 1);
 3945	rate_power &= 0x3f;
 3946	power_level -= rate_power;
 3947	if (power_level < 1)
 3948		power_level = 1;
 3949
 3950	power_group[0] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
 3951	power_group[1] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
 3952	for (cnt = 0; cnt < 2; cnt++) {
 3953		chan_power = power_group[cnt][cur_channel - 1];
 3954		if (chan_power >= 0x20 || chan_power == 0)
 3955			chan_power = 0x10;
 3956		tx_power[cnt] = power_level < chan_power ? power_level : chan_power;
 3957	}
 3958
 3959	reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0);
 3960	rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, tx_power[0]);
 3961	rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, tx_power[1]);
 3962	rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_0, 0x2f);
 3963	rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_1, 0x2f);
 3964
 3965	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
 3966	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
 3967		/* init base power by eeprom target power */
 3968		target_power = rt2800_eeprom_read(rt2x00dev,
 3969						  EEPROM_TXPOWER_INIT);
 3970		rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, target_power);
 3971		rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, target_power);
 3972	}
 3973	rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
 3974
 3975	reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
 3976	rt2x00_set_field32(&reg, TX_ALC_CFG_1_TX_TEMP_COMP, 0);
 3977	rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
 3978
 3979	/* Save MAC SYS CTRL registers */
 3980	mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
 3981	/* Disable Tx/Rx */
 3982	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
 3983	/* Check MAC Tx/Rx idle */
 3984	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
 3985		rt2x00_warn(rt2x00dev, "RF busy while configuring ALC\n");
 3986
 3987	if (chan->center_freq > 2457) {
 3988		bbp = rt2800_bbp_read(rt2x00dev, 30);
 3989		bbp = 0x40;
 3990		rt2800_bbp_write(rt2x00dev, 30, bbp);
 3991		rt2800_rfcsr_write(rt2x00dev, 39, 0);
 3992		if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
 3993			rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
 3994		else
 3995			rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
 3996	} else {
 3997		bbp = rt2800_bbp_read(rt2x00dev, 30);
 3998		bbp = 0x1f;
 3999		rt2800_bbp_write(rt2x00dev, 30, bbp);
 4000		rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
 4001		if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
 4002			rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
 4003		else
 4004			rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
 4005	}
 4006	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
 4007
 4008	rt2800_vco_calibration(rt2x00dev);
 4009}
 4010
 4011static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
 4012					   const unsigned int word,
 4013					   const u8 value)
 4014{
 4015	u8 chain, reg;
 4016
 4017	for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
 4018		reg = rt2800_bbp_read(rt2x00dev, 27);
 4019		rt2x00_set_field8(&reg,  BBP27_RX_CHAIN_SEL, chain);
 4020		rt2800_bbp_write(rt2x00dev, 27, reg);
 4021
 4022		rt2800_bbp_write(rt2x00dev, word, value);
 4023	}
 4024}
 4025
 4026static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
 4027{
 4028	u8 cal;
 4029
 4030	/* TX0 IQ Gain */
 4031	rt2800_bbp_write(rt2x00dev, 158, 0x2c);
 4032	if (channel <= 14)
 4033		cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
 4034	else if (channel >= 36 && channel <= 64)
 4035		cal = rt2x00_eeprom_byte(rt2x00dev,
 4036					 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
 4037	else if (channel >= 100 && channel <= 138)
 4038		cal = rt2x00_eeprom_byte(rt2x00dev,
 4039					 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
 4040	else if (channel >= 140 && channel <= 165)
 4041		cal = rt2x00_eeprom_byte(rt2x00dev,
 4042					 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
 4043	else
 4044		cal = 0;
 4045	rt2800_bbp_write(rt2x00dev, 159, cal);
 4046
 4047	/* TX0 IQ Phase */
 4048	rt2800_bbp_write(rt2x00dev, 158, 0x2d);
 4049	if (channel <= 14)
 4050		cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
 4051	else if (channel >= 36 && channel <= 64)
 4052		cal = rt2x00_eeprom_byte(rt2x00dev,
 4053					 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
 4054	else if (channel >= 100 && channel <= 138)
 4055		cal = rt2x00_eeprom_byte(rt2x00dev,
 4056					 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
 4057	else if (channel >= 140 && channel <= 165)
 4058		cal = rt2x00_eeprom_byte(rt2x00dev,
 4059					 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
 4060	else
 4061		cal = 0;
 4062	rt2800_bbp_write(rt2x00dev, 159, cal);
 4063
 4064	/* TX1 IQ Gain */
 4065	rt2800_bbp_write(rt2x00dev, 158, 0x4a);
 4066	if (channel <= 14)
 4067		cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
 4068	else if (channel >= 36 && channel <= 64)
 4069		cal = rt2x00_eeprom_byte(rt2x00dev,
 4070					 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
 4071	else if (channel >= 100 && channel <= 138)
 4072		cal = rt2x00_eeprom_byte(rt2x00dev,
 4073					 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
 4074	else if (channel >= 140 && channel <= 165)
 4075		cal = rt2x00_eeprom_byte(rt2x00dev,
 4076					 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
 4077	else
 4078		cal = 0;
 4079	rt2800_bbp_write(rt2x00dev, 159, cal);
 4080
 4081	/* TX1 IQ Phase */
 4082	rt2800_bbp_write(rt2x00dev, 158, 0x4b);
 4083	if (channel <= 14)
 4084		cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
 4085	else if (channel >= 36 && channel <= 64)
 4086		cal = rt2x00_eeprom_byte(rt2x00dev,
 4087					 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
 4088	else if (channel >= 100 && channel <= 138)
 4089		cal = rt2x00_eeprom_byte(rt2x00dev,
 4090					 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
 4091	else if (channel >= 140 && channel <= 165)
 4092		cal = rt2x00_eeprom_byte(rt2x00dev,
 4093					 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
 4094	else
 4095		cal = 0;
 4096	rt2800_bbp_write(rt2x00dev, 159, cal);
 4097
 4098	/* FIXME: possible RX0, RX1 callibration ? */
 4099
 4100	/* RF IQ compensation control */
 4101	rt2800_bbp_write(rt2x00dev, 158, 0x04);
 4102	cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
 4103	rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
 4104
 4105	/* RF IQ imbalance compensation control */
 4106	rt2800_bbp_write(rt2x00dev, 158, 0x03);
 4107	cal = rt2x00_eeprom_byte(rt2x00dev,
 4108				 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
 4109	rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
 4110}
 4111
 4112static s8 rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
 4113				  unsigned int channel,
 4114				  s8 txpower)
 4115{
 4116	if (rt2x00_rt(rt2x00dev, RT3593) ||
 4117	    rt2x00_rt(rt2x00dev, RT3883))
 4118		txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
 4119
 4120	if (channel <= 14)
 4121		return clamp_t(s8, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
 4122
 4123	if (rt2x00_rt(rt2x00dev, RT3593) ||
 4124	    rt2x00_rt(rt2x00dev, RT3883))
 4125		return clamp_t(s8, txpower, MIN_A_TXPOWER_3593,
 4126			       MAX_A_TXPOWER_3593);
 4127	else
 4128		return clamp_t(s8, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
 4129}
 4130
 4131static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev,
 4132			      struct rf_channel *rf)
 4133{
 4134	u8 bbp;
 4135
 4136	bbp = (rf->channel > 14) ? 0x48 : 0x38;
 4137	rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
 4138
 4139	rt2800_bbp_write(rt2x00dev, 69, 0x12);
 4140
 4141	if (rf->channel <= 14) {
 4142		rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 4143	} else {
 4144		/* Disable CCK packet detection */
 4145		rt2800_bbp_write(rt2x00dev, 70, 0x00);
 4146	}
 4147
 4148	rt2800_bbp_write(rt2x00dev, 73, 0x10);
 4149
 4150	if (rf->channel > 14) {
 4151		rt2800_bbp_write(rt2x00dev, 62, 0x1d);
 4152		rt2800_bbp_write(rt2x00dev, 63, 0x1d);
 4153		rt2800_bbp_write(rt2x00dev, 64, 0x1d);
 4154	} else {
 4155		rt2800_bbp_write(rt2x00dev, 62, 0x2d);
 4156		rt2800_bbp_write(rt2x00dev, 63, 0x2d);
 4157		rt2800_bbp_write(rt2x00dev, 64, 0x2d);
 4158	}
 4159}
 4160
 4161static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 4162				  struct ieee80211_conf *conf,
 4163				  struct rf_channel *rf,
 4164				  struct channel_info *info)
 4165{
 4166	u32 reg;
 4167	u32 tx_pin;
 4168	u8 bbp, rfcsr;
 4169
 4170	info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
 4171						     info->default_power1);
 4172	info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
 4173						     info->default_power2);
 4174	if (rt2x00dev->default_ant.tx_chain_num > 2)
 4175		info->default_power3 =
 4176			rt2800_txpower_to_dev(rt2x00dev, rf->channel,
 4177					      info->default_power3);
 4178
 4179	switch (rt2x00dev->chip.rt) {
 4180	case RT3883:
 4181		rt3883_bbp_adjust(rt2x00dev, rf);
 4182		break;
 4183	}
 4184
 4185	switch (rt2x00dev->chip.rf) {
 4186	case RF2020:
 4187	case RF3020:
 4188	case RF3021:
 4189	case RF3022:
 4190	case RF3320:
 4191		rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
 4192		break;
 4193	case RF3052:
 4194		rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
 4195		break;
 4196	case RF3053:
 4197		rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
 4198		break;
 4199	case RF3290:
 4200		rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
 4201		break;
 4202	case RF3322:
 4203		rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
 4204		break;
 4205	case RF3853:
 4206		rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info);
 4207		break;
 4208	case RF3070:
 4209	case RF5350:
 4210	case RF5360:
 4211	case RF5362:
 4212	case RF5370:
 4213	case RF5372:
 4214	case RF5390:
 4215	case RF5392:
 4216		rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
 4217		break;
 4218	case RF5592:
 4219		rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
 4220		break;
 4221	case RF7620:
 4222		rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
 4223		break;
 4224	default:
 4225		rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
 4226	}
 4227
 4228	if (rt2x00_rf(rt2x00dev, RF3070) ||
 4229	    rt2x00_rf(rt2x00dev, RF3290) ||
 4230	    rt2x00_rf(rt2x00dev, RF3322) ||
 4231	    rt2x00_rf(rt2x00dev, RF5350) ||
 4232	    rt2x00_rf(rt2x00dev, RF5360) ||
 4233	    rt2x00_rf(rt2x00dev, RF5362) ||
 4234	    rt2x00_rf(rt2x00dev, RF5370) ||
 4235	    rt2x00_rf(rt2x00dev, RF5372) ||
 4236	    rt2x00_rf(rt2x00dev, RF5390) ||
 4237	    rt2x00_rf(rt2x00dev, RF5392)) {
 4238		rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
 4239		if (rt2x00_rf(rt2x00dev, RF3322)) {
 4240			rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M,
 4241					  conf_is_ht40(conf));
 4242			rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M,
 4243					  conf_is_ht40(conf));
 4244		} else {
 4245			rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M,
 4246					  conf_is_ht40(conf));
 4247			rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M,
 4248					  conf_is_ht40(conf));
 4249		}
 4250		rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
 4251
 4252		rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
 4253		rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
 4254		rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
 4255	}
 4256
 4257	/*
 4258	 * Change BBP settings
 4259	 */
 4260
 4261	if (rt2x00_rt(rt2x00dev, RT3352)) {
 4262		rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 4263		rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 4264		rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 4265
 4266		rt2800_bbp_write(rt2x00dev, 27, 0x0);
 4267		rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
 4268		rt2800_bbp_write(rt2x00dev, 27, 0x20);
 4269		rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
 4270		rt2800_bbp_write(rt2x00dev, 86, 0x38);
 4271		rt2800_bbp_write(rt2x00dev, 83, 0x6a);
 4272	} else if (rt2x00_rt(rt2x00dev, RT3593)) {
 4273		if (rf->channel > 14) {
 4274			/* Disable CCK Packet detection on 5GHz */
 4275			rt2800_bbp_write(rt2x00dev, 70, 0x00);
 4276		} else {
 4277			rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 4278		}
 4279
 4280		if (conf_is_ht40(conf))
 4281			rt2800_bbp_write(rt2x00dev, 105, 0x04);
 4282		else
 4283			rt2800_bbp_write(rt2x00dev, 105, 0x34);
 4284
 4285		rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 4286		rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 4287		rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 4288		rt2800_bbp_write(rt2x00dev, 77, 0x98);
 4289	} else if (rt2x00_rt(rt2x00dev, RT3883)) {
 4290		rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 4291		rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 4292		rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 4293
 4294		if (rt2x00dev->default_ant.rx_chain_num > 1)
 4295			rt2800_bbp_write(rt2x00dev, 86, 0x46);
 4296		else
 4297			rt2800_bbp_write(rt2x00dev, 86, 0);
 4298	} else {
 4299		rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 4300		rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 4301		rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 4302		if (rt2x00_rt(rt2x00dev, RT6352))
 4303			rt2800_bbp_write(rt2x00dev, 86, 0x38);
 4304		else
 4305			rt2800_bbp_write(rt2x00dev, 86, 0);
 4306	}
 4307
 4308	if (rf->channel <= 14) {
 4309		if (!rt2x00_rt(rt2x00dev, RT5390) &&
 4310		    !rt2x00_rt(rt2x00dev, RT5392) &&
 4311		    !rt2x00_rt(rt2x00dev, RT6352)) {
 4312			if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 4313				rt2800_bbp_write(rt2x00dev, 82, 0x62);
 4314				rt2800_bbp_write(rt2x00dev, 82, 0x62);
 4315				rt2800_bbp_write(rt2x00dev, 75, 0x46);
 4316			} else {
 4317				if (rt2x00_rt(rt2x00dev, RT3593))
 4318					rt2800_bbp_write(rt2x00dev, 82, 0x62);
 4319				else
 4320					rt2800_bbp_write(rt2x00dev, 82, 0x84);
 4321				rt2800_bbp_write(rt2x00dev, 75, 0x50);
 4322			}
 4323			if (rt2x00_rt(rt2x00dev, RT3593) ||
 4324			    rt2x00_rt(rt2x00dev, RT3883))
 4325				rt2800_bbp_write(rt2x00dev, 83, 0x8a);
 4326		}
 4327
 4328	} else {
 4329		if (rt2x00_rt(rt2x00dev, RT3572))
 4330			rt2800_bbp_write(rt2x00dev, 82, 0x94);
 4331		else if (rt2x00_rt(rt2x00dev, RT3593) ||
 4332			 rt2x00_rt(rt2x00dev, RT3883))
 4333			rt2800_bbp_write(rt2x00dev, 82, 0x82);
 4334		else if (!rt2x00_rt(rt2x00dev, RT6352))
 4335			rt2800_bbp_write(rt2x00dev, 82, 0xf2);
 4336
 4337		if (rt2x00_rt(rt2x00dev, RT3593) ||
 4338		    rt2x00_rt(rt2x00dev, RT3883))
 4339			rt2800_bbp_write(rt2x00dev, 83, 0x9a);
 4340
 4341		if (rt2x00_has_cap_external_lna_a(rt2x00dev))
 4342			rt2800_bbp_write(rt2x00dev, 75, 0x46);
 4343		else
 4344			rt2800_bbp_write(rt2x00dev, 75, 0x50);
 4345	}
 4346
 4347	reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG);
 4348	rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
 4349	rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 4350	rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 4351	rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
 4352
 4353	if (rt2x00_rt(rt2x00dev, RT3572))
 4354		rt2800_rfcsr_write(rt2x00dev, 8, 0);
 4355
 4356	if (rt2x00_rt(rt2x00dev, RT6352)) {
 4357		tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
 4358		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1);
 4359	} else {
 4360		tx_pin = 0;
 4361	}
 4362
 4363	switch (rt2x00dev->default_ant.tx_chain_num) {
 4364	case 3:
 4365		/* Turn on tertiary PAs */
 4366		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
 4367				   rf->channel > 14);
 4368		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
 4369				   rf->channel <= 14);
 4370		fallthrough;
 4371	case 2:
 4372		/* Turn on secondary PAs */
 4373		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
 4374				   rf->channel > 14);
 4375		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
 4376				   rf->channel <= 14);
 4377		fallthrough;
 4378	case 1:
 4379		/* Turn on primary PAs */
 4380		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
 4381				   rf->channel > 14);
 4382		if (rt2x00_has_cap_bt_coexist(rt2x00dev))
 4383			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
 4384		else
 4385			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
 4386					   rf->channel <= 14);
 4387		break;
 4388	}
 4389
 4390	switch (rt2x00dev->default_ant.rx_chain_num) {
 4391	case 3:
 4392		/* Turn on tertiary LNAs */
 4393		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
 4394		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
 4395		fallthrough;
 4396	case 2:
 4397		/* Turn on secondary LNAs */
 4398		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 4399		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 4400		fallthrough;
 4401	case 1:
 4402		/* Turn on primary LNAs */
 4403		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 4404		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 4405		break;
 4406	}
 4407
 4408	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 4409	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 4410
 4411	rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 4412
 4413	if (rt2x00_rt(rt2x00dev, RT3572)) {
 4414		rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
 4415
 4416		/* AGC init */
 4417		if (rf->channel <= 14)
 4418			reg = 0x1c + (2 * rt2x00dev->lna_gain);
 4419		else
 4420			reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
 4421
 4422		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
 4423	}
 4424
 4425	if (rt2x00_rt(rt2x00dev, RT3593)) {
 4426		reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
 4427
 4428		/* Band selection */
 4429		if (rt2x00_is_usb(rt2x00dev) ||
 4430		    rt2x00_is_pcie(rt2x00dev)) {
 4431			/* GPIO #8 controls all paths */
 4432			rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
 4433			if (rf->channel <= 14)
 4434				rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
 4435			else
 4436				rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
 4437		}
 4438
 4439		/* LNA PE control. */
 4440		if (rt2x00_is_usb(rt2x00dev)) {
 4441			/* GPIO #4 controls PE0 and PE1,
 4442			 * GPIO #7 controls PE2
 4443			 */
 4444			rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
 4445			rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
 4446
 4447			rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
 4448			rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
 4449		} else if (rt2x00_is_pcie(rt2x00dev)) {
 4450			/* GPIO #4 controls PE0, PE1 and PE2 */
 4451			rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
 4452			rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
 4453		}
 4454
 4455		rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
 4456
 4457		/* AGC init */
 4458		if (rf->channel <= 14)
 4459			reg = 0x1c + 2 * rt2x00dev->lna_gain;
 4460		else
 4461			reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
 4462
 4463		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
 4464
 4465		usleep_range(1000, 1500);
 4466	}
 4467
 4468	if (rt2x00_rt(rt2x00dev, RT3883)) {
 4469		if (!conf_is_ht40(conf))
 4470			rt2800_bbp_write(rt2x00dev, 105, 0x34);
 4471		else
 4472			rt2800_bbp_write(rt2x00dev, 105, 0x04);
 4473
 4474		/* AGC init */
 4475		if (rf->channel <= 14)
 4476			reg = 0x2e + rt2x00dev->lna_gain;
 4477		else
 4478			reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3);
 4479
 4480		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
 4481
 4482		usleep_range(1000, 1500);
 4483	}
 4484
 4485	if (rt2x00_rt(rt2x00dev, RT5592)) {
 4486		bbp = conf_is_ht40(conf) ? 0x10 : 0x1a;
 4487		rt2800_bbp_glrt_write(rt2x00dev, 141, bbp);
 4488
 4489		bbp = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
 4490		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
 4491
 4492		rt2800_iq_calibrate(rt2x00dev, rf->channel);
 4493	}
 4494
 4495	if (rt2x00_rt(rt2x00dev, RT6352)) {
 4496		/* BBP for GLRT BW */
 4497		bbp = conf_is_ht40(conf) ?
 4498		      0x10 : rt2x00_has_cap_external_lna_bg(rt2x00dev) ?
 4499		      0x15 : 0x1a;
 4500		rt2800_bbp_glrt_write(rt2x00dev, 141, bbp);
 4501
 4502		bbp = conf_is_ht40(conf) ? 0x2f : 0x40;
 4503		rt2800_bbp_glrt_write(rt2x00dev, 157, bbp);
 4504
 4505		if (rt2x00dev->default_ant.rx_chain_num == 1) {
 4506			rt2800_bbp_write(rt2x00dev, 91, 0x07);
 4507			rt2800_bbp_write(rt2x00dev, 95, 0x1a);
 4508			rt2800_bbp_glrt_write(rt2x00dev, 128, 0xa0);
 4509			rt2800_bbp_glrt_write(rt2x00dev, 170, 0x12);
 4510			rt2800_bbp_glrt_write(rt2x00dev, 171, 0x10);
 4511		} else {
 4512			rt2800_bbp_write(rt2x00dev, 91, 0x06);
 4513			rt2800_bbp_write(rt2x00dev, 95, 0x9a);
 4514			rt2800_bbp_glrt_write(rt2x00dev, 128, 0xe0);
 4515			rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
 4516			rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
 4517		}
 4518
 4519		/* AGC init */
 4520		bbp = rf->channel <= 14 ? 0x04 + 2 * rt2x00dev->lna_gain : 0;
 4521		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
 4522
 4523		usleep_range(1000, 1500);
 4524	}
 4525
 4526	bbp = rt2800_bbp_read(rt2x00dev, 4);
 4527	rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 4528	rt2800_bbp_write(rt2x00dev, 4, bbp);
 4529
 4530	bbp = rt2800_bbp_read(rt2x00dev, 3);
 4531	rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
 4532	rt2800_bbp_write(rt2x00dev, 3, bbp);
 4533
 4534	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
 4535		if (conf_is_ht40(conf)) {
 4536			rt2800_bbp_write(rt2x00dev, 69, 0x1a);
 4537			rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 4538			rt2800_bbp_write(rt2x00dev, 73, 0x16);
 4539		} else {
 4540			rt2800_bbp_write(rt2x00dev, 69, 0x16);
 4541			rt2800_bbp_write(rt2x00dev, 70, 0x08);
 4542			rt2800_bbp_write(rt2x00dev, 73, 0x11);
 4543		}
 4544	}
 4545
 4546	usleep_range(1000, 1500);
 4547
 4548	/*
 4549	 * Clear channel statistic counters
 4550	 */
 4551	reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
 4552	reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
 4553	reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
 4554
 4555	/*
 4556	 * Clear update flag
 4557	 */
 4558	if (rt2x00_rt(rt2x00dev, RT3352) ||
 4559	    rt2x00_rt(rt2x00dev, RT5350)) {
 4560		bbp = rt2800_bbp_read(rt2x00dev, 49);
 4561		rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
 4562		rt2800_bbp_write(rt2x00dev, 49, bbp);
 4563	}
 4564}
 4565
 4566static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
 4567{
 4568	u8 tssi_bounds[9];
 4569	u8 current_tssi;
 4570	u16 eeprom;
 4571	u8 step;
 4572	int i;
 4573
 4574	/*
 4575	 * First check if temperature compensation is supported.
 4576	 */
 4577	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
 4578	if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
 4579		return 0;
 4580
 4581	/*
 4582	 * Read TSSI boundaries for temperature compensation from
 4583	 * the EEPROM.
 4584	 *
 4585	 * Array idx               0    1    2    3    4    5    6    7    8
 4586	 * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
 4587	 * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
 4588	 */
 4589	if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
 4590		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1);
 4591		tssi_bounds[0] = rt2x00_get_field16(eeprom,
 4592					EEPROM_TSSI_BOUND_BG1_MINUS4);
 4593		tssi_bounds[1] = rt2x00_get_field16(eeprom,
 4594					EEPROM_TSSI_BOUND_BG1_MINUS3);
 4595
 4596		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2);
 4597		tssi_bounds[2] = rt2x00_get_field16(eeprom,
 4598					EEPROM_TSSI_BOUND_BG2_MINUS2);
 4599		tssi_bounds[3] = rt2x00_get_field16(eeprom,
 4600					EEPROM_TSSI_BOUND_BG2_MINUS1);
 4601
 4602		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3);
 4603		tssi_bounds[4] = rt2x00_get_field16(eeprom,
 4604					EEPROM_TSSI_BOUND_BG3_REF);
 4605		tssi_bounds[5] = rt2x00_get_field16(eeprom,
 4606					EEPROM_TSSI_BOUND_BG3_PLUS1);
 4607
 4608		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4);
 4609		tssi_bounds[6] = rt2x00_get_field16(eeprom,
 4610					EEPROM_TSSI_BOUND_BG4_PLUS2);
 4611		tssi_bounds[7] = rt2x00_get_field16(eeprom,
 4612					EEPROM_TSSI_BOUND_BG4_PLUS3);
 4613
 4614		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5);
 4615		tssi_bounds[8] = rt2x00_get_field16(eeprom,
 4616					EEPROM_TSSI_BOUND_BG5_PLUS4);
 4617
 4618		step = rt2x00_get_field16(eeprom,
 4619					  EEPROM_TSSI_BOUND_BG5_AGC_STEP);
 4620	} else {
 4621		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1);
 4622		tssi_bounds[0] = rt2x00_get_field16(eeprom,
 4623					EEPROM_TSSI_BOUND_A1_MINUS4);
 4624		tssi_bounds[1] = rt2x00_get_field16(eeprom,
 4625					EEPROM_TSSI_BOUND_A1_MINUS3);
 4626
 4627		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2);
 4628		tssi_bounds[2] = rt2x00_get_field16(eeprom,
 4629					EEPROM_TSSI_BOUND_A2_MINUS2);
 4630		tssi_bounds[3] = rt2x00_get_field16(eeprom,
 4631					EEPROM_TSSI_BOUND_A2_MINUS1);
 4632
 4633		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3);
 4634		tssi_bounds[4] = rt2x00_get_field16(eeprom,
 4635					EEPROM_TSSI_BOUND_A3_REF);
 4636		tssi_bounds[5] = rt2x00_get_field16(eeprom,
 4637					EEPROM_TSSI_BOUND_A3_PLUS1);
 4638
 4639		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4);
 4640		tssi_bounds[6] = rt2x00_get_field16(eeprom,
 4641					EEPROM_TSSI_BOUND_A4_PLUS2);
 4642		tssi_bounds[7] = rt2x00_get_field16(eeprom,
 4643					EEPROM_TSSI_BOUND_A4_PLUS3);
 4644
 4645		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5);
 4646		tssi_bounds[8] = rt2x00_get_field16(eeprom,
 4647					EEPROM_TSSI_BOUND_A5_PLUS4);
 4648
 4649		step = rt2x00_get_field16(eeprom,
 4650					  EEPROM_TSSI_BOUND_A5_AGC_STEP);
 4651	}
 4652
 4653	/*
 4654	 * Check if temperature compensation is supported.
 4655	 */
 4656	if (tssi_bounds[4] == 0xff || step == 0xff)
 4657		return 0;
 4658
 4659	/*
 4660	 * Read current TSSI (BBP 49).
 4661	 */
 4662	current_tssi = rt2800_bbp_read(rt2x00dev, 49);
 4663
 4664	/*
 4665	 * Compare TSSI value (BBP49) with the compensation boundaries
 4666	 * from the EEPROM and increase or decrease tx power.
 4667	 */
 4668	for (i = 0; i <= 3; i++) {
 4669		if (current_tssi > tssi_bounds[i])
 4670			break;
 4671	}
 4672
 4673	if (i == 4) {
 4674		for (i = 8; i >= 5; i--) {
 4675			if (current_tssi < tssi_bounds[i])
 4676				break;
 4677		}
 4678	}
 4679
 4680	return (i - 4) * step;
 4681}
 4682
 4683static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
 4684				      enum nl80211_band band)
 4685{
 4686	u16 eeprom;
 4687	u8 comp_en;
 4688	u8 comp_type;
 4689	int comp_value = 0;
 4690
 4691	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA);
 4692
 4693	/*
 4694	 * HT40 compensation not required.
 4695	 */
 4696	if (eeprom == 0xffff ||
 4697	    !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
 4698		return 0;
 4699
 4700	if (band == NL80211_BAND_2GHZ) {
 4701		comp_en = rt2x00_get_field16(eeprom,
 4702				 EEPROM_TXPOWER_DELTA_ENABLE_2G);
 4703		if (comp_en) {
 4704			comp_type = rt2x00_get_field16(eeprom,
 4705					   EEPROM_TXPOWER_DELTA_TYPE_2G);
 4706			comp_value = rt2x00_get_field16(eeprom,
 4707					    EEPROM_TXPOWER_DELTA_VALUE_2G);
 4708			if (!comp_type)
 4709				comp_value = -comp_value;
 4710		}
 4711	} else {
 4712		comp_en = rt2x00_get_field16(eeprom,
 4713				 EEPROM_TXPOWER_DELTA_ENABLE_5G);
 4714		if (comp_en) {
 4715			comp_type = rt2x00_get_field16(eeprom,
 4716					   EEPROM_TXPOWER_DELTA_TYPE_5G);
 4717			comp_value = rt2x00_get_field16(eeprom,
 4718					    EEPROM_TXPOWER_DELTA_VALUE_5G);
 4719			if (!comp_type)
 4720				comp_value = -comp_value;
 4721		}
 4722	}
 4723
 4724	return comp_value;
 4725}
 4726
 4727static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
 4728					int power_level, int max_power)
 4729{
 4730	int delta;
 4731
 4732	if (rt2x00_has_cap_power_limit(rt2x00dev))
 4733		return 0;
 4734
 4735	/*
 4736	 * XXX: We don't know the maximum transmit power of our hardware since
 4737	 * the EEPROM doesn't expose it. We only know that we are calibrated
 4738	 * to 100% tx power.
 4739	 *
 4740	 * Hence, we assume the regulatory limit that cfg80211 calulated for
 4741	 * the current channel is our maximum and if we are requested to lower
 4742	 * the value we just reduce our tx power accordingly.
 4743	 */
 4744	delta = power_level - max_power;
 4745	return min(delta, 0);
 4746}
 4747
 4748static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
 4749				   enum nl80211_band band, int power_level,
 4750				   u8 txpower, int delta)
 4751{
 4752	u16 eeprom;
 4753	u8 criterion;
 4754	u8 eirp_txpower;
 4755	u8 eirp_txpower_criterion;
 4756	u8 reg_limit;
 4757
 4758	if (rt2x00_rt(rt2x00dev, RT3593))
 4759		return min_t(u8, txpower, 0xc);
 4760
 4761	if (rt2x00_rt(rt2x00dev, RT3883))
 4762		return min_t(u8, txpower, 0xf);
 4763
 4764	if (rt2x00_has_cap_power_limit(rt2x00dev)) {
 4765		/*
 4766		 * Check if eirp txpower exceed txpower_limit.
 4767		 * We use OFDM 6M as criterion and its eirp txpower
 4768		 * is stored at EEPROM_EIRP_MAX_TX_POWER.
 4769		 * .11b data rate need add additional 4dbm
 4770		 * when calculating eirp txpower.
 4771		 */
 4772		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
 4773						       EEPROM_TXPOWER_BYRATE,
 4774						       1);
 4775		criterion = rt2x00_get_field16(eeprom,
 4776					       EEPROM_TXPOWER_BYRATE_RATE0);
 4777
 4778		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
 4779
 4780		if (band == NL80211_BAND_2GHZ)
 4781			eirp_txpower_criterion = rt2x00_get_field16(eeprom,
 4782						 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
 4783		else
 4784			eirp_txpower_criterion = rt2x00_get_field16(eeprom,
 4785						 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
 4786
 4787		eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
 4788			       (is_rate_b ? 4 : 0) + delta;
 4789
 4790		reg_limit = (eirp_txpower > power_level) ?
 4791					(eirp_txpower - power_level) : 0;
 4792	} else
 4793		reg_limit = 0;
 4794
 4795	txpower = max(0, txpower + delta - reg_limit);
 4796	return min_t(u8, txpower, 0xc);
 4797}
 4798
 4799
 4800enum {
 4801	TX_PWR_CFG_0_IDX,
 4802	TX_PWR_CFG_1_IDX,
 4803	TX_PWR_CFG_2_IDX,
 4804	TX_PWR_CFG_3_IDX,
 4805	TX_PWR_CFG_4_IDX,
 4806	TX_PWR_CFG_5_IDX,
 4807	TX_PWR_CFG_6_IDX,
 4808	TX_PWR_CFG_7_IDX,
 4809	TX_PWR_CFG_8_IDX,
 4810	TX_PWR_CFG_9_IDX,
 4811	TX_PWR_CFG_0_EXT_IDX,
 4812	TX_PWR_CFG_1_EXT_IDX,
 4813	TX_PWR_CFG_2_EXT_IDX,
 4814	TX_PWR_CFG_3_EXT_IDX,
 4815	TX_PWR_CFG_4_EXT_IDX,
 4816	TX_PWR_CFG_IDX_COUNT,
 4817};
 4818
 4819static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
 4820					 struct ieee80211_channel *chan,
 4821					 int power_level)
 4822{
 4823	u8 txpower;
 4824	u16 eeprom;
 4825	u32 regs[TX_PWR_CFG_IDX_COUNT];
 4826	unsigned int offset;
 4827	enum nl80211_band band = chan->band;
 4828	int delta;
 4829	int i;
 4830
 4831	memset(regs, '\0', sizeof(regs));
 4832
 4833	/* TODO: adapt TX power reduction from the rt28xx code */
 4834
 4835	/* calculate temperature compensation delta */
 4836	delta = rt2800_get_gain_calibration_delta(rt2x00dev);
 4837
 4838	if (band == NL80211_BAND_5GHZ)
 4839		offset = 16;
 4840	else
 4841		offset = 0;
 4842
 4843	if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
 4844		offset += 8;
 4845
 4846	/* read the next four txpower values */
 4847	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
 4848					       offset);
 4849
 4850	/* CCK 1MBS,2MBS */
 4851	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
 4852	txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
 4853					    txpower, delta);
 4854	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
 4855			   TX_PWR_CFG_0_CCK1_CH0, txpower);
 4856	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
 4857			   TX_PWR_CFG_0_CCK1_CH1, txpower);
 4858	rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
 4859			   TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
 4860
 4861	/* CCK 5.5MBS,11MBS */
 4862	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
 4863	txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
 4864					    txpower, delta);
 4865	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
 4866			   TX_PWR_CFG_0_CCK5_CH0, txpower);
 4867	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
 4868			   TX_PWR_CFG_0_CCK5_CH1, txpower);
 4869	rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
 4870			   TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
 4871
 4872	/* OFDM 6MBS,9MBS */
 4873	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
 4874	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 4875					    txpower, delta);
 4876	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
 4877			   TX_PWR_CFG_0_OFDM6_CH0, txpower);
 4878	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
 4879			   TX_PWR_CFG_0_OFDM6_CH1, txpower);
 4880	rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
 4881			   TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
 4882
 4883	/* OFDM 12MBS,18MBS */
 4884	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
 4885	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 4886					    txpower, delta);
 4887	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
 4888			   TX_PWR_CFG_0_OFDM12_CH0, txpower);
 4889	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
 4890			   TX_PWR_CFG_0_OFDM12_CH1, txpower);
 4891	rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
 4892			   TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
 4893
 4894	/* read the next four txpower values */
 4895	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
 4896					       offset + 1);
 4897
 4898	/* OFDM 24MBS,36MBS */
 4899	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
 4900	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 4901					    txpower, delta);
 4902	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
 4903			   TX_PWR_CFG_1_OFDM24_CH0, txpower);
 4904	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
 4905			   TX_PWR_CFG_1_OFDM24_CH1, txpower);
 4906	rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
 4907			   TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
 4908
 4909	/* OFDM 48MBS */
 4910	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
 4911	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 4912					    txpower, delta);
 4913	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
 4914			   TX_PWR_CFG_1_OFDM48_CH0, txpower);
 4915	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
 4916			   TX_PWR_CFG_1_OFDM48_CH1, txpower);
 4917	rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
 4918			   TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
 4919
 4920	/* OFDM 54MBS */
 4921	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
 4922	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 4923					    txpower, delta);
 4924	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
 4925			   TX_PWR_CFG_7_OFDM54_CH0, txpower);
 4926	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
 4927			   TX_PWR_CFG_7_OFDM54_CH1, txpower);
 4928	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
 4929			   TX_PWR_CFG_7_OFDM54_CH2, txpower);
 4930
 4931	/* read the next four txpower values */
 4932	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
 4933					       offset + 2);
 4934
 4935	/* MCS 0,1 */
 4936	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
 4937	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 4938					    txpower, delta);
 4939	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
 4940			   TX_PWR_CFG_1_MCS0_CH0, txpower);
 4941	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
 4942			   TX_PWR_CFG_1_MCS0_CH1, txpower);
 4943	rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
 4944			   TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
 4945
 4946	/* MCS 2,3 */
 4947	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
 4948	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 4949					    txpower, delta);
 4950	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
 4951			   TX_PWR_CFG_1_MCS2_CH0, txpower);
 4952	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
 4953			   TX_PWR_CFG_1_MCS2_CH1, txpower);
 4954	rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
 4955			   TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
 4956
 4957	/* MCS 4,5 */
 4958	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
 4959	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 4960					    txpower, delta);
 4961	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
 4962			   TX_PWR_CFG_2_MCS4_CH0, txpower);
 4963	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
 4964			   TX_PWR_CFG_2_MCS4_CH1, txpower);
 4965	rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
 4966			   TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
 4967
 4968	/* MCS 6 */
 4969	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
 4970	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 4971					    txpower, delta);
 4972	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
 4973			   TX_PWR_CFG_2_MCS6_CH0, txpower);
 4974	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
 4975			   TX_PWR_CFG_2_MCS6_CH1, txpower);
 4976	rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
 4977			   TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
 4978
 4979	/* read the next four txpower values */
 4980	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
 4981					       offset + 3);
 4982
 4983	/* MCS 7 */
 4984	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
 4985	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 4986					    txpower, delta);
 4987	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
 4988			   TX_PWR_CFG_7_MCS7_CH0, txpower);
 4989	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
 4990			   TX_PWR_CFG_7_MCS7_CH1, txpower);
 4991	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
 4992			   TX_PWR_CFG_7_MCS7_CH2, txpower);
 4993
 4994	/* MCS 8,9 */
 4995	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
 4996	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 4997					    txpower, delta);
 4998	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
 4999			   TX_PWR_CFG_2_MCS8_CH0, txpower);
 5000	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
 5001			   TX_PWR_CFG_2_MCS8_CH1, txpower);
 5002	rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
 5003			   TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
 5004
 5005	/* MCS 10,11 */
 5006	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
 5007	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 5008					    txpower, delta);
 5009	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
 5010			   TX_PWR_CFG_2_MCS10_CH0, txpower);
 5011	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
 5012			   TX_PWR_CFG_2_MCS10_CH1, txpower);
 5013	rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
 5014			   TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
 5015
 5016	/* MCS 12,13 */
 5017	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
 5018	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 5019					    txpower, delta);
 5020	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
 5021			   TX_PWR_CFG_3_MCS12_CH0, txpower);
 5022	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
 5023			   TX_PWR_CFG_3_MCS12_CH1, txpower);
 5024	rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
 5025			   TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
 5026
 5027	/* read the next four txpower values */
 5028	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
 5029					       offset + 4);
 5030
 5031	/* MCS 14 */
 5032	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
 5033	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 5034					    txpower, delta);
 5035	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
 5036			   TX_PWR_CFG_3_MCS14_CH0, txpower);
 5037	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
 5038			   TX_PWR_CFG_3_MCS14_CH1, txpower);
 5039	rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
 5040			   TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
 5041
 5042	/* MCS 15 */
 5043	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
 5044	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 5045					    txpower, delta);
 5046	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
 5047			   TX_PWR_CFG_8_MCS15_CH0, txpower);
 5048	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
 5049			   TX_PWR_CFG_8_MCS15_CH1, txpower);
 5050	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
 5051			   TX_PWR_CFG_8_MCS15_CH2, txpower);
 5052
 5053	/* MCS 16,17 */
 5054	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
 5055	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 5056					    txpower, delta);
 5057	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
 5058			   TX_PWR_CFG_5_MCS16_CH0, txpower);
 5059	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
 5060			   TX_PWR_CFG_5_MCS16_CH1, txpower);
 5061	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
 5062			   TX_PWR_CFG_5_MCS16_CH2, txpower);
 5063
 5064	/* MCS 18,19 */
 5065	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
 5066	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 5067					    txpower, delta);
 5068	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
 5069			   TX_PWR_CFG_5_MCS18_CH0, txpower);
 5070	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
 5071			   TX_PWR_CFG_5_MCS18_CH1, txpower);
 5072	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
 5073			   TX_PWR_CFG_5_MCS18_CH2, txpower);
 5074
 5075	/* read the next four txpower values */
 5076	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
 5077					       offset + 5);
 5078
 5079	/* MCS 20,21 */
 5080	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
 5081	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 5082					    txpower, delta);
 5083	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
 5084			   TX_PWR_CFG_6_MCS20_CH0, txpower);
 5085	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
 5086			   TX_PWR_CFG_6_MCS20_CH1, txpower);
 5087	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
 5088			   TX_PWR_CFG_6_MCS20_CH2, txpower);
 5089
 5090	/* MCS 22 */
 5091	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
 5092	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 5093					    txpower, delta);
 5094	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
 5095			   TX_PWR_CFG_6_MCS22_CH0, txpower);
 5096	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
 5097			   TX_PWR_CFG_6_MCS22_CH1, txpower);
 5098	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
 5099			   TX_PWR_CFG_6_MCS22_CH2, txpower);
 5100
 5101	/* MCS 23 */
 5102	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
 5103	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 5104					    txpower, delta);
 5105	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
 5106			   TX_PWR_CFG_8_MCS23_CH0, txpower);
 5107	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
 5108			   TX_PWR_CFG_8_MCS23_CH1, txpower);
 5109	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
 5110			   TX_PWR_CFG_8_MCS23_CH2, txpower);
 5111
 5112	/* read the next four txpower values */
 5113	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
 5114					       offset + 6);
 5115
 5116	/* STBC, MCS 0,1 */
 5117	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
 5118	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 5119					    txpower, delta);
 5120	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
 5121			   TX_PWR_CFG_3_STBC0_CH0, txpower);
 5122	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
 5123			   TX_PWR_CFG_3_STBC0_CH1, txpower);
 5124	rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
 5125			   TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
 5126
 5127	/* STBC, MCS 2,3 */
 5128	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
 5129	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 5130					    txpower, delta);
 5131	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
 5132			   TX_PWR_CFG_3_STBC2_CH0, txpower);
 5133	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
 5134			   TX_PWR_CFG_3_STBC2_CH1, txpower);
 5135	rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
 5136			   TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
 5137
 5138	/* STBC, MCS 4,5 */
 5139	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
 5140	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 5141					    txpower, delta);
 5142	rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
 5143	rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
 5144	rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
 5145			   txpower);
 5146
 5147	/* STBC, MCS 6 */
 5148	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
 5149	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 5150					    txpower, delta);
 5151	rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
 5152	rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
 5153	rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
 5154			   txpower);
 5155
 5156	/* read the next four txpower values */
 5157	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
 5158					       offset + 7);
 5159
 5160	/* STBC, MCS 7 */
 5161	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
 5162	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
 5163					    txpower, delta);
 5164	rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
 5165			   TX_PWR_CFG_9_STBC7_CH0, txpower);
 5166	rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
 5167			   TX_PWR_CFG_9_STBC7_CH1, txpower);
 5168	rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
 5169			   TX_PWR_CFG_9_STBC7_CH2, txpower);
 5170
 5171	rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
 5172	rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
 5173	rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
 5174	rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
 5175	rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
 5176	rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
 5177	rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
 5178	rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
 5179	rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
 5180	rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
 5181
 5182	rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
 5183			      regs[TX_PWR_CFG_0_EXT_IDX]);
 5184	rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
 5185			      regs[TX_PWR_CFG_1_EXT_IDX]);
 5186	rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
 5187			      regs[TX_PWR_CFG_2_EXT_IDX]);
 5188	rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
 5189			      regs[TX_PWR_CFG_3_EXT_IDX]);
 5190	rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
 5191			      regs[TX_PWR_CFG_4_EXT_IDX]);
 5192
 5193	for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
 5194		rt2x00_dbg(rt2x00dev,
 5195			   "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
 5196			   (band == NL80211_BAND_5GHZ) ? '5' : '2',
 5197			   (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
 5198								'4' : '2',
 5199			   (i > TX_PWR_CFG_9_IDX) ?
 5200					(i - TX_PWR_CFG_9_IDX - 1) : i,
 5201			   (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
 5202			   (unsigned long) regs[i]);
 5203}
 5204
 5205static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,
 5206					 struct ieee80211_channel *chan,
 5207					 int power_level)
 5208{
 5209	u32 reg, pwreg;
 5210	u16 eeprom;
 5211	u32 data, gdata;
 5212	u8 t, i;
 5213	enum nl80211_band band = chan->band;
 5214	int delta;
 5215
 5216	/* Warn user if bw_comp is set in EEPROM */
 5217	delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
 5218
 5219	if (delta)
 5220		rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
 5221			    delta);
 5222
 5223	/* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit
 5224	 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor
 5225	 * driver does as well, though it looks kinda wrong.
 5226	 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe
 5227	 * the hardware has a problem handling 0x20, and as the code initially
 5228	 * used a fixed offset between HT20 and HT40 rates they had to work-
 5229	 * around that issue and most likely just forgot about it later on.
 5230	 * Maybe we should use rt2800_get_txpower_bw_comp() here as well,
 5231	 * however, the corresponding EEPROM value is not respected by the
 5232	 * vendor driver, so maybe this is rather being taken care of the
 5233	 * TXALC and the driver doesn't need to handle it...?
 5234	 * Though this is all very awkward, just do as they did, as that's what
 5235	 * board vendors expected when they populated the EEPROM...
 5236	 */
 5237	for (i = 0; i < 5; i++) {
 5238		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
 5239						       EEPROM_TXPOWER_BYRATE,
 5240						       i * 2);
 5241
 5242		data = eeprom;
 5243
 5244		t = eeprom & 0x3f;
 5245		if (t == 32)
 5246			t++;
 5247
 5248		gdata = t;
 5249
 5250		t = (eeprom & 0x3f00) >> 8;
 5251		if (t == 32)
 5252			t++;
 5253
 5254		gdata |= (t << 8);
 5255
 5256		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
 5257						       EEPROM_TXPOWER_BYRATE,
 5258						       (i * 2) + 1);
 5259
 5260		t = eeprom & 0x3f;
 5261		if (t == 32)
 5262			t++;
 5263
 5264		gdata |= (t << 16);
 5265
 5266		t = (eeprom & 0x3f00) >> 8;
 5267		if (t == 32)
 5268			t++;
 5269
 5270		gdata |= (t << 24);
 5271		data |= (eeprom << 16);
 5272
 5273		if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
 5274			/* HT20 */
 5275			if (data != 0xffffffff)
 5276				rt2800_register_write(rt2x00dev,
 5277						      TX_PWR_CFG_0 + (i * 4),
 5278						      data);
 5279		} else {
 5280			/* HT40 */
 5281			if (gdata != 0xffffffff)
 5282				rt2800_register_write(rt2x00dev,
 5283						      TX_PWR_CFG_0 + (i * 4),
 5284						      gdata);
 5285		}
 5286	}
 5287
 5288	/* Aparently Ralink ran out of space in the BYRATE calibration section
 5289	 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x
 5290	 * registers. As recent 2T chips use 8-bit instead of 4-bit values for
 5291	 * power-offsets more space would be needed. Ralink decided to keep the
 5292	 * EEPROM layout untouched and rather have some shared values covering
 5293	 * multiple bitrates.
 5294	 * Populate the registers not covered by the EEPROM in the same way the
 5295	 * vendor driver does.
 5296	 */
 5297
 5298	/* For OFDM 54MBS use value from OFDM 48MBS */
 5299	pwreg = 0;
 5300	reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1);
 5301	t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS);
 5302	rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t);
 5303
 5304	/* For MCS 7 use value from MCS 6 */
 5305	reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2);
 5306	t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7);
 5307	rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t);
 5308	rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
 5309
 5310	/* For MCS 15 use value from MCS 14 */
 5311	pwreg = 0;
 5312	reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3);
 5313	t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14);
 5314	rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t);
 5315	rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
 5316
 5317	/* For STBC MCS 7 use value from STBC MCS 6 */
 5318	pwreg = 0;
 5319	reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4);
 5320	t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6);
 5321	rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t);
 5322	rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
 5323
 5324	rt2800_config_alc_rt6352(rt2x00dev, chan, power_level);
 5325
 5326	/* TODO: temperature compensation code! */
 5327}
 5328
 5329/*
 5330 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
 5331 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
 5332 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
 5333 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
 5334 * Reference per rate transmit power values are located in the EEPROM at
 5335 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
 5336 * current conditions (i.e. band, bandwidth, temperature, user settings).
 5337 */
 5338static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
 5339					 struct ieee80211_channel *chan,
 5340					 int power_level)
 5341{
 5342	u8 txpower, r1;
 5343	u16 eeprom;
 5344	u32 reg, offset;
 5345	int i, is_rate_b, delta, power_ctrl;
 5346	enum nl80211_band band = chan->band;
 5347
 5348	/*
 5349	 * Calculate HT40 compensation. For 40MHz we need to add or subtract
 5350	 * value read from EEPROM (different for 2GHz and for 5GHz).
 5351	 */
 5352	delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
 5353
 5354	/*
 5355	 * Calculate temperature compensation. Depends on measurement of current
 5356	 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
 5357	 * to temperature or maybe other factors) is smaller or bigger than
 5358	 * expected. We adjust it, based on TSSI reference and boundaries values
 5359	 * provided in EEPROM.
 5360	 */
 5361	switch (rt2x00dev->chip.rt) {
 5362	case RT2860:
 5363	case RT2872:
 5364	case RT2883:
 5365	case RT3070:
 5366	case RT3071:
 5367	case RT3090:
 5368	case RT3572:
 5369		delta += rt2800_get_gain_calibration_delta(rt2x00dev);
 5370		break;
 5371	default:
 5372		/* TODO: temperature compensation code for other chips. */
 5373		break;
 5374	}
 5375
 5376	/*
 5377	 * Decrease power according to user settings, on devices with unknown
 5378	 * maximum tx power. For other devices we take user power_level into
 5379	 * consideration on rt2800_compensate_txpower().
 5380	 */
 5381	delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
 5382					      chan->max_power);
 5383
 5384	/*
 5385	 * BBP_R1 controls TX power for all rates, it allow to set the following
 5386	 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
 5387	 *
 5388	 * TODO: we do not use +6 dBm option to do not increase power beyond
 5389	 * regulatory limit, however this could be utilized for devices with
 5390	 * CAPABILITY_POWER_LIMIT.
 5391	 */
 5392	if (delta <= -12) {
 5393		power_ctrl = 2;
 5394		delta += 12;
 5395	} else if (delta <= -6) {
 5396		power_ctrl = 1;
 5397		delta += 6;
 5398	} else {
 5399		power_ctrl = 0;
 5400	}
 5401	r1 = rt2800_bbp_read(rt2x00dev, 1);
 5402	rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
 5403	rt2800_bbp_write(rt2x00dev, 1, r1);
 5404
 5405	offset = TX_PWR_CFG_0;
 5406
 5407	for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
 5408		/* just to be safe */
 5409		if (offset > TX_PWR_CFG_4)
 5410			break;
 5411
 5412		reg = rt2800_register_read(rt2x00dev, offset);
 5413
 5414		/* read the next four txpower values */
 5415		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
 5416						       EEPROM_TXPOWER_BYRATE,
 5417						       i);
 5418
 5419		is_rate_b = i ? 0 : 1;
 5420		/*
 5421		 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
 5422		 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
 5423		 * TX_PWR_CFG_4: unknown
 5424		 */
 5425		txpower = rt2x00_get_field16(eeprom,
 5426					     EEPROM_TXPOWER_BYRATE_RATE0);
 5427		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
 5428					     power_level, txpower, delta);
 5429		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
 5430
 5431		/*
 5432		 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
 5433		 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
 5434		 * TX_PWR_CFG_4: unknown
 5435		 */
 5436		txpower = rt2x00_get_field16(eeprom,
 5437					     EEPROM_TXPOWER_BYRATE_RATE1);
 5438		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
 5439					     power_level, txpower, delta);
 5440		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
 5441
 5442		/*
 5443		 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
 5444		 * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
 5445		 * TX_PWR_CFG_4: unknown
 5446		 */
 5447		txpower = rt2x00_get_field16(eeprom,
 5448					     EEPROM_TXPOWER_BYRATE_RATE2);
 5449		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
 5450					     power_level, txpower, delta);
 5451		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
 5452
 5453		/*
 5454		 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
 5455		 * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
 5456		 * TX_PWR_CFG_4: unknown
 5457		 */
 5458		txpower = rt2x00_get_field16(eeprom,
 5459					     EEPROM_TXPOWER_BYRATE_RATE3);
 5460		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
 5461					     power_level, txpower, delta);
 5462		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
 5463
 5464		/* read the next four txpower values */
 5465		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
 5466						       EEPROM_TXPOWER_BYRATE,
 5467						       i + 1);
 5468
 5469		is_rate_b = 0;
 5470		/*
 5471		 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
 5472		 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
 5473		 * TX_PWR_CFG_4: unknown
 5474		 */
 5475		txpower = rt2x00_get_field16(eeprom,
 5476					     EEPROM_TXPOWER_BYRATE_RATE0);
 5477		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
 5478					     power_level, txpower, delta);
 5479		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
 5480
 5481		/*
 5482		 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
 5483		 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
 5484		 * TX_PWR_CFG_4: unknown
 5485		 */
 5486		txpower = rt2x00_get_field16(eeprom,
 5487					     EEPROM_TXPOWER_BYRATE_RATE1);
 5488		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
 5489					     power_level, txpower, delta);
 5490		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
 5491
 5492		/*
 5493		 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
 5494		 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
 5495		 * TX_PWR_CFG_4: unknown
 5496		 */
 5497		txpower = rt2x00_get_field16(eeprom,
 5498					     EEPROM_TXPOWER_BYRATE_RATE2);
 5499		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
 5500					     power_level, txpower, delta);
 5501		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
 5502
 5503		/*
 5504		 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
 5505		 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
 5506		 * TX_PWR_CFG_4: unknown
 5507		 */
 5508		txpower = rt2x00_get_field16(eeprom,
 5509					     EEPROM_TXPOWER_BYRATE_RATE3);
 5510		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
 5511					     power_level, txpower, delta);
 5512		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
 5513
 5514		rt2800_register_write(rt2x00dev, offset, reg);
 5515
 5516		/* next TX_PWR_CFG register */
 5517		offset += 4;
 5518	}
 5519}
 5520
 5521static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
 5522				  struct ieee80211_channel *chan,
 5523				  int power_level)
 5524{
 5525	if (rt2x00_rt(rt2x00dev, RT3593) ||
 5526	    rt2x00_rt(rt2x00dev, RT3883))
 5527		rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
 5528	else if (rt2x00_rt(rt2x00dev, RT6352))
 5529		rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
 5530	else
 5531		rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
 5532}
 5533
 5534void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
 5535{
 5536	rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
 5537			      rt2x00dev->tx_power);
 5538}
 5539EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
 5540
 5541void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
 5542{
 5543	u32	tx_pin;
 5544	u8	rfcsr;
 5545	unsigned long min_sleep = 0;
 5546
 5547	/*
 5548	 * A voltage-controlled oscillator(VCO) is an electronic oscillator
 5549	 * designed to be controlled in oscillation frequency by a voltage
 5550	 * input. Maybe the temperature will affect the frequency of
 5551	 * oscillation to be shifted. The VCO calibration will be called
 5552	 * periodically to adjust the frequency to be precision.
 5553	*/
 5554
 5555	tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
 5556	tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
 5557	rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 5558
 5559	switch (rt2x00dev->chip.rf) {
 5560	case RF2020:
 5561	case RF3020:
 5562	case RF3021:
 5563	case RF3022:
 5564	case RF3320:
 5565	case RF3052:
 5566		rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
 5567		rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 5568		rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
 5569		break;
 5570	case RF3053:
 5571	case RF3070:
 5572	case RF3290:
 5573	case RF3853:
 5574	case RF5350:
 5575	case RF5360:
 5576	case RF5362:
 5577	case RF5370:
 5578	case RF5372:
 5579	case RF5390:
 5580	case RF5392:
 5581	case RF5592:
 5582		rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
 5583		rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
 5584		rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
 5585		min_sleep = 1000;
 5586		break;
 5587	case RF7620:
 5588		rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
 5589		rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
 5590		rfcsr = rt2800_rfcsr_read(rt2x00dev, 4);
 5591		rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1);
 5592		rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
 5593		min_sleep = 2000;
 5594		break;
 5595	default:
 5596		WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration",
 5597			  rt2x00dev->chip.rf);
 5598		return;
 5599	}
 5600
 5601	if (min_sleep > 0)
 5602		usleep_range(min_sleep, min_sleep * 2);
 5603
 5604	tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
 5605	if (rt2x00dev->rf_channel <= 14) {
 5606		switch (rt2x00dev->default_ant.tx_chain_num) {
 5607		case 3:
 5608			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
 5609			fallthrough;
 5610		case 2:
 5611			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 5612			fallthrough;
 5613		case 1:
 5614		default:
 5615			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
 5616			break;
 5617		}
 5618	} else {
 5619		switch (rt2x00dev->default_ant.tx_chain_num) {
 5620		case 3:
 5621			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
 5622			fallthrough;
 5623		case 2:
 5624			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 5625			fallthrough;
 5626		case 1:
 5627		default:
 5628			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
 5629			break;
 5630		}
 5631	}
 5632	rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 5633}
 5634EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
 5635
 5636static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 5637				      struct rt2x00lib_conf *libconf)
 5638{
 5639	u32 reg;
 5640
 5641	reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
 5642	rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 5643			   libconf->conf->short_frame_max_tx_count);
 5644	rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 5645			   libconf->conf->long_frame_max_tx_count);
 5646	rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
 5647}
 5648
 5649static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
 5650			     struct rt2x00lib_conf *libconf)
 5651{
 5652	enum dev_state state =
 5653	    (libconf->conf->flags & IEEE80211_CONF_PS) ?
 5654		STATE_SLEEP : STATE_AWAKE;
 5655	u32 reg;
 5656
 5657	if (state == STATE_SLEEP) {
 5658		rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
 5659
 5660		reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
 5661		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
 5662		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
 5663				   libconf->conf->listen_interval - 1);
 5664		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
 5665		rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
 5666
 5667		rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 5668	} else {
 5669		reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
 5670		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
 5671		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
 5672		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
 5673		rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
 5674
 5675		rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 5676	}
 5677}
 5678
 5679void rt2800_config(struct rt2x00_dev *rt2x00dev,
 5680		   struct rt2x00lib_conf *libconf,
 5681		   const unsigned int flags)
 5682{
 5683	/* Always recalculate LNA gain before changing configuration */
 5684	rt2800_config_lna_gain(rt2x00dev, libconf);
 5685
 5686	if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
 5687		/*
 5688		 * To provide correct survey data for survey-based ACS algorithm
 5689		 * we have to save survey data for current channel before switching.
 5690		 */
 5691		rt2800_update_survey(rt2x00dev);
 5692
 5693		rt2800_config_channel(rt2x00dev, libconf->conf,
 5694				      &libconf->rf, &libconf->channel);
 5695		rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
 5696				      libconf->conf->power_level);
 5697	}
 5698	if (flags & IEEE80211_CONF_CHANGE_POWER)
 5699		rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
 5700				      libconf->conf->power_level);
 5701	if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 5702		rt2800_config_retry_limit(rt2x00dev, libconf);
 5703	if (flags & IEEE80211_CONF_CHANGE_PS)
 5704		rt2800_config_ps(rt2x00dev, libconf);
 5705}
 5706EXPORT_SYMBOL_GPL(rt2800_config);
 5707
 5708/*
 5709 * Link tuning
 5710 */
 5711void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
 5712{
 5713	u32 reg;
 5714
 5715	/*
 5716	 * Update FCS error count from register.
 5717	 */
 5718	reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
 5719	qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
 5720}
 5721EXPORT_SYMBOL_GPL(rt2800_link_stats);
 5722
 5723static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
 5724{
 5725	u8 vgc;
 5726
 5727	if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
 5728		if (rt2x00_rt(rt2x00dev, RT3070) ||
 5729		    rt2x00_rt(rt2x00dev, RT3071) ||
 5730		    rt2x00_rt(rt2x00dev, RT3090) ||
 5731		    rt2x00_rt(rt2x00dev, RT3290) ||
 5732		    rt2x00_rt(rt2x00dev, RT3390) ||
 5733		    rt2x00_rt(rt2x00dev, RT3572) ||
 5734		    rt2x00_rt(rt2x00dev, RT3593) ||
 5735		    rt2x00_rt(rt2x00dev, RT5390) ||
 5736		    rt2x00_rt(rt2x00dev, RT5392) ||
 5737		    rt2x00_rt(rt2x00dev, RT5592) ||
 5738		    rt2x00_rt(rt2x00dev, RT6352))
 5739			vgc = 0x1c + (2 * rt2x00dev->lna_gain);
 5740		else
 5741			vgc = 0x2e + rt2x00dev->lna_gain;
 5742	} else { /* 5GHZ band */
 5743		if (rt2x00_rt(rt2x00dev, RT3593) ||
 5744		    rt2x00_rt(rt2x00dev, RT3883))
 5745			vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
 5746		else if (rt2x00_rt(rt2x00dev, RT5592))
 5747			vgc = 0x24 + (2 * rt2x00dev->lna_gain);
 5748		else {
 5749			if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
 5750				vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
 5751			else
 5752				vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
 5753		}
 5754	}
 5755
 5756	return vgc;
 5757}
 5758
 5759static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
 5760				  struct link_qual *qual, u8 vgc_level)
 5761{
 5762	if (qual->vgc_level != vgc_level) {
 5763		if (rt2x00_rt(rt2x00dev, RT3572) ||
 5764		    rt2x00_rt(rt2x00dev, RT3593) ||
 5765		    rt2x00_rt(rt2x00dev, RT3883) ||
 5766		    rt2x00_rt(rt2x00dev, RT6352)) {
 5767			rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
 5768						       vgc_level);
 5769		} else if (rt2x00_rt(rt2x00dev, RT5592)) {
 5770			rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
 5771			rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
 5772		} else {
 5773			rt2800_bbp_write(rt2x00dev, 66, vgc_level);
 5774		}
 5775
 5776		qual->vgc_level = vgc_level;
 5777		qual->vgc_level_reg = vgc_level;
 5778	}
 5779}
 5780
 5781void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
 5782{
 5783	rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
 5784}
 5785EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
 5786
 5787void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
 5788		       const u32 count)
 5789{
 5790	u8 vgc;
 5791
 5792	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
 5793		return;
 5794
 5795	/* When RSSI is better than a certain threshold, increase VGC
 5796	 * with a chip specific value in order to improve the balance
 5797	 * between sensibility and noise isolation.
 5798	 */
 5799
 5800	vgc = rt2800_get_default_vgc(rt2x00dev);
 5801
 5802	switch (rt2x00dev->chip.rt) {
 5803	case RT3572:
 5804	case RT3593:
 5805		if (qual->rssi > -65) {
 5806			if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
 5807				vgc += 0x20;
 5808			else
 5809				vgc += 0x10;
 5810		}
 5811		break;
 5812
 5813	case RT3883:
 5814		if (qual->rssi > -65)
 5815			vgc += 0x10;
 5816		break;
 5817
 5818	case RT5592:
 5819		if (qual->rssi > -65)
 5820			vgc += 0x20;
 5821		break;
 5822
 5823	default:
 5824		if (qual->rssi > -80)
 5825			vgc += 0x10;
 5826		break;
 5827	}
 5828
 5829	rt2800_set_vgc(rt2x00dev, qual, vgc);
 5830}
 5831EXPORT_SYMBOL_GPL(rt2800_link_tuner);
 5832
 5833/*
 5834 * Initialization functions.
 5835 */
 5836static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
 5837{
 5838	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 5839	u32 reg;
 5840	u16 eeprom;
 5841	u8 bbp;
 5842	unsigned int i;
 5843	int ret;
 5844
 5845	rt2800_disable_wpdma(rt2x00dev);
 5846
 5847	ret = rt2800_drv_init_registers(rt2x00dev);
 5848	if (ret)
 5849		return ret;
 5850
 5851	if (rt2x00_rt(rt2x00dev, RT6352)) {
 5852		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x01);
 5853
 5854		bbp = rt2800_bbp_read(rt2x00dev, 21);
 5855		bbp |= 0x01;
 5856		rt2800_bbp_write(rt2x00dev, 21, bbp);
 5857		bbp = rt2800_bbp_read(rt2x00dev, 21);
 5858		bbp &= (~0x01);
 5859		rt2800_bbp_write(rt2x00dev, 21, bbp);
 5860
 5861		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00);
 5862	}
 5863
 5864	rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
 5865	rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 5866
 5867	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
 5868
 5869	reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
 5870	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
 5871	rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
 5872	rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
 5873	rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
 5874	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 5875	rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
 5876	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 5877
 5878	rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
 5879
 5880	reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
 5881	rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
 5882	rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 5883	rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 5884
 5885	if (rt2x00_rt(rt2x00dev, RT3290)) {
 5886		reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
 5887		if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
 5888			rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
 5889			rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 5890		}
 5891
 5892		reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
 5893		if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
 5894			rt2x00_set_field32(&reg, LDO0_EN, 1);
 5895			rt2x00_set_field32(&reg, LDO_BGSEL, 3);
 5896			rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
 5897		}
 5898
 5899		reg = rt2800_register_read(rt2x00dev, OSC_CTRL);
 5900		rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
 5901		rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
 5902		rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
 5903		rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
 5904
 5905		reg = rt2800_register_read(rt2x00dev, COEX_CFG0);
 5906		rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
 5907		rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
 5908
 5909		reg = rt2800_register_read(rt2x00dev, COEX_CFG2);
 5910		rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
 5911		rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
 5912		rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
 5913		rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
 5914		rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
 5915
 5916		reg = rt2800_register_read(rt2x00dev, PLL_CTRL);
 5917		rt2x00_set_field32(&reg, PLL_CONTROL, 1);
 5918		rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
 5919	}
 5920
 5921	if (rt2x00_rt(rt2x00dev, RT3071) ||
 5922	    rt2x00_rt(rt2x00dev, RT3090) ||
 5923	    rt2x00_rt(rt2x00dev, RT3290) ||
 5924	    rt2x00_rt(rt2x00dev, RT3390)) {
 5925
 5926		if (rt2x00_rt(rt2x00dev, RT3290))
 5927			rt2800_register_write(rt2x00dev, TX_SW_CFG0,
 5928					      0x00000404);
 5929		else
 5930			rt2800_register_write(rt2x00dev, TX_SW_CFG0,
 5931					      0x00000400);
 5932
 5933		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
 5934		if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
 5935		    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
 5936		    rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
 5937			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
 5938			if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
 5939				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
 5940						      0x0000002c);
 5941			else
 5942				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
 5943						      0x0000000f);
 5944		} else {
 5945			rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
 5946		}
 5947	} else if (rt2x00_rt(rt2x00dev, RT3070)) {
 5948		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
 5949
 5950		if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
 5951			rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
 5952			rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
 5953		} else {
 5954			rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
 5955			rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
 5956		}
 5957	} else if (rt2800_is_305x_soc(rt2x00dev)) {
 5958		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
 5959		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
 5960		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
 5961	} else if (rt2x00_rt(rt2x00dev, RT3352)) {
 5962		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
 5963		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
 5964		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
 5965	} else if (rt2x00_rt(rt2x00dev, RT3572)) {
 5966		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
 5967		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
 5968	} else if (rt2x00_rt(rt2x00dev, RT3593)) {
 5969		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
 5970		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
 5971		if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
 5972			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
 5973			if (rt2x00_get_field16(eeprom,
 5974					       EEPROM_NIC_CONF1_DAC_TEST))
 5975				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
 5976						      0x0000001f);
 5977			else
 5978				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
 5979						      0x0000000f);
 5980		} else {
 5981			rt2800_register_write(rt2x00dev, TX_SW_CFG2,
 5982					      0x00000000);
 5983		}
 5984	} else if (rt2x00_rt(rt2x00dev, RT3883)) {
 5985		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
 5986		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
 5987		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000);
 5988		rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21);
 5989		rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40);
 5990	} else if (rt2x00_rt(rt2x00dev, RT5390) ||
 5991		   rt2x00_rt(rt2x00dev, RT5392)) {
 5992		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
 5993		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
 5994		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
 5995	} else if (rt2x00_rt(rt2x00dev, RT5592)) {
 5996		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
 5997		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
 5998		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
 5999	} else if (rt2x00_rt(rt2x00dev, RT5350)) {
 6000		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
 6001	} else if (rt2x00_rt(rt2x00dev, RT6352)) {
 6002		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
 6003		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001);
 6004		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
 6005		rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
 6006		rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
 6007		rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
 6008		rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
 6009		rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
 6010		rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
 6011				      0x3630363A);
 6012		rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
 6013				      0x3630363A);
 6014		reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
 6015		rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
 6016		rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
 6017
 6018		rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_20M1S, 0x77754433);
 6019		rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_20M2S, 0x77765543);
 6020		rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_40M1S, 0x77765544);
 6021		rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_40M2S, 0x77765544);
 6022
 6023		rt2800_register_write(rt2x00dev, HT_FBK_TO_LEGACY, 0x1010);
 6024
 6025	} else {
 6026		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
 6027		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
 6028	}
 6029
 6030	reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG);
 6031	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
 6032	rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
 6033	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
 6034	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
 6035	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
 6036	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
 6037	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
 6038	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
 6039	rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
 6040
 6041	reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG);
 6042	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
 6043	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
 6044	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
 6045	rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 6046
 6047	reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
 6048	rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
 6049	if (rt2x00_is_usb(rt2x00dev)) {
 6050		drv_data->max_psdu = 3;
 6051	} else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
 6052		   rt2x00_rt(rt2x00dev, RT2883) ||
 6053		   rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) {
 6054		drv_data->max_psdu = 2;
 6055	} else {
 6056		drv_data->max_psdu = 1;
 6057	}
 6058	rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu);
 6059	rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 10);
 6060	rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 10);
 6061	rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
 6062
 6063	reg = rt2800_register_read(rt2x00dev, LED_CFG);
 6064	rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
 6065	rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
 6066	rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 6067	rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 6068	rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
 6069	rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 6070	rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 6071	rt2800_register_write(rt2x00dev, LED_CFG, reg);
 6072
 6073	rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
 6074
 6075	reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
 6076	rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 2);
 6077	rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 2);
 6078	rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
 6079	rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
 6080	rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
 6081	rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
 6082	rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
 6083
 6084	reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
 6085	rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
 6086	rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
 6087	rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 1);
 6088	rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
 6089	rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 0);
 6090	rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
 6091	rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
 6092	rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 6093
 6094	reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
 6095	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
 6096	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
 6097	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
 6098	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
 6099	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
 6100	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
 6101	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
 6102	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
 6103	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
 6104	rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 0);
 6105	rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
 6106
 6107	reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
 6108	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
 6109	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
 6110	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
 6111	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
 6112	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
 6113	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
 6114	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
 6115	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
 6116	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
 6117	rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 0);
 6118	rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 6119
 6120	reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
 6121	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
 6122	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 1);
 6123	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
 6124	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
 6125	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
 6126	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
 6127	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
 6128	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
 6129	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
 6130	rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
 6131	rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
 6132
 6133	reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
 6134	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
 6135	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 1);
 6136	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
 6137	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
 6138	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
 6139	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
 6140	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
 6141	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
 6142	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
 6143	rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
 6144	rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
 6145
 6146	reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
 6147	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
 6148	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 1);
 6149	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
 6150	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
 6151	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
 6152	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
 6153	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
 6154	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
 6155	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
 6156	rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
 6157	rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
 6158
 6159	reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
 6160	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
 6161	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 1);
 6162	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
 6163	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
 6164	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
 6165	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
 6166	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
 6167	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
 6168	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
 6169	rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
 6170	rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
 6171
 6172	if (rt2x00_is_usb(rt2x00dev)) {
 6173		rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
 6174
 6175		reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
 6176		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 6177		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 6178		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 6179		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 6180		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
 6181		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
 6182		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
 6183		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
 6184		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
 6185		rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 6186	}
 6187
 6188	/*
 6189	 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
 6190	 * although it is reserved.
 6191	 */
 6192	reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG);
 6193	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
 6194	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
 6195	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
 6196	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
 6197	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
 6198	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
 6199	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
 6200	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
 6201	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
 6202	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
 6203	rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
 6204
 6205	reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
 6206	rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
 6207
 6208	if (rt2x00_rt(rt2x00dev, RT3883)) {
 6209		rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008);
 6210		rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413);
 6211	}
 6212
 6213	reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
 6214	rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7);
 6215	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
 6216			   IEEE80211_MAX_RTS_THRESHOLD);
 6217	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 1);
 6218	rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
 6219
 6220	rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
 6221
 6222	/*
 6223	 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
 6224	 * time should be set to 16. However, the original Ralink driver uses
 6225	 * 16 for both and indeed using a value of 10 for CCK SIFS results in
 6226	 * connection problems with 11g + CTS protection. Hence, use the same
 6227	 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
 6228	 */
 6229	reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
 6230	rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
 6231	rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
 6232	rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 6233	rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
 6234	rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 6235	rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 6236
 6237	rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
 6238
 6239	/*
 6240	 * ASIC will keep garbage value after boot, clear encryption keys.
 6241	 */
 6242	for (i = 0; i < 4; i++)
 6243		rt2800_register_write(rt2x00dev, SHARED_KEY_MODE_ENTRY(i), 0);
 6244
 6245	for (i = 0; i < 256; i++) {
 6246		rt2800_config_wcid(rt2x00dev, NULL, i);
 6247		rt2800_delete_wcid_attr(rt2x00dev, i);
 6248	}
 6249
 6250	/*
 6251	 * Clear encryption initialization vectors on start, but keep them
 6252	 * for watchdog reset. Otherwise we will have wrong IVs and not be
 6253	 * able to keep connections after reset.
 6254	 */
 6255	if (!test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags))
 6256		for (i = 0; i < 256; i++)
 6257			rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
 6258
 6259	/*
 6260	 * Clear all beacons
 6261	 */
 6262	for (i = 0; i < 8; i++)
 6263		rt2800_clear_beacon_register(rt2x00dev, i);
 6264
 6265	if (rt2x00_is_usb(rt2x00dev)) {
 6266		reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
 6267		rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
 6268		rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
 6269	} else if (rt2x00_is_pcie(rt2x00dev)) {
 6270		reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
 6271		rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
 6272		rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
 6273	} else if (rt2x00_is_soc(rt2x00dev)) {
 6274		struct clk *clk = clk_get_sys("bus", NULL);
 6275		int rate;
 6276
 6277		if (IS_ERR(clk)) {
 6278			clk = clk_get_sys("cpu", NULL);
 6279
 6280			if (IS_ERR(clk)) {
 6281				rate = 125;
 6282			} else {
 6283				rate = clk_get_rate(clk) / 3000000;
 6284				clk_put(clk);
 6285			}
 6286		} else {
 6287			rate = clk_get_rate(clk) / 1000000;
 6288			clk_put(clk);
 6289		}
 6290
 6291		reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
 6292		rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, rate);
 6293		rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
 6294	}
 6295
 6296	reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0);
 6297	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
 6298	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
 6299	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
 6300	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
 6301	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
 6302	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
 6303	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
 6304	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
 6305	rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
 6306
 6307	reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1);
 6308	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
 6309	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
 6310	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
 6311	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
 6312	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
 6313	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
 6314	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
 6315	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
 6316	rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
 6317
 6318	reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0);
 6319	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
 6320	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
 6321	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
 6322	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
 6323	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
 6324	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
 6325	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
 6326	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
 6327	rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
 6328
 6329	reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1);
 6330	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
 6331	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
 6332	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
 6333	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
 6334	rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
 6335
 6336	/*
 6337	 * Do not force the BA window size, we use the TXWI to set it
 6338	 */
 6339	reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE);
 6340	rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
 6341	rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
 6342	rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
 6343
 6344	/*
 6345	 * We must clear the error counters.
 6346	 * These registers are cleared on read,
 6347	 * so we may pass a useless variable to store the value.
 6348	 */
 6349	reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
 6350	reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1);
 6351	reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2);
 6352	reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0);
 6353	reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1);
 6354	reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2);
 6355
 6356	/*
 6357	 * Setup leadtime for pre tbtt interrupt to 6ms
 6358	 */
 6359	reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG);
 6360	rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
 6361	rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
 6362
 6363	/*
 6364	 * Set up channel statistics timer
 6365	 */
 6366	reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG);
 6367	rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
 6368	rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
 6369	rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
 6370	rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
 6371	rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
 6372	rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
 6373
 6374	return 0;
 6375}
 6376
 6377
 6378static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
 6379{
 6380	u8 value;
 6381
 6382	value = rt2800_bbp_read(rt2x00dev, 4);
 6383	rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
 6384	rt2800_bbp_write(rt2x00dev, 4, value);
 6385}
 6386
 6387static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
 6388{
 6389	rt2800_bbp_write(rt2x00dev, 142, 1);
 6390	rt2800_bbp_write(rt2x00dev, 143, 57);
 6391}
 6392
 6393static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
 6394{
 6395	static const u8 glrt_table[] = {
 6396		0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
 6397		0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
 6398		0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
 6399		0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
 6400		0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
 6401		0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
 6402		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
 6403		0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
 6404		0x2E, 0x36, 0x30, 0x6E,					    /* 208 ~ 211 */
 6405	};
 6406	int i;
 6407
 6408	for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
 6409		rt2800_bbp_write(rt2x00dev, 195, 128 + i);
 6410		rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
 6411	}
 6412};
 6413
 6414static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
 6415{
 6416	rt2800_bbp_write(rt2x00dev, 65, 0x2C);
 6417	rt2800_bbp_write(rt2x00dev, 66, 0x38);
 6418	rt2800_bbp_write(rt2x00dev, 68, 0x0B);
 6419	rt2800_bbp_write(rt2x00dev, 69, 0x12);
 6420	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 6421	rt2800_bbp_write(rt2x00dev, 73, 0x10);
 6422	rt2800_bbp_write(rt2x00dev, 81, 0x37);
 6423	rt2800_bbp_write(rt2x00dev, 82, 0x62);
 6424	rt2800_bbp_write(rt2x00dev, 83, 0x6A);
 6425	rt2800_bbp_write(rt2x00dev, 84, 0x99);
 6426	rt2800_bbp_write(rt2x00dev, 86, 0x00);
 6427	rt2800_bbp_write(rt2x00dev, 91, 0x04);
 6428	rt2800_bbp_write(rt2x00dev, 92, 0x00);
 6429	rt2800_bbp_write(rt2x00dev, 103, 0x00);
 6430	rt2800_bbp_write(rt2x00dev, 105, 0x05);
 6431	rt2800_bbp_write(rt2x00dev, 106, 0x35);
 6432}
 6433
 6434static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
 6435{
 6436	u16 eeprom;
 6437	u8 value;
 6438
 6439	value = rt2800_bbp_read(rt2x00dev, 138);
 6440	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
 6441	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
 6442		value |= 0x20;
 6443	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
 6444		value &= ~0x02;
 6445	rt2800_bbp_write(rt2x00dev, 138, value);
 6446}
 6447
 6448static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
 6449{
 6450	rt2800_bbp_write(rt2x00dev, 31, 0x08);
 6451
 6452	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
 6453	rt2800_bbp_write(rt2x00dev, 66, 0x38);
 6454
 6455	rt2800_bbp_write(rt2x00dev, 69, 0x12);
 6456	rt2800_bbp_write(rt2x00dev, 73, 0x10);
 6457
 6458	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 6459
 6460	rt2800_bbp_write(rt2x00dev, 78, 0x0e);
 6461	rt2800_bbp_write(rt2x00dev, 80, 0x08);
 6462
 6463	rt2800_bbp_write(rt2x00dev, 82, 0x62);
 6464
 6465	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
 6466
 6467	rt2800_bbp_write(rt2x00dev, 84, 0x99);
 6468
 6469	rt2800_bbp_write(rt2x00dev, 86, 0x00);
 6470
 6471	rt2800_bbp_write(rt2x00dev, 91, 0x04);
 6472
 6473	rt2800_bbp_write(rt2x00dev, 92, 0x00);
 6474
 6475	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
 6476
 6477	rt2800_bbp_write(rt2x00dev, 105, 0x01);
 6478
 6479	rt2800_bbp_write(rt2x00dev, 106, 0x35);
 6480}
 6481
 6482static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
 6483{
 6484	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
 6485	rt2800_bbp_write(rt2x00dev, 66, 0x38);
 6486
 6487	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
 6488		rt2800_bbp_write(rt2x00dev, 69, 0x16);
 6489		rt2800_bbp_write(rt2x00dev, 73, 0x12);
 6490	} else {
 6491		rt2800_bbp_write(rt2x00dev, 69, 0x12);
 6492		rt2800_bbp_write(rt2x00dev, 73, 0x10);
 6493	}
 6494
 6495	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 6496
 6497	rt2800_bbp_write(rt2x00dev, 81, 0x37);
 6498
 6499	rt2800_bbp_write(rt2x00dev, 82, 0x62);
 6500
 6501	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
 6502
 6503	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
 6504		rt2800_bbp_write(rt2x00dev, 84, 0x19);
 6505	else
 6506		rt2800_bbp_write(rt2x00dev, 84, 0x99);
 6507
 6508	rt2800_bbp_write(rt2x00dev, 86, 0x00);
 6509
 6510	rt2800_bbp_write(rt2x00dev, 91, 0x04);
 6511
 6512	rt2800_bbp_write(rt2x00dev, 92, 0x00);
 6513
 6514	rt2800_bbp_write(rt2x00dev, 103, 0x00);
 6515
 6516	rt2800_bbp_write(rt2x00dev, 105, 0x05);
 6517
 6518	rt2800_bbp_write(rt2x00dev, 106, 0x35);
 6519}
 6520
 6521static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
 6522{
 6523	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
 6524	rt2800_bbp_write(rt2x00dev, 66, 0x38);
 6525
 6526	rt2800_bbp_write(rt2x00dev, 69, 0x12);
 6527	rt2800_bbp_write(rt2x00dev, 73, 0x10);
 6528
 6529	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 6530
 6531	rt2800_bbp_write(rt2x00dev, 79, 0x13);
 6532	rt2800_bbp_write(rt2x00dev, 80, 0x05);
 6533	rt2800_bbp_write(rt2x00dev, 81, 0x33);
 6534
 6535	rt2800_bbp_write(rt2x00dev, 82, 0x62);
 6536
 6537	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
 6538
 6539	rt2800_bbp_write(rt2x00dev, 84, 0x99);
 6540
 6541	rt2800_bbp_write(rt2x00dev, 86, 0x00);
 6542
 6543	rt2800_bbp_write(rt2x00dev, 91, 0x04);
 6544
 6545	rt2800_bbp_write(rt2x00dev, 92, 0x00);
 6546
 6547	if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
 6548	    rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
 6549	    rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
 6550		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
 6551	else
 6552		rt2800_bbp_write(rt2x00dev, 103, 0x00);
 6553
 6554	rt2800_bbp_write(rt2x00dev, 105, 0x05);
 6555
 6556	rt2800_bbp_write(rt2x00dev, 106, 0x35);
 6557
 6558	if (rt2x00_rt(rt2x00dev, RT3071) ||
 6559	    rt2x00_rt(rt2x00dev, RT3090))
 6560		rt2800_disable_unused_dac_adc(rt2x00dev);
 6561}
 6562
 6563static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
 6564{
 6565	u8 value;
 6566
 6567	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
 6568
 6569	rt2800_bbp_write(rt2x00dev, 31, 0x08);
 6570
 6571	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
 6572	rt2800_bbp_write(rt2x00dev, 66, 0x38);
 6573
 6574	rt2800_bbp_write(rt2x00dev, 68, 0x0b);
 6575
 6576	rt2800_bbp_write(rt2x00dev, 69, 0x12);
 6577	rt2800_bbp_write(rt2x00dev, 73, 0x13);
 6578	rt2800_bbp_write(rt2x00dev, 75, 0x46);
 6579	rt2800_bbp_write(rt2x00dev, 76, 0x28);
 6580
 6581	rt2800_bbp_write(rt2x00dev, 77, 0x58);
 6582
 6583	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 6584
 6585	rt2800_bbp_write(rt2x00dev, 74, 0x0b);
 6586	rt2800_bbp_write(rt2x00dev, 79, 0x18);
 6587	rt2800_bbp_write(rt2x00dev, 80, 0x09);
 6588	rt2800_bbp_write(rt2x00dev, 81, 0x33);
 6589
 6590	rt2800_bbp_write(rt2x00dev, 82, 0x62);
 6591
 6592	rt2800_bbp_write(rt2x00dev, 83, 0x7a);
 6593
 6594	rt2800_bbp_write(rt2x00dev, 84, 0x9a);
 6595
 6596	rt2800_bbp_write(rt2x00dev, 86, 0x38);
 6597
 6598	rt2800_bbp_write(rt2x00dev, 91, 0x04);
 6599
 6600	rt2800_bbp_write(rt2x00dev, 92, 0x02);
 6601
 6602	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
 6603
 6604	rt2800_bbp_write(rt2x00dev, 104, 0x92);
 6605
 6606	rt2800_bbp_write(rt2x00dev, 105, 0x1c);
 6607
 6608	rt2800_bbp_write(rt2x00dev, 106, 0x03);
 6609
 6610	rt2800_bbp_write(rt2x00dev, 128, 0x12);
 6611
 6612	rt2800_bbp_write(rt2x00dev, 67, 0x24);
 6613	rt2800_bbp_write(rt2x00dev, 143, 0x04);
 6614	rt2800_bbp_write(rt2x00dev, 142, 0x99);
 6615	rt2800_bbp_write(rt2x00dev, 150, 0x30);
 6616	rt2800_bbp_write(rt2x00dev, 151, 0x2e);
 6617	rt2800_bbp_write(rt2x00dev, 152, 0x20);
 6618	rt2800_bbp_write(rt2x00dev, 153, 0x34);
 6619	rt2800_bbp_write(rt2x00dev, 154, 0x40);
 6620	rt2800_bbp_write(rt2x00dev, 155, 0x3b);
 6621	rt2800_bbp_write(rt2x00dev, 253, 0x04);
 6622
 6623	value = rt2800_bbp_read(rt2x00dev, 47);
 6624	rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
 6625	rt2800_bbp_write(rt2x00dev, 47, value);
 6626
 6627	/* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
 6628	value = rt2800_bbp_read(rt2x00dev, 3);
 6629	rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
 6630	rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
 6631	rt2800_bbp_write(rt2x00dev, 3, value);
 6632}
 6633
 6634static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
 6635{
 6636	rt2800_bbp_write(rt2x00dev, 3, 0x00);
 6637	rt2800_bbp_write(rt2x00dev, 4, 0x50);
 6638
 6639	rt2800_bbp_write(rt2x00dev, 31, 0x08);
 6640
 6641	rt2800_bbp_write(rt2x00dev, 47, 0x48);
 6642
 6643	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
 6644	rt2800_bbp_write(rt2x00dev, 66, 0x38);
 6645
 6646	rt2800_bbp_write(rt2x00dev, 68, 0x0b);
 6647
 6648	rt2800_bbp_write(rt2x00dev, 69, 0x12);
 6649	rt2800_bbp_write(rt2x00dev, 73, 0x13);
 6650	rt2800_bbp_write(rt2x00dev, 75, 0x46);
 6651	rt2800_bbp_write(rt2x00dev, 76, 0x28);
 6652
 6653	rt2800_bbp_write(rt2x00dev, 77, 0x59);
 6654
 6655	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 6656
 6657	rt2800_bbp_write(rt2x00dev, 78, 0x0e);
 6658	rt2800_bbp_write(rt2x00dev, 80, 0x08);
 6659	rt2800_bbp_write(rt2x00dev, 81, 0x37);
 6660
 6661	rt2800_bbp_write(rt2x00dev, 82, 0x62);
 6662
 6663	if (rt2x00_rt(rt2x00dev, RT5350)) {
 6664		rt2800_bbp_write(rt2x00dev, 83, 0x7a);
 6665		rt2800_bbp_write(rt2x00dev, 84, 0x9a);
 6666	} else {
 6667		rt2800_bbp_write(rt2x00dev, 83, 0x6a);
 6668		rt2800_bbp_write(rt2x00dev, 84, 0x99);
 6669	}
 6670
 6671	rt2800_bbp_write(rt2x00dev, 86, 0x38);
 6672
 6673	rt2800_bbp_write(rt2x00dev, 88, 0x90);
 6674
 6675	rt2800_bbp_write(rt2x00dev, 91, 0x04);
 6676
 6677	rt2800_bbp_write(rt2x00dev, 92, 0x02);
 6678
 6679	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
 6680
 6681	rt2800_bbp_write(rt2x00dev, 104, 0x92);
 6682
 6683	if (rt2x00_rt(rt2x00dev, RT5350)) {
 6684		rt2800_bbp_write(rt2x00dev, 105, 0x3c);
 6685		rt2800_bbp_write(rt2x00dev, 106, 0x03);
 6686	} else {
 6687		rt2800_bbp_write(rt2x00dev, 105, 0x34);
 6688		rt2800_bbp_write(rt2x00dev, 106, 0x05);
 6689	}
 6690
 6691	rt2800_bbp_write(rt2x00dev, 120, 0x50);
 6692
 6693	rt2800_bbp_write(rt2x00dev, 137, 0x0f);
 6694
 6695	rt2800_bbp_write(rt2x00dev, 163, 0xbd);
 6696	/* Set ITxBF timeout to 0x9c40=1000msec */
 6697	rt2800_bbp_write(rt2x00dev, 179, 0x02);
 6698	rt2800_bbp_write(rt2x00dev, 180, 0x00);
 6699	rt2800_bbp_write(rt2x00dev, 182, 0x40);
 6700	rt2800_bbp_write(rt2x00dev, 180, 0x01);
 6701	rt2800_bbp_write(rt2x00dev, 182, 0x9c);
 6702	rt2800_bbp_write(rt2x00dev, 179, 0x00);
 6703	/* Reprogram the inband interface to put right values in RXWI */
 6704	rt2800_bbp_write(rt2x00dev, 142, 0x04);
 6705	rt2800_bbp_write(rt2x00dev, 143, 0x3b);
 6706	rt2800_bbp_write(rt2x00dev, 142, 0x06);
 6707	rt2800_bbp_write(rt2x00dev, 143, 0xa0);
 6708	rt2800_bbp_write(rt2x00dev, 142, 0x07);
 6709	rt2800_bbp_write(rt2x00dev, 143, 0xa1);
 6710	rt2800_bbp_write(rt2x00dev, 142, 0x08);
 6711	rt2800_bbp_write(rt2x00dev, 143, 0xa2);
 6712
 6713	rt2800_bbp_write(rt2x00dev, 148, 0xc8);
 6714
 6715	if (rt2x00_rt(rt2x00dev, RT5350)) {
 6716		/* Antenna Software OFDM */
 6717		rt2800_bbp_write(rt2x00dev, 150, 0x40);
 6718		/* Antenna Software CCK */
 6719		rt2800_bbp_write(rt2x00dev, 151, 0x30);
 6720		rt2800_bbp_write(rt2x00dev, 152, 0xa3);
 6721		/* Clear previously selected antenna */
 6722		rt2800_bbp_write(rt2x00dev, 154, 0);
 6723	}
 6724}
 6725
 6726static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
 6727{
 6728	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
 6729	rt2800_bbp_write(rt2x00dev, 66, 0x38);
 6730
 6731	rt2800_bbp_write(rt2x00dev, 69, 0x12);
 6732	rt2800_bbp_write(rt2x00dev, 73, 0x10);
 6733
 6734	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 6735
 6736	rt2800_bbp_write(rt2x00dev, 79, 0x13);
 6737	rt2800_bbp_write(rt2x00dev, 80, 0x05);
 6738	rt2800_bbp_write(rt2x00dev, 81, 0x33);
 6739
 6740	rt2800_bbp_write(rt2x00dev, 82, 0x62);
 6741
 6742	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
 6743
 6744	rt2800_bbp_write(rt2x00dev, 84, 0x99);
 6745
 6746	rt2800_bbp_write(rt2x00dev, 86, 0x00);
 6747
 6748	rt2800_bbp_write(rt2x00dev, 91, 0x04);
 6749
 6750	rt2800_bbp_write(rt2x00dev, 92, 0x00);
 6751
 6752	if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
 6753		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
 6754	else
 6755		rt2800_bbp_write(rt2x00dev, 103, 0x00);
 6756
 6757	rt2800_bbp_write(rt2x00dev, 105, 0x05);
 6758
 6759	rt2800_bbp_write(rt2x00dev, 106, 0x35);
 6760
 6761	rt2800_disable_unused_dac_adc(rt2x00dev);
 6762}
 6763
 6764static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
 6765{
 6766	rt2800_bbp_write(rt2x00dev, 31, 0x08);
 6767
 6768	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
 6769	rt2800_bbp_write(rt2x00dev, 66, 0x38);
 6770
 6771	rt2800_bbp_write(rt2x00dev, 69, 0x12);
 6772	rt2800_bbp_write(rt2x00dev, 73, 0x10);
 6773
 6774	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 6775
 6776	rt2800_bbp_write(rt2x00dev, 79, 0x13);
 6777	rt2800_bbp_write(rt2x00dev, 80, 0x05);
 6778	rt2800_bbp_write(rt2x00dev, 81, 0x33);
 6779
 6780	rt2800_bbp_write(rt2x00dev, 82, 0x62);
 6781
 6782	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
 6783
 6784	rt2800_bbp_write(rt2x00dev, 84, 0x99);
 6785
 6786	rt2800_bbp_write(rt2x00dev, 86, 0x00);
 6787
 6788	rt2800_bbp_write(rt2x00dev, 91, 0x04);
 6789
 6790	rt2800_bbp_write(rt2x00dev, 92, 0x00);
 6791
 6792	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
 6793
 6794	rt2800_bbp_write(rt2x00dev, 105, 0x05);
 6795
 6796	rt2800_bbp_write(rt2x00dev, 106, 0x35);
 6797
 6798	rt2800_disable_unused_dac_adc(rt2x00dev);
 6799}
 6800
 6801static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
 6802{
 6803	rt2800_init_bbp_early(rt2x00dev);
 6804
 6805	rt2800_bbp_write(rt2x00dev, 79, 0x13);
 6806	rt2800_bbp_write(rt2x00dev, 80, 0x05);
 6807	rt2800_bbp_write(rt2x00dev, 81, 0x33);
 6808	rt2800_bbp_write(rt2x00dev, 137, 0x0f);
 6809
 6810	rt2800_bbp_write(rt2x00dev, 84, 0x19);
 6811
 6812	/* Enable DC filter */
 6813	if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
 6814		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
 6815}
 6816
 6817static void rt2800_init_bbp_3883(struct rt2x00_dev *rt2x00dev)
 6818{
 6819	rt2800_init_bbp_early(rt2x00dev);
 6820
 6821	rt2800_bbp_write(rt2x00dev, 4, 0x50);
 6822	rt2800_bbp_write(rt2x00dev, 47, 0x48);
 6823
 6824	rt2800_bbp_write(rt2x00dev, 86, 0x46);
 6825	rt2800_bbp_write(rt2x00dev, 88, 0x90);
 6826
 6827	rt2800_bbp_write(rt2x00dev, 92, 0x02);
 6828
 6829	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
 6830	rt2800_bbp_write(rt2x00dev, 104, 0x92);
 6831	rt2800_bbp_write(rt2x00dev, 105, 0x34);
 6832	rt2800_bbp_write(rt2x00dev, 106, 0x12);
 6833	rt2800_bbp_write(rt2x00dev, 120, 0x50);
 6834	rt2800_bbp_write(rt2x00dev, 137, 0x0f);
 6835	rt2800_bbp_write(rt2x00dev, 163, 0x9d);
 6836
 6837	/* Set ITxBF timeout to 0x9C40=1000msec */
 6838	rt2800_bbp_write(rt2x00dev, 179, 0x02);
 6839	rt2800_bbp_write(rt2x00dev, 180, 0x00);
 6840	rt2800_bbp_write(rt2x00dev, 182, 0x40);
 6841	rt2800_bbp_write(rt2x00dev, 180, 0x01);
 6842	rt2800_bbp_write(rt2x00dev, 182, 0x9c);
 6843
 6844	rt2800_bbp_write(rt2x00dev, 179, 0x00);
 6845
 6846	/* Reprogram the inband interface to put right values in RXWI */
 6847	rt2800_bbp_write(rt2x00dev, 142, 0x04);
 6848	rt2800_bbp_write(rt2x00dev, 143, 0x3b);
 6849	rt2800_bbp_write(rt2x00dev, 142, 0x06);
 6850	rt2800_bbp_write(rt2x00dev, 143, 0xa0);
 6851	rt2800_bbp_write(rt2x00dev, 142, 0x07);
 6852	rt2800_bbp_write(rt2x00dev, 143, 0xa1);
 6853	rt2800_bbp_write(rt2x00dev, 142, 0x08);
 6854	rt2800_bbp_write(rt2x00dev, 143, 0xa2);
 6855	rt2800_bbp_write(rt2x00dev, 148, 0xc8);
 6856}
 6857
 6858static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
 6859{
 6860	int ant, div_mode;
 6861	u16 eeprom;
 6862	u8 value;
 6863
 6864	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
 6865
 6866	rt2800_bbp_write(rt2x00dev, 31, 0x08);
 6867
 6868	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
 6869	rt2800_bbp_write(rt2x00dev, 66, 0x38);
 6870
 6871	rt2800_bbp_write(rt2x00dev, 68, 0x0b);
 6872
 6873	rt2800_bbp_write(rt2x00dev, 69, 0x12);
 6874	rt2800_bbp_write(rt2x00dev, 73, 0x13);
 6875	rt2800_bbp_write(rt2x00dev, 75, 0x46);
 6876	rt2800_bbp_write(rt2x00dev, 76, 0x28);
 6877
 6878	rt2800_bbp_write(rt2x00dev, 77, 0x59);
 6879
 6880	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 6881
 6882	rt2800_bbp_write(rt2x00dev, 79, 0x13);
 6883	rt2800_bbp_write(rt2x00dev, 80, 0x05);
 6884	rt2800_bbp_write(rt2x00dev, 81, 0x33);
 6885
 6886	rt2800_bbp_write(rt2x00dev, 82, 0x62);
 6887
 6888	rt2800_bbp_write(rt2x00dev, 83, 0x7a);
 6889
 6890	rt2800_bbp_write(rt2x00dev, 84, 0x9a);
 6891
 6892	rt2800_bbp_write(rt2x00dev, 86, 0x38);
 6893
 6894	if (rt2x00_rt(rt2x00dev, RT5392))
 6895		rt2800_bbp_write(rt2x00dev, 88, 0x90);
 6896
 6897	rt2800_bbp_write(rt2x00dev, 91, 0x04);
 6898
 6899	rt2800_bbp_write(rt2x00dev, 92, 0x02);
 6900
 6901	if (rt2x00_rt(rt2x00dev, RT5392)) {
 6902		rt2800_bbp_write(rt2x00dev, 95, 0x9a);
 6903		rt2800_bbp_write(rt2x00dev, 98, 0x12);
 6904	}
 6905
 6906	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
 6907
 6908	rt2800_bbp_write(rt2x00dev, 104, 0x92);
 6909
 6910	rt2800_bbp_write(rt2x00dev, 105, 0x3c);
 6911
 6912	if (rt2x00_rt(rt2x00dev, RT5390))
 6913		rt2800_bbp_write(rt2x00dev, 106, 0x03);
 6914	else if (rt2x00_rt(rt2x00dev, RT5392))
 6915		rt2800_bbp_write(rt2x00dev, 106, 0x12);
 6916	else
 6917		WARN_ON(1);
 6918
 6919	rt2800_bbp_write(rt2x00dev, 128, 0x12);
 6920
 6921	if (rt2x00_rt(rt2x00dev, RT5392)) {
 6922		rt2800_bbp_write(rt2x00dev, 134, 0xd0);
 6923		rt2800_bbp_write(rt2x00dev, 135, 0xf6);
 6924	}
 6925
 6926	rt2800_disable_unused_dac_adc(rt2x00dev);
 6927
 6928	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
 6929	div_mode = rt2x00_get_field16(eeprom,
 6930				      EEPROM_NIC_CONF1_ANT_DIVERSITY);
 6931	ant = (div_mode == 3) ? 1 : 0;
 6932
 6933	/* check if this is a Bluetooth combo card */
 6934	if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
 6935		u32 reg;
 6936
 6937		reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
 6938		rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
 6939		rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
 6940		rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
 6941		rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
 6942		if (ant == 0)
 6943			rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
 6944		else if (ant == 1)
 6945			rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
 6946		rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
 6947	}
 6948
 6949	/* These chips have hardware RX antenna diversity */
 6950	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
 6951	    rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
 6952		rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
 6953		rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
 6954		rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
 6955	}
 6956
 6957	value = rt2800_bbp_read(rt2x00dev, 152);
 6958	if (ant == 0)
 6959		rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
 6960	else
 6961		rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
 6962	rt2800_bbp_write(rt2x00dev, 152, value);
 6963
 6964	rt2800_init_freq_calibration(rt2x00dev);
 6965}
 6966
 6967static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
 6968{
 6969	int ant, div_mode;
 6970	u16 eeprom;
 6971	u8 value;
 6972
 6973	rt2800_init_bbp_early(rt2x00dev);
 6974
 6975	value = rt2800_bbp_read(rt2x00dev, 105);
 6976	rt2x00_set_field8(&value, BBP105_MLD,
 6977			  rt2x00dev->default_ant.rx_chain_num == 2);
 6978	rt2800_bbp_write(rt2x00dev, 105, value);
 6979
 6980	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
 6981
 6982	rt2800_bbp_write(rt2x00dev, 20, 0x06);
 6983	rt2800_bbp_write(rt2x00dev, 31, 0x08);
 6984	rt2800_bbp_write(rt2x00dev, 65, 0x2C);
 6985	rt2800_bbp_write(rt2x00dev, 68, 0xDD);
 6986	rt2800_bbp_write(rt2x00dev, 69, 0x1A);
 6987	rt2800_bbp_write(rt2x00dev, 70, 0x05);
 6988	rt2800_bbp_write(rt2x00dev, 73, 0x13);
 6989	rt2800_bbp_write(rt2x00dev, 74, 0x0F);
 6990	rt2800_bbp_write(rt2x00dev, 75, 0x4F);
 6991	rt2800_bbp_write(rt2x00dev, 76, 0x28);
 6992	rt2800_bbp_write(rt2x00dev, 77, 0x59);
 6993	rt2800_bbp_write(rt2x00dev, 84, 0x9A);
 6994	rt2800_bbp_write(rt2x00dev, 86, 0x38);
 6995	rt2800_bbp_write(rt2x00dev, 88, 0x90);
 6996	rt2800_bbp_write(rt2x00dev, 91, 0x04);
 6997	rt2800_bbp_write(rt2x00dev, 92, 0x02);
 6998	rt2800_bbp_write(rt2x00dev, 95, 0x9a);
 6999	rt2800_bbp_write(rt2x00dev, 98, 0x12);
 7000	rt2800_bbp_write(rt2x00dev, 103, 0xC0);
 7001	rt2800_bbp_write(rt2x00dev, 104, 0x92);
 7002	/* FIXME BBP105 owerwrite */
 7003	rt2800_bbp_write(rt2x00dev, 105, 0x3C);
 7004	rt2800_bbp_write(rt2x00dev, 106, 0x35);
 7005	rt2800_bbp_write(rt2x00dev, 128, 0x12);
 7006	rt2800_bbp_write(rt2x00dev, 134, 0xD0);
 7007	rt2800_bbp_write(rt2x00dev, 135, 0xF6);
 7008	rt2800_bbp_write(rt2x00dev, 137, 0x0F);
 7009
 7010	/* Initialize GLRT (Generalized Likehood Radio Test) */
 7011	rt2800_init_bbp_5592_glrt(rt2x00dev);
 7012
 7013	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
 7014
 7015	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
 7016	div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
 7017	ant = (div_mode == 3) ? 1 : 0;
 7018	value = rt2800_bbp_read(rt2x00dev, 152);
 7019	if (ant == 0) {
 7020		/* Main antenna */
 7021		rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
 7022	} else {
 7023		/* Auxiliary antenna */
 7024		rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
 7025	}
 7026	rt2800_bbp_write(rt2x00dev, 152, value);
 7027
 7028	if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
 7029		value = rt2800_bbp_read(rt2x00dev, 254);
 7030		rt2x00_set_field8(&value, BBP254_BIT7, 1);
 7031		rt2800_bbp_write(rt2x00dev, 254, value);
 7032	}
 7033
 7034	rt2800_init_freq_calibration(rt2x00dev);
 7035
 7036	rt2800_bbp_write(rt2x00dev, 84, 0x19);
 7037	if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
 7038		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
 7039}
 7040
 7041static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
 7042{
 7043	u8 bbp;
 7044
 7045	/* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
 7046	bbp = rt2800_bbp_read(rt2x00dev, 105);
 7047	rt2x00_set_field8(&bbp, BBP105_MLD,
 7048			  rt2x00dev->default_ant.rx_chain_num == 2);
 7049	rt2800_bbp_write(rt2x00dev, 105, bbp);
 7050
 7051	/* Avoid data loss and CRC errors */
 7052	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
 7053
 7054	/* Fix I/Q swap issue */
 7055	bbp = rt2800_bbp_read(rt2x00dev, 1);
 7056	bbp |= 0x04;
 7057	rt2800_bbp_write(rt2x00dev, 1, bbp);
 7058
 7059	/* BBP for G band */
 7060	rt2800_bbp_write(rt2x00dev, 3, 0x08);
 7061	rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
 7062	rt2800_bbp_write(rt2x00dev, 6, 0x08);
 7063	rt2800_bbp_write(rt2x00dev, 14, 0x09);
 7064	rt2800_bbp_write(rt2x00dev, 15, 0xFF);
 7065	rt2800_bbp_write(rt2x00dev, 16, 0x01);
 7066	rt2800_bbp_write(rt2x00dev, 20, 0x06);
 7067	rt2800_bbp_write(rt2x00dev, 21, 0x00);
 7068	rt2800_bbp_write(rt2x00dev, 22, 0x00);
 7069	rt2800_bbp_write(rt2x00dev, 27, 0x00);
 7070	rt2800_bbp_write(rt2x00dev, 28, 0x00);
 7071	rt2800_bbp_write(rt2x00dev, 30, 0x00);
 7072	rt2800_bbp_write(rt2x00dev, 31, 0x48);
 7073	rt2800_bbp_write(rt2x00dev, 47, 0x40);
 7074	rt2800_bbp_write(rt2x00dev, 62, 0x00);
 7075	rt2800_bbp_write(rt2x00dev, 63, 0x00);
 7076	rt2800_bbp_write(rt2x00dev, 64, 0x00);
 7077	rt2800_bbp_write(rt2x00dev, 65, 0x2C);
 7078	rt2800_bbp_write(rt2x00dev, 66, 0x1C);
 7079	rt2800_bbp_write(rt2x00dev, 67, 0x20);
 7080	rt2800_bbp_write(rt2x00dev, 68, 0xDD);
 7081	rt2800_bbp_write(rt2x00dev, 69, 0x10);
 7082	rt2800_bbp_write(rt2x00dev, 70, 0x05);
 7083	rt2800_bbp_write(rt2x00dev, 73, 0x18);
 7084	rt2800_bbp_write(rt2x00dev, 74, 0x0F);
 7085	rt2800_bbp_write(rt2x00dev, 75, 0x60);
 7086	rt2800_bbp_write(rt2x00dev, 76, 0x44);
 7087	rt2800_bbp_write(rt2x00dev, 77, 0x59);
 7088	rt2800_bbp_write(rt2x00dev, 78, 0x1E);
 7089	rt2800_bbp_write(rt2x00dev, 79, 0x1C);
 7090	rt2800_bbp_write(rt2x00dev, 80, 0x0C);
 7091	rt2800_bbp_write(rt2x00dev, 81, 0x3A);
 7092	rt2800_bbp_write(rt2x00dev, 82, 0xB6);
 7093	rt2800_bbp_write(rt2x00dev, 83, 0x9A);
 7094	rt2800_bbp_write(rt2x00dev, 84, 0x9A);
 7095	rt2800_bbp_write(rt2x00dev, 86, 0x38);
 7096	rt2800_bbp_write(rt2x00dev, 88, 0x90);
 7097	rt2800_bbp_write(rt2x00dev, 91, 0x04);
 7098	rt2800_bbp_write(rt2x00dev, 92, 0x02);
 7099	rt2800_bbp_write(rt2x00dev, 95, 0x9A);
 7100	rt2800_bbp_write(rt2x00dev, 96, 0x00);
 7101	rt2800_bbp_write(rt2x00dev, 103, 0xC0);
 7102	rt2800_bbp_write(rt2x00dev, 104, 0x92);
 7103	/* FIXME BBP105 owerwrite */
 7104	rt2800_bbp_write(rt2x00dev, 105, 0x3C);
 7105	rt2800_bbp_write(rt2x00dev, 106, 0x12);
 7106	rt2800_bbp_write(rt2x00dev, 109, 0x00);
 7107	rt2800_bbp_write(rt2x00dev, 134, 0x10);
 7108	rt2800_bbp_write(rt2x00dev, 135, 0xA6);
 7109	rt2800_bbp_write(rt2x00dev, 137, 0x04);
 7110	rt2800_bbp_write(rt2x00dev, 142, 0x30);
 7111	rt2800_bbp_write(rt2x00dev, 143, 0xF7);
 7112	rt2800_bbp_write(rt2x00dev, 160, 0xEC);
 7113	rt2800_bbp_write(rt2x00dev, 161, 0xC4);
 7114	rt2800_bbp_write(rt2x00dev, 162, 0x77);
 7115	rt2800_bbp_write(rt2x00dev, 163, 0xF9);
 7116	rt2800_bbp_write(rt2x00dev, 164, 0x00);
 7117	rt2800_bbp_write(rt2x00dev, 165, 0x00);
 7118	rt2800_bbp_write(rt2x00dev, 186, 0x00);
 7119	rt2800_bbp_write(rt2x00dev, 187, 0x00);
 7120	rt2800_bbp_write(rt2x00dev, 188, 0x00);
 7121	rt2800_bbp_write(rt2x00dev, 186, 0x00);
 7122	rt2800_bbp_write(rt2x00dev, 187, 0x01);
 7123	rt2800_bbp_write(rt2x00dev, 188, 0x00);
 7124	rt2800_bbp_write(rt2x00dev, 189, 0x00);
 7125
 7126	rt2800_bbp_write(rt2x00dev, 91, 0x06);
 7127	rt2800_bbp_write(rt2x00dev, 92, 0x04);
 7128	rt2800_bbp_write(rt2x00dev, 93, 0x54);
 7129	rt2800_bbp_write(rt2x00dev, 99, 0x50);
 7130	rt2800_bbp_write(rt2x00dev, 148, 0x84);
 7131	rt2800_bbp_write(rt2x00dev, 167, 0x80);
 7132	rt2800_bbp_write(rt2x00dev, 178, 0xFF);
 7133	rt2800_bbp_write(rt2x00dev, 106, 0x13);
 7134
 7135	/* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
 7136	rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
 7137	rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
 7138	rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
 7139	rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
 7140	rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
 7141	rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
 7142	rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
 7143	rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
 7144	rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
 7145	rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
 7146	rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
 7147	rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
 7148	rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
 7149	rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
 7150	rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
 7151	rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
 7152	rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
 7153	rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
 7154	rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
 7155	rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
 7156	rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
 7157	rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
 7158	rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
 7159	rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
 7160	rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
 7161	rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
 7162	rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
 7163	rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
 7164	rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
 7165	rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
 7166	rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
 7167	rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
 7168	rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
 7169	rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
 7170	rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
 7171	rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
 7172	rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
 7173	rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
 7174	rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
 7175	rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
 7176	rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
 7177	rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
 7178	rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
 7179	rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
 7180	rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
 7181	rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
 7182	rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
 7183	rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
 7184	rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
 7185	rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
 7186	rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
 7187	rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
 7188	rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
 7189	rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
 7190	rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
 7191	rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
 7192	rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
 7193	rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
 7194	rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
 7195	rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
 7196	rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
 7197	rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
 7198	rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
 7199	rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
 7200	rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
 7201	rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
 7202	rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
 7203	rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
 7204	rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
 7205	rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
 7206	rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
 7207	rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
 7208	rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
 7209	rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
 7210	rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
 7211	rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
 7212	rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
 7213	rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
 7214	rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
 7215	rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
 7216	rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
 7217	rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
 7218	rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
 7219
 7220	/* BBP for G band DCOC function */
 7221	rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
 7222	rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
 7223	rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
 7224	rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
 7225	rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
 7226	rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
 7227	rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
 7228	rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
 7229	rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
 7230	rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
 7231	rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
 7232	rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
 7233	rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
 7234	rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
 7235	rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
 7236	rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
 7237	rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
 7238	rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
 7239	rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
 7240	rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
 7241
 7242	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
 7243
 7244	rt2800_bbp_write(rt2x00dev, 84, 0x19);
 7245}
 7246
 7247static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
 7248{
 7249	unsigned int i;
 7250	u16 eeprom;
 7251	u8 reg_id;
 7252	u8 value;
 7253
 7254	if (rt2800_is_305x_soc(rt2x00dev))
 7255		rt2800_init_bbp_305x_soc(rt2x00dev);
 7256
 7257	switch (rt2x00dev->chip.rt) {
 7258	case RT2860:
 7259	case RT2872:
 7260	case RT2883:
 7261		rt2800_init_bbp_28xx(rt2x00dev);
 7262		break;
 7263	case RT3070:
 7264	case RT3071:
 7265	case RT3090:
 7266		rt2800_init_bbp_30xx(rt2x00dev);
 7267		break;
 7268	case RT3290:
 7269		rt2800_init_bbp_3290(rt2x00dev);
 7270		break;
 7271	case RT3352:
 7272	case RT5350:
 7273		rt2800_init_bbp_3352(rt2x00dev);
 7274		break;
 7275	case RT3390:
 7276		rt2800_init_bbp_3390(rt2x00dev);
 7277		break;
 7278	case RT3572:
 7279		rt2800_init_bbp_3572(rt2x00dev);
 7280		break;
 7281	case RT3593:
 7282		rt2800_init_bbp_3593(rt2x00dev);
 7283		return;
 7284	case RT3883:
 7285		rt2800_init_bbp_3883(rt2x00dev);
 7286		return;
 7287	case RT5390:
 7288	case RT5392:
 7289		rt2800_init_bbp_53xx(rt2x00dev);
 7290		break;
 7291	case RT5592:
 7292		rt2800_init_bbp_5592(rt2x00dev);
 7293		return;
 7294	case RT6352:
 7295		rt2800_init_bbp_6352(rt2x00dev);
 7296		break;
 7297	}
 7298
 7299	for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 7300		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
 7301						       EEPROM_BBP_START, i);
 7302
 7303		if (eeprom != 0xffff && eeprom != 0x0000) {
 7304			reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 7305			value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 7306			rt2800_bbp_write(rt2x00dev, reg_id, value);
 7307		}
 7308	}
 7309}
 7310
 7311static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
 7312{
 7313	u32 reg;
 7314
 7315	reg = rt2800_register_read(rt2x00dev, OPT_14_CSR);
 7316	rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
 7317	rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
 7318}
 7319
 7320static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
 7321				u8 filter_target)
 7322{
 7323	unsigned int i;
 7324	u8 bbp;
 7325	u8 rfcsr;
 7326	u8 passband;
 7327	u8 stopband;
 7328	u8 overtuned = 0;
 7329	u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
 7330
 7331	rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
 7332
 7333	bbp = rt2800_bbp_read(rt2x00dev, 4);
 7334	rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
 7335	rt2800_bbp_write(rt2x00dev, 4, bbp);
 7336
 7337	rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
 7338	rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
 7339	rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
 7340
 7341	rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
 7342	rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
 7343	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
 7344
 7345	/*
 7346	 * Set power & frequency of passband test tone
 7347	 */
 7348	rt2800_bbp_write(rt2x00dev, 24, 0);
 7349
 7350	for (i = 0; i < 100; i++) {
 7351		rt2800_bbp_write(rt2x00dev, 25, 0x90);
 7352		msleep(1);
 7353
 7354		passband = rt2800_bbp_read(rt2x00dev, 55);
 7355		if (passband)
 7356			break;
 7357	}
 7358
 7359	/*
 7360	 * Set power & frequency of stopband test tone
 7361	 */
 7362	rt2800_bbp_write(rt2x00dev, 24, 0x06);
 7363
 7364	for (i = 0; i < 100; i++) {
 7365		rt2800_bbp_write(rt2x00dev, 25, 0x90);
 7366		msleep(1);
 7367
 7368		stopband = rt2800_bbp_read(rt2x00dev, 55);
 7369
 7370		if ((passband - stopband) <= filter_target) {
 7371			rfcsr24++;
 7372			overtuned += ((passband - stopband) == filter_target);
 7373		} else
 7374			break;
 7375
 7376		rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
 7377	}
 7378
 7379	rfcsr24 -= !!overtuned;
 7380
 7381	rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
 7382	return rfcsr24;
 7383}
 7384
 7385static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
 7386				       const unsigned int rf_reg)
 7387{
 7388	u8 rfcsr;
 7389
 7390	rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg);
 7391	rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
 7392	rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
 7393	msleep(1);
 7394	rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
 7395	rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
 7396}
 7397
 7398static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
 7399{
 7400	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 7401	u8 filter_tgt_bw20;
 7402	u8 filter_tgt_bw40;
 7403	u8 rfcsr, bbp;
 7404
 7405	/*
 7406	 * TODO: sync filter_tgt values with vendor driver
 7407	 */
 7408	if (rt2x00_rt(rt2x00dev, RT3070)) {
 7409		filter_tgt_bw20 = 0x16;
 7410		filter_tgt_bw40 = 0x19;
 7411	} else {
 7412		filter_tgt_bw20 = 0x13;
 7413		filter_tgt_bw40 = 0x15;
 7414	}
 7415
 7416	drv_data->calibration_bw20 =
 7417		rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
 7418	drv_data->calibration_bw40 =
 7419		rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
 7420
 7421	/*
 7422	 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
 7423	 */
 7424	drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
 7425	drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
 7426
 7427	/*
 7428	 * Set back to initial state
 7429	 */
 7430	rt2800_bbp_write(rt2x00dev, 24, 0);
 7431
 7432	rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
 7433	rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
 7434	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
 7435
 7436	/*
 7437	 * Set BBP back to BW20
 7438	 */
 7439	bbp = rt2800_bbp_read(rt2x00dev, 4);
 7440	rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
 7441	rt2800_bbp_write(rt2x00dev, 4, bbp);
 7442}
 7443
 7444static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
 7445{
 7446	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 7447	u8 min_gain, rfcsr, bbp;
 7448	u16 eeprom;
 7449
 7450	rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
 7451
 7452	rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
 7453	if (rt2x00_rt(rt2x00dev, RT3070) ||
 7454	    rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
 7455	    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
 7456	    rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
 7457		if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
 7458			rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
 7459	}
 7460
 7461	min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
 7462	if (drv_data->txmixer_gain_24g >= min_gain) {
 7463		rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
 7464				  drv_data->txmixer_gain_24g);
 7465	}
 7466
 7467	rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
 7468
 7469	if (rt2x00_rt(rt2x00dev, RT3090)) {
 7470		/*  Turn off unused DAC1 and ADC1 to reduce power consumption */
 7471		bbp = rt2800_bbp_read(rt2x00dev, 138);
 7472		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
 7473		if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
 7474			rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
 7475		if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
 7476			rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
 7477		rt2800_bbp_write(rt2x00dev, 138, bbp);
 7478	}
 7479
 7480	if (rt2x00_rt(rt2x00dev, RT3070)) {
 7481		rfcsr = rt2800_rfcsr_read(rt2x00dev, 27);
 7482		if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
 7483			rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
 7484		else
 7485			rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
 7486		rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
 7487		rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
 7488		rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
 7489		rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
 7490	} else if (rt2x00_rt(rt2x00dev, RT3071) ||
 7491		   rt2x00_rt(rt2x00dev, RT3090) ||
 7492		   rt2x00_rt(rt2x00dev, RT3390)) {
 7493		rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
 7494		rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
 7495		rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
 7496		rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
 7497		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
 7498		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
 7499		rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
 7500
 7501		rfcsr = rt2800_rfcsr_read(rt2x00dev, 15);
 7502		rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
 7503		rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
 7504
 7505		rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
 7506		rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
 7507		rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
 7508
 7509		rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
 7510		rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
 7511		rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
 7512	}
 7513}
 7514
 7515static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
 7516{
 7517	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 7518	u8 rfcsr;
 7519	u8 tx_gain;
 7520
 7521	rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
 7522	rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
 7523	rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
 7524
 7525	rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
 7526	tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
 7527				    RFCSR17_TXMIXER_GAIN);
 7528	rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
 7529	rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
 7530
 7531	rfcsr = rt2800_rfcsr_read(rt2x00dev, 38);
 7532	rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
 7533	rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
 7534
 7535	rfcsr = rt2800_rfcsr_read(rt2x00dev, 39);
 7536	rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
 7537	rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
 7538
 7539	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
 7540	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
 7541	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
 7542	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
 7543
 7544	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
 7545	rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
 7546	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
 7547
 7548	/* TODO: enable stream mode */
 7549}
 7550
 7551static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
 7552{
 7553	u8 reg;
 7554	u16 eeprom;
 7555
 7556	/*  Turn off unused DAC1 and ADC1 to reduce power consumption */
 7557	reg = rt2800_bbp_read(rt2x00dev, 138);
 7558	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
 7559	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
 7560		rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
 7561	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
 7562		rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
 7563	rt2800_bbp_write(rt2x00dev, 138, reg);
 7564
 7565	reg = rt2800_rfcsr_read(rt2x00dev, 38);
 7566	rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
 7567	rt2800_rfcsr_write(rt2x00dev, 38, reg);
 7568
 7569	reg = rt2800_rfcsr_read(rt2x00dev, 39);
 7570	rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
 7571	rt2800_rfcsr_write(rt2x00dev, 39, reg);
 7572
 7573	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
 7574
 7575	reg = rt2800_rfcsr_read(rt2x00dev, 30);
 7576	rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
 7577	rt2800_rfcsr_write(rt2x00dev, 30, reg);
 7578}
 7579
 7580static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
 7581{
 7582	rt2800_rf_init_calibration(rt2x00dev, 30);
 7583
 7584	rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
 7585	rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
 7586	rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
 7587	rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
 7588	rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
 7589	rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
 7590	rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
 7591	rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
 7592	rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
 7593	rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
 7594	rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
 7595	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
 7596	rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
 7597	rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
 7598	rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
 7599	rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
 7600	rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
 7601	rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
 7602	rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
 7603	rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
 7604	rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
 7605	rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
 7606	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
 7607	rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
 7608	rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
 7609	rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
 7610	rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
 7611	rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
 7612	rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
 7613	rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
 7614	rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
 7615	rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
 7616}
 7617
 7618static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
 7619{
 7620	u8 rfcsr;
 7621	u16 eeprom;
 7622	u32 reg;
 7623
 7624	/* XXX vendor driver do this only for 3070 */
 7625	rt2800_rf_init_calibration(rt2x00dev, 30);
 7626
 7627	rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
 7628	rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
 7629	rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
 7630	rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
 7631	rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
 7632	rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
 7633	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
 7634	rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
 7635	rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
 7636	rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
 7637	rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
 7638	rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
 7639	rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
 7640	rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
 7641	rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
 7642	rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
 7643	rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
 7644	rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
 7645	rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
 7646
 7647	if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
 7648		reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
 7649		rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
 7650		rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
 7651		rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
 7652	} else if (rt2x00_rt(rt2x00dev, RT3071) ||
 7653		   rt2x00_rt(rt2x00dev, RT3090)) {
 7654		rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
 7655
 7656		rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
 7657		rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
 7658		rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
 7659
 7660		reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
 7661		rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
 7662		if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
 7663		    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
 7664			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
 7665			if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
 7666				rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
 7667			else
 7668				rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
 7669		}
 7670		rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
 7671
 7672		reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
 7673		rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
 7674		rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
 7675	}
 7676
 7677	rt2800_rx_filter_calibration(rt2x00dev);
 7678
 7679	if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
 7680	    rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
 7681	    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
 7682		rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
 7683
 7684	rt2800_led_open_drain_enable(rt2x00dev);
 7685	rt2800_normal_mode_setup_3xxx(rt2x00dev);
 7686}
 7687
 7688static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
 7689{
 7690	u8 rfcsr;
 7691
 7692	rt2800_rf_init_calibration(rt2x00dev, 2);
 7693
 7694	rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
 7695	rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
 7696	rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
 7697	rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
 7698	rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
 7699	rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
 7700	rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
 7701	rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
 7702	rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
 7703	rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
 7704	rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
 7705	rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
 7706	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
 7707	rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
 7708	rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
 7709	rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
 7710	rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
 7711	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
 7712	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
 7713	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
 7714	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
 7715	rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
 7716	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
 7717	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
 7718	rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
 7719	rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
 7720	rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
 7721	rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
 7722	rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
 7723	rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
 7724	rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
 7725	rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
 7726	rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
 7727	rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
 7728	rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
 7729	rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
 7730	rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
 7731	rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
 7732	rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
 7733	rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
 7734	rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
 7735	rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
 7736	rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
 7737	rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
 7738	rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
 7739	rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
 7740
 7741	rfcsr = rt2800_rfcsr_read(rt2x00dev, 29);
 7742	rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
 7743	rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
 7744
 7745	rt2800_led_open_drain_enable(rt2x00dev);
 7746	rt2800_normal_mode_setup_3xxx(rt2x00dev);
 7747}
 7748
 7749static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
 7750{
 7751	int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0,
 7752				  &rt2x00dev->cap_flags);
 7753	int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1,
 7754				  &rt2x00dev->cap_flags);
 7755	u8 rfcsr;
 7756
 7757	rt2800_rf_init_calibration(rt2x00dev, 30);
 7758
 7759	rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
 7760	rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
 7761	rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
 7762	rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
 7763	rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
 7764	rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
 7765	rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
 7766	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
 7767	rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
 7768	rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
 7769	rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
 7770	rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
 7771	rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
 7772	rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
 7773	rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
 7774	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
 7775	rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
 7776	rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
 7777	rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
 7778	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
 7779	rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
 7780	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
 7781	rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
 7782	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
 7783	rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
 7784	rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
 7785	rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
 7786	rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
 7787	rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
 7788	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
 7789	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
 7790	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
 7791	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
 7792	rfcsr = 0x01;
 7793	if (tx0_ext_pa)
 7794		rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1);
 7795	if (tx1_ext_pa)
 7796		rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1);
 7797	rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
 7798	rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
 7799	rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
 7800	rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
 7801	rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
 7802	rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
 7803	rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
 7804	rfcsr = 0x52;
 7805	if (!tx0_ext_pa) {
 7806		rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1);
 7807		rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1);
 7808	}
 7809	rt2800_rfcsr_write(rt2x00dev, 41, rfcsr);
 7810	rfcsr = 0x52;
 7811	if (!tx1_ext_pa) {
 7812		rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1);
 7813		rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1);
 7814	}
 7815	rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
 7816	rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
 7817	rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
 7818	rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
 7819	rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
 7820	rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
 7821	rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
 7822	rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
 7823	rfcsr = 0x2d;
 7824	if (tx0_ext_pa)
 7825		rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1);
 7826	if (tx1_ext_pa)
 7827		rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1);
 7828	rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
 7829	rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f));
 7830	rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00));
 7831	rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52));
 7832	rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b));
 7833	rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f));
 7834	rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00));
 7835	rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52));
 7836	rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b));
 7837	rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
 7838	rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
 7839	rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
 7840	rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
 7841	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
 7842
 7843	rt2800_rx_filter_calibration(rt2x00dev);
 7844	rt2800_led_open_drain_enable(rt2x00dev);
 7845	rt2800_normal_mode_setup_3xxx(rt2x00dev);
 7846}
 7847
 7848static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
 7849{
 7850	u32 reg;
 7851
 7852	rt2800_rf_init_calibration(rt2x00dev, 30);
 7853
 7854	rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
 7855	rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
 7856	rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
 7857	rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
 7858	rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
 7859	rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
 7860	rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
 7861	rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
 7862	rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
 7863	rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
 7864	rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
 7865	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
 7866	rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
 7867	rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
 7868	rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
 7869	rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
 7870	rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
 7871	rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
 7872	rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
 7873	rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
 7874	rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
 7875	rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
 7876	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
 7877	rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
 7878	rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
 7879	rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
 7880	rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
 7881	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
 7882	rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
 7883	rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
 7884	rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
 7885	rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
 7886
 7887	reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
 7888	rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
 7889	rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
 7890
 7891	rt2800_rx_filter_calibration(rt2x00dev);
 7892
 7893	if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
 7894		rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
 7895
 7896	rt2800_led_open_drain_enable(rt2x00dev);
 7897	rt2800_normal_mode_setup_3xxx(rt2x00dev);
 7898}
 7899
 7900static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
 7901{
 7902	u8 rfcsr;
 7903	u32 reg;
 7904
 7905	rt2800_rf_init_calibration(rt2x00dev, 30);
 7906
 7907	rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
 7908	rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
 7909	rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
 7910	rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
 7911	rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
 7912	rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
 7913	rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
 7914	rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
 7915	rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
 7916	rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
 7917	rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
 7918	rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
 7919	rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
 7920	rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
 7921	rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
 7922	rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
 7923	rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
 7924	rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
 7925	rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
 7926	rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
 7927	rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
 7928	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
 7929	rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
 7930	rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
 7931	rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
 7932	rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
 7933	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
 7934	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
 7935	rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
 7936	rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
 7937	rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
 7938
 7939	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
 7940	rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
 7941	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
 7942
 7943	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
 7944	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
 7945	rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
 7946	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
 7947	msleep(1);
 7948	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
 7949	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
 7950	rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
 7951	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
 7952
 7953	rt2800_rx_filter_calibration(rt2x00dev);
 7954	rt2800_led_open_drain_enable(rt2x00dev);
 7955	rt2800_normal_mode_setup_3xxx(rt2x00dev);
 7956}
 7957
 7958static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
 7959{
 7960	u8 bbp;
 7961	bool txbf_enabled = false; /* FIXME */
 7962
 7963	bbp = rt2800_bbp_read(rt2x00dev, 105);
 7964	if (rt2x00dev->default_ant.rx_chain_num == 1)
 7965		rt2x00_set_field8(&bbp, BBP105_MLD, 0);
 7966	else
 7967		rt2x00_set_field8(&bbp, BBP105_MLD, 1);
 7968	rt2800_bbp_write(rt2x00dev, 105, bbp);
 7969
 7970	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
 7971
 7972	rt2800_bbp_write(rt2x00dev, 92, 0x02);
 7973	rt2800_bbp_write(rt2x00dev, 82, 0x82);
 7974	rt2800_bbp_write(rt2x00dev, 106, 0x05);
 7975	rt2800_bbp_write(rt2x00dev, 104, 0x92);
 7976	rt2800_bbp_write(rt2x00dev, 88, 0x90);
 7977	rt2800_bbp_write(rt2x00dev, 148, 0xc8);
 7978	rt2800_bbp_write(rt2x00dev, 47, 0x48);
 7979	rt2800_bbp_write(rt2x00dev, 120, 0x50);
 7980
 7981	if (txbf_enabled)
 7982		rt2800_bbp_write(rt2x00dev, 163, 0xbd);
 7983	else
 7984		rt2800_bbp_write(rt2x00dev, 163, 0x9d);
 7985
 7986	/* SNR mapping */
 7987	rt2800_bbp_write(rt2x00dev, 142, 6);
 7988	rt2800_bbp_write(rt2x00dev, 143, 160);
 7989	rt2800_bbp_write(rt2x00dev, 142, 7);
 7990	rt2800_bbp_write(rt2x00dev, 143, 161);
 7991	rt2800_bbp_write(rt2x00dev, 142, 8);
 7992	rt2800_bbp_write(rt2x00dev, 143, 162);
 7993
 7994	/* ADC/DAC control */
 7995	rt2800_bbp_write(rt2x00dev, 31, 0x08);
 7996
 7997	/* RX AGC energy lower bound in log2 */
 7998	rt2800_bbp_write(rt2x00dev, 68, 0x0b);
 7999
 8000	/* FIXME: BBP 105 owerwrite? */
 8001	rt2800_bbp_write(rt2x00dev, 105, 0x04);
 8002
 8003}
 8004
 8005static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
 8006{
 8007	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 8008	u32 reg;
 8009	u8 rfcsr;
 8010
 8011	/* Disable GPIO #4 and #7 function for LAN PE control */
 8012	reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
 8013	rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
 8014	rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
 8015	rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
 8016
 8017	/* Initialize default register values */
 8018	rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
 8019	rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
 8020	rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
 8021	rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
 8022	rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
 8023	rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
 8024	rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
 8025	rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
 8026	rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
 8027	rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
 8028	rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
 8029	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
 8030	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
 8031	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
 8032	rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
 8033	rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
 8034	rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
 8035	rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
 8036	rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
 8037	rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
 8038	rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
 8039	rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
 8040	rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
 8041	rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
 8042	rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
 8043	rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
 8044	rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
 8045	rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
 8046	rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
 8047	rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
 8048	rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
 8049	rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
 8050
 8051	/* Initiate calibration */
 8052	/* TODO: use rt2800_rf_init_calibration ? */
 8053	rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
 8054	rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
 8055	rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
 8056
 8057	rt2800_freq_cal_mode1(rt2x00dev);
 8058
 8059	rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
 8060	rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
 8061	rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
 8062
 8063	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
 8064	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
 8065	rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
 8066	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
 8067	usleep_range(1000, 1500);
 8068	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
 8069	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
 8070	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
 8071
 8072	/* Set initial values for RX filter calibration */
 8073	drv_data->calibration_bw20 = 0x1f;
 8074	drv_data->calibration_bw40 = 0x2f;
 8075
 8076	/* Save BBP 25 & 26 values for later use in channel switching */
 8077	drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
 8078	drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
 8079
 8080	rt2800_led_open_drain_enable(rt2x00dev);
 8081	rt2800_normal_mode_setup_3593(rt2x00dev);
 8082
 8083	rt3593_post_bbp_init(rt2x00dev);
 8084
 8085	/* TODO: enable stream mode support */
 8086}
 8087
 8088static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev)
 8089{
 8090	rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
 8091	rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
 8092	rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
 8093	rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
 8094	rt2800_rfcsr_write(rt2x00dev, 4, 0x49);
 8095	rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
 8096	rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
 8097	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
 8098	rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
 8099	rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
 8100	rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
 8101	rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
 8102	rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
 8103	if (rt2800_clk_is_20mhz(rt2x00dev))
 8104		rt2800_rfcsr_write(rt2x00dev, 13, 0x1f);
 8105	else
 8106		rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
 8107	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
 8108	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
 8109	rt2800_rfcsr_write(rt2x00dev, 16, 0xc0);
 8110	rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
 8111	rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
 8112	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
 8113	rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
 8114	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
 8115	rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
 8116	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
 8117	rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
 8118	rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
 8119	rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
 8120	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
 8121	rt2800_rfcsr_write(rt2x00dev, 29, 0xd0);
 8122	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
 8123	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
 8124	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
 8125	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
 8126	rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
 8127	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
 8128	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
 8129	rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
 8130	rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
 8131	rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
 8132	rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
 8133	rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
 8134	rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
 8135	rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
 8136	rt2800_rfcsr_write(rt2x00dev, 44, 0x0c);
 8137	rt2800_rfcsr_write(rt2x00dev, 45, 0xa6);
 8138	rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
 8139	rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
 8140	rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
 8141	rt2800_rfcsr_write(rt2x00dev, 49, 0x80);
 8142	rt2800_rfcsr_write(rt2x00dev, 50, 0x00);
 8143	rt2800_rfcsr_write(rt2x00dev, 51, 0x00);
 8144	rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
 8145	rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
 8146	rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
 8147	rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
 8148	rt2800_rfcsr_write(rt2x00dev, 56, 0x82);
 8149	rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
 8150	rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
 8151	rt2800_rfcsr_write(rt2x00dev, 59, 0x0b);
 8152	rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
 8153	rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
 8154	rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
 8155	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
 8156}
 8157
 8158static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev)
 8159{
 8160	u8 rfcsr;
 8161
 8162	/* TODO: get the actual ECO value from the SoC */
 8163	const unsigned int eco = 5;
 8164
 8165	rt2800_rf_init_calibration(rt2x00dev, 2);
 8166
 8167	rt2800_rfcsr_write(rt2x00dev, 0, 0xe0);
 8168	rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
 8169	rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
 8170	rt2800_rfcsr_write(rt2x00dev, 3, 0x20);
 8171	rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
 8172	rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
 8173	rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
 8174	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
 8175	rt2800_rfcsr_write(rt2x00dev, 8, 0x5b);
 8176	rt2800_rfcsr_write(rt2x00dev, 9, 0x08);
 8177	rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
 8178	rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
 8179	rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
 8180	rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
 8181	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
 8182	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
 8183	rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
 8184
 8185	/* RFCSR 17 will be initialized later based on the
 8186	 * frequency offset stored in the EEPROM
 8187	 */
 8188
 8189	rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
 8190	rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
 8191	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
 8192	rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
 8193	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
 8194	rt2800_rfcsr_write(rt2x00dev, 23, 0xc0);
 8195	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
 8196	rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
 8197	rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
 8198	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
 8199	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
 8200	rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
 8201	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
 8202	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
 8203	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
 8204	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
 8205	rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
 8206	rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
 8207	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
 8208	rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
 8209	rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
 8210	rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
 8211	rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
 8212	rt2800_rfcsr_write(rt2x00dev, 41, 0x00);
 8213	rt2800_rfcsr_write(rt2x00dev, 42, 0x00);
 8214	rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
 8215	rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
 8216	rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
 8217	rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
 8218	rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
 8219	rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
 8220	rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
 8221	rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
 8222	rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
 8223	rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
 8224	rt2800_rfcsr_write(rt2x00dev, 53, 0x76);
 8225	rt2800_rfcsr_write(rt2x00dev, 54, 0x76);
 8226	rt2800_rfcsr_write(rt2x00dev, 55, 0x76);
 8227	rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
 8228	rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
 8229	rt2800_rfcsr_write(rt2x00dev, 58, 0x00);
 8230	rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
 8231	rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
 8232	rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
 8233	rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
 8234	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
 8235
 8236	/* TODO: rx filter calibration? */
 8237
 8238	rt2800_bbp_write(rt2x00dev, 137, 0x0f);
 8239
 8240	rt2800_bbp_write(rt2x00dev, 163, 0x9d);
 8241
 8242	rt2800_bbp_write(rt2x00dev, 105, 0x05);
 8243
 8244	rt2800_bbp_write(rt2x00dev, 179, 0x02);
 8245	rt2800_bbp_write(rt2x00dev, 180, 0x00);
 8246	rt2800_bbp_write(rt2x00dev, 182, 0x40);
 8247	rt2800_bbp_write(rt2x00dev, 180, 0x01);
 8248	rt2800_bbp_write(rt2x00dev, 182, 0x9c);
 8249
 8250	rt2800_bbp_write(rt2x00dev, 179, 0x00);
 8251
 8252	rt2800_bbp_write(rt2x00dev, 142, 0x04);
 8253	rt2800_bbp_write(rt2x00dev, 143, 0x3b);
 8254	rt2800_bbp_write(rt2x00dev, 142, 0x06);
 8255	rt2800_bbp_write(rt2x00dev, 143, 0xa0);
 8256	rt2800_bbp_write(rt2x00dev, 142, 0x07);
 8257	rt2800_bbp_write(rt2x00dev, 143, 0xa1);
 8258	rt2800_bbp_write(rt2x00dev, 142, 0x08);
 8259	rt2800_bbp_write(rt2x00dev, 143, 0xa2);
 8260	rt2800_bbp_write(rt2x00dev, 148, 0xc8);
 8261
 8262	if (eco == 5) {
 8263		rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
 8264		rt2800_rfcsr_write(rt2x00dev, 33, 0x32);
 8265	}
 8266
 8267	rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
 8268	rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_BP, 0);
 8269	rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
 8270	rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
 8271	msleep(1);
 8272	rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
 8273	rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
 8274
 8275	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
 8276	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
 8277	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
 8278
 8279	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
 8280	rfcsr |= 0xc0;
 8281	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
 8282
 8283	rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
 8284	rfcsr |= 0x20;
 8285	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
 8286
 8287	rfcsr = rt2800_rfcsr_read(rt2x00dev, 46);
 8288	rfcsr |= 0x20;
 8289	rt2800_rfcsr_write(rt2x00dev, 46, rfcsr);
 8290
 8291	rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
 8292	rfcsr &= ~0xee;
 8293	rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
 8294}
 8295
 8296static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
 8297{
 8298	rt2800_rf_init_calibration(rt2x00dev, 2);
 8299
 8300	rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
 8301	rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
 8302	rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
 8303	rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
 8304	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
 8305		rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
 8306	else
 8307		rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
 8308	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
 8309	rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
 8310	rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
 8311	rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
 8312	rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
 8313	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
 8314	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
 8315	rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
 8316	rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
 8317	rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
 8318
 8319	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
 8320	rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
 8321	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
 8322	rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
 8323	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
 8324	if (rt2x00_is_usb(rt2x00dev) &&
 8325	    rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
 8326		rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
 8327	else
 8328		rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
 8329	rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
 8330	rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
 8331	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
 8332	rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
 8333
 8334	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
 8335	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
 8336	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
 8337	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
 8338	rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
 8339	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
 8340	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
 8341	rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
 8342	rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
 8343	rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
 8344
 8345	rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
 8346	rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
 8347	rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
 8348	rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
 8349	rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
 8350	rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
 8351	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
 8352		rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
 8353	else
 8354		rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
 8355	rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
 8356	rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
 8357	rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
 8358
 8359	rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
 8360	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
 8361		rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
 8362	else
 8363		rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
 8364	rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
 8365	rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
 8366	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
 8367		rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
 8368	else
 8369		rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
 8370	rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
 8371	rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
 8372	rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
 8373
 8374	rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
 8375	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
 8376		if (rt2x00_is_usb(rt2x00dev))
 8377			rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
 8378		else
 8379			rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
 8380	} else {
 8381		if (rt2x00_is_usb(rt2x00dev))
 8382			rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
 8383		else
 8384			rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
 8385	}
 8386	rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
 8387	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
 8388
 8389	rt2800_normal_mode_setup_5xxx(rt2x00dev);
 8390
 8391	rt2800_led_open_drain_enable(rt2x00dev);
 8392}
 8393
 8394static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
 8395{
 8396	rt2800_rf_init_calibration(rt2x00dev, 2);
 8397
 8398	rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
 8399	rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
 8400	rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
 8401	rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
 8402	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
 8403	rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
 8404	rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
 8405	rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
 8406	rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
 8407	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
 8408	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
 8409	rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
 8410	rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
 8411	rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
 8412	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
 8413	rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
 8414	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
 8415	rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
 8416	rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
 8417	rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
 8418	rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
 8419	rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
 8420	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
 8421	rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
 8422	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
 8423	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
 8424	rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
 8425	rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
 8426	rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
 8427	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
 8428	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
 8429	rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
 8430	rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
 8431	rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
 8432	rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
 8433	rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
 8434	rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
 8435	rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
 8436	rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
 8437	rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
 8438	rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
 8439	rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
 8440	rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
 8441	rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
 8442	rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
 8443	rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
 8444	rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
 8445	rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
 8446	rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
 8447	rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
 8448	rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
 8449	rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
 8450	rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
 8451	rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
 8452	rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
 8453	rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
 8454	rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
 8455	rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
 8456
 8457	rt2800_normal_mode_setup_5xxx(rt2x00dev);
 8458
 8459	rt2800_led_open_drain_enable(rt2x00dev);
 8460}
 8461
 8462static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
 8463{
 8464	rt2800_rf_init_calibration(rt2x00dev, 30);
 8465
 8466	rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
 8467	rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
 8468	rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
 8469	rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
 8470	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
 8471	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
 8472	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
 8473	rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
 8474	rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
 8475	rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
 8476	rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
 8477	rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
 8478	rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
 8479	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
 8480	rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
 8481	rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
 8482	rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
 8483	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
 8484	rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
 8485	rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
 8486	rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
 8487
 8488	rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
 8489	msleep(1);
 8490
 8491	rt2800_freq_cal_mode1(rt2x00dev);
 8492
 8493	/* Enable DC filter */
 8494	if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
 8495		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
 8496
 8497	rt2800_normal_mode_setup_5xxx(rt2x00dev);
 8498
 8499	if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
 8500		rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
 8501
 8502	rt2800_led_open_drain_enable(rt2x00dev);
 8503}
 8504
 8505static void rt2800_rf_self_txdc_cal(struct rt2x00_dev *rt2x00dev)
 8506{
 8507	u8 rfb5r1_org, rfb7r1_org, rfvalue;
 8508	u32 mac0518, mac051c, mac0528, mac052c;
 8509	u8 i;
 8510
 8511	mac0518 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
 8512	mac051c = rt2800_register_read(rt2x00dev, RF_BYPASS0);
 8513	mac0528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);
 8514	mac052c = rt2800_register_read(rt2x00dev, RF_BYPASS2);
 8515
 8516	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0);
 8517	rt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0);
 8518
 8519	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0xC);
 8520	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x3306);
 8521	rt2800_register_write(rt2x00dev, RF_CONTROL2, 0x3330);
 8522	rt2800_register_write(rt2x00dev, RF_BYPASS2, 0xfffff);
 8523	rfb5r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
 8524	rfb7r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1);
 8525
 8526	rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, 0x4);
 8527	for (i = 0; i < 100; ++i) {
 8528		usleep_range(50, 100);
 8529		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
 8530		if ((rfvalue & 0x04) != 0x4)
 8531			break;
 8532	}
 8533	rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rfb5r1_org);
 8534
 8535	rt2800_rfcsr_write_bank(rt2x00dev, 7, 1, 0x4);
 8536	for (i = 0; i < 100; ++i) {
 8537		usleep_range(50, 100);
 8538		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1);
 8539		if ((rfvalue & 0x04) != 0x4)
 8540			break;
 8541	}
 8542	rt2800_rfcsr_write_bank(rt2x00dev, 7, 1, rfb7r1_org);
 8543
 8544	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0);
 8545	rt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0);
 8546	rt2800_register_write(rt2x00dev, RF_CONTROL0, mac0518);
 8547	rt2800_register_write(rt2x00dev, RF_BYPASS0, mac051c);
 8548	rt2800_register_write(rt2x00dev, RF_CONTROL2, mac0528);
 8549	rt2800_register_write(rt2x00dev, RF_BYPASS2, mac052c);
 8550}
 8551
 8552static int rt2800_calcrcalibrationcode(struct rt2x00_dev *rt2x00dev, int d1, int d2)
 8553{
 8554	int calcode = ((d2 - d1) * 1000) / 43;
 8555
 8556	if ((calcode % 10) >= 5)
 8557		calcode += 10;
 8558	calcode = (calcode / 10);
 8559
 8560	return calcode;
 8561}
 8562
 8563static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev)
 8564{
 8565	u32 savemacsysctrl;
 8566	u8 saverfb0r1, saverfb0r34, saverfb0r35;
 8567	u8 saverfb5r4, saverfb5r17, saverfb5r18;
 8568	u8 saverfb5r19, saverfb5r20;
 8569	u8 savebbpr22, savebbpr47, savebbpr49;
 8570	u8 bytevalue = 0;
 8571	int rcalcode;
 8572	u8 r_cal_code = 0;
 8573	s8 d1 = 0, d2 = 0;
 8574	u8 rfvalue;
 8575	u32 MAC_RF_BYPASS0, MAC_RF_CONTROL0, MAC_PWR_PIN_CFG;
 8576	u32 maccfg;
 8577
 8578	saverfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
 8579	saverfb0r34 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 34);
 8580	saverfb0r35 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
 8581	saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
 8582	saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
 8583	saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
 8584	saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
 8585	saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
 8586
 8587	savebbpr22 = rt2800_bbp_read(rt2x00dev, 22);
 8588	savebbpr47 = rt2800_bbp_read(rt2x00dev, 47);
 8589	savebbpr49 = rt2800_bbp_read(rt2x00dev, 49);
 8590
 8591	savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
 8592	MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
 8593	MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
 8594	MAC_PWR_PIN_CFG = rt2800_register_read(rt2x00dev, PWR_PIN_CFG);
 8595
 8596	maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
 8597	maccfg &= (~0x04);
 8598	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);
 8599
 8600	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
 8601		rt2x00_warn(rt2x00dev, "Wait MAC Tx Status to MAX !!!\n");
 8602
 8603	maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
 8604	maccfg &= (~0x08);
 8605	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);
 8606
 8607	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
 8608		rt2x00_warn(rt2x00dev, "Wait MAC Rx Status to MAX !!!\n");
 8609
 8610	rfvalue = (MAC_RF_BYPASS0 | 0x3004);
 8611	rt2800_register_write(rt2x00dev, RF_BYPASS0, rfvalue);
 8612	rfvalue = (MAC_RF_CONTROL0 | (~0x3002));
 8613	rt2800_register_write(rt2x00dev, RF_CONTROL0, rfvalue);
 8614
 8615	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x27);
 8616	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);
 8617	rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0x83);
 8618	rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x00);
 8619	rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);
 8620
 8621	rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x00);
 8622	rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, 0x13);
 8623	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
 8624
 8625	rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x1);
 8626
 8627	rt2800_bbp_write(rt2x00dev, 47, 0x04);
 8628	rt2800_bbp_write(rt2x00dev, 22, 0x80);
 8629	usleep_range(100, 200);
 8630	bytevalue = rt2800_bbp_read(rt2x00dev, 49);
 8631	if (bytevalue > 128)
 8632		d1 = bytevalue - 256;
 8633	else
 8634		d1 = (s8)bytevalue;
 8635	rt2800_bbp_write(rt2x00dev, 22, 0x0);
 8636	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x01);
 8637
 8638	rt2800_bbp_write(rt2x00dev, 22, 0x80);
 8639	usleep_range(100, 200);
 8640	bytevalue = rt2800_bbp_read(rt2x00dev, 49);
 8641	if (bytevalue > 128)
 8642		d2 = bytevalue - 256;
 8643	else
 8644		d2 = (s8)bytevalue;
 8645	rt2800_bbp_write(rt2x00dev, 22, 0x0);
 8646
 8647	rcalcode = rt2800_calcrcalibrationcode(rt2x00dev, d1, d2);
 8648	if (rcalcode < 0)
 8649		r_cal_code = 256 + rcalcode;
 8650	else
 8651		r_cal_code = (u8)rcalcode;
 8652
 8653	rt2800_rfcsr_write_bank(rt2x00dev, 0, 7, r_cal_code);
 8654
 8655	rt2800_bbp_write(rt2x00dev, 22, 0x0);
 8656
 8657	bytevalue = rt2800_bbp_read(rt2x00dev, 21);
 8658	bytevalue |= 0x1;
 8659	rt2800_bbp_write(rt2x00dev, 21, bytevalue);
 8660	bytevalue = rt2800_bbp_read(rt2x00dev, 21);
 8661	bytevalue &= (~0x1);
 8662	rt2800_bbp_write(rt2x00dev, 21, bytevalue);
 8663
 8664	rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, saverfb0r1);
 8665	rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, saverfb0r34);
 8666	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, saverfb0r35);
 8667	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4);
 8668	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
 8669	rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
 8670	rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
 8671	rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
 8672
 8673	rt2800_bbp_write(rt2x00dev, 22, savebbpr22);
 8674	rt2800_bbp_write(rt2x00dev, 47, savebbpr47);
 8675	rt2800_bbp_write(rt2x00dev, 49, savebbpr49);
 8676
 8677	rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
 8678	rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
 8679
 8680	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
 8681	rt2800_register_write(rt2x00dev, PWR_PIN_CFG, MAC_PWR_PIN_CFG);
 8682}
 8683
 8684static void rt2800_rxdcoc_calibration(struct rt2x00_dev *rt2x00dev)
 8685{
 8686	u8 bbpreg = 0;
 8687	u32 macvalue = 0;
 8688	u8 saverfb0r2, saverfb5r4, saverfb7r4, rfvalue;
 8689	int i;
 8690
 8691	saverfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
 8692	rfvalue = saverfb0r2;
 8693	rfvalue |= 0x03;
 8694	rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfvalue);
 8695
 8696	rt2800_bbp_write(rt2x00dev, 158, 141);
 8697	bbpreg = rt2800_bbp_read(rt2x00dev, 159);
 8698	bbpreg |= 0x10;
 8699	rt2800_bbp_write(rt2x00dev, 159, bbpreg);
 8700
 8701	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
 8702	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x8);
 8703
 8704	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
 8705		rt2x00_warn(rt2x00dev, "RF TX busy in RX RXDCOC calibration\n");
 8706
 8707	saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
 8708	saverfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
 8709	saverfb5r4 = saverfb5r4 & (~0x40);
 8710	saverfb7r4 = saverfb7r4 & (~0x40);
 8711	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x64);
 8712	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4);
 8713	rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, saverfb7r4);
 8714
 8715	rt2800_bbp_write(rt2x00dev, 158, 140);
 8716	bbpreg = rt2800_bbp_read(rt2x00dev, 159);
 8717	bbpreg = bbpreg & (~0x40);
 8718	rt2800_bbp_write(rt2x00dev, 159, bbpreg);
 8719	bbpreg |= 0x48;
 8720	rt2800_bbp_write(rt2x00dev, 159, bbpreg);
 8721
 8722	for (i = 0; i < 10000; i++) {
 8723		bbpreg = rt2800_bbp_read(rt2x00dev, 159);
 8724		if ((bbpreg & 0x40) == 0)
 8725			break;
 8726		usleep_range(50, 100);
 8727	}
 8728
 8729	bbpreg = rt2800_bbp_read(rt2x00dev, 159);
 8730	bbpreg = bbpreg & (~0x40);
 8731	rt2800_bbp_write(rt2x00dev, 159, bbpreg);
 8732
 8733	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
 8734
 8735	rt2800_bbp_write(rt2x00dev, 158, 141);
 8736	bbpreg = rt2800_bbp_read(rt2x00dev, 159);
 8737	bbpreg &= (~0x10);
 8738	rt2800_bbp_write(rt2x00dev, 159, bbpreg);
 8739
 8740	rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, saverfb0r2);
 8741}
 8742
 8743static u32 rt2800_do_sqrt_accumulation(u32 si)
 8744{
 8745	u32 root, root_pre, bit;
 8746	s8 i;
 8747
 8748	bit = 1 << 15;
 8749	root = 0;
 8750	for (i = 15; i >= 0; i = i - 1) {
 8751		root_pre = root + bit;
 8752		if ((root_pre * root_pre) <= si)
 8753			root = root_pre;
 8754		bit = bit >> 1;
 8755	}
 8756
 8757	return root;
 8758}
 8759
 8760static void rt2800_rxiq_calibration(struct rt2x00_dev *rt2x00dev)
 8761{
 8762	u8 rfb0r1, rfb0r2, rfb0r42;
 8763	u8 rfb4r0, rfb4r19;
 8764	u8 rfb5r3, rfb5r4, rfb5r17, rfb5r18, rfb5r19, rfb5r20;
 8765	u8 rfb6r0, rfb6r19;
 8766	u8 rfb7r3, rfb7r4, rfb7r17, rfb7r18, rfb7r19, rfb7r20;
 8767
 8768	u8 bbp1, bbp4;
 8769	u8 bbpr241, bbpr242;
 8770	u32 i;
 8771	u8 ch_idx;
 8772	u8 bbpval;
 8773	u8 rfval, vga_idx = 0;
 8774	int mi = 0, mq = 0, si = 0, sq = 0, riq = 0;
 8775	int sigma_i, sigma_q, r_iq, g_rx;
 8776	int g_imb;
 8777	int ph_rx;
 8778	u32 savemacsysctrl = 0;
 8779	u32 orig_RF_CONTROL0 = 0;
 8780	u32 orig_RF_BYPASS0 = 0;
 8781	u32 orig_RF_CONTROL1 = 0;
 8782	u32 orig_RF_BYPASS1 = 0;
 8783	u32 orig_RF_CONTROL3 = 0;
 8784	u32 orig_RF_BYPASS3 = 0;
 8785	u32 bbpval1 = 0;
 8786	static const u8 rf_vga_table[] = {0x20, 0x21, 0x22, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f};
 8787
 8788	savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
 8789	orig_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
 8790	orig_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
 8791	orig_RF_CONTROL1 = rt2800_register_read(rt2x00dev, RF_CONTROL1);
 8792	orig_RF_BYPASS1 = rt2800_register_read(rt2x00dev, RF_BYPASS1);
 8793	orig_RF_CONTROL3 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
 8794	orig_RF_BYPASS3 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
 8795
 8796	bbp1 = rt2800_bbp_read(rt2x00dev, 1);
 8797	bbp4 = rt2800_bbp_read(rt2x00dev, 4);
 8798
 8799	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x0);
 8800
 8801	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
 8802		rt2x00_warn(rt2x00dev, "Timeout waiting for MAC status in RXIQ calibration\n");
 8803
 8804	bbpval = bbp4 & (~0x18);
 8805	bbpval = bbp4 | 0x00;
 8806	rt2800_bbp_write(rt2x00dev, 4, bbpval);
 8807
 8808	bbpval = rt2800_bbp_read(rt2x00dev, 21);
 8809	bbpval = bbpval | 1;
 8810	rt2800_bbp_write(rt2x00dev, 21, bbpval);
 8811	bbpval = bbpval & 0xfe;
 8812	rt2800_bbp_write(rt2x00dev, 21, bbpval);
 8813
 8814	rt2800_register_write(rt2x00dev, RF_CONTROL1, 0x00000202);
 8815	rt2800_register_write(rt2x00dev, RF_BYPASS1, 0x00000303);
 8816	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
 8817		rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0101);
 8818	else
 8819		rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0000);
 8820
 8821	rt2800_register_write(rt2x00dev, RF_BYPASS3, 0xf1f1);
 8822
 8823	rfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
 8824	rfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
 8825	rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
 8826	rfb4r0 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
 8827	rfb4r19 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 19);
 8828	rfb5r3 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
 8829	rfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
 8830	rfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
 8831	rfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
 8832	rfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
 8833	rfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
 8834
 8835	rfb6r0 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
 8836	rfb6r19 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 19);
 8837	rfb7r3 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
 8838	rfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
 8839	rfb7r17 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
 8840	rfb7r18 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
 8841	rfb7r19 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
 8842	rfb7r20 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
 8843
 8844	rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x87);
 8845	rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0x27);
 8846	rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x38);
 8847	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x38);
 8848	rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x80);
 8849	rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0xC1);
 8850	rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x60);
 8851	rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
 8852
 8853	rt2800_bbp_write(rt2x00dev, 23, 0x0);
 8854	rt2800_bbp_write(rt2x00dev, 24, 0x0);
 8855
 8856	rt2800_bbp_dcoc_write(rt2x00dev, 5, 0x0);
 8857
 8858	bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
 8859	bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
 8860
 8861	rt2800_bbp_write(rt2x00dev, 241, 0x10);
 8862	rt2800_bbp_write(rt2x00dev, 242, 0x84);
 8863	rt2800_bbp_write(rt2x00dev, 244, 0x31);
 8864
 8865	bbpval = rt2800_bbp_dcoc_read(rt2x00dev, 3);
 8866	bbpval = bbpval & (~0x7);
 8867	rt2800_bbp_dcoc_write(rt2x00dev, 3, bbpval);
 8868
 8869	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
 8870	udelay(1);
 8871	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);
 8872	usleep_range(1, 200);
 8873	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003376);
 8874	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);
 8875	udelay(1);
 8876	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
 8877		rt2800_bbp_write(rt2x00dev, 23, 0x06);
 8878		rt2800_bbp_write(rt2x00dev, 24, 0x06);
 8879	} else {
 8880		rt2800_bbp_write(rt2x00dev, 23, 0x02);
 8881		rt2800_bbp_write(rt2x00dev, 24, 0x02);
 8882	}
 8883
 8884	for (ch_idx = 0; ch_idx < 2; ch_idx = ch_idx + 1) {
 8885		if (ch_idx == 0) {
 8886			rfval = rfb0r1 | 0x1;
 8887			rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);
 8888			rfval = rfb0r2 | 0x11;
 8889			rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);
 8890			rfval = rfb0r42 | 0x10;
 8891			rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);
 8892
 8893			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);
 8894			udelay(1);
 8895
 8896			bbpval = bbp1 & (~0x18);
 8897			bbpval = bbpval | 0x00;
 8898			rt2800_bbp_write(rt2x00dev, 1, bbpval);
 8899
 8900			rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x00);
 8901		} else {
 8902			rfval = rfb0r1 | 0x2;
 8903			rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);
 8904			rfval = rfb0r2 | 0x22;
 8905			rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);
 8906			rfval = rfb0r42 | 0x40;
 8907			rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);
 8908
 8909			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002006);
 8910			udelay(1);
 8911
 8912			bbpval = bbp1 & (~0x18);
 8913			bbpval = bbpval | 0x08;
 8914			rt2800_bbp_write(rt2x00dev, 1, bbpval);
 8915
 8916			rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x01);
 8917		}
 8918		usleep_range(500, 1500);
 8919
 8920		vga_idx = 0;
 8921		while (vga_idx < 11) {
 8922			rt2800_rfcsr_write_dccal(rt2x00dev, 3, rf_vga_table[vga_idx]);
 8923			rt2800_rfcsr_write_dccal(rt2x00dev, 4, rf_vga_table[vga_idx]);
 8924
 8925			rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x93);
 8926
 8927			for (i = 0; i < 10000; i++) {
 8928				bbpval = rt2800_bbp_read(rt2x00dev, 159);
 8929				if ((bbpval & 0xff) == 0x93)
 8930					usleep_range(50, 100);
 8931				else
 8932					break;
 8933				}
 8934
 8935			if ((bbpval & 0xff) == 0x93) {
 8936				rt2x00_warn(rt2x00dev, "Fatal Error: Calibration doesn't finish");
 8937				goto restore_value;
 8938			}
 8939			for (i = 0; i < 5; i++) {
 8940				u32 bbptemp = 0;
 8941				u8 value = 0;
 8942				int result = 0;
 8943
 8944				rt2800_bbp_write(rt2x00dev, 158, 0x1e);
 8945				rt2800_bbp_write(rt2x00dev, 159, i);
 8946				rt2800_bbp_write(rt2x00dev, 158, 0x22);
 8947				value = rt2800_bbp_read(rt2x00dev, 159);
 8948				bbptemp = bbptemp + (value << 24);
 8949				rt2800_bbp_write(rt2x00dev, 158, 0x21);
 8950				value = rt2800_bbp_read(rt2x00dev, 159);
 8951				bbptemp = bbptemp + (value << 16);
 8952				rt2800_bbp_write(rt2x00dev, 158, 0x20);
 8953				value = rt2800_bbp_read(rt2x00dev, 159);
 8954				bbptemp = bbptemp + (value << 8);
 8955				rt2800_bbp_write(rt2x00dev, 158, 0x1f);
 8956				value = rt2800_bbp_read(rt2x00dev, 159);
 8957				bbptemp = bbptemp + value;
 8958
 8959				if (i < 2 && (bbptemp & 0x800000))
 8960					result = (bbptemp & 0xffffff) - 0x1000000;
 8961				else
 8962					result = bbptemp;
 8963
 8964				if (i == 0)
 8965					mi = result / 4096;
 8966				else if (i == 1)
 8967					mq = result / 4096;
 8968				else if (i == 2)
 8969					si = bbptemp / 4096;
 8970				else if (i == 3)
 8971					sq = bbptemp / 4096;
 8972				else
 8973					riq = result / 4096;
 8974			}
 8975
 8976			bbpval1 = si - mi * mi;
 8977			rt2x00_dbg(rt2x00dev,
 8978				   "RXIQ si=%d, sq=%d, riq=%d, bbpval %d, vga_idx %d",
 8979				   si, sq, riq, bbpval1, vga_idx);
 8980
 8981			if (bbpval1 >= (100 * 100))
 8982				break;
 8983
 8984			if (bbpval1 <= 100)
 8985				vga_idx = vga_idx + 9;
 8986			else if (bbpval1 <= 158)
 8987				vga_idx = vga_idx + 8;
 8988			else if (bbpval1 <= 251)
 8989				vga_idx = vga_idx + 7;
 8990			else if (bbpval1 <= 398)
 8991				vga_idx = vga_idx + 6;
 8992			else if (bbpval1 <= 630)
 8993				vga_idx = vga_idx + 5;
 8994			else if (bbpval1 <= 1000)
 8995				vga_idx = vga_idx + 4;
 8996			else if (bbpval1 <= 1584)
 8997				vga_idx = vga_idx + 3;
 8998			else if (bbpval1 <= 2511)
 8999				vga_idx = vga_idx + 2;
 9000			else
 9001				vga_idx = vga_idx + 1;
 9002		}
 9003
 9004		sigma_i = rt2800_do_sqrt_accumulation(100 * (si - mi * mi));
 9005		sigma_q = rt2800_do_sqrt_accumulation(100 * (sq - mq * mq));
 9006		r_iq = 10 * (riq - (mi * mq));
 9007
 9008		rt2x00_dbg(rt2x00dev, "Sigma_i=%d, Sigma_q=%d, R_iq=%d", sigma_i, sigma_q, r_iq);
 9009
 9010		if (sigma_i <= 1400 && sigma_i >= 1000 &&
 9011		    (sigma_i - sigma_q) <= 112 &&
 9012		    (sigma_i - sigma_q) >= -112 &&
 9013		    mi <= 32 && mi >= -32 &&
 9014		    mq <= 32 && mq >= -32) {
 9015			r_iq = 10 * (riq - (mi * mq));
 9016			rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n",
 9017				   sigma_i, sigma_q, r_iq);
 9018
 9019			g_rx = (1000 * sigma_q) / sigma_i;
 9020			g_imb = ((-2) * 128 * (1000 - g_rx)) / (1000 + g_rx);
 9021			ph_rx = (r_iq * 2292) / (sigma_i * sigma_q);
 9022
 9023			if (ph_rx > 20 || ph_rx < -20) {
 9024				ph_rx = 0;
 9025				rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
 9026			}
 9027
 9028			if (g_imb > 12 || g_imb < -12) {
 9029				g_imb = 0;
 9030				rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
 9031			}
 9032		} else {
 9033			g_imb = 0;
 9034			ph_rx = 0;
 9035			rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n",
 9036				   sigma_i, sigma_q, r_iq);
 9037			rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
 9038		}
 9039
 9040		if (ch_idx == 0) {
 9041			rt2800_bbp_write(rt2x00dev, 158, 0x37);
 9042			rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);
 9043			rt2800_bbp_write(rt2x00dev, 158, 0x35);
 9044			rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);
 9045		} else {
 9046			rt2800_bbp_write(rt2x00dev, 158, 0x55);
 9047			rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);
 9048			rt2800_bbp_write(rt2x00dev, 158, 0x53);
 9049			rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);
 9050		}
 9051	}
 9052
 9053restore_value:
 9054	rt2800_bbp_write(rt2x00dev, 158, 0x3);
 9055	bbpval = rt2800_bbp_read(rt2x00dev, 159);
 9056	rt2800_bbp_write(rt2x00dev, 159, (bbpval | 0x07));
 9057
 9058	rt2800_bbp_write(rt2x00dev, 158, 0x00);
 9059	rt2800_bbp_write(rt2x00dev, 159, 0x00);
 9060	rt2800_bbp_write(rt2x00dev, 1, bbp1);
 9061	rt2800_bbp_write(rt2x00dev, 4, bbp4);
 9062	rt2800_bbp_write(rt2x00dev, 241, bbpr241);
 9063	rt2800_bbp_write(rt2x00dev, 242, bbpr242);
 9064
 9065	rt2800_bbp_write(rt2x00dev, 244, 0x00);
 9066	bbpval = rt2800_bbp_read(rt2x00dev, 21);
 9067	bbpval |= 0x1;
 9068	rt2800_bbp_write(rt2x00dev, 21, bbpval);
 9069	usleep_range(10, 200);
 9070	bbpval &= 0xfe;
 9071	rt2800_bbp_write(rt2x00dev, 21, bbpval);
 9072
 9073	rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfb0r1);
 9074	rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfb0r2);
 9075	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
 9076
 9077	rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, rfb4r0);
 9078	rt2800_rfcsr_write_bank(rt2x00dev, 4, 19, rfb4r19);
 9079	rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rfb5r3);
 9080	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rfb5r4);
 9081	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rfb5r17);
 9082	rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, rfb5r18);
 9083	rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, rfb5r19);
 9084	rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, rfb5r20);
 9085
 9086	rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, rfb6r0);
 9087	rt2800_rfcsr_write_bank(rt2x00dev, 6, 19, rfb6r19);
 9088	rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, rfb7r3);
 9089	rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, rfb7r4);
 9090	rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, rfb7r17);
 9091	rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, rfb7r18);
 9092	rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, rfb7r19);
 9093	rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, rfb7r20);
 9094
 9095	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);
 9096	udelay(1);
 9097	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
 9098	udelay(1);
 9099	rt2800_register_write(rt2x00dev, RF_CONTROL0, orig_RF_CONTROL0);
 9100	udelay(1);
 9101	rt2800_register_write(rt2x00dev, RF_BYPASS0, orig_RF_BYPASS0);
 9102	rt2800_register_write(rt2x00dev, RF_CONTROL1, orig_RF_CONTROL1);
 9103	rt2800_register_write(rt2x00dev, RF_BYPASS1, orig_RF_BYPASS1);
 9104	rt2800_register_write(rt2x00dev, RF_CONTROL3, orig_RF_CONTROL3);
 9105	rt2800_register_write(rt2x00dev, RF_BYPASS3, orig_RF_BYPASS3);
 9106	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
 9107}
 9108
 9109static void rt2800_rf_configstore(struct rt2x00_dev *rt2x00dev,
 9110				  struct rf_reg_pair rf_reg_record[][13], u8 chain)
 9111{
 9112	u8 rfvalue = 0;
 9113
 9114	if (chain == CHAIN_0) {
 9115		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
 9116		rf_reg_record[CHAIN_0][0].bank = 0;
 9117		rf_reg_record[CHAIN_0][0].reg = 1;
 9118		rf_reg_record[CHAIN_0][0].value = rfvalue;
 9119		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
 9120		rf_reg_record[CHAIN_0][1].bank = 0;
 9121		rf_reg_record[CHAIN_0][1].reg = 2;
 9122		rf_reg_record[CHAIN_0][1].value = rfvalue;
 9123		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
 9124		rf_reg_record[CHAIN_0][2].bank = 0;
 9125		rf_reg_record[CHAIN_0][2].reg = 35;
 9126		rf_reg_record[CHAIN_0][2].value = rfvalue;
 9127		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
 9128		rf_reg_record[CHAIN_0][3].bank = 0;
 9129		rf_reg_record[CHAIN_0][3].reg = 42;
 9130		rf_reg_record[CHAIN_0][3].value = rfvalue;
 9131		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
 9132		rf_reg_record[CHAIN_0][4].bank = 4;
 9133		rf_reg_record[CHAIN_0][4].reg = 0;
 9134		rf_reg_record[CHAIN_0][4].value = rfvalue;
 9135		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 2);
 9136		rf_reg_record[CHAIN_0][5].bank = 4;
 9137		rf_reg_record[CHAIN_0][5].reg = 2;
 9138		rf_reg_record[CHAIN_0][5].value = rfvalue;
 9139		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 34);
 9140		rf_reg_record[CHAIN_0][6].bank = 4;
 9141		rf_reg_record[CHAIN_0][6].reg = 34;
 9142		rf_reg_record[CHAIN_0][6].value = rfvalue;
 9143		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
 9144		rf_reg_record[CHAIN_0][7].bank = 5;
 9145		rf_reg_record[CHAIN_0][7].reg = 3;
 9146		rf_reg_record[CHAIN_0][7].value = rfvalue;
 9147		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
 9148		rf_reg_record[CHAIN_0][8].bank = 5;
 9149		rf_reg_record[CHAIN_0][8].reg = 4;
 9150		rf_reg_record[CHAIN_0][8].value = rfvalue;
 9151		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
 9152		rf_reg_record[CHAIN_0][9].bank = 5;
 9153		rf_reg_record[CHAIN_0][9].reg = 17;
 9154		rf_reg_record[CHAIN_0][9].value = rfvalue;
 9155		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
 9156		rf_reg_record[CHAIN_0][10].bank = 5;
 9157		rf_reg_record[CHAIN_0][10].reg = 18;
 9158		rf_reg_record[CHAIN_0][10].value = rfvalue;
 9159		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
 9160		rf_reg_record[CHAIN_0][11].bank = 5;
 9161		rf_reg_record[CHAIN_0][11].reg = 19;
 9162		rf_reg_record[CHAIN_0][11].value = rfvalue;
 9163		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
 9164		rf_reg_record[CHAIN_0][12].bank = 5;
 9165		rf_reg_record[CHAIN_0][12].reg = 20;
 9166		rf_reg_record[CHAIN_0][12].value = rfvalue;
 9167	} else if (chain == CHAIN_1) {
 9168		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
 9169		rf_reg_record[CHAIN_1][0].bank = 0;
 9170		rf_reg_record[CHAIN_1][0].reg = 1;
 9171		rf_reg_record[CHAIN_1][0].value = rfvalue;
 9172		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
 9173		rf_reg_record[CHAIN_1][1].bank = 0;
 9174		rf_reg_record[CHAIN_1][1].reg = 2;
 9175		rf_reg_record[CHAIN_1][1].value = rfvalue;
 9176		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
 9177		rf_reg_record[CHAIN_1][2].bank = 0;
 9178		rf_reg_record[CHAIN_1][2].reg = 35;
 9179		rf_reg_record[CHAIN_1][2].value = rfvalue;
 9180		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
 9181		rf_reg_record[CHAIN_1][3].bank = 0;
 9182		rf_reg_record[CHAIN_1][3].reg = 42;
 9183		rf_reg_record[CHAIN_1][3].value = rfvalue;
 9184		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
 9185		rf_reg_record[CHAIN_1][4].bank = 6;
 9186		rf_reg_record[CHAIN_1][4].reg = 0;
 9187		rf_reg_record[CHAIN_1][4].value = rfvalue;
 9188		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 2);
 9189		rf_reg_record[CHAIN_1][5].bank = 6;
 9190		rf_reg_record[CHAIN_1][5].reg = 2;
 9191		rf_reg_record[CHAIN_1][5].value = rfvalue;
 9192		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 34);
 9193		rf_reg_record[CHAIN_1][6].bank = 6;
 9194		rf_reg_record[CHAIN_1][6].reg = 34;
 9195		rf_reg_record[CHAIN_1][6].value = rfvalue;
 9196		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
 9197		rf_reg_record[CHAIN_1][7].bank = 7;
 9198		rf_reg_record[CHAIN_1][7].reg = 3;
 9199		rf_reg_record[CHAIN_1][7].value = rfvalue;
 9200		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
 9201		rf_reg_record[CHAIN_1][8].bank = 7;
 9202		rf_reg_record[CHAIN_1][8].reg = 4;
 9203		rf_reg_record[CHAIN_1][8].value = rfvalue;
 9204		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
 9205		rf_reg_record[CHAIN_1][9].bank = 7;
 9206		rf_reg_record[CHAIN_1][9].reg = 17;
 9207		rf_reg_record[CHAIN_1][9].value = rfvalue;
 9208		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
 9209		rf_reg_record[CHAIN_1][10].bank = 7;
 9210		rf_reg_record[CHAIN_1][10].reg = 18;
 9211		rf_reg_record[CHAIN_1][10].value = rfvalue;
 9212		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
 9213		rf_reg_record[CHAIN_1][11].bank = 7;
 9214		rf_reg_record[CHAIN_1][11].reg = 19;
 9215		rf_reg_record[CHAIN_1][11].value = rfvalue;
 9216		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
 9217		rf_reg_record[CHAIN_1][12].bank = 7;
 9218		rf_reg_record[CHAIN_1][12].reg = 20;
 9219		rf_reg_record[CHAIN_1][12].value = rfvalue;
 9220	} else {
 9221		rt2x00_warn(rt2x00dev, "Unknown chain = %u\n", chain);
 9222	}
 9223}
 9224
 9225static void rt2800_rf_configrecover(struct rt2x00_dev *rt2x00dev,
 9226				    struct rf_reg_pair rf_record[][13])
 9227{
 9228	u8 chain_index = 0, record_index = 0;
 9229	u8 bank = 0, rf_register = 0, value = 0;
 9230
 9231	for (chain_index = 0; chain_index < 2; chain_index++) {
 9232		for (record_index = 0; record_index < 13; record_index++) {
 9233			bank = rf_record[chain_index][record_index].bank;
 9234			rf_register = rf_record[chain_index][record_index].reg;
 9235			value = rf_record[chain_index][record_index].value;
 9236			rt2800_rfcsr_write_bank(rt2x00dev, bank, rf_register, value);
 9237			rt2x00_dbg(rt2x00dev, "bank: %d, rf_register: %d, value: %x\n",
 9238				   bank, rf_register, value);
 9239		}
 9240	}
 9241}
 9242
 9243static void rt2800_setbbptonegenerator(struct rt2x00_dev *rt2x00dev)
 9244{
 9245	rt2800_bbp_write(rt2x00dev, 158, 0xAA);
 9246	rt2800_bbp_write(rt2x00dev, 159, 0x00);
 9247
 9248	rt2800_bbp_write(rt2x00dev, 158, 0xAB);
 9249	rt2800_bbp_write(rt2x00dev, 159, 0x0A);
 9250
 9251	rt2800_bbp_write(rt2x00dev, 158, 0xAC);
 9252	rt2800_bbp_write(rt2x00dev, 159, 0x3F);
 9253
 9254	rt2800_bbp_write(rt2x00dev, 158, 0xAD);
 9255	rt2800_bbp_write(rt2x00dev, 159, 0x3F);
 9256
 9257	rt2800_bbp_write(rt2x00dev, 244, 0x40);
 9258}
 9259
 9260static u32 rt2800_do_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx, u8 read_neg)
 9261{
 9262	u32 macvalue = 0;
 9263	int fftout_i = 0, fftout_q = 0;
 9264	u32 ptmp = 0, pint = 0;
 9265	u8 bbp = 0;
 9266	u8 tidxi;
 9267
 9268	rt2800_bbp_write(rt2x00dev, 158, 0x00);
 9269	rt2800_bbp_write(rt2x00dev, 159, 0x9b);
 9270
 9271	bbp = 0x9b;
 9272
 9273	while (bbp == 0x9b) {
 9274		usleep_range(10, 50);
 9275		bbp = rt2800_bbp_read(rt2x00dev, 159);
 9276		bbp = bbp & 0xff;
 9277	}
 9278
 9279	rt2800_bbp_write(rt2x00dev, 158, 0xba);
 9280	rt2800_bbp_write(rt2x00dev, 159, tidx);
 9281	rt2800_bbp_write(rt2x00dev, 159, tidx);
 9282	rt2800_bbp_write(rt2x00dev, 159, tidx);
 9283
 9284	macvalue = rt2800_register_read(rt2x00dev, 0x057C);
 9285
 9286	fftout_i = (macvalue >> 16);
 9287	fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
 9288	fftout_q = (macvalue & 0xffff);
 9289	fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
 9290	ptmp = (fftout_i * fftout_i);
 9291	ptmp = ptmp + (fftout_q * fftout_q);
 9292	pint = ptmp;
 9293	rt2x00_dbg(rt2x00dev, "I = %d,  Q = %d, power = %x\n", fftout_i, fftout_q, pint);
 9294	if (read_neg) {
 9295		pint = pint >> 1;
 9296		tidxi = 0x40 - tidx;
 9297		tidxi = tidxi & 0x3f;
 9298
 9299		rt2800_bbp_write(rt2x00dev, 158, 0xba);
 9300		rt2800_bbp_write(rt2x00dev, 159, tidxi);
 9301		rt2800_bbp_write(rt2x00dev, 159, tidxi);
 9302		rt2800_bbp_write(rt2x00dev, 159, tidxi);
 9303
 9304		macvalue = rt2800_register_read(rt2x00dev, 0x057C);
 9305
 9306		fftout_i = (macvalue >> 16);
 9307		fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
 9308		fftout_q = (macvalue & 0xffff);
 9309		fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
 9310		ptmp = (fftout_i * fftout_i);
 9311		ptmp = ptmp + (fftout_q * fftout_q);
 9312		ptmp = ptmp >> 1;
 9313		pint = pint + ptmp;
 9314	}
 9315
 9316	return pint;
 9317}
 9318
 9319static u32 rt2800_read_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx)
 9320{
 9321	u32 macvalue = 0;
 9322	int fftout_i = 0, fftout_q = 0;
 9323	u32 ptmp = 0, pint = 0;
 9324
 9325	rt2800_bbp_write(rt2x00dev, 158, 0xBA);
 9326	rt2800_bbp_write(rt2x00dev, 159, tidx);
 9327	rt2800_bbp_write(rt2x00dev, 159, tidx);
 9328	rt2800_bbp_write(rt2x00dev, 159, tidx);
 9329
 9330	macvalue = rt2800_register_read(rt2x00dev, 0x057C);
 9331
 9332	fftout_i = (macvalue >> 16);
 9333	fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
 9334	fftout_q = (macvalue & 0xffff);
 9335	fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
 9336	ptmp = (fftout_i * fftout_i);
 9337	ptmp = ptmp + (fftout_q * fftout_q);
 9338	pint = ptmp;
 9339
 9340	return pint;
 9341}
 9342
 9343static void rt2800_write_dc(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc, u8 iorq, u8 dc)
 9344{
 9345	u8 bbp = 0;
 9346
 9347	rt2800_bbp_write(rt2x00dev, 158, 0xb0);
 9348	bbp = alc | 0x80;
 9349	rt2800_bbp_write(rt2x00dev, 159, bbp);
 9350
 9351	if (ch_idx == 0)
 9352		bbp = (iorq == 0) ? 0xb1 : 0xb2;
 9353	else
 9354		bbp = (iorq == 0) ? 0xb8 : 0xb9;
 9355
 9356	rt2800_bbp_write(rt2x00dev, 158, bbp);
 9357	bbp = dc;
 9358	rt2800_bbp_write(rt2x00dev, 159, bbp);
 9359}
 9360
 9361static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx,
 9362			       u8 alc_idx, u8 dc_result[][RF_ALC_NUM][2])
 9363{
 9364	u32 p0 = 0, p1 = 0, pf = 0;
 9365	s8 idx0 = 0, idx1 = 0;
 9366	u8 idxf[] = {0x00, 0x00};
 9367	u8 ibit = 0x20;
 9368	u8 iorq;
 9369	s8 bidx;
 9370
 9371	rt2800_bbp_write(rt2x00dev, 158, 0xb0);
 9372	rt2800_bbp_write(rt2x00dev, 159, 0x80);
 9373
 9374	for (bidx = 5; bidx >= 0; bidx--) {
 9375		for (iorq = 0; iorq <= 1; iorq++) {
 9376			if (idxf[iorq] == 0x20) {
 9377				idx0 = 0x20;
 9378				p0 = pf;
 9379			} else {
 9380				idx0 = idxf[iorq] - ibit;
 9381				idx0 = idx0 & 0x3F;
 9382				rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx0);
 9383				p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
 9384			}
 9385
 9386			idx1 = idxf[iorq] + (bidx == 5 ? 0 : ibit);
 9387			idx1 = idx1 & 0x3F;
 9388			rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx1);
 9389			p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
 9390
 9391			rt2x00_dbg(rt2x00dev, "alc=%u, IorQ=%u, idx_final=%2x\n",
 9392				   alc_idx, iorq, idxf[iorq]);
 9393			rt2x00_dbg(rt2x00dev, "p0=%x, p1=%x, pf=%x, idx_0=%x, idx_1=%x, ibit=%x\n",
 9394				   p0, p1, pf, idx0, idx1, ibit);
 9395
 9396			if (bidx != 5 && pf <= p0 && pf < p1) {
 9397				/* no need to adjust idxf[] */;
 9398			} else if (p0 < p1) {
 9399				pf = p0;
 9400				idxf[iorq] = idx0 & 0x3F;
 9401			} else {
 9402				pf = p1;
 9403				idxf[iorq] = idx1 & 0x3F;
 9404			}
 9405			rt2x00_dbg(rt2x00dev, "IorQ=%u, idx_final[%u]:%x, pf:%8x\n",
 9406				   iorq, iorq, idxf[iorq], pf);
 9407
 9408			rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idxf[iorq]);
 9409		}
 9410		ibit = ibit >> 1;
 9411	}
 9412	dc_result[ch_idx][alc_idx][0] = idxf[0];
 9413	dc_result[ch_idx][alc_idx][1] = idxf[1];
 9414}
 9415
 9416static void rt2800_iq_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 *ges, u8 *pes)
 9417{
 9418	u32 p0 = 0, p1 = 0, pf = 0;
 9419	s8 perr = 0, gerr = 0, iq_err = 0;
 9420	s8 pef = 0, gef = 0;
 9421	s8 psta, pend;
 9422	s8 gsta, gend;
 9423
 9424	u8 ibit = 0x20;
 9425	u8 first_search = 0x00, touch_neg_max = 0x00;
 9426	s8 idx0 = 0, idx1 = 0;
 9427	u8 gop;
 9428	u8 bbp = 0;
 9429	s8 bidx;
 9430
 9431	for (bidx = 5; bidx >= 1; bidx--) {
 9432		for (gop = 0; gop < 2; gop++) {
 9433			if (gop == 1 || bidx < 4) {
 9434				if (gop == 0)
 9435					iq_err = gerr;
 9436				else
 9437					iq_err = perr;
 9438
 9439				first_search = (gop == 0) ? (bidx == 3) : (bidx == 5);
 9440				touch_neg_max = (gop) ? ((iq_err & 0x0F) == 0x08) :
 9441							((iq_err & 0x3F) == 0x20);
 9442
 9443				if (touch_neg_max) {
 9444					p0 = pf;
 9445					idx0 = iq_err;
 9446				} else {
 9447					idx0 = iq_err - ibit;
 9448					bbp = (ch_idx == 0) ? ((gop == 0) ? 0x28 : 0x29) :
 9449							      ((gop == 0) ? 0x46 : 0x47);
 9450
 9451					rt2800_bbp_write(rt2x00dev, 158, bbp);
 9452					rt2800_bbp_write(rt2x00dev, 159, idx0);
 9453
 9454					p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
 9455				}
 9456
 9457				idx1 = iq_err + (first_search ? 0 : ibit);
 9458				idx1 = (gop == 0) ? (idx1 & 0x0F) : (idx1 & 0x3F);
 9459
 9460				bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 :
 9461				      (gop == 0) ? 0x46 : 0x47;
 9462
 9463				rt2800_bbp_write(rt2x00dev, 158, bbp);
 9464				rt2800_bbp_write(rt2x00dev, 159, idx1);
 9465
 9466				p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
 9467
 9468				rt2x00_dbg(rt2x00dev,
 9469					   "p0=%x, p1=%x, pwer_final=%x, idx0=%x, idx1=%x, iq_err=%x, gop=%d, ibit=%x\n",
 9470					   p0, p1, pf, idx0, idx1, iq_err, gop, ibit);
 9471
 9472				if (!(!first_search && pf <= p0 && pf < p1)) {
 9473					if (p0 < p1) {
 9474						pf = p0;
 9475						iq_err = idx0;
 9476					} else {
 9477						pf = p1;
 9478						iq_err = idx1;
 9479					}
 9480				}
 9481
 9482				bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 :
 9483						      (gop == 0) ? 0x46 : 0x47;
 9484
 9485				rt2800_bbp_write(rt2x00dev, 158, bbp);
 9486				rt2800_bbp_write(rt2x00dev, 159, iq_err);
 9487
 9488				if (gop == 0)
 9489					gerr = iq_err;
 9490				else
 9491					perr = iq_err;
 9492
 9493				rt2x00_dbg(rt2x00dev, "IQCalibration pf=%8x (%2x, %2x) !\n",
 9494					   pf, gerr & 0x0F, perr & 0x3F);
 9495			}
 9496		}
 9497
 9498		if (bidx > 0)
 9499			ibit = (ibit >> 1);
 9500	}
 9501	gerr = (gerr & 0x08) ? (gerr & 0x0F) - 0x10 : (gerr & 0x0F);
 9502	perr = (perr & 0x20) ? (perr & 0x3F) - 0x40 : (perr & 0x3F);
 9503
 9504	gerr = (gerr < -0x07) ? -0x07 : (gerr > 0x05) ? 0x05 : gerr;
 9505	gsta = gerr - 1;
 9506	gend = gerr + 2;
 9507
 9508	perr = (perr < -0x1f) ? -0x1f : (perr > 0x1d) ? 0x1d : perr;
 9509	psta = perr - 1;
 9510	pend = perr + 2;
 9511
 9512	for (gef = gsta; gef <= gend; gef = gef + 1)
 9513		for (pef = psta; pef <= pend; pef = pef + 1) {
 9514			bbp = (ch_idx == 0) ? 0x28 : 0x46;
 9515			rt2800_bbp_write(rt2x00dev, 158, bbp);
 9516			rt2800_bbp_write(rt2x00dev, 159, gef & 0x0F);
 9517
 9518			bbp = (ch_idx == 0) ? 0x29 : 0x47;
 9519			rt2800_bbp_write(rt2x00dev, 158, bbp);
 9520			rt2800_bbp_write(rt2x00dev, 159, pef & 0x3F);
 9521
 9522			p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
 9523			if (gef == gsta && pef == psta) {
 9524				pf = p1;
 9525				gerr = gef;
 9526				perr = pef;
 9527			} else if (pf > p1) {
 9528				pf = p1;
 9529				gerr = gef;
 9530				perr = pef;
 9531			}
 9532			rt2x00_dbg(rt2x00dev, "Fine IQCalibration p1=%8x pf=%8x (%2x, %2x) !\n",
 9533				   p1, pf, gef & 0x0F, pef & 0x3F);
 9534		}
 9535
 9536	ges[ch_idx] = gerr & 0x0F;
 9537	pes[ch_idx] = perr & 0x3F;
 9538}
 9539
 9540static void rt2800_rf_aux_tx0_loopback(struct rt2x00_dev *rt2x00dev)
 9541{
 9542	rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x21);
 9543	rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x10);
 9544	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
 9545	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x1b);
 9546	rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, 0x81);
 9547	rt2800_rfcsr_write_bank(rt2x00dev, 4, 2, 0x81);
 9548	rt2800_rfcsr_write_bank(rt2x00dev, 4, 34, 0xee);
 9549	rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, 0x2d);
 9550	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x2d);
 9551	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);
 9552	rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xd7);
 9553	rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0xa2);
 9554	rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);
 9555}
 9556
 9557static void rt2800_rf_aux_tx1_loopback(struct rt2x00_dev *rt2x00dev)
 9558{
 9559	rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x22);
 9560	rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x20);
 9561	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
 9562	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x4b);
 9563	rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, 0x81);
 9564	rt2800_rfcsr_write_bank(rt2x00dev, 6, 2, 0x81);
 9565	rt2800_rfcsr_write_bank(rt2x00dev, 6, 34, 0xee);
 9566	rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, 0x2d);
 9567	rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, 0x2d);
 9568	rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, 0x80);
 9569	rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, 0xd7);
 9570	rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, 0xa2);
 9571	rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, 0x20);
 9572}
 9573
 9574static void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev)
 9575{
 9576	struct rf_reg_pair rf_store[CHAIN_NUM][13];
 9577	u32 macorg1 = 0;
 9578	u32 macorg2 = 0;
 9579	u32 macorg3 = 0;
 9580	u32 macorg4 = 0;
 9581	u32 macorg5 = 0;
 9582	u32 orig528 = 0;
 9583	u32 orig52c = 0;
 9584
 9585	u32 savemacsysctrl = 0;
 9586	u32 macvalue = 0;
 9587	u32 mac13b8 = 0;
 9588	u32 p0 = 0, p1 = 0;
 9589	u32 p0_idx10 = 0, p1_idx10 = 0;
 9590
 9591	u8 rfvalue;
 9592	u8 loft_dc_search_result[CHAIN_NUM][RF_ALC_NUM][2];
 9593	u8 ger[CHAIN_NUM], per[CHAIN_NUM];
 9594
 9595	u8 vga_gain[] = {14, 14};
 9596	u8 bbp = 0, ch_idx = 0, rf_alc_idx = 0, idx = 0;
 9597	u8 bbpr30, rfb0r39, rfb0r42;
 9598	u8 bbpr1;
 9599	u8 bbpr4;
 9600	u8 bbpr241, bbpr242;
 9601	u8 count_step;
 9602
 9603	static const u8 rf_gain[] = {0x00, 0x01, 0x02, 0x04, 0x08, 0x0c};
 9604	static const u8 rfvga_gain_table[] = {0x24, 0x25, 0x26, 0x27, 0x28, 0x2c, 0x2d, 0x2e, 0x2f, 0x30,
 9605					      0x31, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3F};
 9606	static const u8 bbp_2324gain[] = {0x16, 0x14, 0x12, 0x10, 0x0c, 0x08};
 9607
 9608	savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
 9609	macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
 9610	macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
 9611	macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
 9612	macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
 9613	macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
 9614	mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
 9615	orig528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);
 9616	orig52c = rt2800_register_read(rt2x00dev, RF_BYPASS2);
 9617
 9618	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
 9619	macvalue &= (~0x04);
 9620	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
 9621
 9622	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
 9623		rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n");
 9624
 9625	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
 9626	macvalue &= (~0x08);
 9627	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
 9628
 9629	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
 9630		rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n");
 9631
 9632	for (ch_idx = 0; ch_idx < 2; ch_idx++)
 9633		rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
 9634
 9635	bbpr30 = rt2800_bbp_read(rt2x00dev, 30);
 9636	rfb0r39 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 39);
 9637	rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
 9638
 9639	rt2800_bbp_write(rt2x00dev, 30, 0x1F);
 9640	rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, 0x80);
 9641	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x5B);
 9642
 9643	rt2800_bbp_write(rt2x00dev, 23, 0x00);
 9644	rt2800_bbp_write(rt2x00dev, 24, 0x00);
 9645
 9646	rt2800_setbbptonegenerator(rt2x00dev);
 9647
 9648	for (ch_idx = 0; ch_idx < 2; ch_idx++) {
 9649		rt2800_bbp_write(rt2x00dev, 23, 0x00);
 9650		rt2800_bbp_write(rt2x00dev, 24, 0x00);
 9651		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00);
 9652		rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
 9653		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
 9654		rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
 9655		rt2800_register_write(rt2x00dev, 0x13b8, 0x10);
 9656		udelay(1);
 9657
 9658		if (ch_idx == 0)
 9659			rt2800_rf_aux_tx0_loopback(rt2x00dev);
 9660		else
 9661			rt2800_rf_aux_tx1_loopback(rt2x00dev);
 9662
 9663		udelay(1);
 9664
 9665		if (ch_idx == 0)
 9666			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
 9667		else
 9668			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
 9669
 9670		rt2800_bbp_write(rt2x00dev, 158, 0x05);
 9671		rt2800_bbp_write(rt2x00dev, 159, 0x00);
 9672
 9673		rt2800_bbp_write(rt2x00dev, 158, 0x01);
 9674		if (ch_idx == 0)
 9675			rt2800_bbp_write(rt2x00dev, 159, 0x00);
 9676		else
 9677			rt2800_bbp_write(rt2x00dev, 159, 0x01);
 9678
 9679		vga_gain[ch_idx] = 18;
 9680		for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
 9681			rt2800_bbp_write(rt2x00dev, 23, bbp_2324gain[rf_alc_idx]);
 9682			rt2800_bbp_write(rt2x00dev, 24, bbp_2324gain[rf_alc_idx]);
 9683
 9684			macvalue = rt2800_register_read(rt2x00dev, RF_CONTROL3);
 9685			macvalue &= (~0x0000F1F1);
 9686			macvalue |= (rf_gain[rf_alc_idx] << 4);
 9687			macvalue |= (rf_gain[rf_alc_idx] << 12);
 9688			rt2800_register_write(rt2x00dev, RF_CONTROL3, macvalue);
 9689			macvalue = (0x0000F1F1);
 9690			rt2800_register_write(rt2x00dev, RF_BYPASS3, macvalue);
 9691
 9692			if (rf_alc_idx == 0) {
 9693				rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x21);
 9694				for (; vga_gain[ch_idx] > 0;
 9695				     vga_gain[ch_idx] = vga_gain[ch_idx] - 2) {
 9696					rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
 9697					rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
 9698					rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
 9699					rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
 9700					rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
 9701					p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
 9702					rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x21);
 9703					p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
 9704					rt2x00_dbg(rt2x00dev, "LOFT AGC %d %d\n", p0, p1);
 9705					if ((p0 < 7000 * 7000) && (p1 < (7000 * 7000)))
 9706						break;
 9707				}
 9708
 9709				rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
 9710				rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
 9711
 9712				rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx],
 9713					   rfvga_gain_table[vga_gain[ch_idx]]);
 9714			}
 9715
 9716			rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
 9717
 9718			rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
 9719			rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
 9720
 9721			rt2800_loft_search(rt2x00dev, ch_idx, rf_alc_idx, loft_dc_search_result);
 9722		}
 9723	}
 9724
 9725	for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
 9726		for (idx = 0; idx < 4; idx++) {
 9727			rt2800_bbp_write(rt2x00dev, 158, 0xB0);
 9728			bbp = (idx << 2) + rf_alc_idx;
 9729			rt2800_bbp_write(rt2x00dev, 159, bbp);
 9730			rt2x00_dbg(rt2x00dev, " ALC %2x,", bbp);
 9731
 9732			rt2800_bbp_write(rt2x00dev, 158, 0xb1);
 9733			bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x00];
 9734			bbp = bbp & 0x3F;
 9735			rt2800_bbp_write(rt2x00dev, 159, bbp);
 9736			rt2x00_dbg(rt2x00dev, " I0 %2x,", bbp);
 9737
 9738			rt2800_bbp_write(rt2x00dev, 158, 0xb2);
 9739			bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x01];
 9740			bbp = bbp & 0x3F;
 9741			rt2800_bbp_write(rt2x00dev, 159, bbp);
 9742			rt2x00_dbg(rt2x00dev, " Q0 %2x,", bbp);
 9743
 9744			rt2800_bbp_write(rt2x00dev, 158, 0xb8);
 9745			bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x00];
 9746			bbp = bbp & 0x3F;
 9747			rt2800_bbp_write(rt2x00dev, 159, bbp);
 9748			rt2x00_dbg(rt2x00dev, " I1 %2x,", bbp);
 9749
 9750			rt2800_bbp_write(rt2x00dev, 158, 0xb9);
 9751			bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x01];
 9752			bbp = bbp & 0x3F;
 9753			rt2800_bbp_write(rt2x00dev, 159, bbp);
 9754			rt2x00_dbg(rt2x00dev, " Q1 %2x\n", bbp);
 9755		}
 9756	}
 9757
 9758	rt2800_bbp_write(rt2x00dev, 23, 0x00);
 9759	rt2800_bbp_write(rt2x00dev, 24, 0x00);
 9760
 9761	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
 9762
 9763	rt2800_bbp_write(rt2x00dev, 158, 0x00);
 9764	rt2800_bbp_write(rt2x00dev, 159, 0x00);
 9765
 9766	bbp = 0x00;
 9767	rt2800_bbp_write(rt2x00dev, 244, 0x00);
 9768
 9769	rt2800_bbp_write(rt2x00dev, 21, 0x01);
 9770	udelay(1);
 9771	rt2800_bbp_write(rt2x00dev, 21, 0x00);
 9772
 9773	rt2800_rf_configrecover(rt2x00dev, rf_store);
 9774
 9775	rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
 9776	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
 9777	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
 9778	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
 9779	rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
 9780	udelay(1);
 9781	rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
 9782	rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
 9783	rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
 9784	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
 9785	rt2800_register_write(rt2x00dev, RF_CONTROL2, orig528);
 9786	rt2800_register_write(rt2x00dev, RF_BYPASS2, orig52c);
 9787	rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
 9788
 9789	savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
 9790	macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
 9791	macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
 9792	macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
 9793	macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
 9794	macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
 9795
 9796	bbpr1 = rt2800_bbp_read(rt2x00dev, 1);
 9797	bbpr4 = rt2800_bbp_read(rt2x00dev, 4);
 9798	bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
 9799	bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
 9800	mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
 9801
 9802	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
 9803	macvalue &= (~0x04);
 9804	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
 9805
 9806	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
 9807		rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n");
 9808
 9809	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
 9810	macvalue &= (~0x08);
 9811	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
 9812
 9813	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
 9814		rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n");
 9815
 9816	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
 9817		rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000101);
 9818		rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
 9819	}
 9820
 9821	rt2800_bbp_write(rt2x00dev, 23, 0x00);
 9822	rt2800_bbp_write(rt2x00dev, 24, 0x00);
 9823
 9824	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
 9825		rt2800_bbp_write(rt2x00dev, 4, bbpr4 & (~0x18));
 9826		rt2800_bbp_write(rt2x00dev, 21, 0x01);
 9827		udelay(1);
 9828		rt2800_bbp_write(rt2x00dev, 21, 0x00);
 9829
 9830		rt2800_bbp_write(rt2x00dev, 241, 0x14);
 9831		rt2800_bbp_write(rt2x00dev, 242, 0x80);
 9832		rt2800_bbp_write(rt2x00dev, 244, 0x31);
 9833	} else {
 9834		rt2800_setbbptonegenerator(rt2x00dev);
 9835	}
 9836
 9837	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
 9838	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
 9839	udelay(1);
 9840
 9841	rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
 9842
 9843	if (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
 9844		rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000000);
 9845		rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
 9846	}
 9847
 9848	rt2800_register_write(rt2x00dev, 0x13b8, 0x00000010);
 9849
 9850	for (ch_idx = 0; ch_idx < 2; ch_idx++)
 9851		rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
 9852
 9853	rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x3B);
 9854	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x3B);
 9855
 9856	rt2800_bbp_write(rt2x00dev, 158, 0x03);
 9857	rt2800_bbp_write(rt2x00dev, 159, 0x60);
 9858	rt2800_bbp_write(rt2x00dev, 158, 0xB0);
 9859	rt2800_bbp_write(rt2x00dev, 159, 0x80);
 9860
 9861	for (ch_idx = 0; ch_idx < 2; ch_idx++) {
 9862		rt2800_bbp_write(rt2x00dev, 23, 0x00);
 9863		rt2800_bbp_write(rt2x00dev, 24, 0x00);
 9864
 9865		if (ch_idx == 0) {
 9866			rt2800_bbp_write(rt2x00dev, 158, 0x01);
 9867			rt2800_bbp_write(rt2x00dev, 159, 0x00);
 9868			if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
 9869				bbp = bbpr1 & (~0x18);
 9870				bbp = bbp | 0x00;
 9871				rt2800_bbp_write(rt2x00dev, 1, bbp);
 9872			}
 9873			rt2800_rf_aux_tx0_loopback(rt2x00dev);
 9874			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
 9875		} else {
 9876			rt2800_bbp_write(rt2x00dev, 158, 0x01);
 9877			rt2800_bbp_write(rt2x00dev, 159, 0x01);
 9878			if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {
 9879				bbp = bbpr1 & (~0x18);
 9880				bbp = bbp | 0x08;
 9881				rt2800_bbp_write(rt2x00dev, 1, bbp);
 9882			}
 9883			rt2800_rf_aux_tx1_loopback(rt2x00dev);
 9884			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
 9885		}
 9886
 9887		rt2800_bbp_write(rt2x00dev, 158, 0x05);
 9888		rt2800_bbp_write(rt2x00dev, 159, 0x04);
 9889
 9890		bbp = (ch_idx == 0) ? 0x28 : 0x46;
 9891		rt2800_bbp_write(rt2x00dev, 158, bbp);
 9892		rt2800_bbp_write(rt2x00dev, 159, 0x00);
 9893
 9894		if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
 9895			rt2800_bbp_write(rt2x00dev, 23, 0x06);
 9896			rt2800_bbp_write(rt2x00dev, 24, 0x06);
 9897			count_step = 1;
 9898		} else {
 9899			rt2800_bbp_write(rt2x00dev, 23, 0x1F);
 9900			rt2800_bbp_write(rt2x00dev, 24, 0x1F);
 9901			count_step = 2;
 9902		}
 9903
 9904		for (; vga_gain[ch_idx] < 19; vga_gain[ch_idx] = (vga_gain[ch_idx] + count_step)) {
 9905			rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
 9906			rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
 9907			rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
 9908
 9909			bbp = (ch_idx == 0) ? 0x29 : 0x47;
 9910			rt2800_bbp_write(rt2x00dev, 158, bbp);
 9911			rt2800_bbp_write(rt2x00dev, 159, 0x00);
 9912			p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
 9913			if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
 9914				p0_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
 9915
 9916			bbp = (ch_idx == 0) ? 0x29 : 0x47;
 9917			rt2800_bbp_write(rt2x00dev, 158, bbp);
 9918			rt2800_bbp_write(rt2x00dev, 159, 0x21);
 9919			p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
 9920			if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags))
 9921				p1_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
 9922
 9923			rt2x00_dbg(rt2x00dev, "IQ AGC %d %d\n", p0, p1);
 9924
 9925			if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
 9926				rt2x00_dbg(rt2x00dev, "IQ AGC IDX 10 %d %d\n", p0_idx10, p1_idx10);
 9927				if ((p0_idx10 > 7000 * 7000) || (p1_idx10 > 7000 * 7000)) {
 9928					if (vga_gain[ch_idx] != 0)
 9929						vga_gain[ch_idx] = vga_gain[ch_idx] - 1;
 9930					break;
 9931				}
 9932			}
 9933
 9934			if ((p0 > 2500 * 2500) || (p1 > 2500 * 2500))
 9935				break;
 9936		}
 9937
 9938		if (vga_gain[ch_idx] > 18)
 9939			vga_gain[ch_idx] = 18;
 9940		rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx],
 9941			   rfvga_gain_table[vga_gain[ch_idx]]);
 9942
 9943		bbp = (ch_idx == 0) ? 0x29 : 0x47;
 9944		rt2800_bbp_write(rt2x00dev, 158, bbp);
 9945		rt2800_bbp_write(rt2x00dev, 159, 0x00);
 9946
 9947		rt2800_iq_search(rt2x00dev, ch_idx, ger, per);
 9948	}
 9949
 9950	rt2800_bbp_write(rt2x00dev, 23, 0x00);
 9951	rt2800_bbp_write(rt2x00dev, 24, 0x00);
 9952	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
 9953
 9954	rt2800_bbp_write(rt2x00dev, 158, 0x28);
 9955	bbp = ger[CHAIN_0] & 0x0F;
 9956	rt2800_bbp_write(rt2x00dev, 159, bbp);
 9957
 9958	rt2800_bbp_write(rt2x00dev, 158, 0x29);
 9959	bbp = per[CHAIN_0] & 0x3F;
 9960	rt2800_bbp_write(rt2x00dev, 159, bbp);
 9961
 9962	rt2800_bbp_write(rt2x00dev, 158, 0x46);
 9963	bbp = ger[CHAIN_1] & 0x0F;
 9964	rt2800_bbp_write(rt2x00dev, 159, bbp);
 9965
 9966	rt2800_bbp_write(rt2x00dev, 158, 0x47);
 9967	bbp = per[CHAIN_1] & 0x3F;
 9968	rt2800_bbp_write(rt2x00dev, 159, bbp);
 9969
 9970	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
 9971		rt2800_bbp_write(rt2x00dev, 1, bbpr1);
 9972		rt2800_bbp_write(rt2x00dev, 241, bbpr241);
 9973		rt2800_bbp_write(rt2x00dev, 242, bbpr242);
 9974	}
 9975	rt2800_bbp_write(rt2x00dev, 244, 0x00);
 9976
 9977	rt2800_bbp_write(rt2x00dev, 158, 0x00);
 9978	rt2800_bbp_write(rt2x00dev, 159, 0x00);
 9979	rt2800_bbp_write(rt2x00dev, 158, 0xB0);
 9980	rt2800_bbp_write(rt2x00dev, 159, 0x00);
 9981
 9982	rt2800_bbp_write(rt2x00dev, 30, bbpr30);
 9983	rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, rfb0r39);
 9984	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
 9985
 9986	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
 9987		rt2800_bbp_write(rt2x00dev, 4, bbpr4);
 9988
 9989	rt2800_bbp_write(rt2x00dev, 21, 0x01);
 9990	udelay(1);
 9991	rt2800_bbp_write(rt2x00dev, 21, 0x00);
 9992
 9993	rt2800_rf_configrecover(rt2x00dev, rf_store);
 9994
 9995	rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
 9996	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
 9997	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
 9998	rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
 9999	udelay(1);
10000	rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
10001	rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
10002	rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
10003	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
10004	rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
10005}
10006
10007static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
10008				       bool set_bw, bool is_ht40)
10009{
10010	u8 bbp_val;
10011
10012	bbp_val = rt2800_bbp_read(rt2x00dev, 21);
10013	bbp_val |= 0x1;
10014	rt2800_bbp_write(rt2x00dev, 21, bbp_val);
10015	usleep_range(100, 200);
10016
10017	if (set_bw) {
10018		bbp_val = rt2800_bbp_read(rt2x00dev, 4);
10019		rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40);
10020		rt2800_bbp_write(rt2x00dev, 4, bbp_val);
10021		usleep_range(100, 200);
10022	}
10023
10024	bbp_val = rt2800_bbp_read(rt2x00dev, 21);
10025	bbp_val &= (~0x1);
10026	rt2800_bbp_write(rt2x00dev, 21, bbp_val);
10027	usleep_range(100, 200);
10028}
10029
10030static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)
10031{
10032	u8 rf_val;
10033
10034	if (btxcal)
10035		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
10036	else
10037		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02);
10038
10039	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06);
10040
10041	rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
10042	rf_val |= 0x80;
10043	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val);
10044
10045	if (btxcal) {
10046		rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1);
10047		rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20);
10048		rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
10049		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
10050		rf_val &= (~0x3F);
10051		rf_val |= 0x3F;
10052		rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
10053		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
10054		rf_val &= (~0x3F);
10055		rf_val |= 0x3F;
10056		rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
10057		rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31);
10058	} else {
10059		rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1);
10060		rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18);
10061		rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
10062		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
10063		rf_val &= (~0x3F);
10064		rf_val |= 0x34;
10065		rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
10066		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
10067		rf_val &= (~0x3F);
10068		rf_val |= 0x34;
10069		rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
10070	}
10071
10072	return 0;
10073}
10074
10075static s8 rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
10076{
10077	unsigned int cnt;
10078	u8 bbp_val;
10079	s8 cal_val;
10080
10081	rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
10082
10083	cnt = 0;
10084	do {
10085		usleep_range(500, 2000);
10086		bbp_val = rt2800_bbp_read(rt2x00dev, 159);
10087		if (bbp_val == 0x02 || cnt == 20)
10088			break;
10089
10090		cnt++;
10091	} while (cnt < 20);
10092
10093	bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39);
10094	cal_val = bbp_val & 0x7F;
10095	if (cal_val >= 0x40)
10096		cal_val -= 128;
10097
10098	return cal_val;
10099}
10100
10101static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
10102					 bool btxcal)
10103{
10104	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
10105	u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc;
10106	u8 filter_target;
10107	u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02;
10108	u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31;
10109	int loop = 0, is_ht40, cnt;
10110	u8 bbp_val, rf_val;
10111	s8 cal_r32_init, cal_r32_val, cal_diff;
10112	u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05;
10113	u8 saverfb5r06, saverfb5r07;
10114	u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20;
10115	u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41;
10116	u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46;
10117	u8 saverfb5r58, saverfb5r59;
10118	u8 savebbp159r0, savebbp159r2, savebbpr23;
10119	u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0;
10120
10121	/* Save MAC registers */
10122	MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
10123	MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
10124
10125	/* save BBP registers */
10126	savebbpr23 = rt2800_bbp_read(rt2x00dev, 23);
10127
10128	savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0);
10129	savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2);
10130
10131	/* Save RF registers */
10132	saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
10133	saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
10134	saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
10135	saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
10136	saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5);
10137	saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
10138	saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
10139	saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
10140	saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
10141	saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
10142	saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
10143	saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
10144
10145	saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37);
10146	saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38);
10147	saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39);
10148	saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40);
10149	saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41);
10150	saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42);
10151	saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43);
10152	saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44);
10153	saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45);
10154	saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46);
10155
10156	saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
10157	saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
10158
10159	rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
10160	rf_val |= 0x3;
10161	rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
10162
10163	rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
10164	rf_val |= 0x1;
10165	rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val);
10166
10167	cnt = 0;
10168	do {
10169		usleep_range(500, 2000);
10170		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
10171		if (((rf_val & 0x1) == 0x00) || (cnt == 40))
10172			break;
10173		cnt++;
10174	} while (cnt < 40);
10175
10176	rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
10177	rf_val &= (~0x3);
10178	rf_val |= 0x1;
10179	rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
10180
10181	/* I-3 */
10182	bbp_val = rt2800_bbp_read(rt2x00dev, 23);
10183	bbp_val &= (~0x1F);
10184	bbp_val |= 0x10;
10185	rt2800_bbp_write(rt2x00dev, 23, bbp_val);
10186
10187	do {
10188		/* I-4,5,6,7,8,9 */
10189		if (loop == 0) {
10190			is_ht40 = false;
10191
10192			if (btxcal)
10193				filter_target = tx_filter_target_20m;
10194			else
10195				filter_target = rx_filter_target_20m;
10196		} else {
10197			is_ht40 = true;
10198
10199			if (btxcal)
10200				filter_target = tx_filter_target_40m;
10201			else
10202				filter_target = rx_filter_target_40m;
10203		}
10204
10205		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
10206		rf_val &= (~0x04);
10207		if (loop == 1)
10208			rf_val |= 0x4;
10209
10210		rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val);
10211
10212		rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40);
10213
10214		rt2800_rf_lp_config(rt2x00dev, btxcal);
10215		if (btxcal) {
10216			tx_agc_fc = 0;
10217			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
10218			rf_val &= (~0x7F);
10219			rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
10220			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
10221			rf_val &= (~0x7F);
10222			rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
10223		} else {
10224			rx_agc_fc = 0;
10225			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
10226			rf_val &= (~0x7F);
10227			rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
10228			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
10229			rf_val &= (~0x7F);
10230			rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
10231		}
10232
10233		usleep_range(1000, 2000);
10234
10235		bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
10236		bbp_val &= (~0x6);
10237		rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
10238
10239		rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
10240
10241		cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
10242
10243		bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
10244		bbp_val |= 0x6;
10245		rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
10246do_cal:
10247		if (btxcal) {
10248			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
10249			rf_val &= (~0x7F);
10250			rf_val |= tx_agc_fc;
10251			rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
10252			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
10253			rf_val &= (~0x7F);
10254			rf_val |= tx_agc_fc;
10255			rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
10256		} else {
10257			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
10258			rf_val &= (~0x7F);
10259			rf_val |= rx_agc_fc;
10260			rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
10261			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
10262			rf_val &= (~0x7F);
10263			rf_val |= rx_agc_fc;
10264			rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
10265		}
10266
10267		usleep_range(500, 1000);
10268
10269		rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
10270
10271		cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
10272
10273		cal_diff = cal_r32_init - cal_r32_val;
10274
10275		if (btxcal)
10276			cmm_agc_fc = tx_agc_fc;
10277		else
10278			cmm_agc_fc = rx_agc_fc;
10279
10280		if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) ||
10281		    ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) {
10282			if (btxcal)
10283				tx_agc_fc = 0;
10284			else
10285				rx_agc_fc = 0;
10286		} else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) {
10287			if (btxcal)
10288				tx_agc_fc++;
10289			else
10290				rx_agc_fc++;
10291			goto do_cal;
10292		}
10293
10294		if (btxcal) {
10295			if (loop == 0)
10296				drv_data->tx_calibration_bw20 = tx_agc_fc;
10297			else
10298				drv_data->tx_calibration_bw40 = tx_agc_fc;
10299		} else {
10300			if (loop == 0)
10301				drv_data->rx_calibration_bw20 = rx_agc_fc;
10302			else
10303				drv_data->rx_calibration_bw40 = rx_agc_fc;
10304		}
10305
10306		loop++;
10307	} while (loop <= 1);
10308
10309	rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00);
10310	rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01);
10311	rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03);
10312	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04);
10313	rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05);
10314	rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06);
10315	rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07);
10316	rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08);
10317	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
10318	rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
10319	rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
10320	rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
10321
10322	rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37);
10323	rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38);
10324	rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39);
10325	rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40);
10326	rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41);
10327	rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42);
10328	rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43);
10329	rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44);
10330	rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45);
10331	rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46);
10332
10333	rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58);
10334	rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59);
10335
10336	rt2800_bbp_write(rt2x00dev, 23, savebbpr23);
10337
10338	rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0);
10339	rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2);
10340
10341	bbp_val = rt2800_bbp_read(rt2x00dev, 4);
10342	rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH,
10343			  2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
10344	rt2800_bbp_write(rt2x00dev, 4, bbp_val);
10345
10346	rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
10347	rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
10348}
10349
10350static void rt2800_restore_rf_bbp_rt6352(struct rt2x00_dev *rt2x00dev)
10351{
10352	if (rt2x00_has_cap_external_pa(rt2x00dev)) {
10353		rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0);
10354		rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0);
10355	}
10356
10357	if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
10358		rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
10359		rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
10360		rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
10361	}
10362
10363	if (rt2x00_has_cap_external_pa(rt2x00dev)) {
10364		rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xd3);
10365		rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xb3);
10366		rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xd5);
10367		rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
10368		rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6c);
10369		rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xfc);
10370		rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1f);
10371		rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
10372		rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
10373		rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xff);
10374		rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1c);
10375		rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
10376		rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6b);
10377		rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xf7);
10378		rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
10379	}
10380
10381	if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
10382		rt2800_bbp_write(rt2x00dev, 75, 0x60);
10383		rt2800_bbp_write(rt2x00dev, 76, 0x44);
10384		rt2800_bbp_write(rt2x00dev, 79, 0x1c);
10385		rt2800_bbp_write(rt2x00dev, 80, 0x0c);
10386		rt2800_bbp_write(rt2x00dev, 82, 0xB6);
10387	}
10388
10389	if (rt2x00_has_cap_external_pa(rt2x00dev)) {
10390		rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 0x3630363a);
10391		rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6c6c666c);
10392		rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6c6c666c);
10393	}
10394}
10395
10396static void rt2800_calibration_rt6352(struct rt2x00_dev *rt2x00dev)
10397{
10398	u32 reg;
10399
10400	if (rt2x00_has_cap_external_pa(rt2x00dev) ||
10401	    rt2x00_has_cap_external_lna_bg(rt2x00dev))
10402		rt2800_restore_rf_bbp_rt6352(rt2x00dev);
10403
10404	rt2800_r_calibration(rt2x00dev);
10405	rt2800_rf_self_txdc_cal(rt2x00dev);
10406	rt2800_rxdcoc_calibration(rt2x00dev);
10407	rt2800_bw_filter_calibration(rt2x00dev, true);
10408	rt2800_bw_filter_calibration(rt2x00dev, false);
10409	rt2800_loft_iq_calibration(rt2x00dev);
10410
10411	/* missing DPD calibration for internal PA devices */
10412
10413	rt2800_rxdcoc_calibration(rt2x00dev);
10414	rt2800_rxiq_calibration(rt2x00dev);
10415
10416	if (!rt2x00_has_cap_external_pa(rt2x00dev) &&
10417	    !rt2x00_has_cap_external_lna_bg(rt2x00dev))
10418		return;
10419
10420	if (rt2x00_has_cap_external_pa(rt2x00dev)) {
10421		reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
10422		reg |= 0x00000101;
10423		rt2800_register_write(rt2x00dev, RF_CONTROL3, reg);
10424
10425		reg = rt2800_register_read(rt2x00dev, RF_BYPASS3);
10426		reg |= 0x00000101;
10427		rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
10428	}
10429
10430	if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
10431		rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x66);
10432		rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x20);
10433		rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x42);
10434	}
10435
10436	if (rt2x00_has_cap_external_pa(rt2x00dev)) {
10437		rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73);
10438		rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73);
10439		rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73);
10440		rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
10441		rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xc8);
10442		rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xa4);
10443		rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05);
10444		rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
10445		rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xc8);
10446		rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xa4);
10447		rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05);
10448		rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27);
10449		rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xc8);
10450		rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xa4);
10451		rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05);
10452	}
10453
10454	if (rt2x00_has_cap_external_pa(rt2x00dev))
10455		rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00);
10456
10457	if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
10458		rt2800_bbp_write(rt2x00dev, 75, 0x68);
10459		rt2800_bbp_write(rt2x00dev, 76, 0x4c);
10460		rt2800_bbp_write(rt2x00dev, 79, 0x1c);
10461		rt2800_bbp_write(rt2x00dev, 80, 0x0c);
10462		rt2800_bbp_write(rt2x00dev, 82, 0xb6);
10463	}
10464
10465	if (rt2x00_has_cap_external_pa(rt2x00dev)) {
10466		rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 0x36303636);
10467		rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6c6c6b6c);
10468		rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6c6c6b6c);
10469	}
10470}
10471
10472static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
10473{
10474	/* Initialize RF central register to default value */
10475	rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
10476	rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
10477	rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
10478	rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
10479	rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
10480	rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
10481	rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
10482	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
10483	rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
10484	rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
10485	rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
10486	rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
10487	rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
10488	rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
10489	rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
10490	rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
10491	rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
10492	rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
10493	rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
10494	rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
10495	rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
10496	rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
10497	rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
10498	rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
10499	rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
10500	rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
10501	rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
10502	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
10503	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
10504	rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
10505	rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
10506	rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
10507	rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
10508	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
10509	rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
10510	rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
10511	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
10512	rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
10513	rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
10514	rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
10515	rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
10516	rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
10517	rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
10518	rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
10519
10520	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
10521	if (rt2800_clk_is_20mhz(rt2x00dev))
10522		rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
10523	else
10524		rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
10525	rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
10526	rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
10527	rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
10528	rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
10529	rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
10530	rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
10531	rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
10532	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
10533	rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
10534	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
10535	rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
10536	rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
10537	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
10538	rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
10539	rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
10540	rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
10541
10542	rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
10543	rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
10544	rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
10545
10546	/* Initialize RF channel register to default value */
10547	rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
10548	rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
10549	rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
10550	rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
10551	rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
10552	rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
10553	rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
10554	rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
10555	rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
10556	rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
10557	rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
10558	rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
10559	rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
10560	rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
10561	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
10562	rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
10563	rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
10564	rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
10565	rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
10566	rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
10567	rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
10568	rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
10569	rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
10570	rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
10571	rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
10572	rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
10573	rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
10574	rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
10575	rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
10576	rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
10577	rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
10578	rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
10579	rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
10580	rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
10581	rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
10582	rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
10583	rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
10584	rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
10585	rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
10586	rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
10587	rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
10588	rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
10589	rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
10590	rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
10591	rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
10592	rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
10593	rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
10594	rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
10595	rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
10596	rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
10597	rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
10598	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
10599	rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
10600	rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
10601	rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
10602	rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
10603	rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
10604	rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
10605	rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
10606	rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
10607
10608	rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
10609
10610	rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
10611	rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
10612	rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
10613	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
10614	rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
10615	rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
10616	rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
10617	rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
10618	rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
10619	rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
10620	rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
10621	rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
10622	rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
10623	rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
10624	rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
10625	rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
10626	rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
10627	rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
10628	rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
10629	rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
10630	rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
10631	rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
10632	rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
10633	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
10634	rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
10635	rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
10636	rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
10637	rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
10638	rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
10639	rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
10640
10641	rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
10642	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
10643	rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
10644	rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
10645	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
10646	rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
10647	rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
10648	rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
10649	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
10650
10651	rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
10652	rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
10653	rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
10654	rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
10655	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
10656	rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
10657
10658	/* Initialize RF channel register for DRQFN */
10659	rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
10660	rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
10661	rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
10662	rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
10663	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
10664	rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
10665	rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
10666	rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
10667
10668	/* Initialize RF DC calibration register to default value */
10669	rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
10670	rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
10671	rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
10672	rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
10673	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
10674	rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
10675	rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
10676	rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
10677	rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
10678	rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
10679	rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
10680	rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
10681	rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
10682	rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
10683	rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
10684	rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
10685	rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
10686	rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
10687	rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
10688	rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
10689	rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
10690	rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
10691	rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
10692	rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
10693	rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
10694	rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
10695	rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
10696	rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
10697	rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
10698	rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
10699	rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
10700	rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
10701	rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
10702	rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
10703	rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
10704	rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
10705	rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
10706	rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
10707	rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
10708	rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
10709	rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
10710	rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
10711	rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
10712	rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
10713	rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
10714	rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
10715	rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
10716	rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
10717	rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
10718	rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
10719	rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
10720	rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
10721	rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
10722	rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
10723	rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
10724	rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
10725	rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
10726	rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
10727	rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
10728
10729	rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
10730	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
10731	rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
10732
10733	rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
10734	rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
10735
10736	/* Do calibration and init PA/LNA */
10737	rt2800_calibration_rt6352(rt2x00dev);
10738}
10739
10740static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
10741{
10742	if (rt2800_is_305x_soc(rt2x00dev)) {
10743		rt2800_init_rfcsr_305x_soc(rt2x00dev);
10744		return;
10745	}
10746
10747	switch (rt2x00dev->chip.rt) {
10748	case RT3070:
10749	case RT3071:
10750	case RT3090:
10751		rt2800_init_rfcsr_30xx(rt2x00dev);
10752		break;
10753	case RT3290:
10754		rt2800_init_rfcsr_3290(rt2x00dev);
10755		break;
10756	case RT3352:
10757		rt2800_init_rfcsr_3352(rt2x00dev);
10758		break;
10759	case RT3390:
10760		rt2800_init_rfcsr_3390(rt2x00dev);
10761		break;
10762	case RT3883:
10763		rt2800_init_rfcsr_3883(rt2x00dev);
10764		break;
10765	case RT3572:
10766		rt2800_init_rfcsr_3572(rt2x00dev);
10767		break;
10768	case RT3593:
10769		rt2800_init_rfcsr_3593(rt2x00dev);
10770		break;
10771	case RT5350:
10772		rt2800_init_rfcsr_5350(rt2x00dev);
10773		break;
10774	case RT5390:
10775		rt2800_init_rfcsr_5390(rt2x00dev);
10776		break;
10777	case RT5392:
10778		rt2800_init_rfcsr_5392(rt2x00dev);
10779		break;
10780	case RT5592:
10781		rt2800_init_rfcsr_5592(rt2x00dev);
10782		break;
10783	case RT6352:
10784		rt2800_init_rfcsr_6352(rt2x00dev);
10785		break;
10786	}
10787}
10788
10789int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
10790{
10791	u32 reg;
10792	u16 word;
10793
10794	/*
10795	 * Initialize MAC registers.
10796	 */
10797	if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
10798		     rt2800_init_registers(rt2x00dev)))
10799		return -EIO;
10800
10801	/*
10802	 * Wait BBP/RF to wake up.
10803	 */
10804	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
10805		return -EIO;
10806
10807	/*
10808	 * Send signal during boot time to initialize firmware.
10809	 */
10810	rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
10811	rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
10812	if (rt2x00_is_usb(rt2x00dev))
10813		rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
10814	rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
10815	msleep(1);
10816
10817	/*
10818	 * Make sure BBP is up and running.
10819	 */
10820	if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
10821		return -EIO;
10822
10823	/*
10824	 * Initialize BBP/RF registers.
10825	 */
10826	rt2800_init_bbp(rt2x00dev);
10827	rt2800_init_rfcsr(rt2x00dev);
10828
10829	if (rt2x00_is_usb(rt2x00dev) &&
10830	    (rt2x00_rt(rt2x00dev, RT3070) ||
10831	     rt2x00_rt(rt2x00dev, RT3071) ||
10832	     rt2x00_rt(rt2x00dev, RT3572))) {
10833		udelay(200);
10834		rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
10835		udelay(10);
10836	}
10837
10838	/*
10839	 * Enable RX.
10840	 */
10841	reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
10842	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
10843	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
10844	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
10845
10846	udelay(50);
10847
10848	reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
10849	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
10850	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
10851	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
10852	rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
10853
10854	reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
10855	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
10856	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
10857	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
10858
10859	/*
10860	 * Initialize LED control
10861	 */
10862	word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF);
10863	rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
10864			   word & 0xff, (word >> 8) & 0xff);
10865
10866	word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF);
10867	rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
10868			   word & 0xff, (word >> 8) & 0xff);
10869
10870	word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY);
10871	rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
10872			   word & 0xff, (word >> 8) & 0xff);
10873
10874	return 0;
10875}
10876EXPORT_SYMBOL_GPL(rt2800_enable_radio);
10877
10878void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
10879{
10880	u32 reg;
10881
10882	rt2800_disable_wpdma(rt2x00dev);
10883
10884	/* Wait for DMA, ignore error */
10885	rt2800_wait_wpdma_ready(rt2x00dev);
10886
10887	reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
10888	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
10889	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
10890	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
10891}
10892EXPORT_SYMBOL_GPL(rt2800_disable_radio);
10893
10894int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
10895{
10896	u32 reg;
10897	u16 efuse_ctrl_reg;
10898
10899	if (rt2x00_rt(rt2x00dev, RT3290))
10900		efuse_ctrl_reg = EFUSE_CTRL_3290;
10901	else
10902		efuse_ctrl_reg = EFUSE_CTRL;
10903
10904	reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg);
10905	return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
10906}
10907EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
10908
10909static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
10910{
10911	u32 reg;
10912	u16 efuse_ctrl_reg;
10913	u16 efuse_data0_reg;
10914	u16 efuse_data1_reg;
10915	u16 efuse_data2_reg;
10916	u16 efuse_data3_reg;
10917
10918	if (rt2x00_rt(rt2x00dev, RT3290)) {
10919		efuse_ctrl_reg = EFUSE_CTRL_3290;
10920		efuse_data0_reg = EFUSE_DATA0_3290;
10921		efuse_data1_reg = EFUSE_DATA1_3290;
10922		efuse_data2_reg = EFUSE_DATA2_3290;
10923		efuse_data3_reg = EFUSE_DATA3_3290;
10924	} else {
10925		efuse_ctrl_reg = EFUSE_CTRL;
10926		efuse_data0_reg = EFUSE_DATA0;
10927		efuse_data1_reg = EFUSE_DATA1;
10928		efuse_data2_reg = EFUSE_DATA2;
10929		efuse_data3_reg = EFUSE_DATA3;
10930	}
10931	mutex_lock(&rt2x00dev->csr_mutex);
10932
10933	reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg);
10934	rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
10935	rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
10936	rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
10937	rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
10938
10939	/* Wait until the EEPROM has been loaded */
10940	rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
10941	/* Apparently the data is read from end to start */
10942	reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg);
10943	/* The returned value is in CPU order, but eeprom is le */
10944	*(__le32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
10945	reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg);
10946	*(__le32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
10947	reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg);
10948	*(__le32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
10949	reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg);
10950	*(__le32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
10951
10952	mutex_unlock(&rt2x00dev->csr_mutex);
10953}
10954
10955int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
10956{
10957	unsigned int i;
10958
10959	for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
10960		rt2800_efuse_read(rt2x00dev, i);
10961
10962	return 0;
10963}
10964EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
10965
10966int rt2800_read_eeprom_nvmem(struct rt2x00_dev *rt2x00dev)
10967{
10968	struct device_node *np = rt2x00dev->dev->of_node;
10969	unsigned int len = rt2x00dev->ops->eeprom_size;
10970	struct nvmem_cell *cell;
10971	const void *data;
10972	size_t retlen;
10973
10974	cell = of_nvmem_cell_get(np, "eeprom");
10975	if (IS_ERR(cell))
10976		return PTR_ERR(cell);
10977
10978	data = nvmem_cell_read(cell, &retlen);
10979	nvmem_cell_put(cell);
10980
10981	if (IS_ERR(data))
10982		return PTR_ERR(data);
10983
10984	if (retlen != len) {
10985		dev_err(rt2x00dev->dev, "invalid eeprom size, required: 0x%04x\n", len);
10986		kfree(data);
10987		return -EINVAL;
10988	}
10989
10990	memcpy(rt2x00dev->eeprom, data, len);
10991	kfree(data);
10992	return 0;
10993}
10994EXPORT_SYMBOL_GPL(rt2800_read_eeprom_nvmem);
10995
10996static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
10997{
10998	u16 word;
10999
11000	if (rt2x00_rt(rt2x00dev, RT3593) ||
11001	    rt2x00_rt(rt2x00dev, RT3883))
11002		return 0;
11003
11004	word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG);
11005	if ((word & 0x00ff) != 0x00ff)
11006		return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
11007
11008	return 0;
11009}
11010
11011static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
11012{
11013	u16 word;
11014
11015	if (rt2x00_rt(rt2x00dev, RT3593) ||
11016	    rt2x00_rt(rt2x00dev, RT3883))
11017		return 0;
11018
11019	word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A);
11020	if ((word & 0x00ff) != 0x00ff)
11021		return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
11022
11023	return 0;
11024}
11025
11026static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
11027{
11028	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
11029	u16 word;
11030	u8 *mac;
11031	u8 default_lna_gain;
11032	int retval;
11033
11034	/*
11035	 * Read the EEPROM.
11036	 */
11037	retval = rt2800_read_eeprom(rt2x00dev);
11038	if (retval)
11039		return retval;
11040
11041	/*
11042	 * Start validation of the data that has been read.
11043	 */
11044	mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
11045	retval = rt2x00lib_set_mac_address(rt2x00dev, mac);
11046	if (retval)
11047		return retval;
11048
11049	word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
11050	if (word == 0xffff) {
11051		rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
11052		rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
11053		rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
11054		rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
11055		rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
11056	} else if (rt2x00_rt(rt2x00dev, RT2860) ||
11057		   rt2x00_rt(rt2x00dev, RT2872)) {
11058		/*
11059		 * There is a max of 2 RX streams for RT28x0 series
11060		 */
11061		if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
11062			rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
11063		rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
11064	}
11065
11066	word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
11067	if (word == 0xffff) {
11068		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
11069		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
11070		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
11071		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
11072		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
11073		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
11074		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
11075		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
11076		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
11077		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
11078		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
11079		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
11080		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
11081		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
11082		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
11083		rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
11084		rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
11085	}
11086
11087	word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
11088	if ((word & 0x00ff) == 0x00ff) {
11089		rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
11090		rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
11091		rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
11092	}
11093	if ((word & 0xff00) == 0xff00) {
11094		rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
11095				   LED_MODE_TXRX_ACTIVITY);
11096		rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
11097		rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
11098		rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
11099		rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
11100		rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
11101		rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
11102	}
11103
11104	/*
11105	 * During the LNA validation we are going to use
11106	 * lna0 as correct value. Note that EEPROM_LNA
11107	 * is never validated.
11108	 */
11109	word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
11110	default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
11111
11112	word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
11113	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
11114		rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
11115	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
11116		rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
11117	rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
11118
11119	drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
11120
11121	word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
11122	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
11123		rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
11124	if (!rt2x00_rt(rt2x00dev, RT3593) &&
11125	    !rt2x00_rt(rt2x00dev, RT3883)) {
11126		if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
11127		    rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
11128			rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
11129					   default_lna_gain);
11130	}
11131	rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
11132
11133	drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
11134
11135	word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
11136	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
11137		rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
11138	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
11139		rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
11140	rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
11141
11142	word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
11143	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
11144		rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
11145	if (!rt2x00_rt(rt2x00dev, RT3593) &&
11146	    !rt2x00_rt(rt2x00dev, RT3883)) {
11147		if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
11148		    rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
11149			rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
11150					   default_lna_gain);
11151	}
11152	rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
11153
11154	if (rt2x00_rt(rt2x00dev, RT3593) ||
11155	    rt2x00_rt(rt2x00dev, RT3883)) {
11156		word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
11157		if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
11158		    rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
11159			rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
11160					   default_lna_gain);
11161		if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
11162		    rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
11163			rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
11164					   default_lna_gain);
11165		rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
11166	}
11167
11168	return 0;
11169}
11170
11171static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
11172{
11173	u16 value;
11174	u16 eeprom;
11175	u16 rf;
11176
11177	/*
11178	 * Read EEPROM word for configuration.
11179	 */
11180	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
11181
11182	/*
11183	 * Identify RF chipset by EEPROM value
11184	 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
11185	 * RT53xx: defined in "EEPROM_CHIP_ID" field
11186	 */
11187	if (rt2x00_rt(rt2x00dev, RT3290) ||
11188	    rt2x00_rt(rt2x00dev, RT5390) ||
11189	    rt2x00_rt(rt2x00dev, RT5392) ||
11190	    rt2x00_rt(rt2x00dev, RT6352))
11191		rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID);
11192	else if (rt2x00_rt(rt2x00dev, RT3352))
11193		rf = RF3322;
11194	else if (rt2x00_rt(rt2x00dev, RT3883))
11195		rf = RF3853;
11196	else if (rt2x00_rt(rt2x00dev, RT5350))
11197		rf = RF5350;
11198	else if (rt2x00_rt(rt2x00dev, RT5592))
11199		rf = RF5592;
11200	else
11201		rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
11202
11203	switch (rf) {
11204	case RF2820:
11205	case RF2850:
11206	case RF2720:
11207	case RF2750:
11208	case RF3020:
11209	case RF2020:
11210	case RF3021:
11211	case RF3022:
11212	case RF3052:
11213	case RF3053:
11214	case RF3070:
11215	case RF3290:
11216	case RF3320:
11217	case RF3322:
11218	case RF3853:
11219	case RF5350:
11220	case RF5360:
11221	case RF5362:
11222	case RF5370:
11223	case RF5372:
11224	case RF5390:
11225	case RF5392:
11226	case RF5592:
11227	case RF7620:
11228		break;
11229	default:
11230		rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
11231			   rf);
11232		return -ENODEV;
11233	}
11234
11235	rt2x00_set_rf(rt2x00dev, rf);
11236
11237	/*
11238	 * Identify default antenna configuration.
11239	 */
11240	rt2x00dev->default_ant.tx_chain_num =
11241	    rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
11242	rt2x00dev->default_ant.rx_chain_num =
11243	    rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
11244
11245	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
11246
11247	if (rt2x00_rt(rt2x00dev, RT3070) ||
11248	    rt2x00_rt(rt2x00dev, RT3090) ||
11249	    rt2x00_rt(rt2x00dev, RT3352) ||
11250	    rt2x00_rt(rt2x00dev, RT3390)) {
11251		value = rt2x00_get_field16(eeprom,
11252				EEPROM_NIC_CONF1_ANT_DIVERSITY);
11253		switch (value) {
11254		case 0:
11255		case 1:
11256		case 2:
11257			rt2x00dev->default_ant.tx = ANTENNA_A;
11258			rt2x00dev->default_ant.rx = ANTENNA_A;
11259			break;
11260		case 3:
11261			rt2x00dev->default_ant.tx = ANTENNA_A;
11262			rt2x00dev->default_ant.rx = ANTENNA_B;
11263			break;
11264		}
11265	} else {
11266		rt2x00dev->default_ant.tx = ANTENNA_A;
11267		rt2x00dev->default_ant.rx = ANTENNA_A;
11268	}
11269
11270	/* These chips have hardware RX antenna diversity */
11271	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
11272	    rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
11273		rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
11274		rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
11275	}
11276
11277	/*
11278	 * Determine external LNA informations.
11279	 */
11280	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
11281		__set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
11282	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
11283		__set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
11284
11285	/*
11286	 * Detect if this device has an hardware controlled radio.
11287	 */
11288	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
11289		__set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
11290
11291	/*
11292	 * Detect if this device has Bluetooth co-existence.
11293	 */
11294	if (!rt2x00_rt(rt2x00dev, RT3352) &&
11295	    rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
11296		__set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
11297
11298	/*
11299	 * Read frequency offset and RF programming sequence.
11300	 */
11301	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
11302	rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
11303
11304	/*
11305	 * Store led settings, for correct led behaviour.
11306	 */
11307#ifdef CONFIG_RT2X00_LIB_LEDS
11308	rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
11309	rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
11310	rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
11311
11312	rt2x00dev->led_mcu_reg = eeprom;
11313#endif /* CONFIG_RT2X00_LIB_LEDS */
11314
11315	/*
11316	 * Check if support EIRP tx power limit feature.
11317	 */
11318	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
11319
11320	if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
11321					EIRP_MAX_TX_POWER_LIMIT)
11322		__set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
11323
11324	/*
11325	 * Detect if device uses internal or external PA
11326	 */
11327	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
11328
11329	if (rt2x00_rt(rt2x00dev, RT3352) ||
11330	    rt2x00_rt(rt2x00dev, RT6352)) {
11331		if (rt2x00_get_field16(eeprom,
11332		    EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352))
11333		    __set_bit(CAPABILITY_EXTERNAL_PA_TX0,
11334			      &rt2x00dev->cap_flags);
11335		if (rt2x00_get_field16(eeprom,
11336		    EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352))
11337		    __set_bit(CAPABILITY_EXTERNAL_PA_TX1,
11338			      &rt2x00dev->cap_flags);
11339	}
11340
11341	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF2);
11342
11343	if (rt2x00_rt(rt2x00dev, RT6352) && eeprom != 0 && eeprom != 0xffff) {
11344		if (!rt2x00_get_field16(eeprom,
11345					EEPROM_NIC_CONF2_EXTERNAL_PA)) {
11346			__clear_bit(CAPABILITY_EXTERNAL_PA_TX0,
11347				    &rt2x00dev->cap_flags);
11348			__clear_bit(CAPABILITY_EXTERNAL_PA_TX1,
11349				    &rt2x00dev->cap_flags);
11350		}
11351	}
11352
11353	return 0;
11354}
11355
11356/*
11357 * RF value list for rt28xx
11358 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
11359 */
11360static const struct rf_channel rf_vals[] = {
11361	{ 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
11362	{ 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
11363	{ 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
11364	{ 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
11365	{ 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
11366	{ 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
11367	{ 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
11368	{ 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
11369	{ 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
11370	{ 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
11371	{ 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
11372	{ 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
11373	{ 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
11374	{ 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
11375
11376	/* 802.11 UNI / HyperLan 2 */
11377	{ 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
11378	{ 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
11379	{ 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
11380	{ 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
11381	{ 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
11382	{ 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
11383	{ 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
11384	{ 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
11385	{ 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
11386	{ 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
11387	{ 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
11388	{ 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
11389
11390	/* 802.11 HyperLan 2 */
11391	{ 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
11392	{ 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
11393	{ 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
11394	{ 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
11395	{ 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
11396	{ 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
11397	{ 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
11398	{ 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
11399	{ 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
11400	{ 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
11401	{ 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
11402	{ 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
11403	{ 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
11404	{ 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
11405	{ 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
11406	{ 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
11407
11408	/* 802.11 UNII */
11409	{ 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
11410	{ 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
11411	{ 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
11412	{ 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
11413	{ 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
11414	{ 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
11415	{ 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
11416	{ 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
11417	{ 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
11418	{ 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
11419	{ 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
11420
11421	/* 802.11 Japan */
11422	{ 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
11423	{ 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
11424	{ 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
11425	{ 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
11426	{ 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
11427	{ 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
11428	{ 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
11429};
11430
11431/*
11432 * RF value list for rt3xxx
11433 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
11434 */
11435static const struct rf_channel rf_vals_3x[] = {
11436	{1,  241, 2, 2 },
11437	{2,  241, 2, 7 },
11438	{3,  242, 2, 2 },
11439	{4,  242, 2, 7 },
11440	{5,  243, 2, 2 },
11441	{6,  243, 2, 7 },
11442	{7,  244, 2, 2 },
11443	{8,  244, 2, 7 },
11444	{9,  245, 2, 2 },
11445	{10, 245, 2, 7 },
11446	{11, 246, 2, 2 },
11447	{12, 246, 2, 7 },
11448	{13, 247, 2, 2 },
11449	{14, 248, 2, 4 },
11450
11451	/* 802.11 UNI / HyperLan 2 */
11452	{36, 0x56, 0, 4},
11453	{38, 0x56, 0, 6},
11454	{40, 0x56, 0, 8},
11455	{44, 0x57, 0, 0},
11456	{46, 0x57, 0, 2},
11457	{48, 0x57, 0, 4},
11458	{52, 0x57, 0, 8},
11459	{54, 0x57, 0, 10},
11460	{56, 0x58, 0, 0},
11461	{60, 0x58, 0, 4},
11462	{62, 0x58, 0, 6},
11463	{64, 0x58, 0, 8},
11464
11465	/* 802.11 HyperLan 2 */
11466	{100, 0x5b, 0, 8},
11467	{102, 0x5b, 0, 10},
11468	{104, 0x5c, 0, 0},
11469	{108, 0x5c, 0, 4},
11470	{110, 0x5c, 0, 6},
11471	{112, 0x5c, 0, 8},
11472	{116, 0x5d, 0, 0},
11473	{118, 0x5d, 0, 2},
11474	{120, 0x5d, 0, 4},
11475	{124, 0x5d, 0, 8},
11476	{126, 0x5d, 0, 10},
11477	{128, 0x5e, 0, 0},
11478	{132, 0x5e, 0, 4},
11479	{134, 0x5e, 0, 6},
11480	{136, 0x5e, 0, 8},
11481	{140, 0x5f, 0, 0},
11482
11483	/* 802.11 UNII */
11484	{149, 0x5f, 0, 9},
11485	{151, 0x5f, 0, 11},
11486	{153, 0x60, 0, 1},
11487	{157, 0x60, 0, 5},
11488	{159, 0x60, 0, 7},
11489	{161, 0x60, 0, 9},
11490	{165, 0x61, 0, 1},
11491	{167, 0x61, 0, 3},
11492	{169, 0x61, 0, 5},
11493	{171, 0x61, 0, 7},
11494	{173, 0x61, 0, 9},
11495};
11496
11497/*
11498 * RF value list for rt3xxx with Xtal20MHz
11499 * Supports: 2.4 GHz (all) (RF3322)
11500 */
11501static const struct rf_channel rf_vals_3x_xtal20[] = {
11502	{1,    0xE2,	 2,  0x14},
11503	{2,    0xE3,	 2,  0x14},
11504	{3,    0xE4,	 2,  0x14},
11505	{4,    0xE5,	 2,  0x14},
11506	{5,    0xE6,	 2,  0x14},
11507	{6,    0xE7,	 2,  0x14},
11508	{7,    0xE8,	 2,  0x14},
11509	{8,    0xE9,	 2,  0x14},
11510	{9,    0xEA,	 2,  0x14},
11511	{10,   0xEB,	 2,  0x14},
11512	{11,   0xEC,	 2,  0x14},
11513	{12,   0xED,	 2,  0x14},
11514	{13,   0xEE,	 2,  0x14},
11515	{14,   0xF0,	 2,  0x18},
11516};
11517
11518static const struct rf_channel rf_vals_3853[] = {
11519	{1,  241, 6, 2},
11520	{2,  241, 6, 7},
11521	{3,  242, 6, 2},
11522	{4,  242, 6, 7},
11523	{5,  243, 6, 2},
11524	{6,  243, 6, 7},
11525	{7,  244, 6, 2},
11526	{8,  244, 6, 7},
11527	{9,  245, 6, 2},
11528	{10, 245, 6, 7},
11529	{11, 246, 6, 2},
11530	{12, 246, 6, 7},
11531	{13, 247, 6, 2},
11532	{14, 248, 6, 4},
11533
11534	{36, 0x56, 8, 4},
11535	{38, 0x56, 8, 6},
11536	{40, 0x56, 8, 8},
11537	{44, 0x57, 8, 0},
11538	{46, 0x57, 8, 2},
11539	{48, 0x57, 8, 4},
11540	{52, 0x57, 8, 8},
11541	{54, 0x57, 8, 10},
11542	{56, 0x58, 8, 0},
11543	{60, 0x58, 8, 4},
11544	{62, 0x58, 8, 6},
11545	{64, 0x58, 8, 8},
11546
11547	{100, 0x5b, 8, 8},
11548	{102, 0x5b, 8, 10},
11549	{104, 0x5c, 8, 0},
11550	{108, 0x5c, 8, 4},
11551	{110, 0x5c, 8, 6},
11552	{112, 0x5c, 8, 8},
11553	{114, 0x5c, 8, 10},
11554	{116, 0x5d, 8, 0},
11555	{118, 0x5d, 8, 2},
11556	{120, 0x5d, 8, 4},
11557	{124, 0x5d, 8, 8},
11558	{126, 0x5d, 8, 10},
11559	{128, 0x5e, 8, 0},
11560	{132, 0x5e, 8, 4},
11561	{134, 0x5e, 8, 6},
11562	{136, 0x5e, 8, 8},
11563	{140, 0x5f, 8, 0},
11564
11565	{149, 0x5f, 8, 9},
11566	{151, 0x5f, 8, 11},
11567	{153, 0x60, 8, 1},
11568	{157, 0x60, 8, 5},
11569	{159, 0x60, 8, 7},
11570	{161, 0x60, 8, 9},
11571	{165, 0x61, 8, 1},
11572	{167, 0x61, 8, 3},
11573	{169, 0x61, 8, 5},
11574	{171, 0x61, 8, 7},
11575	{173, 0x61, 8, 9},
11576};
11577
11578static const struct rf_channel rf_vals_5592_xtal20[] = {
11579	/* Channel, N, K, mod, R */
11580	{1, 482, 4, 10, 3},
11581	{2, 483, 4, 10, 3},
11582	{3, 484, 4, 10, 3},
11583	{4, 485, 4, 10, 3},
11584	{5, 486, 4, 10, 3},
11585	{6, 487, 4, 10, 3},
11586	{7, 488, 4, 10, 3},
11587	{8, 489, 4, 10, 3},
11588	{9, 490, 4, 10, 3},
11589	{10, 491, 4, 10, 3},
11590	{11, 492, 4, 10, 3},
11591	{12, 493, 4, 10, 3},
11592	{13, 494, 4, 10, 3},
11593	{14, 496, 8, 10, 3},
11594	{36, 172, 8, 12, 1},
11595	{38, 173, 0, 12, 1},
11596	{40, 173, 4, 12, 1},
11597	{42, 173, 8, 12, 1},
11598	{44, 174, 0, 12, 1},
11599	{46, 174, 4, 12, 1},
11600	{48, 174, 8, 12, 1},
11601	{50, 175, 0, 12, 1},
11602	{52, 175, 4, 12, 1},
11603	{54, 175, 8, 12, 1},
11604	{56, 176, 0, 12, 1},
11605	{58, 176, 4, 12, 1},
11606	{60, 176, 8, 12, 1},
11607	{62, 177, 0, 12, 1},
11608	{64, 177, 4, 12, 1},
11609	{100, 183, 4, 12, 1},
11610	{102, 183, 8, 12, 1},
11611	{104, 184, 0, 12, 1},
11612	{106, 184, 4, 12, 1},
11613	{108, 184, 8, 12, 1},
11614	{110, 185, 0, 12, 1},
11615	{112, 185, 4, 12, 1},
11616	{114, 185, 8, 12, 1},
11617	{116, 186, 0, 12, 1},
11618	{118, 186, 4, 12, 1},
11619	{120, 186, 8, 12, 1},
11620	{122, 187, 0, 12, 1},
11621	{124, 187, 4, 12, 1},
11622	{126, 187, 8, 12, 1},
11623	{128, 188, 0, 12, 1},
11624	{130, 188, 4, 12, 1},
11625	{132, 188, 8, 12, 1},
11626	{134, 189, 0, 12, 1},
11627	{136, 189, 4, 12, 1},
11628	{138, 189, 8, 12, 1},
11629	{140, 190, 0, 12, 1},
11630	{149, 191, 6, 12, 1},
11631	{151, 191, 10, 12, 1},
11632	{153, 192, 2, 12, 1},
11633	{155, 192, 6, 12, 1},
11634	{157, 192, 10, 12, 1},
11635	{159, 193, 2, 12, 1},
11636	{161, 193, 6, 12, 1},
11637	{165, 194, 2, 12, 1},
11638	{184, 164, 0, 12, 1},
11639	{188, 164, 4, 12, 1},
11640	{192, 165, 8, 12, 1},
11641	{196, 166, 0, 12, 1},
11642};
11643
11644static const struct rf_channel rf_vals_5592_xtal40[] = {
11645	/* Channel, N, K, mod, R */
11646	{1, 241, 2, 10, 3},
11647	{2, 241, 7, 10, 3},
11648	{3, 242, 2, 10, 3},
11649	{4, 242, 7, 10, 3},
11650	{5, 243, 2, 10, 3},
11651	{6, 243, 7, 10, 3},
11652	{7, 244, 2, 10, 3},
11653	{8, 244, 7, 10, 3},
11654	{9, 245, 2, 10, 3},
11655	{10, 245, 7, 10, 3},
11656	{11, 246, 2, 10, 3},
11657	{12, 246, 7, 10, 3},
11658	{13, 247, 2, 10, 3},
11659	{14, 248, 4, 10, 3},
11660	{36, 86, 4, 12, 1},
11661	{38, 86, 6, 12, 1},
11662	{40, 86, 8, 12, 1},
11663	{42, 86, 10, 12, 1},
11664	{44, 87, 0, 12, 1},
11665	{46, 87, 2, 12, 1},
11666	{48, 87, 4, 12, 1},
11667	{50, 87, 6, 12, 1},
11668	{52, 87, 8, 12, 1},
11669	{54, 87, 10, 12, 1},
11670	{56, 88, 0, 12, 1},
11671	{58, 88, 2, 12, 1},
11672	{60, 88, 4, 12, 1},
11673	{62, 88, 6, 12, 1},
11674	{64, 88, 8, 12, 1},
11675	{100, 91, 8, 12, 1},
11676	{102, 91, 10, 12, 1},
11677	{104, 92, 0, 12, 1},
11678	{106, 92, 2, 12, 1},
11679	{108, 92, 4, 12, 1},
11680	{110, 92, 6, 12, 1},
11681	{112, 92, 8, 12, 1},
11682	{114, 92, 10, 12, 1},
11683	{116, 93, 0, 12, 1},
11684	{118, 93, 2, 12, 1},
11685	{120, 93, 4, 12, 1},
11686	{122, 93, 6, 12, 1},
11687	{124, 93, 8, 12, 1},
11688	{126, 93, 10, 12, 1},
11689	{128, 94, 0, 12, 1},
11690	{130, 94, 2, 12, 1},
11691	{132, 94, 4, 12, 1},
11692	{134, 94, 6, 12, 1},
11693	{136, 94, 8, 12, 1},
11694	{138, 94, 10, 12, 1},
11695	{140, 95, 0, 12, 1},
11696	{149, 95, 9, 12, 1},
11697	{151, 95, 11, 12, 1},
11698	{153, 96, 1, 12, 1},
11699	{155, 96, 3, 12, 1},
11700	{157, 96, 5, 12, 1},
11701	{159, 96, 7, 12, 1},
11702	{161, 96, 9, 12, 1},
11703	{165, 97, 1, 12, 1},
11704	{184, 82, 0, 12, 1},
11705	{188, 82, 4, 12, 1},
11706	{192, 82, 8, 12, 1},
11707	{196, 83, 0, 12, 1},
11708};
11709
11710static const struct rf_channel rf_vals_7620[] = {
11711	{1, 0x50, 0x99, 0x99, 1},
11712	{2, 0x50, 0x44, 0x44, 2},
11713	{3, 0x50, 0xEE, 0xEE, 2},
11714	{4, 0x50, 0x99, 0x99, 3},
11715	{5, 0x51, 0x44, 0x44, 0},
11716	{6, 0x51, 0xEE, 0xEE, 0},
11717	{7, 0x51, 0x99, 0x99, 1},
11718	{8, 0x51, 0x44, 0x44, 2},
11719	{9, 0x51, 0xEE, 0xEE, 2},
11720	{10, 0x51, 0x99, 0x99, 3},
11721	{11, 0x52, 0x44, 0x44, 0},
11722	{12, 0x52, 0xEE, 0xEE, 0},
11723	{13, 0x52, 0x99, 0x99, 1},
11724	{14, 0x52, 0x33, 0x33, 3},
11725};
11726
11727static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
11728{
11729	struct hw_mode_spec *spec = &rt2x00dev->spec;
11730	struct channel_info *info;
11731	s8 *default_power1;
11732	s8 *default_power2;
11733	s8 *default_power3;
11734	unsigned int i, tx_chains, rx_chains;
11735	u32 reg;
11736
11737	/*
11738	 * Disable powersaving as default.
11739	 */
11740	rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
11741
11742	/*
11743	 * Change default retry settings to values corresponding more closely
11744	 * to rate[0].count setting of minstrel rate control algorithm.
11745	 */
11746	rt2x00dev->hw->wiphy->retry_short = 2;
11747	rt2x00dev->hw->wiphy->retry_long = 2;
11748
11749	/*
11750	 * Initialize all hw fields.
11751	 */
11752	ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
11753	ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
11754	ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
11755	ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
11756	ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
11757
11758	/*
11759	 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
11760	 * unless we are capable of sending the buffered frames out after the
11761	 * DTIM transmission using rt2x00lib_beacondone. This will send out
11762	 * multicast and broadcast traffic immediately instead of buffering it
11763	 * infinitly and thus dropping it after some time.
11764	 */
11765	if (!rt2x00_is_usb(rt2x00dev))
11766		ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
11767
11768	ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE);
11769
11770	SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
11771	SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
11772				rt2800_eeprom_addr(rt2x00dev,
11773						   EEPROM_MAC_ADDR_0));
11774
11775	/*
11776	 * As rt2800 has a global fallback table we cannot specify
11777	 * more then one tx rate per frame but since the hw will
11778	 * try several rates (based on the fallback table) we should
11779	 * initialize max_report_rates to the maximum number of rates
11780	 * we are going to try. Otherwise mac80211 will truncate our
11781	 * reported tx rates and the rc algortihm will end up with
11782	 * incorrect data.
11783	 */
11784	rt2x00dev->hw->max_rates = 1;
11785	rt2x00dev->hw->max_report_rates = 7;
11786	rt2x00dev->hw->max_rate_tries = 1;
11787
11788	/*
11789	 * Initialize hw_mode information.
11790	 */
11791	spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
11792
11793	switch (rt2x00dev->chip.rf) {
11794	case RF2720:
11795	case RF2820:
11796		spec->num_channels = 14;
11797		spec->channels = rf_vals;
11798		break;
11799
11800	case RF2750:
11801	case RF2850:
11802		spec->num_channels = ARRAY_SIZE(rf_vals);
11803		spec->channels = rf_vals;
11804		break;
11805
11806	case RF2020:
11807	case RF3020:
11808	case RF3021:
11809	case RF3022:
11810	case RF3070:
11811	case RF3290:
11812	case RF3320:
11813	case RF3322:
11814	case RF5350:
11815	case RF5360:
11816	case RF5362:
11817	case RF5370:
11818	case RF5372:
11819	case RF5390:
11820	case RF5392:
11821		spec->num_channels = 14;
11822		if (rt2800_clk_is_20mhz(rt2x00dev))
11823			spec->channels = rf_vals_3x_xtal20;
11824		else
11825			spec->channels = rf_vals_3x;
11826		break;
11827
11828	case RF7620:
11829		spec->num_channels = ARRAY_SIZE(rf_vals_7620);
11830		spec->channels = rf_vals_7620;
11831		break;
11832
11833	case RF3052:
11834	case RF3053:
11835		spec->num_channels = ARRAY_SIZE(rf_vals_3x);
11836		spec->channels = rf_vals_3x;
11837		break;
11838
11839	case RF3853:
11840		spec->num_channels = ARRAY_SIZE(rf_vals_3853);
11841		spec->channels = rf_vals_3853;
11842		break;
11843
11844	case RF5592:
11845		reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX);
11846		if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
11847			spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
11848			spec->channels = rf_vals_5592_xtal40;
11849		} else {
11850			spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
11851			spec->channels = rf_vals_5592_xtal20;
11852		}
11853		break;
11854	}
11855
11856	if (WARN_ON_ONCE(!spec->channels))
11857		return -ENODEV;
11858
11859	spec->supported_bands = SUPPORT_BAND_2GHZ;
11860	if (spec->num_channels > 14)
11861		spec->supported_bands |= SUPPORT_BAND_5GHZ;
11862
11863	/*
11864	 * Initialize HT information.
11865	 */
11866	if (!rt2x00_rf(rt2x00dev, RF2020))
11867		spec->ht.ht_supported = true;
11868	else
11869		spec->ht.ht_supported = false;
11870
11871	spec->ht.cap =
11872	    IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
11873	    IEEE80211_HT_CAP_GRN_FLD |
11874	    IEEE80211_HT_CAP_SGI_20 |
11875	    IEEE80211_HT_CAP_SGI_40;
11876
11877	tx_chains = rt2x00dev->default_ant.tx_chain_num;
11878	rx_chains = rt2x00dev->default_ant.rx_chain_num;
11879
11880	if (tx_chains >= 2)
11881		spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
11882
11883	spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT;
11884
11885	spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2;
11886	spec->ht.ampdu_density = 4;
11887	spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
11888	if (tx_chains != rx_chains) {
11889		spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
11890		spec->ht.mcs.tx_params |=
11891		    (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
11892	}
11893
11894	switch (rx_chains) {
11895	case 3:
11896		spec->ht.mcs.rx_mask[2] = 0xff;
11897		fallthrough;
11898	case 2:
11899		spec->ht.mcs.rx_mask[1] = 0xff;
11900		fallthrough;
11901	case 1:
11902		spec->ht.mcs.rx_mask[0] = 0xff;
11903		spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
11904		break;
11905	}
11906
11907	/*
11908	 * Create channel information and survey arrays
11909	 */
11910	info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
11911	if (!info)
11912		return -ENOMEM;
11913
11914	rt2x00dev->chan_survey =
11915		kcalloc(spec->num_channels, sizeof(struct rt2x00_chan_survey),
11916			GFP_KERNEL);
11917	if (!rt2x00dev->chan_survey) {
11918		kfree(info);
11919		return -ENOMEM;
11920	}
11921
11922	spec->channels_info = info;
11923
11924	default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
11925	default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
11926
11927	if (rt2x00dev->default_ant.tx_chain_num > 2)
11928		default_power3 = rt2800_eeprom_addr(rt2x00dev,
11929						    EEPROM_EXT_TXPOWER_BG3);
11930	else
11931		default_power3 = NULL;
11932
11933	for (i = 0; i < 14; i++) {
11934		info[i].default_power1 = default_power1[i];
11935		info[i].default_power2 = default_power2[i];
11936		if (default_power3)
11937			info[i].default_power3 = default_power3[i];
11938	}
11939
11940	if (spec->num_channels > 14) {
11941		default_power1 = rt2800_eeprom_addr(rt2x00dev,
11942						    EEPROM_TXPOWER_A1);
11943		default_power2 = rt2800_eeprom_addr(rt2x00dev,
11944						    EEPROM_TXPOWER_A2);
11945
11946		if (rt2x00dev->default_ant.tx_chain_num > 2)
11947			default_power3 =
11948				rt2800_eeprom_addr(rt2x00dev,
11949						   EEPROM_EXT_TXPOWER_A3);
11950		else
11951			default_power3 = NULL;
11952
11953		for (i = 14; i < spec->num_channels; i++) {
11954			info[i].default_power1 = default_power1[i - 14];
11955			info[i].default_power2 = default_power2[i - 14];
11956			if (default_power3)
11957				info[i].default_power3 = default_power3[i - 14];
11958		}
11959	}
11960
11961	switch (rt2x00dev->chip.rf) {
11962	case RF2020:
11963	case RF3020:
11964	case RF3021:
11965	case RF3022:
11966	case RF3320:
11967	case RF3052:
11968	case RF3053:
11969	case RF3070:
11970	case RF3290:
11971	case RF3853:
11972	case RF5350:
11973	case RF5360:
11974	case RF5362:
11975	case RF5370:
11976	case RF5372:
11977	case RF5390:
11978	case RF5392:
11979	case RF5592:
11980	case RF7620:
11981		__set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
11982		break;
11983	}
11984
11985	return 0;
11986}
11987
11988static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
11989{
11990	u32 reg;
11991	u32 rt;
11992	u32 rev;
11993
11994	if (rt2x00_rt(rt2x00dev, RT3290))
11995		reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290);
11996	else
11997		reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
11998
11999	rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
12000	rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
12001
12002	switch (rt) {
12003	case RT2860:
12004	case RT2872:
12005	case RT2883:
12006	case RT3070:
12007	case RT3071:
12008	case RT3090:
12009	case RT3290:
12010	case RT3352:
12011	case RT3390:
12012	case RT3572:
12013	case RT3593:
12014	case RT3883:
12015	case RT5350:
12016	case RT5390:
12017	case RT5392:
12018	case RT5592:
12019		break;
12020	default:
12021		rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
12022			   rt, rev);
12023		return -ENODEV;
12024	}
12025
12026	if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))
12027		rt = RT6352;
12028
12029	rt2x00_set_rt(rt2x00dev, rt, rev);
12030
12031	return 0;
12032}
12033
12034int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
12035{
12036	int retval;
12037	u32 reg;
12038
12039	retval = rt2800_probe_rt(rt2x00dev);
12040	if (retval)
12041		return retval;
12042
12043	/*
12044	 * Allocate eeprom data.
12045	 */
12046	retval = rt2800_validate_eeprom(rt2x00dev);
12047	if (retval)
12048		return retval;
12049
12050	retval = rt2800_init_eeprom(rt2x00dev);
12051	if (retval)
12052		return retval;
12053
12054	/*
12055	 * Enable rfkill polling by setting GPIO direction of the
12056	 * rfkill switch GPIO pin correctly.
12057	 */
12058	reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
12059	rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
12060	rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
12061
12062	/*
12063	 * Initialize hw specifications.
12064	 */
12065	retval = rt2800_probe_hw_mode(rt2x00dev);
12066	if (retval)
12067		return retval;
12068
12069	/*
12070	 * Set device capabilities.
12071	 */
12072	__set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
12073	__set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
12074	if (!rt2x00_is_usb(rt2x00dev))
12075		__set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
12076
12077	/*
12078	 * Set device requirements.
12079	 */
12080	if (!rt2x00_is_soc(rt2x00dev))
12081		__set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
12082	__set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
12083	__set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
12084	if (!rt2800_hwcrypt_disabled(rt2x00dev))
12085		__set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
12086	__set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
12087	__set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
12088	if (rt2x00_is_usb(rt2x00dev))
12089		__set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
12090	else {
12091		__set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
12092		__set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
12093	}
12094
12095	rt2x00dev->link.watchdog = modparam_watchdog;
12096	/* USB NICs don't support DMA watchdog as INT_SOURCE_CSR is invalid */
12097	if (rt2x00_is_usb(rt2x00dev))
12098		rt2x00dev->link.watchdog &= ~RT2800_WATCHDOG_DMA_BUSY;
12099	if (rt2x00dev->link.watchdog) {
12100		__set_bit(CAPABILITY_RESTART_HW, &rt2x00dev->cap_flags);
12101		rt2x00dev->link.watchdog_interval = msecs_to_jiffies(100);
12102	}
12103
12104	/*
12105	 * Set the rssi offset.
12106	 */
12107	rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
12108
12109	return 0;
12110}
12111EXPORT_SYMBOL_GPL(rt2800_probe_hw);
12112
12113/*
12114 * IEEE80211 stack callback functions.
12115 */
12116void rt2800_get_key_seq(struct ieee80211_hw *hw,
12117			struct ieee80211_key_conf *key,
12118			struct ieee80211_key_seq *seq)
12119{
12120	struct rt2x00_dev *rt2x00dev = hw->priv;
12121	struct mac_iveiv_entry iveiv_entry;
12122	u32 offset;
12123
12124	if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
12125		return;
12126
12127	offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
12128	rt2800_register_multiread(rt2x00dev, offset,
12129				      &iveiv_entry, sizeof(iveiv_entry));
12130
12131	memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2);
12132	memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4);
12133}
12134EXPORT_SYMBOL_GPL(rt2800_get_key_seq);
12135
12136int rt2800_set_rts_threshold(struct ieee80211_hw *hw, int radio_idx, u32 value)
12137{
12138	struct rt2x00_dev *rt2x00dev = hw->priv;
12139	u32 reg;
12140	bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
12141
12142	reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
12143	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
12144	rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
12145
12146	reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
12147	rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
12148	rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
12149
12150	reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
12151	rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
12152	rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
12153
12154	reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
12155	rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
12156	rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
12157
12158	reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
12159	rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
12160	rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
12161
12162	reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
12163	rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
12164	rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
12165
12166	reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
12167	rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
12168	rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
12169
12170	return 0;
12171}
12172EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
12173
12174int rt2800_conf_tx(struct ieee80211_hw *hw,
12175		   struct ieee80211_vif *vif,
12176		   unsigned int link_id, u16 queue_idx,
12177		   const struct ieee80211_tx_queue_params *params)
12178{
12179	struct rt2x00_dev *rt2x00dev = hw->priv;
12180	struct data_queue *queue;
12181	struct rt2x00_field32 field;
12182	int retval;
12183	u32 reg;
12184	u32 offset;
12185
12186	/*
12187	 * First pass the configuration through rt2x00lib, that will
12188	 * update the queue settings and validate the input. After that
12189	 * we are free to update the registers based on the value
12190	 * in the queue parameter.
12191	 */
12192	retval = rt2x00mac_conf_tx(hw, vif, link_id, queue_idx, params);
12193	if (retval)
12194		return retval;
12195
12196	/*
12197	 * We only need to perform additional register initialization
12198	 * for WMM queues/
12199	 */
12200	if (queue_idx >= 4)
12201		return 0;
12202
12203	queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
12204
12205	/* Update WMM TXOP register */
12206	offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
12207	field.bit_offset = (queue_idx & 1) * 16;
12208	field.bit_mask = 0xffff << field.bit_offset;
12209
12210	reg = rt2800_register_read(rt2x00dev, offset);
12211	rt2x00_set_field32(&reg, field, queue->txop);
12212	rt2800_register_write(rt2x00dev, offset, reg);
12213
12214	/* Update WMM registers */
12215	field.bit_offset = queue_idx * 4;
12216	field.bit_mask = 0xf << field.bit_offset;
12217
12218	reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG);
12219	rt2x00_set_field32(&reg, field, queue->aifs);
12220	rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
12221
12222	reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG);
12223	rt2x00_set_field32(&reg, field, queue->cw_min);
12224	rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
12225
12226	reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG);
12227	rt2x00_set_field32(&reg, field, queue->cw_max);
12228	rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
12229
12230	/* Update EDCA registers */
12231	offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
12232
12233	reg = rt2800_register_read(rt2x00dev, offset);
12234	rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
12235	rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
12236	rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
12237	rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
12238	rt2800_register_write(rt2x00dev, offset, reg);
12239
12240	return 0;
12241}
12242EXPORT_SYMBOL_GPL(rt2800_conf_tx);
12243
12244u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
12245{
12246	struct rt2x00_dev *rt2x00dev = hw->priv;
12247	u64 tsf;
12248	u32 reg;
12249
12250	reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1);
12251	tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
12252	reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0);
12253	tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
12254
12255	return tsf;
12256}
12257EXPORT_SYMBOL_GPL(rt2800_get_tsf);
12258
12259int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
12260			struct ieee80211_ampdu_params *params)
12261{
12262	struct ieee80211_sta *sta = params->sta;
12263	enum ieee80211_ampdu_mlme_action action = params->action;
12264	u16 tid = params->tid;
12265	struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
12266	int ret = 0;
12267
12268	/*
12269	 * Don't allow aggregation for stations the hardware isn't aware
12270	 * of because tx status reports for frames to an unknown station
12271	 * always contain wcid=WCID_END+1 and thus we can't distinguish
12272	 * between multiple stations which leads to unwanted situations
12273	 * when the hw reorders frames due to aggregation.
12274	 */
12275	if (sta_priv->wcid > WCID_END)
12276		return -ENOSPC;
12277
12278	switch (action) {
12279	case IEEE80211_AMPDU_RX_START:
12280	case IEEE80211_AMPDU_RX_STOP:
12281		/*
12282		 * The hw itself takes care of setting up BlockAck mechanisms.
12283		 * So, we only have to allow mac80211 to nagotiate a BlockAck
12284		 * agreement. Once that is done, the hw will BlockAck incoming
12285		 * AMPDUs without further setup.
12286		 */
12287		break;
12288	case IEEE80211_AMPDU_TX_START:
12289		ret = IEEE80211_AMPDU_TX_START_IMMEDIATE;
12290		break;
12291	case IEEE80211_AMPDU_TX_STOP_CONT:
12292	case IEEE80211_AMPDU_TX_STOP_FLUSH:
12293	case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
12294		ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
12295		break;
12296	case IEEE80211_AMPDU_TX_OPERATIONAL:
12297		break;
12298	default:
12299		rt2x00_warn((struct rt2x00_dev *)hw->priv,
12300			    "Unknown AMPDU action\n");
12301	}
12302
12303	return ret;
12304}
12305EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
12306
12307int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
12308		      struct survey_info *survey)
12309{
12310	struct rt2x00_dev *rt2x00dev = hw->priv;
12311	struct rt2x00_chan_survey *chan_survey =
12312		   &rt2x00dev->chan_survey[idx];
12313	enum nl80211_band band = NL80211_BAND_2GHZ;
12314
12315	if (idx >= rt2x00dev->bands[band].n_channels) {
12316		idx -= rt2x00dev->bands[band].n_channels;
12317		band = NL80211_BAND_5GHZ;
12318	}
12319
12320	if (idx >= rt2x00dev->bands[band].n_channels)
12321		return -ENOENT;
12322
12323	if (idx == 0)
12324		rt2800_update_survey(rt2x00dev);
12325
12326	survey->channel = &rt2x00dev->bands[band].channels[idx];
12327
12328	survey->filled = SURVEY_INFO_TIME |
12329			 SURVEY_INFO_TIME_BUSY |
12330			 SURVEY_INFO_TIME_EXT_BUSY;
12331
12332	survey->time = div_u64(chan_survey->time_idle + chan_survey->time_busy, 1000);
12333	survey->time_busy = div_u64(chan_survey->time_busy, 1000);
12334	survey->time_ext_busy = div_u64(chan_survey->time_ext_busy, 1000);
12335
12336	if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
12337		survey->filled |= SURVEY_INFO_IN_USE;
12338
12339	return 0;
12340
12341}
12342EXPORT_SYMBOL_GPL(rt2800_get_survey);
12343
12344MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
12345MODULE_VERSION(DRV_VERSION);
12346MODULE_DESCRIPTION("Ralink RT2800 library");
12347MODULE_LICENSE("GPL");