rt2400pci.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3	Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   4	<http://rt2x00.serialmonkey.com>
   5
   6 */
   7
   8/*
   9	Module: rt2400pci
  10	Abstract: rt2400pci device specific routines.
  11	Supported chipsets: RT2460.
  12 */
  13
  14#include <linux/delay.h>
  15#include <linux/etherdevice.h>
  16#include <linux/kernel.h>
  17#include <linux/module.h>
  18#include <linux/pci.h>
  19#include <linux/eeprom_93cx6.h>
  20#include <linux/slab.h>
  21
  22#include "rt2x00.h"
  23#include "rt2x00mmio.h"
  24#include "rt2x00pci.h"
  25#include "rt2400pci.h"
  26
  27/*
  28 * Register access.
  29 * All access to the CSR registers will go through the methods
  30 * rt2x00mmio_register_read and rt2x00mmio_register_write.
  31 * BBP and RF register require indirect register access,
  32 * and use the CSR registers BBPCSR and RFCSR to achieve this.
  33 * These indirect registers work with busy bits,
  34 * and we will try maximal REGISTER_BUSY_COUNT times to access
  35 * the register while taking a REGISTER_BUSY_DELAY us delay
  36 * between each attempt. When the busy bit is still set at that time,
  37 * the access attempt is considered to have failed,
  38 * and we will print an error.
  39 */
  40#define WAIT_FOR_BBP(__dev, __reg) \
  41	rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
  42#define WAIT_FOR_RF(__dev, __reg) \
  43	rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
  44
  45static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  46				const unsigned int word, const u8 value)
  47{
  48	u32 reg;
  49
  50	mutex_lock(&rt2x00dev->csr_mutex);
  51
  52	/*
  53	 * Wait until the BBP becomes available, afterwards we
  54	 * can safely write the new data into the register.
  55	 */
  56	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  57		reg = 0;
  58		rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  59		rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  60		rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  61		rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  62
  63		rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
  64	}
  65
  66	mutex_unlock(&rt2x00dev->csr_mutex);
  67}
  68
  69static u8 rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  70			     const unsigned int word)
  71{
  72	u32 reg;
  73	u8 value;
  74
  75	mutex_lock(&rt2x00dev->csr_mutex);
  76
  77	/*
  78	 * Wait until the BBP becomes available, afterwards we
  79	 * can safely write the read request into the register.
  80	 * After the data has been written, we wait until hardware
  81	 * returns the correct value, if at any time the register
  82	 * doesn't become available in time, reg will be 0xffffffff
  83	 * which means we return 0xff to the caller.
  84	 */
  85	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  86		reg = 0;
  87		rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  88		rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  89		rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
  90
  91		rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
  92
  93		WAIT_FOR_BBP(rt2x00dev, &reg);
  94	}
  95
  96	value = rt2x00_get_field32(reg, BBPCSR_VALUE);
  97
  98	mutex_unlock(&rt2x00dev->csr_mutex);
  99
 100	return value;
 101}
 102
 103static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
 104			       const unsigned int word, const u32 value)
 105{
 106	u32 reg;
 107
 108	mutex_lock(&rt2x00dev->csr_mutex);
 109
 110	/*
 111	 * Wait until the RF becomes available, afterwards we
 112	 * can safely write the new data into the register.
 113	 */
 114	if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 115		reg = 0;
 116		rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 117		rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 118		rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 119		rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 120
 121		rt2x00mmio_register_write(rt2x00dev, RFCSR, reg);
 122		rt2x00_rf_write(rt2x00dev, word, value);
 123	}
 124
 125	mutex_unlock(&rt2x00dev->csr_mutex);
 126}
 127
 128static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 129{
 130	struct rt2x00_dev *rt2x00dev = eeprom->data;
 131	u32 reg;
 132
 133	reg = rt2x00mmio_register_read(rt2x00dev, CSR21);
 134
 135	eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 136	eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 137	eeprom->reg_data_clock =
 138	    !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 139	eeprom->reg_chip_select =
 140	    !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 141}
 142
 143static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 144{
 145	struct rt2x00_dev *rt2x00dev = eeprom->data;
 146	u32 reg = 0;
 147
 148	rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 149	rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 150	rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 151			   !!eeprom->reg_data_clock);
 152	rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 153			   !!eeprom->reg_chip_select);
 154
 155	rt2x00mmio_register_write(rt2x00dev, CSR21, reg);
 156}
 157
 158#ifdef CONFIG_RT2X00_LIB_DEBUGFS
 159static const struct rt2x00debug rt2400pci_rt2x00debug = {
 160	.owner	= THIS_MODULE,
 161	.csr	= {
 162		.read		= rt2x00mmio_register_read,
 163		.write		= rt2x00mmio_register_write,
 164		.flags		= RT2X00DEBUGFS_OFFSET,
 165		.word_base	= CSR_REG_BASE,
 166		.word_size	= sizeof(u32),
 167		.word_count	= CSR_REG_SIZE / sizeof(u32),
 168	},
 169	.eeprom	= {
 170		.read		= rt2x00_eeprom_read,
 171		.write		= rt2x00_eeprom_write,
 172		.word_base	= EEPROM_BASE,
 173		.word_size	= sizeof(u16),
 174		.word_count	= EEPROM_SIZE / sizeof(u16),
 175	},
 176	.bbp	= {
 177		.read		= rt2400pci_bbp_read,
 178		.write		= rt2400pci_bbp_write,
 179		.word_base	= BBP_BASE,
 180		.word_size	= sizeof(u8),
 181		.word_count	= BBP_SIZE / sizeof(u8),
 182	},
 183	.rf	= {
 184		.read		= rt2x00_rf_read,
 185		.write		= rt2400pci_rf_write,
 186		.word_base	= RF_BASE,
 187		.word_size	= sizeof(u32),
 188		.word_count	= RF_SIZE / sizeof(u32),
 189	},
 190};
 191#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 192
 193static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 194{
 195	u32 reg;
 196
 197	reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);
 198	return rt2x00_get_field32(reg, GPIOCSR_VAL0);
 199}
 200
 201#ifdef CONFIG_RT2X00_LIB_LEDS
 202static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
 203				     enum led_brightness brightness)
 204{
 205	struct rt2x00_led *led =
 206	    container_of(led_cdev, struct rt2x00_led, led_dev);
 207	unsigned int enabled = brightness != LED_OFF;
 208	u32 reg;
 209
 210	reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);
 211
 212	if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 213		rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 214	else if (led->type == LED_TYPE_ACTIVITY)
 215		rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 216
 217	rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
 218}
 219
 220static int rt2400pci_blink_set(struct led_classdev *led_cdev,
 221			       unsigned long *delay_on,
 222			       unsigned long *delay_off)
 223{
 224	struct rt2x00_led *led =
 225	    container_of(led_cdev, struct rt2x00_led, led_dev);
 226	u32 reg;
 227
 228	reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);
 229	rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 230	rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 231	rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
 232
 233	return 0;
 234}
 235
 236static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
 237			       struct rt2x00_led *led,
 238			       enum led_type type)
 239{
 240	led->rt2x00dev = rt2x00dev;
 241	led->type = type;
 242	led->led_dev.brightness_set = rt2400pci_brightness_set;
 243	led->led_dev.blink_set = rt2400pci_blink_set;
 244	led->flags = LED_INITIALIZED;
 245}
 246#endif /* CONFIG_RT2X00_LIB_LEDS */
 247
 248/*
 249 * Configuration handlers.
 250 */
 251static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
 252				    const unsigned int filter_flags)
 253{
 254	u32 reg;
 255
 256	/*
 257	 * Start configuration steps.
 258	 * Note that the version error will always be dropped
 259	 * since there is no filter for it at this time.
 260	 */
 261	reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
 262	rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 263			   !(filter_flags & FIF_FCSFAIL));
 264	rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 265			   !(filter_flags & FIF_PLCPFAIL));
 266	rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 267			   !(filter_flags & FIF_CONTROL));
 268	rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 269			   !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
 270	rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 271			   !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) &&
 272			   !rt2x00dev->intf_ap_count);
 273	rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 274	rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
 275}
 276
 277static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
 278				  struct rt2x00_intf *intf,
 279				  struct rt2x00intf_conf *conf,
 280				  const unsigned int flags)
 281{
 282	unsigned int bcn_preload;
 283	u32 reg;
 284
 285	if (flags & CONFIG_UPDATE_TYPE) {
 286		/*
 287		 * Enable beacon config
 288		 */
 289		bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
 290		reg = rt2x00mmio_register_read(rt2x00dev, BCNCSR1);
 291		rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 292		rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);
 293
 294		/*
 295		 * Enable synchronisation.
 296		 */
 297		reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
 298		rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 299		rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
 300	}
 301
 302	if (flags & CONFIG_UPDATE_MAC)
 303		rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
 304					       conf->mac, sizeof(conf->mac));
 305
 306	if (flags & CONFIG_UPDATE_BSSID)
 307		rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
 308					       conf->bssid,
 309					       sizeof(conf->bssid));
 310}
 311
 312static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
 313				 struct rt2x00lib_erp *erp,
 314				 u32 changed)
 315{
 316	int preamble_mask;
 317	u32 reg;
 318
 319	/*
 320	 * When short preamble is enabled, we should set bit 0x08
 321	 */
 322	if (changed & BSS_CHANGED_ERP_PREAMBLE) {
 323		preamble_mask = erp->short_preamble << 3;
 324
 325		reg = rt2x00mmio_register_read(rt2x00dev, TXCSR1);
 326		rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
 327		rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
 328		rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 329		rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 330		rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);
 331
 332		reg = rt2x00mmio_register_read(rt2x00dev, ARCSR2);
 333		rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 334		rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 335		rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 336				   GET_DURATION(ACK_SIZE, 10));
 337		rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);
 338
 339		reg = rt2x00mmio_register_read(rt2x00dev, ARCSR3);
 340		rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 341		rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 342		rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 343				   GET_DURATION(ACK_SIZE, 20));
 344		rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);
 345
 346		reg = rt2x00mmio_register_read(rt2x00dev, ARCSR4);
 347		rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 348		rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 349		rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 350				   GET_DURATION(ACK_SIZE, 55));
 351		rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);
 352
 353		reg = rt2x00mmio_register_read(rt2x00dev, ARCSR5);
 354		rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 355		rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 356		rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 357				   GET_DURATION(ACK_SIZE, 110));
 358		rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg);
 359	}
 360
 361	if (changed & BSS_CHANGED_BASIC_RATES)
 362		rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
 363
 364	if (changed & BSS_CHANGED_ERP_SLOT) {
 365		reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
 366		rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
 367		rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
 368
 369		reg = rt2x00mmio_register_read(rt2x00dev, CSR18);
 370		rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
 371		rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
 372		rt2x00mmio_register_write(rt2x00dev, CSR18, reg);
 373
 374		reg = rt2x00mmio_register_read(rt2x00dev, CSR19);
 375		rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
 376		rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
 377		rt2x00mmio_register_write(rt2x00dev, CSR19, reg);
 378	}
 379
 380	if (changed & BSS_CHANGED_BEACON_INT) {
 381		reg = rt2x00mmio_register_read(rt2x00dev, CSR12);
 382		rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 383				   erp->beacon_int * 16);
 384		rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 385				   erp->beacon_int * 16);
 386		rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
 387	}
 388}
 389
 390static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
 391				 struct antenna_setup *ant)
 392{
 393	u8 r1;
 394	u8 r4;
 395
 396	/*
 397	 * We should never come here because rt2x00lib is supposed
 398	 * to catch this and send us the correct antenna explicitely.
 399	 */
 400	BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 401	       ant->tx == ANTENNA_SW_DIVERSITY);
 402
 403	r4 = rt2400pci_bbp_read(rt2x00dev, 4);
 404	r1 = rt2400pci_bbp_read(rt2x00dev, 1);
 405
 406	/*
 407	 * Configure the TX antenna.
 408	 */
 409	switch (ant->tx) {
 410	case ANTENNA_HW_DIVERSITY:
 411		rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
 412		break;
 413	case ANTENNA_A:
 414		rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
 415		break;
 416	case ANTENNA_B:
 417	default:
 418		rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
 419		break;
 420	}
 421
 422	/*
 423	 * Configure the RX antenna.
 424	 */
 425	switch (ant->rx) {
 426	case ANTENNA_HW_DIVERSITY:
 427		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 428		break;
 429	case ANTENNA_A:
 430		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
 431		break;
 432	case ANTENNA_B:
 433	default:
 434		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 435		break;
 436	}
 437
 438	rt2400pci_bbp_write(rt2x00dev, 4, r4);
 439	rt2400pci_bbp_write(rt2x00dev, 1, r1);
 440}
 441
 442static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 443				     struct rf_channel *rf)
 444{
 445	/*
 446	 * Switch on tuning bits.
 447	 */
 448	rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 449	rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 450
 451	rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 452	rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 453	rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 454
 455	/*
 456	 * RF2420 chipset don't need any additional actions.
 457	 */
 458	if (rt2x00_rf(rt2x00dev, RF2420))
 459		return;
 460
 461	/*
 462	 * For the RT2421 chipsets we need to write an invalid
 463	 * reference clock rate to activate auto_tune.
 464	 * After that we set the value back to the correct channel.
 465	 */
 466	rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 467	rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
 468	rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 469
 470	msleep(1);
 471
 472	rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 473	rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 474	rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 475
 476	msleep(1);
 477
 478	/*
 479	 * Switch off tuning bits.
 480	 */
 481	rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 482	rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 483
 484	rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 485	rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 486
 487	/*
 488	 * Clear false CRC during channel switch.
 489	 */
 490	rf->rf1 = rt2x00mmio_register_read(rt2x00dev, CNT0);
 491}
 492
 493static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
 494{
 495	rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
 496}
 497
 498static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 499					 struct rt2x00lib_conf *libconf)
 500{
 501	u32 reg;
 502
 503	reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
 504	rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
 505			   libconf->conf->long_frame_max_tx_count);
 506	rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
 507			   libconf->conf->short_frame_max_tx_count);
 508	rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
 509}
 510
 511static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
 512				struct rt2x00lib_conf *libconf)
 513{
 514	enum dev_state state =
 515	    (libconf->conf->flags & IEEE80211_CONF_PS) ?
 516		STATE_SLEEP : STATE_AWAKE;
 517	u32 reg;
 518
 519	if (state == STATE_SLEEP) {
 520		reg = rt2x00mmio_register_read(rt2x00dev, CSR20);
 521		rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
 522				   (rt2x00dev->beacon_int - 20) * 16);
 523		rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
 524				   libconf->conf->listen_interval - 1);
 525
 526		/* We must first disable autowake before it can be enabled */
 527		rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 528		rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
 529
 530		rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
 531		rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
 532	} else {
 533		reg = rt2x00mmio_register_read(rt2x00dev, CSR20);
 534		rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 535		rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
 536	}
 537
 538	rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 539}
 540
 541static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
 542			     struct rt2x00lib_conf *libconf,
 543			     const unsigned int flags)
 544{
 545	if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 546		rt2400pci_config_channel(rt2x00dev, &libconf->rf);
 547	if (flags & IEEE80211_CONF_CHANGE_POWER)
 548		rt2400pci_config_txpower(rt2x00dev,
 549					 libconf->conf->power_level);
 550	if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 551		rt2400pci_config_retry_limit(rt2x00dev, libconf);
 552	if (flags & IEEE80211_CONF_CHANGE_PS)
 553		rt2400pci_config_ps(rt2x00dev, libconf);
 554}
 555
 556static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
 557				const int cw_min, const int cw_max)
 558{
 559	u32 reg;
 560
 561	reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
 562	rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
 563	rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
 564	rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
 565}
 566
 567/*
 568 * Link tuning
 569 */
 570static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
 571				 struct link_qual *qual)
 572{
 573	u32 reg;
 574	u8 bbp;
 575
 576	/*
 577	 * Update FCS error count from register.
 578	 */
 579	reg = rt2x00mmio_register_read(rt2x00dev, CNT0);
 580	qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 581
 582	/*
 583	 * Update False CCA count from register.
 584	 */
 585	bbp = rt2400pci_bbp_read(rt2x00dev, 39);
 586	qual->false_cca = bbp;
 587}
 588
 589static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
 590				     struct link_qual *qual, u8 vgc_level)
 591{
 592	if (qual->vgc_level_reg != vgc_level) {
 593		rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
 594		qual->vgc_level = vgc_level;
 595		qual->vgc_level_reg = vgc_level;
 596	}
 597}
 598
 599static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
 600				  struct link_qual *qual)
 601{
 602	rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
 603}
 604
 605static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
 606				 struct link_qual *qual, const u32 count)
 607{
 608	/*
 609	 * The link tuner should not run longer then 60 seconds,
 610	 * and should run once every 2 seconds.
 611	 */
 612	if (count > 60 || !(count & 1))
 613		return;
 614
 615	/*
 616	 * Base r13 link tuning on the false cca count.
 617	 */
 618	if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
 619		rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
 620	else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
 621		rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
 622}
 623
 624/*
 625 * Queue handlers.
 626 */
 627static void rt2400pci_start_queue(struct data_queue *queue)
 628{
 629	struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 630	u32 reg;
 631
 632	switch (queue->qid) {
 633	case QID_RX:
 634		reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
 635		rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
 636		rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
 637		break;
 638	case QID_BEACON:
 639		reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
 640		rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 641		rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 642		rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
 643		rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
 644		break;
 645	default:
 646		break;
 647	}
 648}
 649
 650static void rt2400pci_kick_queue(struct data_queue *queue)
 651{
 652	struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 653	u32 reg;
 654
 655	switch (queue->qid) {
 656	case QID_AC_VO:
 657		reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
 658		rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
 659		rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
 660		break;
 661	case QID_AC_VI:
 662		reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
 663		rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
 664		rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
 665		break;
 666	case QID_ATIM:
 667		reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
 668		rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
 669		rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
 670		break;
 671	default:
 672		break;
 673	}
 674}
 675
 676static void rt2400pci_stop_queue(struct data_queue *queue)
 677{
 678	struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 679	u32 reg;
 680
 681	switch (queue->qid) {
 682	case QID_AC_VO:
 683	case QID_AC_VI:
 684	case QID_ATIM:
 685		reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
 686		rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 687		rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
 688		break;
 689	case QID_RX:
 690		reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
 691		rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
 692		rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
 693		break;
 694	case QID_BEACON:
 695		reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
 696		rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 697		rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 698		rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 699		rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
 700
 701		/*
 702		 * Wait for possibly running tbtt tasklets.
 703		 */
 704		tasklet_kill(&rt2x00dev->tbtt_tasklet);
 705		break;
 706	default:
 707		break;
 708	}
 709}
 710
 711/*
 712 * Initialization functions.
 713 */
 714static bool rt2400pci_get_entry_state(struct queue_entry *entry)
 715{
 716	struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
 717	u32 word;
 718
 719	if (entry->queue->qid == QID_RX) {
 720		word = rt2x00_desc_read(entry_priv->desc, 0);
 721
 722		return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
 723	} else {
 724		word = rt2x00_desc_read(entry_priv->desc, 0);
 725
 726		return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
 727		        rt2x00_get_field32(word, TXD_W0_VALID));
 728	}
 729}
 730
 731static void rt2400pci_clear_entry(struct queue_entry *entry)
 732{
 733	struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
 734	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 735	u32 word;
 736
 737	if (entry->queue->qid == QID_RX) {
 738		word = rt2x00_desc_read(entry_priv->desc, 2);
 739		rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
 740		rt2x00_desc_write(entry_priv->desc, 2, word);
 741
 742		word = rt2x00_desc_read(entry_priv->desc, 1);
 743		rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
 744		rt2x00_desc_write(entry_priv->desc, 1, word);
 745
 746		word = rt2x00_desc_read(entry_priv->desc, 0);
 747		rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 748		rt2x00_desc_write(entry_priv->desc, 0, word);
 749	} else {
 750		word = rt2x00_desc_read(entry_priv->desc, 0);
 751		rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 752		rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 753		rt2x00_desc_write(entry_priv->desc, 0, word);
 754	}
 755}
 756
 757static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
 758{
 759	struct queue_entry_priv_mmio *entry_priv;
 760	u32 reg;
 761
 762	/*
 763	 * Initialize registers.
 764	 */
 765	reg = rt2x00mmio_register_read(rt2x00dev, TXCSR2);
 766	rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 767	rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 768	rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
 769	rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 770	rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);
 771
 772	entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 773	reg = rt2x00mmio_register_read(rt2x00dev, TXCSR3);
 774	rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 775			   entry_priv->desc_dma);
 776	rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);
 777
 778	entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 779	reg = rt2x00mmio_register_read(rt2x00dev, TXCSR5);
 780	rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 781			   entry_priv->desc_dma);
 782	rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);
 783
 784	entry_priv = rt2x00dev->atim->entries[0].priv_data;
 785	reg = rt2x00mmio_register_read(rt2x00dev, TXCSR4);
 786	rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 787			   entry_priv->desc_dma);
 788	rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);
 789
 790	entry_priv = rt2x00dev->bcn->entries[0].priv_data;
 791	reg = rt2x00mmio_register_read(rt2x00dev, TXCSR6);
 792	rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 793			   entry_priv->desc_dma);
 794	rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);
 795
 796	reg = rt2x00mmio_register_read(rt2x00dev, RXCSR1);
 797	rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 798	rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 799	rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);
 800
 801	entry_priv = rt2x00dev->rx->entries[0].priv_data;
 802	reg = rt2x00mmio_register_read(rt2x00dev, RXCSR2);
 803	rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 804			   entry_priv->desc_dma);
 805	rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
 806
 807	return 0;
 808}
 809
 810static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
 811{
 812	u32 reg;
 813
 814	rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002);
 815	rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002);
 816	rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00023f20);
 817	rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002);
 818
 819	reg = rt2x00mmio_register_read(rt2x00dev, TIMECSR);
 820	rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 821	rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 822	rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 823	rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);
 824
 825	reg = rt2x00mmio_register_read(rt2x00dev, CSR9);
 826	rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 827			   (rt2x00dev->rx->data_size / 128));
 828	rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
 829
 830	reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
 831	rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 832	rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 833	rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 834	rt2x00_set_field32(&reg, CSR14_TCFP, 0);
 835	rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
 836	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 837	rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
 838	rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
 839	rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
 840
 841	rt2x00mmio_register_write(rt2x00dev, CNT3, 0x3f080000);
 842
 843	reg = rt2x00mmio_register_read(rt2x00dev, ARCSR0);
 844	rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
 845	rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
 846	rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
 847	rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
 848	rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg);
 849
 850	reg = rt2x00mmio_register_read(rt2x00dev, RXCSR3);
 851	rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
 852	rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 853	rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
 854	rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 855	rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
 856	rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 857	rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg);
 858
 859	rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 860
 861	if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 862		return -EBUSY;
 863
 864	rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00217223);
 865	rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518);
 866
 867	reg = rt2x00mmio_register_read(rt2x00dev, MACCSR2);
 868	rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 869	rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);
 870
 871	reg = rt2x00mmio_register_read(rt2x00dev, RALINKCSR);
 872	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 873	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
 874	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 875	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
 876	rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);
 877
 878	reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
 879	rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 880	rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 881	rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 882	rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
 883
 884	reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
 885	rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 886	rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 887	rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
 888
 889	/*
 890	 * We must clear the FCS and FIFO error count.
 891	 * These registers are cleared on read,
 892	 * so we may pass a useless variable to store the value.
 893	 */
 894	reg = rt2x00mmio_register_read(rt2x00dev, CNT0);
 895	reg = rt2x00mmio_register_read(rt2x00dev, CNT4);
 896
 897	return 0;
 898}
 899
 900static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
 901{
 902	unsigned int i;
 903	u8 value;
 904
 905	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 906		value = rt2400pci_bbp_read(rt2x00dev, 0);
 907		if ((value != 0xff) && (value != 0x00))
 908			return 0;
 909		udelay(REGISTER_BUSY_DELAY);
 910	}
 911
 912	rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
 913	return -EACCES;
 914}
 915
 916static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 917{
 918	unsigned int i;
 919	u16 eeprom;
 920	u8 reg_id;
 921	u8 value;
 922
 923	if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
 924		return -EACCES;
 925
 926	rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
 927	rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
 928	rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
 929	rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
 930	rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
 931	rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
 932	rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
 933	rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
 934	rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
 935	rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
 936	rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
 937	rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
 938	rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
 939	rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
 940
 941	for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 942		eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i);
 943
 944		if (eeprom != 0xffff && eeprom != 0x0000) {
 945			reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 946			value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 947			rt2400pci_bbp_write(rt2x00dev, reg_id, value);
 948		}
 949	}
 950
 951	return 0;
 952}
 953
 954/*
 955 * Device state switch handlers.
 956 */
 957static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 958				 enum dev_state state)
 959{
 960	int mask = (state == STATE_RADIO_IRQ_OFF);
 961	u32 reg;
 962	unsigned long flags;
 963
 964	/*
 965	 * When interrupts are being enabled, the interrupt registers
 966	 * should clear the register to assure a clean state.
 967	 */
 968	if (state == STATE_RADIO_IRQ_ON) {
 969		reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
 970		rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
 971	}
 972
 973	/*
 974	 * Only toggle the interrupts bits we are going to use.
 975	 * Non-checked interrupt bits are disabled by default.
 976	 */
 977	spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
 978
 979	reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
 980	rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
 981	rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
 982	rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
 983	rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
 984	rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
 985	rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
 986
 987	spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
 988
 989	if (state == STATE_RADIO_IRQ_OFF) {
 990		/*
 991		 * Ensure that all tasklets are finished before
 992		 * disabling the interrupts.
 993		 */
 994		tasklet_kill(&rt2x00dev->txstatus_tasklet);
 995		tasklet_kill(&rt2x00dev->rxdone_tasklet);
 996		tasklet_kill(&rt2x00dev->tbtt_tasklet);
 997	}
 998}
 999
1000static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1001{
1002	/*
1003	 * Initialize all registers.
1004	 */
1005	if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
1006		     rt2400pci_init_registers(rt2x00dev) ||
1007		     rt2400pci_init_bbp(rt2x00dev)))
1008		return -EIO;
1009
1010	return 0;
1011}
1012
1013static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1014{
1015	/*
1016	 * Disable power
1017	 */
1018	rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0);
1019}
1020
1021static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
1022			       enum dev_state state)
1023{
1024	u32 reg, reg2;
1025	unsigned int i;
1026	bool put_to_sleep;
1027	u8 bbp_state;
1028	u8 rf_state;
1029
1030	put_to_sleep = (state != STATE_AWAKE);
1031
1032	reg = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);
1033	rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1034	rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1035	rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1036	rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1037	rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1038
1039	/*
1040	 * Device is not guaranteed to be in the requested state yet.
1041	 * We must wait until the register indicates that the
1042	 * device has entered the correct state.
1043	 */
1044	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1045		reg2 = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);
1046		bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1047		rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
1048		if (bbp_state == state && rf_state == state)
1049			return 0;
1050		rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1051		msleep(10);
1052	}
1053
1054	return -EBUSY;
1055}
1056
1057static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1058				      enum dev_state state)
1059{
1060	int retval = 0;
1061
1062	switch (state) {
1063	case STATE_RADIO_ON:
1064		retval = rt2400pci_enable_radio(rt2x00dev);
1065		break;
1066	case STATE_RADIO_OFF:
1067		rt2400pci_disable_radio(rt2x00dev);
1068		break;
1069	case STATE_RADIO_IRQ_ON:
1070	case STATE_RADIO_IRQ_OFF:
1071		rt2400pci_toggle_irq(rt2x00dev, state);
1072		break;
1073	case STATE_DEEP_SLEEP:
1074	case STATE_SLEEP:
1075	case STATE_STANDBY:
1076	case STATE_AWAKE:
1077		retval = rt2400pci_set_state(rt2x00dev, state);
1078		break;
1079	default:
1080		retval = -ENOTSUPP;
1081		break;
1082	}
1083
1084	if (unlikely(retval))
1085		rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1086			   state, retval);
1087
1088	return retval;
1089}
1090
1091/*
1092 * TX descriptor initialization
1093 */
1094static void rt2400pci_write_tx_desc(struct queue_entry *entry,
1095				    struct txentry_desc *txdesc)
1096{
1097	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1098	struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1099	__le32 *txd = entry_priv->desc;
1100	u32 word;
1101
1102	/*
1103	 * Start writing the descriptor words.
1104	 */
1105	word = rt2x00_desc_read(txd, 1);
1106	rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1107	rt2x00_desc_write(txd, 1, word);
1108
1109	word = rt2x00_desc_read(txd, 2);
1110	rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1111	rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
1112	rt2x00_desc_write(txd, 2, word);
1113
1114	word = rt2x00_desc_read(txd, 3);
1115	rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
1116	rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1117	rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1118	rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
1119	rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1120	rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1121	rt2x00_desc_write(txd, 3, word);
1122
1123	word = rt2x00_desc_read(txd, 4);
1124	rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW,
1125			   txdesc->u.plcp.length_low);
1126	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1127	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1128	rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH,
1129			   txdesc->u.plcp.length_high);
1130	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1131	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1132	rt2x00_desc_write(txd, 4, word);
1133
1134	/*
1135	 * Writing TXD word 0 must the last to prevent a race condition with
1136	 * the device, whereby the device may take hold of the TXD before we
1137	 * finished updating it.
1138	 */
1139	word = rt2x00_desc_read(txd, 0);
1140	rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1141	rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1142	rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1143			   test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1144	rt2x00_set_field32(&word, TXD_W0_ACK,
1145			   test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1146	rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1147			   test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1148	rt2x00_set_field32(&word, TXD_W0_RTS,
1149			   test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1150	rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1151	rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1152			   test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1153	rt2x00_desc_write(txd, 0, word);
1154
1155	/*
1156	 * Register descriptor details in skb frame descriptor.
1157	 */
1158	skbdesc->desc = txd;
1159	skbdesc->desc_len = TXD_DESC_SIZE;
1160}
1161
1162/*
1163 * TX data initialization
1164 */
1165static void rt2400pci_write_beacon(struct queue_entry *entry,
1166				   struct txentry_desc *txdesc)
1167{
1168	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1169	u32 reg;
1170
1171	/*
1172	 * Disable beaconing while we are reloading the beacon data,
1173	 * otherwise we might be sending out invalid data.
1174	 */
1175	reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
1176	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1177	rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1178
1179	if (rt2x00queue_map_txskb(entry)) {
1180		rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n");
1181		goto out;
1182	}
1183	/*
1184	 * Enable beaconing again.
1185	 */
1186	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1187	/*
1188	 * Write the TX descriptor for the beacon.
1189	 */
1190	rt2400pci_write_tx_desc(entry, txdesc);
1191
1192	/*
1193	 * Dump beacon to userspace through debugfs.
1194	 */
1195	rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1196out:
1197	/*
1198	 * Enable beaconing again.
1199	 */
1200	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1201	rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1202}
1203
1204/*
1205 * RX control handlers
1206 */
1207static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1208				  struct rxdone_entry_desc *rxdesc)
1209{
1210	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1211	struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1212	u32 word0;
1213	u32 word2;
1214	u32 word3;
1215	u32 word4;
1216	u64 tsf;
1217	u32 rx_low;
1218	u32 rx_high;
1219
1220	word0 = rt2x00_desc_read(entry_priv->desc, 0);
1221	word2 = rt2x00_desc_read(entry_priv->desc, 2);
1222	word3 = rt2x00_desc_read(entry_priv->desc, 3);
1223	word4 = rt2x00_desc_read(entry_priv->desc, 4);
1224
1225	if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1226		rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1227	if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1228		rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1229
1230	/*
1231	 * We only get the lower 32bits from the timestamp,
1232	 * to get the full 64bits we must complement it with
1233	 * the timestamp from get_tsf().
1234	 * Note that when a wraparound of the lower 32bits
1235	 * has occurred between the frame arrival and the get_tsf()
1236	 * call, we must decrease the higher 32bits with 1 to get
1237	 * to correct value.
1238	 */
1239	tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw, NULL);
1240	rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1241	rx_high = upper_32_bits(tsf);
1242
1243	if ((u32)tsf <= rx_low)
1244		rx_high--;
1245
1246	/*
1247	 * Obtain the status about this packet.
1248	 * The signal is the PLCP value, and needs to be stripped
1249	 * of the preamble bit (0x08).
1250	 */
1251	rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1252	rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1253	rxdesc->rssi = rt2x00_get_field32(word3, RXD_W3_RSSI) -
1254	    entry->queue->rt2x00dev->rssi_offset;
1255	rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1256
1257	rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1258	if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1259		rxdesc->dev_flags |= RXDONE_MY_BSS;
1260}
1261
1262/*
1263 * Interrupt functions.
1264 */
1265static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1266			     const enum data_queue_qid queue_idx)
1267{
1268	struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1269	struct queue_entry_priv_mmio *entry_priv;
1270	struct queue_entry *entry;
1271	struct txdone_entry_desc txdesc;
1272	u32 word;
1273
1274	while (!rt2x00queue_empty(queue)) {
1275		entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1276		entry_priv = entry->priv_data;
1277		word = rt2x00_desc_read(entry_priv->desc, 0);
1278
1279		if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1280		    !rt2x00_get_field32(word, TXD_W0_VALID))
1281			break;
1282
1283		/*
1284		 * Obtain the status about this packet.
1285		 */
1286		txdesc.flags = 0;
1287		switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1288		case 0: /* Success */
1289		case 1: /* Success with retry */
1290			__set_bit(TXDONE_SUCCESS, &txdesc.flags);
1291			break;
1292		case 2: /* Failure, excessive retries */
1293			__set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1294			fallthrough;	/* this is a failed frame! */
1295		default: /* Failure */
1296			__set_bit(TXDONE_FAILURE, &txdesc.flags);
1297		}
1298		txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1299
1300		rt2x00lib_txdone(entry, &txdesc);
1301	}
1302}
1303
1304static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1305					      struct rt2x00_field32 irq_field)
1306{
1307	u32 reg;
1308
1309	/*
1310	 * Enable a single interrupt. The interrupt mask register
1311	 * access needs locking.
1312	 */
1313	spin_lock_irq(&rt2x00dev->irqmask_lock);
1314
1315	reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1316	rt2x00_set_field32(&reg, irq_field, 0);
1317	rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1318
1319	spin_unlock_irq(&rt2x00dev->irqmask_lock);
1320}
1321
1322static void rt2400pci_txstatus_tasklet(struct tasklet_struct *t)
1323{
1324	struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
1325						    txstatus_tasklet);
1326	u32 reg;
1327
1328	/*
1329	 * Handle all tx queues.
1330	 */
1331	rt2400pci_txdone(rt2x00dev, QID_ATIM);
1332	rt2400pci_txdone(rt2x00dev, QID_AC_VO);
1333	rt2400pci_txdone(rt2x00dev, QID_AC_VI);
1334
1335	/*
1336	 * Enable all TXDONE interrupts again.
1337	 */
1338	if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
1339		spin_lock_irq(&rt2x00dev->irqmask_lock);
1340
1341		reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1342		rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1343		rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1344		rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
1345		rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1346
1347		spin_unlock_irq(&rt2x00dev->irqmask_lock);
1348	}
1349}
1350
1351static void rt2400pci_tbtt_tasklet(struct tasklet_struct *t)
1352{
1353	struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, tbtt_tasklet);
1354	rt2x00lib_beacondone(rt2x00dev);
1355	if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1356		rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
1357}
1358
1359static void rt2400pci_rxdone_tasklet(struct tasklet_struct *t)
1360{
1361	struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
1362						    rxdone_tasklet);
1363	if (rt2x00mmio_rxdone(rt2x00dev))
1364		tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1365	else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1366		rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
1367}
1368
1369static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1370{
1371	struct rt2x00_dev *rt2x00dev = dev_instance;
1372	u32 reg, mask;
1373
1374	/*
1375	 * Get the interrupt sources & saved to local variable.
1376	 * Write register value back to clear pending interrupts.
1377	 */
1378	reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
1379	rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1380
1381	if (!reg)
1382		return IRQ_NONE;
1383
1384	if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1385		return IRQ_HANDLED;
1386
1387	mask = reg;
1388
1389	/*
1390	 * Schedule tasklets for interrupt handling.
1391	 */
1392	if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1393		tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1394
1395	if (rt2x00_get_field32(reg, CSR7_RXDONE))
1396		tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1397
1398	if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1399	    rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1400	    rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1401		tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1402		/*
1403		 * Mask out all txdone interrupts.
1404		 */
1405		rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1406		rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1407		rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1408	}
1409
1410	/*
1411	 * Disable all interrupts for which a tasklet was scheduled right now,
1412	 * the tasklet will reenable the appropriate interrupts.
1413	 */
1414	spin_lock(&rt2x00dev->irqmask_lock);
1415
1416	reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1417	reg |= mask;
1418	rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1419
1420	spin_unlock(&rt2x00dev->irqmask_lock);
1421
1422
1423
1424	return IRQ_HANDLED;
1425}
1426
1427/*
1428 * Device probe functions.
1429 */
1430static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1431{
1432	struct eeprom_93cx6 eeprom;
1433	u32 reg;
1434	u16 word;
1435	u8 *mac;
1436
1437	reg = rt2x00mmio_register_read(rt2x00dev, CSR21);
1438
1439	eeprom.data = rt2x00dev;
1440	eeprom.register_read = rt2400pci_eepromregister_read;
1441	eeprom.register_write = rt2400pci_eepromregister_write;
1442	eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1443	    PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1444	eeprom.reg_data_in = 0;
1445	eeprom.reg_data_out = 0;
1446	eeprom.reg_data_clock = 0;
1447	eeprom.reg_chip_select = 0;
1448
1449	eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1450			       EEPROM_SIZE / sizeof(u16));
1451
1452	/*
1453	 * Start validation of the data that has been read.
1454	 */
1455	mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1456	rt2x00lib_set_mac_address(rt2x00dev, mac);
1457
1458	word = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
1459	if (word == 0xffff) {
1460		rt2x00_err(rt2x00dev, "Invalid EEPROM data detected\n");
1461		return -EINVAL;
1462	}
1463
1464	return 0;
1465}
1466
1467static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1468{
1469	u32 reg;
1470	u16 value;
1471	u16 eeprom;
1472
1473	/*
1474	 * Read EEPROM word for configuration.
1475	 */
1476	eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
1477
1478	/*
1479	 * Identify RF chipset.
1480	 */
1481	value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1482	reg = rt2x00mmio_register_read(rt2x00dev, CSR0);
1483	rt2x00_set_chip(rt2x00dev, RT2460, value,
1484			rt2x00_get_field32(reg, CSR0_REVISION));
1485
1486	if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
1487		rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
1488		return -ENODEV;
1489	}
1490
1491	/*
1492	 * Identify default antenna configuration.
1493	 */
1494	rt2x00dev->default_ant.tx =
1495	    rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1496	rt2x00dev->default_ant.rx =
1497	    rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1498
1499	/*
1500	 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1501	 * I am not 100% sure about this, but the legacy drivers do not
1502	 * indicate antenna swapping in software is required when
1503	 * diversity is enabled.
1504	 */
1505	if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1506		rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1507	if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1508		rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1509
1510	/*
1511	 * Store led mode, for correct led behaviour.
1512	 */
1513#ifdef CONFIG_RT2X00_LIB_LEDS
1514	value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1515
1516	rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1517	if (value == LED_MODE_TXRX_ACTIVITY ||
1518	    value == LED_MODE_DEFAULT ||
1519	    value == LED_MODE_ASUS)
1520		rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1521				   LED_TYPE_ACTIVITY);
1522#endif /* CONFIG_RT2X00_LIB_LEDS */
1523
1524	/*
1525	 * Detect if this device has an hardware controlled radio.
1526	 */
1527	if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1528		__set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1529
1530	/*
1531	 * Check if the BBP tuning should be enabled.
1532	 */
1533	if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1534		__set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1535
1536	return 0;
1537}
1538
1539/*
1540 * RF value list for RF2420 & RF2421
1541 * Supports: 2.4 GHz
1542 */
1543static const struct rf_channel rf_vals_b[] = {
1544	{ 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1545	{ 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1546	{ 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1547	{ 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1548	{ 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1549	{ 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1550	{ 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1551	{ 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1552	{ 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1553	{ 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1554	{ 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1555	{ 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1556	{ 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1557	{ 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1558};
1559
1560static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1561{
1562	struct hw_mode_spec *spec = &rt2x00dev->spec;
1563	struct channel_info *info;
1564	u8 *tx_power;
1565	unsigned int i;
1566
1567	/*
1568	 * Initialize all hw fields.
1569	 */
1570	ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
1571	ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
1572	ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
1573	ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
1574
1575	SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1576	SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1577				rt2x00_eeprom_addr(rt2x00dev,
1578						   EEPROM_MAC_ADDR_0));
1579
1580	/*
1581	 * Initialize hw_mode information.
1582	 */
1583	spec->supported_bands = SUPPORT_BAND_2GHZ;
1584	spec->supported_rates = SUPPORT_RATE_CCK;
1585
1586	spec->num_channels = ARRAY_SIZE(rf_vals_b);
1587	spec->channels = rf_vals_b;
1588
1589	/*
1590	 * Create channel information array
1591	 */
1592	info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
1593	if (!info)
1594		return -ENOMEM;
1595
1596	spec->channels_info = info;
1597
1598	tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1599	for (i = 0; i < 14; i++) {
1600		info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER);
1601		info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1602	}
1603
1604	return 0;
1605}
1606
1607static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1608{
1609	int retval;
1610	u32 reg;
1611
1612	/*
1613	 * Allocate eeprom data.
1614	 */
1615	retval = rt2400pci_validate_eeprom(rt2x00dev);
1616	if (retval)
1617		return retval;
1618
1619	retval = rt2400pci_init_eeprom(rt2x00dev);
1620	if (retval)
1621		return retval;
1622
1623	/*
1624	 * Enable rfkill polling by setting GPIO direction of the
1625	 * rfkill switch GPIO pin correctly.
1626	 */
1627	reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);
1628	rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);
1629	rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
1630
1631	/*
1632	 * Initialize hw specifications.
1633	 */
1634	retval = rt2400pci_probe_hw_mode(rt2x00dev);
1635	if (retval)
1636		return retval;
1637
1638	/*
1639	 * This device requires the atim queue and DMA-mapped skbs.
1640	 */
1641	__set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1642	__set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1643	__set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
1644
1645	/*
1646	 * Set the rssi offset.
1647	 */
1648	rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1649
1650	return 0;
1651}
1652
1653/*
1654 * IEEE80211 stack callback functions.
1655 */
1656static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1657			     struct ieee80211_vif *vif,
1658			     unsigned int link_id, u16 queue,
1659			     const struct ieee80211_tx_queue_params *params)
1660{
1661	struct rt2x00_dev *rt2x00dev = hw->priv;
1662
1663	/*
1664	 * We don't support variating cw_min and cw_max variables
1665	 * per queue. So by default we only configure the TX queue,
1666	 * and ignore all other configurations.
1667	 */
1668	if (queue != 0)
1669		return -EINVAL;
1670
1671	if (rt2x00mac_conf_tx(hw, vif, link_id, queue, params))
1672		return -EINVAL;
1673
1674	/*
1675	 * Write configuration to register.
1676	 */
1677	rt2400pci_config_cw(rt2x00dev,
1678			    rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1679
1680	return 0;
1681}
1682
1683static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw,
1684			     struct ieee80211_vif *vif)
1685{
1686	struct rt2x00_dev *rt2x00dev = hw->priv;
1687	u64 tsf;
1688	u32 reg;
1689
1690	reg = rt2x00mmio_register_read(rt2x00dev, CSR17);
1691	tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1692	reg = rt2x00mmio_register_read(rt2x00dev, CSR16);
1693	tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1694
1695	return tsf;
1696}
1697
1698static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1699{
1700	struct rt2x00_dev *rt2x00dev = hw->priv;
1701	u32 reg;
1702
1703	reg = rt2x00mmio_register_read(rt2x00dev, CSR15);
1704	return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1705}
1706
1707static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1708	.add_chanctx = ieee80211_emulate_add_chanctx,
1709	.remove_chanctx = ieee80211_emulate_remove_chanctx,
1710	.change_chanctx = ieee80211_emulate_change_chanctx,
1711	.switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx,
1712	.tx			= rt2x00mac_tx,
1713	.wake_tx_queue		= ieee80211_handle_wake_tx_queue,
1714	.start			= rt2x00mac_start,
1715	.stop			= rt2x00mac_stop,
1716	.add_interface		= rt2x00mac_add_interface,
1717	.remove_interface	= rt2x00mac_remove_interface,
1718	.config			= rt2x00mac_config,
1719	.configure_filter	= rt2x00mac_configure_filter,
1720	.sw_scan_start		= rt2x00mac_sw_scan_start,
1721	.sw_scan_complete	= rt2x00mac_sw_scan_complete,
1722	.get_stats		= rt2x00mac_get_stats,
1723	.bss_info_changed	= rt2x00mac_bss_info_changed,
1724	.conf_tx		= rt2400pci_conf_tx,
1725	.get_tsf		= rt2400pci_get_tsf,
1726	.tx_last_beacon		= rt2400pci_tx_last_beacon,
1727	.rfkill_poll		= rt2x00mac_rfkill_poll,
1728	.flush			= rt2x00mac_flush,
1729	.set_antenna		= rt2x00mac_set_antenna,
1730	.get_antenna		= rt2x00mac_get_antenna,
1731	.get_ringparam		= rt2x00mac_get_ringparam,
1732	.tx_frames_pending	= rt2x00mac_tx_frames_pending,
1733};
1734
1735static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1736	.irq_handler		= rt2400pci_interrupt,
1737	.txstatus_tasklet	= rt2400pci_txstatus_tasklet,
1738	.tbtt_tasklet		= rt2400pci_tbtt_tasklet,
1739	.rxdone_tasklet		= rt2400pci_rxdone_tasklet,
1740	.probe_hw		= rt2400pci_probe_hw,
1741	.initialize		= rt2x00mmio_initialize,
1742	.uninitialize		= rt2x00mmio_uninitialize,
1743	.get_entry_state	= rt2400pci_get_entry_state,
1744	.clear_entry		= rt2400pci_clear_entry,
1745	.set_device_state	= rt2400pci_set_device_state,
1746	.rfkill_poll		= rt2400pci_rfkill_poll,
1747	.link_stats		= rt2400pci_link_stats,
1748	.reset_tuner		= rt2400pci_reset_tuner,
1749	.link_tuner		= rt2400pci_link_tuner,
1750	.start_queue		= rt2400pci_start_queue,
1751	.kick_queue		= rt2400pci_kick_queue,
1752	.stop_queue		= rt2400pci_stop_queue,
1753	.flush_queue		= rt2x00mmio_flush_queue,
1754	.write_tx_desc		= rt2400pci_write_tx_desc,
1755	.write_beacon		= rt2400pci_write_beacon,
1756	.fill_rxdone		= rt2400pci_fill_rxdone,
1757	.config_filter		= rt2400pci_config_filter,
1758	.config_intf		= rt2400pci_config_intf,
1759	.config_erp		= rt2400pci_config_erp,
1760	.config_ant		= rt2400pci_config_ant,
1761	.config			= rt2400pci_config,
1762};
1763
1764static void rt2400pci_queue_init(struct data_queue *queue)
1765{
1766	switch (queue->qid) {
1767	case QID_RX:
1768		queue->limit = 24;
1769		queue->data_size = DATA_FRAME_SIZE;
1770		queue->desc_size = RXD_DESC_SIZE;
1771		queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1772		break;
1773
1774	case QID_AC_VO:
1775	case QID_AC_VI:
1776	case QID_AC_BE:
1777	case QID_AC_BK:
1778		queue->limit = 24;
1779		queue->data_size = DATA_FRAME_SIZE;
1780		queue->desc_size = TXD_DESC_SIZE;
1781		queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1782		break;
1783
1784	case QID_BEACON:
1785		queue->limit = 1;
1786		queue->data_size = MGMT_FRAME_SIZE;
1787		queue->desc_size = TXD_DESC_SIZE;
1788		queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1789		break;
1790
1791	case QID_ATIM:
1792		queue->limit = 8;
1793		queue->data_size = DATA_FRAME_SIZE;
1794		queue->desc_size = TXD_DESC_SIZE;
1795		queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1796		break;
1797
1798	default:
1799		BUG();
1800		break;
1801	}
1802}
1803
1804static const struct rt2x00_ops rt2400pci_ops = {
1805	.name			= KBUILD_MODNAME,
1806	.max_ap_intf		= 1,
1807	.eeprom_size		= EEPROM_SIZE,
1808	.rf_size		= RF_SIZE,
1809	.tx_queues		= NUM_TX_QUEUES,
1810	.queue_init		= rt2400pci_queue_init,
1811	.lib			= &rt2400pci_rt2x00_ops,
1812	.hw			= &rt2400pci_mac80211_ops,
1813#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1814	.debugfs		= &rt2400pci_rt2x00debug,
1815#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1816};
1817
1818/*
1819 * RT2400pci module information.
1820 */
1821static const struct pci_device_id rt2400pci_device_table[] = {
1822	{ PCI_DEVICE(0x1814, 0x0101) },
1823	{ 0, }
1824};
1825
1826
1827MODULE_AUTHOR(DRV_PROJECT);
1828MODULE_VERSION(DRV_VERSION);
1829MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1830MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1831MODULE_LICENSE("GPL");
1832
1833static int rt2400pci_probe(struct pci_dev *pci_dev,
1834			   const struct pci_device_id *id)
1835{
1836	return rt2x00pci_probe(pci_dev, &rt2400pci_ops);
1837}
1838
1839static struct pci_driver rt2400pci_driver = {
1840	.name		= KBUILD_MODNAME,
1841	.id_table	= rt2400pci_device_table,
1842	.probe		= rt2400pci_probe,
1843	.remove		= rt2x00pci_remove,
1844	.driver.pm	= &rt2x00pci_pm_ops,
1845};
1846
1847module_pci_driver(rt2400pci_driver);