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mmio.c
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linux-6.19.14/drivers/net/wireless/mediatek/mt76/mt7996/mmio.c
1// SPDX-License-Identifier: BSD-3-Clause-Clear 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6#include <linux/kernel.h> 7#include <linux/module.h> 8#include <linux/pci.h> 9#include <linux/rtnetlink.h> 10 11#include "mt7996.h" 12#include "mac.h" 13#include "mcu.h" 14#include "../trace.h" 15#include "../dma.h" 16 17static bool wed_enable; 18module_param(wed_enable, bool, 0644); 19 20static const struct __base mt7996_reg_base[] = { 21 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } }, 22 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } }, 23 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } }, 24 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } }, 25 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } }, 26 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } }, 27 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } }, 28 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } }, 29 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } }, 30 [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } }, 31}; 32 33static const u32 mt7996_offs[] = { 34 [MIB_RVSR0] = 0x720, 35 [MIB_RVSR1] = 0x724, 36 [MIB_BTSCR5] = 0x788, 37 [MIB_BTSCR6] = 0x798, 38 [MIB_RSCR1] = 0x7ac, 39 [MIB_RSCR27] = 0x954, 40 [MIB_RSCR28] = 0x958, 41 [MIB_RSCR29] = 0x95c, 42 [MIB_RSCR30] = 0x960, 43 [MIB_RSCR31] = 0x964, 44 [MIB_RSCR33] = 0x96c, 45 [MIB_RSCR35] = 0x974, 46 [MIB_RSCR36] = 0x978, 47 [MIB_BSCR0] = 0x9cc, 48 [MIB_BSCR1] = 0x9d0, 49 [MIB_BSCR2] = 0x9d4, 50 [MIB_BSCR3] = 0x9d8, 51 [MIB_BSCR4] = 0x9dc, 52 [MIB_BSCR5] = 0x9e0, 53 [MIB_BSCR6] = 0x9e4, 54 [MIB_BSCR7] = 0x9e8, 55 [MIB_BSCR17] = 0xa10, 56 [MIB_TRDR1] = 0xa28, 57 [HIF_REMAP_L1] = 0x24, 58 [HIF_REMAP_BASE_L1] = 0x130000, 59 [HIF_REMAP_L2] = 0x1b4, 60 [HIF_REMAP_BASE_L2] = 0x1000, 61 [CBTOP1_PHY_END] = 0x77ffffff, 62 [INFRA_MCU_END] = 0x7c3fffff, 63 [WTBLON_WDUCR] = 0x370, 64 [WTBL_UPDATE] = 0x380, 65 [WTBL_ITCR] = 0x3b0, 66 [WTBL_ITCR0] = 0x3b8, 67 [WTBL_ITCR1] = 0x3bc, 68}; 69 70static const u32 mt7992_offs[] = { 71 [MIB_RVSR0] = 0x760, 72 [MIB_RVSR1] = 0x764, 73 [MIB_BTSCR5] = 0x7c8, 74 [MIB_BTSCR6] = 0x7d8, 75 [MIB_RSCR1] = 0x7f0, 76 [MIB_RSCR27] = 0x998, 77 [MIB_RSCR28] = 0x99c, 78 [MIB_RSCR29] = 0x9a0, 79 [MIB_RSCR30] = 0x9a4, 80 [MIB_RSCR31] = 0x9a8, 81 [MIB_RSCR33] = 0x9b0, 82 [MIB_RSCR35] = 0x9b8, 83 [MIB_RSCR36] = 0x9bc, 84 [MIB_BSCR0] = 0xac8, 85 [MIB_BSCR1] = 0xacc, 86 [MIB_BSCR2] = 0xad0, 87 [MIB_BSCR3] = 0xad4, 88 [MIB_BSCR4] = 0xad8, 89 [MIB_BSCR5] = 0xadc, 90 [MIB_BSCR6] = 0xae0, 91 [MIB_BSCR7] = 0xae4, 92 [MIB_BSCR17] = 0xb0c, 93 [MIB_TRDR1] = 0xb24, 94 [HIF_REMAP_L1] = 0x8, 95 [HIF_REMAP_BASE_L1] = 0x40000, 96 [HIF_REMAP_L2] = 0x1b4, 97 [HIF_REMAP_BASE_L2] = 0x1000, 98 [CBTOP1_PHY_END] = 0x77ffffff, 99 [INFRA_MCU_END] = 0x7c3fffff, 100 [WTBLON_WDUCR] = 0x370, 101 [WTBL_UPDATE] = 0x380, 102 [WTBL_ITCR] = 0x3b0, 103 [WTBL_ITCR0] = 0x3b8, 104 [WTBL_ITCR1] = 0x3bc, 105}; 106 107static const u32 mt7990_offs[] = { 108 [MIB_RVSR0] = 0x800, 109 [MIB_RVSR1] = 0x804, 110 [MIB_BTSCR5] = 0x868, 111 [MIB_BTSCR6] = 0x878, 112 [MIB_RSCR1] = 0x890, 113 [MIB_RSCR27] = 0xa38, 114 [MIB_RSCR28] = 0xa3c, 115 [MIB_RSCR29] = 0xa40, 116 [MIB_RSCR30] = 0xa44, 117 [MIB_RSCR31] = 0xa48, 118 [MIB_RSCR33] = 0xa50, 119 [MIB_RSCR35] = 0xa58, 120 [MIB_RSCR36] = 0xa5c, 121 [MIB_BSCR0] = 0xbb8, 122 [MIB_BSCR1] = 0xbbc, 123 [MIB_BSCR2] = 0xbc0, 124 [MIB_BSCR3] = 0xbc4, 125 [MIB_BSCR4] = 0xbc8, 126 [MIB_BSCR5] = 0xbcc, 127 [MIB_BSCR6] = 0xbd0, 128 [MIB_BSCR7] = 0xbd4, 129 [MIB_BSCR17] = 0xbfc, 130 [MIB_TRDR1] = 0xc14, 131 [HIF_REMAP_L1] = 0x8, 132 [HIF_REMAP_BASE_L1] = 0x40000, 133 [HIF_REMAP_L2] = 0x1b8, 134 [HIF_REMAP_BASE_L2] = 0x110000, 135 [CBTOP1_PHY_END] = 0x7fffffff, 136 [INFRA_MCU_END] = 0x7cffffff, 137 [WTBLON_WDUCR] = 0x400, 138 [WTBL_UPDATE] = 0x410, 139 [WTBL_ITCR] = 0x440, 140 [WTBL_ITCR0] = 0x448, 141 [WTBL_ITCR1] = 0x44c, 142}; 143 144static const struct __map mt7996_reg_map[] = { 145 { 0x54000000, 0x02000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */ 146 { 0x55000000, 0x03000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */ 147 { 0x56000000, 0x04000, 0x1000 }, /* WFDMA reserved */ 148 { 0x57000000, 0x05000, 0x1000 }, /* WFDMA MCU wrap CR */ 149 { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 150 { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */ 151 { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */ 152 { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */ 153 { 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */ 154 { 0x74030000, 0x10000, 0x1000 }, /* PCIe MAC */ 155 { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 156 { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 157 { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 158 { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 159 { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 160 { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 161 { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */ 162 { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 163 { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */ 164 { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 165 { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 166 { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 167 { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 168 { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 169 { 0x820ca000, 0x26000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */ 170 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 171 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */ 172 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 173 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */ 174 { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 175 { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 176 { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 177 { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 178 { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 179 { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 180 { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 181 { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 182 { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 183 { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 184 { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 185 { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 186 { 0x820cc000, 0xa5000, 0x2000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */ 187 { 0x820c4000, 0xa8000, 0x4000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */ 188 { 0x820b0000, 0xae000, 0x1000 }, /* [APB2] WFSYS_ON */ 189 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 190 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 191 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, wfdma */ 192 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */ 193 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 194 { 0x0, 0x0, 0x0 }, /* imply end of search */ 195}; 196 197static const struct __map mt7990_reg_map[] = { 198 {0x54000000, 0x02000, 0x1000}, /* WFDMA_0 (PCIE0 MCU DMA0) */ 199 {0x55000000, 0x03000, 0x1000}, /* WFDMA_1 (PCIE0 MCU DMA1) */ 200 {0x56000000, 0x04000, 0x1000}, /* WFDMA_2 (Reserved) */ 201 {0x57000000, 0x05000, 0x1000}, /* WFDMA_3 (MCU wrap CR) */ 202 {0x58000000, 0x06000, 0x1000}, /* WFDMA_4 (PCIE1 MCU DMA0 (MEM_DMA)) */ 203 {0x59000000, 0x07000, 0x1000}, /* WFDMA_5 (PCIE1 MCU DMA1) */ 204 {0x820c0000, 0x08000, 0x4000}, /* WF_UMAC_TOP (PLE) */ 205 {0x820c8000, 0x0c000, 0x2000}, /* WF_UMAC_TOP (PSE) */ 206 {0x820cc000, 0x0e000, 0x2000}, /* WF_UMAC_TOP (PP) */ 207 {0x820e0000, 0x20000, 0x0400}, /* WF_LMAC_TOP BN0 (WF_CFG) */ 208 {0x820e1000, 0x20400, 0x0200}, /* WF_LMAC_TOP BN0 (WF_TRB) */ 209 {0x820e2000, 0x20800, 0x0400}, /* WF_LMAC_TOP BN0 (WF_AGG) */ 210 {0x820e3000, 0x20c00, 0x0400}, /* WF_LMAC_TOP BN0 (WF_ARB) */ 211 {0x820e4000, 0x21000, 0x0400}, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 212 {0x820e5000, 0x21400, 0x0800}, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 213 {0x820ce000, 0x21c00, 0x0200}, /* WF_LMAC_TOP (WF_SEC) */ 214 {0x820e7000, 0x21e00, 0x0200}, /* WF_LMAC_TOP BN0 (WF_DMA) */ 215 {0x820cf000, 0x22000, 0x1000}, /* WF_LMAC_TOP (WF_PF) */ 216 {0x820e9000, 0x23400, 0x0200}, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 217 {0x820ea000, 0x24000, 0x0200}, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 218 {0x820eb000, 0x24200, 0x0400}, /* WF_LMAC_TOP BN0 (WF_LPON) */ 219 {0x820ec000, 0x24600, 0x0200}, /* WF_LMAC_TOP BN0 (WF_INT) */ 220 {0x820ed000, 0x24800, 0x0800}, /* WF_LMAC_TOP BN0 (WF_MIB) */ 221 {0x820ca000, 0x26000, 0x2000}, /* WF_LMAC_TOP BN0 (WF_MUCOP) */ 222 {0x820d0000, 0x30000, 0x10000}, /* WF_LMAC_TOP (WF_WTBLON) */ 223 {0x00400000, 0x80000, 0x10000}, /* WF_MCU_SYSRAM */ 224 {0x820f0000, 0xa0000, 0x0400}, /* WF_LMAC_TOP BN1 (WF_CFG) */ 225 {0x820f1000, 0xa0600, 0x0200}, /* WF_LMAC_TOP BN1 (WF_TRB) */ 226 {0x820f2000, 0xa0800, 0x0400}, /* WF_LMAC_TOP BN1 (WF_AGG) */ 227 {0x820f3000, 0xa0c00, 0x0400}, /* WF_LMAC_TOP BN1 (WF_ARB) */ 228 {0x820f4000, 0xa1000, 0x0400}, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 229 {0x820f5000, 0xa1400, 0x0800}, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 230 {0x820f7000, 0xa1e00, 0x0200}, /* WF_LMAC_TOP BN1 (WF_DMA) */ 231 {0x820f9000, 0xa3400, 0x0200}, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 232 {0x820fa000, 0xa4000, 0x0200}, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 233 {0x820fb000, 0xa4200, 0x0400}, /* WF_LMAC_TOP BN1 (WF_LPON) */ 234 {0x820fc000, 0xa4600, 0x0200}, /* WF_LMAC_TOP BN1 (WF_INT) */ 235 {0x820fd000, 0xa4800, 0x0800}, /* WF_LMAC_TOP BN1 (WF_MIB) */ 236 {0x820cc000, 0xa5000, 0x2000}, /* WF_LMAC_TOP BN1 (WF_MUCOP) */ 237 {0x820c4000, 0xa8000, 0x4000}, /* WF_LMAC_TOP (WF_UWTBL) */ 238 {0x81030000, 0xae000, 0x100}, /* WFSYS_AON part 1 */ 239 {0x81031000, 0xae100, 0x100}, /* WFSYS_AON part 2 */ 240 {0x81032000, 0xae200, 0x100}, /* WFSYS_AON part 3 */ 241 {0x81033000, 0xae300, 0x100}, /* WFSYS_AON part 4 */ 242 {0x81034000, 0xae400, 0x100}, /* WFSYS_AON part 5 */ 243 {0x80020000, 0xb0000, 0x10000}, /* WF_TOP_MISC_OFF */ 244 {0x81020000, 0xc0000, 0x10000}, /* WF_TOP_MISC_ON */ 245 {0x81040000, 0x120000, 0x1000}, /* WF_MCU_CFG_ON */ 246 {0x81050000, 0x121000, 0x1000}, /* WF_MCU_EINT */ 247 {0x81060000, 0x122000, 0x1000}, /* WF_MCU_GPT */ 248 {0x81070000, 0x123000, 0x1000}, /* WF_MCU_WDT */ 249 {0x80010000, 0x124000, 0x1000}, /* WF_AXIDMA */ 250 {0x7c020000, 0xd0000, 0x10000}, /* CONN_INFRA, wfdma for from CODA flow use */ 251 {0x7c060000, 0xe0000, 0x10000}, /* CONN_INFRA, conn_host_csr_top for from CODA flow use */ 252 {0x20020000, 0xd0000, 0x10000}, /* CONN_INFRA, wfdma */ 253 {0x20060000, 0xe0000, 0x10000}, /* CONN_INFRA, conn_host_csr_top */ 254 {0x7c000000, 0xf0000, 0x10000}, /* CONN_INFRA */ 255 {0x70020000, 0x1f0000, 0x9000}, /* PCIE remapping (AP2CONN) */ 256 {0x0, 0x0, 0x0}, /* imply end of search */ 257}; 258 259static u32 mt7996_reg_map_l1(struct mt7996_dev *dev, u32 addr) 260{ 261 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr); 262 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr); 263 u32 l1_mask, val; 264 265 if (is_mt7996(&dev->mt76)) { 266 l1_mask = MT_HIF_REMAP_L1_MASK_7996; 267 val = FIELD_PREP(MT_HIF_REMAP_L1_MASK_7996, base); 268 } else { 269 l1_mask = MT_HIF_REMAP_L1_MASK; 270 val = FIELD_PREP(MT_HIF_REMAP_L1_MASK, base); 271 } 272 273 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1, l1_mask, val); 274 /* use read to push write */ 275 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1); 276 277 return MT_HIF_REMAP_BASE_L1 + offset; 278} 279 280static u32 mt7996_reg_map_l2(struct mt7996_dev *dev, u32 addr) 281{ 282 u32 offset, base, l2_mask, val; 283 284 if (is_mt7990(&dev->mt76)) { 285 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET_7990, addr); 286 base = FIELD_GET(MT_HIF_REMAP_L2_BASE_7990, addr); 287 l2_mask = MT_HIF_REMAP_L2_MASK_7990; 288 val = FIELD_PREP(MT_HIF_REMAP_L2_MASK_7990, base); 289 } else { 290 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr); 291 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr); 292 l2_mask = MT_HIF_REMAP_L2_MASK; 293 val = FIELD_PREP(MT_HIF_REMAP_L2_MASK, base); 294 } 295 296 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2, l2_mask, val); 297 /* use read to push write */ 298 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2); 299 300 return MT_HIF_REMAP_BASE_L2 + offset; 301} 302 303static u32 mt7996_reg_map_cbtop(struct mt7996_dev *dev, u32 addr) 304{ 305 u32 offset = FIELD_GET(MT_HIF_REMAP_CBTOP_OFFSET, addr); 306 u32 base = FIELD_GET(MT_HIF_REMAP_CBTOP_BASE, addr); 307 308 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_CBTOP, 309 MT_HIF_REMAP_CBTOP_MASK, 310 FIELD_PREP(MT_HIF_REMAP_CBTOP_MASK, base)); 311 /* use read to push write */ 312 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_CBTOP); 313 314 return MT_HIF_REMAP_BASE_CBTOP + offset; 315} 316 317static u32 __mt7996_reg_addr(struct mt7996_dev *dev, u32 addr) 318{ 319 int i; 320 321 if (addr < 0x100000) 322 return addr; 323 324 for (i = 0; i < dev->reg.map_size; i++) { 325 u32 ofs; 326 327 if (addr < dev->reg.map[i].phys) 328 continue; 329 330 ofs = addr - dev->reg.map[i].phys; 331 if (ofs >= dev->reg.map[i].size) 332 continue; 333 334 return dev->reg.map[i].mapped + ofs; 335 } 336 337 return 0; 338} 339 340static u32 __mt7996_reg_remap_addr(struct mt7996_dev *dev, u32 addr) 341{ 342 if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) || 343 (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) || 344 (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END)) 345 return mt7996_reg_map_l1(dev, addr); 346 347 /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */ 348 if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) { 349 addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE; 350 return mt7996_reg_map_l1(dev, addr); 351 } 352 353 if (dev_is_pci(dev->mt76.dev) && 354 ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) || 355 addr >= MT_CBTOP2_PHY_START)) { 356 if (is_mt7990(&dev->mt76)) 357 return mt7996_reg_map_cbtop(dev, addr); 358 return mt7996_reg_map_l1(dev, addr); 359 } 360 361 return mt7996_reg_map_l2(dev, addr); 362} 363 364void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset, 365 size_t len) 366{ 367 u32 addr = __mt7996_reg_addr(dev, offset); 368 369 if (addr) { 370 memcpy_fromio(buf, dev->mt76.mmio.regs + addr, len); 371 return; 372 } 373 374 spin_lock_bh(&dev->reg_lock); 375 memcpy_fromio(buf, dev->mt76.mmio.regs + 376 __mt7996_reg_remap_addr(dev, offset), len); 377 spin_unlock_bh(&dev->reg_lock); 378} 379 380static u32 mt7996_rr(struct mt76_dev *mdev, u32 offset) 381{ 382 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 383 u32 addr = __mt7996_reg_addr(dev, offset), val; 384 385 if (addr) 386 return dev->bus_ops->rr(mdev, addr); 387 388 spin_lock_bh(&dev->reg_lock); 389 val = dev->bus_ops->rr(mdev, __mt7996_reg_remap_addr(dev, offset)); 390 spin_unlock_bh(&dev->reg_lock); 391 392 return val; 393} 394 395static void mt7996_wr(struct mt76_dev *mdev, u32 offset, u32 val) 396{ 397 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 398 u32 addr = __mt7996_reg_addr(dev, offset); 399 400 if (addr) { 401 dev->bus_ops->wr(mdev, addr, val); 402 return; 403 } 404 405 spin_lock_bh(&dev->reg_lock); 406 dev->bus_ops->wr(mdev, __mt7996_reg_remap_addr(dev, offset), val); 407 spin_unlock_bh(&dev->reg_lock); 408} 409 410static u32 mt7996_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 411{ 412 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 413 u32 addr = __mt7996_reg_addr(dev, offset); 414 415 if (addr) 416 return dev->bus_ops->rmw(mdev, addr, mask, val); 417 418 spin_lock_bh(&dev->reg_lock); 419 val = dev->bus_ops->rmw(mdev, __mt7996_reg_remap_addr(dev, offset), mask, val); 420 spin_unlock_bh(&dev->reg_lock); 421 422 return val; 423} 424 425#ifdef CONFIG_NET_MEDIATEK_SOC_WED 426static int mt7996_mmio_wed_reset(struct mtk_wed_device *wed) 427{ 428 struct mt76_dev *mdev = container_of(wed, struct mt76_dev, mmio.wed); 429 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 430 struct mt76_phy *mphy = &dev->mphy; 431 int ret; 432 433 ASSERT_RTNL(); 434 435 if (test_and_set_bit(MT76_STATE_WED_RESET, &mphy->state)) 436 return -EBUSY; 437 438 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_TRIGGER, UNI_CMD_SER_SET_RECOVER_FROM_ETH, 439 mphy->band_idx); 440 if (ret) 441 goto out; 442 443 rtnl_unlock(); 444 if (!wait_for_completion_timeout(&mdev->mmio.wed_reset, 20 * HZ)) { 445 dev_err(mdev->dev, "wed reset timeout\n"); 446 ret = -ETIMEDOUT; 447 } 448 rtnl_lock(); 449out: 450 clear_bit(MT76_STATE_WED_RESET, &mphy->state); 451 452 return ret; 453} 454#endif 455 456int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr, 457 bool hif2, int *irq) 458{ 459#ifdef CONFIG_NET_MEDIATEK_SOC_WED 460 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 461 struct pci_dev *pci_dev = pdev_ptr; 462 u32 hif1_ofs; 463 464 if (!wed_enable) 465 return 0; 466 467 dev->mt76.hwrro_mode = is_mt7996(&dev->mt76) ? MT76_HWRRO_V3 468 : MT76_HWRRO_V3_1; 469 470 hif1_ofs = dev->hif2 ? MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0) : 0; 471 472 if (hif2) 473 wed = &dev->mt76.mmio.wed_hif2; 474 475 wed->wlan.pci_dev = pci_dev; 476 wed->wlan.bus_type = MTK_WED_BUS_PCIE; 477 478 wed->wlan.base = devm_ioremap(dev->mt76.dev, 479 pci_resource_start(pci_dev, 0), 480 pci_resource_len(pci_dev, 0)); 481 if (!wed->wlan.base) 482 return -ENOMEM; 483 484 wed->wlan.phy_base = pci_resource_start(pci_dev, 0); 485 486 if (hif2) { 487 wed->wlan.wpdma_int = wed->wlan.phy_base + 488 MT_INT_PCIE1_SOURCE_CSR_EXT; 489 wed->wlan.wpdma_mask = wed->wlan.phy_base + 490 MT_INT_PCIE1_MASK_CSR; 491 wed->wlan.wpdma_tx = wed->wlan.phy_base + hif1_ofs + 492 MT_TXQ_RING_BASE(0) + 493 MT7996_TXQ_BAND2 * MT_RING_SIZE; 494 if (mt7996_has_hwrro(dev)) { 495 if (is_mt7996(&dev->mt76)) { 496 wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_EXT) - 1; 497 wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs + 498 MT_RXQ_RING_BASE(0) + 499 MT7996_RXQ_TXFREE2 * MT_RING_SIZE; 500 } else { 501 wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_BAND1_EXT) - 1; 502 wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs + 503 MT_RXQ_RING_BASE(0) + 504 MT7996_RXQ_MCU_WA_EXT * MT_RING_SIZE; 505 } 506 } else { 507 wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs + 508 MT_RXQ_RING_BASE(0) + 509 MT7996_RXQ_MCU_WA_TRI * MT_RING_SIZE; 510 wed->wlan.txfree_tbit = ffs(MT_INT_RX_DONE_WA_TRI) - 1; 511 } 512 513 wed->wlan.wpdma_rx_glo = wed->wlan.phy_base + hif1_ofs + MT_WFDMA0_GLO_CFG; 514 wed->wlan.wpdma_rx[0] = wed->wlan.phy_base + hif1_ofs + 515 MT_RXQ_RING_BASE(MT7996_RXQ_BAND2) + 516 MT7996_RXQ_BAND2 * MT_RING_SIZE; 517 518 wed->wlan.id = MT7996_DEVICE_ID_2; 519 wed->wlan.tx_tbit[0] = ffs(MT_INT_TX_DONE_BAND2) - 1; 520 } else { 521 wed->wlan.hw_rro = mt7996_has_hwrro(dev); 522 wed->wlan.wpdma_int = wed->wlan.phy_base + MT_INT_SOURCE_CSR; 523 wed->wlan.wpdma_mask = wed->wlan.phy_base + MT_INT_MASK_CSR; 524 wed->wlan.wpdma_tx = wed->wlan.phy_base + MT_TXQ_RING_BASE(0) + 525 MT7996_TXQ_BAND0 * MT_RING_SIZE; 526 527 wed->wlan.wpdma_rx_glo = wed->wlan.phy_base + MT_WFDMA0_GLO_CFG; 528 529 wed->wlan.wpdma_rx[0] = wed->wlan.phy_base + 530 MT_RXQ_RING_BASE(MT7996_RXQ_BAND0) + 531 MT7996_RXQ_BAND0 * MT_RING_SIZE; 532 533 wed->wlan.wpdma_rx_rro[0] = wed->wlan.phy_base + 534 MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND0) + 535 MT7996_RXQ_RRO_BAND0 * MT_RING_SIZE; 536 if (is_mt7996(&dev->mt76)) { 537 wed->wlan.wpdma_rx_rro[1] = wed->wlan.phy_base + hif1_ofs + 538 MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND2) + 539 MT7996_RXQ_RRO_BAND2 * MT_RING_SIZE; 540 } else { 541 wed->wlan.wpdma_rx_rro[1] = wed->wlan.phy_base + hif1_ofs + 542 MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND1) + 543 MT7996_RXQ_RRO_BAND1 * MT_RING_SIZE; 544 wed->wlan.wpdma_rx[1] = wed->wlan.phy_base + hif1_ofs + 545 MT_RXQ_RING_BASE(MT7996_RXQ_BAND1) + 546 MT7996_RXQ_BAND1 * MT_RING_SIZE; 547 } 548 549 wed->wlan.wpdma_rx_pg = wed->wlan.phy_base + 550 MT_RXQ_RING_BASE(MT7996_RXQ_MSDU_PG_BAND0) + 551 MT7996_RXQ_MSDU_PG_BAND0 * MT_RING_SIZE; 552 553 wed->wlan.rx_nbuf = 65536; 554 wed->wlan.rx_npkt = dev->hif2 ? 32768 : 24576; 555 wed->wlan.rx_size = SKB_WITH_OVERHEAD(MT_RX_BUF_SIZE); 556 557 wed->wlan.rx_tbit[0] = ffs(MT_INT_RX_DONE_BAND0) - 1; 558 wed->wlan.rro_rx_tbit[0] = ffs(MT_INT_RX_DONE_RRO_BAND0) - 1; 559 if (is_mt7996(&dev->mt76)) { 560 wed->wlan.rx_tbit[1] = ffs(MT_INT_RX_DONE_BAND2) - 1; 561 wed->wlan.rro_rx_tbit[1] = ffs(MT_INT_RX_DONE_RRO_BAND2) - 1; 562 } else { 563 wed->wlan.rx_tbit[1] = ffs(MT_INT_RX_DONE_BAND1) - 1; 564 wed->wlan.rro_rx_tbit[1] = ffs(MT_INT_RX_DONE_RRO_BAND1) - 1; 565 } 566 567 wed->wlan.rx_pg_tbit[0] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND0) - 1; 568 wed->wlan.rx_pg_tbit[1] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND1) - 1; 569 wed->wlan.rx_pg_tbit[2] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND2) - 1; 570 571 wed->wlan.tx_tbit[0] = ffs(MT_INT_TX_DONE_BAND0) - 1; 572 wed->wlan.tx_tbit[1] = ffs(MT_INT_TX_DONE_BAND1) - 1; 573 if (is_mt7996(&dev->mt76)) { 574 if (mt7996_has_hwrro(dev)) { 575 wed->wlan.wpdma_txfree = wed->wlan.phy_base + 576 MT_RXQ_RING_BASE(0) + 577 MT7996_RXQ_TXFREE0 * MT_RING_SIZE; 578 wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_MAIN) - 1; 579 } else { 580 wed->wlan.wpdma_txfree = wed->wlan.phy_base + 581 MT_RXQ_RING_BASE(0) + 582 MT7996_RXQ_MCU_WA_MAIN * MT_RING_SIZE; 583 wed->wlan.txfree_tbit = ffs(MT_INT_RX_DONE_WA_MAIN) - 1; 584 } 585 } else { 586 wed->wlan.txfree_tbit = ffs(MT_INT_RX_DONE_WA_MAIN) - 1; 587 wed->wlan.wpdma_txfree = wed->wlan.phy_base + MT_RXQ_RING_BASE(0) + 588 MT7996_RXQ_MCU_WA_MAIN * MT_RING_SIZE; 589 } 590 dev->mt76.rx_token_size = MT7996_TOKEN_SIZE + wed->wlan.rx_npkt; 591 592 if (dev->hif2 && is_mt7992(&dev->mt76)) 593 wed->wlan.id = 0x7992; 594 } 595 596 wed->wlan.nbuf = MT7996_HW_TOKEN_SIZE; 597 wed->wlan.token_start = MT7996_TOKEN_SIZE - wed->wlan.nbuf; 598 wed->wlan.hif2 = hif2; 599 600 wed->wlan.amsdu_max_subframes = 8; 601 wed->wlan.amsdu_max_len = 1536; 602 603 wed->wlan.init_buf = mt7996_wed_init_buf; 604 wed->wlan.init_rx_buf = mt76_wed_init_rx_buf; 605 wed->wlan.release_rx_buf = mt76_wed_release_rx_buf; 606 wed->wlan.offload_enable = mt76_wed_offload_enable; 607 wed->wlan.offload_disable = mt76_wed_offload_disable; 608 if (!hif2) { 609 wed->wlan.reset = mt7996_mmio_wed_reset; 610 wed->wlan.reset_complete = mt76_wed_reset_complete; 611 } 612 613 if (mtk_wed_device_attach(wed)) { 614 dev->mt76.hwrro_mode = MT76_HWRRO_OFF; 615 return 0; 616 } 617 618 *irq = wed->irq; 619 dev->mt76.dma_dev = wed->dev; 620 621 return 1; 622#else 623 return 0; 624#endif 625} 626 627static int mt7996_mmio_init(struct mt76_dev *mdev, 628 void __iomem *mem_base, 629 u32 device_id) 630{ 631 struct mt76_bus_ops *bus_ops; 632 struct mt7996_dev *dev; 633 634 dev = container_of(mdev, struct mt7996_dev, mt76); 635 mt76_mmio_init(&dev->mt76, mem_base); 636 spin_lock_init(&dev->reg_lock); 637 638 switch (device_id) { 639 case MT7996_DEVICE_ID: 640 dev->reg.base = mt7996_reg_base; 641 dev->reg.offs_rev = mt7996_offs; 642 dev->reg.map = mt7996_reg_map; 643 dev->reg.map_size = ARRAY_SIZE(mt7996_reg_map); 644 break; 645 case MT7992_DEVICE_ID: 646 dev->reg.base = mt7996_reg_base; 647 dev->reg.offs_rev = mt7992_offs; 648 dev->reg.map = mt7996_reg_map; 649 dev->reg.map_size = ARRAY_SIZE(mt7996_reg_map); 650 break; 651 case MT7990_DEVICE_ID: 652 dev->reg.base = mt7996_reg_base; 653 dev->reg.offs_rev = mt7990_offs; 654 dev->reg.map = mt7990_reg_map; 655 dev->reg.map_size = ARRAY_SIZE(mt7990_reg_map); 656 break; 657 default: 658 return -EINVAL; 659 } 660 661 dev->bus_ops = dev->mt76.bus; 662 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 663 GFP_KERNEL); 664 if (!bus_ops) 665 return -ENOMEM; 666 667 bus_ops->rr = mt7996_rr; 668 bus_ops->wr = mt7996_wr; 669 bus_ops->rmw = mt7996_rmw; 670 dev->mt76.bus = bus_ops; 671 672 mdev->rev = (device_id << 16) | (mt76_rr(dev, MT_HW_REV) & 0xff); 673 674 dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 675 676 return 0; 677} 678 679void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg, 680 u32 clear, u32 set) 681{ 682 struct mt76_dev *mdev = &dev->mt76; 683 unsigned long flags; 684 685 spin_lock_irqsave(&mdev->mmio.irq_lock, flags); 686 687 mdev->mmio.irqmask &= ~clear; 688 mdev->mmio.irqmask |= set; 689 690 if (write_reg) { 691 if (mtk_wed_device_active(&mdev->mmio.wed)) { 692 mtk_wed_device_irq_set_mask(&mdev->mmio.wed, 693 mdev->mmio.irqmask); 694 if (mtk_wed_device_active(&mdev->mmio.wed_hif2)) { 695 mtk_wed_device_irq_set_mask(&mdev->mmio.wed_hif2, 696 mdev->mmio.irqmask); 697 } 698 } else { 699 mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask); 700 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask); 701 } 702 } 703 704 spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags); 705} 706 707static void mt7996_rx_poll_complete(struct mt76_dev *mdev, 708 enum mt76_rxq_id q) 709{ 710 if (q == MT_RXQ_NPU0 || q == MT_RXQ_NPU1) { 711 struct airoha_npu *npu; 712 713 npu = rcu_dereference(mdev->mmio.npu); 714 if (npu) 715 airoha_npu_wlan_enable_irq(npu, q - MT_RXQ_NPU0); 716 } else { 717 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, 718 mt76); 719 720 mt7996_irq_enable(dev, MT_INT_RX(q)); 721 } 722} 723 724/* TODO: support 2/4/6/8 MSI-X vectors */ 725static void mt7996_irq_tasklet(struct tasklet_struct *t) 726{ 727 struct mt7996_dev *dev = from_tasklet(dev, t, mt76.irq_tasklet); 728 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 729 struct mtk_wed_device *wed_hif2 = &dev->mt76.mmio.wed_hif2; 730 u32 i, intr, mask, intr1 = 0; 731 732 if (dev->hif2 && mtk_wed_device_active(wed_hif2)) { 733 mtk_wed_device_irq_set_mask(wed_hif2, 0); 734 intr1 = mtk_wed_device_irq_get(wed_hif2, 735 dev->mt76.mmio.irqmask); 736 if (intr1 & MT_INT_RX_TXFREE_EXT) 737 napi_schedule(&dev->mt76.napi[MT_RXQ_TXFREE_BAND2]); 738 739 if (intr1 & MT_INT_RX_DONE_BAND2_EXT) 740 napi_schedule(&dev->mt76.napi[MT_RXQ_BAND2]); 741 742 if (intr1 & MT_INT_RX_TXFREE_BAND1_EXT) 743 napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1_WA]); 744 } 745 746 if (mtk_wed_device_active(wed)) { 747 mtk_wed_device_irq_set_mask(wed, 0); 748 intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask); 749 intr |= (intr1 & ~MT_INT_TX_RX_DONE_EXT); 750 } else { 751 mt76_wr(dev, MT_INT_MASK_CSR, 0); 752 if (dev->hif2) 753 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 754 755 intr = mt76_rr(dev, MT_INT_SOURCE_CSR); 756 intr &= dev->mt76.mmio.irqmask; 757 mt76_wr(dev, MT_INT_SOURCE_CSR, intr); 758 if (dev->hif2) { 759 intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR); 760 intr1 &= dev->mt76.mmio.irqmask; 761 mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1); 762 intr |= intr1; 763 } 764 } 765 766 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); 767 768 mask = intr & MT_INT_RX_DONE_ALL; 769 if (intr & MT_INT_TX_DONE_MCU) 770 mask |= MT_INT_TX_DONE_MCU; 771 mt7996_irq_disable(dev, mask); 772 773 if (intr & MT_INT_TX_DONE_MCU) 774 napi_schedule(&dev->mt76.tx_napi); 775 776 for (i = 0; i < __MT_RXQ_MAX; i++) { 777 if ((intr & MT_INT_RX(i))) 778 napi_schedule(&dev->mt76.napi[i]); 779 } 780 781 if (intr & MT_INT_MCU_CMD) { 782 u32 val = mt76_rr(dev, MT_MCU_CMD); 783 784 mt76_wr(dev, MT_MCU_CMD, val); 785 if (val & (MT_MCU_CMD_ERROR_MASK | MT_MCU_CMD_WDT_MASK)) { 786 dev->recovery.state = val; 787 mt7996_reset(dev); 788 } 789 } 790} 791 792irqreturn_t mt7996_irq_handler(int irq, void *dev_instance) 793{ 794 struct mt7996_dev *dev = dev_instance; 795 796 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 797 mtk_wed_device_irq_set_mask(&dev->mt76.mmio.wed, 0); 798 else 799 mt76_wr(dev, MT_INT_MASK_CSR, 0); 800 801 if (dev->hif2) { 802 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2)) 803 mtk_wed_device_irq_set_mask(&dev->mt76.mmio.wed_hif2, 0); 804 else 805 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 806 } 807 808 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) 809 return IRQ_NONE; 810 811 tasklet_schedule(&dev->mt76.irq_tasklet); 812 813 return IRQ_HANDLED; 814} 815 816struct mt7996_dev *mt7996_mmio_probe(struct device *pdev, 817 void __iomem *mem_base, u32 device_id) 818{ 819 static const struct mt76_driver_ops drv_ops = { 820 /* txwi_size = txd size + txp size */ 821 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_fw_txp), 822 .link_data_size = sizeof(struct mt7996_vif_link), 823 .drv_flags = MT_DRV_TXWI_NO_FREE | 824 MT_DRV_AMSDU_OFFLOAD | 825 MT_DRV_HW_MGMT_TXQ, 826 .survey_flags = SURVEY_INFO_TIME_TX | 827 SURVEY_INFO_TIME_RX | 828 SURVEY_INFO_TIME_BSS_RX, 829 .token_size = MT7996_TOKEN_SIZE, 830 .tx_prepare_skb = mt7996_tx_prepare_skb, 831 .tx_complete_skb = mt76_connac_tx_complete_skb, 832 .rx_skb = mt7996_queue_rx_skb, 833 .rx_check = mt7996_rx_check, 834 .rx_poll_complete = mt7996_rx_poll_complete, 835 .rx_rro_ind_process = mt7996_rro_rx_process, 836 .rx_rro_add_msdu_page = mt7996_rro_msdu_page_add, 837 .update_survey = mt7996_update_channel, 838 .set_channel = mt7996_set_channel, 839 .vif_link_add = mt7996_vif_link_add, 840 .vif_link_remove = mt7996_vif_link_remove, 841 }; 842 struct mt7996_dev *dev; 843 struct mt76_dev *mdev; 844 int ret; 845 846 mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7996_ops, &drv_ops); 847 if (!mdev) 848 return ERR_PTR(-ENOMEM); 849 850 dev = container_of(mdev, struct mt7996_dev, mt76); 851 852 ret = mt7996_mmio_init(mdev, mem_base, device_id); 853 if (ret) 854 goto error; 855 856 tasklet_setup(&mdev->irq_tasklet, mt7996_irq_tasklet); 857 858 mt76_wr(dev, MT_INT_MASK_CSR, 0); 859 860 return dev; 861 862error: 863 mt76_free_device(&dev->mt76); 864 865 return ERR_PTR(ret); 866} 867 868static int __init mt7996_init(void) 869{ 870 int ret; 871 872 ret = pci_register_driver(&mt7996_hif_driver); 873 if (ret) 874 return ret; 875 876 ret = pci_register_driver(&mt7996_pci_driver); 877 if (ret) 878 pci_unregister_driver(&mt7996_hif_driver); 879 880 return ret; 881} 882 883static void __exit mt7996_exit(void) 884{ 885 pci_unregister_driver(&mt7996_pci_driver); 886 pci_unregister_driver(&mt7996_hif_driver); 887} 888 889module_init(mt7996_init); 890module_exit(mt7996_exit); 891MODULE_DESCRIPTION("MediaTek MT7996 MMIO helpers"); 892MODULE_LICENSE("Dual BSD/GPL");
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