regs.h

 1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
 2/* Copyright (C) 2023 MediaTek Inc. */
 3
 4#ifndef __MT7925_REGS_H
 5#define __MT7925_REGS_H
 6
 7#include "../mt792x_regs.h"
 8
 9#define MT_MDP_BASE			0x820cc800
10#define MT_MDP(ofs)			(MT_MDP_BASE + (ofs))
11
12#define MT_MDP_DCR0			MT_MDP(0x000)
13#define MT_MDP_DCR0_DAMSDU_EN		BIT(15)
14#define MT_MDP_DCR0_RX_HDR_TRANS_EN	BIT(19)
15
16#define MT_MDP_DCR1			MT_MDP(0x004)
17#define MT_MDP_DCR1_MAX_RX_LEN		GENMASK(15, 3)
18
19#define MT_MDP_BNRCFR0(_band)		MT_MDP(0x090 + ((_band) << 8))
20#define MT_MDP_RCFR0_MCU_RX_MGMT	GENMASK(5, 4)
21#define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR	GENMASK(7, 6)
22#define MT_MDP_RCFR0_MCU_RX_CTL_BAR	GENMASK(9, 8)
23
24#define MT_MDP_BNRCFR1(_band)		MT_MDP(0x094 + ((_band) << 8))
25#define MT_MDP_RCFR1_MCU_RX_BYPASS	GENMASK(23, 22)
26#define MT_MDP_RCFR1_RX_DROPPED_UCAST	GENMASK(28, 27)
27#define MT_MDP_RCFR1_RX_DROPPED_MCAST	GENMASK(30, 29)
28#define MT_MDP_TO_HIF			0
29#define MT_MDP_TO_WM			1
30
31#define MT_WFDMA0_HOST_INT_ENA		MT_WFDMA0(0x204)
32#define MT_WFDMA0_HOST_INT_DIS		MT_WFDMA0(0x22c)
33#define HOST_RX_DONE_INT_ENA4		BIT(12)
34#define HOST_RX_DONE_INT_ENA5		BIT(13)
35#define HOST_RX_DONE_INT_ENA6		BIT(14)
36#define HOST_RX_DONE_INT_ENA7		BIT(15)
37#define HOST_RX_DONE_INT_ENA8		BIT(16)
38#define HOST_RX_DONE_INT_ENA9		BIT(17)
39#define HOST_RX_DONE_INT_ENA10		BIT(18)
40#define HOST_RX_DONE_INT_ENA11		BIT(19)
41#define HOST_TX_DONE_INT_ENA15		BIT(25)
42#define HOST_TX_DONE_INT_ENA16		BIT(26)
43#define HOST_TX_DONE_INT_ENA17		BIT(27)
44
45/* WFDMA interrupt */
46#define MT_INT_RX_DONE_DATA		HOST_RX_DONE_INT_ENA2
47#define MT_INT_RX_DONE_WM		HOST_RX_DONE_INT_ENA0
48#define MT_INT_RX_DONE_WM2		HOST_RX_DONE_INT_ENA1
49#define MT_INT_RX_DONE_ALL		(MT_INT_RX_DONE_DATA | \
50					 MT_INT_RX_DONE_WM | \
51					 MT_INT_RX_DONE_WM2)
52
53#define MT_INT_TX_DONE_MCU_WM		(HOST_TX_DONE_INT_ENA15 | \
54					 HOST_TX_DONE_INT_ENA17)
55
56#define MT_INT_TX_DONE_FWDL		HOST_TX_DONE_INT_ENA16
57#define MT_INT_TX_DONE_BAND0		HOST_TX_DONE_INT_ENA0
58
59#define MT_INT_TX_DONE_MCU		(MT_INT_TX_DONE_MCU_WM |	\
60					 MT_INT_TX_DONE_FWDL)
61#define MT_INT_TX_DONE_ALL		(MT_INT_TX_DONE_MCU |	\
62					 MT_INT_TX_DONE_BAND0 |	\
63					GENMASK(18, 4))
64
65#define MT_RX_DATA_RING_BASE		MT_WFDMA0(0x500)
66
67#define MT_INFRA_CFG_BASE		0xd1000
68#define MT_INFRA(ofs)			(MT_INFRA_CFG_BASE + (ofs))
69
70#define MT_HIF_REMAP_L1			0x155024
71#define MT_HIF_REMAP_L1_MASK		GENMASK(31, 16)
72#define MT_HIF_REMAP_L1_OFFSET		GENMASK(15, 0)
73#define MT_HIF_REMAP_L1_BASE		GENMASK(31, 16)
74#define MT_HIF_REMAP_BASE_L1		0x130000
75
76#define MT_HIF_REMAP_L2			0x0120
77#if IS_ENABLED(CONFIG_MT76_DEV)
78#define MT_HIF_REMAP_BASE_L2		(0x7c500000 - (0x7c000000 - 0x18000000))
79#else
80#define MT_HIF_REMAP_BASE_L2		0x18500000
81#endif
82
83#define MT_WFSYS_SW_RST_B		0x7c000140
84
85#define MT_WTBLON_TOP_WDUCR		MT_WTBLON_TOP(0x370)
86#define MT_WTBLON_TOP_WDUCR_GROUP	GENMASK(4, 0)
87
88#define MT_WTBL_UPDATE			MT_WTBLON_TOP(0x380)
89#define MT_WTBL_UPDATE_WLAN_IDX		GENMASK(11, 0)
90#define MT_WTBL_UPDATE_ADM_COUNT_CLEAR	BIT(14)
91
92#endif