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linux-6.19.14/drivers/net/wireless/mediatek/mt76/mt7915/regs.h C 
   1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
   2/* Copyright (C) 2020 MediaTek Inc. */
   3
   4#ifndef __MT7915_REGS_H
   5#define __MT7915_REGS_H
   6
   7/* used to differentiate between generations */
   8struct mt7915_reg_desc {
   9	const u32 *reg_rev;
  10	const u32 *offs_rev;
  11	const struct mt76_connac_reg_map *map;
  12	u32 map_size;
  13};
  14
  15enum reg_rev {
  16	INT_SOURCE_CSR,
  17	INT_MASK_CSR,
  18	INT1_SOURCE_CSR,
  19	INT1_MASK_CSR,
  20	INT_MCU_CMD_SOURCE,
  21	INT_MCU_CMD_EVENT,
  22	WFDMA0_ADDR,
  23	WFDMA0_PCIE1_ADDR,
  24	WFDMA_EXT_CSR_ADDR,
  25	CBTOP1_PHY_END,
  26	INFRA_MCU_ADDR_END,
  27	FW_ASSERT_STAT_ADDR,
  28	FW_EXCEPT_TYPE_ADDR,
  29	FW_EXCEPT_COUNT_ADDR,
  30	FW_CIRQ_COUNT_ADDR,
  31	FW_CIRQ_IDX_ADDR,
  32	FW_CIRQ_LISR_ADDR,
  33	FW_TASK_ID_ADDR,
  34	FW_TASK_IDX_ADDR,
  35	FW_TASK_QID1_ADDR,
  36	FW_TASK_QID2_ADDR,
  37	FW_TASK_START_ADDR,
  38	FW_TASK_END_ADDR,
  39	FW_TASK_SIZE_ADDR,
  40	FW_LAST_MSG_ID_ADDR,
  41	FW_EINT_INFO_ADDR,
  42	FW_SCHED_INFO_ADDR,
  43	SWDEF_BASE_ADDR,
  44	TXQ_WED_RING_BASE,
  45	RXQ_WED_RING_BASE,
  46	RXQ_WED_DATA_RING_BASE,
  47	__MT_REG_MAX,
  48};
  49
  50enum offs_rev {
  51	TMAC_CDTR,
  52	TMAC_ODTR,
  53	TMAC_ATCR,
  54	TMAC_TRCR0,
  55	TMAC_ICR0,
  56	TMAC_ICR1,
  57	TMAC_CTCR0,
  58	TMAC_TFCR0,
  59	MDP_BNRCFR0,
  60	MDP_BNRCFR1,
  61	ARB_DRNGR0,
  62	ARB_SCR,
  63	RMAC_MIB_AIRTIME14,
  64	AGG_AWSCR0,
  65	AGG_PCR0,
  66	AGG_ACR0,
  67	AGG_ACR4,
  68	AGG_MRCR,
  69	AGG_ATCR0,
  70	AGG_ATCR1,
  71	AGG_ATCR3,
  72	LPON_UTTR0,
  73	LPON_UTTR1,
  74	LPON_FRCR,
  75	MIB_SDR3,
  76	MIB_SDR4,
  77	MIB_SDR5,
  78	MIB_SDR7,
  79	MIB_SDR8,
  80	MIB_SDR9,
  81	MIB_SDR10,
  82	MIB_SDR11,
  83	MIB_SDR12,
  84	MIB_SDR13,
  85	MIB_SDR14,
  86	MIB_SDR15,
  87	MIB_SDR16,
  88	MIB_SDR17,
  89	MIB_SDR18,
  90	MIB_SDR19,
  91	MIB_SDR20,
  92	MIB_SDR21,
  93	MIB_SDR22,
  94	MIB_SDR23,
  95	MIB_SDR24,
  96	MIB_SDR25,
  97	MIB_SDR27,
  98	MIB_SDR28,
  99	MIB_SDR29,
 100	MIB_SDRVEC,
 101	MIB_SDR31,
 102	MIB_SDR32,
 103	MIB_SDRMUBF,
 104	MIB_DR8,
 105	MIB_DR9,
 106	MIB_DR11,
 107	MIB_MB_SDR0,
 108	MIB_MB_SDR1,
 109	TX_AGG_CNT,
 110	TX_AGG_CNT2,
 111	MIB_ARNG,
 112	WTBLON_TOP_WDUCR,
 113	WTBL_UPDATE,
 114	PLE_FL_Q_EMPTY,
 115	PLE_FL_Q_CTRL,
 116	PLE_AC_QEMPTY,
 117	PLE_FREEPG_CNT,
 118	PLE_FREEPG_HEAD_TAIL,
 119	PLE_PG_HIF_GROUP,
 120	PLE_HIF_PG_INFO,
 121	AC_OFFSET,
 122	ETBF_PAR_RPT0,
 123	__MT_OFFS_MAX,
 124};
 125
 126#define __REG(id)			(dev->reg.reg_rev[(id)])
 127#define __OFFS(id)			(dev->reg.offs_rev[(id)])
 128
 129/* MCU WFDMA0 */
 130#define MT_MCU_WFDMA0_BASE		0x2000
 131#define MT_MCU_WFDMA0(ofs)		(MT_MCU_WFDMA0_BASE + (ofs))
 132
 133#define MT_MCU_WFDMA0_DUMMY_CR		MT_MCU_WFDMA0(0x120)
 134
 135/* MCU WFDMA1 */
 136#define MT_MCU_WFDMA1_BASE		0x3000
 137#define MT_MCU_WFDMA1(ofs)		(MT_MCU_WFDMA1_BASE + (ofs))
 138
 139#define MT_MCU_INT_EVENT		__REG(INT_MCU_CMD_EVENT)
 140#define MT_MCU_INT_EVENT_DMA_STOPPED	BIT(0)
 141#define MT_MCU_INT_EVENT_DMA_INIT	BIT(1)
 142#define MT_MCU_INT_EVENT_SER_TRIGGER	BIT(2)
 143#define MT_MCU_INT_EVENT_RESET_DONE	BIT(3)
 144
 145/* PLE */
 146#define MT_PLE_BASE			0x820c0000
 147#define MT_PLE(ofs)			(MT_PLE_BASE + (ofs))
 148
 149#define MT_PLE_HOST_RPT0		MT_PLE(0x030)
 150#define MT_PLE_HOST_RPT0_TX_LATENCY	BIT(3)
 151
 152#define MT_FL_Q_EMPTY			MT_PLE(__OFFS(PLE_FL_Q_EMPTY))
 153#define MT_FL_Q0_CTRL			MT_PLE(__OFFS(PLE_FL_Q_CTRL))
 154#define MT_FL_Q2_CTRL			MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0x8)
 155#define MT_FL_Q3_CTRL			MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0xc)
 156
 157#define MT_PLE_FREEPG_CNT		MT_PLE(__OFFS(PLE_FREEPG_CNT))
 158#define MT_PLE_FREEPG_HEAD_TAIL		MT_PLE(__OFFS(PLE_FREEPG_HEAD_TAIL))
 159#define MT_PLE_PG_HIF_GROUP		MT_PLE(__OFFS(PLE_PG_HIF_GROUP))
 160#define MT_PLE_HIF_PG_INFO		MT_PLE(__OFFS(PLE_HIF_PG_INFO))
 161
 162#define MT_PLE_AC_QEMPTY(ac, n)		MT_PLE(__OFFS(PLE_AC_QEMPTY) +	\
 163					       __OFFS(AC_OFFSET) *	\
 164					       (ac) + ((n) << 2))
 165#define MT_PLE_AMSDU_PACK_MSDU_CNT(n)	MT_PLE(0x10e0 + ((n) << 2))
 166
 167#define MT_PSE_BASE			0x820c8000
 168#define MT_PSE(ofs)			(MT_PSE_BASE + (ofs))
 169
 170/* WF MDP TOP */
 171#define MT_MDP_BASE			0x820cd000
 172#define MT_MDP(ofs)			(MT_MDP_BASE + (ofs))
 173
 174#define MT_MDP_DCR0			MT_MDP(0x000)
 175#define MT_MDP_DCR0_DAMSDU_EN		BIT(15)
 176#define MT_MDP_DCR0_RX_HDR_TRANS_EN	BIT(19)
 177
 178#define MT_MDP_DCR1			MT_MDP(0x004)
 179#define MT_MDP_DCR1_MAX_RX_LEN		GENMASK(15, 3)
 180
 181#define MT_MDP_DCR2			MT_MDP(0x0e8)
 182#define MT_MDP_DCR2_RX_TRANS_SHORT	BIT(2)
 183
 184#define MT_MDP_BNRCFR0(_band)		MT_MDP(__OFFS(MDP_BNRCFR0) + \
 185					       ((_band) << 8))
 186#define MT_MDP_RCFR0_MCU_RX_MGMT	GENMASK(5, 4)
 187#define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR	GENMASK(7, 6)
 188#define MT_MDP_RCFR0_MCU_RX_CTL_BAR	GENMASK(9, 8)
 189
 190#define MT_MDP_BNRCFR1(_band)		MT_MDP(__OFFS(MDP_BNRCFR1) + \
 191					       ((_band) << 8))
 192#define MT_MDP_RCFR1_MCU_RX_BYPASS	GENMASK(23, 22)
 193#define MT_MDP_RCFR1_RX_DROPPED_UCAST	GENMASK(28, 27)
 194#define MT_MDP_RCFR1_RX_DROPPED_MCAST	GENMASK(30, 29)
 195#define MT_MDP_TO_HIF			0
 196#define MT_MDP_TO_WM			1
 197
 198/* TRB: band 0(0x820e1000), band 1(0x820f1000) */
 199#define MT_WF_TRB_BASE(_band)		((_band) ? 0x820f1000 : 0x820e1000)
 200#define MT_WF_TRB(_band, ofs)		(MT_WF_TRB_BASE(_band) + (ofs))
 201
 202#define MT_TRB_RXPSR0(_band)		MT_WF_TRB(_band, 0x03c)
 203#define MT_TRB_RXPSR0_RX_WTBL_PTR	GENMASK(25, 16)
 204#define MT_TRB_RXPSR0_RX_RMAC_PTR	GENMASK(9, 0)
 205
 206/* TMAC: band 0(0x820e4000), band 1(0x820f4000) */
 207#define MT_WF_TMAC_BASE(_band)		((_band) ? 0x820f4000 : 0x820e4000)
 208#define MT_WF_TMAC(_band, ofs)		(MT_WF_TMAC_BASE(_band) + (ofs))
 209
 210#define MT_TMAC_TCR0(_band)		MT_WF_TMAC(_band, 0)
 211#define MT_TMAC_TCR0_TX_BLINK		GENMASK(7, 6)
 212#define MT_TMAC_TCR0_TBTT_STOP_CTRL	BIT(25)
 213
 214#define MT_TMAC_CDTR(_band)		MT_WF_TMAC(_band, __OFFS(TMAC_CDTR))
 215 #define MT_TMAC_ODTR(_band)		MT_WF_TMAC(_band, __OFFS(TMAC_ODTR))
 216#define MT_TIMEOUT_VAL_PLCP		GENMASK(15, 0)
 217#define MT_TIMEOUT_VAL_CCA		GENMASK(31, 16)
 218
 219#define MT_TMAC_ATCR(_band)		MT_WF_TMAC(_band, __OFFS(TMAC_ATCR))
 220#define MT_TMAC_ATCR_TXV_TOUT		GENMASK(7, 0)
 221
 222#define MT_TMAC_TRCR0(_band)		MT_WF_TMAC(_band, __OFFS(TMAC_TRCR0))
 223#define MT_TMAC_TRCR0_TR2T_CHK		GENMASK(8, 0)
 224#define MT_TMAC_TRCR0_I2T_CHK		GENMASK(24, 16)
 225
 226#define MT_TMAC_ICR0(_band)		MT_WF_TMAC(_band, __OFFS(TMAC_ICR0))
 227#define MT_IFS_EIFS_OFDM		GENMASK(8, 0)
 228#define MT_IFS_RIFS			GENMASK(14, 10)
 229#define MT_IFS_SIFS			GENMASK(22, 16)
 230#define MT_IFS_SLOT			GENMASK(30, 24)
 231
 232#define MT_TMAC_ICR1(_band)		MT_WF_TMAC(_band, __OFFS(TMAC_ICR1))
 233#define MT_IFS_EIFS_CCK			GENMASK(8, 0)
 234
 235#define MT_TMAC_CTCR0(_band)		MT_WF_TMAC(_band, __OFFS(TMAC_CTCR0))
 236#define MT_TMAC_CTCR0_INS_DDLMT_REFTIME		GENMASK(5, 0)
 237#define MT_TMAC_CTCR0_INS_DDLMT_EN		BIT(17)
 238#define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN	BIT(18)
 239
 240#define MT_TMAC_TFCR0(_band)		MT_WF_TMAC(_band, __OFFS(TMAC_TFCR0))
 241
 242/* WF DMA TOP: band 0(0x820e7000),band 1(0x820f7000) */
 243#define MT_WF_DMA_BASE(_band)		((_band) ? 0x820f7000 : 0x820e7000)
 244#define MT_WF_DMA(_band, ofs)		(MT_WF_DMA_BASE(_band) + (ofs))
 245
 246#define MT_DMA_DCR0(_band)		MT_WF_DMA(_band, 0x000)
 247#define MT_DMA_DCR0_MAX_RX_LEN		GENMASK(15, 3)
 248#define MT_DMA_DCR0_RXD_G5_EN		BIT(23)
 249
 250/* WTBLOFF TOP: band 0(0x820e9000),band 1(0x820f9000) */
 251#define MT_WTBLOFF_TOP_BASE(_band)	((_band) ? 0x820f9000 : 0x820e9000)
 252#define MT_WTBLOFF_TOP(_band, ofs)	(MT_WTBLOFF_TOP_BASE(_band) + (ofs))
 253
 254#define MT_WTBLOFF_TOP_RSCR(_band)	MT_WTBLOFF_TOP(_band, 0x008)
 255#define MT_WTBLOFF_TOP_RSCR_RCPI_MODE	GENMASK(31, 30)
 256#define MT_WTBLOFF_TOP_RSCR_RCPI_PARAM	GENMASK(25, 24)
 257
 258#define MT_WTBLOFF_TOP_ACR(_band)	MT_WTBLOFF_TOP(_band, 0x010)
 259#define MT_WTBLOFF_TOP_ADM_BACKOFFTIME	BIT(29)
 260
 261/* ETBF: band 0(0x820ea000), band 1(0x820fa000) */
 262#define MT_WF_ETBF_BASE(_band)		((_band) ? 0x820fa000 : 0x820ea000)
 263#define MT_WF_ETBF(_band, ofs)		(MT_WF_ETBF_BASE(_band) + (ofs))
 264
 265#define MT_ETBF_TX_NDP_BFRP(_band)	MT_WF_ETBF(_band, 0x040)
 266#define MT_ETBF_TX_FB_CPL		GENMASK(31, 16)
 267#define MT_ETBF_TX_FB_TRI		GENMASK(15, 0)
 268
 269#define MT_ETBF_PAR_RPT0(_band)		MT_WF_ETBF(_band, __OFFS(ETBF_PAR_RPT0))
 270#define MT_ETBF_PAR_RPT0_FB_BW		GENMASK(7, 6)
 271#define MT_ETBF_PAR_RPT0_FB_NC		GENMASK(5, 3)
 272#define MT_ETBF_PAR_RPT0_FB_NR		GENMASK(2, 0)
 273
 274#define MT_ETBF_TX_APP_CNT(_band)	MT_WF_ETBF(_band, 0x0f0)
 275#define MT_ETBF_TX_IBF_CNT		GENMASK(31, 16)
 276#define MT_ETBF_TX_EBF_CNT		GENMASK(15, 0)
 277
 278#define MT_ETBF_RX_FB_CNT(_band)	MT_WF_ETBF(_band, 0x0f8)
 279#define MT_ETBF_RX_FB_ALL		GENMASK(31, 24)
 280#define MT_ETBF_RX_FB_HE		GENMASK(23, 16)
 281#define MT_ETBF_RX_FB_VHT		GENMASK(15, 8)
 282#define MT_ETBF_RX_FB_HT		GENMASK(7, 0)
 283
 284/* LPON: band 0(0x820eb000), band 1(0x820fb000) */
 285#define MT_WF_LPON_BASE(_band)		((_band) ? 0x820fb000 : 0x820eb000)
 286#define MT_WF_LPON(_band, ofs)		(MT_WF_LPON_BASE(_band) + (ofs))
 287
 288#define MT_LPON_UTTR0(_band)		MT_WF_LPON(_band, __OFFS(LPON_UTTR0))
 289#define MT_LPON_UTTR1(_band)		MT_WF_LPON(_band, __OFFS(LPON_UTTR1))
 290#define MT_LPON_FRCR(_band)		MT_WF_LPON(_band, __OFFS(LPON_FRCR))
 291
 292#define MT_LPON_TCR(_band, n)		MT_WF_LPON(_band, 0x0a8 +	\
 293						   (((n) * 4) << 1))
 294#define MT_LPON_TCR_MT7916(_band, n)	MT_WF_LPON(_band, 0x0a8 +	\
 295						   (((n) * 4) << 4))
 296#define MT_LPON_TCR_SW_MODE		GENMASK(1, 0)
 297#define MT_LPON_TCR_SW_WRITE		BIT(0)
 298#define MT_LPON_TCR_SW_ADJUST		BIT(1)
 299#define MT_LPON_TCR_SW_READ		GENMASK(1, 0)
 300
 301/* MIB: band 0(0x820ed000), band 1(0x820fd000) */
 302/* These counters are (mostly?) clear-on-read.  So, some should not
 303 * be read at all in case firmware is already reading them.  These
 304 * are commented with 'DNR' below.  The DNR stats will be read by querying
 305 * the firmware API for the appropriate message.  For counters the driver
 306 * does read, the driver should accumulate the counters.
 307 */
 308#define MT_WF_MIB_BASE(_band)		((_band) ? 0x820fd000 : 0x820ed000)
 309#define MT_WF_MIB(_band, ofs)		(MT_WF_MIB_BASE(_band) + (ofs))
 310
 311#define MT_MIB_SDR0(_band)		MT_WF_MIB(_band, 0x010)
 312#define MT_MIB_SDR0_BERACON_TX_CNT_MASK	GENMASK(15, 0)
 313
 314#define MT_MIB_SDR3(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR3))
 315#define MT_MIB_SDR3_FCS_ERR_MASK	GENMASK(15, 0)
 316#define MT_MIB_SDR3_FCS_ERR_MASK_MT7916	GENMASK(31, 16)
 317
 318#define MT_MIB_SDR4(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR4))
 319#define MT_MIB_SDR4_RX_FIFO_FULL_MASK	GENMASK(15, 0)
 320
 321/* rx mpdu counter, full 32 bits */
 322#define MT_MIB_SDR5(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR5))
 323
 324#define MT_MIB_SDR6(_band)		MT_WF_MIB(_band, 0x020)
 325#define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK	GENMASK(15, 0)
 326
 327#define MT_MIB_SDR7(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR7))
 328#define MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK	GENMASK(15, 0)
 329
 330#define MT_MIB_SDR8(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR8))
 331#define MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK	GENMASK(15, 0)
 332
 333/* aka CCA_NAV_TX_TIME */
 334#define MT_MIB_SDR9_DNR(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR9))
 335#define MT_MIB_SDR9_CCA_BUSY_TIME_MASK		GENMASK(23, 0)
 336
 337#define MT_MIB_SDR10(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR10))
 338#define MT_MIB_SDR10_MRDY_COUNT_MASK		GENMASK(25, 0)
 339#define MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916	GENMASK(31, 0)
 340
 341#define MT_MIB_SDR11(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR11))
 342#define MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK	GENMASK(15, 0)
 343
 344/* tx ampdu cnt, full 32 bits */
 345#define MT_MIB_SDR12(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR12))
 346
 347#define MT_MIB_SDR13(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR13))
 348#define MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK	GENMASK(15, 0)
 349
 350/* counts all mpdus in ampdu, regardless of success */
 351#define MT_MIB_SDR14(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR14))
 352#define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK	GENMASK(23, 0)
 353#define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916	GENMASK(31, 0)
 354
 355/* counts all successfully tx'd mpdus in ampdu */
 356#define MT_MIB_SDR15(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR15))
 357#define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK	GENMASK(23, 0)
 358#define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916	GENMASK(31, 0)
 359
 360/* in units of 'us' */
 361#define MT_MIB_SDR16(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR16))
 362#define MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK	GENMASK(23, 0)
 363
 364#define MT_MIB_SDR17(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR17))
 365#define MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK	GENMASK(23, 0)
 366
 367#define MT_MIB_SDR18(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR18))
 368#define MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK	GENMASK(23, 0)
 369
 370/* units are us */
 371#define MT_MIB_SDR19(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR19))
 372#define MT_MIB_SDR19_CCK_MDRDY_TIME_MASK	GENMASK(23, 0)
 373
 374#define MT_MIB_SDR20(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR20))
 375#define MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK	GENMASK(23, 0)
 376
 377#define MT_MIB_SDR21(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR21))
 378#define MT_MIB_SDR21_GREEN_MDRDY_TIME_MASK	GENMASK(23, 0)
 379
 380/* rx ampdu count, 32-bit */
 381#define MT_MIB_SDR22(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR22))
 382
 383/* rx ampdu bytes count, 32-bit */
 384#define MT_MIB_SDR23(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR23))
 385
 386/* rx ampdu valid subframe count */
 387#define MT_MIB_SDR24(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR24))
 388#define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK	GENMASK(23, 0)
 389#define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916	GENMASK(31, 0)
 390
 391/* rx ampdu valid subframe bytes count, 32bits */
 392#define MT_MIB_SDR25(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR25))
 393
 394/* remaining windows protected stats */
 395#define MT_MIB_SDR27(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR27))
 396#define MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK	GENMASK(15, 0)
 397
 398#define MT_MIB_SDR28(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR28))
 399#define MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK	GENMASK(15, 0)
 400
 401#define MT_MIB_SDR29(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR29))
 402#define MT_MIB_SDR29_RX_PFDROP_CNT_MASK		GENMASK(7, 0)
 403#define MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916	GENMASK(15, 0)
 404
 405#define MT_MIB_SDRVEC(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDRVEC))
 406#define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK	GENMASK(15, 0)
 407#define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916	GENMASK(31, 16)
 408
 409/* rx blockack count, 32 bits */
 410#define MT_MIB_SDR31(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR31))
 411
 412#define MT_MIB_SDR32(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR32))
 413#define MT_MIB_SDR32_TX_PKT_EBF_CNT	GENMASK(15, 0)
 414#define MT_MIB_SDR32_TX_PKT_IBF_CNT	GENMASK(31, 16)
 415
 416#define MT_MIB_SDR33(_band)		MT_WF_MIB(_band, 0x088)
 417#define MT_MIB_SDR33_TX_PKT_IBF_CNT	GENMASK(15, 0)
 418
 419#define MT_MIB_SDRMUBF(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDRMUBF))
 420#define MT_MIB_MU_BF_TX_CNT		GENMASK(15, 0)
 421
 422/* 36, 37 both DNR */
 423
 424#define MT_MIB_DR8(_band)		MT_WF_MIB(_band, __OFFS(MIB_DR8))
 425#define MT_MIB_DR9(_band)		MT_WF_MIB(_band, __OFFS(MIB_DR9))
 426#define MT_MIB_DR11(_band)		MT_WF_MIB(_band, __OFFS(MIB_DR11))
 427
 428#define MT_MIB_MB_SDR0(_band, n)	MT_WF_MIB(_band, __OFFS(MIB_MB_SDR0) + (n))
 429#define MT_MIB_RTS_RETRIES_COUNT_MASK	GENMASK(31, 16)
 430#define MT_MIB_RTS_COUNT_MASK		GENMASK(15, 0)
 431
 432#define MT_MIB_MB_SDR1(_band, n)	MT_WF_MIB(_band, __OFFS(MIB_MB_SDR1) + (n))
 433#define MT_MIB_BA_MISS_COUNT_MASK	GENMASK(15, 0)
 434#define MT_MIB_ACK_FAIL_COUNT_MASK	GENMASK(31, 16)
 435
 436#define MT_MIB_MB_SDR2(_band, n)	MT_WF_MIB(_band, 0x518 + (n))
 437#define MT_MIB_MB_BFTF(_band, n)	MT_WF_MIB(_band, 0x510 + (n))
 438
 439#define MT_TX_AGG_CNT(_band, n)		MT_WF_MIB(_band, __OFFS(TX_AGG_CNT) +	\
 440						  ((n) << 2))
 441#define MT_TX_AGG_CNT2(_band, n)	MT_WF_MIB(_band, __OFFS(TX_AGG_CNT2) +	\
 442						  ((n) << 2))
 443#define MT_MIB_ARNG(_band, n)		MT_WF_MIB(_band, __OFFS(MIB_ARNG) +	\
 444						  ((n) << 2))
 445#define MT_MIB_ARNCR_RANGE(val, n)	(((val) >> ((n) << 3)) & GENMASK(7, 0))
 446
 447#define MT_MIB_BFCR0(_band)		MT_WF_MIB(_band, 0x7b0)
 448#define MT_MIB_BFCR0_RX_FB_HT		GENMASK(15, 0)
 449#define MT_MIB_BFCR0_RX_FB_VHT		GENMASK(31, 16)
 450
 451#define MT_MIB_BFCR1(_band)		MT_WF_MIB(_band, 0x7b4)
 452#define MT_MIB_BFCR1_RX_FB_HE		GENMASK(15, 0)
 453
 454#define MT_MIB_BFCR2(_band)		MT_WF_MIB(_band, 0x7b8)
 455#define MT_MIB_BFCR2_BFEE_TX_FB_TRIG	GENMASK(15, 0)
 456
 457#define MT_MIB_BFCR7(_band)		MT_WF_MIB(_band, 0x7cc)
 458#define MT_MIB_BFCR7_BFEE_TX_FB_CPL	GENMASK(15, 0)
 459
 460/* WTBLON TOP */
 461#define MT_WTBLON_TOP_BASE		0x820d4000
 462#define MT_WTBLON_TOP(ofs)		(MT_WTBLON_TOP_BASE + (ofs))
 463#define MT_WTBLON_TOP_WDUCR		MT_WTBLON_TOP(__OFFS(WTBLON_TOP_WDUCR))
 464#define MT_WTBLON_TOP_WDUCR_GROUP	GENMASK(2, 0)
 465
 466#define MT_WTBL_UPDATE			MT_WTBLON_TOP(__OFFS(WTBL_UPDATE))
 467#define MT_WTBL_UPDATE_WLAN_IDX		GENMASK(9, 0)
 468#define MT_WTBL_UPDATE_ADM_COUNT_CLEAR	BIT(12)
 469#define MT_WTBL_UPDATE_BUSY		BIT(31)
 470
 471/* WTBL */
 472#define MT_WTBL_BASE			0x820d8000
 473#define MT_WTBL_LMAC_ID			GENMASK(14, 8)
 474#define MT_WTBL_LMAC_DW			GENMASK(7, 2)
 475#define MT_WTBL_LMAC_OFFS(_id, _dw)	(MT_WTBL_BASE | \
 476					 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \
 477					 FIELD_PREP(MT_WTBL_LMAC_DW, _dw))
 478
 479/* AGG: band 0(0x820e2000), band 1(0x820f2000) */
 480#define MT_WF_AGG_BASE(_band)		((_band) ? 0x820f2000 : 0x820e2000)
 481#define MT_WF_AGG(_band, ofs)		(MT_WF_AGG_BASE(_band) + (ofs))
 482
 483#define MT_AGG_AWSCR0(_band, _n)	MT_WF_AGG(_band, (__OFFS(AGG_AWSCR0) +	\
 484							  (_n) * 4))
 485#define MT_AGG_PCR0(_band, _n)		MT_WF_AGG(_band, (__OFFS(AGG_PCR0) +	\
 486							  (_n) * 4))
 487#define MT_AGG_PCR0_MM_PROT		BIT(0)
 488#define MT_AGG_PCR0_GF_PROT		BIT(1)
 489#define MT_AGG_PCR0_BW20_PROT		BIT(2)
 490#define MT_AGG_PCR0_BW40_PROT		BIT(4)
 491#define MT_AGG_PCR0_BW80_PROT		BIT(6)
 492#define MT_AGG_PCR0_ERP_PROT		GENMASK(12, 8)
 493#define MT_AGG_PCR0_VHT_PROT		BIT(13)
 494#define MT_AGG_PCR0_PTA_WIN_DIS		BIT(15)
 495
 496#define MT_AGG_PCR1_RTS0_NUM_THRES	GENMASK(31, 23)
 497#define MT_AGG_PCR1_RTS0_LEN_THRES	GENMASK(19, 0)
 498
 499#define MT_AGG_ACR0(_band)		MT_WF_AGG(_band, __OFFS(AGG_ACR0))
 500#define MT_AGG_ACR_CFEND_RATE		GENMASK(13, 0)
 501#define MT_AGG_ACR_BAR_RATE		GENMASK(29, 16)
 502
 503#define MT_AGG_ACR4(_band)		MT_WF_AGG(_band, __OFFS(AGG_ACR4))
 504#define MT_AGG_ACR_PPDU_TXS2H		BIT(1)
 505
 506#define MT_AGG_MRCR(_band)		MT_WF_AGG(_band, __OFFS(AGG_MRCR))
 507#define MT_AGG_MRCR_BAR_CNT_LIMIT		GENMASK(15, 12)
 508#define MT_AGG_MRCR_LAST_RTS_CTS_RN		BIT(6)
 509#define MT_AGG_MRCR_RTS_FAIL_LIMIT		GENMASK(11, 7)
 510#define MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT	GENMASK(28, 24)
 511
 512#define MT_AGG_ATCR0(_band)			MT_WF_AGG(_band, __OFFS(AGG_ATCR0))
 513#define MT_AGG_ATCR_MAC_BFF_TIME_EN	BIT(30)
 514
 515#define MT_AGG_ATCR1(_band)		MT_WF_AGG(_band, __OFFS(AGG_ATCR1))
 516#define MT_AGG_ATCR3(_band)		MT_WF_AGG(_band, __OFFS(AGG_ATCR3))
 517
 518/* ARB: band 0(0x820e3000), band 1(0x820f3000) */
 519#define MT_WF_ARB_BASE(_band)		((_band) ? 0x820f3000 : 0x820e3000)
 520#define MT_WF_ARB(_band, ofs)		(MT_WF_ARB_BASE(_band) + (ofs))
 521
 522#define MT_ARB_SCR(_band)		MT_WF_ARB(_band, __OFFS(ARB_SCR))
 523#define MT_ARB_SCR_TX_DISABLE		BIT(8)
 524#define MT_ARB_SCR_RX_DISABLE		BIT(9)
 525
 526#define MT_ARB_DRNGR0(_band, _n)	MT_WF_ARB(_band, (__OFFS(ARB_DRNGR0) +	\
 527							  (_n) * 4))
 528
 529/* RMAC: band 0(0x820e5000), band 1(0x820f5000) */
 530#define MT_WF_RMAC_BASE(_band)		((_band) ? 0x820f5000 : 0x820e5000)
 531#define MT_WF_RMAC(_band, ofs)		(MT_WF_RMAC_BASE(_band) + (ofs))
 532
 533#define MT_WF_RFCR(_band)		MT_WF_RMAC(_band, 0x000)
 534#define MT_WF_RFCR_DROP_STBC_MULTI	BIT(0)
 535#define MT_WF_RFCR_DROP_FCSFAIL		BIT(1)
 536#define MT_WF_RFCR_DROP_VERSION		BIT(3)
 537#define MT_WF_RFCR_DROP_PROBEREQ	BIT(4)
 538#define MT_WF_RFCR_DROP_MCAST		BIT(5)
 539#define MT_WF_RFCR_DROP_BCAST		BIT(6)
 540#define MT_WF_RFCR_DROP_MCAST_FILTERED	BIT(7)
 541#define MT_WF_RFCR_DROP_A3_MAC		BIT(8)
 542#define MT_WF_RFCR_DROP_A3_BSSID	BIT(9)
 543#define MT_WF_RFCR_DROP_A2_BSSID	BIT(10)
 544#define MT_WF_RFCR_DROP_OTHER_BEACON	BIT(11)
 545#define MT_WF_RFCR_DROP_FRAME_REPORT	BIT(12)
 546#define MT_WF_RFCR_DROP_CTL_RSV		BIT(13)
 547#define MT_WF_RFCR_DROP_CTS		BIT(14)
 548#define MT_WF_RFCR_DROP_RTS		BIT(15)
 549#define MT_WF_RFCR_DROP_DUPLICATE	BIT(16)
 550#define MT_WF_RFCR_DROP_OTHER_BSS	BIT(17)
 551#define MT_WF_RFCR_DROP_OTHER_UC	BIT(18)
 552#define MT_WF_RFCR_DROP_OTHER_TIM	BIT(19)
 553#define MT_WF_RFCR_DROP_NDPA		BIT(20)
 554#define MT_WF_RFCR_DROP_UNWANTED_CTL	BIT(21)
 555
 556#define MT_WF_RFCR1(_band)		MT_WF_RMAC(_band, 0x004)
 557#define MT_WF_RFCR1_DROP_ACK		BIT(4)
 558#define MT_WF_RFCR1_DROP_BF_POLL	BIT(5)
 559#define MT_WF_RFCR1_DROP_BA		BIT(6)
 560#define MT_WF_RFCR1_DROP_CFEND		BIT(7)
 561#define MT_WF_RFCR1_DROP_CFACK		BIT(8)
 562
 563#define MT_WF_RMAC_RSVD0(_band)	MT_WF_RMAC(_band, 0x02e0)
 564#define MT_WF_RMAC_RSVD0_EIFS_CLR	BIT(21)
 565
 566#define MT_WF_RMAC_MIB_AIRTIME0(_band)	MT_WF_RMAC(_band, 0x0380)
 567#define MT_WF_RMAC_MIB_RXTIME_CLR	BIT(31)
 568#define MT_WF_RMAC_MIB_OBSS_BACKOFF	GENMASK(15, 0)
 569#define MT_WF_RMAC_MIB_ED_OFFSET	GENMASK(20, 16)
 570
 571#define MT_WF_RMAC_MIB_AIRTIME1(_band)	MT_WF_RMAC(_band, 0x0384)
 572#define MT_WF_RMAC_MIB_NONQOSD_BACKOFF	GENMASK(31, 16)
 573
 574#define MT_WF_RMAC_MIB_AIRTIME3(_band)	MT_WF_RMAC(_band, 0x038c)
 575#define MT_WF_RMAC_MIB_QOS01_BACKOFF	GENMASK(31, 0)
 576
 577#define MT_WF_RMAC_MIB_AIRTIME4(_band)	MT_WF_RMAC(_band, 0x0390)
 578#define MT_WF_RMAC_MIB_QOS23_BACKOFF	GENMASK(31, 0)
 579
 580/* WFDMA0 */
 581#define MT_WFDMA0_BASE			__REG(WFDMA0_ADDR)
 582#define MT_WFDMA0(ofs)			(MT_WFDMA0_BASE + (ofs))
 583
 584#define MT_WFDMA0_RST			MT_WFDMA0(0x100)
 585#define MT_WFDMA0_RST_LOGIC_RST		BIT(4)
 586#define MT_WFDMA0_RST_DMASHDL_ALL_RST	BIT(5)
 587
 588#define MT_WFDMA0_BUSY_ENA		MT_WFDMA0(0x13c)
 589#define MT_WFDMA0_BUSY_ENA_TX_FIFO0	BIT(0)
 590#define MT_WFDMA0_BUSY_ENA_TX_FIFO1	BIT(1)
 591#define MT_WFDMA0_BUSY_ENA_RX_FIFO	BIT(2)
 592
 593#define MT_WFDMA0_MCU_HOST_INT_ENA	MT_WFDMA0(0x1f4)
 594
 595#define MT_WFDMA0_GLO_CFG		MT_WFDMA0(0x208)
 596#define MT_WFDMA0_GLO_CFG_TX_DMA_EN	BIT(0)
 597#define MT_WFDMA0_GLO_CFG_RX_DMA_EN	BIT(2)
 598#define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO	BIT(28)
 599#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO	BIT(27)
 600#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2	BIT(21)
 601
 602#define MT_WFDMA0_RST_DTX_PTR		MT_WFDMA0(0x20c)
 603
 604#define MT_WFDMA0_EXT0_CFG		MT_WFDMA0(0x2b0)
 605#define MT_WFDMA0_EXT0_RXWB_KEEP	BIT(10)
 606
 607#define MT_WFDMA0_PRI_DLY_INT_CFG0	MT_WFDMA0(0x2f0)
 608#define MT_WFDMA0_PRI_DLY_INT_CFG1	MT_WFDMA0(0x2f4)
 609#define MT_WFDMA0_PRI_DLY_INT_CFG2	MT_WFDMA0(0x2f8)
 610#define MT_WPDMA_GLO_CFG		MT_WFDMA0(0x208)
 611
 612/* WFDMA1 */
 613#define MT_WFDMA1_BASE			0xd5000
 614#define MT_WFDMA1(ofs)			(MT_WFDMA1_BASE + (ofs))
 615
 616#define MT_WFDMA1_RST			MT_WFDMA1(0x100)
 617#define MT_WFDMA1_RST_LOGIC_RST		BIT(4)
 618#define MT_WFDMA1_RST_DMASHDL_ALL_RST	BIT(5)
 619
 620#define MT_WFDMA1_BUSY_ENA		MT_WFDMA1(0x13c)
 621#define MT_WFDMA1_BUSY_ENA_TX_FIFO0	BIT(0)
 622#define MT_WFDMA1_BUSY_ENA_TX_FIFO1	BIT(1)
 623#define MT_WFDMA1_BUSY_ENA_RX_FIFO	BIT(2)
 624
 625#define MT_WFDMA1_GLO_CFG		MT_WFDMA1(0x208)
 626#define MT_WFDMA1_GLO_CFG_TX_DMA_EN	BIT(0)
 627#define MT_WFDMA1_GLO_CFG_RX_DMA_EN	BIT(2)
 628#define MT_WFDMA1_GLO_CFG_OMIT_TX_INFO	BIT(28)
 629#define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO	BIT(27)
 630#define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2	BIT(21)
 631
 632#define MT_WFDMA1_RST_DTX_PTR		MT_WFDMA1(0x20c)
 633#define MT_WFDMA1_PRI_DLY_INT_CFG0	MT_WFDMA1(0x2f0)
 634
 635/* WFDMA CSR */
 636#define MT_WFDMA_EXT_CSR_BASE		__REG(WFDMA_EXT_CSR_ADDR)
 637#define MT_WFDMA_EXT_CSR_PHYS_BASE	0x18027000
 638#define MT_WFDMA_EXT_CSR(ofs)		(MT_WFDMA_EXT_CSR_BASE + (ofs))
 639#define MT_WFDMA_EXT_CSR_PHYS(ofs)	(MT_WFDMA_EXT_CSR_PHYS_BASE + (ofs))
 640
 641#define MT_WFDMA_HOST_CONFIG		MT_WFDMA_EXT_CSR_PHYS(0x30)
 642#define MT_WFDMA_HOST_CONFIG_PDMA_BAND	BIT(0)
 643#define MT_WFDMA_HOST_CONFIG_WED	BIT(1)
 644
 645#define MT_WFDMA_WED_RING_CONTROL	MT_WFDMA_EXT_CSR_PHYS(0x34)
 646#define MT_WFDMA_WED_RING_CONTROL_TX0	GENMASK(4, 0)
 647#define MT_WFDMA_WED_RING_CONTROL_TX1	GENMASK(12, 8)
 648#define MT_WFDMA_WED_RING_CONTROL_RX1	GENMASK(20, 16)
 649
 650#define MT_WFDMA_EXT_CSR_HIF_MISC	MT_WFDMA_EXT_CSR_PHYS(0x44)
 651#define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY	BIT(0)
 652
 653#define MT_PCIE_RECOG_ID		0xd7090
 654#define MT_PCIE_RECOG_ID_MASK		GENMASK(30, 0)
 655#define MT_PCIE_RECOG_ID_SEM		BIT(31)
 656
 657#define MT_INT_WED_SOURCE_CSR		MT_WFDMA_EXT_CSR(0x200)
 658#define MT_INT_WED_MASK_CSR		MT_WFDMA_EXT_CSR(0x204)
 659
 660#define MT_WED_TX_RING_BASE		MT_WFDMA_EXT_CSR(0x300)
 661#define MT_WED_RX_RING_BASE		MT_WFDMA_EXT_CSR(0x400)
 662
 663/* WFDMA0 PCIE1 */
 664#define MT_WFDMA0_PCIE1_BASE		__REG(WFDMA0_PCIE1_ADDR)
 665#define MT_WFDMA0_PCIE1(ofs)		(MT_WFDMA0_PCIE1_BASE + (ofs))
 666
 667#define MT_WFDMA0_PCIE1_BUSY_ENA	MT_WFDMA0_PCIE1(0x13c)
 668#define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0	BIT(0)
 669#define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1	BIT(1)
 670#define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO	BIT(2)
 671
 672/* WFDMA1 PCIE1 */
 673#define MT_WFDMA1_PCIE1_BASE		0xd9000
 674#define MT_WFDMA1_PCIE1(ofs)		(MT_WFDMA1_PCIE1_BASE + (ofs))
 675
 676#define MT_WFDMA1_PCIE1_BUSY_ENA	MT_WFDMA1_PCIE1(0x13c)
 677#define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0	BIT(0)
 678#define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1	BIT(1)
 679#define MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO	BIT(2)
 680
 681/* WFDMA COMMON */
 682#define __RXQ(q)			((q) + __MT_MCUQ_MAX)
 683#define __TXQ(q)			(__RXQ(q) + MT_RXQ_BAND2)
 684
 685#define MT_Q_ID(q)			(dev->q_id[(q)])
 686#define MT_Q_BASE(q)			((dev->wfdma_mask >> (q)) & 0x1 ?	\
 687					 MT_WFDMA1_BASE : MT_WFDMA0_BASE)
 688
 689#define MT_MCUQ_ID(q)			MT_Q_ID(q)
 690#define MT_TXQ_ID(q)			MT_Q_ID(__TXQ(q))
 691#define MT_RXQ_ID(q)			MT_Q_ID(__RXQ(q))
 692
 693#define MT_MCUQ_RING_BASE(q)		(MT_Q_BASE(q) + 0x300)
 694#define MT_TXQ_RING_BASE(q)		(MT_Q_BASE(__TXQ(q)) + 0x300)
 695#define MT_RXQ_RING_BASE(q)		(MT_Q_BASE(__RXQ(q)) + 0x500)
 696
 697#define MT_MCUQ_EXT_CTRL(q)		(MT_Q_BASE(q) +	0x600 +	\
 698					 MT_MCUQ_ID(q)* 0x4)
 699#define MT_RXQ_BAND1_CTRL(q)		(MT_Q_BASE(__RXQ(q)) + 0x680 +	\
 700					 MT_RXQ_ID(q)* 0x4)
 701#define MT_TXQ_EXT_CTRL(q)		(MT_Q_BASE(__TXQ(q)) + 0x600 +	\
 702					 MT_TXQ_ID(q)* 0x4)
 703
 704#define MT_TXQ_WED_RING_BASE		__REG(TXQ_WED_RING_BASE)
 705#define MT_RXQ_WED_RING_BASE		__REG(RXQ_WED_RING_BASE)
 706#define MT_RXQ_WED_DATA_RING_BASE	__REG(RXQ_WED_DATA_RING_BASE)
 707
 708#define MT_INT_SOURCE_CSR		__REG(INT_SOURCE_CSR)
 709#define MT_INT_MASK_CSR			__REG(INT_MASK_CSR)
 710
 711#define MT_INT1_SOURCE_CSR		__REG(INT1_SOURCE_CSR)
 712#define MT_INT1_MASK_CSR		__REG(INT1_MASK_CSR)
 713
 714#define MT_INT_RX_DONE_BAND0		BIT(16)
 715#define MT_INT_RX_DONE_BAND1		BIT(17)
 716#define MT_INT_RX_DONE_WM		BIT(0)
 717#define MT_INT_RX_DONE_WA		BIT(1)
 718#define MT_INT_RX_DONE_WA_MAIN		BIT(1)
 719#define MT_INT_RX_DONE_WA_EXT		BIT(2)
 720#define MT_INT_MCU_CMD			BIT(29)
 721#define MT_INT_RX_DONE_BAND0_MT7916	BIT(22)
 722#define MT_INT_RX_DONE_BAND1_MT7916	BIT(23)
 723#define MT_INT_RX_DONE_WA_MAIN_MT7916	BIT(2)
 724#define MT_INT_RX_DONE_WA_EXT_MT7916	BIT(3)
 725
 726#define MT_INT_WED_RX_DONE_BAND0_MT7916		BIT(18)
 727#define MT_INT_WED_RX_DONE_BAND1_MT7916		BIT(19)
 728#define MT_INT_WED_RX_DONE_WA_MAIN_MT7916	BIT(1)
 729#define MT_INT_WED_RX_DONE_WA_MT7916		BIT(17)
 730
 731#define MT_INT_RX(q)			(dev->q_int_mask[__RXQ(q)])
 732#define MT_INT_TX_MCU(q)		(dev->q_int_mask[(q)])
 733
 734#define MT_INT_RX_DONE_MCU		(MT_INT_RX(MT_RXQ_MCU) |	\
 735					 MT_INT_RX(MT_RXQ_MCU_WA))
 736
 737#define MT_INT_BAND0_RX_DONE		(MT_INT_RX(MT_RXQ_MAIN) |	\
 738					 MT_INT_RX(MT_RXQ_MAIN_WA))
 739
 740#define MT_INT_BAND1_RX_DONE		(MT_INT_RX(MT_RXQ_BAND1) |	\
 741					 MT_INT_RX(MT_RXQ_BAND1_WA) |	\
 742					 MT_INT_RX(MT_RXQ_MAIN_WA))
 743
 744#define MT_INT_RX_DONE_ALL		(MT_INT_RX_DONE_MCU |		\
 745					 MT_INT_BAND0_RX_DONE |		\
 746					 MT_INT_BAND1_RX_DONE)
 747
 748#define MT_INT_TX_DONE_FWDL		BIT(26)
 749#define MT_INT_TX_DONE_MCU_WM		BIT(27)
 750#define MT_INT_TX_DONE_MCU_WA		BIT(15)
 751#define MT_INT_TX_DONE_BAND0		BIT(30)
 752#define MT_INT_TX_DONE_BAND1		BIT(31)
 753#define MT_INT_TX_DONE_MCU_WA_MT7916	BIT(25)
 754#define MT_INT_WED_TX_DONE_BAND0	BIT(4)
 755#define MT_INT_WED_TX_DONE_BAND1	BIT(5)
 756
 757#define MT_INT_TX_DONE_MCU		(MT_INT_TX_MCU(MT_MCUQ_WA) |	\
 758					 MT_INT_TX_MCU(MT_MCUQ_WM) |	\
 759					 MT_INT_TX_MCU(MT_MCUQ_FWDL))
 760
 761#define MT_MCU_CMD			__REG(INT_MCU_CMD_SOURCE)
 762#define MT_MCU_CMD_STOP_DMA_FW_RELOAD	BIT(1)
 763#define MT_MCU_CMD_STOP_DMA		BIT(2)
 764#define MT_MCU_CMD_RESET_DONE		BIT(3)
 765#define MT_MCU_CMD_RECOVERY_DONE	BIT(4)
 766#define MT_MCU_CMD_NORMAL_STATE		BIT(5)
 767#define MT_MCU_CMD_ERROR_MASK		GENMASK(5, 1)
 768
 769#define MT_MCU_CMD_WA_WDT		BIT(31)
 770#define MT_MCU_CMD_WM_WDT		BIT(30)
 771#define MT_MCU_CMD_WDT_MASK		GENMASK(31, 30)
 772
 773/* TOP RGU */
 774#define MT_TOP_RGU_BASE			0x18000000
 775#define MT_TOP_PWR_CTRL			(MT_TOP_RGU_BASE + (0x0))
 776#define MT_TOP_PWR_KEY			(0x5746 << 16)
 777#define MT_TOP_PWR_SW_RST		BIT(0)
 778#define MT_TOP_PWR_SW_PWR_ON		GENMASK(3, 2)
 779#define MT_TOP_PWR_HW_CTRL		BIT(4)
 780#define MT_TOP_PWR_PWR_ON		BIT(7)
 781
 782#define MT_TOP_RGU_SYSRAM_PDN		(MT_TOP_RGU_BASE + 0x050)
 783#define MT_TOP_RGU_SYSRAM_SLP		(MT_TOP_RGU_BASE + 0x054)
 784#define MT_TOP_WFSYS_PWR		(MT_TOP_RGU_BASE + 0x010)
 785#define MT_TOP_PWR_EN_MASK		BIT(7)
 786#define MT_TOP_PWR_ACK_MASK		BIT(6)
 787#define MT_TOP_PWR_KEY_MASK		GENMASK(31, 16)
 788
 789#define MT7986_TOP_WM_RESET		(MT_TOP_RGU_BASE + 0x120)
 790#define MT7986_TOP_WM_RESET_MASK	BIT(0)
 791
 792/* l1/l2 remap */
 793#define MT_HIF_REMAP_L1			0xf11ac
 794#define MT_HIF_REMAP_L1_MT7916		0xfe260
 795#define MT_HIF_REMAP_L1_MASK		GENMASK(15, 0)
 796#define MT_HIF_REMAP_L1_OFFSET		GENMASK(15, 0)
 797#define MT_HIF_REMAP_L1_BASE		GENMASK(31, 16)
 798#define MT_HIF_REMAP_BASE_L1		0xe0000
 799
 800#define MT_HIF_REMAP_L2			0xf11b0
 801#define MT_HIF_REMAP_L2_MASK		GENMASK(19, 0)
 802#define MT_HIF_REMAP_L2_OFFSET		GENMASK(11, 0)
 803#define MT_HIF_REMAP_L2_BASE		GENMASK(31, 12)
 804#define MT_HIF_REMAP_L2_MT7916		0x1b8
 805#define MT_HIF_REMAP_L2_MASK_MT7916	GENMASK(31, 16)
 806#define MT_HIF_REMAP_L2_OFFSET_MT7916	GENMASK(15, 0)
 807#define MT_HIF_REMAP_L2_BASE_MT7916	GENMASK(31, 16)
 808#define MT_HIF_REMAP_BASE_L2_MT7916	0x40000
 809
 810#define MT_INFRA_BASE			0x18000000
 811#define MT_WFSYS0_PHY_START		0x18400000
 812#define MT_WFSYS1_PHY_START		0x18800000
 813#define MT_WFSYS1_PHY_END		0x18bfffff
 814#define MT_CBTOP1_PHY_START		0x70000000
 815#define MT_CBTOP1_PHY_END		__REG(CBTOP1_PHY_END)
 816#define MT_CBTOP2_PHY_START		0xf0000000
 817#define MT_INFRA_MCU_START		0x7c000000
 818#define MT_INFRA_MCU_END		__REG(INFRA_MCU_ADDR_END)
 819#define MT_CONN_INFRA_OFFSET(p)		((p) - MT_INFRA_BASE)
 820
 821/* CONN INFRA CFG */
 822#define MT_CONN_INFRA_BASE		0x18001000
 823#define MT_CONN_INFRA(ofs)		(MT_CONN_INFRA_BASE + (ofs))
 824
 825#define MT_CONN_INFRA_EFUSE		MT_CONN_INFRA(0x020)
 826
 827#define MT_CONN_INFRA_ADIE_RESET	MT_CONN_INFRA(0x030)
 828#define MT_CONN_INFRA_ADIE1_RESET_MASK	BIT(0)
 829#define MT_CONN_INFRA_ADIE2_RESET_MASK	BIT(2)
 830
 831#define MT_CONN_INFRA_OSC_RC_EN		MT_CONN_INFRA(0x380)
 832
 833#define MT_CONN_INFRA_OSC_CTRL		MT_CONN_INFRA(0x300)
 834#define MT_CONN_INFRA_OSC_RC_EN_MASK	BIT(7)
 835#define MT_CONN_INFRA_OSC_STB_TIME_MASK	GENMASK(23, 0)
 836
 837#define MT_CONN_INFRA_HW_CTRL		MT_CONN_INFRA(0x200)
 838#define MT_CONN_INFRA_HW_CTRL_MASK	BIT(0)
 839
 840#define MT_CONN_INFRA_WF_SLP_PROT	MT_CONN_INFRA(0x540)
 841#define MT_CONN_INFRA_WF_SLP_PROT_MASK	BIT(0)
 842
 843#define MT_CONN_INFRA_WF_SLP_PROT_RDY	MT_CONN_INFRA(0x544)
 844#define MT_CONN_INFRA_CONN_WF_MASK	(BIT(29) | BIT(31))
 845#define MT_CONN_INFRA_CONN		(BIT(25) | BIT(29) | BIT(31))
 846
 847#define MT_CONN_INFRA_EMI_REQ		MT_CONN_INFRA(0x414)
 848#define MT_CONN_INFRA_EMI_REQ_MASK	BIT(0)
 849#define MT_CONN_INFRA_INFRA_REQ_MASK	BIT(5)
 850
 851/* AFE */
 852#define MT_AFE_CTRL_BASE(_band)		(0x18003000 + ((_band) << 19))
 853#define MT_AFE_CTRL(_band, ofs)		(MT_AFE_CTRL_BASE(_band) + (ofs))
 854
 855#define MT_AFE_DIG_EN_01(_band)		MT_AFE_CTRL(_band, 0x00)
 856#define MT_AFE_DIG_EN_02(_band)		MT_AFE_CTRL(_band, 0x04)
 857#define MT_AFE_DIG_EN_03(_band)		MT_AFE_CTRL(_band, 0x08)
 858#define MT_AFE_DIG_TOP_01(_band)	MT_AFE_CTRL(_band, 0x0c)
 859
 860#define MT_AFE_PLL_STB_TIME(_band)	MT_AFE_CTRL(_band, 0xf4)
 861#define MT_AFE_PLL_STB_TIME_MASK	(GENMASK(30, 16) | GENMASK(14, 0))
 862#define MT_AFE_PLL_STB_TIME_VAL		(FIELD_PREP(GENMASK(30, 16), 0x4bc) | \
 863					 FIELD_PREP(GENMASK(14, 0), 0x7e4))
 864#define MT_AFE_BPLL_CFG_MASK		GENMASK(7, 6)
 865#define MT_AFE_WPLL_CFG_MASK		GENMASK(1, 0)
 866#define MT_AFE_MCU_WPLL_CFG_MASK	GENMASK(3, 2)
 867#define MT_AFE_MCU_BPLL_CFG_MASK	GENMASK(17, 16)
 868#define MT_AFE_PLL_CFG_MASK		(MT_AFE_BPLL_CFG_MASK | \
 869					 MT_AFE_WPLL_CFG_MASK | \
 870					 MT_AFE_MCU_WPLL_CFG_MASK | \
 871					 MT_AFE_MCU_BPLL_CFG_MASK)
 872#define MT_AFE_PLL_CFG_VAL		(FIELD_PREP(MT_AFE_BPLL_CFG_MASK, 0x1) | \
 873					 FIELD_PREP(MT_AFE_WPLL_CFG_MASK, 0x2) | \
 874					 FIELD_PREP(MT_AFE_MCU_WPLL_CFG_MASK, 0x1) | \
 875					 FIELD_PREP(MT_AFE_MCU_BPLL_CFG_MASK, 0x2))
 876
 877#define MT_AFE_DIG_TOP_01_MASK		GENMASK(18, 15)
 878#define MT_AFE_DIG_TOP_01_VAL		FIELD_PREP(MT_AFE_DIG_TOP_01_MASK, 0x9)
 879
 880#define MT_AFE_RG_WBG_EN_RCK_MASK	BIT(0)
 881#define MT_AFE_RG_WBG_EN_BPLL_UP_MASK	BIT(21)
 882#define MT_AFE_RG_WBG_EN_WPLL_UP_MASK	BIT(20)
 883#define MT_AFE_RG_WBG_EN_PLL_UP_MASK	(MT_AFE_RG_WBG_EN_BPLL_UP_MASK | \
 884					 MT_AFE_RG_WBG_EN_WPLL_UP_MASK)
 885#define MT_AFE_RG_WBG_EN_TXCAL_WF4	BIT(29)
 886#define MT_AFE_RG_WBG_EN_TXCAL_BT	BIT(21)
 887#define MT_AFE_RG_WBG_EN_TXCAL_WF3	BIT(20)
 888#define MT_AFE_RG_WBG_EN_TXCAL_WF2	BIT(19)
 889#define MT_AFE_RG_WBG_EN_TXCAL_WF1	BIT(18)
 890#define MT_AFE_RG_WBG_EN_TXCAL_WF0	BIT(17)
 891
 892#define MT_ADIE_SLP_CTRL_BASE(_band)	(0x18005000 + ((_band) << 19))
 893#define MT_ADIE_SLP_CTRL(_band, ofs)	(MT_ADIE_SLP_CTRL_BASE(_band) + (ofs))
 894
 895#define MT_ADIE_SLP_CTRL_CK0(_band)	MT_ADIE_SLP_CTRL(_band, 0x120)
 896
 897/* ADIE */
 898#define MT_ADIE_CHIP_ID			0x02c
 899#define MT_ADIE_VERSION_MASK		GENMASK(15, 0)
 900#define MT_ADIE_CHIP_ID_MASK		GENMASK(31, 16)
 901#define MT_ADIE_IDX0			GENMASK(15, 0)
 902#define MT_ADIE_IDX1			GENMASK(31, 16)
 903
 904#define MT_ADIE_RG_TOP_THADC_BG		0x034
 905#define MT_ADIE_VRPI_SEL_CR_MASK	GENMASK(15, 12)
 906#define MT_ADIE_VRPI_SEL_EFUSE_MASK	GENMASK(6, 3)
 907
 908#define MT_ADIE_RG_TOP_THADC		0x038
 909#define MT_ADIE_PGA_GAIN_MASK		GENMASK(25, 23)
 910#define MT_ADIE_PGA_GAIN_EFUSE_MASK	GENMASK(2, 0)
 911#define MT_ADIE_LDO_CTRL_MASK		GENMASK(27, 26)
 912#define MT_ADIE_LDO_CTRL_EFUSE_MASK	GENMASK(6, 5)
 913
 914#define MT_AFE_RG_ENCAL_WBTAC_IF_SW	0x070
 915#define MT_ADIE_EFUSE_RDATA0		0x130
 916
 917#define MT_ADIE_EFUSE2_CTRL		0x148
 918#define MT_ADIE_EFUSE_CTRL_MASK		BIT(1)
 919
 920#define MT_ADIE_EFUSE_CFG		0x144
 921#define MT_ADIE_EFUSE_MODE_MASK		GENMASK(7, 6)
 922#define MT_ADIE_EFUSE_ADDR_MASK		GENMASK(25, 16)
 923#define MT_ADIE_EFUSE_VALID_MASK	BIT(29)
 924#define MT_ADIE_EFUSE_KICK_MASK		BIT(30)
 925
 926#define MT_ADIE_THADC_ANALOG		0x3a6
 927
 928#define MT_ADIE_THADC_SLOP		0x3a7
 929#define MT_ADIE_ANA_EN_MASK		BIT(7)
 930
 931#define MT_ADIE_7975_XTAL_CAL		0x3a1
 932#define MT_ADIE_TRIM_MASK		GENMASK(6, 0)
 933#define MT_ADIE_EFUSE_TRIM_MASK		GENMASK(5, 0)
 934#define MT_ADIE_XO_TRIM_EN_MASK		BIT(7)
 935#define MT_ADIE_XTAL_DECREASE_MASK	BIT(6)
 936
 937#define MT_ADIE_7975_XO_TRIM2		0x3a2
 938#define MT_ADIE_7975_XO_TRIM3		0x3a3
 939#define MT_ADIE_7975_XO_TRIM4		0x3a4
 940#define MT_ADIE_7975_XTAL_EN		0x3a5
 941
 942#define MT_ADIE_XO_TRIM_FLOW		0x3ac
 943#define MT_ADIE_XTAL_AXM_80M_OSC	0x390
 944#define MT_ADIE_XTAL_AXM_40M_OSC	0x391
 945#define MT_ADIE_XTAL_TRIM1_80M_OSC	0x398
 946#define MT_ADIE_XTAL_TRIM1_40M_OSC	0x399
 947#define MT_ADIE_WRI_CK_SEL		0x4ac
 948#define MT_ADIE_RG_STRAP_PIN_IN		0x4fc
 949#define MT_ADIE_XTAL_C1			0x654
 950#define MT_ADIE_XTAL_C2			0x658
 951#define MT_ADIE_RG_XO_01		0x65c
 952#define MT_ADIE_RG_XO_03		0x664
 953
 954#define MT_ADIE_CLK_EN			0xa00
 955
 956#define MT_ADIE_7975_XTAL		0xa18
 957#define MT_ADIE_7975_XTAL_EN_MASK	BIT(29)
 958
 959#define MT_ADIE_7975_COCLK		0xa1c
 960#define MT_ADIE_7975_XO_2		0xa84
 961#define MT_ADIE_7975_XO_2_FIX_EN	BIT(31)
 962
 963#define MT_ADIE_7975_XO_CTRL2		0xa94
 964#define MT_ADIE_7975_XO_CTRL2_C1_MASK	GENMASK(26, 20)
 965#define MT_ADIE_7975_XO_CTRL2_C2_MASK	GENMASK(18, 12)
 966#define MT_ADIE_7975_XO_CTRL2_MASK	(MT_ADIE_7975_XO_CTRL2_C1_MASK | \
 967					 MT_ADIE_7975_XO_CTRL2_C2_MASK)
 968
 969#define MT_ADIE_7975_XO_CTRL6		0xaa4
 970#define MT_ADIE_7975_XO_CTRL6_MASK	BIT(16)
 971
 972/* TOP SPI */
 973#define MT_TOP_SPI_ADIE_BASE(_band)	(0x18004000 + ((_band) << 19))
 974#define MT_TOP_SPI_ADIE(_band, ofs)	(MT_TOP_SPI_ADIE_BASE(_band) + (ofs))
 975
 976#define MT_TOP_SPI_BUSY_CR(_band)	MT_TOP_SPI_ADIE(_band, 0)
 977#define MT_TOP_SPI_POLLING_BIT		BIT(5)
 978
 979#define MT_TOP_SPI_ADDR_CR(_band)	MT_TOP_SPI_ADIE(_band, 0x50)
 980#define MT_TOP_SPI_READ_ADDR_FORMAT	(BIT(12) | BIT(13) | BIT(15))
 981#define MT_TOP_SPI_WRITE_ADDR_FORMAT	(BIT(13) | BIT(15))
 982
 983#define MT_TOP_SPI_WRITE_DATA_CR(_band)	MT_TOP_SPI_ADIE(_band, 0x54)
 984#define MT_TOP_SPI_READ_DATA_CR(_band)	MT_TOP_SPI_ADIE(_band, 0x58)
 985
 986/* CONN INFRA CKGEN */
 987#define MT_INFRA_CKGEN_BASE		0x18009000
 988#define MT_INFRA_CKGEN(ofs)		(MT_INFRA_CKGEN_BASE + (ofs))
 989
 990#define MT_INFRA_CKGEN_BUS		MT_INFRA_CKGEN(0xa00)
 991#define MT_INFRA_CKGEN_BUS_CLK_SEL_MASK	BIT(23)
 992#define MT_INFRA_CKGEN_BUS_RDY_SEL_MASK	BIT(29)
 993
 994#define MT_INFRA_CKGEN_BUS_WPLL_DIV_1	MT_INFRA_CKGEN(0x008)
 995#define MT_INFRA_CKGEN_BUS_WPLL_DIV_2	MT_INFRA_CKGEN(0x00c)
 996
 997#define MT_INFRA_CKGEN_RFSPI_WPLL_DIV	MT_INFRA_CKGEN(0x040)
 998#define MT_INFRA_CKGEN_DIV_SEL_MASK	GENMASK(7, 2)
 999#define MT_INFRA_CKGEN_DIV_EN_MASK	BIT(0)
1000
1001/* CONN INFRA BUS */
1002#define MT_INFRA_BUS_BASE		0x1800e000
1003#define MT_INFRA_BUS(ofs)		(MT_INFRA_BUS_BASE + (ofs))
1004
1005#define MT_INFRA_BUS_OFF_TIMEOUT	MT_INFRA_BUS(0x300)
1006#define MT_INFRA_BUS_TIMEOUT_LIMIT_MASK	GENMASK(14, 7)
1007#define MT_INFRA_BUS_TIMEOUT_EN_MASK	GENMASK(3, 0)
1008
1009#define MT_INFRA_BUS_ON_TIMEOUT		MT_INFRA_BUS(0x31c)
1010#define MT_INFRA_BUS_EMI_START		MT_INFRA_BUS(0x360)
1011#define MT_INFRA_BUS_EMI_END		MT_INFRA_BUS(0x364)
1012
1013/* CONN_INFRA_SKU */
1014#define MT_CONNINFRA_SKU_DEC_ADDR	0x18050000
1015#define MT_CONNINFRA_SKU_MASK		GENMASK(15, 0)
1016#define MT_ADIE_TYPE_MASK		BIT(1)
1017
1018/* FW MODE SYNC */
1019#define MT_FW_ASSERT_STAT		__REG(FW_ASSERT_STAT_ADDR)
1020#define MT_FW_EXCEPT_TYPE		__REG(FW_EXCEPT_TYPE_ADDR)
1021#define MT_FW_EXCEPT_COUNT		__REG(FW_EXCEPT_COUNT_ADDR)
1022#define MT_FW_CIRQ_COUNT		__REG(FW_CIRQ_COUNT_ADDR)
1023#define MT_FW_CIRQ_IDX			__REG(FW_CIRQ_IDX_ADDR)
1024#define MT_FW_CIRQ_LISR			__REG(FW_CIRQ_LISR_ADDR)
1025#define MT_FW_TASK_ID			__REG(FW_TASK_ID_ADDR)
1026#define MT_FW_TASK_IDX			__REG(FW_TASK_IDX_ADDR)
1027#define MT_FW_TASK_QID1			__REG(FW_TASK_QID1_ADDR)
1028#define MT_FW_TASK_QID2			__REG(FW_TASK_QID2_ADDR)
1029#define MT_FW_TASK_START		__REG(FW_TASK_START_ADDR)
1030#define MT_FW_TASK_END			__REG(FW_TASK_END_ADDR)
1031#define MT_FW_TASK_SIZE			__REG(FW_TASK_SIZE_ADDR)
1032#define MT_FW_LAST_MSG_ID		__REG(FW_LAST_MSG_ID_ADDR)
1033#define MT_FW_EINT_INFO			__REG(FW_EINT_INFO_ADDR)
1034#define MT_FW_SCHED_INFO		__REG(FW_SCHED_INFO_ADDR)
1035
1036#define MT_SWDEF_BASE			__REG(SWDEF_BASE_ADDR)
1037
1038#define MT_SWDEF(ofs)			(MT_SWDEF_BASE + (ofs))
1039#define MT_SWDEF_MODE			MT_SWDEF(0x3c)
1040#define MT_SWDEF_NORMAL_MODE		0
1041#define MT_SWDEF_ICAP_MODE		1
1042#define MT_SWDEF_SPECTRUM_MODE		2
1043
1044#define MT_SWDEF_SER_STATS		MT_SWDEF(0x040)
1045#define MT_SWDEF_PLE_STATS		MT_SWDEF(0x044)
1046#define MT_SWDEF_PLE1_STATS		MT_SWDEF(0x048)
1047#define MT_SWDEF_PLE_AMSDU_STATS	MT_SWDEF(0x04C)
1048#define MT_SWDEF_PSE_STATS		MT_SWDEF(0x050)
1049#define MT_SWDEF_PSE1_STATS		MT_SWDEF(0x054)
1050#define MT_SWDEF_LAMC_WISR6_BN0_STATS	MT_SWDEF(0x058)
1051#define MT_SWDEF_LAMC_WISR6_BN1_STATS	MT_SWDEF(0x05C)
1052#define MT_SWDEF_LAMC_WISR7_BN0_STATS	MT_SWDEF(0x060)
1053#define MT_SWDEF_LAMC_WISR7_BN1_STATS	MT_SWDEF(0x064)
1054
1055#define MT_DIC_CMD_REG_BASE		0x41f000
1056#define MT_DIC_CMD_REG(ofs)		(MT_DIC_CMD_REG_BASE + (ofs))
1057#define MT_DIC_CMD_REG_CMD		MT_DIC_CMD_REG(0x10)
1058
1059#define MT_CPU_UTIL_BASE		0x41f030
1060#define MT_CPU_UTIL(ofs)		(MT_CPU_UTIL_BASE + (ofs))
1061#define MT_CPU_UTIL_BUSY_PCT		MT_CPU_UTIL(0x00)
1062#define MT_CPU_UTIL_PEAK_BUSY_PCT	MT_CPU_UTIL(0x04)
1063#define MT_CPU_UTIL_IDLE_CNT		MT_CPU_UTIL(0x08)
1064#define MT_CPU_UTIL_PEAK_IDLE_CNT	MT_CPU_UTIL(0x0c)
1065#define MT_CPU_UTIL_CTRL		MT_CPU_UTIL(0x1c)
1066
1067/* LED */
1068#define MT_LED_TOP_BASE			0x18013000
1069#define MT_LED_PHYS(_n)			(MT_LED_TOP_BASE + (_n))
1070
1071#define MT_LED_CTRL(_n)			MT_LED_PHYS(0x00 + ((_n) * 4))
1072#define MT_LED_CTRL_KICK		BIT(7)
1073#define MT_LED_CTRL_BAND		BIT(4)
1074#define MT_LED_CTRL_BLINK_MODE		BIT(2)
1075#define MT_LED_CTRL_POLARITY		BIT(1)
1076
1077#define MT_LED_TX_BLINK(_n)		MT_LED_PHYS(0x10 + ((_n) * 4))
1078#define MT_LED_TX_BLINK_ON_MASK		GENMASK(7, 0)
1079#define MT_LED_TX_BLINK_OFF_MASK        GENMASK(15, 8)
1080
1081#define MT_LED_STATUS_0(_n)		MT_LED_PHYS(0x20 + ((_n) * 8))
1082#define MT_LED_STATUS_1(_n)		MT_LED_PHYS(0x24 + ((_n) * 8))
1083#define MT_LED_STATUS_OFF		GENMASK(31, 24)
1084#define MT_LED_STATUS_ON		GENMASK(23, 16)
1085#define MT_LED_STATUS_DURATION		GENMASK(15, 0)
1086
1087#define MT_LED_EN(_n)			MT_LED_PHYS(0x40 + ((_n) * 4))
1088
1089#define MT_LED_GPIO_MUX0		0x70005050 /* GPIO 1 and GPIO 2 */
1090#define MT_LED_GPIO_MUX1		0x70005054 /* GPIO 14 and 15 */
1091#define MT_LED_GPIO_MUX2                0x70005058 /* GPIO 18 */
1092#define MT_LED_GPIO_MUX3		0x7000505c /* GPIO 26 */
1093
1094/* MT TOP */
1095#define MT_TOP_BASE			0x18060000
1096#define MT_TOP(ofs)			(MT_TOP_BASE + (ofs))
1097
1098#define MT_TOP_LPCR_HOST_BAND(_band)	MT_TOP(0x10 + ((_band) * 0x10))
1099#define MT_TOP_LPCR_HOST_FW_OWN		BIT(0)
1100#define MT_TOP_LPCR_HOST_DRV_OWN	BIT(1)
1101#define MT_TOP_LPCR_HOST_FW_OWN_STAT	BIT(2)
1102
1103#define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band)	MT_TOP(0x14 + ((_band) * 0x10))
1104#define MT_TOP_LPCR_HOST_BAND_STAT	BIT(0)
1105
1106#define MT_TOP_MISC			MT_TOP(0xf0)
1107#define MT_TOP_MISC_FW_STATE		GENMASK(2, 0)
1108
1109#define MT_TOP_WFSYS_WAKEUP		MT_TOP(0x1a4)
1110#define MT_TOP_WFSYS_WAKEUP_MASK	BIT(0)
1111
1112#define MT_TOP_MCU_EMI_BASE		MT_TOP(0x1c4)
1113#define MT_TOP_MCU_EMI_BASE_MASK	GENMASK(19, 0)
1114
1115#define MT_TOP_WF_AP_PERI_BASE		MT_TOP(0x1c8)
1116#define MT_TOP_WF_AP_PERI_BASE_MASK	GENMASK(19, 0)
1117
1118#define MT_TOP_EFUSE_BASE		MT_TOP(0x1cc)
1119#define MT_TOP_EFUSE_BASE_MASK		GENMASK(19, 0)
1120
1121#define MT_TOP_CONN_INFRA_WAKEUP	MT_TOP(0x1a0)
1122#define MT_TOP_CONN_INFRA_WAKEUP_MASK	BIT(0)
1123
1124#define MT_TOP_WFSYS_RESET_STATUS	MT_TOP(0x2cc)
1125#define MT_TOP_WFSYS_RESET_STATUS_MASK	BIT(30)
1126
1127/* SEMA */
1128#define MT_SEMA_BASE			0x18070000
1129#define MT_SEMA(ofs)			(MT_SEMA_BASE + (ofs))
1130
1131#define MT_SEMA_RFSPI_STATUS		(MT_SEMA(0x2000) + (11 * 4))
1132#define MT_SEMA_RFSPI_RELEASE		(MT_SEMA(0x2200) + (11 * 4))
1133#define MT_SEMA_RFSPI_STATUS_MASK	BIT(1)
1134
1135/* MCU BUS */
1136#define MT_MCU_BUS_BASE			0x18400000
1137#define MT_MCU_BUS(ofs)			(MT_MCU_BUS_BASE + (ofs))
1138
1139#define MT_MCU_BUS_TIMEOUT		MT_MCU_BUS(0xf0440)
1140#define MT_MCU_BUS_TIMEOUT_SET_MASK	GENMASK(7, 0)
1141#define MT_MCU_BUS_TIMEOUT_CG_EN_MASK	BIT(28)
1142#define MT_MCU_BUS_TIMEOUT_EN_MASK	BIT(31)
1143
1144#define MT_MCU_BUS_REMAP		MT_MCU_BUS(0x120)
1145
1146/* TOP CFG */
1147#define MT_TOP_CFG_BASE			0x184b0000
1148#define MT_TOP_CFG(ofs)			(MT_TOP_CFG_BASE + (ofs))
1149
1150#define MT_TOP_CFG_IP_VERSION_ADDR	MT_TOP_CFG(0x010)
1151
1152/* TOP CFG ON */
1153#define MT_TOP_CFG_ON_BASE		0x184c1000
1154#define MT_TOP_CFG_ON(ofs)		(MT_TOP_CFG_ON_BASE + (ofs))
1155
1156#define MT_TOP_CFG_ON_ROM_IDX		MT_TOP_CFG_ON(0x604)
1157
1158/* SLP CTRL */
1159#define MT_SLP_BASE			0x184c3000
1160#define MT_SLP(ofs)			(MT_SLP_BASE + (ofs))
1161
1162#define MT_SLP_STATUS			MT_SLP(0x00c)
1163#define MT_SLP_WFDMA2CONN_MASK		(BIT(21) | BIT(23))
1164#define MT_SLP_CTRL_EN_MASK		BIT(0)
1165#define MT_SLP_CTRL_BSY_MASK		BIT(1)
1166
1167/* MCU BUS DBG */
1168#define MT_MCU_BUS_DBG_BASE		0x18500000
1169#define MT_MCU_BUS_DBG(ofs)		(MT_MCU_BUS_DBG_BASE + (ofs))
1170
1171#define MT_MCU_BUS_DBG_TIMEOUT		MT_MCU_BUS_DBG(0x0)
1172#define MT_MCU_BUS_DBG_TIMEOUT_SET_MASK GENMASK(31, 16)
1173#define MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK BIT(3)
1174#define MT_MCU_BUS_DBG_TIMEOUT_EN_MASK	BIT(2)
1175
1176#define MT_HW_BOUND			0x70010020
1177#define MT_HW_REV			0x70010204
1178#define MT_WF_SUBSYS_RST		0x70002600
1179
1180/* PCIE MAC */
1181#define MT_PCIE_MAC_BASE		0x74030000
1182#define MT_PCIE_MAC(ofs)		(MT_PCIE_MAC_BASE + (ofs))
1183#define MT_PCIE_MAC_INT_ENABLE		MT_PCIE_MAC(0x188)
1184
1185#define MT_PCIE1_MAC_INT_ENABLE		0x74020188
1186#define MT_PCIE1_MAC_INT_ENABLE_MT7916	0x74090188
1187
1188#define MT_WM_MCU_PC			0x7c060204
1189#define MT_WA_MCU_PC			0x7c06020c
1190
1191/* PP TOP */
1192#define MT_WF_PP_TOP_BASE		0x820cc000
1193#define MT_WF_PP_TOP(ofs)		(MT_WF_PP_TOP_BASE + (ofs))
1194
1195#define MT_WF_PP_TOP_RXQ_WFDMA_CF_5	MT_WF_PP_TOP(0x0e8)
1196#define MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK	BIT(6)
1197
1198#define MT_WF_IRPI_BASE			0x83000000
1199#define MT_WF_IRPI(ofs)			(MT_WF_IRPI_BASE + (ofs))
1200
1201#define MT_WF_IRPI_NSS(phy, nss)	MT_WF_IRPI(0x6000 + ((phy) << 20) + ((nss) << 16))
1202#define MT_WF_IRPI_NSS_MT7916(phy, nss)	MT_WF_IRPI(0x1000 + ((phy) << 20) + ((nss) << 16))
1203
1204/* PHY */
1205#define MT_WF_PHY_BASE			0x83080000
1206#define MT_WF_PHY(ofs)			(MT_WF_PHY_BASE + (ofs))
1207
1208#define MT_WF_PHY_RX_CTRL1(_phy)	MT_WF_PHY(0x2004 + ((_phy) << 16))
1209#define MT_WF_PHY_RX_CTRL1_MT7916(_phy)	MT_WF_PHY(0x2004 + ((_phy) << 20))
1210#define MT_WF_PHY_RX_CTRL1_IPI_EN	GENMASK(2, 0)
1211#define MT_WF_PHY_RX_CTRL1_STSCNT_EN	GENMASK(11, 9)
1212
1213#define MT_WF_PHY_RXTD12(_phy)		MT_WF_PHY(0x8230 + ((_phy) << 16))
1214#define MT_WF_PHY_RXTD12_MT7916(_phy)	MT_WF_PHY(0x8230 + ((_phy) << 20))
1215#define MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY	BIT(18)
1216#define MT_WF_PHY_RXTD12_IRPI_SW_CLR		BIT(29)
1217
1218#define MT_WF_PHY_TPC_CTRL_STAT(_phy)		MT_WF_PHY(0xe7a0 + ((_phy) << 16))
1219#define MT_WF_PHY_TPC_CTRL_STAT_MT7916(_phy)	MT_WF_PHY(0xe7a0 + ((_phy) << 20))
1220#define MT_WF_PHY_TPC_POWER			GENMASK(15, 8)
1221
1222#define MT_MCU_WM_CIRQ_BASE			0x89010000
1223#define MT_MCU_WM_CIRQ(ofs)			(MT_MCU_WM_CIRQ_BASE + (ofs))
1224#define MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR	MT_MCU_WM_CIRQ(0x80)
1225#define MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR		MT_MCU_WM_CIRQ(0xc0)
1226#define MT_MCU_WM_CIRQ_EINT_MASK_CLR_ADDR	MT_MCU_WM_CIRQ(0x108)
1227#define MT_MCU_WM_CIRQ_EINT_SOFT_ADDR		MT_MCU_WM_CIRQ(0x118)
1228
1229#endif
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