mt7915.h

  1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
  2/* Copyright (C) 2020 MediaTek Inc. */
  3
  4#ifndef __MT7915_H
  5#define __MT7915_H
  6
  7#include <linux/interrupt.h>
  8#include <linux/ktime.h>
  9#include "../mt76_connac.h"
 10#include "regs.h"
 11
 12#define MT7915_MAX_INTERFACES		19
 13#define MT7915_WTBL_SIZE		288
 14#define MT7916_WTBL_SIZE		544
 15#define MT7915_WTBL_RESERVED		(mt7915_wtbl_size(dev) - 1)
 16#define MT7915_WTBL_STA			(MT7915_WTBL_RESERVED - \
 17					 MT7915_MAX_INTERFACES)
 18
 19#define MT7915_WATCHDOG_TIME		(HZ / 10)
 20#define MT7915_RESET_TIMEOUT		(30 * HZ)
 21
 22#define MT7915_TX_RING_SIZE		2048
 23#define MT7915_TX_MCU_RING_SIZE		256
 24#define MT7915_TX_FWDL_RING_SIZE	128
 25
 26#define MT7915_RX_RING_SIZE		1536
 27#define MT7915_RX_MCU_RING_SIZE		512
 28
 29#define MT7915_FIRMWARE_WA		"mediatek/mt7915_wa.bin"
 30#define MT7915_FIRMWARE_WM		"mediatek/mt7915_wm.bin"
 31#define MT7915_ROM_PATCH		"mediatek/mt7915_rom_patch.bin"
 32
 33#define MT7916_FIRMWARE_WA		"mediatek/mt7916_wa.bin"
 34#define MT7916_FIRMWARE_WM		"mediatek/mt7916_wm.bin"
 35#define MT7916_ROM_PATCH		"mediatek/mt7916_rom_patch.bin"
 36
 37#define MT7981_FIRMWARE_WA		"mediatek/mt7981_wa.bin"
 38#define MT7981_FIRMWARE_WM		"mediatek/mt7981_wm.bin"
 39#define MT7981_ROM_PATCH		"mediatek/mt7981_rom_patch.bin"
 40
 41#define MT7986_FIRMWARE_WA		"mediatek/mt7986_wa.bin"
 42#define MT7986_FIRMWARE_WM		"mediatek/mt7986_wm.bin"
 43#define MT7986_FIRMWARE_WM_MT7975	"mediatek/mt7986_wm_mt7975.bin"
 44#define MT7986_ROM_PATCH		"mediatek/mt7986_rom_patch.bin"
 45#define MT7986_ROM_PATCH_MT7975		"mediatek/mt7986_rom_patch_mt7975.bin"
 46
 47#define MT7915_EEPROM_DEFAULT		"mediatek/mt7915_eeprom.bin"
 48#define MT7915_EEPROM_DEFAULT_DBDC	"mediatek/mt7915_eeprom_dbdc.bin"
 49#define MT7916_EEPROM_DEFAULT		"mediatek/mt7916_eeprom.bin"
 50
 51#define MT7981_EEPROM_MT7976_DEFAULT_DBDC	"mediatek/mt7981_eeprom_mt7976_dbdc.bin"
 52
 53#define MT7986_EEPROM_MT7975_DEFAULT		"mediatek/mt7986_eeprom_mt7975.bin"
 54#define MT7986_EEPROM_MT7975_DUAL_DEFAULT	"mediatek/mt7986_eeprom_mt7975_dual.bin"
 55#define MT7986_EEPROM_MT7976_DEFAULT		"mediatek/mt7986_eeprom_mt7976.bin"
 56#define MT7986_EEPROM_MT7976_DEFAULT_DBDC	"mediatek/mt7986_eeprom_mt7976_dbdc.bin"
 57#define MT7986_EEPROM_MT7976_DUAL_DEFAULT	"mediatek/mt7986_eeprom_mt7976_dual.bin"
 58
 59#define MT7915_EEPROM_SIZE		3584
 60#define MT7916_EEPROM_SIZE		4096
 61
 62#define MT7915_EEPROM_BLOCK_SIZE	16
 63#define MT7915_HW_TOKEN_SIZE		4096
 64#define MT7915_TOKEN_SIZE		8192
 65
 66#define MT7915_CFEND_RATE_DEFAULT	0x49	/* OFDM 24M */
 67#define MT7915_CFEND_RATE_11B		0x03	/* 11B LP, 11M */
 68
 69#define MT7915_THERMAL_THROTTLE_MAX	100
 70#define MT7915_CDEV_THROTTLE_MAX	99
 71
 72#define MT7915_SKU_RATE_NUM		161
 73#define MT7915_SKU_PATH_NUM		185
 74
 75#define MT7915_MAX_TWT_AGRT		16
 76#define MT7915_MAX_STA_TWT_AGRT		8
 77#define MT7915_MIN_TWT_DUR 64
 78#define MT7915_MAX_QUEUE		(MT_RXQ_BAND2 + __MT_MCUQ_MAX + 2)
 79
 80#define MT7915_WED_RX_TOKEN_SIZE	12288
 81
 82#define MT7915_CRIT_TEMP_IDX		0
 83#define MT7915_MAX_TEMP_IDX		1
 84#define MT7915_CRIT_TEMP		110
 85#define MT7915_MAX_TEMP			120
 86
 87struct mt7915_vif;
 88struct mt7915_sta;
 89struct mt7915_dfs_pulse;
 90struct mt7915_dfs_pattern;
 91
 92enum mt7915_txq_id {
 93	MT7915_TXQ_FWDL = 16,
 94	MT7915_TXQ_MCU_WM,
 95	MT7915_TXQ_BAND0,
 96	MT7915_TXQ_BAND1,
 97	MT7915_TXQ_MCU_WA,
 98};
 99
100enum mt7915_rxq_id {
101	MT7915_RXQ_BAND0 = 0,
102	MT7915_RXQ_BAND1,
103	MT7915_RXQ_MCU_WM = 0,
104	MT7915_RXQ_MCU_WA,
105	MT7915_RXQ_MCU_WA_EXT,
106};
107
108enum mt7916_rxq_id {
109	MT7916_RXQ_MCU_WM = 0,
110	MT7916_RXQ_MCU_WA,
111	MT7916_RXQ_MCU_WA_MAIN,
112	MT7916_RXQ_MCU_WA_EXT,
113	MT7916_RXQ_BAND0,
114	MT7916_RXQ_BAND1,
115};
116
117struct mt7915_twt_flow {
118	struct list_head list;
119	u64 start_tsf;
120	u64 tsf;
121	u32 duration;
122	u16 wcid;
123	__le16 mantissa;
124	u8 exp;
125	u8 table_id;
126	u8 id;
127	u8 protection:1;
128	u8 flowtype:1;
129	u8 trigger:1;
130	u8 sched:1;
131};
132
133DECLARE_EWMA(avg_signal, 10, 8)
134
135struct mt7915_sta {
136	struct mt76_wcid wcid; /* must be first */
137
138	struct mt7915_vif *vif;
139
140	struct list_head rc_list;
141	u32 airtime_ac[8];
142
143	int ack_signal;
144	struct ewma_avg_signal avg_ack_signal;
145
146	unsigned long changed;
147	unsigned long jiffies;
148	struct mt76_connac_sta_key_conf bip;
149
150	struct {
151		u8 flowid_mask;
152		struct mt7915_twt_flow flow[MT7915_MAX_STA_TWT_AGRT];
153	} twt;
154};
155
156struct mt7915_vif_cap {
157	bool ht_ldpc:1;
158	bool vht_ldpc:1;
159	bool he_ldpc:1;
160	bool vht_su_ebfer:1;
161	bool vht_su_ebfee:1;
162	bool vht_mu_ebfer:1;
163	bool vht_mu_ebfee:1;
164	bool he_su_ebfer:1;
165	bool he_su_ebfee:1;
166	bool he_mu_ebfer:1;
167};
168
169struct mt7915_vif {
170	struct mt76_vif_link mt76; /* must be first */
171
172	struct mt7915_vif_cap cap;
173	struct mt7915_sta sta;
174	struct mt7915_phy *phy;
175
176	struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS];
177	struct cfg80211_bitrate_mask bitrate_mask;
178};
179
180/* crash-dump */
181struct mt7915_crash_data {
182	guid_t guid;
183	struct timespec64 timestamp;
184
185	u8 *memdump_buf;
186	size_t memdump_buf_len;
187};
188
189struct mt7915_hif {
190	struct list_head list;
191
192	struct device *dev;
193	void __iomem *regs;
194	int irq;
195	u32 index;
196};
197
198struct mt7915_phy {
199	struct mt76_phy *mt76;
200	struct mt7915_dev *dev;
201
202	struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
203
204	struct ieee80211_vif *monitor_vif;
205
206	struct thermal_cooling_device *cdev;
207	u8 cdev_state;
208	u8 throttle_state;
209	u32 throttle_temp[2]; /* 0: critical high, 1: maximum */
210
211	u32 rxfilter;
212	u64 omac_mask;
213
214	u16 noise;
215
216	s16 coverage_class;
217	u8 slottime;
218
219	u32 trb_ts;
220
221	u32 rx_ampdu_ts;
222	u32 ampdu_ref;
223
224	struct mt76_mib_stats mib;
225	struct mt76_channel_state state_ts;
226
227	bool sku_limit_en:1;
228	bool sku_path_en:1;
229
230#ifdef CONFIG_NL80211_TESTMODE
231	struct {
232		u32 *reg_backup;
233
234		s32 last_freq_offset;
235		u8 last_rcpi[4];
236		s8 last_ib_rssi[4];
237		s8 last_wb_rssi[4];
238		u8 last_snr;
239
240		u8 spe_idx;
241	} test;
242#endif
243};
244
245struct mt7915_dev {
246	union { /* must be first */
247		struct mt76_dev mt76;
248		struct mt76_phy mphy;
249	};
250
251	struct mt7915_hif *hif2;
252	struct mt7915_reg_desc reg;
253	u8 q_id[MT7915_MAX_QUEUE];
254	u32 q_int_mask[MT7915_MAX_QUEUE];
255	u32 wfdma_mask;
256
257	const struct mt76_bus_ops *bus_ops;
258	struct mt7915_phy phy;
259
260	/* monitor rx chain configured channel */
261	struct cfg80211_chan_def rdd2_chandef;
262	struct mt7915_phy *rdd2_phy;
263
264	u16 chainmask;
265	u16 chainshift;
266	u32 hif_idx;
267
268	struct work_struct init_work;
269	struct work_struct rc_work;
270	struct work_struct dump_work;
271	struct work_struct reset_work;
272	wait_queue_head_t reset_wait;
273
274	struct {
275		u32 state;
276		u32 wa_reset_count;
277		u32 wm_reset_count;
278		bool hw_full_reset:1;
279		bool hw_init_done:1;
280		bool restart:1;
281	} recovery;
282
283	/* protects coredump data */
284	struct mutex dump_mutex;
285#ifdef CONFIG_DEV_COREDUMP
286	struct {
287		struct mt7915_crash_data *crash_data;
288	} coredump;
289#endif
290
291	struct list_head sta_rc_list;
292	struct list_head twt_list;
293	spinlock_t reg_lock;
294
295	u32 hw_pattern;
296
297	bool dbdc_support;
298	bool flash_mode;
299	bool muru_debug;
300	bool ibf;
301
302	u8 monitor_mask;
303
304	struct dentry *debugfs_dir;
305	struct rchan *relay_fwlog;
306
307	void *cal;
308	u32 cur_prek_offset;
309	u8 dpd_chan_num_2g;
310	u8 dpd_chan_num_5g;
311	u8 dpd_chan_num_6g;
312
313	struct {
314		u8 debug_wm;
315		u8 debug_wa;
316		u8 debug_bin;
317	} fw;
318
319	struct {
320		u16 table_mask;
321		u8 n_agrt;
322	} twt;
323
324	struct reset_control *rstc;
325	void __iomem *dcm;
326	void __iomem *sku;
327};
328
329enum {
330	WFDMA0 = 0x0,
331	WFDMA1,
332	WFDMA_EXT,
333	__MT_WFDMA_MAX,
334};
335
336enum rdd_idx {
337	MT_RDD_IDX_BAND0,	/* RDD idx for band idx 0 (single-band) */
338	MT_RDD_IDX_BAND1,	/* RDD idx for band idx 1 */
339	MT_RDD_IDX_BACKGROUND,	/* RDD idx for background chain */
340};
341
342enum mt7915_rdd_cmd {
343	RDD_STOP,
344	RDD_START,
345	RDD_DET_MODE,
346	RDD_RADAR_EMULATE,
347	RDD_START_TXQ = 20,
348	RDD_SET_WF_ANT = 30,
349	RDD_CAC_START = 50,
350	RDD_CAC_END,
351	RDD_NORMAL_START,
352	RDD_DISABLE_DFS_CAL,
353	RDD_PULSE_DBG,
354	RDD_READ_PULSE,
355	RDD_RESUME_BF,
356	RDD_IRQ_OFF,
357};
358
359static inline int
360mt7915_get_rdd_idx(struct mt7915_phy *phy, bool is_background)
361{
362	if (!phy->mt76->cap.has_5ghz)
363		return -1;
364
365	if (is_background)
366		return MT_RDD_IDX_BACKGROUND;
367
368	return phy->mt76->band_idx;
369}
370
371static inline struct mt7915_phy *
372mt7915_hw_phy(struct ieee80211_hw *hw)
373{
374	struct mt76_phy *phy = hw->priv;
375
376	return phy->priv;
377}
378
379static inline struct mt7915_dev *
380mt7915_hw_dev(struct ieee80211_hw *hw)
381{
382	struct mt76_phy *phy = hw->priv;
383
384	return container_of(phy->dev, struct mt7915_dev, mt76);
385}
386
387static inline struct mt7915_phy *
388mt7915_ext_phy(struct mt7915_dev *dev)
389{
390	struct mt76_phy *phy = dev->mt76.phys[MT_BAND1];
391
392	if (!phy)
393		return NULL;
394
395	return phy->priv;
396}
397
398static inline u32 mt7915_check_adie(struct mt7915_dev *dev, bool sku)
399{
400	u32 mask = sku ? MT_CONNINFRA_SKU_MASK : MT_ADIE_TYPE_MASK;
401	if (!is_mt798x(&dev->mt76))
402		return 0;
403
404	return mt76_rr(dev, MT_CONNINFRA_SKU_DEC_ADDR) & mask;
405}
406
407extern const struct ieee80211_ops mt7915_ops;
408extern const struct mt76_testmode_ops mt7915_testmode_ops;
409extern struct pci_driver mt7915_pci_driver;
410extern struct pci_driver mt7915_hif_driver;
411extern struct platform_driver mt798x_wmac_driver;
412
413#ifdef CONFIG_MT798X_WMAC
414int mt7986_wmac_enable(struct mt7915_dev *dev);
415void mt7986_wmac_disable(struct mt7915_dev *dev);
416#else
417static inline int mt7986_wmac_enable(struct mt7915_dev *dev)
418{
419	return 0;
420}
421
422static inline void mt7986_wmac_disable(struct mt7915_dev *dev)
423{
424}
425#endif
426struct mt7915_dev *mt7915_mmio_probe(struct device *pdev,
427				     void __iomem *mem_base, u32 device_id);
428void mt7915_wfsys_reset(struct mt7915_dev *dev);
429irqreturn_t mt7915_irq_handler(int irq, void *dev_instance);
430u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif);
431u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);
432
433int mt7915_register_device(struct mt7915_dev *dev);
434void mt7915_unregister_device(struct mt7915_dev *dev);
435int mt7915_eeprom_init(struct mt7915_dev *dev);
436void mt7915_eeprom_parse_hw_cap(struct mt7915_dev *dev,
437				struct mt7915_phy *phy);
438int mt7915_eeprom_get_target_power(struct mt7915_dev *dev,
439				   struct ieee80211_channel *chan,
440				   u8 chain_idx);
441s8 mt7915_eeprom_get_power_delta(struct mt7915_dev *dev, int band);
442bool mt7915_eeprom_has_background_radar(struct mt7915_dev *dev);
443int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2);
444void mt7915_dma_prefetch(struct mt7915_dev *dev);
445void mt7915_dma_cleanup(struct mt7915_dev *dev);
446int mt7915_dma_reset(struct mt7915_dev *dev, bool force);
447int mt7915_dma_start(struct mt7915_dev *dev, bool reset, bool wed_reset);
448int mt7915_txbf_init(struct mt7915_dev *dev);
449void mt7915_init_txpower(struct mt7915_phy *phy);
450void mt7915_reset(struct mt7915_dev *dev);
451int mt7915_run(struct ieee80211_hw *hw);
452int mt7915_mcu_init(struct mt7915_dev *dev);
453int mt7915_mcu_init_firmware(struct mt7915_dev *dev);
454int mt7915_mcu_twt_agrt_update(struct mt7915_dev *dev,
455			       struct mt7915_vif *mvif,
456			       struct mt7915_twt_flow *flow,
457			       int cmd);
458int mt7915_mcu_add_dev_info(struct mt7915_phy *phy,
459			    struct ieee80211_vif *vif, bool enable);
460int mt7915_mcu_add_bss_info(struct mt7915_phy *phy,
461			    struct ieee80211_vif *vif, int enable);
462int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
463		       struct ieee80211_sta *sta, int conn_state, bool newly);
464int mt7915_mcu_add_tx_ba(struct mt7915_dev *dev,
465			 struct ieee80211_ampdu_params *params,
466			 bool add);
467int mt7915_mcu_add_rx_ba(struct mt7915_dev *dev,
468			 struct ieee80211_ampdu_params *params,
469			 bool add);
470int mt7915_mcu_update_bss_color(struct mt7915_dev *dev, struct ieee80211_vif *vif,
471				struct cfg80211_he_bss_color *he_bss_color);
472int mt7915_mcu_add_inband_discov(struct mt7915_dev *dev, struct ieee80211_vif *vif,
473				 u32 changed);
474int mt7915_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
475			  int enable, u32 changed);
476int mt7915_mcu_add_obss_spr(struct mt7915_phy *phy, struct ieee80211_vif *vif,
477			    struct ieee80211_he_obss_pd *he_obss_pd);
478int mt7915_mcu_add_rate_ctrl(struct mt7915_dev *dev, struct ieee80211_vif *vif,
479			     struct ieee80211_sta *sta, bool changed);
480int mt7915_mcu_add_smps(struct mt7915_dev *dev, struct ieee80211_vif *vif,
481			struct ieee80211_sta *sta);
482int mt7915_set_channel(struct mt76_phy *mphy);
483int mt7915_mcu_set_chan_info(struct mt7915_phy *phy, int cmd);
484int mt7915_mcu_set_tx(struct mt7915_dev *dev, struct ieee80211_vif *vif);
485int mt7915_mcu_update_edca(struct mt7915_dev *dev, void *req);
486int mt7915_mcu_set_fixed_rate_ctrl(struct mt7915_dev *dev,
487				   struct ieee80211_vif *vif,
488				   struct ieee80211_sta *sta,
489				   void *data, u32 field);
490int mt7915_mcu_set_eeprom(struct mt7915_dev *dev);
491int mt7915_mcu_get_eeprom(struct mt7915_dev *dev, u32 offset, u8 *read_buf);
492int mt7915_mcu_get_eeprom_free_block(struct mt7915_dev *dev, u8 *block_num);
493int mt7915_mcu_set_mac(struct mt7915_dev *dev, int band, bool enable,
494		       bool hdr_trans);
495int mt7915_mcu_set_test_param(struct mt7915_dev *dev, u8 param, bool test_mode,
496			      u8 en);
497int mt7915_mcu_set_ser(struct mt7915_dev *dev, u8 action, u8 set, u8 band);
498int mt7915_mcu_set_sku_en(struct mt7915_phy *phy);
499int mt7915_mcu_set_txpower_sku(struct mt7915_phy *phy);
500int mt7915_mcu_get_txpower_sku(struct mt7915_phy *phy, s8 *txpower, int len,
501			       u8 category);
502int mt7915_mcu_set_txpower_frame_min(struct mt7915_phy *phy, s8 txpower);
503int mt7915_mcu_set_txpower_frame(struct mt7915_phy *phy,
504				 struct ieee80211_vif *vif,
505				 struct ieee80211_sta *sta, s8 txpower);
506int mt7915_mcu_set_txbf(struct mt7915_dev *dev, u8 action);
507int mt7915_mcu_set_fcc5_lpn(struct mt7915_dev *dev, int val);
508int mt7915_mcu_set_pulse_th(struct mt7915_dev *dev,
509			    const struct mt7915_dfs_pulse *pulse);
510int mt7915_mcu_set_radar_th(struct mt7915_dev *dev, int index,
511			    const struct mt7915_dfs_pattern *pattern);
512int mt7915_mcu_set_muru_ctrl(struct mt7915_dev *dev, u32 cmd, u32 val);
513int mt7915_mcu_apply_group_cal(struct mt7915_dev *dev);
514int mt7915_mcu_apply_tx_dpd(struct mt7915_phy *phy);
515int mt7915_mcu_get_chan_mib_info(struct mt7915_phy *phy, bool chan_switch);
516int mt7915_mcu_get_temperature(struct mt7915_phy *phy);
517int mt7915_mcu_set_thermal_throttling(struct mt7915_phy *phy, u8 state);
518int mt7915_mcu_set_thermal_protect(struct mt7915_phy *phy);
519int mt7915_mcu_get_rx_rate(struct mt7915_phy *phy, struct ieee80211_vif *vif,
520			   struct ieee80211_sta *sta, struct rate_info *rate);
521int mt7915_mcu_rdd_background_enable(struct mt7915_phy *phy,
522				     struct cfg80211_chan_def *chandef);
523int mt7915_mcu_wed_wa_tx_stats(struct mt7915_dev *dev, u16 wcid);
524int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set);
525int mt7915_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3);
526int mt7915_mcu_fw_log_2_host(struct mt7915_dev *dev, u8 type, u8 ctrl);
527int mt7915_mcu_fw_dbg_ctrl(struct mt7915_dev *dev, u32 module, u8 level);
528void mt7915_mcu_rx_event(struct mt7915_dev *dev, struct sk_buff *skb);
529void mt7915_mcu_exit(struct mt7915_dev *dev);
530
531static inline u16 mt7915_wtbl_size(struct mt7915_dev *dev)
532{
533	return is_mt7915(&dev->mt76) ? MT7915_WTBL_SIZE : MT7916_WTBL_SIZE;
534}
535
536static inline u16 mt7915_eeprom_size(struct mt7915_dev *dev)
537{
538	return is_mt7915(&dev->mt76) ? MT7915_EEPROM_SIZE : MT7916_EEPROM_SIZE;
539}
540
541void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev, bool write_reg,
542				  u32 clear, u32 set);
543
544static inline void mt7915_irq_enable(struct mt7915_dev *dev, u32 mask)
545{
546	if (dev->hif2)
547		mt7915_dual_hif_set_irq_mask(dev, false, 0, mask);
548	else
549		mt76_set_irq_mask(&dev->mt76, 0, 0, mask);
550
551	tasklet_schedule(&dev->mt76.irq_tasklet);
552}
553
554static inline void mt7915_irq_disable(struct mt7915_dev *dev, u32 mask)
555{
556	if (dev->hif2)
557		mt7915_dual_hif_set_irq_mask(dev, true, mask, 0);
558	else
559		mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
560}
561
562void mt7915_memcpy_fromio(struct mt7915_dev *dev, void *buf, u32 offset,
563			  size_t len);
564
565void mt7915_mac_init(struct mt7915_dev *dev);
566u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw);
567bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask);
568void mt7915_mac_reset_counters(struct mt7915_phy *phy);
569void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy);
570void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool ext_phy);
571void mt7915_mac_enable_rtscts(struct mt7915_dev *dev,
572			      struct ieee80211_vif *vif, bool enable);
573void mt7915_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi,
574			   struct sk_buff *skb, struct mt76_wcid *wcid, int pid,
575			   struct ieee80211_key_conf *key,
576			   enum mt76_txq_id qid, u32 changed);
577void mt7915_mac_set_timing(struct mt7915_phy *phy);
578int mt7915_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
579		       struct ieee80211_sta *sta);
580int mt7915_mac_sta_event(struct mt76_dev *mdev, struct ieee80211_vif *vif,
581			 struct ieee80211_sta *sta, enum mt76_sta_event ev);
582void mt7915_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
583			   struct ieee80211_sta *sta);
584void mt7915_mac_work(struct work_struct *work);
585void mt7915_mac_reset_work(struct work_struct *work);
586void mt7915_mac_dump_work(struct work_struct *work);
587void mt7915_mac_sta_rc_work(struct work_struct *work);
588void mt7915_mac_update_stats(struct mt7915_phy *phy);
589void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev,
590				  struct mt7915_sta *msta,
591				  u8 flowid);
592void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw,
593			      struct ieee80211_sta *sta,
594			      struct ieee80211_twt_setup *twt);
595int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
596			  enum mt76_txq_id qid, struct mt76_wcid *wcid,
597			  struct ieee80211_sta *sta,
598			  struct mt76_tx_info *tx_info);
599void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
600			 struct sk_buff *skb, u32 *info);
601bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len);
602void mt7915_stats_work(struct work_struct *work);
603int mt76_dfs_start_rdd(struct mt7915_dev *dev, bool force);
604int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy);
605void mt7915_set_stream_he_caps(struct mt7915_phy *phy);
606void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy);
607void mt7915_update_channel(struct mt76_phy *mphy);
608int mt7915_mcu_muru_debug_set(struct mt7915_dev *dev, bool enable);
609int mt7915_mcu_muru_debug_get(struct mt7915_phy *phy);
610int mt7915_mcu_wed_enable_rx_stats(struct mt7915_dev *dev);
611int mt7915_init_debugfs(struct mt7915_phy *phy);
612void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int len);
613bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len);
614#ifdef CONFIG_MAC80211_DEBUGFS
615void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
616			    struct ieee80211_sta *sta, struct dentry *dir);
617#endif
618int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
619			 bool pci, int *irq);
620
621#endif