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mmio.c
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linux-6.19.14/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
1// SPDX-License-Identifier: BSD-3-Clause-Clear 2/* Copyright (C) 2020 MediaTek Inc. */ 3 4#include <linux/kernel.h> 5#include <linux/module.h> 6#include <linux/platform_device.h> 7#include <linux/rtnetlink.h> 8#include <linux/pci.h> 9 10#include "mt7915.h" 11#include "mac.h" 12#include "mcu.h" 13#include "../trace.h" 14#include "../dma.h" 15 16static bool wed_enable; 17module_param(wed_enable, bool, 0644); 18MODULE_PARM_DESC(wed_enable, "Enable Wireless Ethernet Dispatch support"); 19 20static const u32 mt7915_reg[] = { 21 [INT_SOURCE_CSR] = 0xd7010, 22 [INT_MASK_CSR] = 0xd7014, 23 [INT1_SOURCE_CSR] = 0xd7088, 24 [INT1_MASK_CSR] = 0xd708c, 25 [INT_MCU_CMD_SOURCE] = 0xd51f0, 26 [INT_MCU_CMD_EVENT] = 0x3108, 27 [WFDMA0_ADDR] = 0xd4000, 28 [WFDMA0_PCIE1_ADDR] = 0xd8000, 29 [WFDMA_EXT_CSR_ADDR] = 0xd7000, 30 [CBTOP1_PHY_END] = 0x77ffffff, 31 [INFRA_MCU_ADDR_END] = 0x7c3fffff, 32 [FW_ASSERT_STAT_ADDR] = 0x219848, 33 [FW_EXCEPT_TYPE_ADDR] = 0x21987c, 34 [FW_EXCEPT_COUNT_ADDR] = 0x219848, 35 [FW_CIRQ_COUNT_ADDR] = 0x216f94, 36 [FW_CIRQ_IDX_ADDR] = 0x216ef8, 37 [FW_CIRQ_LISR_ADDR] = 0x2170ac, 38 [FW_TASK_ID_ADDR] = 0x216f90, 39 [FW_TASK_IDX_ADDR] = 0x216f9c, 40 [FW_TASK_QID1_ADDR] = 0x219680, 41 [FW_TASK_QID2_ADDR] = 0x219760, 42 [FW_TASK_START_ADDR] = 0x219558, 43 [FW_TASK_END_ADDR] = 0x219554, 44 [FW_TASK_SIZE_ADDR] = 0x219560, 45 [FW_LAST_MSG_ID_ADDR] = 0x216f70, 46 [FW_EINT_INFO_ADDR] = 0x219818, 47 [FW_SCHED_INFO_ADDR] = 0x219828, 48 [SWDEF_BASE_ADDR] = 0x41f200, 49 [TXQ_WED_RING_BASE] = 0xd7300, 50 [RXQ_WED_RING_BASE] = 0xd7410, 51 [RXQ_WED_DATA_RING_BASE] = 0xd4500, 52}; 53 54static const u32 mt7916_reg[] = { 55 [INT_SOURCE_CSR] = 0xd4200, 56 [INT_MASK_CSR] = 0xd4204, 57 [INT1_SOURCE_CSR] = 0xd8200, 58 [INT1_MASK_CSR] = 0xd8204, 59 [INT_MCU_CMD_SOURCE] = 0xd41f0, 60 [INT_MCU_CMD_EVENT] = 0x2108, 61 [WFDMA0_ADDR] = 0xd4000, 62 [WFDMA0_PCIE1_ADDR] = 0xd8000, 63 [WFDMA_EXT_CSR_ADDR] = 0xd7000, 64 [CBTOP1_PHY_END] = 0x7fffffff, 65 [INFRA_MCU_ADDR_END] = 0x7c085fff, 66 [FW_ASSERT_STAT_ADDR] = 0x02204c14, 67 [FW_EXCEPT_TYPE_ADDR] = 0x022051a4, 68 [FW_EXCEPT_COUNT_ADDR] = 0x022050bc, 69 [FW_CIRQ_COUNT_ADDR] = 0x022001ac, 70 [FW_CIRQ_IDX_ADDR] = 0x02204f84, 71 [FW_CIRQ_LISR_ADDR] = 0x022050d0, 72 [FW_TASK_ID_ADDR] = 0x0220406c, 73 [FW_TASK_IDX_ADDR] = 0x0220500c, 74 [FW_TASK_QID1_ADDR] = 0x022028c8, 75 [FW_TASK_QID2_ADDR] = 0x02202a38, 76 [FW_TASK_START_ADDR] = 0x0220286c, 77 [FW_TASK_END_ADDR] = 0x02202870, 78 [FW_TASK_SIZE_ADDR] = 0x02202878, 79 [FW_LAST_MSG_ID_ADDR] = 0x02204fe8, 80 [FW_EINT_INFO_ADDR] = 0x0220525c, 81 [FW_SCHED_INFO_ADDR] = 0x0220516c, 82 [SWDEF_BASE_ADDR] = 0x411400, 83 [TXQ_WED_RING_BASE] = 0xd7300, 84 [RXQ_WED_RING_BASE] = 0xd7410, 85 [RXQ_WED_DATA_RING_BASE] = 0xd4540, 86}; 87 88static const u32 mt7986_reg[] = { 89 [INT_SOURCE_CSR] = 0x24200, 90 [INT_MASK_CSR] = 0x24204, 91 [INT1_SOURCE_CSR] = 0x28200, 92 [INT1_MASK_CSR] = 0x28204, 93 [INT_MCU_CMD_SOURCE] = 0x241f0, 94 [INT_MCU_CMD_EVENT] = 0x54000108, 95 [WFDMA0_ADDR] = 0x24000, 96 [WFDMA0_PCIE1_ADDR] = 0x28000, 97 [WFDMA_EXT_CSR_ADDR] = 0x27000, 98 [CBTOP1_PHY_END] = 0x7fffffff, 99 [INFRA_MCU_ADDR_END] = 0x7c085fff, 100 [FW_ASSERT_STAT_ADDR] = 0x02204b54, 101 [FW_EXCEPT_TYPE_ADDR] = 0x022050dc, 102 [FW_EXCEPT_COUNT_ADDR] = 0x02204ffc, 103 [FW_CIRQ_COUNT_ADDR] = 0x022001ac, 104 [FW_CIRQ_IDX_ADDR] = 0x02204ec4, 105 [FW_CIRQ_LISR_ADDR] = 0x02205010, 106 [FW_TASK_ID_ADDR] = 0x02204fac, 107 [FW_TASK_IDX_ADDR] = 0x02204f4c, 108 [FW_TASK_QID1_ADDR] = 0x02202814, 109 [FW_TASK_QID2_ADDR] = 0x02202984, 110 [FW_TASK_START_ADDR] = 0x022027b8, 111 [FW_TASK_END_ADDR] = 0x022027bc, 112 [FW_TASK_SIZE_ADDR] = 0x022027c4, 113 [FW_LAST_MSG_ID_ADDR] = 0x02204f28, 114 [FW_EINT_INFO_ADDR] = 0x02205194, 115 [FW_SCHED_INFO_ADDR] = 0x022051a4, 116 [SWDEF_BASE_ADDR] = 0x411400, 117 [TXQ_WED_RING_BASE] = 0x24420, 118 [RXQ_WED_RING_BASE] = 0x24520, 119 [RXQ_WED_DATA_RING_BASE] = 0x24540, 120}; 121 122static const u32 mt7915_offs[] = { 123 [TMAC_CDTR] = 0x090, 124 [TMAC_ODTR] = 0x094, 125 [TMAC_ATCR] = 0x098, 126 [TMAC_TRCR0] = 0x09c, 127 [TMAC_ICR0] = 0x0a4, 128 [TMAC_ICR1] = 0x0b4, 129 [TMAC_CTCR0] = 0x0f4, 130 [TMAC_TFCR0] = 0x1e0, 131 [MDP_BNRCFR0] = 0x070, 132 [MDP_BNRCFR1] = 0x074, 133 [ARB_DRNGR0] = 0x194, 134 [ARB_SCR] = 0x080, 135 [RMAC_MIB_AIRTIME14] = 0x3b8, 136 [AGG_AWSCR0] = 0x05c, 137 [AGG_PCR0] = 0x06c, 138 [AGG_ACR0] = 0x084, 139 [AGG_ACR4] = 0x08c, 140 [AGG_MRCR] = 0x098, 141 [AGG_ATCR0] = 0x0ec, 142 [AGG_ATCR1] = 0x0f0, 143 [AGG_ATCR3] = 0x0f4, 144 [LPON_UTTR0] = 0x080, 145 [LPON_UTTR1] = 0x084, 146 [LPON_FRCR] = 0x314, 147 [MIB_SDR3] = 0x014, 148 [MIB_SDR4] = 0x018, 149 [MIB_SDR5] = 0x01c, 150 [MIB_SDR7] = 0x024, 151 [MIB_SDR8] = 0x028, 152 [MIB_SDR9] = 0x02c, 153 [MIB_SDR10] = 0x030, 154 [MIB_SDR11] = 0x034, 155 [MIB_SDR12] = 0x038, 156 [MIB_SDR13] = 0x03c, 157 [MIB_SDR14] = 0x040, 158 [MIB_SDR15] = 0x044, 159 [MIB_SDR16] = 0x048, 160 [MIB_SDR17] = 0x04c, 161 [MIB_SDR18] = 0x050, 162 [MIB_SDR19] = 0x054, 163 [MIB_SDR20] = 0x058, 164 [MIB_SDR21] = 0x05c, 165 [MIB_SDR22] = 0x060, 166 [MIB_SDR23] = 0x064, 167 [MIB_SDR24] = 0x068, 168 [MIB_SDR25] = 0x06c, 169 [MIB_SDR27] = 0x074, 170 [MIB_SDR28] = 0x078, 171 [MIB_SDR29] = 0x07c, 172 [MIB_SDRVEC] = 0x080, 173 [MIB_SDR31] = 0x084, 174 [MIB_SDR32] = 0x088, 175 [MIB_SDRMUBF] = 0x090, 176 [MIB_DR8] = 0x0c0, 177 [MIB_DR9] = 0x0c4, 178 [MIB_DR11] = 0x0cc, 179 [MIB_MB_SDR0] = 0x100, 180 [MIB_MB_SDR1] = 0x104, 181 [TX_AGG_CNT] = 0x0a8, 182 [TX_AGG_CNT2] = 0x164, 183 [MIB_ARNG] = 0x4b8, 184 [WTBLON_TOP_WDUCR] = 0x0, 185 [WTBL_UPDATE] = 0x030, 186 [PLE_FL_Q_EMPTY] = 0x0b0, 187 [PLE_FL_Q_CTRL] = 0x1b0, 188 [PLE_AC_QEMPTY] = 0x500, 189 [PLE_FREEPG_CNT] = 0x100, 190 [PLE_FREEPG_HEAD_TAIL] = 0x104, 191 [PLE_PG_HIF_GROUP] = 0x110, 192 [PLE_HIF_PG_INFO] = 0x114, 193 [AC_OFFSET] = 0x040, 194 [ETBF_PAR_RPT0] = 0x068, 195}; 196 197static const u32 mt7916_offs[] = { 198 [TMAC_CDTR] = 0x0c8, 199 [TMAC_ODTR] = 0x0cc, 200 [TMAC_ATCR] = 0x00c, 201 [TMAC_TRCR0] = 0x010, 202 [TMAC_ICR0] = 0x014, 203 [TMAC_ICR1] = 0x018, 204 [TMAC_CTCR0] = 0x114, 205 [TMAC_TFCR0] = 0x0e4, 206 [MDP_BNRCFR0] = 0x090, 207 [MDP_BNRCFR1] = 0x094, 208 [ARB_DRNGR0] = 0x1e0, 209 [ARB_SCR] = 0x000, 210 [RMAC_MIB_AIRTIME14] = 0x0398, 211 [AGG_AWSCR0] = 0x030, 212 [AGG_PCR0] = 0x040, 213 [AGG_ACR0] = 0x054, 214 [AGG_ACR4] = 0x05c, 215 [AGG_MRCR] = 0x068, 216 [AGG_ATCR0] = 0x1a4, 217 [AGG_ATCR1] = 0x1a8, 218 [AGG_ATCR3] = 0x080, 219 [LPON_UTTR0] = 0x360, 220 [LPON_UTTR1] = 0x364, 221 [LPON_FRCR] = 0x37c, 222 [MIB_SDR3] = 0x698, 223 [MIB_SDR4] = 0x788, 224 [MIB_SDR5] = 0x780, 225 [MIB_SDR7] = 0x5a8, 226 [MIB_SDR8] = 0x78c, 227 [MIB_SDR9] = 0x024, 228 [MIB_SDR10] = 0x76c, 229 [MIB_SDR11] = 0x790, 230 [MIB_SDR12] = 0x558, 231 [MIB_SDR13] = 0x560, 232 [MIB_SDR14] = 0x564, 233 [MIB_SDR15] = 0x568, 234 [MIB_SDR16] = 0x7fc, 235 [MIB_SDR17] = 0x800, 236 [MIB_SDR18] = 0x030, 237 [MIB_SDR19] = 0x5ac, 238 [MIB_SDR20] = 0x5b0, 239 [MIB_SDR21] = 0x5b4, 240 [MIB_SDR22] = 0x770, 241 [MIB_SDR23] = 0x774, 242 [MIB_SDR24] = 0x778, 243 [MIB_SDR25] = 0x77c, 244 [MIB_SDR27] = 0x080, 245 [MIB_SDR28] = 0x084, 246 [MIB_SDR29] = 0x650, 247 [MIB_SDRVEC] = 0x5a8, 248 [MIB_SDR31] = 0x55c, 249 [MIB_SDR32] = 0x7a8, 250 [MIB_SDRMUBF] = 0x7ac, 251 [MIB_DR8] = 0x56c, 252 [MIB_DR9] = 0x570, 253 [MIB_DR11] = 0x574, 254 [MIB_MB_SDR0] = 0x688, 255 [MIB_MB_SDR1] = 0x690, 256 [TX_AGG_CNT] = 0x7dc, 257 [TX_AGG_CNT2] = 0x7ec, 258 [MIB_ARNG] = 0x0b0, 259 [WTBLON_TOP_WDUCR] = 0x200, 260 [WTBL_UPDATE] = 0x230, 261 [PLE_FL_Q_EMPTY] = 0x360, 262 [PLE_FL_Q_CTRL] = 0x3e0, 263 [PLE_AC_QEMPTY] = 0x600, 264 [PLE_FREEPG_CNT] = 0x380, 265 [PLE_FREEPG_HEAD_TAIL] = 0x384, 266 [PLE_PG_HIF_GROUP] = 0x00c, 267 [PLE_HIF_PG_INFO] = 0x388, 268 [AC_OFFSET] = 0x080, 269 [ETBF_PAR_RPT0] = 0x100, 270}; 271 272static const struct mt76_connac_reg_map mt7915_reg_map[] = { 273 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 274 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure regs) */ 275 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */ 276 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */ 277 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */ 278 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 279 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */ 280 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 281 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */ 282 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 283 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 284 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */ 285 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */ 286 { 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */ 287 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */ 288 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */ 289 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 290 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 291 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 292 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 293 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 294 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 295 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 296 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 297 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 298 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 299 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 300 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 301 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 302 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 303 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 304 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 305 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 306 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 307 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 308 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 309 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 310 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 311 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 312 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 313 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 314 { 0x0, 0x0, 0x0 }, /* imply end of search */ 315}; 316 317static const struct mt76_connac_reg_map mt7916_reg_map[] = { 318 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */ 319 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */ 320 { 0x56000000, 0x04000, 0x01000 }, /* WFDMA_2 (Reserved) */ 321 { 0x57000000, 0x05000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */ 322 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */ 323 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */ 324 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */ 325 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */ 326 { 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */ 327 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 328 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 329 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 330 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 331 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 332 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 333 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */ 334 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 335 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */ 336 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 337 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 338 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 339 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 340 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 341 { 0x820ca000, 0x26000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */ 342 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 343 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 344 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure cr) */ 345 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 346 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 347 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 348 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 349 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 350 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 351 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 352 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 353 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 354 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 355 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 356 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 357 { 0x820c4000, 0xa8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */ 358 { 0x820b0000, 0xae000, 0x01000 }, /* [APB2] WFSYS_ON */ 359 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 360 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 361 { 0x0, 0x0, 0x0 }, /* imply end of search */ 362}; 363 364static const struct mt76_connac_reg_map mt7986_reg_map[] = { 365 { 0x54000000, 0x402000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */ 366 { 0x55000000, 0x403000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */ 367 { 0x56000000, 0x404000, 0x01000 }, /* WFDMA_2 (Reserved) */ 368 { 0x57000000, 0x405000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */ 369 { 0x58000000, 0x406000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */ 370 { 0x59000000, 0x407000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */ 371 { 0x820c0000, 0x408000, 0x04000 }, /* WF_UMAC_TOP (PLE) */ 372 { 0x820c8000, 0x40c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */ 373 { 0x820cc000, 0x40e000, 0x02000 }, /* WF_UMAC_TOP (PP) */ 374 { 0x820e0000, 0x420000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 375 { 0x820e1000, 0x420400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 376 { 0x820e2000, 0x420800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 377 { 0x820e3000, 0x420c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 378 { 0x820e4000, 0x421000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 379 { 0x820e5000, 0x421400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 380 { 0x820ce000, 0x421c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */ 381 { 0x820e7000, 0x421e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 382 { 0x820cf000, 0x422000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */ 383 { 0x820e9000, 0x423400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 384 { 0x820ea000, 0x424000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 385 { 0x820eb000, 0x424200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 386 { 0x820ec000, 0x424600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 387 { 0x820ed000, 0x424800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 388 { 0x820ca000, 0x426000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */ 389 { 0x820d0000, 0x430000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 390 { 0x00400000, 0x480000, 0x10000 }, /* WF_MCU_SYSRAM */ 391 { 0x00410000, 0x490000, 0x10000 }, /* WF_MCU_SYSRAM */ 392 { 0x820f0000, 0x4a0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 393 { 0x820f1000, 0x4a0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 394 { 0x820f2000, 0x4a0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 395 { 0x820f3000, 0x4a0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 396 { 0x820f4000, 0x4a1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 397 { 0x820f5000, 0x4a1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 398 { 0x820f7000, 0x4a1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 399 { 0x820f9000, 0x4a3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 400 { 0x820fa000, 0x4a4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 401 { 0x820fb000, 0x4a4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 402 { 0x820fc000, 0x4a4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 403 { 0x820fd000, 0x4a4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 404 { 0x820c4000, 0x4a8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */ 405 { 0x820b0000, 0x4ae000, 0x01000 }, /* [APB2] WFSYS_ON */ 406 { 0x80020000, 0x4b0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 407 { 0x81020000, 0x4c0000, 0x10000 }, /* WF_TOP_MISC_ON */ 408 { 0x89000000, 0x4d0000, 0x01000 }, /* WF_MCU_CFG_ON */ 409 { 0x89010000, 0x4d1000, 0x01000 }, /* WF_MCU_CIRQ */ 410 { 0x89020000, 0x4d2000, 0x01000 }, /* WF_MCU_GPT */ 411 { 0x89030000, 0x4d3000, 0x01000 }, /* WF_MCU_WDT */ 412 { 0x80010000, 0x4d4000, 0x01000 }, /* WF_AXIDMA */ 413 { 0x0, 0x0, 0x0 }, /* imply end of search */ 414}; 415 416static u32 mt7915_reg_map_l1(struct mt7915_dev *dev, u32 addr) 417{ 418 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr); 419 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr); 420 u32 l1_remap; 421 422 if (is_mt798x(&dev->mt76)) 423 return MT_CONN_INFRA_OFFSET(addr); 424 425 l1_remap = is_mt7915(&dev->mt76) ? 426 MT_HIF_REMAP_L1 : MT_HIF_REMAP_L1_MT7916; 427 428 dev->bus_ops->rmw(&dev->mt76, l1_remap, 429 MT_HIF_REMAP_L1_MASK, 430 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base)); 431 /* use read to push write */ 432 dev->bus_ops->rr(&dev->mt76, l1_remap); 433 434 return MT_HIF_REMAP_BASE_L1 + offset; 435} 436 437static u32 mt7915_reg_map_l2(struct mt7915_dev *dev, u32 addr) 438{ 439 u32 offset, base; 440 441 if (is_mt7915(&dev->mt76)) { 442 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr); 443 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr); 444 445 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2, 446 MT_HIF_REMAP_L2_MASK, 447 FIELD_PREP(MT_HIF_REMAP_L2_MASK, base)); 448 449 /* use read to push write */ 450 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2); 451 } else { 452 u32 ofs = is_mt798x(&dev->mt76) ? 0x400000 : 0; 453 454 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET_MT7916, addr); 455 base = FIELD_GET(MT_HIF_REMAP_L2_BASE_MT7916, addr); 456 457 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs, 458 MT_HIF_REMAP_L2_MASK_MT7916, 459 FIELD_PREP(MT_HIF_REMAP_L2_MASK_MT7916, base)); 460 461 /* use read to push write */ 462 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs); 463 464 offset += (MT_HIF_REMAP_BASE_L2_MT7916 + ofs); 465 } 466 467 return offset; 468} 469 470static u32 __mt7915_reg_addr(struct mt7915_dev *dev, u32 addr) 471{ 472 int i; 473 474 if (addr < 0x100000) 475 return addr; 476 477 if (!dev->reg.map) { 478 dev_err(dev->mt76.dev, "err: reg_map is null\n"); 479 return addr; 480 } 481 482 for (i = 0; i < dev->reg.map_size; i++) { 483 u32 ofs; 484 485 if (addr < dev->reg.map[i].phys) 486 continue; 487 488 ofs = addr - dev->reg.map[i].phys; 489 if (ofs >= dev->reg.map[i].size) 490 continue; 491 492 return dev->reg.map[i].maps + ofs; 493 } 494 495 return 0; 496} 497 498static u32 __mt7915_reg_remap_addr(struct mt7915_dev *dev, u32 addr) 499{ 500 if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) || 501 (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) || 502 (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END)) 503 return mt7915_reg_map_l1(dev, addr); 504 505 if (dev_is_pci(dev->mt76.dev) && 506 ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) || 507 addr >= MT_CBTOP2_PHY_START)) 508 return mt7915_reg_map_l1(dev, addr); 509 510 /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */ 511 if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) { 512 addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE; 513 return mt7915_reg_map_l1(dev, addr); 514 } 515 516 return mt7915_reg_map_l2(dev, addr); 517} 518 519void mt7915_memcpy_fromio(struct mt7915_dev *dev, void *buf, u32 offset, 520 size_t len) 521{ 522 u32 addr = __mt7915_reg_addr(dev, offset); 523 524 if (addr) { 525 memcpy_fromio(buf, dev->mt76.mmio.regs + addr, len); 526 return; 527 } 528 529 spin_lock_bh(&dev->reg_lock); 530 memcpy_fromio(buf, dev->mt76.mmio.regs + 531 __mt7915_reg_remap_addr(dev, offset), len); 532 spin_unlock_bh(&dev->reg_lock); 533} 534 535static u32 mt7915_rr(struct mt76_dev *mdev, u32 offset) 536{ 537 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 538 u32 addr = __mt7915_reg_addr(dev, offset), val; 539 540 if (addr) 541 return dev->bus_ops->rr(mdev, addr); 542 543 spin_lock_bh(&dev->reg_lock); 544 val = dev->bus_ops->rr(mdev, __mt7915_reg_remap_addr(dev, offset)); 545 spin_unlock_bh(&dev->reg_lock); 546 547 return val; 548} 549 550static void mt7915_wr(struct mt76_dev *mdev, u32 offset, u32 val) 551{ 552 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 553 u32 addr = __mt7915_reg_addr(dev, offset); 554 555 if (addr) { 556 dev->bus_ops->wr(mdev, addr, val); 557 return; 558 } 559 560 spin_lock_bh(&dev->reg_lock); 561 dev->bus_ops->wr(mdev, __mt7915_reg_remap_addr(dev, offset), val); 562 spin_unlock_bh(&dev->reg_lock); 563} 564 565static u32 mt7915_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 566{ 567 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 568 u32 addr = __mt7915_reg_addr(dev, offset); 569 570 if (addr) 571 return dev->bus_ops->rmw(mdev, addr, mask, val); 572 573 spin_lock_bh(&dev->reg_lock); 574 val = dev->bus_ops->rmw(mdev, __mt7915_reg_remap_addr(dev, offset), mask, val); 575 spin_unlock_bh(&dev->reg_lock); 576 577 return val; 578} 579 580#ifdef CONFIG_NET_MEDIATEK_SOC_WED 581static void mt7915_mmio_wed_update_rx_stats(struct mtk_wed_device *wed, 582 struct mtk_wed_wo_rx_stats *stats) 583{ 584 int idx = le16_to_cpu(stats->wlan_idx); 585 struct mt7915_dev *dev; 586 struct mt76_wcid *wcid; 587 588 dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed); 589 590 rcu_read_lock(); 591 592 wcid = mt76_wcid_ptr(dev, idx); 593 if (wcid) { 594 wcid->stats.rx_bytes += le32_to_cpu(stats->rx_byte_cnt); 595 wcid->stats.rx_packets += le32_to_cpu(stats->rx_pkt_cnt); 596 wcid->stats.rx_errors += le32_to_cpu(stats->rx_err_cnt); 597 wcid->stats.rx_drops += le32_to_cpu(stats->rx_drop_cnt); 598 } 599 600 rcu_read_unlock(); 601} 602 603static int mt7915_mmio_wed_reset(struct mtk_wed_device *wed) 604{ 605 struct mt76_dev *mdev = container_of(wed, struct mt76_dev, mmio.wed); 606 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 607 struct mt76_phy *mphy = &dev->mphy; 608 int ret; 609 610 ASSERT_RTNL(); 611 612 if (test_and_set_bit(MT76_STATE_WED_RESET, &mphy->state)) 613 return -EBUSY; 614 615 ret = mt7915_mcu_set_ser(dev, SER_RECOVER, SER_SET_RECOVER_L1, 616 mphy->band_idx); 617 if (ret) 618 goto out; 619 620 rtnl_unlock(); 621 if (!wait_for_completion_timeout(&mdev->mmio.wed_reset, 20 * HZ)) { 622 dev_err(mdev->dev, "wed reset timeout\n"); 623 ret = -ETIMEDOUT; 624 } 625 rtnl_lock(); 626out: 627 clear_bit(MT76_STATE_WED_RESET, &mphy->state); 628 629 return ret; 630} 631#endif 632 633int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr, 634 bool pci, int *irq) 635{ 636#ifdef CONFIG_NET_MEDIATEK_SOC_WED 637 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 638 int ret; 639 640 if (!wed_enable) 641 return 0; 642 643 if (pci) { 644 struct pci_dev *pci_dev = pdev_ptr; 645 646 wed->wlan.pci_dev = pci_dev; 647 wed->wlan.bus_type = MTK_WED_BUS_PCIE; 648 wed->wlan.base = devm_ioremap(dev->mt76.dev, 649 pci_resource_start(pci_dev, 0), 650 pci_resource_len(pci_dev, 0)); 651 if (!wed->wlan.base) 652 return -ENOMEM; 653 654 wed->wlan.phy_base = pci_resource_start(pci_dev, 0); 655 wed->wlan.wpdma_int = pci_resource_start(pci_dev, 0) + 656 MT_INT_WED_SOURCE_CSR; 657 wed->wlan.wpdma_mask = pci_resource_start(pci_dev, 0) + 658 MT_INT_WED_MASK_CSR; 659 wed->wlan.wpdma_phys = pci_resource_start(pci_dev, 0) + 660 MT_WFDMA_EXT_CSR_BASE; 661 wed->wlan.wpdma_tx = pci_resource_start(pci_dev, 0) + 662 MT_TXQ_WED_RING_BASE; 663 wed->wlan.wpdma_txfree = pci_resource_start(pci_dev, 0) + 664 MT_RXQ_WED_RING_BASE; 665 wed->wlan.wpdma_rx_glo = pci_resource_start(pci_dev, 0) + 666 MT_WPDMA_GLO_CFG; 667 wed->wlan.wpdma_rx[0] = pci_resource_start(pci_dev, 0) + 668 MT_RXQ_WED_DATA_RING_BASE; 669 } else { 670 struct platform_device *plat_dev = pdev_ptr; 671 struct resource *res; 672 673 res = platform_get_resource(plat_dev, IORESOURCE_MEM, 0); 674 if (!res) 675 return 0; 676 677 wed->wlan.platform_dev = plat_dev; 678 wed->wlan.bus_type = MTK_WED_BUS_AXI; 679 wed->wlan.base = devm_ioremap(dev->mt76.dev, res->start, 680 resource_size(res)); 681 if (!wed->wlan.base) 682 return -ENOMEM; 683 684 wed->wlan.phy_base = res->start; 685 wed->wlan.wpdma_int = res->start + MT_INT_SOURCE_CSR; 686 wed->wlan.wpdma_mask = res->start + MT_INT_MASK_CSR; 687 wed->wlan.wpdma_tx = res->start + MT_TXQ_WED_RING_BASE; 688 wed->wlan.wpdma_txfree = res->start + MT_RXQ_WED_RING_BASE; 689 wed->wlan.wpdma_rx_glo = res->start + MT_WPDMA_GLO_CFG; 690 wed->wlan.wpdma_rx[0] = res->start + MT_RXQ_WED_DATA_RING_BASE; 691 } 692 wed->wlan.nbuf = MT7915_HW_TOKEN_SIZE; 693 wed->wlan.tx_tbit[0] = is_mt7915(&dev->mt76) ? 4 : 30; 694 wed->wlan.tx_tbit[1] = is_mt7915(&dev->mt76) ? 5 : 31; 695 wed->wlan.txfree_tbit = is_mt798x(&dev->mt76) ? 2 : 1; 696 wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf; 697 wed->wlan.wcid_512 = !is_mt7915(&dev->mt76); 698 699 wed->wlan.rx_nbuf = 65536; 700 wed->wlan.rx_npkt = MT7915_WED_RX_TOKEN_SIZE; 701 wed->wlan.rx_size = SKB_WITH_OVERHEAD(MT_RX_BUF_SIZE); 702 if (is_mt7915(&dev->mt76)) { 703 wed->wlan.rx_tbit[0] = 16; 704 wed->wlan.rx_tbit[1] = 17; 705 } else if (is_mt798x(&dev->mt76)) { 706 wed->wlan.rx_tbit[0] = 22; 707 wed->wlan.rx_tbit[1] = 23; 708 } else { 709 wed->wlan.rx_tbit[0] = 18; 710 wed->wlan.rx_tbit[1] = 19; 711 } 712 713 wed->wlan.init_buf = mt7915_wed_init_buf; 714 wed->wlan.offload_enable = mt76_wed_offload_enable; 715 wed->wlan.offload_disable = mt76_wed_offload_disable; 716 wed->wlan.init_rx_buf = mt76_wed_init_rx_buf; 717 wed->wlan.release_rx_buf = mt76_wed_release_rx_buf; 718 wed->wlan.update_wo_rx_stats = mt7915_mmio_wed_update_rx_stats; 719 wed->wlan.reset = mt7915_mmio_wed_reset; 720 wed->wlan.reset_complete = mt76_wed_reset_complete; 721 722 dev->mt76.rx_token_size = wed->wlan.rx_npkt; 723 724 if (mtk_wed_device_attach(wed)) 725 return 0; 726 727 *irq = wed->irq; 728 dev->mt76.dma_dev = wed->dev; 729 730 ret = dma_set_mask(wed->dev, DMA_BIT_MASK(32)); 731 if (ret) 732 return ret; 733 734 return 1; 735#else 736 return 0; 737#endif 738} 739 740static int mt7915_mmio_init(struct mt76_dev *mdev, 741 void __iomem *mem_base, 742 u32 device_id) 743{ 744 struct mt76_bus_ops *bus_ops; 745 struct mt7915_dev *dev; 746 747 dev = container_of(mdev, struct mt7915_dev, mt76); 748 mt76_mmio_init(&dev->mt76, mem_base); 749 spin_lock_init(&dev->reg_lock); 750 751 switch (device_id) { 752 case 0x7915: 753 dev->reg.reg_rev = mt7915_reg; 754 dev->reg.offs_rev = mt7915_offs; 755 dev->reg.map = mt7915_reg_map; 756 dev->reg.map_size = ARRAY_SIZE(mt7915_reg_map); 757 break; 758 case 0x7906: 759 dev->reg.reg_rev = mt7916_reg; 760 dev->reg.offs_rev = mt7916_offs; 761 dev->reg.map = mt7916_reg_map; 762 dev->reg.map_size = ARRAY_SIZE(mt7916_reg_map); 763 break; 764 case 0x7981: 765 case 0x7986: 766 dev->reg.reg_rev = mt7986_reg; 767 dev->reg.offs_rev = mt7916_offs; 768 dev->reg.map = mt7986_reg_map; 769 dev->reg.map_size = ARRAY_SIZE(mt7986_reg_map); 770 break; 771 default: 772 return -EINVAL; 773 } 774 775 dev->bus_ops = dev->mt76.bus; 776 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 777 GFP_KERNEL); 778 if (!bus_ops) 779 return -ENOMEM; 780 781 bus_ops->rr = mt7915_rr; 782 bus_ops->wr = mt7915_wr; 783 bus_ops->rmw = mt7915_rmw; 784 dev->mt76.bus = bus_ops; 785 786 mdev->rev = (device_id << 16) | 787 (mt76_rr(dev, MT_HW_REV) & 0xff); 788 dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 789 790 return 0; 791} 792 793void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev, 794 bool write_reg, 795 u32 clear, u32 set) 796{ 797 struct mt76_dev *mdev = &dev->mt76; 798 unsigned long flags; 799 800 spin_lock_irqsave(&mdev->mmio.irq_lock, flags); 801 802 mdev->mmio.irqmask &= ~clear; 803 mdev->mmio.irqmask |= set; 804 805 if (write_reg) { 806 if (mtk_wed_device_active(&mdev->mmio.wed)) 807 mtk_wed_device_irq_set_mask(&mdev->mmio.wed, 808 mdev->mmio.irqmask); 809 else 810 mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask); 811 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask); 812 } 813 814 spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags); 815} 816 817static void mt7915_rx_poll_complete(struct mt76_dev *mdev, 818 enum mt76_rxq_id q) 819{ 820 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 821 822 mt7915_irq_enable(dev, MT_INT_RX(q)); 823} 824 825/* TODO: support 2/4/6/8 MSI-X vectors */ 826static void mt7915_irq_tasklet(struct tasklet_struct *t) 827{ 828 struct mt7915_dev *dev = from_tasklet(dev, t, mt76.irq_tasklet); 829 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 830 u32 intr, intr1, mask; 831 832 if (mtk_wed_device_active(wed)) { 833 mtk_wed_device_irq_set_mask(wed, 0); 834 if (dev->hif2) 835 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 836 intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask); 837 } else { 838 mt76_wr(dev, MT_INT_MASK_CSR, 0); 839 if (dev->hif2) 840 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 841 842 intr = mt76_rr(dev, MT_INT_SOURCE_CSR); 843 intr &= dev->mt76.mmio.irqmask; 844 mt76_wr(dev, MT_INT_SOURCE_CSR, intr); 845 } 846 847 if (dev->hif2) { 848 intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR); 849 intr1 &= dev->mt76.mmio.irqmask; 850 mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1); 851 852 intr |= intr1; 853 } 854 855 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); 856 857 mask = intr & MT_INT_RX_DONE_ALL; 858 if (intr & MT_INT_TX_DONE_MCU) 859 mask |= MT_INT_TX_DONE_MCU; 860 861 mt7915_irq_disable(dev, mask); 862 863 if (intr & MT_INT_TX_DONE_MCU) 864 napi_schedule(&dev->mt76.tx_napi); 865 866 if (intr & MT_INT_RX(MT_RXQ_MAIN)) 867 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]); 868 869 if (intr & MT_INT_RX(MT_RXQ_BAND1)) 870 napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1]); 871 872 if (intr & MT_INT_RX(MT_RXQ_MCU)) 873 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]); 874 875 if (intr & MT_INT_RX(MT_RXQ_MCU_WA)) 876 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]); 877 878 if (!is_mt7915(&dev->mt76) && 879 (intr & MT_INT_RX(MT_RXQ_MAIN_WA))) 880 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN_WA]); 881 882 if (intr & MT_INT_RX(MT_RXQ_BAND1_WA)) 883 napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1_WA]); 884 885 if (intr & MT_INT_MCU_CMD) { 886 u32 val = mt76_rr(dev, MT_MCU_CMD); 887 888 mt76_wr(dev, MT_MCU_CMD, val); 889 if (val & (MT_MCU_CMD_ERROR_MASK | MT_MCU_CMD_WDT_MASK)) { 890 dev->recovery.state = val; 891 mt7915_reset(dev); 892 } 893 } 894} 895 896irqreturn_t mt7915_irq_handler(int irq, void *dev_instance) 897{ 898 struct mt7915_dev *dev = dev_instance; 899 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 900 901 if (mtk_wed_device_active(wed)) 902 mtk_wed_device_irq_set_mask(wed, 0); 903 else 904 mt76_wr(dev, MT_INT_MASK_CSR, 0); 905 906 if (dev->hif2) 907 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 908 909 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) 910 return IRQ_NONE; 911 912 tasklet_schedule(&dev->mt76.irq_tasklet); 913 914 return IRQ_HANDLED; 915} 916 917struct mt7915_dev *mt7915_mmio_probe(struct device *pdev, 918 void __iomem *mem_base, u32 device_id) 919{ 920 static const struct mt76_driver_ops drv_ops = { 921 /* txwi_size = txd size + txp size */ 922 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_fw_txp), 923 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ | 924 MT_DRV_AMSDU_OFFLOAD, 925 .survey_flags = SURVEY_INFO_TIME_TX | 926 SURVEY_INFO_TIME_RX | 927 SURVEY_INFO_TIME_BSS_RX, 928 .token_size = MT7915_TOKEN_SIZE, 929 .tx_prepare_skb = mt7915_tx_prepare_skb, 930 .tx_complete_skb = mt76_connac_tx_complete_skb, 931 .rx_skb = mt7915_queue_rx_skb, 932 .rx_check = mt7915_rx_check, 933 .rx_poll_complete = mt7915_rx_poll_complete, 934 .sta_add = mt7915_mac_sta_add, 935 .sta_event = mt7915_mac_sta_event, 936 .sta_remove = mt7915_mac_sta_remove, 937 .update_survey = mt7915_update_channel, 938 .set_channel = mt7915_set_channel, 939 }; 940 struct mt7915_dev *dev; 941 struct mt76_dev *mdev; 942 int ret; 943 944 mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7915_ops, &drv_ops); 945 if (!mdev) 946 return ERR_PTR(-ENOMEM); 947 948 dev = container_of(mdev, struct mt7915_dev, mt76); 949 950 ret = mt7915_mmio_init(mdev, mem_base, device_id); 951 if (ret) 952 goto error; 953 954 tasklet_setup(&mdev->irq_tasklet, mt7915_irq_tasklet); 955 956 return dev; 957 958error: 959 mt76_free_device(&dev->mt76); 960 961 return ERR_PTR(ret); 962} 963 964static int __init mt7915_init(void) 965{ 966 int ret; 967 968 ret = pci_register_driver(&mt7915_hif_driver); 969 if (ret) 970 return ret; 971 972 ret = pci_register_driver(&mt7915_pci_driver); 973 if (ret) 974 goto error_pci; 975 976 if (IS_ENABLED(CONFIG_MT798X_WMAC)) { 977 ret = platform_driver_register(&mt798x_wmac_driver); 978 if (ret) 979 goto error_wmac; 980 } 981 982 return 0; 983 984error_wmac: 985 pci_unregister_driver(&mt7915_pci_driver); 986error_pci: 987 pci_unregister_driver(&mt7915_hif_driver); 988 989 return ret; 990} 991 992static void __exit mt7915_exit(void) 993{ 994 if (IS_ENABLED(CONFIG_MT798X_WMAC)) 995 platform_driver_unregister(&mt798x_wmac_driver); 996 997 pci_unregister_driver(&mt7915_pci_driver); 998 pci_unregister_driver(&mt7915_hif_driver); 999} 1000 1001module_init(mt7915_init); 1002module_exit(mt7915_exit); 1003MODULE_DESCRIPTION("MediaTek MT7915E MMIO helpers"); 1004MODULE_LICENSE("Dual BSD/GPL");
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