mt76x02_mmio.c

  1// SPDX-License-Identifier: BSD-3-Clause-Clear
  2/*
  3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
  4 * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
  5 */
  6
  7#include <linux/kernel.h>
  8#include <linux/irq.h>
  9
 10#include "mt76x02.h"
 11#include "mt76x02_mcu.h"
 12#include "trace.h"
 13
 14static void mt76x02_pre_tbtt_tasklet(struct tasklet_struct *t)
 15{
 16	struct mt76x02_dev *dev = from_tasklet(dev, t, mt76.pre_tbtt_tasklet);
 17	struct mt76_dev *mdev = &dev->mt76;
 18	struct mt76_queue *q = dev->mphy.q_tx[MT_TXQ_PSD];
 19	struct beacon_bc_data data = {
 20		.dev = dev,
 21	};
 22	struct sk_buff *skb;
 23	int i;
 24
 25	if (dev->mphy.offchannel)
 26		return;
 27
 28	__skb_queue_head_init(&data.q);
 29
 30	mt76x02_resync_beacon_timer(dev);
 31
 32	/* Prevent corrupt transmissions during update */
 33	mt76_set(dev, MT_BCN_BYPASS_MASK, 0xffff);
 34	dev->beacon_data_count = 0;
 35
 36	ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev),
 37		IEEE80211_IFACE_ITER_RESUME_ALL,
 38		mt76x02_update_beacon_iter, &data);
 39
 40	while ((skb = __skb_dequeue(&data.q)) != NULL)
 41		mt76x02_mac_set_beacon(dev, skb);
 42
 43	mt76_wr(dev, MT_BCN_BYPASS_MASK,
 44		0xff00 | ~(0xff00 >> dev->beacon_data_count));
 45
 46	mt76_csa_check(mdev);
 47
 48	if (mdev->csa_complete)
 49		return;
 50
 51	mt76x02_enqueue_buffered_bc(dev, &data, 8);
 52
 53	if (!skb_queue_len(&data.q))
 54		return;
 55
 56	for (i = 0; i < ARRAY_SIZE(data.tail); i++) {
 57		if (!data.tail[i])
 58			continue;
 59
 60		mt76_skb_set_moredata(data.tail[i], false);
 61	}
 62
 63	spin_lock(&q->lock);
 64	while ((skb = __skb_dequeue(&data.q)) != NULL) {
 65		struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
 66		struct ieee80211_vif *vif = info->control.vif;
 67		struct mt76x02_vif *mvif = (struct mt76x02_vif *)vif->drv_priv;
 68
 69		mt76_tx_queue_skb(dev, q, MT_TXQ_PSD, skb, &mvif->group_wcid,
 70				  NULL);
 71	}
 72	spin_unlock(&q->lock);
 73}
 74
 75static void mt76x02e_pre_tbtt_enable(struct mt76x02_dev *dev, bool en)
 76{
 77	if (en)
 78		tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
 79	else
 80		tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
 81}
 82
 83static void mt76x02e_beacon_enable(struct mt76x02_dev *dev, bool en)
 84{
 85	mt76_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en);
 86	if (en)
 87		mt76x02_irq_enable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
 88	else
 89		mt76x02_irq_disable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
 90}
 91
 92void mt76x02e_init_beacon_config(struct mt76x02_dev *dev)
 93{
 94	static const struct mt76x02_beacon_ops beacon_ops = {
 95		.nslots = 8,
 96		.slot_size = 1024,
 97		.pre_tbtt_enable = mt76x02e_pre_tbtt_enable,
 98		.beacon_enable = mt76x02e_beacon_enable,
 99	};
100
101	dev->beacon_ops = &beacon_ops;
102
103	/* Fire a pre-TBTT interrupt 8 ms before TBTT */
104	mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT,
105		       8 << 4);
106	mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_GP_TIMER,
107		       MT_DFS_GP_INTERVAL);
108	mt76_wr(dev, MT_INT_TIMER_EN, 0);
109
110	mt76x02_init_beacon_config(dev);
111}
112EXPORT_SYMBOL_GPL(mt76x02e_init_beacon_config);
113
114static int
115mt76x02_init_rx_queue(struct mt76x02_dev *dev, struct mt76_queue *q,
116		      int idx, int n_desc, int bufsize)
117{
118	int err;
119
120	err = mt76_queue_alloc(dev, q, idx, n_desc, bufsize,
121			       MT_RX_RING_BASE);
122	if (err < 0)
123		return err;
124
125	mt76x02_irq_enable(dev, MT_INT_RX_DONE(idx));
126
127	return 0;
128}
129
130static void mt76x02_process_tx_status_fifo(struct mt76x02_dev *dev)
131{
132	struct mt76x02_tx_status stat;
133	u8 update = 1;
134
135	while (kfifo_get(&dev->txstatus_fifo, &stat))
136		mt76x02_send_tx_status(dev, &stat, &update);
137}
138
139static void mt76x02_tx_worker(struct mt76_worker *w)
140{
141	struct mt76x02_dev *dev;
142
143	dev = container_of(w, struct mt76x02_dev, mt76.tx_worker);
144
145	mt76x02_mac_poll_tx_status(dev, false);
146	mt76x02_process_tx_status_fifo(dev);
147
148	mt76_txq_schedule_all(&dev->mphy);
149}
150
151static int mt76x02_poll_tx(struct napi_struct *napi, int budget)
152{
153	struct mt76x02_dev *dev = container_of(napi, struct mt76x02_dev,
154					       mt76.tx_napi);
155	int i;
156
157	mt76x02_mac_poll_tx_status(dev, false);
158
159	mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);
160	for (i = MT_TXQ_PSD; i >= 0; i--)
161		mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false);
162
163	if (napi_complete_done(napi, 0))
164		mt76x02_irq_enable(dev, MT_INT_TX_DONE_ALL);
165
166	mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);
167	for (i = MT_TXQ_PSD; i >= 0; i--)
168		mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false);
169
170	mt76_worker_schedule(&dev->mt76.tx_worker);
171
172	return 0;
173}
174
175int mt76x02_dma_init(struct mt76x02_dev *dev)
176{
177	int i, ret, fifo_size;
178	struct mt76_queue *q;
179	void *status_fifo;
180
181	BUILD_BUG_ON(sizeof(struct mt76x02_rxwi) > MT_RX_HEADROOM);
182
183	fifo_size = roundup_pow_of_two(32 * sizeof(struct mt76x02_tx_status));
184	status_fifo = devm_kzalloc(dev->mt76.dev, fifo_size, GFP_KERNEL);
185	if (!status_fifo)
186		return -ENOMEM;
187
188	dev->mt76.tx_worker.fn = mt76x02_tx_worker;
189	tasklet_setup(&dev->mt76.pre_tbtt_tasklet, mt76x02_pre_tbtt_tasklet);
190
191	spin_lock_init(&dev->txstatus_fifo_lock);
192	kfifo_init(&dev->txstatus_fifo, status_fifo, fifo_size);
193
194	mt76_dma_attach(&dev->mt76);
195
196	mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
197
198	for (i = 0; i < IEEE80211_NUM_ACS; i++) {
199		ret = mt76_init_tx_queue(&dev->mphy, i, mt76_ac_to_hwq(i),
200					 MT76x02_TX_RING_SIZE,
201					 MT_TX_RING_BASE, NULL, 0);
202		if (ret)
203			return ret;
204	}
205
206	ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT_TX_HW_QUEUE_MGMT,
207				 MT76x02_PSD_RING_SIZE, MT_TX_RING_BASE,
208				 NULL, 0);
209	if (ret)
210		return ret;
211
212	ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT_TX_HW_QUEUE_MCU,
213				  MT_MCU_RING_SIZE, MT_TX_RING_BASE);
214	if (ret)
215		return ret;
216
217	mt76x02_irq_enable(dev,
218			   MT_INT_TX_DONE(IEEE80211_AC_VO) |
219			   MT_INT_TX_DONE(IEEE80211_AC_VI) |
220			   MT_INT_TX_DONE(IEEE80211_AC_BE) |
221			   MT_INT_TX_DONE(IEEE80211_AC_BK) |
222			   MT_INT_TX_DONE(MT_TX_HW_QUEUE_MGMT) |
223			   MT_INT_TX_DONE(MT_TX_HW_QUEUE_MCU));
224
225	ret = mt76x02_init_rx_queue(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1,
226				    MT_MCU_RING_SIZE, MT_RX_BUF_SIZE);
227	if (ret)
228		return ret;
229
230	q = &dev->mt76.q_rx[MT_RXQ_MAIN];
231	q->buf_offset = MT_RX_HEADROOM - sizeof(struct mt76x02_rxwi);
232	ret = mt76x02_init_rx_queue(dev, q, 0, MT76X02_RX_RING_SIZE,
233				    MT_RX_BUF_SIZE);
234	if (ret)
235		return ret;
236
237	ret = mt76_init_queues(dev, mt76_dma_rx_poll);
238	if (ret)
239		return ret;
240
241	netif_napi_add_tx(dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
242			  mt76x02_poll_tx);
243	napi_enable(&dev->mt76.tx_napi);
244
245	return 0;
246}
247EXPORT_SYMBOL_GPL(mt76x02_dma_init);
248
249void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
250{
251	struct mt76x02_dev *dev;
252
253	dev = container_of(mdev, struct mt76x02_dev, mt76);
254	mt76x02_irq_enable(dev, MT_INT_RX_DONE(q));
255}
256EXPORT_SYMBOL_GPL(mt76x02_rx_poll_complete);
257
258irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance)
259{
260	struct mt76x02_dev *dev = dev_instance;
261	u32 intr, mask;
262
263	intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
264	intr &= dev->mt76.mmio.irqmask;
265	mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
266
267	if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
268		return IRQ_NONE;
269
270	trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
271
272	mask = intr & (MT_INT_RX_DONE_ALL | MT_INT_GPTIMER);
273	if (intr & (MT_INT_TX_DONE_ALL | MT_INT_TX_STAT))
274		mask |= MT_INT_TX_DONE_ALL;
275
276	mt76x02_irq_disable(dev, mask);
277
278	if (intr & MT_INT_RX_DONE(0))
279		napi_schedule(&dev->mt76.napi[0]);
280
281	if (intr & MT_INT_RX_DONE(1))
282		napi_schedule(&dev->mt76.napi[1]);
283
284	if (intr & MT_INT_PRE_TBTT)
285		tasklet_schedule(&dev->mt76.pre_tbtt_tasklet);
286
287	/* send buffered multicast frames now */
288	if (intr & MT_INT_TBTT) {
289		if (dev->mt76.csa_complete)
290			mt76_csa_finish(&dev->mt76);
291		else
292			mt76_queue_kick(dev, dev->mphy.q_tx[MT_TXQ_PSD]);
293	}
294
295	if (intr & MT_INT_TX_STAT)
296		mt76x02_mac_poll_tx_status(dev, true);
297
298	if (intr & (MT_INT_TX_STAT | MT_INT_TX_DONE_ALL))
299		napi_schedule(&dev->mt76.tx_napi);
300
301	if (intr & MT_INT_GPTIMER)
302		tasklet_schedule(&dev->dfs_pd.dfs_tasklet);
303
304	return IRQ_HANDLED;
305}
306EXPORT_SYMBOL_GPL(mt76x02_irq_handler);
307
308static void mt76x02_dma_enable(struct mt76x02_dev *dev)
309{
310	u32 val;
311
312	mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
313	mt76x02_wait_for_wpdma(&dev->mt76, 1000);
314	usleep_range(50, 100);
315
316	val = FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) |
317	      MT_WPDMA_GLO_CFG_TX_DMA_EN |
318	      MT_WPDMA_GLO_CFG_RX_DMA_EN;
319	mt76_set(dev, MT_WPDMA_GLO_CFG, val);
320	mt76_clear(dev, MT_WPDMA_GLO_CFG,
321		   MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
322}
323
324void mt76x02_dma_disable(struct mt76x02_dev *dev)
325{
326	u32 val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
327
328	val &= MT_WPDMA_GLO_CFG_DMA_BURST_SIZE |
329	       MT_WPDMA_GLO_CFG_BIG_ENDIAN |
330	       MT_WPDMA_GLO_CFG_HDR_SEG_LEN;
331	val |= MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE;
332	mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
333}
334EXPORT_SYMBOL_GPL(mt76x02_dma_disable);
335
336void mt76x02_mac_start(struct mt76x02_dev *dev)
337{
338	mt76x02_mac_reset_counters(dev);
339	mt76x02_dma_enable(dev);
340	mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter);
341	mt76_wr(dev, MT_MAC_SYS_CTRL,
342		MT_MAC_SYS_CTRL_ENABLE_TX |
343		MT_MAC_SYS_CTRL_ENABLE_RX);
344	mt76x02_irq_enable(dev,
345			   MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
346			   MT_INT_TX_STAT);
347}
348EXPORT_SYMBOL_GPL(mt76x02_mac_start);
349
350static bool mt76x02_tx_hang(struct mt76x02_dev *dev)
351{
352	u32 dma_idx, prev_dma_idx;
353	struct mt76_queue *q;
354	int i;
355
356	for (i = 0; i < 4; i++) {
357		q = dev->mphy.q_tx[i];
358
359		prev_dma_idx = dev->mt76.tx_dma_idx[i];
360		dma_idx = readl(&q->regs->dma_idx);
361		dev->mt76.tx_dma_idx[i] = dma_idx;
362
363		if (!q->queued || prev_dma_idx != dma_idx) {
364			dev->tx_hang_check[i] = 0;
365			continue;
366		}
367
368		if (++dev->tx_hang_check[i] >= MT_TX_HANG_TH)
369			return true;
370	}
371
372	return false;
373}
374
375static void mt76x02_key_sync(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
376			     struct ieee80211_sta *sta,
377			     struct ieee80211_key_conf *key, void *data)
378{
379	struct mt76x02_dev *dev = hw->priv;
380	struct mt76_wcid *wcid;
381
382	if (!sta)
383		return;
384
385	wcid = (struct mt76_wcid *)sta->drv_priv;
386
387	if (wcid->hw_key_idx != key->keyidx || wcid->sw_iv)
388		return;
389
390	mt76x02_mac_wcid_sync_pn(dev, wcid->idx, key);
391}
392
393static void mt76x02_reset_state(struct mt76x02_dev *dev)
394{
395	int i;
396
397	lockdep_assert_held(&dev->mt76.mutex);
398
399	clear_bit(MT76_STATE_RUNNING, &dev->mphy.state);
400
401	rcu_read_lock();
402	ieee80211_iter_keys_rcu(dev->mt76.hw, NULL, mt76x02_key_sync, NULL);
403	rcu_read_unlock();
404
405	for (i = 0; i < MT76x02_N_WCIDS; i++) {
406		struct ieee80211_sta *sta;
407		struct ieee80211_vif *vif;
408		struct mt76x02_sta *msta;
409		struct mt76_wcid *wcid;
410		void *priv;
411
412		wcid = rcu_dereference_protected(dev->mt76.wcid[i],
413					lockdep_is_held(&dev->mt76.mutex));
414		if (!wcid)
415			continue;
416
417		rcu_assign_pointer(dev->mt76.wcid[i], NULL);
418
419		priv = msta = container_of(wcid, struct mt76x02_sta, wcid);
420		sta = container_of(priv, struct ieee80211_sta, drv_priv);
421
422		priv = msta->vif;
423		vif = container_of(priv, struct ieee80211_vif, drv_priv);
424
425		__mt76_sta_remove(&dev->mphy, vif, sta);
426		memset(msta, 0, sizeof(*msta));
427	}
428
429	dev->mt76.vif_mask = 0;
430	dev->mt76.beacon_mask = 0;
431}
432
433static void mt76x02_watchdog_reset(struct mt76x02_dev *dev)
434{
435	u32 mask = dev->mt76.mmio.irqmask;
436	bool restart = dev->mt76.mcu_ops->mcu_restart;
437	int i;
438
439	ieee80211_stop_queues(dev->mt76.hw);
440	set_bit(MT76_RESET, &dev->mphy.state);
441
442	tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
443	mt76_worker_disable(&dev->mt76.tx_worker);
444	napi_disable(&dev->mt76.tx_napi);
445
446	mt76_for_each_q_rx(&dev->mt76, i) {
447		napi_disable(&dev->mt76.napi[i]);
448	}
449
450	mutex_lock(&dev->mt76.mutex);
451
452	dev->mcu_timeout = 0;
453	if (restart)
454		mt76x02_reset_state(dev);
455
456	if (dev->mt76.beacon_mask)
457		mt76_clear(dev, MT_BEACON_TIME_CFG,
458			   MT_BEACON_TIME_CFG_BEACON_TX |
459			   MT_BEACON_TIME_CFG_TBTT_EN);
460
461	mt76x02_irq_disable(dev, mask);
462
463	/* perform device reset */
464	mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
465	mt76_wr(dev, MT_MAC_SYS_CTRL, 0);
466	mt76_clear(dev, MT_WPDMA_GLO_CFG,
467		   MT_WPDMA_GLO_CFG_TX_DMA_EN | MT_WPDMA_GLO_CFG_RX_DMA_EN);
468	usleep_range(5000, 10000);
469	mt76_wr(dev, MT_INT_SOURCE_CSR, 0xffffffff);
470
471	/* let fw reset DMA */
472	mt76_set(dev, 0x734, 0x3);
473
474	if (restart)
475		mt76_mcu_restart(dev);
476
477	mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], true);
478	for (i = 0; i < __MT_TXQ_MAX; i++)
479		mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);
480
481	mt76_for_each_q_rx(&dev->mt76, i) {
482		mt76_queue_rx_reset(dev, i);
483	}
484
485	mt76_tx_status_check(&dev->mt76, true);
486
487	mt76x02_mac_start(dev);
488
489	if (dev->ed_monitor)
490		mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
491
492	if (dev->mt76.beacon_mask && !restart)
493		mt76_set(dev, MT_BEACON_TIME_CFG,
494			 MT_BEACON_TIME_CFG_BEACON_TX |
495			 MT_BEACON_TIME_CFG_TBTT_EN);
496
497	mt76x02_irq_enable(dev, mask);
498
499	mutex_unlock(&dev->mt76.mutex);
500
501	clear_bit(MT76_RESET, &dev->mphy.state);
502
503	mt76_worker_enable(&dev->mt76.tx_worker);
504	tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
505
506	napi_enable(&dev->mt76.tx_napi);
507	mt76_for_each_q_rx(&dev->mt76, i) {
508		napi_enable(&dev->mt76.napi[i]);
509	}
510
511	local_bh_disable();
512	napi_schedule(&dev->mt76.tx_napi);
513	mt76_for_each_q_rx(&dev->mt76, i) {
514		napi_schedule(&dev->mt76.napi[i]);
515	}
516	local_bh_enable();
517
518	if (restart) {
519		set_bit(MT76_RESTART, &dev->mphy.state);
520		mt76x02_mcu_function_select(dev, Q_SELECT, 1);
521		ieee80211_restart_hw(dev->mt76.hw);
522	} else {
523		ieee80211_wake_queues(dev->mt76.hw);
524		mt76_txq_schedule_all(&dev->mphy);
525	}
526}
527
528void mt76x02_reconfig_complete(struct ieee80211_hw *hw,
529			       enum ieee80211_reconfig_type reconfig_type)
530{
531	struct mt76x02_dev *dev = hw->priv;
532
533	if (reconfig_type != IEEE80211_RECONFIG_TYPE_RESTART)
534		return;
535
536	clear_bit(MT76_RESTART, &dev->mphy.state);
537}
538EXPORT_SYMBOL_GPL(mt76x02_reconfig_complete);
539
540static void mt76x02_check_tx_hang(struct mt76x02_dev *dev)
541{
542	if (test_bit(MT76_RESTART, &dev->mphy.state))
543		return;
544
545	if (!mt76x02_tx_hang(dev) && !dev->mcu_timeout)
546		return;
547
548	mt76x02_watchdog_reset(dev);
549
550	dev->tx_hang_reset++;
551	memset(dev->tx_hang_check, 0, sizeof(dev->tx_hang_check));
552	memset(dev->mt76.tx_dma_idx, 0xff,
553	       sizeof(dev->mt76.tx_dma_idx));
554}
555
556void mt76x02_wdt_work(struct work_struct *work)
557{
558	struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev,
559					       wdt_work.work);
560
561	mt76x02_check_tx_hang(dev);
562
563	ieee80211_queue_delayed_work(mt76_hw(dev), &dev->wdt_work,
564				     MT_WATCHDOG_TIME);
565}