mt76x02_mac.c

   1// SPDX-License-Identifier: BSD-3-Clause-Clear
   2/*
   3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
   4 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
   5 */
   6
   7#include "mt76x02.h"
   8#include "mt76x02_trace.h"
   9#include "trace.h"
  10
  11void mt76x02_mac_reset_counters(struct mt76x02_dev *dev)
  12{
  13	int i;
  14
  15	mt76_rr(dev, MT_RX_STAT_0);
  16	mt76_rr(dev, MT_RX_STAT_1);
  17	mt76_rr(dev, MT_RX_STAT_2);
  18	mt76_rr(dev, MT_TX_STA_0);
  19	mt76_rr(dev, MT_TX_STA_1);
  20	mt76_rr(dev, MT_TX_STA_2);
  21
  22	for (i = 0; i < 16; i++)
  23		mt76_rr(dev, MT_TX_AGG_CNT(i));
  24
  25	for (i = 0; i < 16; i++)
  26		mt76_rr(dev, MT_TX_STAT_FIFO);
  27
  28	memset(dev->mphy.aggr_stats, 0, sizeof(dev->mphy.aggr_stats));
  29}
  30EXPORT_SYMBOL_GPL(mt76x02_mac_reset_counters);
  31
  32static enum mt76x02_cipher_type
  33mt76x02_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data)
  34{
  35	memset(key_data, 0, 32);
  36	if (!key)
  37		return MT76X02_CIPHER_NONE;
  38
  39	if (key->keylen > 32)
  40		return MT76X02_CIPHER_NONE;
  41
  42	memcpy(key_data, key->key, key->keylen);
  43
  44	switch (key->cipher) {
  45	case WLAN_CIPHER_SUITE_WEP40:
  46		return MT76X02_CIPHER_WEP40;
  47	case WLAN_CIPHER_SUITE_WEP104:
  48		return MT76X02_CIPHER_WEP104;
  49	case WLAN_CIPHER_SUITE_TKIP:
  50		return MT76X02_CIPHER_TKIP;
  51	case WLAN_CIPHER_SUITE_CCMP:
  52		return MT76X02_CIPHER_AES_CCMP;
  53	default:
  54		return MT76X02_CIPHER_NONE;
  55	}
  56}
  57
  58int mt76x02_mac_shared_key_setup(struct mt76x02_dev *dev, u8 vif_idx,
  59				 u8 key_idx, struct ieee80211_key_conf *key)
  60{
  61	enum mt76x02_cipher_type cipher;
  62	u8 key_data[32];
  63	u32 val;
  64
  65	cipher = mt76x02_mac_get_key_info(key, key_data);
  66	if (cipher == MT76X02_CIPHER_NONE && key)
  67		return -EOPNOTSUPP;
  68
  69	val = mt76_rr(dev, MT_SKEY_MODE(vif_idx));
  70	val &= ~(MT_SKEY_MODE_MASK << MT_SKEY_MODE_SHIFT(vif_idx, key_idx));
  71	val |= cipher << MT_SKEY_MODE_SHIFT(vif_idx, key_idx);
  72	mt76_wr(dev, MT_SKEY_MODE(vif_idx), val);
  73
  74	mt76_wr_copy(dev, MT_SKEY(vif_idx, key_idx), key_data,
  75		     sizeof(key_data));
  76
  77	return 0;
  78}
  79EXPORT_SYMBOL_GPL(mt76x02_mac_shared_key_setup);
  80
  81void mt76x02_mac_wcid_sync_pn(struct mt76x02_dev *dev, u8 idx,
  82			      struct ieee80211_key_conf *key)
  83{
  84	enum mt76x02_cipher_type cipher;
  85	u8 key_data[32];
  86	u32 iv, eiv;
  87	u64 pn;
  88
  89	cipher = mt76x02_mac_get_key_info(key, key_data);
  90	iv = mt76_rr(dev, MT_WCID_IV(idx));
  91	eiv = mt76_rr(dev, MT_WCID_IV(idx) + 4);
  92
  93	pn = (u64)eiv << 16;
  94	if (cipher == MT76X02_CIPHER_TKIP) {
  95		pn |= (iv >> 16) & 0xff;
  96		pn |= (iv & 0xff) << 8;
  97	} else if (cipher >= MT76X02_CIPHER_AES_CCMP) {
  98		pn |= iv & 0xffff;
  99	} else {
 100		return;
 101	}
 102
 103	atomic64_set(&key->tx_pn, pn);
 104}
 105
 106int mt76x02_mac_wcid_set_key(struct mt76x02_dev *dev, u8 idx,
 107			     struct ieee80211_key_conf *key)
 108{
 109	enum mt76x02_cipher_type cipher;
 110	u8 key_data[32];
 111	u8 iv_data[8];
 112	u64 pn;
 113
 114	cipher = mt76x02_mac_get_key_info(key, key_data);
 115	if (cipher == MT76X02_CIPHER_NONE && key)
 116		return -EOPNOTSUPP;
 117
 118	mt76_wr_copy(dev, MT_WCID_KEY(idx), key_data, sizeof(key_data));
 119	mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PKEY_MODE, cipher);
 120
 121	memset(iv_data, 0, sizeof(iv_data));
 122	if (key) {
 123		mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PAIRWISE,
 124			       !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 125
 126		pn = atomic64_read(&key->tx_pn);
 127
 128		iv_data[3] = key->keyidx << 6;
 129		if (cipher >= MT76X02_CIPHER_TKIP) {
 130			iv_data[3] |= 0x20;
 131			put_unaligned_le32(pn >> 16, &iv_data[4]);
 132		}
 133
 134		if (cipher == MT76X02_CIPHER_TKIP) {
 135			iv_data[0] = (pn >> 8) & 0xff;
 136			iv_data[1] = (iv_data[0] | 0x20) & 0x7f;
 137			iv_data[2] = pn & 0xff;
 138		} else if (cipher >= MT76X02_CIPHER_AES_CCMP) {
 139			put_unaligned_le16((pn & 0xffff), &iv_data[0]);
 140		}
 141	}
 142
 143	mt76_wr_copy(dev, MT_WCID_IV(idx), iv_data, sizeof(iv_data));
 144
 145	return 0;
 146}
 147
 148void mt76x02_mac_wcid_setup(struct mt76x02_dev *dev, u8 idx,
 149			    u8 vif_idx, u8 *mac)
 150{
 151	struct mt76_wcid_addr addr = {};
 152	u32 attr;
 153
 154	attr = FIELD_PREP(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) |
 155	       FIELD_PREP(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8));
 156
 157	mt76_wr(dev, MT_WCID_ATTR(idx), attr);
 158
 159	if (idx >= 128)
 160		return;
 161
 162	if (mac)
 163		memcpy(addr.macaddr, mac, ETH_ALEN);
 164
 165	mt76_wr_copy(dev, MT_WCID_ADDR(idx), &addr, sizeof(addr));
 166}
 167EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_setup);
 168
 169void mt76x02_mac_wcid_set_drop(struct mt76x02_dev *dev, u8 idx, bool drop)
 170{
 171	u32 val = mt76_rr(dev, MT_WCID_DROP(idx));
 172	u32 bit = MT_WCID_DROP_MASK(idx);
 173
 174	/* prevent unnecessary writes */
 175	if ((val & bit) != (bit * drop))
 176		mt76_wr(dev, MT_WCID_DROP(idx), (val & ~bit) | (bit * drop));
 177}
 178
 179static u16
 180mt76x02_mac_tx_rate_val(struct mt76x02_dev *dev,
 181			const struct ieee80211_tx_rate *rate, u8 *nss_val)
 182{
 183	u8 phy, rate_idx, nss, bw = 0;
 184	u16 rateval;
 185
 186	if (rate->flags & IEEE80211_TX_RC_VHT_MCS) {
 187		rate_idx = rate->idx;
 188		nss = 1 + (rate->idx >> 4);
 189		phy = MT_PHY_TYPE_VHT;
 190		if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
 191			bw = 2;
 192		else if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
 193			bw = 1;
 194	} else if (rate->flags & IEEE80211_TX_RC_MCS) {
 195		rate_idx = rate->idx;
 196		nss = 1 + (rate->idx >> 3);
 197		phy = MT_PHY_TYPE_HT;
 198		if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
 199			phy = MT_PHY_TYPE_HT_GF;
 200		if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
 201			bw = 1;
 202	} else {
 203		const struct ieee80211_rate *r;
 204		int band = dev->mphy.chandef.chan->band;
 205		u16 val;
 206
 207		r = &dev->mt76.hw->wiphy->bands[band]->bitrates[rate->idx];
 208		if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
 209			val = r->hw_value_short;
 210		else
 211			val = r->hw_value;
 212
 213		phy = val >> 8;
 214		rate_idx = val & 0xff;
 215		nss = 1;
 216	}
 217
 218	rateval = FIELD_PREP(MT_RXWI_RATE_INDEX, rate_idx);
 219	rateval |= FIELD_PREP(MT_RXWI_RATE_PHY, phy);
 220	rateval |= FIELD_PREP(MT_RXWI_RATE_BW, bw);
 221	if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
 222		rateval |= MT_RXWI_RATE_SGI;
 223
 224	*nss_val = nss;
 225	return rateval;
 226}
 227
 228void mt76x02_mac_wcid_set_rate(struct mt76x02_dev *dev, struct mt76_wcid *wcid,
 229			       const struct ieee80211_tx_rate *rate)
 230{
 231	s8 max_txpwr_adj = mt76x02_tx_get_max_txpwr_adj(dev, rate);
 232	u16 rateval;
 233	u32 tx_info;
 234	s8 nss;
 235
 236	rateval = mt76x02_mac_tx_rate_val(dev, rate, &nss);
 237	tx_info = FIELD_PREP(MT_WCID_TX_INFO_RATE, rateval) |
 238		  FIELD_PREP(MT_WCID_TX_INFO_NSS, nss) |
 239		  FIELD_PREP(MT_WCID_TX_INFO_TXPWR_ADJ, max_txpwr_adj) |
 240		  MT_WCID_TX_INFO_SET;
 241	wcid->tx_info = tx_info;
 242}
 243
 244void mt76x02_mac_set_short_preamble(struct mt76x02_dev *dev, bool enable)
 245{
 246	if (enable)
 247		mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT);
 248	else
 249		mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT);
 250}
 251
 252bool mt76x02_mac_load_tx_status(struct mt76x02_dev *dev,
 253				struct mt76x02_tx_status *stat)
 254{
 255	u32 stat1, stat2;
 256
 257	stat2 = mt76_rr(dev, MT_TX_STAT_FIFO_EXT);
 258	stat1 = mt76_rr(dev, MT_TX_STAT_FIFO);
 259
 260	stat->valid = !!(stat1 & MT_TX_STAT_FIFO_VALID);
 261	if (!stat->valid)
 262		return false;
 263
 264	stat->success = !!(stat1 & MT_TX_STAT_FIFO_SUCCESS);
 265	stat->aggr = !!(stat1 & MT_TX_STAT_FIFO_AGGR);
 266	stat->ack_req = !!(stat1 & MT_TX_STAT_FIFO_ACKREQ);
 267	stat->wcid = FIELD_GET(MT_TX_STAT_FIFO_WCID, stat1);
 268	stat->rate = FIELD_GET(MT_TX_STAT_FIFO_RATE, stat1);
 269
 270	stat->retry = FIELD_GET(MT_TX_STAT_FIFO_EXT_RETRY, stat2);
 271	stat->pktid = FIELD_GET(MT_TX_STAT_FIFO_EXT_PKTID, stat2);
 272
 273	trace_mac_txstat_fetch(dev, stat);
 274
 275	return true;
 276}
 277
 278static int
 279mt76x02_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate,
 280			    enum nl80211_band band)
 281{
 282	u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate);
 283
 284	txrate->idx = 0;
 285	txrate->flags = 0;
 286	txrate->count = 1;
 287
 288	switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) {
 289	case MT_PHY_TYPE_OFDM:
 290		if (band == NL80211_BAND_2GHZ)
 291			idx += 4;
 292
 293		txrate->idx = idx;
 294		return 0;
 295	case MT_PHY_TYPE_CCK:
 296		if (idx >= 8)
 297			idx -= 8;
 298
 299		txrate->idx = idx;
 300		return 0;
 301	case MT_PHY_TYPE_HT_GF:
 302		txrate->flags |= IEEE80211_TX_RC_GREEN_FIELD;
 303		fallthrough;
 304	case MT_PHY_TYPE_HT:
 305		txrate->flags |= IEEE80211_TX_RC_MCS;
 306		txrate->idx = idx;
 307		break;
 308	case MT_PHY_TYPE_VHT:
 309		txrate->flags |= IEEE80211_TX_RC_VHT_MCS;
 310		txrate->idx = idx;
 311		break;
 312	default:
 313		return -EINVAL;
 314	}
 315
 316	switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) {
 317	case MT_PHY_BW_20:
 318		break;
 319	case MT_PHY_BW_40:
 320		txrate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
 321		break;
 322	case MT_PHY_BW_80:
 323		txrate->flags |= IEEE80211_TX_RC_80_MHZ_WIDTH;
 324		break;
 325	default:
 326		return -EINVAL;
 327	}
 328
 329	if (rate & MT_RXWI_RATE_SGI)
 330		txrate->flags |= IEEE80211_TX_RC_SHORT_GI;
 331
 332	return 0;
 333}
 334
 335void mt76x02_mac_write_txwi(struct mt76x02_dev *dev, struct mt76x02_txwi *txwi,
 336			    struct sk_buff *skb, struct mt76_wcid *wcid,
 337			    struct ieee80211_sta *sta, int len)
 338{
 339	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
 340	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
 341	struct ieee80211_tx_rate *rate = &info->control.rates[0];
 342	struct ieee80211_key_conf *key = info->control.hw_key;
 343	u32 wcid_tx_info;
 344	u16 rate_ht_mask = FIELD_PREP(MT_RXWI_RATE_PHY, BIT(1) | BIT(2));
 345	u16 txwi_flags = 0, rateval;
 346	u8 nss;
 347	s8 txpwr_adj, max_txpwr_adj;
 348	u8 ccmp_pn[8], nstreams = dev->mphy.chainmask & 0xf;
 349
 350	memset(txwi, 0, sizeof(*txwi));
 351
 352	mt76_tx_check_agg_ssn(sta, skb);
 353
 354	if (!info->control.hw_key && wcid && wcid->hw_key_idx != 0xff &&
 355	    ieee80211_has_protected(hdr->frame_control)) {
 356		wcid = NULL;
 357		ieee80211_get_tx_rates(info->control.vif, sta, skb,
 358				       info->control.rates, 1);
 359	}
 360
 361	if (wcid)
 362		txwi->wcid = wcid->idx;
 363	else
 364		txwi->wcid = 0xff;
 365
 366	if (wcid && wcid->sw_iv && key) {
 367		u64 pn = atomic64_inc_return(&key->tx_pn);
 368
 369		ccmp_pn[0] = pn;
 370		ccmp_pn[1] = pn >> 8;
 371		ccmp_pn[2] = 0;
 372		ccmp_pn[3] = 0x20 | (key->keyidx << 6);
 373		ccmp_pn[4] = pn >> 16;
 374		ccmp_pn[5] = pn >> 24;
 375		ccmp_pn[6] = pn >> 32;
 376		ccmp_pn[7] = pn >> 40;
 377		txwi->iv = *((__le32 *)&ccmp_pn[0]);
 378		txwi->eiv = *((__le32 *)&ccmp_pn[4]);
 379	}
 380
 381	if (wcid && (rate->idx < 0 || !rate->count)) {
 382		wcid_tx_info = wcid->tx_info;
 383		rateval = FIELD_GET(MT_WCID_TX_INFO_RATE, wcid_tx_info);
 384		max_txpwr_adj = FIELD_GET(MT_WCID_TX_INFO_TXPWR_ADJ,
 385					  wcid_tx_info);
 386		nss = FIELD_GET(MT_WCID_TX_INFO_NSS, wcid_tx_info);
 387	} else {
 388		rateval = mt76x02_mac_tx_rate_val(dev, rate, &nss);
 389		max_txpwr_adj = mt76x02_tx_get_max_txpwr_adj(dev, rate);
 390	}
 391	txwi->rate = cpu_to_le16(rateval);
 392
 393	txpwr_adj = mt76x02_tx_get_txpwr_adj(dev, dev->txpower_conf,
 394					     max_txpwr_adj);
 395	txwi->ctl2 = FIELD_PREP(MT_TX_PWR_ADJ, txpwr_adj);
 396
 397	if (nstreams > 1 && mt76_rev(&dev->mt76) >= MT76XX_REV_E4)
 398		txwi->txstream = 0x13;
 399	else if (nstreams > 1 && mt76_rev(&dev->mt76) >= MT76XX_REV_E3 &&
 400		 !(txwi->rate & cpu_to_le16(rate_ht_mask)))
 401		txwi->txstream = 0x93;
 402
 403	if (is_mt76x2(dev) && (info->flags & IEEE80211_TX_CTL_LDPC))
 404		txwi->rate |= cpu_to_le16(MT_RXWI_RATE_LDPC);
 405	if ((info->flags & IEEE80211_TX_CTL_STBC) && nss == 1)
 406		txwi->rate |= cpu_to_le16(MT_RXWI_RATE_STBC);
 407	if (nss > 1 && sta && sta->deflink.smps_mode == IEEE80211_SMPS_DYNAMIC)
 408		txwi_flags |= MT_TXWI_FLAGS_MMPS;
 409	if (!(info->flags & IEEE80211_TX_CTL_NO_ACK))
 410		txwi->ack_ctl |= MT_TXWI_ACK_CTL_REQ;
 411	if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
 412		txwi->ack_ctl |= MT_TXWI_ACK_CTL_NSEQ;
 413	if ((info->flags & IEEE80211_TX_CTL_AMPDU) && sta) {
 414		u8 ba_size = IEEE80211_MIN_AMPDU_BUF;
 415		u8 ampdu_density = sta->deflink.ht_cap.ampdu_density;
 416
 417		ba_size <<= sta->deflink.ht_cap.ampdu_factor;
 418		ba_size = min_t(int, 63, ba_size - 1);
 419		if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)
 420			ba_size = 0;
 421		txwi->ack_ctl |= FIELD_PREP(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size);
 422
 423		if (ampdu_density < IEEE80211_HT_MPDU_DENSITY_4)
 424			ampdu_density = IEEE80211_HT_MPDU_DENSITY_4;
 425
 426		txwi_flags |= MT_TXWI_FLAGS_AMPDU |
 427			 FIELD_PREP(MT_TXWI_FLAGS_MPDU_DENSITY, ampdu_density);
 428	}
 429
 430	if (ieee80211_is_probe_resp(hdr->frame_control) ||
 431	    ieee80211_is_beacon(hdr->frame_control))
 432		txwi_flags |= MT_TXWI_FLAGS_TS;
 433
 434	txwi->flags |= cpu_to_le16(txwi_flags);
 435	txwi->len_ctl = cpu_to_le16(len);
 436}
 437EXPORT_SYMBOL_GPL(mt76x02_mac_write_txwi);
 438
 439static void
 440mt76x02_tx_rate_fallback(struct ieee80211_tx_rate *rates, int idx, int phy)
 441{
 442	u8 mcs, nss;
 443
 444	if (!idx)
 445		return;
 446
 447	rates += idx - 1;
 448	rates[1] = rates[0];
 449	switch (phy) {
 450	case MT_PHY_TYPE_VHT:
 451		mcs = ieee80211_rate_get_vht_mcs(rates);
 452		nss = ieee80211_rate_get_vht_nss(rates);
 453
 454		if (mcs == 0)
 455			nss = max_t(int, nss - 1, 1);
 456		else
 457			mcs--;
 458
 459		ieee80211_rate_set_vht(rates + 1, mcs, nss);
 460		break;
 461	case MT_PHY_TYPE_HT_GF:
 462	case MT_PHY_TYPE_HT:
 463		/* MCS 8 falls back to MCS 0 */
 464		if (rates[0].idx == 8) {
 465			rates[1].idx = 0;
 466			break;
 467		}
 468		fallthrough;
 469	default:
 470		rates[1].idx = max_t(int, rates[0].idx - 1, 0);
 471		break;
 472	}
 473}
 474
 475static void
 476mt76x02_mac_fill_tx_status(struct mt76x02_dev *dev, struct mt76x02_sta *msta,
 477			   struct ieee80211_tx_info *info,
 478			   struct mt76x02_tx_status *st, int n_frames)
 479{
 480	struct ieee80211_tx_rate *rate = info->status.rates;
 481	struct ieee80211_tx_rate last_rate;
 482	u16 first_rate;
 483	int retry = st->retry;
 484	int phy;
 485	int i;
 486
 487	if (!n_frames)
 488		return;
 489
 490	phy = FIELD_GET(MT_RXWI_RATE_PHY, st->rate);
 491
 492	if (st->pktid & MT_PACKET_ID_HAS_RATE) {
 493		first_rate = st->rate & ~MT_PKTID_RATE;
 494		first_rate |= st->pktid & MT_PKTID_RATE;
 495
 496		mt76x02_mac_process_tx_rate(&rate[0], first_rate,
 497					    dev->mphy.chandef.chan->band);
 498	} else if (rate[0].idx < 0) {
 499		if (!msta)
 500			return;
 501
 502		mt76x02_mac_process_tx_rate(&rate[0], msta->wcid.tx_info,
 503					    dev->mphy.chandef.chan->band);
 504	}
 505
 506	mt76x02_mac_process_tx_rate(&last_rate, st->rate,
 507				    dev->mphy.chandef.chan->band);
 508
 509	for (i = 0; i < ARRAY_SIZE(info->status.rates); i++) {
 510		retry--;
 511		if (i + 1 == ARRAY_SIZE(info->status.rates)) {
 512			info->status.rates[i] = last_rate;
 513			info->status.rates[i].count = max_t(int, retry, 1);
 514			break;
 515		}
 516
 517		mt76x02_tx_rate_fallback(info->status.rates, i, phy);
 518		if (info->status.rates[i].idx == last_rate.idx)
 519			break;
 520	}
 521
 522	if (i + 1 < ARRAY_SIZE(info->status.rates)) {
 523		info->status.rates[i + 1].idx = -1;
 524		info->status.rates[i + 1].count = 0;
 525	}
 526
 527	info->status.ampdu_len = n_frames;
 528	info->status.ampdu_ack_len = st->success ? n_frames : 0;
 529
 530	if (st->aggr)
 531		info->flags |= IEEE80211_TX_CTL_AMPDU |
 532			       IEEE80211_TX_STAT_AMPDU;
 533
 534	if (!st->ack_req)
 535		info->flags |= IEEE80211_TX_CTL_NO_ACK;
 536	else if (st->success)
 537		info->flags |= IEEE80211_TX_STAT_ACK;
 538}
 539
 540void mt76x02_send_tx_status(struct mt76x02_dev *dev,
 541			    struct mt76x02_tx_status *stat, u8 *update)
 542{
 543	struct ieee80211_tx_info info = {};
 544	struct ieee80211_tx_status status = {
 545		.info = &info
 546	};
 547	static const u8 ac_to_tid[4] = {
 548		[IEEE80211_AC_BE] = 0,
 549		[IEEE80211_AC_BK] = 1,
 550		[IEEE80211_AC_VI] = 4,
 551		[IEEE80211_AC_VO] = 6
 552	};
 553	struct mt76_wcid *wcid = NULL;
 554	struct mt76x02_sta *msta = NULL;
 555	struct mt76_dev *mdev = &dev->mt76;
 556	struct sk_buff_head list;
 557	u32 duration = 0;
 558	u8 cur_pktid;
 559	u32 ac = 0;
 560	int len = 0;
 561
 562	if (stat->pktid == MT_PACKET_ID_NO_ACK)
 563		return;
 564
 565	rcu_read_lock();
 566
 567	wcid = mt76_wcid_ptr(dev, stat->wcid);
 568	if (wcid && wcid->sta) {
 569		void *priv;
 570
 571		priv = msta = container_of(wcid, struct mt76x02_sta, wcid);
 572		status.sta = container_of(priv, struct ieee80211_sta,
 573					  drv_priv);
 574	}
 575
 576	mt76_tx_status_lock(mdev, &list);
 577
 578	if (wcid) {
 579		if (mt76_is_skb_pktid(stat->pktid))
 580			status.skb = mt76_tx_status_skb_get(mdev, wcid,
 581							    stat->pktid, &list);
 582		if (status.skb)
 583			status.info = IEEE80211_SKB_CB(status.skb);
 584	}
 585
 586	if (!status.skb && !(stat->pktid & MT_PACKET_ID_HAS_RATE)) {
 587		mt76_tx_status_unlock(mdev, &list);
 588		goto out;
 589	}
 590
 591
 592	if (msta && stat->aggr && !status.skb) {
 593		u32 stat_val, stat_cache;
 594
 595		stat_val = stat->rate;
 596		stat_val |= ((u32)stat->retry) << 16;
 597		stat_cache = msta->status.rate;
 598		stat_cache |= ((u32)msta->status.retry) << 16;
 599
 600		if (*update == 0 && stat_val == stat_cache &&
 601		    stat->wcid == msta->status.wcid && msta->n_frames < 32) {
 602			msta->n_frames++;
 603			mt76_tx_status_unlock(mdev, &list);
 604			goto out;
 605		}
 606
 607		cur_pktid = msta->status.pktid;
 608		mt76x02_mac_fill_tx_status(dev, msta, status.info,
 609					   &msta->status, msta->n_frames);
 610
 611		msta->status = *stat;
 612		msta->n_frames = 1;
 613		*update = 0;
 614	} else {
 615		cur_pktid = stat->pktid;
 616		mt76x02_mac_fill_tx_status(dev, msta, status.info, stat, 1);
 617		*update = 1;
 618	}
 619
 620	if (status.skb) {
 621		info = *status.info;
 622		len = status.skb->len;
 623		ac = skb_get_queue_mapping(status.skb);
 624		mt76_tx_status_skb_done(mdev, status.skb, &list);
 625	} else if (msta) {
 626		len = status.info->status.ampdu_len * ewma_pktlen_read(&msta->pktlen);
 627		ac = FIELD_GET(MT_PKTID_AC, cur_pktid);
 628	}
 629
 630	mt76_tx_status_unlock(mdev, &list);
 631
 632	if (!status.skb) {
 633		spin_lock_bh(&dev->mt76.rx_lock);
 634		ieee80211_tx_status_ext(mt76_hw(dev), &status);
 635		spin_unlock_bh(&dev->mt76.rx_lock);
 636	}
 637
 638	if (!len)
 639		goto out;
 640
 641	duration = ieee80211_calc_tx_airtime(mt76_hw(dev), &info, len);
 642
 643	spin_lock_bh(&dev->mt76.cc_lock);
 644	dev->tx_airtime += duration;
 645	spin_unlock_bh(&dev->mt76.cc_lock);
 646
 647	if (msta)
 648		ieee80211_sta_register_airtime(status.sta, ac_to_tid[ac], duration, 0);
 649
 650out:
 651	rcu_read_unlock();
 652}
 653
 654static int
 655mt76x02_mac_process_rate(struct mt76x02_dev *dev,
 656			 struct mt76_rx_status *status,
 657			 u16 rate)
 658{
 659	u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate);
 660
 661	switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) {
 662	case MT_PHY_TYPE_OFDM:
 663		if (idx >= 8)
 664			idx = 0;
 665
 666		if (status->band == NL80211_BAND_2GHZ)
 667			idx += 4;
 668
 669		status->rate_idx = idx;
 670		return 0;
 671	case MT_PHY_TYPE_CCK:
 672		if (idx >= 8) {
 673			idx -= 8;
 674			status->enc_flags |= RX_ENC_FLAG_SHORTPRE;
 675		}
 676
 677		if (idx >= 4)
 678			idx = 0;
 679
 680		status->rate_idx = idx;
 681		return 0;
 682	case MT_PHY_TYPE_HT_GF:
 683		status->enc_flags |= RX_ENC_FLAG_HT_GF;
 684		fallthrough;
 685	case MT_PHY_TYPE_HT:
 686		status->encoding = RX_ENC_HT;
 687		status->rate_idx = idx;
 688		break;
 689	case MT_PHY_TYPE_VHT: {
 690		u8 n_rxstream = dev->mphy.chainmask & 0xf;
 691
 692		status->encoding = RX_ENC_VHT;
 693		status->rate_idx = FIELD_GET(MT_RATE_INDEX_VHT_IDX, idx);
 694		status->nss = min_t(u8, n_rxstream,
 695				    FIELD_GET(MT_RATE_INDEX_VHT_NSS, idx) + 1);
 696		break;
 697	}
 698	default:
 699		return -EINVAL;
 700	}
 701
 702	if (rate & MT_RXWI_RATE_LDPC)
 703		status->enc_flags |= RX_ENC_FLAG_LDPC;
 704
 705	if (rate & MT_RXWI_RATE_SGI)
 706		status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
 707
 708	if (rate & MT_RXWI_RATE_STBC)
 709		status->enc_flags |= 1 << RX_ENC_FLAG_STBC_SHIFT;
 710
 711	switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) {
 712	case MT_PHY_BW_20:
 713		break;
 714	case MT_PHY_BW_40:
 715		status->bw = RATE_INFO_BW_40;
 716		break;
 717	case MT_PHY_BW_80:
 718		status->bw = RATE_INFO_BW_80;
 719		break;
 720	default:
 721		break;
 722	}
 723
 724	return 0;
 725}
 726
 727void mt76x02_mac_setaddr(struct mt76x02_dev *dev, const u8 *addr)
 728{
 729	static const u8 null_addr[ETH_ALEN] = {};
 730	int i;
 731
 732	ether_addr_copy(dev->mphy.macaddr, addr);
 733
 734	if (!is_valid_ether_addr(dev->mphy.macaddr)) {
 735		eth_random_addr(dev->mphy.macaddr);
 736		dev_info(dev->mt76.dev,
 737			 "Invalid MAC address, using random address %pM\n",
 738			 dev->mphy.macaddr);
 739	}
 740
 741	mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->mphy.macaddr));
 742	mt76_wr(dev, MT_MAC_ADDR_DW1,
 743		get_unaligned_le16(dev->mphy.macaddr + 4) |
 744		FIELD_PREP(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff));
 745
 746	mt76_wr(dev, MT_MAC_BSSID_DW0,
 747		get_unaligned_le32(dev->mphy.macaddr));
 748	mt76_wr(dev, MT_MAC_BSSID_DW1,
 749		get_unaligned_le16(dev->mphy.macaddr + 4) |
 750		FIELD_PREP(MT_MAC_BSSID_DW1_MBSS_MODE, 3) | /* 8 APs + 8 STAs */
 751		MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT);
 752	/* enable 7 additional beacon slots and control them with bypass mask */
 753	mt76_rmw_field(dev, MT_MAC_BSSID_DW1, MT_MAC_BSSID_DW1_MBEACON_N, 7);
 754
 755	for (i = 0; i < 16; i++)
 756		mt76x02_mac_set_bssid(dev, i, null_addr);
 757}
 758EXPORT_SYMBOL_GPL(mt76x02_mac_setaddr);
 759
 760static int
 761mt76x02_mac_get_rssi(struct mt76x02_dev *dev, s8 rssi, int chain)
 762{
 763	struct mt76x02_rx_freq_cal *cal = &dev->cal.rx;
 764
 765	rssi += cal->rssi_offset[chain];
 766	rssi -= cal->lna_gain;
 767
 768	return rssi;
 769}
 770
 771int mt76x02_mac_process_rx(struct mt76x02_dev *dev, struct sk_buff *skb,
 772			   void *rxi)
 773{
 774	struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
 775	struct ieee80211_hdr *hdr;
 776	struct mt76x02_rxwi *rxwi = rxi;
 777	struct mt76x02_sta *sta;
 778	u32 rxinfo = le32_to_cpu(rxwi->rxinfo);
 779	u32 ctl = le32_to_cpu(rxwi->ctl);
 780	u16 rate = le16_to_cpu(rxwi->rate);
 781	u16 tid_sn = le16_to_cpu(rxwi->tid_sn);
 782	bool unicast = rxwi->rxinfo & cpu_to_le32(MT_RXINFO_UNICAST);
 783	int pad_len = 0, nstreams = dev->mphy.chainmask & 0xf;
 784	s8 signal;
 785	u8 pn_len;
 786	u8 wcid;
 787	int len;
 788
 789	if (!test_bit(MT76_STATE_RUNNING, &dev->mphy.state))
 790		return -EINVAL;
 791
 792	if (rxinfo & MT_RXINFO_L2PAD)
 793		pad_len += 2;
 794
 795	if (rxinfo & MT_RXINFO_DECRYPT) {
 796		status->flag |= RX_FLAG_DECRYPTED;
 797		status->flag |= RX_FLAG_MMIC_STRIPPED;
 798		status->flag |= RX_FLAG_MIC_STRIPPED;
 799		status->flag |= RX_FLAG_IV_STRIPPED;
 800	}
 801
 802	wcid = FIELD_GET(MT_RXWI_CTL_WCID, ctl);
 803	sta = mt76x02_rx_get_sta(&dev->mt76, wcid);
 804	status->wcid = mt76x02_rx_get_sta_wcid(sta, unicast);
 805
 806	len = FIELD_GET(MT_RXWI_CTL_MPDU_LEN, ctl);
 807	pn_len = FIELD_GET(MT_RXINFO_PN_LEN, rxinfo);
 808	if (pn_len) {
 809		int offset = ieee80211_get_hdrlen_from_skb(skb) + pad_len;
 810		u8 *data = skb->data + offset;
 811
 812		status->iv[0] = data[7];
 813		status->iv[1] = data[6];
 814		status->iv[2] = data[5];
 815		status->iv[3] = data[4];
 816		status->iv[4] = data[1];
 817		status->iv[5] = data[0];
 818
 819		/*
 820		 * Driver CCMP validation can't deal with fragments.
 821		 * Let mac80211 take care of it.
 822		 */
 823		if (rxinfo & MT_RXINFO_FRAG) {
 824			status->flag &= ~RX_FLAG_IV_STRIPPED;
 825		} else {
 826			pad_len += pn_len << 2;
 827			len -= pn_len << 2;
 828		}
 829	}
 830
 831	mt76x02_remove_hdr_pad(skb, pad_len);
 832
 833	if ((rxinfo & MT_RXINFO_BA) && !(rxinfo & MT_RXINFO_NULL))
 834		status->aggr = true;
 835
 836	if (rxinfo & MT_RXINFO_AMPDU) {
 837		status->flag |= RX_FLAG_AMPDU_DETAILS;
 838		status->ampdu_ref = dev->ampdu_ref;
 839
 840		/*
 841		 * When receiving an A-MPDU subframe and RSSI info is not valid,
 842		 * we can assume that more subframes belonging to the same A-MPDU
 843		 * are coming. The last one will have valid RSSI info
 844		 */
 845		if (rxinfo & MT_RXINFO_RSSI) {
 846			if (!++dev->ampdu_ref)
 847				dev->ampdu_ref++;
 848		}
 849	}
 850
 851	if (WARN_ON_ONCE(len > skb->len))
 852		return -EINVAL;
 853
 854	if (pskb_trim(skb, len))
 855		return -EINVAL;
 856
 857	status->chains = BIT(0);
 858	signal = mt76x02_mac_get_rssi(dev, rxwi->rssi[0], 0);
 859	status->chain_signal[0] = signal;
 860	if (nstreams > 1) {
 861		status->chains |= BIT(1);
 862		status->chain_signal[1] = mt76x02_mac_get_rssi(dev,
 863							       rxwi->rssi[1],
 864							       1);
 865	}
 866	status->freq = dev->mphy.chandef.chan->center_freq;
 867	status->band = dev->mphy.chandef.chan->band;
 868
 869	hdr = (struct ieee80211_hdr *)skb->data;
 870	status->qos_ctl = *ieee80211_get_qos_ctl(hdr);
 871	status->seqno = FIELD_GET(MT_RXWI_SN, tid_sn);
 872
 873	return mt76x02_mac_process_rate(dev, status, rate);
 874}
 875
 876void mt76x02_mac_poll_tx_status(struct mt76x02_dev *dev, bool irq)
 877{
 878	struct mt76x02_tx_status stat = {};
 879	u8 update = 1;
 880	bool ret;
 881
 882	if (!test_bit(MT76_STATE_RUNNING, &dev->mphy.state))
 883		return;
 884
 885	trace_mac_txstat_poll(dev);
 886
 887	while (!irq || !kfifo_is_full(&dev->txstatus_fifo)) {
 888		if (!spin_trylock(&dev->txstatus_fifo_lock))
 889			break;
 890
 891		ret = mt76x02_mac_load_tx_status(dev, &stat);
 892		spin_unlock(&dev->txstatus_fifo_lock);
 893
 894		if (!ret)
 895			break;
 896
 897		if (!irq) {
 898			mt76x02_send_tx_status(dev, &stat, &update);
 899			continue;
 900		}
 901
 902		kfifo_put(&dev->txstatus_fifo, stat);
 903	}
 904}
 905
 906void mt76x02_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e)
 907{
 908	struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
 909	struct mt76x02_txwi *txwi;
 910	u8 *txwi_ptr;
 911
 912	if (!e->txwi) {
 913		dev_kfree_skb_any(e->skb);
 914		return;
 915	}
 916
 917	mt76x02_mac_poll_tx_status(dev, false);
 918
 919	txwi_ptr = mt76_get_txwi_ptr(mdev, e->txwi);
 920	txwi = (struct mt76x02_txwi *)txwi_ptr;
 921	trace_mac_txdone(mdev, txwi->wcid, txwi->pktid);
 922
 923	mt76_tx_complete_skb(mdev, e->wcid, e->skb);
 924}
 925EXPORT_SYMBOL_GPL(mt76x02_tx_complete_skb);
 926
 927void mt76x02_mac_set_rts_thresh(struct mt76x02_dev *dev, u32 val)
 928{
 929	u32 data = 0;
 930
 931	if (val != ~0)
 932		data = FIELD_PREP(MT_PROT_CFG_CTRL, 1) |
 933		       MT_PROT_CFG_RTS_THRESH;
 934
 935	mt76_rmw_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH, val);
 936
 937	mt76_rmw(dev, MT_CCK_PROT_CFG,
 938		 MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data);
 939	mt76_rmw(dev, MT_OFDM_PROT_CFG,
 940		 MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data);
 941}
 942
 943void mt76x02_mac_set_tx_protection(struct mt76x02_dev *dev, bool legacy_prot,
 944				   int ht_mode)
 945{
 946	int mode = ht_mode & IEEE80211_HT_OP_MODE_PROTECTION;
 947	bool non_gf = !!(ht_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
 948	u32 prot[6];
 949	u32 vht_prot[3];
 950	int i;
 951	u16 rts_thr;
 952
 953	for (i = 0; i < ARRAY_SIZE(prot); i++) {
 954		prot[i] = mt76_rr(dev, MT_CCK_PROT_CFG + i * 4);
 955		prot[i] &= ~MT_PROT_CFG_CTRL;
 956		if (i >= 2)
 957			prot[i] &= ~MT_PROT_CFG_RATE;
 958	}
 959
 960	for (i = 0; i < ARRAY_SIZE(vht_prot); i++) {
 961		vht_prot[i] = mt76_rr(dev, MT_TX_PROT_CFG6 + i * 4);
 962		vht_prot[i] &= ~(MT_PROT_CFG_CTRL | MT_PROT_CFG_RATE);
 963	}
 964
 965	rts_thr = mt76_get_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH);
 966
 967	if (rts_thr != 0xffff)
 968		prot[0] |= MT_PROT_CTRL_RTS_CTS;
 969
 970	if (legacy_prot) {
 971		prot[1] |= MT_PROT_CTRL_CTS2SELF;
 972
 973		prot[2] |= MT_PROT_RATE_CCK_11;
 974		prot[3] |= MT_PROT_RATE_CCK_11;
 975		prot[4] |= MT_PROT_RATE_CCK_11;
 976		prot[5] |= MT_PROT_RATE_CCK_11;
 977
 978		vht_prot[0] |= MT_PROT_RATE_CCK_11;
 979		vht_prot[1] |= MT_PROT_RATE_CCK_11;
 980		vht_prot[2] |= MT_PROT_RATE_CCK_11;
 981	} else {
 982		if (rts_thr != 0xffff)
 983			prot[1] |= MT_PROT_CTRL_RTS_CTS;
 984
 985		prot[2] |= MT_PROT_RATE_OFDM_24;
 986		prot[3] |= MT_PROT_RATE_DUP_OFDM_24;
 987		prot[4] |= MT_PROT_RATE_OFDM_24;
 988		prot[5] |= MT_PROT_RATE_DUP_OFDM_24;
 989
 990		vht_prot[0] |= MT_PROT_RATE_OFDM_24;
 991		vht_prot[1] |= MT_PROT_RATE_DUP_OFDM_24;
 992		vht_prot[2] |= MT_PROT_RATE_SGI_OFDM_24;
 993	}
 994
 995	switch (mode) {
 996	case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
 997	case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
 998		prot[2] |= MT_PROT_CTRL_RTS_CTS;
 999		prot[3] |= MT_PROT_CTRL_RTS_CTS;
1000		prot[4] |= MT_PROT_CTRL_RTS_CTS;
1001		prot[5] |= MT_PROT_CTRL_RTS_CTS;
1002		vht_prot[0] |= MT_PROT_CTRL_RTS_CTS;
1003		vht_prot[1] |= MT_PROT_CTRL_RTS_CTS;
1004		vht_prot[2] |= MT_PROT_CTRL_RTS_CTS;
1005		break;
1006	case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1007		prot[3] |= MT_PROT_CTRL_RTS_CTS;
1008		prot[5] |= MT_PROT_CTRL_RTS_CTS;
1009		vht_prot[1] |= MT_PROT_CTRL_RTS_CTS;
1010		vht_prot[2] |= MT_PROT_CTRL_RTS_CTS;
1011		break;
1012	}
1013
1014	if (non_gf) {
1015		prot[4] |= MT_PROT_CTRL_RTS_CTS;
1016		prot[5] |= MT_PROT_CTRL_RTS_CTS;
1017	}
1018
1019	for (i = 0; i < ARRAY_SIZE(prot); i++)
1020		mt76_wr(dev, MT_CCK_PROT_CFG + i * 4, prot[i]);
1021
1022	for (i = 0; i < ARRAY_SIZE(vht_prot); i++)
1023		mt76_wr(dev, MT_TX_PROT_CFG6 + i * 4, vht_prot[i]);
1024}
1025
1026void mt76x02_update_channel(struct mt76_phy *mphy)
1027{
1028	struct mt76x02_dev *dev = container_of(mphy->dev, struct mt76x02_dev, mt76);
1029	struct mt76_channel_state *state;
1030
1031	state = mphy->chan_state;
1032	state->cc_busy += mt76_rr(dev, MT_CH_BUSY);
1033
1034	spin_lock_bh(&dev->mt76.cc_lock);
1035	state->cc_tx += dev->tx_airtime;
1036	dev->tx_airtime = 0;
1037	spin_unlock_bh(&dev->mt76.cc_lock);
1038}
1039EXPORT_SYMBOL_GPL(mt76x02_update_channel);
1040
1041static void mt76x02_check_mac_err(struct mt76x02_dev *dev)
1042{
1043	if (dev->mt76.beacon_mask) {
1044		if (mt76_rr(dev, MT_TX_STA_0) & MT_TX_STA_0_BEACONS) {
1045			dev->beacon_hang_check = 0;
1046			return;
1047		}
1048
1049		if (dev->beacon_hang_check < 10)
1050			return;
1051
1052	} else {
1053		u32 val = mt76_rr(dev, 0x10f4);
1054		if (!(val & BIT(29)) || !(val & (BIT(7) | BIT(5))))
1055			return;
1056	}
1057
1058	dev_err(dev->mt76.dev, "MAC error detected\n");
1059
1060	mt76_wr(dev, MT_MAC_SYS_CTRL, 0);
1061	if (!mt76x02_wait_for_txrx_idle(&dev->mt76)) {
1062		dev_err(dev->mt76.dev, "MAC stop failed\n");
1063		goto out;
1064	}
1065
1066	dev->beacon_hang_check = 0;
1067	mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR);
1068	udelay(10);
1069
1070out:
1071	mt76_wr(dev, MT_MAC_SYS_CTRL,
1072		MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX);
1073}
1074
1075static void
1076mt76x02_edcca_tx_enable(struct mt76x02_dev *dev, bool enable)
1077{
1078	if (enable) {
1079		u32 data;
1080
1081		mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
1082		mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_EN);
1083		/* enable pa-lna */
1084		data = mt76_rr(dev, MT_TX_PIN_CFG);
1085		data |= MT_TX_PIN_CFG_TXANT |
1086			MT_TX_PIN_CFG_RXANT |
1087			MT_TX_PIN_RFTR_EN |
1088			MT_TX_PIN_TRSW_EN;
1089		mt76_wr(dev, MT_TX_PIN_CFG, data);
1090	} else {
1091		mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
1092		mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_EN);
1093		/* disable pa-lna */
1094		mt76_clear(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_TXANT);
1095		mt76_clear(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_RXANT);
1096	}
1097	dev->ed_tx_blocked = !enable;
1098}
1099
1100void mt76x02_edcca_init(struct mt76x02_dev *dev)
1101{
1102	dev->ed_trigger = 0;
1103	dev->ed_silent = 0;
1104
1105	if (dev->ed_monitor) {
1106		struct ieee80211_channel *chan = dev->mphy.chandef.chan;
1107		u8 ed_th = chan->band == NL80211_BAND_5GHZ ? 0x0e : 0x20;
1108
1109		mt76_clear(dev, MT_TX_LINK_CFG, MT_TX_CFACK_EN);
1110		mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
1111		mt76_rmw(dev, MT_BBP(AGC, 2), GENMASK(15, 0),
1112			 ed_th << 8 | ed_th);
1113		mt76_set(dev, MT_TXOP_HLDR_ET, MT_TXOP_HLDR_TX40M_BLK_EN);
1114	} else {
1115		mt76_set(dev, MT_TX_LINK_CFG, MT_TX_CFACK_EN);
1116		mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
1117		if (is_mt76x2(dev)) {
1118			mt76_wr(dev, MT_BBP(AGC, 2), 0x00007070);
1119			mt76_set(dev, MT_TXOP_HLDR_ET,
1120				 MT_TXOP_HLDR_TX40M_BLK_EN);
1121		} else {
1122			mt76_wr(dev, MT_BBP(AGC, 2), 0x003a6464);
1123			mt76_clear(dev, MT_TXOP_HLDR_ET,
1124				   MT_TXOP_HLDR_TX40M_BLK_EN);
1125		}
1126	}
1127	mt76x02_edcca_tx_enable(dev, true);
1128	dev->ed_monitor_learning = true;
1129
1130	/* clear previous CCA timer value */
1131	mt76_rr(dev, MT_ED_CCA_TIMER);
1132	dev->ed_time = ktime_get_boottime();
1133}
1134EXPORT_SYMBOL_GPL(mt76x02_edcca_init);
1135
1136#define MT_EDCCA_TH		92
1137#define MT_EDCCA_BLOCK_TH	2
1138#define MT_EDCCA_LEARN_TH	50
1139#define MT_EDCCA_LEARN_CCA	180
1140#define MT_EDCCA_LEARN_TIMEOUT	(20 * HZ)
1141
1142static void mt76x02_edcca_check(struct mt76x02_dev *dev)
1143{
1144	ktime_t cur_time;
1145	u32 active, val, busy;
1146
1147	cur_time = ktime_get_boottime();
1148	val = mt76_rr(dev, MT_ED_CCA_TIMER);
1149
1150	active = ktime_to_us(ktime_sub(cur_time, dev->ed_time));
1151	dev->ed_time = cur_time;
1152
1153	busy = (val * 100) / active;
1154	busy = min_t(u32, busy, 100);
1155
1156	if (busy > MT_EDCCA_TH) {
1157		dev->ed_trigger++;
1158		dev->ed_silent = 0;
1159	} else {
1160		dev->ed_silent++;
1161		dev->ed_trigger = 0;
1162	}
1163
1164	if (dev->cal.agc_lowest_gain &&
1165	    dev->cal.false_cca > MT_EDCCA_LEARN_CCA &&
1166	    dev->ed_trigger > MT_EDCCA_LEARN_TH) {
1167		dev->ed_monitor_learning = false;
1168		dev->ed_trigger_timeout = jiffies + 20 * HZ;
1169	} else if (!dev->ed_monitor_learning &&
1170		   time_is_after_jiffies(dev->ed_trigger_timeout)) {
1171		dev->ed_monitor_learning = true;
1172		mt76x02_edcca_tx_enable(dev, true);
1173	}
1174
1175	if (dev->ed_monitor_learning)
1176		return;
1177
1178	if (dev->ed_trigger > MT_EDCCA_BLOCK_TH && !dev->ed_tx_blocked)
1179		mt76x02_edcca_tx_enable(dev, false);
1180	else if (dev->ed_silent > MT_EDCCA_BLOCK_TH && dev->ed_tx_blocked)
1181		mt76x02_edcca_tx_enable(dev, true);
1182}
1183
1184void mt76x02_mac_work(struct work_struct *work)
1185{
1186	struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev,
1187					       mphy.mac_work.work);
1188	int i, idx;
1189
1190	mutex_lock(&dev->mt76.mutex);
1191
1192	mt76_update_survey(&dev->mphy);
1193	for (i = 0, idx = 0; i < 16; i++) {
1194		u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i));
1195
1196		dev->mphy.aggr_stats[idx++] += val & 0xffff;
1197		dev->mphy.aggr_stats[idx++] += val >> 16;
1198	}
1199
1200	mt76x02_check_mac_err(dev);
1201
1202	if (dev->ed_monitor)
1203		mt76x02_edcca_check(dev);
1204
1205	mutex_unlock(&dev->mt76.mutex);
1206
1207	mt76_tx_status_check(&dev->mt76, false);
1208
1209	ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work,
1210				     MT_MAC_WORK_INTERVAL);
1211}
1212
1213void mt76x02_mac_cc_reset(struct mt76x02_dev *dev)
1214{
1215	dev->mphy.survey_time = ktime_get_boottime();
1216
1217	mt76_wr(dev, MT_CH_TIME_CFG,
1218		MT_CH_TIME_CFG_TIMER_EN |
1219		MT_CH_TIME_CFG_TX_AS_BUSY |
1220		MT_CH_TIME_CFG_RX_AS_BUSY |
1221		MT_CH_TIME_CFG_NAV_AS_BUSY |
1222		MT_CH_TIME_CFG_EIFS_AS_BUSY |
1223		MT_CH_CCA_RC_EN |
1224		FIELD_PREP(MT_CH_TIME_CFG_CH_TIMER_CLR, 1));
1225
1226	/* channel cycle counters read-and-clear */
1227	mt76_rr(dev, MT_CH_BUSY);
1228	mt76_rr(dev, MT_CH_IDLE);
1229}
1230EXPORT_SYMBOL_GPL(mt76x02_mac_cc_reset);
1231
1232void mt76x02_mac_set_bssid(struct mt76x02_dev *dev, u8 idx, const u8 *addr)
1233{
1234	idx &= 7;
1235	mt76_wr(dev, MT_MAC_APC_BSSID_L(idx), get_unaligned_le32(addr));
1236	mt76_rmw_field(dev, MT_MAC_APC_BSSID_H(idx), MT_MAC_APC_BSSID_H_ADDR,
1237		       get_unaligned_le16(addr + 4));
1238}