mt76_connac.h

  1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
  2/* Copyright (C) 2020 MediaTek Inc. */
  3
  4#ifndef __MT76_CONNAC_H
  5#define __MT76_CONNAC_H
  6
  7#include "mt76.h"
  8
  9enum rx_pkt_type {
 10	PKT_TYPE_TXS,
 11	PKT_TYPE_TXRXV,
 12	PKT_TYPE_NORMAL,
 13	PKT_TYPE_RX_DUP_RFB,
 14	PKT_TYPE_RX_TMR,
 15	PKT_TYPE_RETRIEVE,
 16	PKT_TYPE_TXRX_NOTIFY,
 17	PKT_TYPE_RX_EVENT,
 18	PKT_TYPE_NORMAL_MCU,
 19	PKT_TYPE_RX_FW_MONITOR	= 0x0c,
 20	PKT_TYPE_TXRX_NOTIFY_V0	= 0x18,
 21};
 22
 23#define MT76_CONNAC_SCAN_IE_LEN			600
 24#define MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL	 10
 25#define MT76_CONNAC_MAX_TIME_SCHED_SCAN_INTERVAL U16_MAX
 26#define MT76_CONNAC_MAX_SCHED_SCAN_SSID		10
 27#define MT76_CONNAC_MAX_SCAN_MATCH		16
 28
 29#define MT76_CONNAC_MAX_WMM_SETS		4
 30
 31#define MT76_CONNAC_COREDUMP_TIMEOUT		(HZ / 20)
 32#define MT76_CONNAC_COREDUMP_SZ			(1300 * 1024)
 33
 34#define MT_TXD_SIZE				(8 * 4)
 35
 36#define MT_USB_TXD_SIZE				(MT_TXD_SIZE + 8 * 4)
 37#define MT_USB_HDR_SIZE				4
 38#define MT_USB_TAIL_SIZE			4
 39
 40#define MT_SDIO_TXD_SIZE			(MT_TXD_SIZE + 8 * 4)
 41#define MT_SDIO_TAIL_SIZE			8
 42#define MT_SDIO_HDR_SIZE			4
 43
 44#define MT_MSDU_ID_VALID		BIT(15)
 45
 46#define MT_TXD_LEN_LAST			BIT(15)
 47#define MT_TXD_LEN_MASK			GENMASK(11, 0)
 48#define MT_TXD_LEN_MSDU_LAST		BIT(14)
 49#define MT_TXD_LEN_AMSDU_LAST		BIT(15)
 50
 51enum {
 52	CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20,
 53	CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40,
 54	CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80,
 55	CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160,
 56	CMD_CBW_10MHZ,
 57	CMD_CBW_5MHZ,
 58	CMD_CBW_8080MHZ,
 59	CMD_CBW_320MHZ,
 60
 61	CMD_HE_MCS_BW80 = 0,
 62	CMD_HE_MCS_BW160,
 63	CMD_HE_MCS_BW8080,
 64	CMD_HE_MCS_BW_NUM
 65};
 66
 67enum {
 68	HW_BSSID_0 = 0x0,
 69	HW_BSSID_1,
 70	HW_BSSID_2,
 71	HW_BSSID_3,
 72	HW_BSSID_MAX = HW_BSSID_3,
 73	EXT_BSSID_START = 0x10,
 74	EXT_BSSID_1,
 75	EXT_BSSID_15 = 0x1f,
 76	EXT_BSSID_MAX = EXT_BSSID_15,
 77	REPEATER_BSSID_START = 0x20,
 78	REPEATER_BSSID_MAX = 0x3f,
 79};
 80
 81struct mt76_connac_reg_map {
 82	u32 phys;
 83	u32 maps;
 84	u32 size;
 85};
 86
 87struct mt76_connac_pm {
 88	bool enable:1;
 89	bool enable_user:1;
 90	bool ds_enable:1;
 91	bool ds_enable_user:1;
 92	bool suspended:1;
 93
 94	spinlock_t txq_lock;
 95	struct {
 96		struct mt76_wcid *wcid;
 97		struct sk_buff *skb;
 98	} tx_q[IEEE80211_NUM_ACS];
 99
100	struct work_struct wake_work;
101	wait_queue_head_t wait;
102
103	struct {
104		spinlock_t lock;
105		u32 count;
106	} wake;
107	struct mutex mutex;
108
109	struct delayed_work ps_work;
110	unsigned long last_activity;
111	unsigned long idle_timeout;
112
113	struct {
114		unsigned long last_wake_event;
115		unsigned long awake_time;
116		unsigned long last_doze_event;
117		unsigned long doze_time;
118		unsigned int lp_wake;
119	} stats;
120};
121
122struct mt76_connac_coredump {
123	struct sk_buff_head msg_list;
124	struct delayed_work work;
125	unsigned long last_activity;
126};
127
128struct mt76_connac_sta_key_conf {
129	s8 keyidx;
130	u8 key[16];
131};
132
133#define MT_TXP_MAX_BUF_NUM		6
134
135struct mt76_connac_fw_txp {
136	__le16 flags;
137	__le16 token;
138	u8 bss_idx;
139	__le16 rept_wds_wcid;
140	u8 nbuf;
141	__le32 buf[MT_TXP_MAX_BUF_NUM];
142	__le16 len[MT_TXP_MAX_BUF_NUM];
143} __packed __aligned(4);
144
145#define MT_HW_TXP_MAX_MSDU_NUM		4
146#define MT_HW_TXP_MAX_BUF_NUM		4
147
148struct mt76_connac_txp_ptr {
149	__le32 buf0;
150	__le16 len0;
151	__le16 len1;
152	__le32 buf1;
153} __packed __aligned(4);
154
155struct mt76_connac_hw_txp {
156	__le16 msdu_id[MT_HW_TXP_MAX_MSDU_NUM];
157	struct mt76_connac_txp_ptr ptr[MT_HW_TXP_MAX_BUF_NUM / 2];
158} __packed __aligned(4);
159
160struct mt76_connac_txp_common {
161	union {
162		struct mt76_connac_fw_txp fw;
163		struct mt76_connac_hw_txp hw;
164	};
165};
166
167struct mt76_connac_tx_free {
168	__le16 rx_byte_cnt;
169	__le16 ctrl;
170	__le32 txd;
171} __packed __aligned(4);
172
173extern const struct wiphy_wowlan_support mt76_connac_wowlan_support;
174
175static inline bool is_mt7925(struct mt76_dev *dev)
176{
177	return mt76_chip(dev) == 0x7925;
178}
179
180static inline bool is_mt7920(struct mt76_dev *dev)
181{
182	return mt76_chip(dev) == 0x7920;
183}
184
185static inline bool is_mt7922(struct mt76_dev *dev)
186{
187	return mt76_chip(dev) == 0x7922;
188}
189
190static inline bool is_mt7921(struct mt76_dev *dev)
191{
192	return mt76_chip(dev) == 0x7961 || is_mt7922(dev) || is_mt7920(dev);
193}
194
195static inline bool is_mt7663(struct mt76_dev *dev)
196{
197	return mt76_chip(dev) == 0x7663;
198}
199
200static inline bool is_mt7915(struct mt76_dev *dev)
201{
202	return mt76_chip(dev) == 0x7915;
203}
204
205static inline bool is_mt7916(struct mt76_dev *dev)
206{
207	return mt76_chip(dev) == 0x7906;
208}
209
210static inline bool is_mt7981(struct mt76_dev *dev)
211{
212	return mt76_chip(dev) == 0x7981;
213}
214
215static inline bool is_mt7986(struct mt76_dev *dev)
216{
217	return mt76_chip(dev) == 0x7986;
218}
219
220static inline bool is_mt798x(struct mt76_dev *dev)
221{
222	return is_mt7981(dev) || is_mt7986(dev);
223}
224
225static inline bool is_mt7996(struct mt76_dev *dev)
226{
227	return mt76_chip(dev) == 0x7990;
228}
229
230static inline bool is_mt7992(struct mt76_dev *dev)
231{
232	return mt76_chip(dev) == 0x7992;
233}
234
235static inline bool is_mt7990(struct mt76_dev *dev)
236{
237	return mt76_chip(dev) == 0x7993;
238}
239
240static inline bool is_mt799x(struct mt76_dev *dev)
241{
242	return is_mt7996(dev) || is_mt7992(dev) || is_mt7990(dev);
243}
244
245static inline bool is_mt7622(struct mt76_dev *dev)
246{
247	if (!IS_ENABLED(CONFIG_MT7622_WMAC))
248		return false;
249
250	return mt76_chip(dev) == 0x7622;
251}
252
253static inline bool is_mt7615(struct mt76_dev *dev)
254{
255	return mt76_chip(dev) == 0x7615 || mt76_chip(dev) == 0x7611;
256}
257
258static inline bool is_mt7611(struct mt76_dev *dev)
259{
260	return mt76_chip(dev) == 0x7611;
261}
262
263static inline bool is_connac_v1(struct mt76_dev *dev)
264{
265	return is_mt7615(dev) || is_mt7663(dev) || is_mt7622(dev);
266}
267
268static inline bool is_mt76_fw_txp(struct mt76_dev *dev)
269{
270	switch (mt76_chip(dev)) {
271	case 0x7961:
272	case 0x7920:
273	case 0x7922:
274	case 0x7925:
275	case 0x7663:
276	case 0x7622:
277		return false;
278	default:
279		return true;
280	}
281}
282
283static inline u8 mt76_connac_chan_bw(struct cfg80211_chan_def *chandef)
284{
285	static const u8 width_to_bw[] = {
286		[NL80211_CHAN_WIDTH_40] = CMD_CBW_40MHZ,
287		[NL80211_CHAN_WIDTH_80] = CMD_CBW_80MHZ,
288		[NL80211_CHAN_WIDTH_80P80] = CMD_CBW_8080MHZ,
289		[NL80211_CHAN_WIDTH_160] = CMD_CBW_160MHZ,
290		[NL80211_CHAN_WIDTH_5] = CMD_CBW_5MHZ,
291		[NL80211_CHAN_WIDTH_10] = CMD_CBW_10MHZ,
292		[NL80211_CHAN_WIDTH_20] = CMD_CBW_20MHZ,
293		[NL80211_CHAN_WIDTH_20_NOHT] = CMD_CBW_20MHZ,
294		[NL80211_CHAN_WIDTH_320] = CMD_CBW_320MHZ,
295	};
296
297	if (chandef->width >= ARRAY_SIZE(width_to_bw))
298		return 0;
299
300	return width_to_bw[chandef->width];
301}
302
303static inline u8 mt76_connac_lmac_mapping(u8 ac)
304{
305	/* LMAC uses the reverse order of mac80211 AC indexes */
306	return 3 - ac;
307}
308
309static inline void *
310mt76_connac_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t)
311{
312	u8 *txwi;
313
314	if (!t)
315		return NULL;
316
317	txwi = mt76_get_txwi_ptr(dev, t);
318
319	return (void *)(txwi + MT_TXD_SIZE);
320}
321
322static inline u8 mt76_connac_spe_idx(u8 antenna_mask)
323{
324	static const u8 ant_to_spe[] = {0, 0, 1, 0, 3, 2, 4, 0,
325					9, 8, 6, 10, 16, 12, 18, 0};
326
327	if (antenna_mask >= sizeof(ant_to_spe))
328		return 0;
329
330	return ant_to_spe[antenna_mask];
331}
332
333static inline void mt76_connac_irq_enable(struct mt76_dev *dev, u32 mask)
334{
335	mt76_set_irq_mask(dev, 0, 0, mask);
336	tasklet_schedule(&dev->irq_tasklet);
337}
338
339int mt76_connac_pm_wake(struct mt76_phy *phy, struct mt76_connac_pm *pm);
340void mt76_connac_power_save_sched(struct mt76_phy *phy,
341				  struct mt76_connac_pm *pm);
342void mt76_connac_free_pending_tx_skbs(struct mt76_connac_pm *pm,
343				      struct mt76_wcid *wcid);
344
345static inline void mt76_connac_tx_cleanup(struct mt76_dev *dev)
346{
347	dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WM], false);
348	dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WA], false);
349}
350
351static inline bool
352mt76_connac_pm_ref(struct mt76_phy *phy, struct mt76_connac_pm *pm)
353{
354	bool ret = false;
355
356	spin_lock_bh(&pm->wake.lock);
357	if (test_bit(MT76_STATE_PM, &phy->state))
358		goto out;
359
360	pm->wake.count++;
361	ret = true;
362out:
363	spin_unlock_bh(&pm->wake.lock);
364
365	return ret;
366}
367
368static inline void
369mt76_connac_pm_unref(struct mt76_phy *phy, struct mt76_connac_pm *pm)
370{
371	spin_lock_bh(&pm->wake.lock);
372
373	pm->last_activity = jiffies;
374	if (--pm->wake.count == 0 &&
375	    test_bit(MT76_STATE_MCU_RUNNING, &phy->state))
376		mt76_connac_power_save_sched(phy, pm);
377
378	spin_unlock_bh(&pm->wake.lock);
379}
380
381static inline bool
382mt76_connac_skip_fw_pmctrl(struct mt76_phy *phy, struct mt76_connac_pm *pm)
383{
384	struct mt76_dev *dev = phy->dev;
385	bool ret;
386
387	if (dev->token_count)
388		return true;
389
390	spin_lock_bh(&pm->wake.lock);
391	ret = pm->wake.count || test_and_set_bit(MT76_STATE_PM, &phy->state);
392	spin_unlock_bh(&pm->wake.lock);
393
394	return ret;
395}
396
397static inline void
398mt76_connac_mutex_acquire(struct mt76_dev *dev, struct mt76_connac_pm *pm)
399	__acquires(&dev->mutex)
400{
401	mutex_lock(&dev->mutex);
402	mt76_connac_pm_wake(&dev->phy, pm);
403}
404
405static inline void
406mt76_connac_mutex_release(struct mt76_dev *dev, struct mt76_connac_pm *pm)
407	__releases(&dev->mutex)
408{
409	mt76_connac_power_save_sched(&dev->phy, pm);
410	mutex_unlock(&dev->mutex);
411}
412
413void mt76_connac_gen_ppe_thresh(u8 *he_ppet, int nss, enum nl80211_band band);
414int mt76_connac_init_tx_queues(struct mt76_phy *phy, int idx, int n_desc,
415			       int ring_base, void *wed, u32 flags);
416
417void mt76_connac_write_hw_txp(struct mt76_dev *dev,
418			      struct mt76_tx_info *tx_info,
419			      void *txp_ptr, u32 id);
420void mt76_connac_txp_skb_unmap(struct mt76_dev *dev,
421			       struct mt76_txwi_cache *txwi);
422void mt76_connac_tx_complete_skb(struct mt76_dev *mdev,
423				 struct mt76_queue_entry *e);
424void mt76_connac_pm_queue_skb(struct ieee80211_hw *hw,
425			      struct mt76_connac_pm *pm,
426			      struct mt76_wcid *wcid,
427			      struct sk_buff *skb);
428void mt76_connac_pm_dequeue_skbs(struct mt76_phy *phy,
429				 struct mt76_connac_pm *pm);
430void mt76_connac2_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi,
431				 struct sk_buff *skb, struct mt76_wcid *wcid,
432				 struct ieee80211_key_conf *key, int pid,
433				 enum mt76_txq_id qid, u32 changed);
434u16 mt76_connac2_mac_tx_rate_val(struct mt76_phy *mphy,
435				 struct ieee80211_bss_conf *conf,
436				 bool beacon, bool mcast);
437bool mt76_connac2_mac_fill_txs(struct mt76_dev *dev, struct mt76_wcid *wcid,
438			       __le32 *txs_data);
439bool mt76_connac2_mac_add_txs_skb(struct mt76_dev *dev, struct mt76_wcid *wcid,
440				  int pid, __le32 *txs_data);
441void mt76_connac2_mac_decode_he_radiotap(struct mt76_dev *dev,
442					 struct sk_buff *skb,
443					 __le32 *rxv, u32 mode);
444int mt76_connac2_reverse_frag0_hdr_trans(struct ieee80211_vif *vif,
445					 struct sk_buff *skb, u16 hdr_offset);
446int mt76_connac2_mac_fill_rx_rate(struct mt76_dev *dev,
447				  struct mt76_rx_status *status,
448				  struct ieee80211_supported_band *sband,
449				  __le32 *rxv, u8 *mode);
450void mt76_connac2_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi);
451void mt76_connac2_txwi_free(struct mt76_dev *dev, struct mt76_txwi_cache *t,
452			    struct ieee80211_sta *sta,
453			    struct list_head *free_list);
454void mt76_connac2_tx_token_put(struct mt76_dev *dev);
455
456/* connac3 */
457void mt76_connac3_mac_decode_he_radiotap(struct sk_buff *skb, __le32 *rxv,
458					 u8 mode);
459void mt76_connac3_mac_decode_eht_radiotap(struct sk_buff *skb, __le32 *rxv,
460					  u8 mode);
461#endif /* __MT76_CONNAC_H */