sdio.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * NXP Wireless LAN device driver: SDIO specific definitions
  4 *
  5 * Copyright 2011-2020 NXP
  6 */
  7
  8#ifndef	_MWIFIEX_SDIO_H
  9#define	_MWIFIEX_SDIO_H
 10
 11
 12#include <linux/completion.h>
 13#include <linux/mmc/sdio.h>
 14#include <linux/mmc/sdio_ids.h>
 15#include <linux/mmc/sdio_func.h>
 16#include <linux/mmc/card.h>
 17#include <linux/mmc/host.h>
 18
 19#include "main.h"
 20
 21#define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
 22#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
 23#define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
 24#define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
 25#define SD8887_DEFAULT_FW_NAME "mrvl/sd8887_uapsta.bin"
 26#define SD8801_DEFAULT_FW_NAME "mrvl/sd8801_uapsta.bin"
 27#define SD8977_DEFAULT_FW_NAME "mrvl/sdsd8977_combo_v2.bin"
 28#define SD8978_SDIOUART_FW_NAME "mrvl/sdiouartiw416_combo_v0.bin"
 29#define SD8987_DEFAULT_FW_NAME "mrvl/sd8987_uapsta.bin"
 30#define SD8997_DEFAULT_FW_NAME "mrvl/sdsd8997_combo_v4.bin"
 31#define SD8997_SDIOUART_FW_NAME "mrvl/sdiouart8997_combo_v4.bin"
 32
 33#define BLOCK_MODE	1
 34#define BYTE_MODE	0
 35
 36#define MWIFIEX_SDIO_IO_PORT_MASK		0xfffff
 37
 38#define MWIFIEX_SDIO_BYTE_MODE_MASK	0x80000000
 39
 40#define MWIFIEX_MAX_FUNC2_REG_NUM	13
 41#define MWIFIEX_SDIO_SCRATCH_SIZE	10
 42
 43#define SDIO_MPA_ADDR_BASE		0x1000
 44#define CTRL_PORT			0
 45#define CTRL_PORT_MASK			0x0001
 46
 47#define CMD_PORT_UPLD_INT_MASK		(0x1U<<6)
 48#define CMD_PORT_DNLD_INT_MASK		(0x1U<<7)
 49#define HOST_TERM_CMD53			(0x1U << 2)
 50#define REG_PORT			0
 51#define MEM_PORT			0x10000
 52
 53#define CMD53_NEW_MODE			(0x1U << 0)
 54#define CMD_PORT_RD_LEN_EN		(0x1U << 2)
 55#define CMD_PORT_AUTO_EN		(0x1U << 0)
 56#define CMD_PORT_SLCT			0x8000
 57#define UP_LD_CMD_PORT_HOST_INT_STATUS	(0x40U)
 58#define DN_LD_CMD_PORT_HOST_INT_STATUS	(0x80U)
 59
 60#define MWIFIEX_MP_AGGR_BUF_SIZE_16K	(16384)
 61#define MWIFIEX_MP_AGGR_BUF_SIZE_32K	(32768)
 62/* we leave one block of 256 bytes for DMA alignment*/
 63#define MWIFIEX_MP_AGGR_BUF_SIZE_MAX    (65280)
 64
 65/* Misc. Config Register : Auto Re-enable interrupts */
 66#define AUTO_RE_ENABLE_INT              BIT(4)
 67
 68/* Host Control Registers : Configuration */
 69#define CONFIGURATION_REG		0x00
 70/* Host Control Registers : Host power up */
 71#define HOST_POWER_UP			(0x1U << 1)
 72
 73/* Host Control Registers : Upload host interrupt mask */
 74#define UP_LD_HOST_INT_MASK		(0x1U)
 75/* Host Control Registers : Download host interrupt mask */
 76#define DN_LD_HOST_INT_MASK		(0x2U)
 77
 78/* Host Control Registers : Upload host interrupt status */
 79#define UP_LD_HOST_INT_STATUS		(0x1U)
 80/* Host Control Registers : Download host interrupt status */
 81#define DN_LD_HOST_INT_STATUS		(0x2U)
 82
 83/* Host Control Registers : Host interrupt status */
 84#define CARD_INT_STATUS_REG		0x28
 85
 86/* Card Control Registers : Card I/O ready */
 87#define CARD_IO_READY                   (0x1U << 3)
 88/* Card Control Registers : Download card ready */
 89#define DN_LD_CARD_RDY                  (0x1U << 0)
 90
 91/* Max retry number of CMD53 write */
 92#define MAX_WRITE_IOMEM_RETRY		2
 93
 94/* SDIO Tx aggregation in progress ? */
 95#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
 96
 97/* SDIO Tx aggregation buffer room for next packet ? */
 98#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len)	\
 99						<= a->mpa_tx.buf_size)
100
101/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
102#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do {		\
103	memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len],			\
104			payload, pkt_len);				\
105	a->mpa_tx.buf_len += pkt_len;					\
106	if (!a->mpa_tx.pkt_cnt)						\
107		a->mpa_tx.start_port = port;				\
108	if (a->mpa_tx.start_port <= port)				\
109		a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt));		\
110	else								\
111		a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+		\
112						(a->max_ports -	\
113						a->mp_end_port)));	\
114	a->mpa_tx.pkt_cnt++;						\
115} while (0)
116
117/* SDIO Tx aggregation limit ? */
118#define MP_TX_AGGR_PKT_LIMIT_REACHED(a)					\
119			(a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
120
121/* Reset SDIO Tx aggregation buffer parameters */
122#define MP_TX_AGGR_BUF_RESET(a) do {					\
123	a->mpa_tx.pkt_cnt = 0;						\
124	a->mpa_tx.buf_len = 0;						\
125	a->mpa_tx.ports = 0;						\
126	a->mpa_tx.start_port = 0;					\
127} while (0)
128
129/* SDIO Rx aggregation limit ? */
130#define MP_RX_AGGR_PKT_LIMIT_REACHED(a)					\
131			(a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
132
133/* SDIO Rx aggregation in progress ? */
134#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
135
136/* SDIO Rx aggregation buffer room for next packet ? */
137#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len)				\
138			((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
139
140/* Reset SDIO Rx aggregation buffer parameters */
141#define MP_RX_AGGR_BUF_RESET(a) do {					\
142	a->mpa_rx.pkt_cnt = 0;						\
143	a->mpa_rx.buf_len = 0;						\
144	a->mpa_rx.ports = 0;						\
145	a->mpa_rx.start_port = 0;					\
146} while (0)
147
148/* data structure for SDIO MPA TX */
149struct mwifiex_sdio_mpa_tx {
150	/* multiport tx aggregation buffer pointer */
151	u8 *buf;
152	u32 buf_len;
153	u32 pkt_cnt;
154	u32 ports;
155	u16 start_port;
156	u8 enabled;
157	u32 buf_size;
158	u32 pkt_aggr_limit;
159};
160
161struct mwifiex_sdio_mpa_rx {
162	u8 *buf;
163	u32 buf_len;
164	u32 pkt_cnt;
165	u32 ports;
166	u16 start_port;
167	u32 *len_arr;
168	u8 enabled;
169	u32 buf_size;
170	u32 pkt_aggr_limit;
171};
172
173int mwifiex_bus_register(void);
174void mwifiex_bus_unregister(void);
175
176struct mwifiex_sdio_card_reg {
177	u8 start_rd_port;
178	u8 start_wr_port;
179	u8 base_0_reg;
180	u8 base_1_reg;
181	u8 poll_reg;
182	u8 host_int_enable;
183	u8 host_int_rsr_reg;
184	u8 host_int_status_reg;
185	u8 host_int_mask_reg;
186	u8 host_strap_reg;
187	u8 host_strap_mask;
188	u8 host_strap_value;
189	u8 status_reg_0;
190	u8 status_reg_1;
191	u8 sdio_int_mask;
192	u32 data_port_mask;
193	u8 io_port_0_reg;
194	u8 io_port_1_reg;
195	u8 io_port_2_reg;
196	u8 max_mp_regs;
197	u8 rd_bitmap_l;
198	u8 rd_bitmap_u;
199	u8 rd_bitmap_1l;
200	u8 rd_bitmap_1u;
201	u8 wr_bitmap_l;
202	u8 wr_bitmap_u;
203	u8 wr_bitmap_1l;
204	u8 wr_bitmap_1u;
205	u8 rd_len_p0_l;
206	u8 rd_len_p0_u;
207	u8 card_misc_cfg_reg;
208	u8 card_cfg_2_1_reg;
209	u8 cmd_rd_len_0;
210	u8 cmd_rd_len_1;
211	u8 cmd_rd_len_2;
212	u8 cmd_rd_len_3;
213	u8 cmd_cfg_0;
214	u8 cmd_cfg_1;
215	u8 cmd_cfg_2;
216	u8 cmd_cfg_3;
217	u8 fw_dump_host_ready;
218	u8 fw_dump_ctrl;
219	u8 fw_dump_start;
220	u8 fw_dump_end;
221	u8 func1_dump_reg_start;
222	u8 func1_dump_reg_end;
223	u8 func1_scratch_reg;
224	u8 func1_spec_reg_num;
225	u8 func1_spec_reg_table[MWIFIEX_MAX_FUNC2_REG_NUM];
226};
227
228struct sdio_mmc_card {
229	struct sdio_func *func;
230	struct mwifiex_adapter *adapter;
231
232	struct completion fw_done;
233	const char *firmware;
234	const char *firmware_sdiouart;
235	const struct mwifiex_sdio_card_reg *reg;
236	u8 max_ports;
237	u8 mp_agg_pkt_limit;
238	u16 tx_buf_size;
239	u32 mp_tx_agg_buf_size;
240	u32 mp_rx_agg_buf_size;
241
242	u32 mp_rd_bitmap;
243	u32 mp_wr_bitmap;
244
245	u16 mp_end_port;
246	u32 mp_data_port_mask;
247
248	u8 curr_rd_port;
249	u8 curr_wr_port;
250
251	u8 *mp_regs;
252	bool supports_sdio_new_mode;
253	bool has_control_mask;
254	bool can_dump_fw;
255	bool fw_dump_enh;
256	bool can_auto_tdls;
257	bool can_ext_scan;
258	bool fw_ready_extra_delay;
259	bool host_mlme;
260
261	struct mwifiex_sdio_mpa_tx mpa_tx;
262	struct mwifiex_sdio_mpa_rx mpa_rx;
263
264	struct work_struct work;
265	unsigned long work_flags;
266};
267
268struct mwifiex_sdio_device {
269	const char *firmware;
270	const char *firmware_sdiouart;
271	const struct mwifiex_sdio_card_reg *reg;
272	u8 max_ports;
273	u8 mp_agg_pkt_limit;
274	u16 tx_buf_size;
275	u32 mp_tx_agg_buf_size;
276	u32 mp_rx_agg_buf_size;
277	bool supports_sdio_new_mode;
278	bool has_control_mask;
279	bool can_dump_fw;
280	bool fw_dump_enh;
281	bool can_auto_tdls;
282	bool can_ext_scan;
283	bool fw_ready_extra_delay;
284	bool host_mlme;
285};
286
287/*
288 * .cmdrsp_complete handler
289 */
290static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
291					       struct sk_buff *skb)
292{
293	dev_kfree_skb_any(skb);
294	return 0;
295}
296
297/*
298 * .event_complete handler
299 */
300static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
301					      struct sk_buff *skb)
302{
303	dev_kfree_skb_any(skb);
304	return 0;
305}
306
307static inline bool
308mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
309{
310	u8 tmp;
311
312	if (card->curr_rd_port < card->mpa_rx.start_port) {
313		if (card->supports_sdio_new_mode)
314			tmp = card->mp_end_port >> 1;
315		else
316			tmp = card->mp_agg_pkt_limit;
317
318		if (((card->max_ports - card->mpa_rx.start_port) +
319		    card->curr_rd_port) >= tmp)
320			return true;
321	}
322
323	if (!card->supports_sdio_new_mode)
324		return false;
325
326	if ((card->curr_rd_port - card->mpa_rx.start_port) >=
327	    (card->mp_end_port >> 1))
328		return true;
329
330	return false;
331}
332
333static inline bool
334mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
335{
336	u16 tmp;
337
338	if (card->curr_wr_port < card->mpa_tx.start_port) {
339		if (card->supports_sdio_new_mode)
340			tmp = card->mp_end_port >> 1;
341		else
342			tmp = card->mp_agg_pkt_limit;
343
344		if (((card->max_ports - card->mpa_tx.start_port) +
345		    card->curr_wr_port) >= tmp)
346			return true;
347	}
348
349	if (!card->supports_sdio_new_mode)
350		return false;
351
352	if ((card->curr_wr_port - card->mpa_tx.start_port) >=
353	    (card->mp_end_port >> 1))
354		return true;
355
356	return false;
357}
358
359/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
360static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
361				    u16 rx_len, u8 port)
362{
363	card->mpa_rx.buf_len += rx_len;
364
365	if (!card->mpa_rx.pkt_cnt)
366		card->mpa_rx.start_port = port;
367
368	if (card->supports_sdio_new_mode) {
369		card->mpa_rx.ports |= (1 << port);
370	} else {
371		if (card->mpa_rx.start_port <= port)
372			card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt);
373		else
374			card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1);
375	}
376	card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = rx_len;
377	card->mpa_rx.pkt_cnt++;
378}
379#endif /* _MWIFIEX_SDIO_H */