iwl-context-info.h

  1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
  2/*
  3 * Copyright (C) 2017 Intel Deutschland GmbH
  4 * Copyright (C) 2018-2020, 2022, 2024-2025 Intel Corporation
  5 */
  6#ifndef __iwl_context_info_file_h__
  7#define __iwl_context_info_file_h__
  8
  9/* maximum number of DRAM map entries supported by FW */
 10#define IWL_MAX_DRAM_ENTRY	64
 11#define CSR_CTXT_INFO_BA	0x40
 12
 13/**
 14 * enum iwl_context_info_flags - Context information control flags
 15 * @IWL_CTXT_INFO_AUTO_FUNC_INIT: If set, FW will not wait before interrupting
 16 *	the init done for driver command that configures several system modes
 17 * @IWL_CTXT_INFO_EARLY_DEBUG: enable early debug
 18 * @IWL_CTXT_INFO_ENABLE_CDMP: enable core dump
 19 * @IWL_CTXT_INFO_RB_CB_SIZE: mask of the RBD Cyclic Buffer Size
 20 *	exponent, the actual size is 2**value, valid sizes are 8-2048.
 21 *	The value is four bits long. Maximum valid exponent is 12
 22 * @IWL_CTXT_INFO_TFD_FORMAT_LONG: use long TFD Format (the
 23 *	default is short format - not supported by the driver)
 24 * @IWL_CTXT_INFO_RB_SIZE: RB size mask
 25 *	(values are IWL_CTXT_INFO_RB_SIZE_*K)
 26 * @IWL_CTXT_INFO_RB_SIZE_1K: Value for 1K RB size
 27 * @IWL_CTXT_INFO_RB_SIZE_2K: Value for 2K RB size
 28 * @IWL_CTXT_INFO_RB_SIZE_4K: Value for 4K RB size
 29 * @IWL_CTXT_INFO_RB_SIZE_8K: Value for 8K RB size
 30 * @IWL_CTXT_INFO_RB_SIZE_12K: Value for 12K RB size
 31 * @IWL_CTXT_INFO_RB_SIZE_16K: Value for 16K RB size
 32 * @IWL_CTXT_INFO_RB_SIZE_20K: Value for 20K RB size
 33 * @IWL_CTXT_INFO_RB_SIZE_24K: Value for 24K RB size
 34 * @IWL_CTXT_INFO_RB_SIZE_28K: Value for 28K RB size
 35 * @IWL_CTXT_INFO_RB_SIZE_32K: Value for 32K RB size
 36 */
 37enum iwl_context_info_flags {
 38	IWL_CTXT_INFO_AUTO_FUNC_INIT	= 0x0001,
 39	IWL_CTXT_INFO_EARLY_DEBUG	= 0x0002,
 40	IWL_CTXT_INFO_ENABLE_CDMP	= 0x0004,
 41	IWL_CTXT_INFO_RB_CB_SIZE	= 0x00f0,
 42	IWL_CTXT_INFO_TFD_FORMAT_LONG	= 0x0100,
 43	IWL_CTXT_INFO_RB_SIZE		= 0x1e00,
 44	IWL_CTXT_INFO_RB_SIZE_1K	= 0x1,
 45	IWL_CTXT_INFO_RB_SIZE_2K	= 0x2,
 46	IWL_CTXT_INFO_RB_SIZE_4K	= 0x4,
 47	IWL_CTXT_INFO_RB_SIZE_8K	= 0x8,
 48	IWL_CTXT_INFO_RB_SIZE_12K	= 0x9,
 49	IWL_CTXT_INFO_RB_SIZE_16K	= 0xa,
 50	IWL_CTXT_INFO_RB_SIZE_20K	= 0xb,
 51	IWL_CTXT_INFO_RB_SIZE_24K	= 0xc,
 52	IWL_CTXT_INFO_RB_SIZE_28K	= 0xd,
 53	IWL_CTXT_INFO_RB_SIZE_32K	= 0xe,
 54};
 55
 56/**
 57 * struct iwl_context_info_version - version structure
 58 * @mac_id: SKU and revision id
 59 * @version: context information version id
 60 * @size: the size of the context information in DWs
 61 * @reserved: (reserved)
 62 */
 63struct iwl_context_info_version {
 64	__le16 mac_id;
 65	__le16 version;
 66	__le16 size;
 67	__le16 reserved;
 68} __packed;
 69
 70/**
 71 * struct iwl_context_info_control - version structure
 72 * @control_flags: context information flags see &enum iwl_context_info_flags
 73 * @reserved: (reserved)
 74 */
 75struct iwl_context_info_control {
 76	__le32 control_flags;
 77	__le32 reserved;
 78} __packed;
 79
 80/**
 81 * struct iwl_context_info_dram_nonfseq - images DRAM map
 82 * each entry in the map represents a DRAM chunk of up to 32 KB
 83 * @umac_img: UMAC image DRAM map
 84 * @lmac_img: LMAC image DRAM map
 85 * @virtual_img: paged image DRAM map
 86 */
 87struct iwl_context_info_dram_nonfseq {
 88	__le64 umac_img[IWL_MAX_DRAM_ENTRY];
 89	__le64 lmac_img[IWL_MAX_DRAM_ENTRY];
 90	__le64 virtual_img[IWL_MAX_DRAM_ENTRY];
 91} __packed;
 92
 93/**
 94 * struct iwl_context_info_rbd_cfg - RBDs configuration
 95 * @free_rbd_addr: default queue free RB CB base address
 96 * @used_rbd_addr: default queue used RB CB base address
 97 * @status_wr_ptr: default queue used RB status write pointer
 98 */
 99struct iwl_context_info_rbd_cfg {
100	__le64 free_rbd_addr;
101	__le64 used_rbd_addr;
102	__le64 status_wr_ptr;
103} __packed;
104
105/**
106 * struct iwl_context_info_hcmd_cfg  - command queue configuration
107 * @cmd_queue_addr: address of command queue
108 * @cmd_queue_size: number of entries
109 * @reserved: (reserved)
110 */
111struct iwl_context_info_hcmd_cfg {
112	__le64 cmd_queue_addr;
113	u8 cmd_queue_size;
114	u8 reserved[7];
115} __packed;
116
117/**
118 * struct iwl_context_info_dump_cfg - Core Dump configuration
119 * @core_dump_addr: core dump (debug DRAM address) start address
120 * @core_dump_size: size, in DWs
121 * @reserved: (reserved)
122 */
123struct iwl_context_info_dump_cfg {
124	__le64 core_dump_addr;
125	__le32 core_dump_size;
126	__le32 reserved;
127} __packed;
128
129/**
130 * struct iwl_context_info_pnvm_cfg - platform NVM data configuration
131 * @platform_nvm_addr: Platform NVM data start address
132 * @platform_nvm_size: size in DWs
133 * @reserved: (reserved)
134 */
135struct iwl_context_info_pnvm_cfg {
136	__le64 platform_nvm_addr;
137	__le32 platform_nvm_size;
138	__le32 reserved;
139} __packed;
140
141/**
142 * struct iwl_context_info_early_dbg_cfg - early debug configuration for
143 *	dumping DRAM addresses
144 * @early_debug_addr: early debug start address
145 * @early_debug_size: size in DWs
146 * @reserved: (reserved)
147 */
148struct iwl_context_info_early_dbg_cfg {
149	__le64 early_debug_addr;
150	__le32 early_debug_size;
151	__le32 reserved;
152} __packed;
153
154/**
155 * struct iwl_context_info - device INIT configuration
156 * @version: version information of context info and HW
157 * @control: control flags of FH configurations
158 * @reserved0: (reserved)
159 * @rbd_cfg: default RX queue configuration
160 * @hcmd_cfg: command queue configuration
161 * @reserved1: (reserved)
162 * @dump_cfg: core dump data
163 * @edbg_cfg: early debug configuration
164 * @pnvm_cfg: platform nvm configuration
165 * @reserved2: (reserved)
166 * @dram: firmware image addresses in DRAM
167 * @reserved3: (reserved)
168 */
169struct iwl_context_info {
170	struct iwl_context_info_version version;
171	struct iwl_context_info_control control;
172	__le64 reserved0;
173	struct iwl_context_info_rbd_cfg rbd_cfg;
174	struct iwl_context_info_hcmd_cfg hcmd_cfg;
175	__le32 reserved1[4];
176	struct iwl_context_info_dump_cfg dump_cfg;
177	struct iwl_context_info_early_dbg_cfg edbg_cfg;
178	struct iwl_context_info_pnvm_cfg pnvm_cfg;
179	__le32 reserved2[16];
180	struct iwl_context_info_dram_nonfseq dram;
181	__le32 reserved3[16];
182} __packed; /* BOOT_LOADER_CONTEXT_INFO_S */
183
184int iwl_pcie_ctxt_info_init(struct iwl_trans *trans, const struct fw_img *img);
185void iwl_pcie_ctxt_info_free(struct iwl_trans *trans);
186void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans);
187int iwl_pcie_init_fw_sec(struct iwl_trans *trans,
188			 const struct fw_img *fw,
189			 struct iwl_context_info_dram_nonfseq *ctxt_dram);
190void *iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans,
191					    size_t size,
192					    dma_addr_t *phys);
193int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans,
194				 const void *data, u32 len,
195				 struct iwl_dram_data *dram);
196
197#endif /* __iwl_context_info_file_h__ */